93LCS56T-I/ST [MICROCHIP]
2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect; 2K / 4K 2.5V Microwire串行EEPROM与软件写保护型号: | 93LCS56T-I/ST |
厂家: | MICROCHIP |
描述: | 2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect |
文件: | 总14页 (文件大小:183K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Obsolete Device
93LCS56/66
®
2K/4K 2.5V Microwire Serial EEPROM with Software Write Protect
FEATURES
BLOCK DIAGRAM
• Single supply with programming operation down
to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 5 µA standby current (typical) at 3.0V
• x16 memory organization
V
CC
VSS
ADDRESS
DECODER
MEMORY
ARRAY
- 128x16 (93LCS56)
- 256x16 (93LCS66)
• Software write protection of user defined memory
space
ADDRESS
COUNTER
OUTPUT
BUFFER
• Self timed erase and write cycles
• Automatic ERAL before WRAL
• Power on/off data protection
• Industry standard 3-wire serial I/O
• Device status signal during E/W
• Sequential READ function
DATA REGISTER
DO
DI
MODE
DECODE
LOGIC
PRE
PE
CS
CLOCK
CLK
GENERATOR
• 1,000,000 E/W cycles guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC and 14-pin SOIC packages
DESCRIPTION
The Microchip Technology Inc. 93LCS56/66 are low volt-
age Serial Electrically Erasable PROMs with memory
capacities of 2K bits/4K bits respectively. A write protect
register is included in order to provide a user defined
region of write protected memory. All memory locations
greater than or equal to the address placed in the write
protect register will be protected from any attempted write
or erase operation. It is also possible to protect the
address in the write protect register permanently by using
a one time only instruction (PRDS). Any attempt to alter
data in a register whose address is equal to or greater
than the address stored in the protect register will be
aborted. Advanced CMOS technology makes this device
ideal for low power non-volatile memory applications.
• Temperature ranges supported
- Commercial (C):
- Industrial (I):
0°C to +70°C
-40°C to +85°C
PACKAGE TYPES
SOIC
1
2
3
4
5
6
7
14
13
12
11
10
9
NC
CS
CLK
NC
DI
NC
VCC
PRE
NC
DIP
SOIC
1
2
3
4
8
7
6
5
VCC
PRE
PE
CS
CLK
DI
1
8
CS
VCC
2
7
CLK
PRE
PE
3
6
DI
PE
DO
NC
VSS
NC
4
5
VSS
DO
8
DO
VSS
93LCS56
93LCS66
93LCS56
93LCS66
93LCS56
93LCS66
Microwire is a registered trademark of National Semiconductor Incorporated.
2004 Microchip Technology Inc.
DS11181E-page 1
93LCS56/66
TABLE 1-1:
Name
PIN FUNCTION TABLE
Function
1.0
ELECTRICAL CHARACTERISTICS
1.1
Maximum Ratings*
CS
CLK
DI
Chip Select
VCC...................................................................................7.0V
All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) .............+300°C
ESD protection on all pins................................................4 kV
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
DO
VSS
PE
Program Enable
Protect Register Enable
Power Supply
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
PRE
VCC
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = +2.5V to +6.0V
Commercial(C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Parameter
Symbol
Min
Max
Units
Conditions
High level input voltage
Low level input voltage
Low level output voltage
VIH
VIL
2.0
-0.3
—
VCC +1
0.8
0.4
0.2
—
V
V
VCC ≥ 2.5V
VCC ≥ 2.5V
VOL1
VOL2
VOH1
VOH2
ILI
V
IOL = 2.1 mA; VCC = 4.5V
IOL = 100 µA; VCC = 2.5V
IOH = -400µA; VCC = 4.5V
IOH = -100µA; VCC = 2.5V
VIN = 0.1V to VCC
—
V
High level output voltage
2.4
V
VCC-0.2
-10
—
V
Input leakage current
Output leakage current
10
µA
µA
pF
ILO
-10
10
VOUT = 0.1V to Vcc
Pin capacitance
(all inputs/outputs)
CIN, COUT
—
7
VIN/VOUT = 0V (Note 1 & 2)
Tamb = +25°C; FCLK = 1 MHz
Operating current
ICC Write
ICC Read
—
—
3
mA
FCLK = 2 MHz; VCC = 3.0V (Note 2)
1
500
mA
µA
FCLK = 2 MHz; VCC = 6.0V
FCLK = 1 MHz; VCC = 3.0V
Standby current
Clock frequency
ICCS
—
—
100
30
µA
µA
CLK = CS = 0V; VCC = 6.0V
CLK = CS = 0V; VCC = 3.0V
DI = PE = PRE = VSS
FCLK
2
1
MHz
MHz
VCC ≥ 4.5V
VCC < 4.5V
Clock high time
TCKH
TCKL
TCSS
TCSH
TCSL
TPRES
TPES
TPREH
TPEH
TDIS
250
250
50
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
PRE setup time
—
Relative to CLK
Relative to CLK
0
—
250
100
100
0
—
—
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
Relative to CLK
CL=100 pF
PE setup time
—
PRE hold time
—
PE hold time
500
100
100
—
—
Data input setup time
Data input hold time
Data output delay time
Data output disable time
—
TDIH
TPD
—
400
100
TCZ
—
CL=100 pF (Note 2)
Note 1: This parameter is tested at Tamb = 25°C and FCLK = 1 MHz.
2: This parameter is periodically sampled and not 100% tested.
DS11181E-page 2
2004 Microchip Technology Inc.
93LCS56/66
(Continued)
TABLE 1-2:
DC AND AC ELECTRICAL CHARACTERISTICS
VCC = +2.5V to +6.0V
Commercial(C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
Parameter
Symbol
Min
Max
Units
Conditions
Status valid time
TSV
TWC
TEC
TWL
—
500
10
15
30
—
ns
ms
CL=100 pF
Program cycle time
ERASE/WRITE mode (Note 3)
ERAL mode
ms
ms
WRAL mode
Endurance
1M
cycles
25°C, Vcc = 5.0V, Block Mode
(Note 4)
3: Typical program cycle time is 4 ms per word.
4: This parameter is not tested but guaranteed by characterization. For endurance estimates in a specific appli-
cation, please consult the Total Endurance Model which can be obtained on our BBS or website.
TABLE 1-3:
INSTRUCTION SET FOR 93LCS56*/66
93LCS56/66 (x 16 organization)
Data In Data Out PRE PE
Instruction SB Opcode
Address
Comments
READ
EWEN
ERASE
1
1
1
10
00
11
A7 - A0
—
—
—
D15-D0
0
X
1
1
Reads data stored in memory, start-
ing at specified address (.Note).
11XXXXXX
A7 - A0
High-Z
0
Erase/Write Enable must precede all
programming modes.
(RDY/
BSY)
Erase data at specified address
location if address is unprotected
(Note).
ERAL
1
1
1
1
1
1
00
01
00
00
10
00
10XXXXXX
A7 - A0*
—
(RDY/
BSY)
0
0
0
0
1
1
1
1
1
X
X
1
Erase all registers to “FF”. Valid only
when Protect Register is cleared.
WRITE
WRAL
EWDS
PRREAD
PREN
D15 - D0
(RDY/
BSY)
Writes register if address is unpro-
tected.
01XXXXXX D15 - D0
(RDY/
BSY)
Writes all registers. Valid only when
Protect Register is cleared.
00XXXXXX
XXXXXXXX
11XXXXXX
—
—
—
High-Z
A7-A0
High-Z
Erase/Write Disable deactivates all
programming instructions.
Reads address stored in Protect
Register.
Must immediately precede
PRCLEAR, PRWRITE and PRDS
instructions.
PRCLEAR
PRWRITE
1
1
11
01
11111111
A7 - A0*
—
—
(RDY/
BSY)
1
1
1
1
Clears the Protect Register such that
all data are NOT write-protected.
(RDY/
BSY)
Programs address into Protect Reg-
ister. Thereafter, memory addresses
greater than or equal to the address
in Protect Register are write-pro-
tected.
PRDS
1
00
00000000
—
(RDY/
BSY)
1
1
ONE TIME ONLY instruction after
which the address in the Protect
Register cannot be altered.
Note:
Address A7 bit is a “don’t care” on 93LCS56.
2004 Microchip Technology Inc.
DS11181E-page 3
93LCS56/66
2.4
READ
2.0
FUNCTIONAL DESCRIPTION
The 93LCS56/66 is organized as 128/256 registers by
16 bits. Instructions, addresses and write data are
clocked into the DI pin on the rising edge of the clock
(CLK). The DO pin is normally held in a high-Z state
except when reading data from the device, or when
checking the ready/busy status during a programming
operation. The ready/busy status can be verified during
an Erase/Write operation by polling the DO pin; DO low
indicates that programming is still in progress, while
DO high indicates the device is ready. The DO will enter
the high-Z state on the falling edge of the CS.
The READ instruction outputs the serial data of the
addressed memory location on the DO pin. A dummy
zero bit precedes the 16 bit output string. The output
data bits will toggle on the rising edge of the CLK and
are stable after the specified time delay (TPD). Sequen-
tial read is possible when CS is held high. The memory
data will automatically cycle to the next register and
output sequentially.
2.5
Erase/Write Enable and Disable
(EWEN, EWDS)
2.1
START Condition
The 93LCS56/66 powers up in the Erase/Write Disable
(EWDS) state. All programming modes must be pre-
ceded by an Erase/Write Enable (EWEN) instruction.
The PE pin MUST be held “high” while loading the
EWEN instruction. Once the EWEN instruction is exe-
cuted, programming remains enabled until an EWDS
instruction is executed or VCC is removed from the
device. To protect against accidental data disturb, the
EWDS instruction can be used to disable all Erase/
Write functions and should follow all programming
operations. Execution of a READ instruction is inde-
pendent of both the EWEN and EWDS instructions.
The START bit is detected by the device if CS and DI
are both HIGH with respect to the positive edge of CLK
for the first time.
Before a START condition is detected, CS, CLK, and DI
may change in any combination (except to that of a
START condition), without resulting in any device oper-
ation (READ, WRITE, ERASE, EWEN, EWDS, ERAL,
WRAL, PRREAD, PREN, PRCLEAR, PRWRITE, and
PRDS). As soon as CS is HIGH, the device is no longer
in the standby mode.
An instruction following a START condition will only be
executed if the required amount of opcode, address
and data bits for any particular instruction is clocked in.
2.6
ERASE
The ERASE instruction forces all data bits of the spec-
ified address to the logical “1” state. CS is brought low
following the loading of the last address bit. This falling
edge of the CS pin initiates the self-timed programming
cycle. The PE pin MUST be latched “high” during load-
ing the ERASE instruction but becomes a “don't care”
after loading the instruction.
After execution of an instruction (i.e., clock in or out of
the last required address or data bit) CLK and DI
become don't care bits until a new start condition is
detected.
2.2
DI/DO
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCLS). DO at logical “0” indicates that program-
ming is still in progress. DO at logical “1” indicates that
the register at the specified address has been erased
and the device is ready for another instruction. ERASE
instruction is valid if specified address is unprotected.
It is possible to connect the Data In and Data Out pins
together. However, with this configuration it is possible
for a “bus conflict” to occur during the “dummy zero”
that precedes the READ operation, if A0 is a logic
HIGH level. Under such a condition the voltage level
seen at Data Out is undefined and will depend upon the
relative impedances of Data Out and the signal source
driving A0. The higher the current sourcing capability of
A0, the higher the voltage at the Data Out pin.
The ERASE cycle takes 4 ms per word typical.
2.7
WRITE
2.3
Data Protection
The WRITE instruction is followed by 16 bits of data
which are written into the specified address. After the
last data bit is put on the DI pin, CS must be brought
low before the next rising edge of the CLK clock. Both
CS and CLK must be low to initiate the self-timed auto-
erase and programming cycle. The PE pin MUST be
latched “high” while loading the WRITE instruction but
becomes a “don't care” thereafter.
During power-up, all programming modes of operation
are inhibited until VCC has reached a level greater than
1.4V. During power-down, the source data protection
circuitry acts to inhibit all programming modes when
VCC has fallen below 1.4V.
The EWEN and EWDS commands give additional pro-
tection against accidentally programming during nor-
mal operation.
After power-up, the device is automatically in the
EWDS mode. Therefore, an EWEN instruction must be
performed before any ERASE or WRITE instruction
can be executed.
DS11181E-page 4
2004 Microchip Technology Inc.
93LCS56/66
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
(TCSL) and before the entire write cycle is complete. DO
at logical “0” indicates that programming is still in
progress. DO at logical “1” indicates that the register at
the specified address has been written with the data
specified and the device is ready for another instruc-
tion. WRITE instruction is valid only if specified address
is unprotected.
2.10
Protect Register Read (PRREAD)
The Protect Register Read (PRREAD) instruction out-
puts the address stored in the Protect Register on the
DO pin. The PRE pin MUST be held HIGH when load-
ing the instruction and remains HIGH until CS goes
LOW. A dummy zero bit precedes the 8-bit output
string. The output data bits in the memory Protect Reg-
ister will toggle on the rising edge of the CLK as in the
READ mode.
The WRITE cycle takes 4 ms per word typical.
2.11
Protect Register Enable (PREN)
2.8
Erase All (ERAL)
The Protect Register Enable (PREN) instruction is
used to enable the PRCLEAR, PRWRITE, and PRDS
modes. Before the PREN mode can be entered, the
device must be in the EWEN mode. Both PRE and PE
pins MUST be held “high” while loading the instruction.
The PREN instruction MUST immediately precede a
PRCLEAR, PRWRITE, or PRDS instruction.
The ERAL instruction will erase the entire memory
array to the logical “1”. The ERAL cycle is identical to
the ERASE cycle except for the different opcode. The
ERAL cycle is completely self-timed and commences
at the falling edge of the CS. PE pin MUST be held
“high” while loading the instruction but becomes “don't
care” thereafter. Clocking of the CLK pin is not neces-
sary after the device has entered the self clocking
mode. The ERAL instruction is guaranteed at VCC = 4.5
to 6V and valid only when Protect Register is cleared.
2.12
Protect Register Clear (PRCLEAR)
The Protect Register Clear (PRCLEAR) instruction
clears the address stored in the Protect Register and,
therefore, enables all registers for programming
instructions such as ERASE, ERAL, WRITE, and
WRAL. The PRE and PE pin MUST be held HIGH
when loading the instruction. Thereafter, PRE and PE
pins become “don't care”. A PREN instruction must
immediately precede a PRCLEAR instruction.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL) and before the entire write cycle is complete.
The ERAL cycle takes 15 ms maximum (8 ms typical).
2.9
Write All (WRAL)
The WRAL instruction will write the entire memory
array with the data specified in the command. The
WRAL cycle is completely self-timed and commences
at the falling edge of the CS. PE pin MUST be held
“high” while loading the instruction but becomes “don't
care” thereafter. Clocking of the CLK pin is not neces-
sary after the device has entered the self clocking
mode. The WRAL command does include an automatic
ERAL cycle for the device. Therefore, the WRAL
instruction does not require an ERAL instruction but the
chip must be in the EWEN status. The WRAL instruc-
tion is guaranteed at VCC = 4.5 to 6V and valid only
when Protect Register is cleared.
2.13
Protect Register Write (PRWRITE)
The Protect Register Write (PRWRITE) instruction
writes into the Protect Register the address of the first
register to be protected. After this instruction is exe-
cuted, all registers whose memory addresses are
greater than or equal to the address pointer specified in
the Protect register are protected from any program-
ming instructions. Note that a PREN instruction must
be executed before a PRWRITE instruction and, the
Protect Register must be cleared (by a PRCLEAR
instruction) before executing the PRWRITE instruction.
The PRE and PE pins MUST be held HIGH while load-
ing PRWRITE instruction. After the instruction is
loaded, they become “don't care”.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (TCSL).
2.14
Protect Register Disable (PRDS)
The WRAL cycle takes 30 ms maximum (16 ms typi-
cal).
The Protect Register Disable (PRDS) instruction is a
ONE TIME ONLY instruction to permanently set the
address specified in the Protect Register. Any attempts
to change the address pointer will be aborted. The PRE
and PE pins MUST be held HIGH while loading PRDS
instruction. After the instruction is loaded, they become
“don't care”. Note that a PREN instruction must be exe-
cuted before a PRDS instruction.
Note: In order to execute either READ, EWEN,
ERAL, WRITE, WRAL, or EWDS instruc-
tions, the Protect Register Enable (PRE)
pin must be held LOW.
2004 Microchip Technology Inc.
DS11181E-page 5
93LCS56/66
FIGURE 2-1: SYNCHRONOUS DATA TIMING
V
IH
PRE
V
IL
T
T
PRES
T
PREH
V
IH
PE
V
V
IL
T
PEH
PES
IH
CS
T
CSS
T
CKH
T
CKL
V
IL
T
CSH
V
IH
CLK
V
IL
T
DIH
T
DIS
V
IH
DI
V
IL
T
T
CZ
CZ
T
PD
T
PD
V
OH
DO
(READ)
V
V
OL
T
SV
OH
DO
(PROGRAM)
STATUS VALID
V
OL
FIGURE 2-2: READ TIMING
TCSL
CS
CLK
DI
1
1
0
A2
• • •
A0
TRI-STATE
DO
0
D15
• • •
D0
D15*
• • •
D0
D15*
• • •
PRE = 0
PE = X
* The memory automatically cycles to the next register.
Tri-State is a registered trademark of National Semiconductor.
FIGURE 2-3: EWEN TIMING
DS11181E-page 6
2004 Microchip Technology Inc.
93LCS56/66
FIGURE 2-4: EWDS TIMING
T
CSL
CS
CLK
DI
† † †
1
0
0
0
0
X
X
PRE = 0
PE = X
6 DON'T CARE BITS
DO = TRI-STATE
FIGURE 2-5: WRITE TIMING
PE
T
CSL
CS
CLK
† † †
† † †
1
0
1
A7
A0
D15
D0
DI
BUSY
TRI-STATE
READY
DO
† Address bit A7 becomes a "don't care" for 93LCS56.
PRE = 0
T
WC
FIGURE 2-6: WRAL TIMING
PE
TCSL
CS
CLK
1
0
0
0
1
X
• • •
X
D15
• • •
D0
DI
6 DON'T CARE BITS
TRI-STATE
BUSY
TRISTATE
READY
DO
Guaranteed at VCC = 4.5V to 6.0V
Protect Register must be cleared
PRE = 0
TWL
2004 Microchip Technology Inc.
DS11181E-page 7
93LCS56/66
FIGURE 2-7: ERASE TIMING
PE
CS
T
CSL
STANDBY
CHECK STATUS
CLK
DI
A7
1
1
1
† † †
A0
T
CZ
T
SV
TRI-STATE
TRI-STATE
DO
READY
BUSY
T
WC
† Address bit A7 is a "don't care" for 93LCS56.
PRE = 0
FIGURE 2-8: ERAL TIMING
PE
CS
T
CSL
STANDBY
CHECK STATUS
CLK
DI
1
0
0
1
0
† † †
X
X
T
CZ
T
SV
6 DON'T CARE BITS
TRI-STATE
TRI-STATE
READY
BUSY
DO
T
EC
Guarantee at V
CC = 4.5V to 6.0V
PRE = 0
Protect Register must be cleared
FIGURE 2-9: PRREAD TIMING
PRE
CS
T
CSL
CLK
X
† † †
X
1
1
0
DI
8 DON'T CARE BITS
PE = X
0
A7
A6
† † †
A0
DO
† X †
† Address bit A7 is a "don't care" for 93LCS56.
DS11181E-page 8
2004 Microchip Technology Inc.
93LCS56/66
FIGURE 2-10: PREN TIMING
PRE
PE
CS
T
CSL
CLK
1
0
0
1
1
X
† † †
X
DI
DO = TRI-STATE
6 DON'T CARE BITS
A EWEN cycle must precede a PREN cycle.
FIGURE 2-11: PRCLEAR TIMING
PRE
PE
CS
TCSL
CLK
1
1
1
1
• • •
1
1
1
1
DI
8 BITS OF "1"
TRI-STATE
READY
BUSY
DO
A PREN cycle must immediately precede a PRCLEAR cycle.
TWC
FIGURE 2-12: PRWRITE TIMING
PRE
PE
CS
T
CSL
CLK
1
0
1
A7
• • •
A0
DI
READY
BUSY
DO
T
WC
Protect Register MUST be cleared before a PRWRITE cycle.
A PREN cycle must immediately precede a PRWRITE cycle.
Address bit A7 is a "don't care" for 93LCS56.
2004 Microchip Technology Inc.
DS11181E-page 9
93LCS56/66
FIGURE 2-13: PRDS TIMING
PRE
PE
CS
TCSL
CLK
1
0
0
0
• • •
0
0
0
0
DI
8 BITS OF "0"
READY
BUSY
DO
TWC
ONE TIME ONLY instruction. A PREN cycle must immediately precede a PRDS cycle.
data bits before an instruction is executed (see instruc-
tion set truth table). CLK and DI then become don't care
inputs waiting for a new start condition to be detected.
3.0
PIN DESCRIPTION
3.1
Chip Select (CS)
Note: CS must go LOW between consecutive
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated and/or in
progress will be completed, regardless of the CS input
signal. If CS is brought LOW during a program cycle,
the device will go into standby mode as soon as the
programming cycle is completed.
instructions.
3.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
3.4
Data Out (DO)
CS must be LOW for 250 ns minimum (TCSL) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
Data Out is used in the READ and PRREAD mode to
output data synchronously with the CLK input (TPD
after the positive edge of CLK).
3.2
Serial Clock (CLK)
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available on the DO pin if CS is
brought HIGH after held LOW for minimum chip select
low time (TCSL) and an ERASE or WRITE operation
has been initiated.
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LCS56/66.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (TCDD)
and clock LOW time (TCKL). This gives the controlling
master freedom in preparing opcode, address, and
data.
The status signal is not available on DO, if CS is held
LOW or HIGH during the entire WRITE or ERASE
cycle. In all other cases DO is in the HIGH-Z mode. If
status is checked after the WRITE/ERASE cycle, a
pull-up resistor on DO is required to read the READY
signal.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
3.5
Program Enable (PE)
This pin should be held HIGH in the programming
mode or when executing the Protect Register program-
ming instructions.
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
3.6
Protect Register Enable (PRE)
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all required opcode, address, and
This pin should be held HIGH when executing all Pro-
tect Register instructions. Otherwise, it must be held
LOW for normal operations.
DS11181E-page 10
2004 Microchip Technology Inc.
93LCS56/66
93LCS56/66 Product Identification System
To order or to obtain information, e.g., on pricing or delivery, please use the listed part numbers, and refer to the factory or the listed
sales offices.
93LCS56/66
–
/P
P = Plastic DIP (300 mil Body), 8-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SM = Plastic SOIC (207 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead
Package:
Temperature
Range:
Blank = 0°C to +70°C
I = -40°C to +85°C
93LCS56/66 Microwire Serial EEPROM
93LCS56T/66T Microwire Serial EEPROM (Tape and Reel)
Device:
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-
mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277
3. The Microchip Worldwide Web Site (www.microchip.com)
2004 Microchip Technology Inc.
DS11181E-page 11
93LCS56/66
NOTES:
DS11181E-page 12
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS11181E-page 13
WORLDWIDE SALES AND SERVICE
China - Beijing
Singapore
AMERICAS
Corporate Office
2355 West Chandler Blvd.
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Technical Support: 480-792-7627
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#07-02 Prime Centre
Singapore, 188980
Tel: 65-6334-8870 Fax: 65-6334-8850
Taiwan
Kaohsiung Branch
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Min Chuan 2nd Road
Kaohsiung 806, Taiwan
Tel: 886-7-536-4816
Fax: 886-7-536-4817
China - Chengdu
Rm. 2401-2402, 24th Floor,
Ming Xing Financial Tower
No. 88 TIDU Street
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Tel: 86-28-86766200
Atlanta
3780 Mansell Road, Suite 130
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Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Taiwan Branch
Fax: 86-28-86766599
Boston
11F-3, No. 207
China - Fuzhou
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Tel: 86-591-7503506
Fax: 86-591-7503521
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Tel: 978-692-3848
Fax: 978-692-3821
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Tel: 886-2-2717-7175 Fax: 886-2-2545-0139
Taiwan
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Tel: 886-3-572-9526
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
China - Hong Kong SAR
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Dallas
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Austria
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Denmark
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Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
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Room 701, Bldg. B
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Tel: 86-755-82901380
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China - Shunde
Fax: 248-538-2260
Kokomo
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Tel: 86-757-28395507 Fax: 86-757-28395571
Los Angeles
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Tel: 949-462-9523
Germany
China - Qingdao
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Tel: 86-532-5027355 Fax: 86-532-5027205
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Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Fax: 949-462-9608
San Jose
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Tel: 650-215-1444
Italy
India
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20025 Legnano (MI)
Milan, Italy
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1 Floor, Wing A (A3/A4)
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Tel: 91-80-22290061 Fax: 91-80-22290062
Japan
Fax: 650-961-0286
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands
Waegenburghtplein 4
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Tel: 31-416-690399
Toronto
6285 Northam Drive, Suite 108
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Tel: 905-673-0699
Yusen Shin Yokohama Building 10F
3-17-2, Shin Yokohama, Kohoku-ku,
Yokohama, Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Fax: 905-673-6509
Fax: 31-416-690340
ASIA/PACIFIC
Australia
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Unit 32 41 Rawson Street
Epping 2121, NSW
Sydney, Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
United Kingdom
505 Eskdale Road
Winnersh Triangle
Korea
168-1, Youngbo Bldg. 3 Floor
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Tel: 82-2-554-7200 Fax: 82-2-558-5932 or
82-2-558-5934
07/12/04
2004 Microchip Technology Inc.
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