ATA6563-GBQW0 [MICROCHIP]
High-Speed CAN Transceiver with Standby Mode;
| 型号： | ATA6563-GBQW0 |
| 厂家： | 
MICROCHIP |
| 描述： | High-Speed CAN Transceiver with Standby Mode |
| 文件： | 总32页 (文件大小：1484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATA6562/3
High-Speed CAN Transceiver with Standby Mode
Features
General Description
• Fully ISO 11898-2, ISO 11898-2: 2016 and
SAE J2962-2 Compliant
The ATA6562/3 is a high-speed CAN transceiver that
provides an interface between a Controller Area Net-
work (CAN) protocol controller and the physical
Two-Wire CAN bus. The transceiver is designed for
high-speed (up to 5 Mbps) CAN applications in the
automotive industry, providing differential transmit and
receive capability to (a microcontroller with) a CAN pro-
tocol controller.
• CAN FD Ready
• Communication Speed up to 5 Mbps
• ISO 26262 Functional Safety Ready
• Low Electromagnetic Emission (EME) and High
Electromagnetic Immunity (EMI)
• Differential Receiver with Wide Common-Mode
Range
It offers improved electromagnetic compatibility (EMC)
and ESD performance as well as features such as:
• ATA6562: Silent Mode
• Ideal passive behavior to the CAN bus when the
supply voltage is off
• Remote Wake-Up Capability via CAN Bus -
Wake-Up on Pattern (WUP), as Specified in
ISO 11898-2: 2016, 3.8 µs Activity Filter Time
• Direct interfacing to microcontrollers with supply
voltages from 3V to 5V (ATA6563)
• Functional Behavior Predictable under All Supply
Conditions
Three operating modes together with the dedicated
fail-safe features make the ATA6562/3 an excellent
choice for all types of high-speed CAN networks, espe-
cially in nodes requiring Low-Power mode with
wake-up capability via the CAN bus.
• Transceiver Disengages from the Bus When Not
Powered Up
• RXD Recessive Clamping Detection
• High Electrostatic Discharge (ESD) Handling
Capability on the Bus Pins
Package Types
• Bus Pins Protected Against Transients in
Automotive Environments
ATA6562
SOIC
ATA6563
SOIC
• Transmit Data (TXD) Dominant Time-Out
Function
• Undervoltage Detection on VCC and VIO Pins
TXD
STBY
CANH
TXD
STBY
CANH
1
2
8
7
1
2
8
7
• CANH/CANL Short-Circuit and Overtemperature
Protected
GND
GND
VCC 3
6
5
CANL
NSIL
VCC 3
6
5
CANL
VIO
• Fulfills the OEM “Hardware Requirements for LIN,
CAN and FlexRay Interfaces in Automotive Appli-
cations”, Rev. 1.3
4
4
RXD
RXD
• AEC-Q100 and AEC-Q006 Qualified
ATA6563
3 x 3 VDFN* with
wettable flanks
• Two Ambient Temperature Grades Available:
ATA6562
3 x 3 VDFN* with
wettable flanks
- ATA6562-GAQW1, ATA6563-GAQW1,
ATA6562-GBQW1 and ATA6563-GBQW1 up
to Tamb = +125°C
TXD
STBY
TXD
STBY
1
2
8
7
1
2
8
7
- ATA6562-GAQW0, ATA6563-GAQW0,
ATA6562-GBQW0 and ATA6563-GBQW0 up
to Tamb = +150°C
GND
GND
CANH
CANL
VIO
CANH
CANL
NSIL
VCC
RXD
VCC
RXD
3
4
6
5
3
4
6
5
• Packages: 8-pin SOIC, 8-pin VDFN with Wettable
Flanks (Moisture Sensitivity Level 1)
Applications
*Includes Exposed Thermal Pad (EP); see Table 1-2.
Classical CAN and CAN FD networks in Automotive,
Industrial, Aerospace, Medical and Consumer
applications.
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 1
ATA6562/3
ATA6562/3 Family Members
Device
VIO Pin
NSIL Grade 0 Grade 1 VDFN8 SOIC8
Description
ATA6562-GAQW0
ATA6562-GAQW1
ATA6562-GBQW0
ATA6562-GBQW1
ATA6563-GAQW0
X
X
X
X
X
X
X
X
X
Standby mode and Silent mode
Standby mode and Silent mode
Standby mode and Silent mode
Standby mode and Silent mode
X
X
X
X
X
X
X
X
X
X
Standby mode, VIO - pin for
compatibility with 3.3V and 5V
microcontroller
ATA6563-GAQW1
ATA6563-GBQW0
ATA6563-GBQW1
X
Standby mode, VIO - pin for
compatibility with 3.3V and 5V
microcontroller
X
X
X
Standby mode, VIO-pin for com-
patibility with 3.3V and 5V micro-
controller
X
Standby mode, VIO - pin for
compatibility with 3.3V and 5V
microcontroller
Note:
For ordering information, see the Product Identification System section.
DS20005790E-page 2
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
Functional Block Diagram
V,2
5(1)
V&&
3
VCC
Temperature
Protection
VIO(1)
VIO(1)
VIO(1)
7
Slope Control
and
CANH
TXD
Time-Out-
Timer
1
8
TXD
STBY
NSIL
Driver
6
CANL
Control Unit
5(1)
VIO(ꢀꢁ
HSC(2)
4
MUX
RXD
Wake-up
Filter
WUC(3)
2
GND
Notes: 1. Pin 5: ATA6563: VIO
ATA6562: NSIL (the VIO line and the VCC line are internally connected)
2. HSC: High-Speed comparator
3. WUC: Wake-Up comparator
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 3
ATA6562/3
• ATA6563: The pin 5 is the VIO pin and should be
connected to the microcontroller supply voltage.
This allows direct interfacing to microcontrollers
with supply voltages down to 3V and adjusts the
signal levels of the TXD, RXD, and STBY pins to
the I/O levels of the microcontroller. The I/O ports
are supplied by the VIO pin.
1.0
FUNCTIONAL DESCRIPTION
The ATA6562/3 is a stand-alone dual high-speed CAN
transceiver compliant with the ISO 11898-2, ISO
11898-2: 2016, ISO 11898-5 and SAE J2962-2 CAN
standards. It provides a very low current consumption
in Standby mode and wake-up capability via the CAN
bus. There are two versions available, only differing in
the function of pin 5:
1.1
Operating Modes
• ATA6562: The pin 5 is the control input for Silent
mode NSIL, allowing the ATA6562 to only receive
data but not send data via the bus. The output
driver stage is disabled. The VIO line and the
VCC line are internally connected, this sets the
signal levels of the TXD, RXD, STBY, and NSIL
pins to levels compatible with 5V microcontrollers.
Each of the transceivers supports three operating
modes: Unpowered, Standby and Normal. The
ATA6562 additionally has the Silent mode. These
modes can be selected via the STBY and NSIL pin.
See Figure 1-1 and Table 1-1 for a description of the
operating modes.
FIGURE 1-1:
OPERATING MODES
ATA6562
ATA6563
VCC < Vuvd(VCC) or
VIO < Vuvd(VIO)
VCC < Vuvd(VCC) or
VIO < Vuvd(VIO)
VCC < Vuvd(VCC)
VCC < Vuvd(VCC)
Unpowered
Mode
Unpowered
Mode
VCC < Vuvd(VCC) or
IO < Vuvd(VIO)
VCC > Vuvd(VCC) or
IO > Vuvd(VIO)
VCC < Vuvd(VCC)
VCC > Vuvd(VCC)
STBY = 1
V
V
STBY = 1
STBY = 1
STBY = 1
Standby
Mode
Standby
Mode
STBY = 0 and
(NSIL = 0 or
TXD = 0)
STBY = 0 and
NSIL = 1 and
TXD = 1 and
Error = 0
STBY = 0 and
TXD = 0
STBY = 0 and
TXD = 1 and
Error = 0
NSIL = 1 and TXD = 1 and Error = 0
NSIL = 0 or Error = 1
TXD = 1 and Error = 0
Error = 1
Silent
Mode
Normal
Mode
Silent
Mode *
Normal
Mode
* Silent Pode is externally not accessible
Note: For the ATA6563 NSIL is internally set to “1”.
TABLE 1-1:
OPERATING MODES
STBY
Inputs
NSIL
Outputs
CAN Driver
Mode
Pin TXD
Pin RXD
Unpowered
Standby
X(3)
X(3)
X(3)
X(3)
X(3)
X(3)
Recessive
Recessive
Recessive
Dominant
Recessive
Recessive
Active(4)
Active(1)
LOW
HIGH
LOW
LOW
LOW
Silent (only for ATA6562)
Normal
LOW
HIGH(2)
HIGH(2)
LOW
HIGH
HIGH
Note 1: LOW if the CAN bus is dominant, HIGH if the CAN bus is recessive.
2: Internally pulled up if not bonded out.
3: Irrelevant
4: Reflects the bus only for wake-up
DS20005790E-page 4
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
To switch the device in normal operating mode, set the
STBY pin to low and the TXD pin to high (see Table 1-1
and Figure 1-2). The STBY pin provides a pull-up
resistor to VIO, thus ensuring a defined level if the pin
is open.
1.1.1
NORMAL MODE
A low level on the STBY pin together with a high level
on pin TXD selects the Normal mode. In this mode, the
transceiver is able to transmit and receive data via the
CANH and CANL bus lines (see Functional Block
Diagram). The output driver stage is active and drives
data from the TXD input to the CAN bus. The
High-Speed Comparator (HSC) converts the analog
data on the bus lines into digital data which is output to
pin RXD. The bus biasing is set to VVCC/2 and the
undervoltage monitoring of VCC is active.
Please note that the device cannot enter Normal mode
as long as TXD is at ground level.
The switching into Normal mode is depicted in the
following two figures, Figure 1-2 and Figure 1-3.
The slope of the output signals on the bus lines is
controlled and optimized in a way that guarantees the
lowest possible electromagnetic emission (EME).
FIGURE 1-2:
SWITCHING FROM STANDBY MODE TO NORMAL MODE (NSIL = HIGH)
ꢀꢂꢁ ꢁ
ꢀꢁꢂꢃ/
ꢀꢁ
ꢀꢁꢂꢃ
ꢀꢁ
ꢘ/
ꢀꢁ
)
ꢎ/ ꢏꢐꢑꢒ'*ꢓ,ꢔ "%ꢕꢖ/ꢗ/
ꢄꢂ
ꢀꢁꢂ
ꢃꢂ
ꢀꢁ
ꢀꢁ
ꢙꢚꢀ.(/ꢛꢆ+/
ꢄ#ꢅ$ꢆ)ꢇ!ꢈ/
ꢉ!ꢊꢅ/
ꢀ)ꢆꢋꢊꢌ-/ꢉ!ꢍꢅ/
ꢜ!&ꢝꢆꢞ/ꢉ!ꢊꢅ/
ꢀꢁ
FIGURE 1-3:
SWITCHING FROM SILENT MODE TO NORMAL MODE
ꢀꢁꢂꢃ0
ꢀꢁ
ꢀꢁ
ꢄꢀꢅꢆ0
ꢀꢁꢂꢃ
ꢀꢁ
ꢙ
-
ꢀꢁ
ꢏ0
ꢐꢑꢒꢓ+ꢔꢕꢖ$&) ꢗ0ꢘ0
ꢃꢂ
ꢚ0ꢂꢃ ꢛꢇꢜꢀ/,0ꢇ"ꢉ.ꢇ0 ꢇ
ꢆ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢇ
ꢈꢃ
ꢉꢊꢃ
ꢀꢁ ꢄꢅꢃ
ꢝ0
ꢇ'ꢈ(ꢉ-ꢊ%#0
ꢋ%ꢌꢈ0
ꢀꢊꢍꢈ#-0ꢋ%ꢌꢎ0
ꢄ%*"ꢉꢞ0ꢋ%ꢌꢈ0
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 5
ATA6562/3
1.1.2
SILENT MODE (ONLY WITH THE
ATA6562)
1.1.3.1
Remote Wake-up via the CAN Bus
In Standby mode the bus lines are biased to ground to
reduce current consumption to a minimum. The
ATA6562/3 monitors the bus lines for a valid wake-up
pattern as specified in the ISO 11898-2: 2016. This
filtering helps to avoid spurious wake-up events, which
would be triggered by scenarios such as a dominant
clamped bus or by a dominant phase due to noise,
spikes on the bus, automotive transients or EMI.
A low level on the NSIL pin (available on Pin 5) and on
the STBY pin selects Silent mode. This receive-only
mode can be used to test the connection of the bus
medium. In Silent mode, the ATA6562 can still receive
data from the bus, but the transmitter is disabled and
therefore no data can be sent to the CAN bus. The bus
pins are released to recessive state. All other IC
functions, including the high-speed comparator (HSC),
continue to operate as they do in Normal mode. Silent
mode can be used to prevent a faulty CAN controller
from disrupting all network communications.
The wake-up pattern consists of at least two
consecutive dominant bus levels for a duration of at
least tFilter, each separated by a recessive bus level
with a duration of at least tFilter. Dominant or recessive
bus levels shorter than tFilter are always being ignored.
The complete dominant-recessive-dominant pattern
(as shown in Figure 1-4) must be received within the
bus wake-up time-out time tWake to be recognized as a
valid wake-up pattern. Otherwise, the internal wake-up
logic is reset and then the complete wake-up pattern
must be retransmitted to trigger a wake-up event. Pin
RXD remains at high level until a valid wake-up event
has been detected.
1.1.3
STANDBY MODE
A high level on the STBY pin selects Standby mode. In
this mode, the transceiver is not able to transmit or
correctly receive data via the bus lines. The transmitter
and the high-speed comparator (HSC) are switched off
to reduce current consumption.
For ATA6562 only: In the event the NSIL input pin is
set to low in Standby mode, the internal pull-up resistor
causes an additional quiescent current from VIO to
GND. Microchip recommends setting the NSIL pin to
high in Standby mode.
During Normal mode, at a VCC undervoltage condition
or when the complete wake-up pattern is not received
within tWake, no wake-up is signalled at the RXD pin.
When a valid CAN wake-up pattern is detected on the
bus, the RXD pin switches to low to signal a wake-up
request. A transition to Normal mode is not triggered
until the STBY pin is forced back to low by the micro-
controller.
FIGURE 1-4:
TIMING OF THE BUS WAKE-UP PATTERN (WUP) IN STANDBY MODE
ꢀꢁꢁꢁꢁꢁꢁꢁꢂꢃꢃꢃꢄꢄ
ꢀꢁꢂꢃꢄ
ꢀꢁꢂꢑꢄ
ꢅꢆꢇꢈꢉꢊꢉꢋꢄ
ꢌꢍꢎꢍꢏꢏꢈꢐꢍꢄ
ꢅꢆꢇꢈꢉꢊꢉꢋꢄ
ꢀꢁꢁꢁꢁꢁꢁꢁꢂꢃꢃꢃꢄꢄ
ꢀꢁꢂꢃꢄꢅꢄꢀꢆꢇꢄꢈꢉꢂꢊꢄ
ꢋꢌꢍꢎꢄꢏꢄꢐꢆꢑꢄꢈꢉꢂꢊꢄ
ꢂꢁ
ꢀꢁ
ꢃꢄꢅꢆꢇ
ꢀꢁꢂ
ꢀꢁꢂꢃ ꢄꢅꢆꢇꢈꢉꢊꢃ ꢀꢁ
ꢋꢂꢃꢂꢋꢌꢍꢎꢏꢏꢇꢐꢃ
DS20005790E-page 6
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
1.2.5
The
OVERTEMPERATURE
PROTECTION
1.2
Fail-safe Features
1.2.1
TXD DOMINANT TIME-OUT
FUNCTION
output
drivers
are
protected
against
overtemperature conditions. If the junction temperature
exceeds the shutdown junction temperature, TJsd, the
output drivers are disabled until the junction
temperature drops below TJsd and pin TXD is at high
level again. The TXD condition ensures that output
driver oscillations due to temperature drift are avoided.
See Figure 1-5.
A TXD dominant time-out timer is started when the
TXD pin is set to low. If the low state on the TXD pin
persists for longer than tto(dom)TXD, the transmitter is
disabled, releasing the bus lines to recessive state.
This function prevents a hardware and/or software
application failure from driving the bus lines to a
permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is
reset when the TXD pin is set to high. If the low state on
the TXD pin was longer than tto(dom)TXD, then the TXD
pin has to be set to high longer 4 µs in order to reset the
TXD dominant time-out timer.
1.2.6
SHORT-CIRCUIT PROTECTION OF
THE BUS PINS
The CANH and CANL bus outputs are short-circuit
protected, either against GND or a positive supply
voltage.
A
current-limiting circuit protects the
transceiver against damage. If the device is heating up
due to a continuous short on CANH or CANL, the
internal overtemperature protection switches off the
bus transmitter.
1.2.2
INTERNAL PULL-UP STRUCTURE
AT THE TXD AND STBY INPUT PINS
The TXD and STBY pins have an internal pull-up
resistor to VIO. This ensures a safe, defined state in
case one or both pins are left floating. Pull-up currents
flow in these pins in all states, meaning all pins should
be in high state during Standby mode to minimize the
current consumption.
1.2.7
RXD RECESSIVE CLAMPING
This fail-safe feature prevents the controller from
sending data on the bus if its RXD line is clamped to
HIGH (e.g., recessive). That is, if the RXD pin cannot
signalize a dominant bus condition because it is e.g,
shorted to VCC, the transmitter within ATA6562/3 is
disabled to avoid possible data collisions on the bus. In
Normal and Silent mode (only ATA6562), the device
permanently compares the state of the high-speed
comparator (HSC) with the state of the RXD pin. If the
HSC indicates a dominant bus state for more than
tRC_det without the RXD pin doing the same, a
recessive clamping situation is detected and the
transceiver is forced into Silent mode. This Fail-safe
mode is released by either entering Standby or
Unpowered mode or if the RXD pin is showing a
dominant (e.g., low) level again. See Figure 1-6.
1.2.3
UNDERVOLTAGE DETECTION ON
PIN VCC
If VVCC or VVIO drops below its undervoltage detection
levels (Vuvd(VCC) and Vuvd(VIO))(see Section 2.0,
Electrical Characteristics), the transceiver switches off
and disengages from the bus until VVCC and VVIO has
recovered. The low-power wake-up comparator is only
switched off during a VCC and VIO undervoltage. The
logic state of the STBY pin is ignored until the VVCC
voltage or VVIO voltage has recovered.
1.2.4
BUS WAKE UP ONLY AT
DEDICATED WAKE-UP PATTERN
Due to the implementation of the wake-up filtering the
ATA6562/3 does not wake-up when the bus is in a long
dominant phase, it only wakes up at a dedicated
wake-up pattern as specified in the ISO 11898-2: 2016.
This means for
a valid wake-up at least two
consecutive dominant bus levels for a duration of at
least tFilter, each separated by a recessive bus level
with a duration of at least tFilter must be received via the
bus. Dominant or recessive bus levels shorter than
tFilter are always being ignored. The complete
dominant-recessive-dominant pattern as shown in
Figure 1-4, must be received within the bus wake-up
time-out time tWake to be recognized as a valid wake-up
pattern. This filtering leads to a higher robustness
against EMI and transients and reduces therefore the
risk of an unwanted bus wake- up significantly.
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 7
ATA6562/3
FIGURE 1-5:
RELEASE OF TRANSMISSION AFTER OVERTEMPERATURE CONDITION
Failure
Overtemp
OT
Overtemperature
t
t
TXD
VIO
GND
BUS VDIFF
(CANH-CANL)
D
R
D
R
D
R
t
t
RXD
VIO
GND
t
FIGURE 1-6:
RXD RECESSIVE CLAMPING DETECTION
DS20005790E-page 8
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
1.3
Pin Description
The descriptions of the pins are listed in Table 1-2.
TABLE 1-2:
ATA6562
PIN FUNCTION TABLE
ATA6563
Pin Name
Description
SOIC8 VDFN8 SOIC8 VDFN8
Transmit data input
1
2
1
2
1
2
1
2
TXD
GND
VCC
RXD
VIO
Ground
3
3
3
3
Supply voltage
4
4
4
4
Receive data output; reads out data from the bus lines
Supply voltage for I/O level adapter
Silent mode control input (low active);
Low-level CAN bus line
—
5
—
5
5
5
—
6
—
6
NSIL
CANL
CANH
STBY
EP
6
6
7
7
7
7
High-level CAN bus line
8
8
8
8
Standby mode control input
—
9
—
9
Exposed Thermal Pad: Heat slug, internally connected to the
GND pin.
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 9
ATA6562/3
1.4
Typical Application
Typical Application ATA6562
5V
12V
BAT
+
22 µF(1)
100 nF
VCC
7
3
VDD
Microcontroller
GND
STBY
NSIL
TXD
CANH
CANL
8
5
1
4
CANH
ATA6562
2
RXD
6
CANL
GND
GND
(1) The size of this capacitor depends on the used external voltage regulator
Note: For VDFN8 package: EP (heatslug) must always be connected to GND.
Typical Application ATA6563
3.3V
12V
BAT
5V
12V
22 µF(1)
+
100 nF
100 nF
VIO
VCC
5
3
VDD
Microcontroller
GND
CANH
CANL
7
6
CANH
STBY
TXD
8
1
4
ATA6563
2
RXD
CANL
GND
GND
(1) The size of this capacitor depends on the used external voltage regulator
Note: For VDFN8 package: EP (heatslug) must always be connected to GND.
DS20005790E-page 10
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
2.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
DC Voltage at CANH, CANL (VCANH, VCANL) ................................................................................................–27 to +42V
Transient Voltage at CANH, CANL (according to ISO 7637 part 2) (VCANH, VCANL) .................................–150 to +100V
Max. Differential Bus Voltage (VDiff).................................................................................................................–5 to +18V
DC Voltage on all other Pins (VX) ................................................................................................................–0.3 to +5.5V
ESD according to IBEE CAN EMC - Test Specification Following IEC 61000-4-2 - Pin CANH, CANL ..................±8 kV
ESD (HBM Following STM5.1 with 1.5 kΩ/100 pF) - Pins CANH, CANL to GND....................................................±6 kV
Component Level ESD (HBM according to ANSI/ESD STM5.1, JESD22-A114, AEC-Q100 (002) ........................±4 kV
CDM ESD STM 5.3.1..............................................................................................................................................±750V
ESD Machine Model AEC-Q100-RevF(003)...........................................................................................................±200V
Virtual Junction Temperature (TvJ)............................................................................................................. –40 to +175°C
Storage Temperature Range (Tstg).........................................................................................................-55°C to +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
ELECTRICAL CHARACTERISTICS
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Supply, Pin VCC
Symbol
Min.
Typ.
Max.
Units
Conditions
Supply Voltage
VVCC
IVCC_sil
IVCC_rec
IVCC_dom
4.5
1.9
2
—
2.5
—
5.5
3.2
5
V
Supply Current in Silent Mode
mA
mA
mA
Silent mode, VTXD = VVIO
Recessive, VTXD = VVIO
Dominant, VTXD = 0V
Supply Current in Normal
Mode
30
50
70
Short between CANH and CANL
(Note 1)
IVCC_short
IVCC_STBY
Vuvd(VCC)
—
—
85
mA
VCC = VIO,
—
—
—
7
12
—
µA
µA
V
Supply Current in Standby
Mode
VTXD = VNSIL = VVIO
Ta = 25°C (Note 3)
Undervoltage Detection
Threshold on Pin VCC
2.75
—
4.5
I/O Level Adapter Supply, Pin VIO (only with the ATA6563)
Supply Voltage on Pin VIO
VVIO
2.8
—
5.5
V
Normal and Silent mode
Recessive, VTXD = VVIO
IVIO_rec
10
80
250
µA
Supply Current on Pin VIO
Normal and Silent mode
Dominant, VTXD = 0V
IVIO_dom
IVIO_STBY
Vuvd(VIO)
50
—
350
—
500
1
µA
µA
V
Standby mode
Undervoltage Detection
Threshold on Pin VIO
1.3
—
2.7
Note 1: 100% correlation tested
2: Characterized on samples
3: Design parameter
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 11
ATA6562/3
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Mode Control Input, Pin NSIL and STBY
0.7
VVIO
—
—
VVIO
+0.3
V
V
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
0.3
VVIO
–0.3
Pull-Up Resistor to VCC
Rpu
IL
75
–2
125
—
175
+2
kΩ
µA
VSTBY = 0V, VNSIL = 0V
High-Level Leakage Current
CAN Transmit Data Input, Pin TXD
VSTBY = VVIO, VNSIL = VVIO
0.7
VVIO
VVIO
+0.3
High-Level Input Voltage
Low-Level Input Voltage
VIH
VIL
—
—
V
V
0.3
VVIO
–0.3
Pull-Up Resistor to VCC
High-Level Leakage Current
Input Capacitance
RTXD
ITXD
20
–2
—
35
—
5
50
+2
10
kΩ
µA
pF
VTXD = 0V
Normal mode, VTXD = VVIO
Note 3
CTXD
CAN Receive Data Output, Pin RXD
Normal mode,
High-Level Output Current
IOH
IOL
–8
2
—
—
–1
12
mA
mA
V
RXD = VVIO – 0.4V, VVIO = VVCC
Normal mode,
RXD = 0.4V, Bus Dominant
Low-Level Output Current,
Bus Dominant
V
Bus Lines, Pins CANH and CANL
VTXD = 0V, t < tto(dom)TXD
RL = 50Ω to 65Ω
pin CANH (Note 1)
2.75
0.5
3.5
1.5
4.5
V
V
Single Ended Dominant
Output Voltage
VO(dom)
VTXD = 0V, t < tto(dom)TXD
RL = 50Ω to 65Ω
2.25
pin CANL (Note 1)
VSym = (VCANH + VCANL) / VVCC
,
Transmitter Voltage Symmetry
VSym
0.9
1.5
1.0
—
1.1
3
—
V
Split Termination, RL = 2 x 30,
CSplit = 4.7 nF (Note 3)
VTXD = 0V, t < tto(dom)TXD
RL = 45Ω to 65Ω
1.5
1.5
—
—
3.3
5
V
V
RL = 70Ω (Note 3)
RL = 2240Ω (Note 3)
Bus Differential Output
Voltage
Normal and Silent mode:
VVCC = 4.75V to 5.25V
VDiff
–50
—
—
+50
mV
mV
VTXD = VVIO, recessive, no load
Standby mode:
VVCC = 4.75V to 5.25V
–200
+200
VTXD = VVIO, recessive, no load
Note 1: 100% correlation tested
2: Characterized on samples
3: Design parameter
DS20005790E-page 12
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
0.5
VVCC
Normal and Silent mode,
VTXD = VVIO, no load
2
3
V
Single Ended Recessive
Output Voltage
VO(rec)
Standby mode,
VTXD = VVIO, no load
–0.1
0.5
0.4
50
—
0.7
0.7
120
+0.1
0.9
V
V
Normal and Silent mode (HSC),
Vcm(CAN) = –27V to +27V
Differential Receiver
Threshold Voltage
Vth(RX)dif
Standby mode (WUC),
Vcm(CAN) = –27V to +27V (Note 1)
1.1
V
Differential Receiver
Hysteresis Voltage
Normal and Silent mode (HSC),
Vhys(RX)dif
200
mV
Vcm(CAN) = –27V to +27V (Note 1)
VTXD = 0V, t < tto(dom)TXD
,
–75
35
—
—
–35
75
mA
mA
V
VCC = 5V
pin CANH, VCANH = –5V
Dominant Output Current
IIO(dom)
VTXD = 0V, t < tto(dom)TXD
,
VVCC = 5V
pin CANL, VCANL = +40V
Normal and Silent mode,
VTXD = VVIO, no load,
Recessive Output Current
Leakage Current
IIO(rec)
–5
–5
–5
—
0
+5
+5
+5
mA
µA
µA
V
CANH = VCANL = –27V to +32V
VVCC = VVIO = 0V,
CANH = VCANL = 5V
V
IIO(leak)
VCC = VIO connected to GND
with R = 47kΩ
0
VCANH = VCANL = 5V (Note 3)
9
9
15
15
28
28
kΩ
kΩ
VCANH = VCANL = 4V
Input Resistance
Ri
–2V ≤ VCANH ≤ +7V,
–2V ≤ VCANL ≤ +7V (Note 3)
Between CANH and CANL
–1
–1
0
0
+1
+1
%
%
VCANH = VCANL = 4V (Note 1)
Input Resistance Deviation
Differential Input Resistance
ΔRi
Between CANH and CANL
–2V ≤ VCANH ≤ +7V,
–2V ≤ VCANL ≤ +7V (Note 3)
18
18
30
30
56
56
kΩ
kΩ
VCANH = VCANL = 4V (Note 1)
Ri(dif)
–2V ≤ VCANH ≤ +7V,
–2V ≤ VCANL ≤ +7V (Note 3)
Common-mode Input
Capacitance
f = 500 kHz, CANH and CANL
referred to GND (Note 3)
Ci(cm)
Ci(dif)
—
—
—
—
20
10
pF
pF
f = 500kHz, between CANH and
CANL (Note 3)
Differential Input Capacitance
Note 1: 100% correlation tested
2: Characterized on samples
3: Design parameter
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 13
ATA6562/3
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Normal and Silent mode (HSC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V (Note 3)
–3
—
+0.5
V
Differential Bus Voltage
Range for RECESSIVE State
Detection
VDiff_rec
Standby mode (WUC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V(Note 3)
–3
0.9
—
—
—
+0.4
8.0
V
V
V
Normal and Silent mode (HSC)
–27V ≤ VCANH ≤ +27V,
–27V ≤ VCANL ≤ +27V (Note 3)
Differential Bus Voltage
Range for DOMINANT State
Detection
VDiff_dom
Standby mode (WUC)
–27V ≤ VCANH ≤ +27V,
1.15
8.0
–27V ≤ VCANL ≤ +27V (Note 3)
Transceiver Timing, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3
Delay Time from TXD to Bus
td(TXD-busdom)
40
40
20
20
—
—
—
—
130
130
100
100
ns
ns
ns
ns
Normal mode (Note 2)
Normal mode (Note 2)
Normal mode (Note 2)
Normal mode (Note 2)
Dominant
Delay Time from TXD to Bus
Recessive
td(TXD-busrec)
Delay Time from Bus
Dominant to RXD
td(busdom-RXD
)
Delay Time from Bus
Recessive to RXD
td(busrec-RXD)
Normal mode, Rising edge at pin
TXD
RL = 60Ω, CL = 100 pF
40
40
—
—
—
—
—
—
210
200
300
300
ns
ns
ns
ns
Normal mode, Falling edge at pin
TXD
RL = 60Ω, CL = 100 pF
Propagation Delay from TXD
to RXD
tPD(TXD-RXD)
Normal mode, Rising edge at pin
TXD
RL = 150Ω, CL = 100 pF (Note 3)
Normal mode, Falling edge at pin
TXD
RL = 150Ω, CL = 100pF (Note 3)
TXD Dominant Time-Out Time tto(dom)TXD
0.8
0.8
—
—
3
3
ms
ms
VTXD = 0V, Normal mode
Standby mode
Bus Wake-up Time-Out Time
tWake
Min. Dominant/Recessive Bus
Wake-up Time
tFilter
0.5
—
—
—
—
3
3.8
47
5
µs
µs
µs
µs
µs
Standby mode
Delay Time for Standby Mode
to Normal Mode Transition
tdel(stby-norm)
tdel(norm-stby)
tdel(norm-sil)
tdel(sil-norm)
—
—
—
—
Falling edge at pin STBY
Rising edge at pin STBY (Note 3)
Delay Time for Normal Mode
to Standby Mode Transition
Delay Time for Normal Mode
to Silent Mode Transition
Falling edge at pin NSIL
STBY = LOW (Note 3)
10
10
Delay time for Silent Mode to
Normal Mode Transition
Rising edge at pin NSIL
STBY = LOW (Note 3)
Note 1: 100% correlation tested
2: Characterized on samples
3: Design parameter
DS20005790E-page 14
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: The values below are valid for each of the two identical integrated CAN transceivers.
Grade 1: Tamb = -40°C to +125°C and Grade 0: Tamb = -40°C to +150°C; TvJ 170°C; VVCC = 4.5V to 5.5V; RL = 60Ω,
CL = 100 pF unless specified otherwise; all voltages are defined in relation to ground; positive currents flow into the IC.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Delay Time for Silent Mode to
Standby Mode Transition
Rising edge at pin STBY
NSIL = LOW (Note 3)
tdel(sil-stby)
—
—
5
µs
Delay Time for Standby Mode
to Silent Mode Transition
Rising edge at pin STBY
NSIL = LOW (Note 3)
tdel(stby-sil)
—
—
—
47
—
µs
ns
Debouncing Time for
Recessive Clamping State
Detection
V(CANH-CANL) > 900mV
RXD = high (Note 3)
tRC_det
90
Transceiver Timing for higher Bit Rates, Pins CANH, CANL, TXD, and RXD, see Figure 2-1 and Figure 2-3
Normal mode, tBit(TXD) = 500 ns
400
120
435
155
—
—
—
—
550
220
530
210
ns
ns
ns
ns
RL = 60, CL = 100 pF (Note 1)
Recessive Bit Time on Pin
RXD
tBit(RXD)
Normal mode, tBit(TXD) = 200 ns
RL = 60, CL = 100 pF
Normal mode, tBit(TXD) = 500 ns
RL = 60, CL = 100 pF (Note 1)
Recessive Bit Time on the
Bus
tBit(Bus)
Normal mode, tBit(TXD) = 200 ns
RL = 60, CL = 100 pF
Normal mode, tBit(TXD) = 500 ns
ΔtRec = tBit(RXD)–tBit(Bus)
RL = 60, CL = 100 pF (Note 1)
–65
–45
—
—
+40
+15
ns
ns
Receiver Timing Symmetry
ΔtRec
Normal mode, tBit(TXD) = 200 ns
ΔtRec = tBit(RXD)–tBit(Bus)
RL = 60, CL = 100 pF
Note 1: 100% correlation tested
2: Characterized on samples
3: Design parameter
TABLE 2-1:
TEMPERATURE SPECIFICATIONS
Parameters
Symbol
Min.
Typ.
Max.
Units
Thermal Characteristics SOIC8 Package
Thermal Resistance Virtual Junction to Ambient
RthvJA
TVJsd
—
145
—
—
K/W
°C
Thermal Shutdown of the Bus Drivers for
150
195
ATA6562-GAQW1, ATA6563-GAQW1 (Grade 1)
Thermal Shutdown of the Bus Drivers for
ATA6562-GAQW0, ATA6563-GAQW0 (Grade 0)
TVJsd
170
—
—
195
—
°C
°C
Thermal Shutdown Hysteresis
TvJsd_hys
15
Thermal Characteristics VDFN8 Package
Thermal Resistance Virtual Junction to
Heat Slug
RthvJC
—
10
—
K/W
Thermal Resistance Virtual Junction to Ambient,
where Heat Slug is soldered to PCB according
to JEDEC
RthvJA
TVJsd
—
50
—
—
K/W
°C
Thermal Shutdown of the Bus Drivers for
150
195
ATA6562-GBQW1, ATA6563-GBQW1 (Grade 1)
Thermal Shutdown of the Bus Drivers
ATA6562-GBQW0, ATA6563-GBQW0 (Grade 0)
TVJsd
170
—
—
195
—
°C
°C
Thermal Shutdown Hysteresis
TvJsd_hys
15
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 15
ATA6562/3
FIGURE 2-1:
TIMING TEST CIRCUIT FOR THE ATA6562/3 CAN TRANSCEIVER
FIGURE 2-2:
CAN TRANSCEIVER TIMING DIAGRAM 1
HIGH
LOW
TXD
CANH
CANL
dominant
0.9V
0.5V
VDiff
recessive
HIGH
0.7 VIO
RXD
0.3 V,2
LOW
td(TXD-busdom)
td(TXD-busrec)
td(busdom-RXD)
td(busrec-RXD)
tPD(TXD-RXD)
tPD(TXD-RXD)
DS20005790E-page 16
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
FIGURE 2-3:
CAN TRANSCEIVER TIMING DIAGRAM 2
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 17
ATA6562/3
NOTES:
DS20005790E-page 18
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
3.0
PACKAGING INFORMATION
Package Marking Information
8-Lead SOIC
Example
ATA6562 Grade 0
Example
ATA6562 Grade 1
721
721
ATA6562
1729256
ATA6562H
1729256
Example
ATA6563 Grade 0
Example
ATA6563 Grade 1
721
ATA6563H
1729256
721
ATA6563
1729256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
)
3
e
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 19
ATA6562/3
8-Lead 3 X 3 mm VDFN
Example
Example
ATA6562 Grade 0
ATA6562 Grade 1
6562
256
6562H
256
Example
Example
ATA6563 Grade 0
ATA6563 Grade 1
6563H
256
6563
256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20005790E-page 20
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2X
0.10 C A–B
D
A
D
NOTE 5
N
E
2
E1
2
E1
E
2X
0.10 C A–B
2X
0.10 C A–B
1
2
NOTE 1
e
NX b
0.25
C A–B D
B
NOTE 5
TOP VIEW
0.10 C
0.10 C
C
A2
A
SEATING
PLANE
8X
SIDE VIEW
A1
h
R0.13
R0.13
h
H
0.23
L
SEE VIEW C
(L1)
VIEW A–A
VIEW C
Microchip Technology Drawing No. C04-057-OA Rev F Sheet 1 of 2
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 21
ATA6562/3
8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
MIN
NOM
MAX
Number of Pins
Pitch
Overall Height
Molded Package Thickness
Standoff
N
8
e
1.27 BSC
A
-
-
-
-
1.75
-
0.25
A2
A1
E
1.25
0.10
§
Overall Width
6.00 BSC
Molded Package Width
Overall Length
Chamfer (Optional)
Foot Length
E1
D
h
3.90 BSC
4.90 BSC
0.25
0.40
-
-
0.50
1.27
L
Footprint
Foot Angle
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
L1
1.04 REF
0°
0.17
0.31
5°
-
-
-
-
-
8°
c
b
0.25
0.51
15°
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A & B to be determined at Datum H.
Microchip Technology Drawing No. C04-057-OA Rev F Sheet 2 of 2
DS20005790E-page 22
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
8-Lead Plastic Small Outline (OA) - Narrow, 3.90 mm (.150 In.) Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
SILK SCREEN
C
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
C
X1
Y1
1.27 BSC
5.40
Contact Pad Spacing
Contact Pad Width (X8)
Contact Pad Length (X8)
0.60
1.55
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2057-OA Rev F
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 23
ATA6562/3
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DS20005790E-page 24
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
'ꢀGrhqꢁWrꢂꢁUuvꢁQyhvpꢁ9hyꢁAyhꢃꢁIꢁGrhqꢁQhpxhtrꢁꢄR'7ꢅꢁꢀꢁ"" ꢁꢁ7qꢁbW9AId
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2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 25
ATA6562/3
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DS20005790E-page 26
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
APPENDIX A: REVISION HISTORY
Revision E (December 2021)
The following is the list of modifications:
• Updated the SOIC and VDFN package drawings
in Section 3.0 “Packaging Information”
• Minor typographical edits
Revision D (June 2020)
The following is the list of modifications:
• Updated parameter “Supply Current in Silent
Mode” in Table : Electrical Characteristics
• Added test conditions at several parameters in
Table : Electrical Characteristics
• Added parameter “Bus Differential Output Volt-
age” in Standby mode in Table : Electrical Charac-
teristics
• Updated Package Marking Information
Revision C (August 2019)
The following is the list of modifications:
• Updated Table 2-1: Temperature Specifications
• Added test conditions at several parameters in
Table : Electrical Characteristics
Revision B (August 2017)
The following is the list of modifications:
• Added new devices ATA6562-GBQW0 and
ATA6563-GBQW0 and updated the related infor-
mation across the document
• Updated Features section
• Updated ATA6562/3 Family Members section
• Updated Table 2-1: Temperature Specifications
• Updated Package Marking Information
• Updated Product Identification System section
• Various typographical edits
Revision A (June 2017)
• Original release of this document
• This document replaces Atmel – 9389C-
11/16ATA6562/3
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 27
ATA6562/3
NOTES:
DS20005790E-page 28
2017-2021 Microchip Technology Inc. and its subsidiaries
ATA6562/3
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
[X](1)
XX
Device Package
PART NO.
X
X
a) ATA6562-GAQW0:
b) ATA6562-GAQW1:
c) ATA6562-GBQW0:
d) ATA6562-GBQW1:
e) ATA6563-GAQW0:
f) ATA6563-GAQW1:
f) ATA6563-GBQW0:
ATA6562, 8-Lead SOIC,
Tape and Reel, Package
according to RoHS,
Tape and Reel
Option
Package directives
classification
Temperature
Range
Temperature Grade 0
Device:
ATA6562:
ATA6563:
High-speed CAN Transceiver with Standby
and Silent Mode CAN FD Ready
High-speed CAN Transceiver with Standby
Mode and VIO-pin CAN FD Ready
ATA6562, 8-Lead SOIC,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
ATA6562, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Package:
GA
GB
=
=
8-Lead SOIC
8-Lead VDFN
Temperature Grade 0
Tape and Reel
Option:
Q
=
=
330 mm diameter Tape and Reel
ATA6562, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
Package
W
Package according to RoHS(2)
directives
classification:
ATA6563, 8-Lead SOIC,
Tape and Reel, Package
according to RoHS,
Temperature
Range:
0
1
=
=
Temperature Grade 0 (-40°C to +150°C)
Temperature Grade 1 (-40°C to +125°C)
Temperature Grade 0
ATA6563, 8-Lead SOIC,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
ATA6563, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 0
g
ATA6563-GBQW1:
ATA6563, 8-Lead VDFN,
Tape and Reel, Package
according to RoHS,
Temperature Grade 1
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2: RoHS compliant, Maximum concentration
value of 0.09% (900 ppm) for Bromine (Br)
and Chlorine (Cl) and less than 0.15% (1500
ppm) total Bromine (Br) and Chlorine (Cl) in
any homogeneous material. Maximum
concentration value of 0.09% (900 ppm) for
Antimony (Sb) in any homogeneous material.
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 29
ATA6562/3
NOTES:
DS20005790E-page 30
2017-2021 Microchip Technology Inc. and its subsidiaries
Note the following details of the code protection feature on Microchip products:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and
under normal conditions.
•
•
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of
Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to
continuously improving the code protection features of our products.
This publication and the information herein may be used only
with Microchip products, including to design, test, and integrate
Microchip products with your application. Use of this informa-
tion in any other manner violates these terms. Information
regarding device applications is provided only for your conve-
nience and may be superseded by updates. It is your responsi-
bility to ensure that your application meets with your
specifications. Contact your local Microchip sales office for
additional support or, obtain additional support at https://
www.microchip.com/en-us/support/design-help/client-support-
services.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud,
CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO,
JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus,
maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower,
PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch,
SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash,
Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O,
Vectron, and XMEGA are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight
Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
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MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
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IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-
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BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES
ARE FORESEEABLE. TO THE FULLEST EXTENT
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON
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OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF
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any Microchip intellectual property rights unless otherwise
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SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, Symmcom, and Trusted Time are registered
trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017-2021, Microchip Technology Incorporated and its subsidiar-
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All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
ISBN: 978-1-5224-9513-0
2017-2021 Microchip Technology Inc. and its subsidiaries
DS20005790E-page 31
Worldwide Sales and Service
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Technical Support:
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Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Los Angeles
Tel: 48-22-3325737
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
Fax: 44-118-921-5820
DS20005790E-page 32
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09/14/21
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