ATF1504AS-7AX44 [MICROCHIP]
IC CPLD 64MC 7.5NS 44TQFP;
| 型号： | ATF1504AS-7AX44 |
| 厂家： | 
MICROCHIP |
| 描述： | IC CPLD 64MC 7.5NS 44TQFP 时钟 ATM 异步传输模式 输入元件 可编程逻辑 |
| 文件： | 总33页 (文件大小：378K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
High-
performance
Complex
Programmable
Logic Device
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
• Advanced EE Technology
ATF1504AS
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
ATF1504ASL
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• 3.3V or 5.0V I/O Pins
• Security Fuse Feature
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent – Latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• VCC Power-up Reset Option
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0950N–PLD–07/02
44-lead TQFP
Top View
44-lead PLCC
Top View
TDI/I/O
I/O
7
8
9
39 I/O
I/O/TDI
I/O
1
2
3
4
5
6
7
8
9
33 I/O
38 I/O/TDO
37 I/O
32 I/O/TDO
31 I/O
I/O
GND 10
PD1/I/O 11
I/O 12
36 I/O
I/O
35 VCC
34 I/O
GND
PD1/I/O
I/O
30 I/O
29 VCC
28 I/O
I/O/TMS 13
I/O 14
33 I/O
32 I/O/TCK
31 I/O
TMS/I/O
I/O
27 I/O
VCC 15
I/O 16
26 I/O/TCK
25 I/O
30 GND
29 I/O
VCC
I/O 17
I/O 10
I/O 11
24 GND
23 I/O
68-lead PLCC
Top View
84-lead PLCC
Top View
I/O 10
60 I/O
I/O 12
VCCIO 13
I/O/TDI 14
I/O 15
74 I/O
VCCIO 11
I/O/TD1 12
I/O 13
59 I/O
73 I/O
58 GND
57 I/O/TDO
56 I/O
72 GND
71 I/O/TDO
70 I/O
I/O 14
I/O 16
I/O 15
55 I/O
I/O 17
69 I/O
GND 16
I/O/PD1 17
I/O 18
54 I/O
I/O 18
68 I/O
GND 19
I/O/PD1 20
I/O 21
67 I/O
53 VCCIO
52 I/O
66 VCCIO
65 I/O
I/O/TMS 19
I/O 20
51 I/O
I/O 22
64 I/O
50 I/O/TCK
49 I/O
I/O/TMS 23
I/O 24
63 I/O
VCCIO 21
I/O 22
62 I/O/TCK
61 I/O
48 GND
47 I/O
I/O 25
I/O 23
VCCIO 26
I/O 27
60 I/O
I/O 24
46 I/O
59 GND
58 I/O
I/O 25
45 I/O
I/O 28
GND 26
44 I/O
I/O 29
57 I/O
I/O 30
56 I/O
I/O 31
55 I/O
GND 32
54 I/O
2
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
100-lead PQFP
Top View
100-lead TQFP
Top View
NC
NC
1
2
3
4
5
6
7
8
9
75 I/O
NC
NC
1
2
3
4
5
6
7
8
9
80 NC
79 NC
78 I/O
77 I/O
76 GND
75 I/O/TDO
74 NC
73 I/O
72 NC
71 I/O
70 I/O
69 I/O
68 VCCIO
67 I/O
66 I/O
65 I/O
64 I/O/TCK
63 I/O
62 I/O
61 GND
60 I/O
59 I/O
58 I/O
57 NC
56 I/O
55 NC
54 I/O
53 VCCIO
52 NC
51 NC
74 GND
73 I/O/TDO
72 NC
71 I/O
VCCIO
I/O/TDI
NC
I/O
I/O
VCCIO
I/O/TDI
NC
I/O
70 NC
69 I/O
NC
I/O
68 I/O
I/O
I/O
67 I/O
NC
I/O 10
GND 11
I/O/PD1 12
I/O 13
66 VCCIO
65 I/O
I/O 10
I/O 11
64 I/O
I/O 12
63 I/O
GND 13
I/O/PD1 14
I/O 15
I/O 14
62 I/O/TCK
61 I/O
I/O/TMS 15
I/O 16
60 I/O
I/O 16
I/O 17
59 GND
58 I/O
I/O/TMS 17
I/O 18
VCCIO 18
I/O 19
57 I/O
I/O 19
I/O 20
56 I/O
VCCIO 20
I/O 21
I/O 21
55 NC
54 I/O
NC 22
I/O 22
I/O 23
53 NC
52 I/O
I/O 23
NC 24
NC 24
I/O 25
51 VCCIO
I/O 25
NC 26
I/O 27
GND 28
NC 29
NC 30
3
0950N–PLD–07/02
Description
The ATF1504AS is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices
increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1504AS has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504AS allows fast, efficient generation of complex logic func-
tions. The ATF1504AS contains four such logic chains, each capable of creating sum
term logic with a fan-in of up to 40 product terms.
The ATF1504AS macrocell, shown in Figure 1, is flexible enough to support highly-com-
plex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
4
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Block Diagram
I/O (MC64)/GCLK3
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user for pur-
poses such as storing project name, part number, revision or date. The User Signature
is accessible regardless of the state of the security fuse.
The ATF1504AS device is an in-system programmable (ISP) device. It uses the indus-
try-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG’s
Boundary-scan Description Language (BSDL). ISP allows the device to be programmed
without removing it from the printed circuit board. In addition to simplifying the manufac-
turing flow, ISP also allows design modifications to be made in the field via software.
5
0950N–PLD–07/02
Product Terms and Select
Mux
Each ATF1504AS macrocell has five product terms. Each product term receives as its
possible inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
OR/XOR/CASCADE Logic
The ATF1504AS’s logic structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with a little small additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
Flip-flop
The ATF1504AS’s flip-flop has very flexible data and control functions. The data input
can come from either the XOR gate, from a separate product term or directly from the
I/O pin. Selecting the separate product term allows creation of a buried registered feed-
back within a combinatorial output macrocell. (This feature is automatically implemented
by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be
configured as a flow-through latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
The clock itself can be either one of the Global CLK Signals (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK sig-
nal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (product term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.
Output Select and Enable
The ATF1504AS macrocell output can be selected as registered or combinatorial. The
buried feedback signal can be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output enable signals. Any buffer can
be permanently enabled for simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configuration all the macrocell
resources are still available, including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be selected as either of the two dedi-
cated OE input pins as an I/O pin configured as an input, or as an individual product
term.
Global Bus/Switch Matrix
The global bus contains all input and I/O pin signals as well as the buried feedback sig-
nal from all 64 macrocells. The switch matrix in each logic block receives as its possible
inputs all signals from the global bus. Under software control, up to 40 of these signals
can be selected as inputs to the logic block.
6
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Foldback Bus
Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The sixteen foldback terms in each region allow generation
of high fan-in sum terms (up to sixteen product terms) with a nominal additional delay.
Figure 1. ATF1504AS Macrocell
7
0950N–PLD–07/02
Programmable Pin-
keeper Option for
Inputs and I/Os
The ATF1504AS offers the option of programming all input and I/O pins so that pin-
keeper circuits can be utilized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Input Diagram
Speed/Power
Management
The ATF1504AS has several built-in speed and power management features. The
ATF1504AS contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
I/O Diagram
To further reduce power, each ATF1504AS macrocell has a Reduced Power bit feature.
This feature allows individual macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1504AS also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power-down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
8
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the
AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP
.
The ATF1504AS macrocell also has an option whereby the power can be reduced on a
per macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned-down, thereby reducing the overall power consumption
of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1504AS designs are supported by several industry-standard third-party tools. Auto-
mated fitters allow logic synthesis using a variety of high level description languages
and formats.
Power-up Reset
The ATF1504AS is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from VCC crossing VRST, all registers will be ini-
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the
system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3. The clock must remain stable during TD.
The ATF1504AS has two options for the hysteresis about the reset level, VRST, Small
and Large. During the fitting process users may configure the device with the Power-up
Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large
option by including the flag “-power_reset” on the command line after “filename.POF”.
To allow the registers to be properly reinitialized with the Large hysteresis option
selected, the following condition is added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on
again.
When the Large hysteresis option is active, ICC is reduced by several hundred micro-
amps as well.
Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504AS fuse pat-
terns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
9
0950N–PLD–07/02
Programming
ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG
protocol. This capability eliminates package handling normally required for programming
and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1504AS via
the PC. ISP is performed by using either a download cable or a comparable board tester
or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel provided software utilities.
ATF1504AS devices can also be programmed using standard third-party programmers.
With third-party programmer, the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1504AS has a special feature that locks the device and prevents the inputs and
I/O from driving if the programming process is interrupted for any reason. The inputs
and I/O default to high-Z state during such a condition. In addition the pin-keeper option
preserves the former state during device programming, if this circuit were previously
programmed on the device. This prevents disturbing the operation of other circuits in the
system while the ATF1504AS is being programmed via ISP.
All ATF1504AS devices are initially shipped in the erased state thereby making them
ready to use for ISP.
Note:
For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
10
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
DC and AC Operating Conditions
Commercial
0°C - 70°C
5V 5%
Industrial
-40°C - 85°C
5V 10%
Operating Temperature (Ambient)
V
V
CCINT or VCCIO (5V) Power Supply
CCIO (3.3V) Power Supply
3.0V - 3.6V
3.0V - 3.6V
DC Characteristics
Symbol Parameter
Condition
IN = VCC
Min
Typ
Max
Units
Input or I/O Low
IIL
V
-2
-10
µA
Leakage Current
Input or I/O High
Leakage Current
IIH
2
10
40
Tri-state Output
IOZ
VO = VCC or GND
-40
µA
Off-state Current
Com.
Ind.
105
130
10
mA
mA
µA
Std Mode
Power Supply Current,
Standby
VCC = Max
VIN = 0, VCC
ICC1
Com.
Ind.
“L” Mode
10
µA
Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
ICC2
“PD” Mode
Std Power
1
10
mA
ma
Com
Ind
85
Current in Reduced-power
Mode
VCC = Max
VIN = 0, VCC
(2)
ICC3
105
Com.
Ind.
4.75
4.5
5.25
5.5
V
V
V
V
V
V
VCCIO
Supply Voltage
5.0V Device Output
3.3V Device Output
VCCIO
VIL
Supply Voltage
3.0
3.6
Input Low Voltage
Input High Voltage
-0.3
2.0
0.8
VIH
VCCIO + 0.3
0.45
Com.
Ind.
VIN = VIH or VIL
VCCIO = MIN, IOL = 12 mA
Output Low Voltage (TTL)
VOL
Com.
Ind.
.2
.2
V
V
VIN = VIH or VIL
VCC = MIN, IOL = 0.1 mA
Output Low Voltage (CMOS)
Output High Voltage (TTL)
VIN = VIH or VIL
VCCIO = MIN, IOH = -4.0 mA
VOH
2.4
V
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. When macrocell reduced-power feature is enabled.
Pin Capacitance
Typ
8
Max
10
Units
pF
Conditions
CIN
VIN = 0V; f = 1.0 MHz
VOUT = 0V; f = 1.0 MHz
CI/O
8
10
pF
Note:
Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
11
0950N–PLD–07/02
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias.................................. -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
AC Characteristics
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Input or Feedback to
Non-registered Output
tPD1
7.5
10
3
15
20
25
ns
I/O Input or Feedback to
Non-registered Feedback
tPD2
7
9
3
12
16
25
ns
tSU
tH
Global Clock Setup Time
Global Clock Hold Time
6
0
7
0
11
0
16
0
20
0
ns
ns
Global Clock Setup Time of
Fast Input
tFSU
tFH
3
3
3
3
5
2
ns
ns
Global Clock Hold Time of
Fast Input
0.5
0.5
1.0
1.5
tCOP
tCH
Global Clock to Output Delay
Global Clock High Time
Global Clock Low Time
Array Clock Setup Time
Array Clock Hold Time
Array Clock Output Delay
Array Clock High Time
Array Clock Low Time
4.5
7.5
5
8
10
20
13
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
2
4
4
3
3
5
5
4
4
6
6
4
5
7
7
5
6
tCL
tASU
tAH
tACOP
tACH
tACL
tCNT
10
15
3
3
4
4
6
6
8
8
10
10
Minimum Clock Global Period
8
8
10
10
13
13
17
17
22
22
Maximum Internal Global
Clock Frequency
fCNT
125
125
100
100
76.9
76.9
66
66
50
50
MHz
ns
tACNT
fACNT
Minimum Array Clock Period
Maximum Internal Array
Clock Frequency
MHz
12
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
AC Characteristics (Continued)
-7
-10
-15
-20
-25
Symbol
fMAX
tIN
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
MHz
ns
Maximum Clock Frequency
Input Pad and Buffer Delay
I/O Input Pad and Buffer Delay
Fast Input Delay
166.7
125
100
83.3
60
0.5
0.5
1
0.5
0.5
1
2
2
2
8
1
6
6
3
2
2
2
2
tIO
ns
tFIN
2
2
ns
tSEXP
tPEXP
tLAD
tLAC
Foldback Term Delay
Cascade Logic Delay
Logic Array Delay
4
5
10
1
12
1.2
8
ns
0.8
3
0.8
5
ns
7
ns
Logic Control Delay
3
5
7
8
ns
tIOE
Internal Output Enable Delay
2
2
3
4
ns
Output Buffer and Pad Delay
(Slow slew rate = OFF;
tOD1
tOD2
tOD3
2
2.5
5
1.5
2.0
5.5
4
5
8
5
6
6
7
ns
ns
ns
V
CCIO = 5V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = OFF;
V
CCIO = 3.3V; CL = 35 pF)
Output Buffer and Pad Delay
(Slow slew rate = ON;
10
10
V
CCIO = 5V or 3.3V; CL = 35 pF)
Note:
See ordering information for valid part numbers.
Timing Model
13
0950N–PLD–07/02
AC Characteristics (Continued)
-7
-10
-15
-20
-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Units
Output Buffer Enable Delay
(Slow slew rate = OFF;
tZX1
4.0
5.0
7
9
10
ns
V
CCIO = 5.0V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = OFF;
tZX2
4.5
5.5
7
9
10
ns
V
CCIO = 3.3V; CL = 35 pF)
Output Buffer Enable Delay
(Slow slew rate = ON;
tZX3
9
4
9
5
10
6
11
7
12
8
ns
ns
V
CCIO = 5.0V/3.3V; CL = 35 pF)
Output Buffer Disable Delay
(CL = 5 pF)
tXZ
tSU
Register Setup Time
Register Hold Time
3
2
3
3
4
4
2
2
5
5
2
2
6
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tH
tFSU
tFH
Register Setup Time of Fast Input
Register Hold Time of Fast Input
Register Delay
3
3
3
0.5
0.5
2.5
tRD
1
1
2
2
1
1
2
2
2
2
tCOMB
tIC
Combinatorial Delay
Array Clock Delay
3
5
6
7
8
tEN
Register Enable Time
Global Control Delay
Register Preset Time
Register Clear Time
Switch Matrix Delay
3
5
6
7
8
tGLOB
tPRE
tCLR
tUIM
tRPA
1
1
1
1
1
2
3
4
5
6
2
3
4
5
6
1
1
2
2
2
Reduced-power Adder(2)
10
11
13
14
15
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
Input Test Waveforms and Measurement Levels
tR, tF = 1.5 ns typical
14
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Output AC Test Loads
Note:
*Numbers in parenthesis refer to 3.0V operating conditions (preliminary).
Power-down Mode
The ATF1504AS includes an optional pin-controlled power-down feature. When this
mode is enabled, the PD pin acts as the power-down pin. When the PD pin is high, the
device supply current is reduced to less than 10 mA. During power-down, all output data
and internal logic states are latched internally and held. Therefore, all registered and
combinatorial output data remain valid. Any outputs that were in a high-Z state at the
onset will remain at high-Z. During power-down, all input signals except the power-down
pin are blocked. Input and I/O hold latches remain active to ensure that pins do not float
to indeterminate levels, further reducing system power. The power-down mode feature
is enabled in the logic design file or as a fitted or translated s/w option. Designs using
the power-down pin may not use the PD pin as a logic array input. However, all other PD
pin macrocell resources may still be used, including the buried feedback and foldback
product term array inputs.
Power Down AC Characteristics(1)(2)
-7
-10
-15
-20
-25
Symbol
tIVDH
Parameter
Min
7
Max
Min Max Min Max Min Max Min Max
Units
ns
Valid I, I/O before PD High
Valid OE(2) before PD High
Valid Clock(2) before PD High
I, I/O Don’t Care after PD High
OE(2) Don’t Care after PD High
Clock(2) Don’t Care after PD High
PD Low to Valid I, I/O
10
10
10
15
15
15
20
20
20
25
25
25
tGVDH
tCVDH
tDHIX
7
ns
7
ns
12
12
12
1
15
15
15
1
25
25
25
1
30
30
30
1
35
35
35
1
ns
tDHGX
tDHCX
tDLIV
ns
ns
µs
tDLGV
tDLCV
tDLOV
PD Low to Valid OE (Pin or Term)
PD Low to Valid Clock (Pin or Term)
PD Low to Valid Output
1
1
1
1
1
µs
1
1
1
1
1
µs
1
1
1
1
1
µs
Notes: 1. For slow slew outputs, add tSSO
.
2. Pin or product term.
3. Includes tRPA due to reduced power bit enabled.
15
0950N–PLD–07/02
JTAG-BST/ISP
Overview
The JTAG boundary-scan testing is controlled by the Test Access Port (TAP) controller
in the ATF1504AS. The boundary-scan technique involves the inclusion of a shift-regis-
ter stage (contained in a boundary-scan cell) adjacent to each component so that
signals at component boundaries can be controlled and observed using scan testing
principles. Each input pin and I/O pin has its own boundary-scan cell (BSC) in order to
support boundary scan testing. The ATF1504AS does not currently include a Test Reset
(TRST) input pin because the TAP controller is automatically reset at power-up. The five
JTAG modes supported include: SAMPLE/PRELOAD, EXTEST, BYPASS, IDCODE
and HIGHZ. The ATF1504AS’s ISP can be fully described using JTAG’s BSDL as
described in IEEE Standard 1149.1b. This allows ATF1504AS programming to be
described and implemented using any one of the third-party development tools support-
ing this standard.
The ATF1504AS has the option of using four JTAG-standard I/O pins for boundary-scan
testing (BST) and in-system programming (ISP) purposes. The ATF1504AS is program-
mable through the four JTAG pins using the IEEE standard JTAG programming protocol
established by IEEE Standard 1149.1 using 5V TTL-level programming signals from the
ISP interface for in-system programming. The JTAG feature is a programmable option.
If JTAG (BST or ISP) is not needed, then the four JTAG control pins are available as I/O
pins.
JTAG Boundary-scan The ATF1504AS contains up to 68 I/O pins and four input pins, depending on the device
type and package type selected. Each input pin and I/O pin has its own boundary-scan
Cell (BSC) Testing
cell (BSC) in order to support boundary-scan testing as described in detail by IEEE
Standard 1149.1. A typical BSC consists of three capture registers or scan registers and
up to two update registers. There are two types of BSCs, one for input or I/O pin, and
one for the macrocells. The BSCs in the device are chained together through the cap-
ture registers. Input to the capture register chain is fed in from the TDI pin while the
output is directed to the TDO pin. Capture registers are used to capture active device
data signals, to shift data in and out of the device and to load data into the update regis-
ters. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration for Input and I/O Pins (Except JTAG TAP Pins)
Note:
The ATF1504AS has pull-up option on TMS and TDI pins. This feature is selected as a design option.
16
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
BSC Configuration for Macrocell
Pin BSC
TDO
0
DQ
Pin
1
Capture
DR
Clock
TDI
Shift
TDO
OEJ
0
1
0
1
D Q
D Q
OUTJ
0
1
Pin
0
1
D Q
D Q
Capture
DR
Update
DR
Mode
TDI
Clock
Shift
Macrocell BSC
17
0950N–PLD–07/02
PCI Compliance
The ATF1504AS also supports the growing need in the industry to support the new
Peripheral Component Interconnect (PCI) interface standard in PCI-based designs and
specifications. The PCI interface calls for high current drivers, which are much larger
than the traditional TTL drivers. In general, PLDs and FPGAs parallel outputs to support
the high current load required by the PCI interface. The ATF1504AS allows this without
contributing to system noise while delivering low output-to-output skew. Having a pro-
grammable high drive option is also possible without increasing output delay or pin
capacitance. The PCI electrical characteristics appear on the next page.
PCI Voltage-to-current Curves for +5V Signaling in Pull-up Mode
Pull Up
VCC
Test Point
2.4
DC
drive point
1.4
AC drive
point
Current (mA)
-44
-2
-178
PCI Voltage-to-current Curves for +5V Signaling in Pull-down Mode
Pull Down
VCC
AC drive
point
2.2
DC
drive point
0.55
Test Point
Current (mA)
95
3,6
380
18
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
PCI DC Characteristics
Symbol
VCC
VIH
Parameter
Conditions
Min
4.75
2.0
Max
5.25
Units
V
Supply Voltage
Input High Voltage
Input Low Voltage
VCC + 0.5
0.8
V
VIL
-0.5
V
IIH
Input High Leakage Current
Input Low Leakage Current
Output High Voltage
Output Low Voltage
Input Pin Capacitance
CLK Pin Capacitance
IDSEL Pin Capacitance
Pin Inductance
VIN = 2.7V
70
µA
µA
V
IIL
VIN = 0.5V
-70
VOH
VOL
IOUT = -2 mA
IOUT = 3 mA, 6 mA
2.4
0.55
10
12
8
V
CIN
pF
pF
pF
nH
CCLK
CIDSEL
LPIN
20
Note:
Leakage current is with pin-keeper off.
PCI AC Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
mA
mA
mA
µA
0 < VOUT ≤ 1.4
1.4 < VOUT < 2.4
3.1 < VOUT < VCC
-44
Switching
-44+(VOUT - 1.4)/0.024
IOH(AC)
Current High
(Test High)
Equation A
-142
VOUT = 3.1V
VOUT > 2.2V
95
mA
mA
mA
mA
mA
V/ns
V/ns
Switching
2.2 > VOUT > 0
0.1 > VOUT > 0
VOUT/0.023
IOL(AC)
Current Low
(Test Point)
Equation B
206
VOUT = 0.71
ICL
Low Clamp Current
Output Rise Slew Rate
Output Fall Slew Rate
-5 < VIN ≤ -1
-25+(VIN + 1)/0.015
SLEWR
SLEWF
0.4V to 2.4V load
2.4V to 0.4V load
0.5
0.5
3
3
Notes: 1. Equation A: IOH = 11.9 (VOUT - 5.25) * (VOUT + 2.45) for VCC > VOUT > 3.1V.
2. Equation B: IOL = 78.5 * VOUT * (4.4 - VOUT) for 0V < VOUT < 0.71V.
19
0950N–PLD–07/02
ATF1504AS Dedicated Pinouts
44-lead
TQFP
44-lead
68-lead
J-lead
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
Dedicated Pin
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
J-lead
40
39
38
37
35
5, 19
1
2
2
1
2
1
92
91
90
89
1
44
68
84
90
88
INPUT/GCLK1
I/O /GCLK3
43
67
83
89
87
41
65
81
87
85
I/O/PD (1,2)
11, 25
7
17, 37
12
20, 46
14
14, 44
6
12, 42
4
I/O/TDI (JTAG)
I/O/TMS (JTAG)
I/O/TCK (JTAG)
I/O/TDO (JTAG)
7
13
19
23
17
15
26
32
32
50
62
64
62
38
57
71
75
73
6, 16, 26, 34,
38, 48, 58, 66
7, 19, 32, 42,
47, 59, 72, 82
13, 28, 40, 45,
61, 76, 88, 97
11, 26, 38, 43,
59, 74, 86, 95
GND
4, 16, 24, 36
9, 17, 29, 41
–
10, 22, 30, 42
3, 15, 23, 35
–
VCCINT
VCCIO
3, 35
3, 43
41, 93
39, 91
11, 21, 31, 43,
53, 63
13, 26, 38, 53,
66, 78
5, 20, 36, 53,
68, 84
3, 18, 34, 51,
66, 82
1, 2, 7, 9,
1, 2, 5, 7, 22,
24, 27, 28, 49,
50, 53, 55, 70,
72, 77, 78
24, 26, 29, 30,
51, 52, 55, 57,
72, 74, 79, 80
N/C
–
–
–
–
# of Signal Pins
36
32
36
32
52
48
68
64
68
64
68
64
# User I/O Pins
OE (1, 2)
Global OE Pins
GCLR
Global Clear Pin
Global Clock Pins
Power down pins
GCLK (1, 2, 3)
PD (1, 2)
TDI, TMS, TCK, TDO
GND
JTAG pins used for boundary-scan testing or in-system programming
Ground Pins
VCCINT
VCC pins for the device (+5V - Internal)
VCCIO
VCC pins for output drivers (for I/O pins) (+5V or 3.3V - I/Os)
20
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
ATF1504AS I/O Pinouts
44-
44-
68-
84-
lead
100-
lead
PQFP
100-
lead
TQFP
44-
lead
44-
lead
68-
lead
84-
lead
100-
lead
PQFP
100-
lead
TQFP
lead
lead
lead
MC
1
PLC PLCC TQFP PLCC PLCC
MC
33
PLC
C
PLCC TQFP PLCC PLCC
A
A
12
6
18
22
21
16
15
14
13
24
18
36
44
45
42
43
40
41
2
–
–
–
34
C
–
–
–
A/
PD1
C/
PD2
3
11
5
17
20
14
12
35
25
19
37
46
44
42
4
5
6
7
A
A
A
A
9
8
–
–
3
2
–
–
15
14
13
–
18
17
16
15
12
11
10
8
10
9
36
37
38
39
C
C
C
C
26
27
–
20
21
–
39
40
41
–
48
49
50
51
46
47
48
49
44
45
46
47
8
6
–
–
8/
TDI
A
7
1
12
14
6
4
40
C
28
22
42
52
50
48
9
A
A
A
A
A
A
A
–
–
6
–
–
5
–
–
–
10
–
12
11
10
9
4
3
100
99
98
97
96
94
93
41
42
43
44
45
46
47
C
C
C
C
C
C
C
29
–
23
–
44
–
54
55
56
57
58
60
61
54
56
58
59
60
62
63
52
54
56
57
58
60
61
10
11
12
13
14
15
44
–
9
100
99
98
96
95
–
–
45
46
47
49
–
8
–
–
–
7
8
–
–
43
–
5
6
31
–
25
–
–
5
48/
TCK
16
A
4
42
4
4
94
92
C
32
26
50
62
64
62
17
18
19
20
21
22
23
B
B
B
B
B
B
B
21
–
15
–
33
–
41
40
39
37
36
35
34
39
38
37
35
34
33
32
37
36
35
33
32
31
30
49
50
51
52
53
54
55
D
D
D
D
D
D
D
33
–
27
–
51
–
63
64
65
67
68
69
70
65
66
67
69
70
71
73
63
64
65
67
68
69
71
20
19
18
–
14
13
12
–
32
30
29
28
–
34
36
37
–
28
30
31
–
52
54
55
56
–
–
–
–
–
56/
TDO
24
B
17
11
27
33
31
29
D
38
32
57
71
75
73
25
26
27
28
29
30
31
B
B
B
B
B
B
B
16
–
10
–
25
–
31
30
29
28
27
25
24
27
25
23
22
21
19
18
25
23
21
20
19
17
16
57
58
59
60
61
62
63
D
D
D
D
D
D
D
39
–
33
–
59
–
73
74
75
76
77
79
80
77
78
81
82
83
85
86
75
76
79
80
81
83
84
–
–
24
23
22
20
–
–
–
60
61
62
64
–
–
–
–
–
–
–
–
–
14
–
8
40
–
34
–
–
32/
TMS
D/
GCLK3
B
13
7
19
23
17
15
64
41
35
65
81
87
85
21
0950N–PLD–07/02
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(TA = 25°C, F = 0)
125
100
75
50
25
0
1100
1000
900
STANDARD
STANDARD POWER
800
REDUCED POWER MODE
REDUCED POWER MODE
700
4.50
4.75
5.00
5.25
5.50
4.50
4.75
5.00
5.25
5.50
V
CC (V)
VCC (V)
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
LOW POWER (TA = 25°C)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW-POWER ("L") VERSION
(TA = 25°C, F = 0)
125.0
100.0
75.0
50.0
25.0
0.0
30
20
10
0
STANDARD POWER
REDUCED POWER MODE
0.00
5.00
10.00
15.00
20.00
25.00
4.50
4.75
5.00
5.25
5.50
FREQUENCY (MHz)
V
CC (V)
OUTPUT SOURCE CURRENT VS. OUTPUT VOLTAGE
(VCC = 5V, TA = 25°C)
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-70.0
-80.0
-90.0
-100.0
200.0
150.0
100.0
50.0
STANDARD POWER
REDUCED POWER MODE
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
0.00
20.00
40.00
60.00
80.00
100.00
OUTPUT VOLTAGE (V)
FREQUENCY (MHz)
INPUT CLAMP CURRENT VS. INPUT VOLTAGE
OUTPUT SOURCE CURRENT VS. SUPPLY VOLTAGE
(VCC = 5V, TA = 25°C)
(VOH = 2.4V, TA = 25°C)
0
-10
-20
-30
-40
-50
-60
0.0
-10.0
-20.0
-30.0
-40.0
-50.0
-60.0
-1.00
-0.80
-0.60
-0.40
-0.20
0.00
4.50
4.75
5.00
5.25
5.50
INPUT VOLTAGE (V)
SUPPLY VOLTAGE (V)
22
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
OUTPUT SINK CURRENT VS. SUPPLY VOLTAGE
NORMALIZED TPD
VS. TEMPERATURE (VCC = 5.0V)
(VOL = 0.5V, TA = 25°C)
43
42
41
40
39
38
37
36
35
34
1.2
1.1
1.0
0.9
0.8
4.50
4.75
5.00
5.25
5.50
SUPPLY VOLTAGE (V)
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
NORMALIZED TPD
VS. SUPPLY VOLTAGE (TA = 25°C)
1.20
1.10
1.00
0.90
0.80
NORMALIZED TCO
VS. SUPPLY VOLTAGE (TA = 25°C)
1.2
1.1
1.0
0.9
0.8
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
4.5
4.8
5.0
5.3
5.5
SUPPLY VOLTAGE (V)
INPUT CURRENT VS. INPUT VOLTAGE
(VCC = 5V, TA = 25°C)
40
30
20
10
0
NORMALIZED TSU
VS. SUPPLY VOLTAGE (TA = 25°C)
1.2
1.1
1.0
0.9
0.8
-10
-20
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
INPUT VOLTAGE (V)
4.5
4.8
5.0
5.3
5.5
OUTPUT SINK CURRENT VS. OUTPUT VOLTAGE
SUPPLY VOLTAGE (V)
(VCC = 5V, TA = 25°C)
140.0
120.0
100.0
80.0
60.0
40.0
20.0
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
OUTPUT VOLTAGE (V)
23
0950N–PLD–07/02
NORMALIZED TCO
VS.TEMPERATURE (VCC = 5.0V)
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
NORMALIZED TSU
VS. TEMPERATURE (VCC = 5.0V)
1.2
1.1
1.0
0.9
0.8
-40.0
0.0
25.0
75.0
TEMPERATURE (C)
24
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
ATF1504AS Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
7.5
10
10
15
15
4.5
166.7
ATF1504AS-7 AC44
ATF1504AS-7 JC44
ATF1504AS-7 JC68
ATF1504AS-7 JC84
ATF1504AS-7 QC100
ATF1504AS-7 AC100
44A
Commercial
44J
(0°C to 70°C)
68J
84J
100Q1
100A
5
125
ATF1504AS-10 AC44
ATF1504AS-10 JC44
ATF1504AS-10 JC68
ATF1504AS-10 JC84
ATF1504AS-10 QC100
ATF1504AS-10 AC100
44A
Commercial
44J
(0°C to 70°C)
68J
84J
100Q1
100A
5
125
ATF1504AS-10 AI44
ATF1504AS-10 JI44
ATF1504AS-10 JI68
ATF1504AS-10 JI84
ATF1504AS-10 QI100
ATF1504AS-10 AI100
44A
Industrial
44J
(-40°C to +85°C)
68J
84J
100Q1
100A
8
100
ATF1504AS-15 AC44
ATF1504AS-15 JC44
ATF1504AS-15 JC68
ATF1504AS-15 JC84
ATF1504AS-15 QC100
ATF1500AS-15 AC100
44A
Commercial
44J
(0°C to 70°C)
68J
84J
100Q1
100A
8
100
ATF1504AS-15 AI44
ATF1504AS-15 JI44
ATF1504AS-15 JI68
ATF1504AS-15 JI84
ATF1504AS-15 QI100
ATF1504AS-15 AI100
44A
Industrial
44J
(-40°C to +85°C)
68J
84J
100Q1
100A
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
25
0950N–PLD–07/02
ATF1504ASL Ordering Information
tPD
tCO1
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
20
12
83.3
ATF1504ASL-20 AC44
ATF1504ASL-20 JC44
ATF1504ASL-20 JC68
ATF1504ASL-20 JC84
ATF1504ASL-20 QC100
ATF1504ASL-20 AC100
44A
Commercial
44J
(0°C to 70°C)
68J
84J
100Q1
100A
25
15
70
ATF1504ASL-25 AI44
ATF1504ASL-25 JI84
ATF1504ASL-25 JI68
ATF1504ASL-25 JI84
ATF1504ASL-25 QI100
ATF1504ASL-25 AI100
44A
Industrial
44J
(-40°C to +85°C)
68J
84J
100Q1
100A
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
26
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
Packaging Information
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
27
0950N–PLD–07/02
44J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
44J
B
R
28
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
68J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
25.019
24.130
25.019
24.130
–
25.273
D1
E
–
24.333 Note 2
25.273
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AE.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
24.333 Note 2
23.622
D2/E2 22.606
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
68J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
68J, 68-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
29
0950N–PLD–07/02
84J – PLCC
1.14(0.045) X 45˚
PIN NO. 1
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
30.099
29.210
30.099
29.210
–
30.353
D1
E
–
29.413 Note 2
30.353
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
29.413 Note 2
28.702
D2/E2 27.686
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC)
84J
B
R
30
ATF1504AS(L)
0950N–PLD–07/02
ATF1504AS(L)
100Q1 – PQFP
Dimensions in Millimeters and (Inches)*
*Controlling dimensions: millimeters
JEDEC STANDARD MS-022, GC-1
17.45 (0.687)
16.95 (0.667)
PIN 1 ID
PIN 1
20.10 (0.791)
19.90 (0.783)
0.65 (0.0256) BSC
0.40 (0.016)
0.22 (0.009)
23.45 (0.923)
22.95 (0.904)
14.12 (0.556)
13.90 (0.547)
3.40 (0.134) MAX
0.23 (0.009)
0.11 (0.004)
0º~7º
1.03 (0.041)
0.73 (0.029)
0.50 (0.020)
0.25 (0.010)
04/11/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch,
Plastic Quad Flat Package (PQFP)
100Q1
A
R
31
0950N–PLD–07/02
100A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
14.10 Note 2
0.27
C
–
0.20
3. Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
C
R
32
ATF1504AS(L)
0950N–PLD–07/02
Atmel Headquarters
Atmel Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
TEL (49) 71-31-67-0
FAX (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131
TEL 1(408) 441-0311
FAX 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
FAX 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
TEL (41) 26-426-5555
FAX (41) 26-426-5500
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
TEL (33) 2-40-18-18-18
FAX (33) 2-40-18-19-60
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
BP 123
38521 Saint-Egreve Cedex, France
TEL (33) 4-76-58-30-00
FAX (33) 4-76-58-34-80
ASIC/ASSP/Smart Cards
Zone Industrielle
Hong Kong
TEL (852) 2721-9778
FAX (852) 2722-1369
13106 Rousset Cedex, France
TEL (33) 4-42-53-60-00
FAX (33) 4-42-53-60-01
Japan
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL 1(719) 576-3300
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
FAX 1(719) 540-1759
TEL (81) 3-3523-3551
FAX (81) 3-3523-7581
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
TEL (44) 1355-803-000
FAX (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
© Atmel Corporation 2002.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATMEL® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0950N–PLD–07/02
xM
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