ATMEGA644PA-MN [MICROCHIP]
IC MCU 8BIT 64KB FLASH 44VQFN;
| 型号： | ATMEGA644PA-MN |
| 厂家： | 
MICROCHIP |
| 描述： | IC MCU 8BIT 64KB FLASH 44VQFN 时钟 外围集成电路 装置 |
| 文件： | 总17页 (文件大小：365K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8-bit AVR Microcontrollers
ATmega644PA
DATASHEET SUMMARY
Introduction
The Atmel® picoPower® ATmega644PA is a low-power CMOS 8-bit
®
microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega644PA
achieves throughputs close to 1MIPS per MHz. This empowers system
designer to optimize the device for power consumption versus processing
speed.
Feature
®
®
High Performance, Low Power Atmel AVR 8-Bit Microcontroller Family
• Advanced RISC Architecture
–
–
–
–
–
–
131 Powerful Instructions
Most Single Clock Cycle Execution
32 x 8 General Purpose Working Registers
Fully Static Operation
Up to 20 MIPS Throughput at 20MHz
On-chip 2-cycle Multiplier
•
High Endurance Non-volatile Memory Segments
–
64KBytes of In-System Self-Programmable Flash Program
Memory
–
–
–
–
–
2KBytes EEPROM
4KBytes Internal SRAM
Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
Data Retention: 20 Years at 85°C/100 Years at 25°C(1)
Optional Boot Code Section with Independent Lock Bits
•
•
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
–
Programming Lock for Software Security
®
•
Atmel QTouch Library Support
–
–
–
Capacitive Touch Buttons, Sliders and Wheels
QTouch and QMatrix acquisition
Up to 64 Sense Channels
Atmel-42717C-ATmega644PA_Datasheet_Summary-10/2016
•
•
JTAG (IEEE std. 1149.1 Compliant) Interface
–
–
–
Boundary-scan Capabilities According to the JTAG Standard
Extensive On-chip Debug Support
Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
Peripheral Features
–
–
–
–
–
Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
Real Time Counter with Separate Oscillator
Six PWM Channels
8-channel 10-bit ADC
•
Differential Mode with Selectable Gain at 1×, 10× or 200×
–
–
–
–
–
–
One Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
Two Programmable Serial USART
One Master/Slave SPI Serial Interface
Programmable Watchdog Timer with Separate On-chip Oscillator
On-chip Analog Comparator
Interrupt and Wake-up on Pin Change
•
•
Special Microcontroller Features
–
–
–
–
Power-on Reset and Programmable Brown-out Detection
Internal Calibrated RC Oscillator
External and Internal Interrupt Sources
Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
I/O and Packages
–
–
–
–
32 Programmable I/O Lines
40-pin PDIP
44-lead TQFP
44-pad VQFN/QFN
•
•
Operating Voltage:
1.8 - 5.5V
Speed Grades
–
–
–
–
0 - 4MHz @ 1.8V - 5.5V
0 - 10MHz @ 2.7V - 5.5V
0 - 20MHz @ 4.5 - 5.5V
•
Power Consumption at 1MHz, 1.8V, 25°C
–
–
–
Active Mode: 0.4mA
Power-down Mode: 0.1μA
Power-save Mode: 0.6μA (Including 32kHz RTC)
Note:ꢀ
1. Refer to Data Retention
Related Links
Data Retention on page 13
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Table of Contents
Introduction......................................................................................................................1
Feature............................................................................................................................ 1
1. Description.................................................................................................................4
2. Configuration Summary.............................................................................................5
3. Ordering Information .................................................................................................6
4. Block Diagram........................................................................................................... 7
5. Pin Configurations..................................................................................................... 8
5.1. Pinout........................................................................................................................................... 8
5.2. Pin Descriptions............................................................................................................................9
6. I/O Multiplexing........................................................................................................ 11
7. General Information.................................................................................................13
7.1. Resources.................................................................................................................................. 13
7.2. Data Retention............................................................................................................................13
7.3. About Code Examples................................................................................................................13
7.4. Capacitive Touch Sensing..........................................................................................................13
8. Packaging Information.............................................................................................14
8.1. 40-pin PDIP................................................................................................................................14
8.2. 44-pin TQFP...............................................................................................................................15
8.3. 44-pin VQFN...............................................................................................................................16
1.
Description
®
The Atmel ATmega644PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega644PA achieves
throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
®
The Atmel AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega644PA provides the following features: 64Kbytes of In-System Programmable Flash with
Read-While-Write capabilities, 2Kbytes EEPROM, 4Kbytes SRAM, 32 general purpose I/O lines, 32
general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare
modes and PWM, two serial programmable USARTs , one byte-oriented 2-wire Serial Interface (I2C), a 8-
channel 10-bit ADC with optional differential input stage with programmable gain, a programmable
Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test
interface, also used for accessing the On-chip Debug system and programming and six software
selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode, both the
main oscillator and the asynchronous timer continue to run.
®
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
®
™
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression (AKS )
technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you
to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega644PA is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega644PA is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.
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2.
Configuration Summary
The table below compares the device series of feature and pin compatible devices, providing a seamless
migration path.
Table 2-1.ꢀConfiguration Summary and Device Comparison
Features
ATmega164PA
ATmega324PA
ATmega644PA
ATmega1284P
Pin Count
40/44/49
16K
1K
40/44/49
32K
2K
40/44
64K
4K
40/44
128K
16K
4K
Flash (Bytes)
SRAM (Bytes)
EEPROM (Bytes)
512
1K
2K
General Purpose
I/O Lines
32
32
32
32
SPI
1
1
1
1
TWI (I2C)
USART
1
1
1
1
2
2
2
2
ADC
10-bit 15ksps
10-bit 15ksps
10-bit 15ksps
10-bit 15ksps
ADC Channels
Analog Comparator
8
1
2
8
1
2
8
1
2
8
1
2
8-bit Timer/
Counters
16-bit Timer/
Counters
1
1
1
2
PWM channels
Packages
6
6
6
8
PDIP
PDIP
PDIP
PDIP
TQFP
TQFP
TQFP
TQFP
VQFN/QFN
DRQFN
VFBGA
VQFN/QFN
DRQFN
VFBGA
VQFN/QFN
VQFNQFN
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3.
Ordering Information
Speed [MHz](3)
Power Supply [V]
Ordering Code(2)
Package(1)
Operational Range
20
1.8 - 5.5
Industrial
(-40°C to 85°C)
ATmega644PA-AU
ATmega644PA-AUR(4)
ATmega644PA-PU
ATmega644PA-MU
ATmega644PA-MUR(4)
44A
44A
40P6
44M1
44M1
20
1.8 - 5.5
Industrial
(-40°C to 105°C)
ATmega644PA-AN
ATmega644PA-ANR(4)
ATmega644PA-PN
ATmega644PA-MN
ATmega644PA-MNR(4)
44A
44A
40P6
44M1
44M1
Note:ꢀ
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
Package Type
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-
Lead (VQFN)
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4.
Block Diagram
Figure 4-1.ꢀBlock Diagram
SRAM
TCK
TMS
TDI
JTAG
CPU
TDO
OCD
Clock generation
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
I/O
PORTS
TOSC1
I
N
/
O
U
T
8MHz
Calib RC
NVM
programming
32.768kHz
XOSC
FLASH
TOSC2
XTAL1
128kHz int
osc
16MHz LP
XOSC
Power
management
and clock
control
GPIOR[2:0]
External
clock
XTAL2
D
A
T
D
A
T
EEPROM
T0
OC0A
OC0B
TC 0
(8-bit)
A
B
U
S
A
B
U
S
MISO
MOSI
SCK
SS
VCC
EEPROMIF
SPI
AC
Power
Watchdog
Timer
Supervision
POR/BOD &
RESET
RESET
GND
AIN0
AIN1
ACO
ADCMUX
Internal
Reference
ADC[7:0]
AREF
ADC
RxD0
TxD0
XCK0
PCINT[31:0]
INT[2:0]
EXTINT
USART 0
USART 1
TWI
OC1A/B
T1
ICP1
RxD1
TxD1
XCK1
TC 1
(16-bit)
SDA
SCL
OC2A
OC2B
TC 2
(8-bit async)
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5.
Pin Configurations
5.1.
Pinout
5.1.1.
PDIP
(PCINT8/XCK0/T0)
(PCINT9/CLKO/T1)
(PCINT10/INT2/AIN0)
(PCINT11/OC0A/AIN1)
(PCINT12/OC0B/
(ADC0/PCINT0)
(ADC1/PCINT1)
(ADC2/PCINT2)
(ADC3/PCINT3)
(ADC4/PCINT4)
(PCINT13/MOSI)
(ADC5/PCINT5)
(ADC6/PCINT6)
(ADC7/PCINT7)
(PCINT14/MISO)
(PCINT15//SCK)
(TOSC2/PCINT23)
(TOSC1/PCINT22)
(TDI/PCINT21)
(TDO/PCINT20)
(TMS/PCINT19)
(TCK/PCINT18)
(SDA/PCINT17)
(SCL/PCINT16)
(OC2A/PCINT31)
XTAL2
XTAL1
(PCINT24/RXD0)
(PCINT25/TXD0)
(PCINT26/RXD1/INT0)
(PCINT27/TXD1/INT1)
(PCINT28/XCK1/OC1B)
(PCINT29/OC1A)
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
(PCINT30/OC2B/ICP1)
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5.1.2.
TQFN and QFN
Power
Ground
Programming/debug
Digital
Analog
Crystal/Osc
1
2
33
32
31
30
29
28
27
26
25
24
23
(PCINT13/MOSI) PB5
(PCINT14/MISO) PB6
(PCINT15/SCK) PB7
RESET
PA4 (ADC4/PCINT4)
PA5 (ADC5/PCINT5)
PA6 (ADC6/PCINT6)
PA7 (ADC7/PCINT7)
AREF
3
4
5
VCC
6
GND
GND
7
XTAL2
AVCC
8
XTAL1
PC7 (TOSC2/PCINT23)
PC6 (TOSC1/PCINT22)
PC5 (TDI/PCINT21)
PC4 (TDO/PCINT20)
9
(PCINT24/RXD0) PD0
(PCINT25/TXD0) PD1
(PCINT26/RXD1/INT0) PD2
10
11
5.2.
Pin Descriptions
5.2.1.
VCC
Digital supply voltage.
5.2.2.
5.2.3.
GND
Ground.
Port A (PA[7:0])
This port serves as analog inputs to the Analog-to-digital Converter.
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This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.2.4.
5.2.5.
5.2.6.
5.2.7.
Port B (PB[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of various special features.
Port C (PC[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of the JTAG interface, along with special features.
Port D (PD[7:0])
This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
This port also serves the functions of various special features.
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset.
5.2.8.
5.2.9.
XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
XTAL2
Output from the inverting Oscillator amplifier.
5.2.10. AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter.
5.2.11. AREF
This is the analog reference pin for the Analog-to-digital Converter.
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6.
I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1.ꢀPORT Function Multiplexing
32-pin TQFP/ QFN/ MLF Pin # 40-pin PDIP Pin # PAD
EXTINT PCINT
PCINT13
ADC/AC OSC
T/C # 0 T/C # 1 USART I2C
SPI
JTAG
1
6
PB[5]
PB[6]
PB[7]
RESET
VCC
MOSI
MISO
SCK
2
7
PCINT14
PCINT15
3
8
4
9
5
10
11
12
13
14
15
16
17
18
19
20
21
-
6
GND
7
XTAL2
XTAL1
PD[0]
PD[1]
PD[2]
PD[3]
PD[4]
PD[5]
PD[6]
PD[7]
VCC
8
9
PCINT24
PCINT25
PCINT26
PCINT27
PCINT28
PCINT29
PCINT30
PCINT31
RxD0
TxD0
RxD1
TXD1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
INT0
INT1
OC1B
OC1A
ICP1
XCK1
OC2B
OC2A
RxD2
TxD2
MISO1
MOSI1
-
GND
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
PC[0]
PC[1]
PC[2]
PC[3]
PC[4]
PC[5]
PC[6]
PC[7]
AVCC
GND
PCINT16
PCINT17
PCINT18
PCINT19
PCINT20
PCINT21
PCINT22
PCINT23
SCL
SDA
TCK
TMS
TDO
TDI
TOSC1
TOSC2
AREF
PA[7]
PA[6]
PA[5]
PA[4]
PA[3]
AREF
ADC7
ADC6
ADC5
ADC4
ADC3
PCINT7
PCINT6
PCINT5
PCINT4
PCINT3
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32-pin TQFP/ QFN/ MLF Pin # 40-pin PDIP Pin # PAD
EXTINT PCINT
PCINT2
ADC/AC OSC
ADC2
T/C # 0 T/C # 1 USART I2C
SPI
JTAG
35
36
37
38
39
40
41
42
43
44
-
38
39
40
-
PA[2]
PA[1]
PA[0]
VCC
GND
PB[0]
PB[1]
PB[2]
PB[3]
PB[4]
GND
GND
GND
GND
GND
PCINT1
ADC1
PCINT0
ADC0
SDA1
SCL1
-
1
2
3
4
5
-
PCINT8
PCINT9
T0
XCK0
CLKO
T1
INT2
PCINT10 AIN0
PCINT11 AIN1
PCINT12
OC0A
OC0B
SS
-
-
-
-
-
-
-
-
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7.
General Information
7.1.
Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.atmel.com/avr.
7.2.
7.3.
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
7.4.
Capacitive Touch Sensing
7.4.1.
QTouch Library
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive interfaces on
most Atmel AVR® microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel
QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location: http://
www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.
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8.
Packaging Information
8.1.
40-pin PDIP
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
0º ~ 15º REF
C
MIN
–
MAX
4.826
–
NOM
NOTE
SYMBOL
eB
A
–
A1
D
0.381
52.070
15.240
13.462
0.356
1.041
3.048
0.203
15.494
–
–
52.578 Note 2
15.875
E
–
E1
B
–
13.970 Note 2
0.559
–
B1
L
–
1.651
–
3.556
Notes:
1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010").
C
–
–
0.381
eB
e
17.526
2.540 TYP
13/02/2014
40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual
Inline Package (PDIP)
C
40P6
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8.2.
44-pin TQFP
PIN 1 IDENTIFIER
PIN 1
B
e
E1
E
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
–
0.15
1.00
1.05
12.00
10.00
12.00
10.00
0.37
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
(0.17)
0.60
0.20
3. Lead coplanarity is 0.10mm maximum.
L
0.75
e
0.80 TYP
06/02/2014
44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,
0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)
44A
C
Atmel ATmega644PA [DATASHEET]
15
Atmel-42717C-ATmega644PA_Datasheet_Summary-10/2016
8.3.
44-pin VQFN
D
Marked Pin# 1 I D
E
SE ATING PLANE
A1
A3
TOP VIEW
A
K
L
Pin #1 Co rne r
SIDE VIEW
D2
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
3
MIN
0.80
–
MAX
1.00
NOM
0.90
NOTE
SYMBOL
A
E2
Option B
Option C
A1
A3
b
0.02
0.05
Pin #1
Cham fer
(C 0.30)
0.20 REF
0.23
0.18
6.90
5.00
6.90
0.30
7.10
5.40
7.10
D
7.00
D2
E
5.20
K
Pin #1
Notch
(0.20 R)
e
b
7.00
E2
e
5.00
5.20
0.50 BSC
0.64
5.40
BOTTOM VIEW
L
0.59
0.20
0.69
0.41
Note : JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 .
K
0.26
9/26/08
GPC
ZWS
DRAWING NO.
TITLE
REV.
44M1,44-pad, 7 x 7 x 1.0mm body, lead
pitch 0.50mm, 5.20mm exposed pad, thermally
enhanced plastic very thin quad flat no
lead package (VQFN)
Package Drawing Contact:
avr@atmel.com
44M1
H
Atmel ATmega644PA [DATASHEET]
16
Atmel-42717C-ATmega644PA_Datasheet_Summary-10/2016
Atmel Corporation
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2016 Atmel Corporation. / Rev.: Atmel-42717C-ATmega644PA_Datasheet_Summary-10/2016
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