ATMEGA88PA-MMNR中文资料_数据手册_规格书

Atmel 8-bit Microcontroller with 4/8/16/32KBytes In-

System Programmable Flash

ATmega48A; ATmega48PA; ATmega88A; ATmega88PA;

ATmega168A; ATmega168PA; ATmega328; ATmega328P

SUMMARY

Features

• High Performance, Low Power Atmel^®AVR^®8-Bit Microcontroller Family

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20MHz

– On-chip 2-cycle Multiplier

• High Endurance Non-volatile Memory Segments

– 4/8/16/32KBytes of In-System Self-Programmable Flash program memory

– 256/512/512/1KBytes EEPROM

– 512/1K/1K/2KBytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM

– Data retention: 20 years at 85C/100 years at 25C⁽¹⁾

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

• Atmel^®QTouch^®library support

– Capacitive touch buttons, sliders and wheels

– QTouch and QMatrix^®acquisition

– Up to 64 sense channels

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel 10-bit ADC in TQFP and QFN/MLF package

Temperature Measurement

– 6-channel 10-bit ADC in PDIP Package

Temperature Measurement

– Programmable Serial USART

– Master/Slave SPI Serial Interface

– Byte-oriented 2-wire Serial Interface (Philips I²C compatible)

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 23 Programmable I/O Lines

– 28-pin PDIP, 32-lead TQFP, 28-pad QFN/MLF and 32-pad QFN/MLF

• Operating Voltage:

– 1.8 - 5.5V

• Temperature Range:

– -40C to 85C

• Speed Grade:

– 0 - 4MHz@1.8 - 5.5V, 0 - 10MHz@2.7 - 5.5.V, 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1MHz, 1.8V, 25C

– Active Mode: 0.2mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.75µA (Including 32kHz RTC)

8271GS–AVR–02/2013

1. Pin Configurations

Figure 1-1. Pinout ATmega48A/PA/88A/PA/168A/PA/328/P

28 PDIP

32 TQFP Top View

(PCINT14/RESET) PC6

(PCINT16/RXD) PD0

(PCINT17/TXD) PD1

(PCINT18/INT0) PD2

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

1

28 PC5 (ADC5/SCL/PCINT13)

27 PC4 (ADC4/SDA/PCINT12)

26 PC3 (ADC3/PCINT11)

25 PC2 (ADC2/PCINT10)

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 GND

2

3

4

5

6

7

8

9

(PCINT19/OC2B/INT1) PD3

1

2

3

4

5

6

7

8

24 PC1 (ADC1/PCINT9)

23 PC0 (ADC0/PCINT8)

22 ADC7

(PCINT20/XCK/T0) PD4

GND

VCC

GND

21 GND

20 AREF

GND

21 AREF

VCC

19 ADC6

(PCINT6/XTAL1/TOSC1) PB6

20 AVCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

18 AVCC

(PCINT7/XTAL2/TOSC2) PB7 10

(PCINT21/OC0B/T1) PD5 11

(PCINT22/OC0A/AIN0) PD6 12

(PCINT23/AIN1) PD7 13

19 PB5 (SCK/PCINT5)

18 PB4 (MISO/PCINT4)

17 PB3 (MOSI/OC2A/PCINT3)

16 PB2 (SS/OC1B/PCINT2)

15 PB1 (OC1A/PCINT1)

17 PB5 (SCK/PCINT5)

(PCINT0/CLKO/ICP1) PB0 14

32 MLF Top View

28 MLF Top View

(PCINT19/OC2B/INT1) PD3

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

ADC7

1

2

3

4

5

6

7

8

24

23

22

21

20

19

18

17

(PCINT19/OC2B/INT1) PD3

(PCINT20/XCK/T0) PD4

VCC

PC2 (ADC2/PCINT10)

PC1 (ADC1/PCINT9)

PC0 (ADC0/PCINT8)

GND

1

2

3

4

5

6

7

21

20

19

18

17

16

15

(PCINT20/XCK/T0) PD4

GND

VCC

GND

AREF

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

(PCINT21/OC0B/T1) PD5

AREF

VCC

ADC6

AVCC

(PCINT6/XTAL1/TOSC1) PB6

(PCINT7/XTAL2/TOSC2) PB7

AVCC

PB5 (SCK/PCINT5)

NOTE: Bottom pad should be soldered to ground.

Table 1-1.

32UFBGA - Pinout ATmega48A/48PA/88A/88PA/168A/168PA

1

2

3

4

5

6

A

B

C

D

E

F

PD2

PD3

GND

VDD

PB6

PB7

PD1

PD4

GND

VDD

PD6

PD5

PC6

PD0

PC4

PC5

PC2

PC1

PC0

GND

ADC6

PB5

PB4

PC3

ADC7

AREF

AVDD

PB3

PB0

PD7

PB2

PB1

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

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8271GS–AVR–02/2013

1.1

Pin Descriptions

1.1.1

VCC

Digital supply voltage.

1.1.2

1.1.3

GND

Ground.

Port B (PB7:0) XTAL1/XTAL2/TOSC1/TOSC2

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

Depending on the clock selection fuse settings, PB6 can be used as input to the inverting Oscillator amplifier and

input to the internal clock operating circuit.

Depending on the clock selection fuse settings, PB7 can be used as output from the inverting Oscillator amplifier.

If the Internal Calibrated RC Oscillator is used as chip clock source, PB7...6 is used as TOSC2...1 input for the

Asynchronous Timer/Counter2 if the AS2 bit in ASSR is set.

The various special features of Port B are elaborated in ”Alternate Functions of Port B” on page 83 and ”System

Clock and Clock Options” on page 26.

1.1.4

1.1.5

Port C (PC5:0)

Port C is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The PC5...0 output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

PC6/RESET

If the RSTDISBL Fuse is programmed, PC6 is used as an I/O pin. Note that the electrical characteristics of PC6 dif-

fer from those of the other pins of Port C.

If the RSTDISBL Fuse is unprogrammed, PC6 is used as a Reset input. A low level on this pin for longer than the

minimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given in

Table 29-12 on page 310. Shorter pulses are not guaranteed to generate a Reset.

The various special features of Port C are elaborated in ”Alternate Functions of Port C” on page 86.

1.1.6

1.1.7

Port D (PD7:0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf-

fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are

externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a

reset condition becomes active, even if the clock is not running.

The various special features of Port D are elaborated in ”Alternate Functions of Port D” on page 89.

AV_CC

AV_CCis the supply voltage pin for the A/D Converter, PC3:0, and ADC7:6. It should be externally connected to V_CC

,

even if the ADC is not used. If the ADC is used, it should be connected to V_CCthrough a low-pass filter. Note that

PC6...4 use digital supply voltage, V_CC

.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

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8271GS–AVR–02/2013

1.1.8

1.1.9

AREF

AREF is the analog reference pin for the A/D Converter.

ADC7:6 (TQFP and QFN/MLF Package Only)

In the TQFP and QFN/MLF package, ADC7:6 serve as analog inputs to the A/D converter. These pins are powered

from the analog supply and serve as 10-bit ADC channels.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

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8271GS–AVR–02/2013

2. Overview

The ATmega48A/PA/88A/PA/168A/PA/328/P is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

ATmega48A/PA/88A/PA/168A/PA/328/P achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

Watchdog

Timer

Power

Supervision

POR / BOD &

RESET

debugWIRE

Watchdog

Oscillator

PROGRAM

LOGIC

Oscillator

Circuits /

Clock

Flash

SRAM

Generation

CPU

EEPROM

AVCC

AREF

GND

2

8bit T/C 0

8bit T/C 2

16bit T/C 1

A/D Conv.

Analog

Comp.

Internal

Bandgap

6

USART 0

PORT D (8)

PD[0..7]

SPI

PORT B (8)

PB[0..7]

TWI

PORT C (7)

PC[0..6]

RESET

XTAL[1..2]

ADC[6..7]

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are

directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one

single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving

throughputs up to ten times faster than conventional CISC microcontrollers.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

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8271GS–AVR–02/2013

The ATmega48A/PA/88A/PA/168A/PA/328/P provides the following features: 4K/8Kbytes of In-System Program-

mable Flash with Read-While-Write capabilities, 256/512/512/1Kbytes EEPROM, 512/1K/1K/2Kbytes SRAM,

23 general purpose I/O lines, 32 general purpose working registers, three flexible Timer/Counters with compare

modes, internal and external interrupts, a serial programmable USART, a byte-oriented 2-wire Serial Interface, an

SPI serial port, a 6-channel 10-bit ADC (8 channels in TQFP and QFN/MLF packages), a programmable Watchdog

Timer with internal Oscillator, and five software selectable power saving modes. The Idle mode stops the CPU

while allowing the SRAM, Timer/Counters, USART, 2-wire Serial Interface, SPI port, and interrupt system to con-

tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other

chip functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous timer continues to

run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction

mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during

ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleep-

ing. This allows very fast start-up combined with low power consumption.

Atmel^®offers the QTouch^®library for embedding capacitive touch buttons, sliders and wheels functionality into

AVR^®microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully

debounced reporting of touch keys and includes Adjacent Key Suppression^®(AKS™) technology for unambiguous

detection of key events. The easy-to-use QTouch Suite toolchain allows you to explore, develop and debug your

own touch applications.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP Flash

allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-

volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use

any interface to download the application program in the Application Flash memory. Software in the Boot Flash

section will continue to run while the Application Flash section is updated, providing true Read-While-Write opera-

tion. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel

ATmega48A/PA/88A/PA/168A/PA/328/P is a powerful microcontroller that provides a highly flexible and cost effec-

tive solution to many embedded control applications.

The ATmega48A/PA/88A/PA/168A/PA/328/P AVR is supported with a full suite of program and system develop-

ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and

Evaluation kits.

2.2

Comparison Between Processors

The ATmega48A/PA/88A/PA/168A/PA/328/P differ only in memory sizes, boot loader support, and interrupt vector

sizes. Table 2-1 summarizes the different memory and interrupt vector sizes for the devices.

Table 2-1.

Device

Memory Size Summary

Flash

EEPROM

RAM

Interrupt Vector Size

ATmega48A

ATmega48PA

ATmega88A

ATmega88PA

ATmega168A

ATmega168PA

ATmega328

ATmega328P

4KBytes

8KBytes

16KBytes

32KBytes

256Bytes

512Bytes

1KBytes

512Bytes

1KBytes

2KBytes

1 instruction word/vector

2 instruction words/vector

ATmega48A/PA/88A/PA/168A/PA/328/P support a real Read-While-Write Self-Programming mechanism. There is

a separate Boot Loader Section, and the SPM instruction can only execute from there. In ATmega 48A/48PA there

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

6

8271GS–AVR–02/2013

is no Read-While-Write support and no separate Boot Loader Section. The SPM instruction can execute from the

entire Flash

3. Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

http://www.atmel.com/avr.

Note:

1.

4. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20

years at 85°C or 100 years at 25°C.

5. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These

code examples assume that the part specific header file is included before compilation. Be aware that not all C

compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.

Please confirm with the C compiler documentation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be

replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”,

“SBRC”, “SBR”, and “CBR”.

6. Capacitive Touch Sensing

The Atmel^®QTouch^®Library provides a simple to use solution to realize touch sensitive interfaces on most Atmel

AVR^®microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel QMatrix^®acquisition

methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the AVR Micro-

controller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the

touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch Library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch Library

User Guide - also available for download from Atmel website.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

7

8271GS–AVR–02/2013

7. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

(0xBE)

Reserved

UDR0

–

USART I/O Data Register

194

198

UBRR0H

UBRR0L

Reserved

UCSR0C

UCSR0B

UCSR0A

Reserved

USART Baud Rate Register High

USART Baud Rate Register Low

–

UMSEL01

RXCIE0

RXC0

–

UMSEL00

TXCIE0

TXC0

–

UPM01

UDRIE0

UDRE0

–

UPM00

RXEN0

FE0

–

USBS0

TXEN0

DOR0

–

UCPOL0

TXB80

MPCM0

–

UCSZ01 /UDORD0

UCSZ00 / UCPHA0

196/207

195

UCSZ02

RXB80

UPE0

U2X0

194

–

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

8

8271GS–AVR–02/2013

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

(0x7C)

(0x7B)

(0x7A)

TWAMR

TWCR

TWAM6

TWINT

TWAM5

TWEA

TWAM4

TWSTA

TWAM3

TWSTO

TWAM2

TWWC

TWAM1

TWEN

TWAM0

–

237

235

237

236

235

TWIE

TWDR

2-wire Serial Interface Data Register

TWAR

TWA6

TWS7

TWA5

TWS6

TWA4

TWS5

TWA3

TWS4

TWA2

TWS3

TWA1

–

TWA0

TWGCE

TWPS0

TWSR

TWPS1

TWBR

2-wire Serial Interface Bit Rate Register

Reserved

ASSR

–

AS2

–

TCN2UB

–

OCR2AUB

–

OCR2BUB

–

TCR2AUB

–

TCR2BUB

–

EXCLK

–

160

Reserved

OCR2B

Timer/Counter2 Output Compare Register B

Timer/Counter2 Output Compare Register A

Timer/Counter2 (8-bit)

159

158

OCR2A

TCNT2

TCCR2B

TCCR2A

Reserved

OCR1BH

OCR1BL

OCR1AH

OCR1AL

ICR1H

FOC2A

FOC2B

–

WGM22

CS22

–

CS21

CS20

COM2A1

COM2A0

COM2B1

COM2B0

–

WGM21

WGM20

155

–

Timer/Counter1 - Output Compare Register B High Byte

Timer/Counter1 - Output Compare Register B Low Byte

Timer/Counter1 - Output Compare Register A High Byte

Timer/Counter1 - Output Compare Register A Low Byte

Timer/Counter1 - Input Capture Register High Byte

Timer/Counter1 - Input Capture Register Low Byte

Timer/Counter1 - Counter Register High Byte

136

135

ICR1L

TCNT1H

TCNT1L

Reserved

TCCR1C

TCCR1B

TCCR1A

DIDR1

Timer/Counter1 - Counter Register Low Byte

–

FOC1A

ICNC1

COM1A1

–

FOC1B

ICES1

COM1A0

–

135

134

132

241

257

–

COM1B1

–

WGM13

WGM12

CS12

–

CS11

WGM11

AIN1D

ADC1D

–

CS10

WGM10

AIN0D

ADC0D

–

COM1B0

–

DIDR0

–

ADC5D

–

ADC4D

ADC3D

–

ADC2D

–

Reserved

ADMUX

–

REFS1

–

REFS0

ACME

ADSC

ADLAR

–

MUX3

–

MUX2

ADTS2

ADPS2

MUX1

ADTS1

ADPS1

MUX0

ADTS0

ADPS0

254

257

255

ADCSRB

ADCSRA

–

ADEN

ADATE

ADIF

ADIE

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

9

8271GS–AVR–02/2013

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

(0x79)

(0x78)

ADCH

ADCL

ADC Data Register High byte

ADC Data Register Low byte

256

(0x77)

Reserved

TIMSK2

TIMSK1

TIMSK0

PCMSK2

PCMSK1

PCMSK0

Reserved

EICRA

–

(0x76)

–

(0x75)

–

(0x74)

–

(0x73)

–

(0x72)

–

(0x71)

–

(0x70)

–

OCIE2B

OCIE1B

OCIE0B

PCINT18

PCINT10

PCINT2

–

OCIE2A

OCIE1A

OCIE0A

PCINT17

PCINT9

PCINT1

–

TOIE2

TOIE1

TOIE0

PCINT16

PCINT8

PCINT0

–

159

136

110

75

(0x6F)

–

ICIE1

–

(0x6E)

–

PCINT19

PCINT11

PCINT3

–

(0x6D)

PCINT23

PCINT22

PCINT21

PCINT20

(0x6C)

–

PCINT14

PCINT13

PCINT12

75

(0x6B)

PCINT7

PCINT6

PCINT5

PCINT4

75

(0x6A)

–

(0x69)

ISC11

–

ISC10

PCIE2

–

ISC01

PCIE1

–

ISC00

PCIE0

–

72

(0x68)

PCICR

(0x67)

Reserved

OSCCAL

Reserved

PRR

–

(0x66)

Oscillator Calibration Register

36

41

(0x65)

–

(0x64)

PRTWI

PRTIM2

PRTIM0

–

PRTIM1

PRSPI

PRUSART0

PRADC

(0x63)

Reserved

CLKPR

WDTCSR

SREG

–

(0x62)

–

(0x61)

CLKPCE

–

CLKPS3

CLKPS2

CLKPS1

CLKPS0

36

54

9

(0x60)

WDIF

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

WDP0

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

I

T

H

S

V

N

Z

C

SPH

–

(SP10) ^5.

SP9

SP8

12

SPL

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Reserved

SPMCSR

Reserved

MCUCR

MCUSR

SMCR

–

PGERS

–

SPMEN

–

SPMIE

(RWWSB)^5.

SIGRD

(RWWSRE)^5.

BLBSET

PGWRT

283

–

PUD

–

BODS⁽⁶⁾

BODSE⁽⁶⁾

IVSEL

EXTRF

SM0

–

IVCE

PORF

SE

44/69/92

54

–

WDRF

SM2

–

BORF

SM1

–

39

Reserved

ACSR

–

ACBG

–

ACD

–

ACO

–

ACI

–

ACIE

–

ACIC

–

ACIS1

–

ACIS0

–

240

Reserved

SPDR

SPI Data Register

171

170

169

25

SPSR

SPIF

SPIE

WCOL

SPE

–

SPI2X

SPR0

SPCR

DORD

MSTR

CPOL

CPHA

SPR1

GPIOR2

GPIOR1

Reserved

OCR0B

OCR0A

TCNT0

General Purpose I/O Register 2

General Purpose I/O Register 1

25

–

Timer/Counter0 Output Compare Register B

Timer/Counter0 Output Compare Register A

Timer/Counter0 (8-bit)

TCCR0B

TCCR0A

GTCCR

EEARH

EEARL

FOC0A

COM0A1

TSM

FOC0B

COM0A0

–

COM0B1

–

COM0B0

–

WGM02

CS02

CS01

CS00

–

WGM01

PSRASY

WGM00

PSRSYNC

141/161

21

(EEPROM Address Register High Byte) ^5.

EEPROM Address Register Low Byte

EEPROM Data Register

21

EEDR

21

EECR

–

EEPM1

EEPM0

EERIE

EEMPE

EEPE

EERE

21

GPIOR0

EIMSK

General Purpose I/O Register 0

25

–

INT1

INTF1

PCIF1

–

INT0

INTF0

PCIF0

–

73

EIFR

–

73

PCIFR

–

PCIF2

Reserved

TIFR2

–

OCF2B

OCF1B

OCF2A

OCF1A

TOV2

TOV1

160

137

TIFR1

ICF1

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

10

8271GS–AVR–02/2013

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x0 (0x20)

TIFR0

Reserved

PORTD

DDRD

–

OCF0B

OCF0A

TOV0

–

PORTD7

PORTD6

DDD6

PIND6

PORTC6

DDC6

PINC6

PORTB6

DDB6

PINB6

–

PORTD5

DDD5

PIND5

PORTC5

DDC5

PINC5

PORTB5

DDB5

PINB5

–

PORTD4

DDD4

PIND4

PORTC4

DDC4

PINC4

PORTB4

DDB4

PINB4

–

PORTD3

DDD3

PIND3

PORTC3

DDC3

PINC3

PORTB3

DDB3

PINB3

–

PORTD2

DDD2

PIND2

PORTC2

DDC2

PINC2

PORTB2

DDB2

PINB2

–

PORTD1

DDD1

PIND1

PORTC1

DDC1

PINC1

PORTB1

DDB1

PINB1

–

PORTD0

DDD0

PIND0

PORTC0

DDC0

PINC0

PORTB0

DDB0

PINB0

–

93

92

DDD7

PIND

PIND7

PORTC

DDRC

–

PINC

–

PORTB

DDRB

PORTB7

DDB7

PINB

PINB7

Reserved

–

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O

Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The

ATmega48A/PA/88A/PA/168A/PA/328/P is a complex microcontroller with more peripheral units than can be supported

within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in

SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

5. Only valid for ATmega88A/88PA/168A/168PA/328/328P.

6. BODS and BODSE only available for picoPower devices ATmega48PA/88PA/168PA/328P

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

11

8271GS–AVR–02/2013

8. Ordering Information

8.1

ATmega48A

Speed (MHz)

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega48A-AU

32A

ATmega48A-AUR⁽⁵⁾

ATmega48A-CCU

ATmega48A-CCUR⁽⁵⁾

ATmega48A-MMH⁽⁴⁾

ATmega48A-MMHR⁽⁴⁾⁽⁵⁾

ATmega48A-MU

32A

32CC1

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

20⁽³⁾

1.8 - 5.5

ATmega48A-MUR⁽⁵⁾

ATmega48A-PU

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See ”Speed Grades” on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

32CC1

28M1

32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5 mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

12

8271GS–AVR–02/2013

8.2

ATmega48PA

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega48PA-AU

32A

ATmega48PA-AUR⁽⁵⁾

ATmega48PA-CCU

ATmega48PA-CCUR⁽⁵⁾

ATmega48PA-MMH⁽⁴⁾

ATmega48PA-MMHR⁽⁴⁾⁽⁵⁾

ATmega48PA-MU

32A

32CC1

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

ATmega48PA-MUR⁽⁵⁾

ATmega48PA-PU

20

1.8 - 5.5

ATmega48PA-AN

32A

ATmega48PA-ANR⁽⁵⁾

ATmega48PA-MMN⁽⁴⁾

ATmega48PA-MMNR⁽⁴⁾⁽⁵⁾

ATmega48PA-MN

28M1

32M1-A

28P3

Industrial

(-40C to 105C)

ATmega48PA-MNR⁽⁵⁾

ATmega48PA-PN

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. See ”Speed Grades” on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

28M1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

13

8271GS–AVR–02/2013

8.3

ATmega88A

Speed (MHz)

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega88A-AU

32A

ATmega88A-AUR⁽⁵⁾

ATmega88A-CCU

ATmega88A-CCUR⁽⁵⁾

ATmega88A-MMH⁽⁴⁾

ATmega88A-MMHR⁽⁴⁾⁽⁵⁾

ATmega88A-MU

32A

32CC1

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

20⁽³⁾

1.8 - 5.5

ATmega88A-MUR⁽⁵⁾

ATmega88A-PU

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See ”Speed Grades” on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

28M1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

14

8271GS–AVR–02/2013

8.4

ATmega88PA

Speed (MHz)⁽³⁾

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega88PA-AU

32A

ATmega88PA-AUR⁽⁵⁾

ATmega88PA-CCU

ATmega88PA-CCUR⁽⁵⁾

ATmega88PA-MMH⁽⁴⁾

ATmega88PA-MMHR⁽⁴⁾⁽⁵⁾

ATmega88PA-MU

32A

32CC1

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

ATmega88PA-MUR⁽⁵⁾

ATmega88PA-PU

20

1.8 - 5.5

ATmega88PA-AN

32A

ATmega88PA-ANR⁽⁵⁾

ATmega88PA-MMN⁽⁴⁾

ATmega88PA-MMNR⁽⁴⁾⁽⁵⁾

ATmega88PA-MN

28M1

32M1-A

28P3

Industrial

(-40C to 105C)

ATmega88PA-MNR⁽⁵⁾

ATmega88PA-PN

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See ”Speed Grades” on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

28M1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5 mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

15

8271GS–AVR–02/2013

8.5

ATmega168A

Speed (MHz)⁽³⁾

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega168A-AU

32A

ATmega168A-AUR⁽⁵⁾

ATmega168A-CCU

ATmega168A-CCUR⁽⁵⁾

ATmega168A-MMH⁽⁴⁾

ATmega168A-MMHR⁽⁴⁾⁽⁵⁾

ATmega168A-MU

32A

32CC1

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

20

1.8 - 5.5

ATmega168A-MUR⁽⁵⁾

ATmega168A-PU

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See ”Speed Grades” on page 308

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

28M1

32-ball, 4 x 4 x 0.6 mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

16

8271GS–AVR–02/2013

8.6

ATmega168PA

Speed (MHz)⁽³⁾

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega168PA-AU

32A

ATmega168PA-AUR⁽⁵⁾

ATmega168PA-CCU

ATmega168PA-CCUR⁽⁵⁾

ATmega168PA-MMH⁽⁴⁾

ATmega168PA-MMHR⁽⁴⁾⁽⁵⁾

ATmega168PA-MU

32A

32CC1

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

20

1.8 - 5.5

ATmega168PA-MUR⁽⁵⁾

ATmega168PA-PU

ATmega168PA-AN

ATmega168PA-ANR⁽⁵⁾

ATmega168PA-MN

ATmega168PA-MNR⁽⁵⁾

ATmega168PA-PN

32A

32M1-A

28P3

Industrial

(-40C to 105C)

1.8 - 5.5

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See ”Speed Grades” on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

32CC1

28M1

32-ball, 4 x 4 x 0.6mm package, ball pitch 0.5mm, Ultra Thin, Fine-Pitch Ball Grill Array (UFBGA)

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

32M1-A

28P3

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

17

8271GS–AVR–02/2013

8.7

ATmega328

Speed (MHz)

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega328-AU

32A

ATmega328-AUR⁽⁵⁾

ATmega328-MMH⁽⁴⁾

ATmega328-MMHR⁽⁴⁾⁽⁵⁾

ATmega328-MU

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

20⁽³⁾

1.8 - 5.5

ATmega328-MUR⁽⁵⁾

ATmega328-PU

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 29-1 on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28M1

28P3

32M1-A

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

18

8271GS–AVR–02/2013

8.8

ATmega328P

Speed (MHz)⁽³⁾

Power Supply (V)

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATmega328P-AU

32A

ATmega328P-AUR⁽⁵⁾

ATmega328P-MMH⁽⁴⁾

ATmega328P-MMHR⁽⁴⁾⁽⁵⁾

ATmega328P-MU

28M1

32M1-A

28P3

Industrial

(-40C to 85C)

ATmega328P-MUR⁽⁵⁾

ATmega328P-PU

20

1.8 - 5.5

ATmega328P-AN

ATmega328P-ANR⁽⁵⁾

ATmega328P-MN

ATmega328P-MNR⁽⁵⁾

ATmega328P-PN

32A

32M1-A

28P3

Industrial

(-40C to 105C)

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive).Also

Halide free and fully Green.

3. See Figure 29-1 on page 308.

4. NiPdAu Lead Finish.

5. Tape & Reel.

Package Type

32A

32-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)

28M1

28P3

32M1-A

28-pad, 4 x 4 x 1.0 body, Lead Pitch 0.45mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

28-lead, 0.300” Wide, Plastic Dual Inline Package (PDIP)

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50mm Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

19

8271GS–AVR–02/2013

9. Packaging Information

9.1

32A

PIN 1 IDENTIFIER

PIN 1

B

e

E1

E

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

D1

E

Note 2

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10mm maximum.

E1

B

C

–

L

–

e

0.80 TYP

2010-10-20

TITLE

DRAWING NO.

REV.

32A, 32-lead, 7 x 7mm body size, 1.0mm body thickness,

0.8mm lead pitch, thin proﬁle plastic quad ﬂat package (TQFP)

32A

C

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

20

8271GS–AVR–02/2013

9.2

32CC1

1 2 3 4

5

6

0.08

A

B

Pin#1 ID

C

D

SIDE VIEW

b1

D

E

F

A1

A

E

A2

TOP VIEW

E1

e

32-Øb

1 2 3 4

5

6

F

COMMON DIMENSIONS

(Unit of Measure = mm)

E

D

C

MIN

–

MAX

0.60

–

NOM

–

NOTE

SYMBOL

D1

A

A1

A2

b

0.12

–

B

A

e

0.38 REF

0.30

0.25

3.90

0.35

–

1

2

b1

D

–

4.00

4.10

A1 BALL CORNER

BOTTOM VIEW

D1

E

2.50 BSC

4.00

3.90

4.10

E1

e

2.50 BSC

0.50 BSC

Note1: Dimension“b”is measured at the maximum ball dia. in a plane parallel

to the seating plane.

Note2: Dimension “b1” is the solderable surface defined by the opening of the

solder resist layer.

07/06/10

GPC

DRAWING NO.

TITLE

REV.

32CC1, 32-ball (6 x 6 Array), 4 x 4 x 0.6 mm

package, ball pitch 0.50 mm, Ultra Thin,

Fine-Pitch Ball Grid Array (UFBGA)

Package Drawing Contact:

packagedrawings@atmel.com

B

CAG

32CC1

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

21

8271GS–AVR–02/2013

9.3

28M1

D

C

1

2

3

Pin 1 ID

E

SIDE VIEW

A1

TOP VIEW

A

y

K

D2

0.45

E2

COMMON DIMENSIONS

(Unit of Measure = mm)

1

2

3

R 0.20

MIN

MAX

NOM

NOTE

SYMBOL

A

0.80

0.90

1.00

A1

b

0.00

0.17

0.02

0.22

0.20 REF

4.00

2.40

4.00

2.40

0.45

0.40

–

0.05

0.27

b

C

D

D2

E

3.95

2.35

3.95

2.35

4.05

2.45

4.05

2.45

L

e

E2

e

0.4 Ref

(4x)

BOTTOM VIEW

L

0.35

0.00

0.20

0.45

0.08

–

y

K

–

The terminal #1 ID is a Laser-marked Feature.

Note:

10/24/08

GPC

DRAWING NO.

TITLE

REV.

28M1, 28-pad,4 x 4 x 1.0mm Body, Lead Pitch 0.45mm,

2.4 x 2.4mm Exposed Pad, Thermally Enhanced

Plastic Very Thin Quad Flat No Lead Package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

ZBV

28M1

B

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

22

8271GS–AVR–02/2013

9.4

32M1-A

D

D1

1

2

3

0

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

0.08

C

(Unit of Measure = mm)

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

A

A1

A2

A3

b

1

2

3

P

–

Pin #1 Notch

(0.20 R)

E2

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

D

K

D1

D2

E

e

b

L

E1

E2

e

BOTTOM VIEW

L

0.30

–

0.50

0.60

P

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0mm Body, Lead Pitch 0.50mm,

3.10mm Exposed Pad, Micro Lead Frame Package (MLF)

E

R

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

23

8271GS–AVR–02/2013

9.5

28P3

D

1

E1

A

SEATING PLANE

A1

L

B2

(4 PLACES)

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

E

E1

B

7.493 Note 1

0.533

B1

B2

L

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25mm (0.010").

1.143

3.429

C

0.356

eB

e

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

28P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

24

8271GS–AVR–02/2013

10. Errata

10.1 Errata ATmega48A

The revision letter in this section refers to the revision of the ATmega48A device.

10.1.1

Rev. D

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

10.2 Errata ATmega48PA

The revision letter in this section refers to the revision of the ATmega48PA device.

10.2.1

Rev. D

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

25

8271GS–AVR–02/2013

10.3 Errata ATmega88A

The revision letter in this section refers to the revision of the ATmega88A device.

10.3.1

Rev. F

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

10.4 Errata ATmega88PA

The revision letter in this section refers to the revision of the ATmega88PA device.

10.4.1

Rev. F

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

26

8271GS–AVR–02/2013

10.5 Errata ATmega168A

The revision letter in this section refers to the revision of the ATmega168A device.

10.5.1

Rev. E

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

10.6 Errata ATmega168PA

The revision letter in this section refers to the revision of the ATmega168PA device.

10.6.1

Rev E

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

27

8271GS–AVR–02/2013

10.7 Errata ATmega328

The revision letter in this section refers to the revision of the ATmega328 device.

10.7.1

Rev D

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

10.7.2

10.7.3

Rev C

Not sampled.

Rev B

• Analog MUX can be turned off when setting ACME bit

• Unstable 32kHz Oscillator

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. Unstable 32kHz Oscillator

The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is

inaccurate.

Problem Fix/ Workaround

None.

10.7.4

Rev A

• Analog MUX can be turned off when setting ACME bit

• Unstable 32kHz Oscillator

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

28

8271GS–AVR–02/2013

2. Unstable 32kHz Oscillator

The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is

inaccurate.

Problem Fix/ Workaround

None.

10.8 Errata ATmega328P

The revision letter in this section refers to the revision of the ATmega328P device.

10.8.1

Rev D

• Analog MUX can be turned off when setting ACME bit

• TWI Data setup time can be too short

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. TWI Data setup time can be too short

When running the device as a TWI slave with a system clock above 2MHz, the data setup time for the first bit

after ACK may in some cases be too short. This may cause a false start or stop condition on the TWI line.

Problem Fix/Workaround

Insert a delay between setting TWDR and TWCR.

10.8.2

10.8.3

Rev C

Not sampled.

Rev B

• Analog MUX can be turned off when setting ACME bit

• Unstable 32kHz Oscillator

1. Analog MUX can be turned off when setting ACME bit

If the ACME (Analog Comparator Multiplexer Enabled) bit in ADCSRB is set while MUX3 in ADMUX is '1'

(ADMUX[3:0]=1xxx), all MUX'es are turned off until the ACME bit is cleared.

Problem Fix/Workaround

Clear the MUX3 bit before setting the ACME bit.

2. Unstable 32kHz Oscillator

The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is

inaccurate.

Problem Fix/ Workaround

None.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

29

8271GS–AVR–02/2013

10.8.4

Rev A

• Unstable 32kHz Oscillator

1. Unstable 32kHz Oscillator

The 32kHz oscillator does not work as system clock. The 32kHz oscillator used as asynchronous timer is

inaccurate.

Problem Fix/ Workaround

None.

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET SUMMARY]

30

8271GS–AVR–02/2013

Atmel Corporation

Atmel Asia Limited

Atmel Munich GmbH

Atmel Japan G.K.

1600 Technology Drive

Unit 01-5 & 16, 19F

Business Campus

16F Shin-Osaki Kangyo Bldg

San Jose, CA 95110

USA

BEA Tower, Millennium City 5

418 Kwun Tong Roa

Kwun Tong, Kowloon

HONG KONG

Parkring 4

1-6-4 Osaki, Shinagawa-ku

Tokyo 141-0032

D-85748 Garching b. Munich

GERMANY

Tel: (+1) (408) 441-0311

Fax: (+1) (408) 487-2600

www.atmel.com

JAPAN

Tel: (+49) 89-31970-0

Fax: (+49) 89-3194621

Tel: (+81) (3) 6417-0300

Fax: (+81) (3) 6417-0370

Tel: (+852) 2245-6100

Fax: (+852) 2722-1369

Atmel^®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities^®, and others are registered trademarks or trademarks of Atmel Corporation or its

subsidiaries. Other terms and product names may be trademarks of others.

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this

document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES

NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED

WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,

CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF

INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time

without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,

automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	包装说明：	VQFN-28
Reach Compliance Code：	compliant	Factory Lead Time：	9 weeks
风险等级：	0.94	具有ADC：	YES
其他特性：	ALSO OPERATES AT 2.7 V MINIMUM SUPPLY AT 10 MHZ AND 1.8 V MINIMUM SUPPLY AT 4 MHZ	地址总线宽度：
位大小：	8	CPU系列：	AVR RISC
最大时钟频率：	20 MHz	DAC 通道：	NO
DMA 通道：	NO	外部数据总线宽度：
JESD-30 代码：	S-PQCC-N28	长度：	4 mm
I/O 线路数量：	23	端子数量：	28
片上程序ROM宽度：	8	最高工作温度：	105 °C
最低工作温度：	-40 °C	PWM 通道：	YES
封装主体材料：	PLASTIC/EPOXY	封装代码：	HVQCCN
封装等效代码：	LCC28,.16SQ,18	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	电源：	2/5 V
认证状态：	Not Qualified	RAM（字节）：	1024
ROM（单词）：	8192	ROM可编程性：	FLASH
座面最大高度：	1 mm	速度：	20 MHz
子类别：	Microcontrollers	最大压摆率：	9 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子形式：	NO LEAD	端子节距：	0.45 mm
端子位置：	QUAD	宽度：	4 mm
uPs/uCs/外围集成电路类型：	MICROCONTROLLER, RISC	Base Number Matches：	1

型号	制造商	描述	价格	文档
ATMEGA88PA-MMUR	MICROCHIP	IC MCU 8BIT 8KB FLASH 28VQFN	获取价格
ATMEGA88PA-MU	ATMEL	8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash	获取价格
ATMEGA88PA-MUR	ATMEL	8-bit Microcontroller with 4/8/16/32K Bytes In-System Programmable Flash	获取价格
ATMEGA88PA-PU	ATMEL	8-bit Microcontroller with 8K Bytes In-System Programmable Flash	获取价格
ATmega88PB	ATMEL	Advanced RISC architecture	获取价格
ATmega88PB	MICROCHIP	The high-performance Microchip's AVR? 8-bit RISC-based microcontroller with picoPower? technology	获取价格
ATmega88PB-AN	ATMEL	Advanced RISC architecture	获取价格
ATMEGA88PB-AN	MICROCHIP		获取价格
ATmega88PB-ANR	ATMEL	Advanced RISC architecture	获取价格
ATMEGA88PB-ANR	MICROCHIP		获取价格

ATMEGA88PA-MMNR

ATMEGA88PA-MMNR 概述

ATMEGA88PA-MMNR 规格参数

ATMEGA88PA-MMNR 数据手册

ATMEGA88PA-MMNR CAD模型

原理图符号

PCB 封装图

3D模型

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