ATSAMA5D35-EK [MICROCHIP]
EVAL KIT SAMA5D35 CORTEX-A5;
| 型号： | ATSAMA5D35-EK |
| 厂家： | 
MICROCHIP |
| 描述： | EVAL KIT SAMA5D35 CORTEX-A5 |
| 文件： | 总122页 (文件大小：3107K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ARM-based Embedded MPUs
SAMA5D3x-EK User Guide
USER GUIDE
Introduction
This user guide introduces the evaluation kits for the Atmel® SAMA5D3 series
embedded MPUs listed below:
SAMA5D31
SAMA5D33
SAMA5D34
SAMA5D35
SAMA5D36
It pertains to the following evaluation kit references:
SAMA5D31-EK
SAMA5D33-EK
SAMA5D34-EK
SAMA5D35-EK
SAMA5D36-EK
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Contents
Important: Unpack and assemble the kit carefully, following the assembly guide provided in the box.
Boards
One SAMA5D3 main board (MB)
One of the five available CPU module (CM) boards
SAMA5D31-CM
SAMA5D33-CM
SAMA5D34-CM
SAMA5D35-CM
SAMA5D36-CM
One optional Display Module (DM) board (5"_WVGA_R-DM), available for all SAMA5D3x evaluation kits
that feature an LCD interface: SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D36
Power supply
One universal input AC/DC power supply with US, Europe and UK plug adapters
One 3V lithium battery type CR1225
Cables
One micro A/B-type USB cable
One RJ45 crossed cable
A welcome letter
Related Items
Atmel SAMA5D3 Series Datasheet
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Table of Contents
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Related Items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1. Evaluation Kit Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1
Electrostatic Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2. Power Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1
Power up the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2
Sample Code and Technical Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3. Evaluation Kit Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4. CPU Module (CM) Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
4.2
4.3
4.4
4.5
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Equipment List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Embest/Flextronics Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Ronetix Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
5. Main Board (MB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
5.1
5.2
5.3
5.4
5.5
Main Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Function Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
PIO Usage and Interface Connectors Details. . . . . . . . . . . . . . . . . . . . . . . . . 76
Main Board Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6. Optional Display Module (DM) Board . . . . . . . . . . . . . . . . . . . . . . 116
6.1
DM Board Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
6.2
Schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7. Troubleshooting and Recommendations . . . . . . . . . . . . . . . . . . . . 120
7.1
Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
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1.
Evaluation Kit Specifications
Table 1-1.
Evaluation Kit Specifications
Specifications
Characteristic
Clock speed
Ports
Up to 536 MHz PCK, up to 166 MHz MCK
10/100/1000 Ethernet, USB, RS232, JTAG, CAN, Audio, HDMI, SD card
5V DC from connector
Board supply voltage
Dimensions:
MB (Main Board)
165 * 135 * 20 mm
67.60 * (40 to 47) * 5 mm
135 * 80 * 6 mm
CM (Computer Module) Board
DM (Display Module) Board
RoHS status
Compliant
Compliant
CE and FCC Part 15 status
Kit Identification
SAMA5D31-EK
SAMA5D33-EK
SAMA5D34-EK
SAMA5D35-EK
SAMA5D36-EK
1.1
Electrostatic Warning
Warning:
ESD-Sensitive Electronic Equipment!
The evaluation kit is shipped in a protective anti-static package. The board system must not be subjected to high
electrostatic potentials.
We strongly recommend using a grounding strap or similar ESD protective device when handling the board in hostile
ESD environments (offices with synthetic carpet, for example). Avoid touching the component pins or any other metallic
element on the board.
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2.
Power Up
2.1
Power up the Board
Unpack the board, taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug
adapter corresponding to that of your country and insert it in the power supply.
Connect the power supply DC connector to the board and plug the power supply to an AC power plug.
The LCD should light up and display a welcome page. Click or touch icons displayed on the screen and view the demo
(the red ones need to be replaced by demo software).
2.2
Sample Code and Technical Support
After booting up the board, you can run sample code or your own application on the development kit. You can download
sample code and get technical support from the Atmel web site.
Linux software and demos can be found on the web site Linux4SAM.
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3.
Evaluation Kit Hardware
3.1
Introduction
The Atmel SAMA5D3 series evaluation kit is a fully-featured evaluation platform for Atmel SAMA5D3 series
microcontrollers. The evaluation kit allows users to extensively evaluate, prototype and create application-specific
designs.
The Atmel SAMA5D3 series evaluation kit is a platform architecture based on a main board, a computer module
equipped with a SAMA5D3 series processor and an optional display module, providing maximum flexibility for kit users.
The SAMA5D3 series evaluation kit consists of three boards:
The computer module (CM) board, is a single-board computer that integrates all the core components and is
mounted onto an application-specific main board (MB). The computer module has specified pinouts based on the
SODIMM200 connector. It provides the functional requirements for an embedded application. These functions
include, but are not limited to, graphics, audio, mass storage, network and multiple serial and USB ports. A single
SODIMM200 connector provides the main board interface to carry all the I/O signals to and from the computer
module.
The main board (MB) provides all the interface connectors required to attach the system to the application specific
peripherals. This versatility allows the designer to create a densely-packed solution, which results in a more
reliable product while simplifying system integration.
The display module board (DM) integrates LCD, touchscreen and Qtouch® technology
Table 3-1.
Feature
CAN0
CAN1
GMAC
EMAC
HSMCI1
HSMCI2
LCDC
UART0
UART1
ISI
Evaluation Kit Features
SAMA5D31
SAMA5D33
SAMA5D34
SAMA5D35
SAMA5D36
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SHA
AES
TDES
TC1
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4.
CPU Module (CM) Board
4.1
Overview
The CPU module (CM) board is the heart of the SAMA5D3x-EK. It connects to the main board through a SODIMM200
interface and integrates the SAMA5D3 series processor and external memories. The CM board serves as a minimal CPU
sub-system. All five SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 and SAMA5D36 processors share the same CM
board circuitry with minor configuration settings.
The CM board connects to a carrier board containing its connectors, power supply and any expansion I/O through a
standard gold-plated SODIMM 200-pin connection.
Note: There are five CM boards from three different manufacturers. The five processors are implemented as shown in
Table 4-1.
Table 4-1.
CM Board Implementation
Manufacturer and
Module Kind
SAMA5D31-CM
SAMA5D33-CM
SAMA5D34-CM
SAMA5D35-CM
SAMA5D36-CM
Embest/Flextronics
Ronetix
X
X
X
X
X
X
X
The five CM boards share the same circuitry design with different designator information and PCB layouts. The circuitry
reference in this guide, for common design parts, refers to schematics from SAMA5D3 series-CM (mfg2). All the other
schematics are provided in the Section 4.4 “Embest/Flextronics Schematics” and Section 4.5 “Ronetix Schematics”.
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Figure 4-1.
CPU Module Board from Embest/Flextronics
Figure 4-2.
CPU Module Board from Ronetix
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Figure 4-3.
Board Architecture
Nand Flash
DDR2
Nor Flash
Gigabit Ethernet
to Sodimm200
Data Flash
Led
Led
DDR2
2Gb
NAND
FLASH
2Gb
NOR
FLASH
128Mb
Serial
Data
FLASH
OneWire
Gigabit Ethernet
RGMII
EBI
SPI
PIO
External Memory
SAMA5D3x-CM_BGA324
System
PIO
Controller
A
B
C
D
E
Power
3v3
1V8
1V2
32Khz
12Mhz
Osc
SoDIMM200
SAMA5D3 Series
Note: Different interfaces on the main board share the same connections to the CPU module. The actual usage
depends on the CPU module featured in your evaluation kit.
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4.2
Equipment List
The CM board is built around an ARM® Cortex®-A5-based microcontroller (BGA 324 package) with external memory and
Gigabit Ethernet PHYsical layer transceiver.
4.2.1 Devices
Table 4-2.
Characteristic
PCB
CPU Module Specifications
Specifications
CPU Module (10 layers)
Dimensions in mm:
(L x W x H)
67.60 *(40 to 47) * 5 max
Processor
SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35 and SAMA5D36 (324-ball BGA package)
Clock speed
12 MHz crystal
32.768 kHz
Memory
2 x DDR2 2 Gb 16 Meg x 16 x 8 banks
1 x SLC NAND Flash 2/4Gb 8-bit data
1 x NOR 128 Mb 16-bit data
On-board I/O Ports
One Serial EEPROM SPI
One 1-Wire EEPROM DS2431
One user-powered red LED and one user blue LED
One gigabit Ethernet PHY
Connector
SODIMM200
Board supply voltage
3.3V from SODIMM200 connector
On-board power regulation
Temperature:
- operating
- storage
0°C to +60°C
-40°C to +85°C
Relative humidity
RoHS status
0 to 90% (non condensing)
Compliant
SAMA5D31-CM
SAMA5D33-CM
SAMA5D34-CM
SAMA5D35-CM
SAMA5D36-CM
Board Identification
Silkscreen top
4.2.2 Interface Connection
SODIMM200 card edge interface
4.2.3 Configuration Items
One jumper for SPI DataFlash chip select connection
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4.2.4 Boot Options
Table 4-3 lists the supported boot options
Table 4-3.
Boot Options
Boot Mode
BMS OPEN
Boot Device
Type
Note
Embedded ROM Boot
ROM Boot followed by:
- SPI0, NPCS0
- SD/MMC MCI0, MCI1
- NAND Flash
Default boot is from
embedded ROM
- SPI0, NPCS1
- TWI0
- SAM-BA®
BMS CLOSE
NOR Flash
On-board NOR Flash
using NCS0
Boot from external NOR
Flash memory
4.2.4.1
Boot Configuration
In order to use SAM-BA boot, the NAND Flash and SPI DataFlash must be deselected.
Pressing the pushbutton PB4 (CS boot disable) disconnects these two components from the system while the ROM Boot
is searching for a boot device after reset. A reset can be forced by pressing the PB1 (NRST) pushbutton. Note that PB1
and PB4 pushbuttons are located on the main board (MB).
In order to boot from SAM-BA, both PB1 and PB4 should be pressed, then PB1 released while PB4 is kept pressed until
SAM-BA boots.
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4.3
Functional Blocks
4.3.1 Processor
The CM board is equipped with one Atmel SAMA5D3 ARM-based embedded MPU from the list below:
SAMA5D31
SAMA5D33
SAMA5D34
SAMA5D35
SAMA5D36
The SAMA5D3x devices are packaged in a BGA324-ball BGA package and share an identical footprint.
.As different interfaces can be defined using the same pins, the functions available on the evaluation board depend on
the actual configuration of the CPU.
The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the ARM Cortex-A5
processor, achieving 536 MHz with power consumption levels below 0.5 mW in low-power mode. The device features a
floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture.
It integrates advanced user interface and connectivity peripherals and security features.
The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the
high bandwidth required by the processor and the high-speed peripherals. The device offers support for
DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC.
The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition,
a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588,
10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for
encryption (AES, TDES) and hash function (SHA), the SAMA5D3 ensures anti-cloning, code protection and secure
external data transfers.
Refer to Section 4. “CPU Module (CM) Board” on page 7 for details.
The processor runs at frequencies up to 536 MHz for the core and up to 166 MHz for the system bus.
4.3.2 Clock Circuitry
The CM board includes three clock sources:
Two clocks are alternatives for the SAMA5D3 series processor main clock
One crystal oscillator is used for the Ethernet RGMII chip
Table 4-4.
Main Components Associated with the Clock Systems
Component
Assignment
Quantity
Description
1
1
1
Crystal for internal clock, 12 MHz
Crystal for RTC clock, 32.768 kHz
Oscillator for ethernet clock RGMII, 25 MHz
Y1
Y2
Y3
4.3.3 Reset Circuitry
The reset sources for the CM board are:
Power-on reset
Pushbutton reset (Pushbutton is equipped on main board)
JTAG reset from an in-circuit emulator (MB features an on-board JTAG interface)
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4.3.4 Power Supplies
The CM board is driven by +3.3V input power rail from the MB through the SODIMM200 connector. The CM board
embeds all necessary power rails required for the microprocessor.
When additional voltages are required, they are generated on-board from the 3.3V supply (power source is a linear
regulator or a switching regulator). The detailed power supply requirements for given modules are specified within the
corresponding product documentation.
Table 4-5 summarizes the power specifications.
Table 4-5.
Nominal
Supply Group Configuration
Name
Powers
Component
the Slow Clock oscillator, the internal 32K
RC, the internal 12M RC and a part of the
System Controller
3.0V
VDDBU
From VBAT 3V, SODIMM200 connector
3.3V
3.3V
3.3V
3.3V
3.3V
VDDIOP0
VDDIOP1
VDDUTMII
VDDOSC
VDDANA
a part of peripheral I/O lines
a part of peripheral I/O lines
the USB device and host UTMI + interface
the main oscillator cells
From main 3.3V, SODIMM200 connector
From main 3.3V, SODIMM200 connector
From main 3.3V, SODIMM200 connector
From main 3.3V, SODIMM200 connector
From main 3.3V, SODIMM200 connector
the analog-to-digital converter
the core, including the processor, the
embedded memories and the peripherals
1.2V
VDDCORE
Regulator on-board
1.2V
1.2V
1.8V
VDDUTMIC
VDDPLLA
the USB device and host UTMI + core
the PLLA cell
Regulator on-board
Regulator on-board
Regulator on-board
VDDIODDR
DDR2 interface I/O lines
NAND, NOR Flash and SMC interface I/O
lines
1.8V
VDDIOM
Regulator on-board
3.0V to
3.3V
ADVREF
ADC reference voltage
From ADVREF, SODIMM200 connector
Regulator on-board
2.5V
VDDFUSE
Fuse box for programming
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Figure 4-4.
Embest/Flextronics Power Supply
TP1
SMD
L1
VCC_3V3
VDDIOP1
180ohm at 100MHz
1
2
VCC_1V2
MN15
VOUT
RT9018B-18GSP
VCC_3V3
C1
C2
100nF
NTRST
TDI
TP2
SMD
L2
180ohm at 100MHz
6
3
4
100nF
VIN
VDD
1
2
C131
100nF
C0603
C132
10uF
C134
10uF 23.7K 1%
C0805
R46
TP3
SMD
C14
10nF
C0402
1
7
5
2
PGOOD
ADJ
NC
EN
R0402
TP7
PWR_EN
TMS
TCK
TP4
SMD
SMD
VDDBU
R40
100K 1%
R0402
R51
47K 1%
R0402
R44
DNP
R0402
VDDIOP0
C12
TP5
SMD
TP8
SMD
TP6
SMD
C6
100nF
C7
100nF
C8
100nF
C3
100nF
C4
100nF
C9
100nF
C10
100nF
C5
100nF
SOP_8__50_154X193_69
C11
100nF
TDO
NRST
TP9
SMD
C15
4.7uF
100nF
VCC_3V3
VDDIOP0
VCC_3V3
TP10
SMD
VDDBU
VDDIODDR
MN16
RT8010GQW
VIN
VCC_3V3
TP12
SMD
2.2uH L15
R4
4
6
3
2
DNP
LX
10uF
C25
C0805
3D16-2
C13
22pF
TP11
SMD
R38
200K 1%
R0402
C128
100nF
C0603
C130
10uF
C0805
T9
VDDIOM
{7}
JTAGSEL
TDI
TMS
TCK
TDO
C0402
JTAGSEL
TDI
TMS
TCK
TDO
NTRST
NRST
TDI
TMS
TCK
TDO
NTRST
NRST
R8
N10
P9
M11
P11
V9
P12
T16
PWR_EN
{7}
{7}
{7}
{7}
{7}
PWR_EN
{7}
VDDIOM_1
VDDIOM_2
FB
EN
C17
100nF
C18
100nF
R39
100K 1%
R0402
R49
DNP
WDFN-6L_2X2
NTRST
R0402
{3,6,7} NRST
D13
F14
G10
G13
H11
VCC_3V3
VDDIODDR_1
VDDIODDR_2
VDDIODDR_3
VDDIODDR_4
VDDIODDR_5
R8
10K
U15
U9
TST
BMS
C19
100nF
C23
100nF
C20
100nF
C21
100nF
C24
100nF
{7}
BMS
R6
R7
100K
100K
VDDIOP0
VDDBU
WKUP
SHDN
T10
T12
{7}
{7}
WKUP
SHDN
WKUP
SHDN
FUSE_2V5
VCC_3V3
C27
20pF
R3
VDDFUSE
U8
V8
XIN
C28
100nF
C29
100nF
Y1
12MHz
U11
U13
R10
VDDOSC
VDDUTMII
VDDPLLA
VDDOSC
WKUP
SHDN
TP14
SMD
C30
C31
20pF
20pF
XOUT
XIN32
XOUT32
L6
10uH/150mA
MN2H
SAMA5D3x_BGA324
VDDOSC
VCC_3V3
TP15
SMD
TP16
SMD
L5
TP17
SMD
U16
V16
VDDPLLA
10uH/150mA
VCC_1V2
C34
100nF
C35
100nF
R11
1R
Y2
32.768 kHz
C32
C33
100nF
R10
1R
100nF
C36
20pF
C38
4.7uF
U6
V6
VCC_1V2
R111 0R
C37
4.7uF
{7}
{7}
DIBN
DIBP
DIBN
DIBP
V13
VDDUTMIC
VDDANA
ADVREF
C39
100nF
TP18
V10
U10
{7}
{7}
HHSDMA
HHSDPA
HHSDMA
HHSDPA
SMD
L7
VDDANA
10uH/150mA
VCC_3V3
V12
U12
L6
L5
GNDUTMI
{7}
{7}
HHSDMB
HHSDPB
HHSDMB
HHSDPB
C40
100nF
C41
100nF
R16
1R
V14
U14
{7}
{7}
HHSDMC
HHSDPC
HHSDMC
HHSDPC
ADVREF
TP19 C42
SMD 4.7uF
R11
VBG
C43
100nF
MN14
XC6206P251MR-G
Voltage Detector
SUP1
R19
5.62K 1%
C44
10pF
FUSE_2V5
VCC_3V3
2
1
Vo
3
R109
0R
C121
1uF
Vin
Vss
C127
1uF
GNDUTMI
GNDUTMI
DNP
CA89405MF
GNDUTMI
SAMA5D3x-EK User Guide [USER GUIDE]
14
11180B–ATARM–29-Oct-13
Figure 4-5.
Ronetix Power Supply
Soft-Start Time
Typ
Min
100 us
EN Input High Threshold
EN Input Low Threshold
1.2
V
V
Max 0.4
SEE TABLE 1
VDD_CORE
3V3
U1
L1
1
5
4
VIN
LX
3V3
LQM2HPN1R0MG0L
C3
2
GND
C4
22u/6V3
RS1
0402
22u/6V3
GND
3
EN
VOUT
R1
RS1
2k49/1%
100k
GND
RS2
GND
SC189ASKTRT 1V0
C5
10k/1%
POWER_ENABLE
SEE TABLE 1
2;3
GND pins are provided and should be
GND
VDDIODDR
C7
3V3
U2
L2
1
5
4
VIN
GND
EN
LX
LQM2HPN1R0MG0L
C6
2
22u/6V3
R3 5k1/1%
0402
22u/6V3
GND
3
VOUT
GND
GND
SC189ASKTRT 1V0
C8
R2
6k34/1%
GND
VDD_CORE
VDD_PLL
R4
0R
3V3
US1 DNP
1
5
4
VIN
VOUT
C9
2
GND
STBY
C10
1uF/10V
3
NC
1uF/10V
GND
GND
BU12TD3WG-TR
C11
10n/25V
OR BU10TD3WG-TR
SEE TABLE 1
Start Time
Typ
Min
50 us
GND
GND
EN Input High Threshold
EN Input Low Threshold
1.2
V
V
Max 0.3
SAMA5D3x-EK User Guide [USER GUIDE]
15
11180B–ATARM–29-Oct-13
Figure 4-6.
Ronetix Power Supply (Continued)
(3V3)
VDD_IOM
VDD_IOP0 VDD_IOP1
VDD_CORE
U3-A
C12
C13
100n/10V
100n/10V
T16
C5
C7
C14
C16
C15
C18
C17
C19
C23
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
VDDIOM
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
P12
VDDIOM
D14
T15
U17
V7
T17
J11
GNDIOM
GNDIOM
C20
C22
C21
C24
100n/10V
100n/10V
100n/10V
100n/10V
V11
G7
T7
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
M4
C9
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GND
L11
N13
T8
U7
N11
J7
T14
V17
A16
GNDIOP
GNDIOP
GNDIOP
GNDIOP
GND
VDDIODDR
GND
Vbat
E5
D13
F14
G10
G13
H11
C26
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
C25
100n/10V
V15
T13
C28
C27
C30
C29
VDDBU
GNDBU
VDD_ANA
GND
L3
top/bot
L6
L4
VDDANA
GNDANA
BLM15AG121SN1D
C33
VDDFUSE
E14
F10
F13
F15
H14
GNDIODDR
GNDIODDR
GNDIODDR
GNDIODDR
GNDIODDR
GND
C31
4u7/6V3/X5R
R3
P4
VDDFUSE
GNDFUSE
C32
470n/16V/Y5V
AGND
0603
GND
GND
top/bot
R10
P10
VDDPLLA
GNDPLL
R9 0R
3V3
L4
GND
VDD_PLL
470p/50V
C34
VDD_PLL
top/bot
top/bot
U11
T11
top/bot
VDDOSC
GNDOSC
V13
U13
R12
BLM15AG121SN1D
VDDUTMIC
VDDUTMII
GNDUTMI
L5
C36
L5
ADVREF
4u7/6V3/X5R
BLM15AG121SN1D
C105
100n/10V
C35
470n/16V/Y5V
SAMA5D3x
C39
C37
470p/50V
4u7/6V3/X5R
C38
ADVREF
2;4
GND
UTMI_GND
470n/16V/Y5V
A cooper for UTMI_GND net
cover all USB Components
C40
100n/10V
GND
3V3
L6
GND
BLM15AG121SN1D
R57
0603
C41
C43
4u7/6V3/X5R
470p/50V
0R
C42
GND
UTMI_GND
470n/16V/Y5V
UTMI_GND
SAMA5D3x-EK User Guide [USER GUIDE]
16
11180B–ATARM–29-Oct-13
4.3.5 Memory
4.3.5.1
Memory Organization
The SAMA5D3 series processor features a DDR/SDR memory interface and an External Bus Interface (EBI) to interface
to a wide range of external memories and to almost any kind of parallel peripheral.
4.3.5.2
Resource Allocation
This section describes the memory devices that equip the SAMA5D3 series CM board.
Two SDRAM/DDR2 are used as main system memory. MT47H128M16 - 2 Gb - 16 Meg x 16 x 8 banks, the board
provides up to 2 Gb of on-board, soldered DDR2 SDRAM. The memory bus is 32 bits wide and operates at up to
166 MHz.
Figure 4-7.
Embest/Flextronics DDR2 Memory
{3} DDR_D[0..31]
{3} DDR_A[0..13]
MN8
MN9
DDR2 SDRAM
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DDR2 SDRAM
DDR2 SDRAM
MT47H128M16RT
MT47H128M16RT
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
{3}
{3}
{3}
DDR_BA0
DDR_BA1
DDR_BA2
BA0
BA1
BA2
BA0
BA1
BA2
VDDIODDR
VDDIODDR
VDDIODDR
A1
E1
J9
M9
R1
A1
E1
J9
M9
R1
VDDIODDR
R93 DNP
C53 100nF
C55 100nF
C57 100nF
C59 100nF
C61 100nF
C54 100nF
C56 100nF
C58 100nF
C60 100nF
C62 100nF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
K9
R91 DNP
K9
ODT
ODT
R92
0R
R94 0R
DDR_CKE
K2
DDR_CKE
K2
{3}
DDR_CKE
CKE
CKE
J1
J1
C63 100nF
C64 100nF
VDDL
VDDL
DDR_CLK
J8
K8
DDR_CLK
DDR_CLKN
J8
K8
{3}
{3}
DDR_CLK
DDR_CLKN
CK
CK
CK
CK
DDR_CLKN
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
C65 100nF
C67 100nF
C69 100nF
C71 100nF
C73 100nF
C75 100nF
C77 100nF
C79 100nF
C81 100nF
C83 100nF
C66 100nF
C68 100nF
C70 100nF
C72 100nF
C74 100nF
C76 100nF
C78 100nF
C80 100nF
C82 100nF
C84 100nF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR_CS
L8
DDR_CS
L8
{3}
DDR_CS
CS
CS
DDR_CAS
DDR_RAS
L7
K7
DDR_CAS
DDR_RAS
L7
K7
{3}
{3}
DDR_CAS
DDR_RAS
CAS
RAS
CAS
RAS
DDR_WE
K3
DDR_WE
K3
{3}
{3}
DDR_WE
WE
WE
J2
DDR_VREF
J2
DDR_VREF
VREF
VREF
B7
A8
B7
A8
DDR_DQS1
{3}
{3}
DDR_DQS3
DDR_DQS2
UDQS
UDQS
UDQS
UDQS
A3
E3
J3
N1
P9
A3
E3
J3
N1
P9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C85
100nF
C86
100nF
4.7K
4.7K
R98 4.7K
R99 4.7K
R100
R101
F7
E8
F7
E8
{3}
DDR_DQS0
LDQS
LDQS
LDQS
LDQS
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
B3
F3
B3
F3
{3}
{3}
DDR_DQM1
DDR_DQM0
{3}
{3}
DDR_DQM3
DDR_DQM2
UDM
LDM
UDM
LDM
A2
E2
R3
R7
A2
E2
R3
R7
RFU1
RFU2
RFU3
RFU4
RFU1
RFU2
RFU3
RFU4
VDDIODDR
L8
10uH/150mA
TP22
SMD
C87
4.7uF
R64
1R
R65
1.5K 1%
C88
100nF
DDR_VREF
DDR_VREF {3}
C89
4.7uF
C90
100nF
R66
1.5K 1%
SAMA5D3x-EK User Guide [USER GUIDE]
17
11180B–ATARM–29-Oct-13
Figure 4-8.
Ronetix DDR2 Memory
DDR_ADDR
DDR_A[0-13]
Address and control traces may not exceed 1.3 inches (33.0 mm).
Address and control traces must be length-matched to within 0.1 inch (2.54 mm).
Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm).
U3-H
12.09.2012
B10 DDR_A0
Chenged U4 and U5
DDR_A0
DDR_A1
C11 DDR_A1
From MT47H64M16HR-25H to MT47H128M16RT-3:C
A9 DDR_A2
group 3AB
L3
&
L8
Zo=50 ohms
minimizing crosstalk with [DQ, DQS, DQM]
DDR_A2
D11 DDR_A3
DDR_A3
B9 DDR_A4
DDR_A4
E10 DDR_A5
DDR_A5
D10 DDR_A6
DDR_ADDR
DDR_A[0-13]
DDR_DATA
group 2A
L3 L8
DDR_ADDR
DDR_A[0-13]
DDR_DATA
group 2B
DDR_A6
A8 DDR_A7
&
L3
&
L8
DDR_A7
DDR_D[0-15]
DDR_D[16-31]
C10 DDR_A8
U4
U5
DDR_A8
B8 DDR_A9
F11 DDR_A10
A7 DDR_A11
D9 DDR_A12
A6 DDR_A13
H12
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
A
G8
G2
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
B
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_A9
A0
DQ0
A0
DQ0
DQ1
DDR_DATA
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_D0
A1
DQ1
DQ2
A1
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
A2
A2
DQ2
DDR_D[0-31]
A3
DQ3
A3
DQ3
A4
DQ4
A4
DQ4
DDR_D0
A5
DQ5
A5
DQ5
H17
DDR_D1
DDR_D2
DDR_D1
A6
DQ6
A6
DQ6
H13
DDR_D2
A7
DQ7
A7
DQ7
G17
DDR_D3
DDR_D3
A8
DQ8
A8
DQ8
G16
DDR_D4
DDR_D4
A9
DQ9
A9
DQ9
H15
DDR_D5
DDR_D5
A10
A11
A12
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A10
A11
A12
RFU(A13)
RFU
RFU
BA0
BA1
BA2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
F17
DDR_D6
DDR_D6
G15
DDR_D7
DDR_D7
F16
DDR_D8
DDR_D8
RFU(A13)
RFU
E17
DDR_D9
DDR_D9
G14
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQSN0
DDR_DQSN1
DDR_DQSN2
DDR_DQSN3
DDR_CS
RFU
E16
DDR_BA0
DDR_BA1
DDR_BA2
DDR_BA0
DDR_BA1
DDR_BA2
5
5
5
BA0
5
5
D17
L3
F7
E8
B7
A8
DDR_DQS0
L3
F7
E8
B7
A8
DDR_DQS2
4k7
0402
BA1
LDQS
5
5
LDQS
5
5
C18
DDR_CKE
L1
R72
4k7
DDR_CKE
L1
R70
R71
0402
5
BA2
LDQS#/NU
UDQS
5
5
LDQS#/NU
D16
DDR_DQS1
DDR_DQS3
4k7
0402
UDQS
C17
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
K3
L7
K7
L8
K9
R73
4k7
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
K3
L7
K7
L8
K9
0402
5
5
5
5
WE#
CAS#
RAS#
CS#
UDQS#/NU
5
5
5
5
WE#
CAS#
RAS#
CS#
UDQS#/NU
B16
B18
F3
B3
DDR_DQM0
DDR_DQM1
F3
B3
DDR_DQM2
DDR_DQM3
LDM
UDM
5
5
GND
LDM
UDM
5
5
GND
C15
A18
ODT
ODT
VDDIODDR
R50
VDDIODDR
R52
C16
A2
E2
VDDIODDR
A2
E2
VDDIODDR
NC
NC
NC
NC
0R
0R
0R
0R
C14
DNP
K2
J8
DNP
K2
J8
0402
0402
0402
0402
CKE
CK
CKE
CK
D15
R51
R53
B14
DDR_CK
K8
A1
E1
J9
C44 100n/10V
C109
DDR_CK
DDR_CK#
group 1AB
K8
A1
E1
J9
C46 100n/10V
C117
C47 100n/10V
C118
C50 100n/10V
C116
C51 100n/10V
5
5
CK#
VDD
VDD
5
5
CK#
VDD
VDD
A15
DDR_CK#
100n/10V
100n/10V
100n/10V
100n/10V
A14
group 1AB
A3
E3
J3
C45 100n/10V
C110
A3
E3
J3
GND
VSS
VDD
GND
VSS
VDD
E12
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
100n/10V
100n/10V
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
VSS
VDD
VSS
VDD
A11
C48 100n/10V
C108
VSS
VDD
VSS
VDD
B11
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
F12
C49 100n/10V
VSS
VSS
A10
C77 100n/10V
C52 100n/10V
C79 100n/10V
C53 100n/10V
C76 100n/10V
C56 100n/10V
C111 100n/10V
C57 100n/10V
C114 100n/10V
C115 100n/10V
C113 100n/10V
C119 100n/10V
C120 100n/10V
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
E11
C54 100n/10V
C55 100n/10V
C58 100n/10V
C59 100n/10V
G12
5
5
5
5
5
5
5
5
E15
B15
D12
E18
G18
B17
C112 100n/10V
B13
D18
J2
DDR_VREF
group 1AB
J2
DDR_VREF
group 1AB
VREF
5
VREF
5
GND
GND
F18
DDR_VREF
TP13
5
A17
MT47H128M16RT-3:C
MT47H128M16RT-3:C
GND
GND
A13
C60
C61
group 1AB
C8
TP12
DDR_CS#
5
100n/10V
100n/10V
B12
top/bot
top/bot
DDR_CK
DDR_CK#
DDR_CLK
DDR_CLKN
DDR_CKE
DDR_RAS
DDR_CAS
DDR_WE
DDR_BA0
DDR_BA1
DDR_BA2
DDR_CALN
DDR_CALP
DDR_VREF
5
5
Differential
100 ohms
A12
B7
G11
A5
DDR_CKE
DDR_RAS#
5
GND
GND
VDDIODDR
VDDIODDR
5
5
5
5
5
5
DDR_CAS#
DDR_WE#
DDR_BA0
DDR_BA1
DDR_BA2
L7
B5
E9
BLM15AG121SN1D
R10
B6
C62
R12
200R
Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of MIURA.
The layout EBI DDR2 should use controlled impedance traces of ZO 50Ohm characteristic impedance.
Trace width 0.13mm: target 50Ohm impedance.
Trace space 0.30 to 0.38 mm.
F9
R11
1R
=
1k5/1%
100n/10V
group 1AB
DDR_VREF
C12
E13
C13
=
=
top/bot
5
DDR_VREF
group 1AB
R13
C65
5
C63
100n/10V
R14
SAMA5D3x
200R
C64
4u7/6V3/X5R
1k5/1%
100n/10V
GND
GND
GND
GND
One NAND Flash: NAND is connected to the processor. Maximum size is 256 bytes.
One NOR Flash (optional, not populated): NOR Flash is 16 bits wide. Maximum size is 128 Mbytes.
SAMA5D3x-EK User Guide [USER GUIDE]
18
11180B–ATARM–29-Oct-13
Figure 4-9.
Embest/Flextronics External Memory
MN5
JS28F128P33TF70A
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
29
25
24
23
22
21
20
19
8
7
6
5
4
3
2
1
55
18
17
16
11
10
9
34
36
39
41
47
49
51
53
35
37
40
42
48
50
52
54
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
M_EBI_D8
M_EBI_D9
M_EBI_D10
M_EBI_D11
M_EBI_D12
M_EBI_D13
M_EBI_D14
M_EBI_D15
A1
A2
A3
A4
A5
A6
A7
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
56
46
WAIT
ADV#
26
27
13
RFU1
RFU2
NC
VDDIOM
R27
R29
R30
0R
45
44
15
CLK
100K
100K
RST#
WP#
VDDIOM
{2,6,7}
NRST
33
38
VCC
VCCQ
VDDIOM
30
32
14
C47
100nF
C48
100nF
CE#
OE#
WE#
NRD
NWE
12
28
31
VSS
VSS
VSS
43
R31
10K
VDDIOM
VPP
MN6
NL17SZ126
VDDIOM
NCS0
R34
470K
1
2
3
5
4
{5} OE_Nandflash
OE
IN
VCC
NCS3
C49
100nF
OUT
GND
MN7
MT29F2G08ABAEAWP
NANDCLE
NANDALE
0R
16
17
8
18
9
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
CLE
ALE
RE
WE
CE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
NRD R41
NWE R43
NANDCE
R45
0R
470K
0R
470K
470K
VDDIOM
VDDIOM
NANDRDY R48
R50
7
R/B
R52
19
WP
I/O8_N.C
I/O9_N.C
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
1
2
3
4
5
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
R58
DNP
TP13
SMD
6
10
11
14
15
20
23
24
35
21
22
38
VDDIOM
VCC_3V3
VDDIOM
N.C7
N.C8
12
37
34
39
1
2
VCC
VCC
N.C9
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
VCC_N.C
VCC_N.C
L13
180ohm at 100MHz
C51
100nF
C52
100nF
13
36
25
48
VSS
VSS
VSS_N.C
VSS_N.C
SAMA5D3x-EK User Guide [USER GUIDE]
19
11180B–ATARM–29-Oct-13
Figure 4-10. Ronetix External Memory
U3-G
P13
PE0/A0(NBS0)
R14
R13
V18
P14
U18
T18
R15
P17
P15
P18
R16
N16
R17
N17
R18
N18
P16
M18
N15
M15
N14
M17
M13
M16
N12
M14
A1_NOR
A2_NOR
A3_NOR
A4_NOR
A5_NOR
A6_NOR
A7_NOR
A8_NOR
A9_NOR
A10_NOR
A11_NOR
A12_NOR
A13_NOR
A14_NOR
A15_NOR
A16_NOR
A17_NOR
A18_NOR
A19_NOR
A20_NOR
PE1/A1
PE2/A2
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
VDD_IOM
PE3/A3
PE4/A4
PE5/A5
PE6/A6
NOR FLASH
R15
100k
PE7/A7
PE8/A8
U6
PE9/A9
R16 22R
D0
D1
D2
D3
D4
D5
D6
D7
E3
H3
E4
H4
H5
E5
H6
E6
F3
G3
F4
G4
F5
G6
F6
G7
F2
A5
G2
B5
F7
A4
PE26/NCS0/TXD2
0402
PE10/A10
PE11/A11
PE12/A12
PE13/A13
PE14/A14
6
6
6
6
6
6
6
6
DQ0
E#
W#
2;6
NWE_NOR/NAND_WE
NRD_NOR/NAND_OE
DQ1
6
6
DQ2
G#
NRST
DQ3
RP#
2;7;8
DQ4
BYTE#
R/B#
PE15/A15/SCK3
DQ5
PE16/A16/CTS3
PE17/A17/RTS3
DQ6
DQ7
D8
PE18/A18/RXD3
6
6
6
6
6
6
6
6
DQ8
D9
PE19/A19/TXD3
DQ9
D10
D11
D12
D13
D14
D15
PE20/A20/SCK2
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
A21_NOR/NAND_ALE
A22_NOR/NAND_CLE
PE21/A21(NANDALE)
PE22/A22(NANDCLE)
PE23/A23/CTS2
6
6
PE23/A23_NOR/CTS2
PE24/RTS2
PE25/RXD2/1-Wire
PE26/NCS0/TXD2
2;6
2;8
VDD_IOM
PE24/A24/RTS2
B4
PE25/A25/RXD2
2;6;8
VPP/WP#
PE26/NCS0/TXD2
2;6
2
M12 PE27/NCS1/TIOA2/LCDDAT22
L13 PE28/NCS2/TIOB2/LCDDAT23
A1_NOR
A2_NOR
A3_NOR
A4_NOR
A5_NOR
A6_NOR
A7_NOR
A8_NOR
A9_NOR
A10_NOR
A11_NOR
A12_NOR
A13_NOR
A14_NOR
A15_NOR
A16_NOR
A17_NOR
A18_NOR
A19_NOR
A20_NOR
E2
D2
C2
A2
B2
D3
C3
A3
B6
A6
C6
D6
B7
A7
C7
D7
E7
B3
C4
D5
D4
C5
B8
D8
F1
G5
C66
C68
C67
100n/10V
100n/10V
100n/10V
PE27/NCS1/TIOA2/LCDDAT22
PE28/NCS2/TIOB2/LCDDAT23
PE29/NWR1(NBS1)/TCLK2
PE30/NWAIT
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
A0
VCCQ
VCCQ
VCC
2
A1
L15
L14
L16
PE29/NWR1(NBS1)/TCLK2
PE30/NWAIT
2
A2
2
A3
PE31/IRQ/PWML1
PE31/IRQ/PWML1
2
A4
GND
A5
K12
K15
K14
K16
K13
K17
J12
K18
J14
J16
J13
J17
J15
J18
H16
H18
L12
L18
L17
K11
D0
D1
D2
D3
D4
D5
D6
D7
A1
A8
B1
C1
C8
D1
E1
F8
G1
G8
H1
H8
D0
D1
6
6
6
6
6
6
6
6
A6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A7
D2
D3
A8
A9
D4
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
D5
D6
D7
D8
D8
6
6
6
6
6
6
6
6
6
6
6
6
D9
D9
D10
D11
D12
D13
D14
D15
D10
D11
D12
D13
D14
D15
A21_NOR/NAND_ALE
A22_NOR/NAND_CLE
E8
H2
H7
6
6
VSS
VSS
VSS
NAND_CS/NCS3
PE23/A23_NOR/CTS2
NCS3
2;6
NAND_RD/BY
NRD_NOR/NAND_OE
NWE_NOR/NAND_WE
NANDRDY
NRD
M29W128GL70ZA6E
EN29GL128H90BAIP
GND
NWE(NWR0)
Alternative component : EN29GL128H90BAIP
SAMA5D3x
VDD_IOM
NAND FLASH
R17
100k
U8
CLE
A22_NOR/NAND_CLE
A21_NOR/NAND_ALE
NRD_NOR/NAND_OE
NWE_NOR/NAND_WE
16
17
8
29
30
31
32
41
42
43
44
D0
6
6
6
6
6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
D1
ALE
RE#
WE#
CE#
6
D2
6
18
9
D3
6
NAND_CS_R/NCS3
R19
0R
D4
6
D5
0402
6
6
10
14
15
4
D6
6
D7
NC
NC
NC
NC
NC
NC
NC
NC
6
VDD_IOM
5
6
R23
R24
10k
26
35
1
2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
100k
3
R22 0R
0402
NAND_RD/BY
7
11
20
21
22
23
24
27
28
33
40
45
46
6
RD/BY#
WP#
NAND_WP
19
VDD_IOM
34
39
25
48
VCC!
VCC!
VSS!
VSS!
C70
C71
100n/10V
100n/10V
12
37
13
36
38
VCC
VCC
VSS
VSS
DNU
47
DNU
GND
MT29F2G08ABAEAWP-IT
HY27UF082G2B-TPCB
Alternative component : HY27UF082G2B-TPCB
SAMA5D3x-EK User Guide [USER GUIDE]
20
11180B–ATARM–29-Oct-13
4.3.6 Serial Peripheral Interface Controller (SPI)
The SAMA5D3 series processor provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used
to interface with the on-board serial DataFlash. Note that the on-board serial DataFlash is enabled through a jumper: JP1
on Embest modules, J1 on Ronetix modules. The jumper must be in place access (and boot) the serial DataFlash.
Figure 4-11. Embest/Flextronics Serial DataFlash on SPI
VDDIOP1
R67
470K
MN10
AT25DF321A
VDDIOP1
PD11
PD10
PD12
(SPI0_MOSI) R68
(SPI0_MIS0) R69
(SPI0_SPCK) R70
0R
0R
0R
5
2
6
8
SI
VCC
SO
SCK
C91
100nF
3
7
WP
HOLD
1
CS
4
GND
JP1
VDDIOP1
SERIAL DATAFLASH
R71
10K
MN11
NL17SZ126
VDDIOP1
OE_Dataflash
1
2
3
5
{3} OE_Nandflash
OE
IN
VCC
PD13
D1
4
C92
100nF
OUT
BAT54C
GND
{7} BOOT_CS_OFF
Figure 4-12. Ronetix Serial DataFlash on SPI
VDD_IOM
VDD_IOM
C69
100n/10V
R21
10k
Populate either R25 or J1 /J2/
J2
5
U9
A
GND
VCC
NAND_CS/NCS3
2
1
Y
4
NAND_CS_R/NCS3
HEADER TH 2x1/2mm/90dgr
6
6
VDD_IOP0
OE
J1
SERIAL FLASH
GND
3
HEADER SMD 2x1/2mm/90dgr
SN74LVC1G126DBVT
R26
100k
VDD_IOP0
VDD_IOP0
U10
D1
R25 0R DNP
0402
GND
VDD_IOP0
C72
CS_BOOT_DISABLE
1
8
2
CS#
VCC
WP#
BAT54CWT1G
PD10/SPI0_MISO
2;6;9
R65
22R
2
3
R27
10k
0402
SO (SOI)
SI (SIO)
SCK
PD11/SPI0_MOSI
5
6
2;6;9
C73
100n/10V
100n/10V
GND
PD12/SPI0_SPCK
2;6;9
VDD_IOP0
5
U11
A
7
4
HOLD#
GND
VCC
PD13/SPI0_CS0
2
1
Y
4
2;6;9
AT25DF321A-SH
GND
OE
GND
3
SN74LVC1G126DBVT
GND
SAMA5D3x-EK User Guide [USER GUIDE]
21
11180B–ATARM–29-Oct-13
4.3.7 1-Wire EEPROM
The SAMA5D3 series CM board uses a 1-wire device as a “soft label” to store information such as chip type,
manufacture name, production date, etc.
Only page 1 is used.
Warning:
Do not modify the information contained in this page.
Pages 2 to n remain free for the user.
Figure 4-13. Embest 1-Wire EEPROM
VDDIOM
R72
1.5K
MN12
DS2431P+
3
4
5
6
NC1
PE25
R73
0R
2
IO
NC2
NC3
NC4
1-WIRE EEPROM
Figure 4-14. Ronetix 1-Wire EEPROM
VDD_IOM
1-Wire EEPROM
R18
1k5/1%
2
U7
IO
R20 0R
0402
PE25/RXD2/1-Wire
3
4
5
6
2;6;8
NC
NC
NC
NC
1
GND
DS2431P
GND
SAMA5D3x-EK User Guide [USER GUIDE]
22
11180B–ATARM–29-Oct-13
4.3.8 Tri-Speed Ethernet PHY
The SAMA5D3 series CM board is equipped with a MICREL PHY device (MICREL KSZ9021/31) operating at
10/100/1000 Mbps. The board supports the RGMII interface mode. The Ethernet interface consists of four pairs of low-
voltage differential pair signals designated from GRX± and GTx± plus control signals for link activity indicators. These
signals can be used to connect to a 10/100/1000 Base-T RJ45 connector integrated on the main board.
For more information about the Ethernet controller device, refer to the MICREL KSZ89021RN controller manufacturer's
datasheet.
Figure 4-15. Embest/Flextronics GEthernet ETH0
AVDDL_PLL
R77
27R
NRST
{2,3,7}
+
C94
10nF
C95
10nF
C93
10uF
R78
R79
4.7K
1K
VDDIOP1
PB[0..31] {5,7}
R80
R81
R82
27R
27R
27R
G125CK
INT_GETHR PB25
GMDIO
PB18
L9
VDDIOP1 180ohm at 100MHz
AVDDH
PB17
1
2
VDDIOP1
+
C97
10nF
C98
10nF
C99
10nF
C96
10uF
R83
4.99K 1%
+
C100
10nF
C101
10nF
C102
10nF
C103
10uF
MN17
AVDDL
KSZ9021RN
VDDIOP1
+
C105
10nF
C106
10nF
C104
10uF
R90 R95 R96 R97
4.7K 4.7K 4.7K 4.7K
1
2
3
4
5
6
7
8
9
36
R84
R85
27R
27R
GMDC
GRXCK
PB16
PB11
AVDDH
MDC
35
{7}
{7}
ETH0_TX1+
ETH0_TX1-
TXRXP_A
TXRXM_A
AVDDL
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
AVDDL
RX_CLK
34
33
32
31
30
29
28
27
26
25
DVDDH
RX_DV
RXD0
RXD1
DVDDL
VSS
RXD2
RXD3
DVDDL
TX_EN
R102
27R
27R
27R
PB13
PB4
PB5
GRX_CTL
GRX0
GRX1
3
4
RR24C
RR24D
6
5
{7}
{7}
{7}
{7}
ETH0_RX1+
ETH0_RX1-
ETH0_TX2+
ETH0_TX2-
KSZ9021RN
48-pin QFN
RR25A
RR25B
1
2
8
7
27R
27R
GRX2
GRX3
PB6
PB7
10
11
12
{7}
{7}
ETH0_RX2+
ETH0_RX2-
TXRXP_D
TXRXM_D
AVDDH
R87
27R
GTX_CTL PB9
DVDDL
VDDIOP1
+
C108
10nF
C109
10nF
C110
10nF
C111
10nF
C112
10nF
C113
10nF
C107
10uF
R88
R89
27R
GTXCK
PB8
4.7K
3
4
1
2
RR25C
RR25D
RR26A
RR26B
6
5
8
7
27R
27R
27R
27R
GTX3
GTX2
GTX1
GTX0
PB3
PB2
PB1
PB0
{7}
{7}
LED2
LED1
MN13
SC189ASKTRT
VCC_3V3
L14
LQM2HPN1R0MG0L
AVDDL_PMOS
L10
AVDDL_PLL
180ohm at 100MHz
1
2
3
5
4
1
2
VIN
GND
EN
LX
C120
10nF
C115
10uF
C114
C119
20pF
XI
R32
2K 1%
VOUT
+
C118
22uF
C116
47uF
L11
180ohm at 100MHz
1
AVDDL
C117
10nF
Y3
25MHz
R33
10K 1%
2
20pF
XO
L12
180ohm at 100MHz
DVDDL
1
2
SAMA5D3x-EK User Guide [USER GUIDE]
23
11180B–ATARM–29-Oct-13
Figure 4-16. Ronetix GEthernet ETH0
ETH_DVDDL
L8
2A !
max 345mA-->
BLM21PG221SN1D
C74
C128
22u/6V3
22u/6V3
ETH_AVDDL
L11
2A !
GND
GND
max 205mA-->
BLM21PG221SN1D
C78
C129
ETH_AVDDH
VDD_IOP1
22u/6V3
22u/6V3
max ?mA-->
ETH_AVDDL_PLL
GND
GND
L9
2A
!
U15
VIN
L13
0.5A !
L10
max ?mA-->
max 563mA-->
C131
1
5
4
ETH_V1
max 13mA-->
LX
BLM21PG221SN1D
LQM2HPN1R0MG0L
BLM15AG121SN1D
C75
2
C81
C130
GND
EN
C92
C106
C107
100n/10V
22u/6V3
22u/6V3
22u/6V3
GND
3
10u/6V3
0402
VOUT
10n/25V
RS3
2k/1%
SC189ASKTRT 1V0
C127
GND
GND
RS4
10k/1%
GND
GND
GND
GND
GND
ETH_DVDDH
GND GND
L12
2A !
max ?mA-->
C132
BLM21PG221SN1D
C80
RGMII Routing Constraints (Reduced Gigabit Media Independent Interface):
The RGMII signals must be length-matched by TX and RX groups.
That is, the TX group should be matched within 0.25 inch (6.35 mm),
and the RX group should be matched within 0.25 inch (6.35 mm).
Total length should not exceed 1.75 inch (44.5 mm).
ETH_DVDDH
22u/6V3
22u/6V3
There is no requirement to match the TX and RX groups
because their clocks are not related.
GND
GND
R28
4k7
U12
KSZ9021RN
PB0/GTX0
19
20
21
22
24
25
2
3
top/bot
top/bot
ETH0_TX1+
ETH0_TX1-
7
7
7
7
TXD0
TXRXP_A
TXRXM_A
2
2
PB1/GTX1
PB2/GTX2
PB3/GTX3
TXD1
TXD2
place close to CPU
U3-D
5
6
top/bot
top/bot
ETH0_RX1+
ETH0_RX1-
TXD3
TXRXP_B
TXRXM_B
2
2
T2
N7
T3
N6
P5
T4
R4
U1
R5
P3
R6
V3
P6
V1
R7
U3
P7
V2
V5
T6
N8
U4
M7
U5
R69
R68
R67
R66
22R
PB0/GTX0
ETH_DVDDH
PB8/GTX_CLK
PB9/GTXEN
top/bot
0402
0402
0402
0402
PB0/GTX0/PWMH0
PB1/GTX1/PWML0
PB2/GTX2/TK1
7
7
7
7
7
7
7
7
7
7
7
GTX_CLK
TX_EN
22R
22R
22R
PB1/GTX1
PB2/GTX2
7
ETH_DVDDH
place close to KSZ9021RN
7
8
top/bot
top/bot
ETH0_TX2+
ETH0_TX2-
TXRXP_C
TXRXM_C
2
2
PB3/GTX3
PB4/GRX0
R59
R60
R61
R62
R33
22R
22R
22R
22R
22R
32
31
28
27
35
33
0402
0402
0402
0402
PB3/GTX3/TF1
7
7
7
7
RXD0/MODE0
RXD1/MODE1
RXD2/MODE2
RXD3/MODE3
RX_CLK/PHYAD2
PB4/GRX0
PB5/GRX1
PB6/GRX2
PB7/GRX3
PB8/GTX_CLK
PB9/GTXEN
PB5/GRX1
PB4/GRX0/PWMH1
PB5/GRX1/PWML1
PB6/GRX2/TD1
R31
4k7
R32
PB6/GRX2
10
11
top/bot
top/bot
ETH0_RX2+
ETH0_RX2-
TXRXP_D
TXRXM_D
2
2
4k7
R35
4k7
PB7/GRX3
PB11/RX_CLK
PB12/RX_DV R75
0 4 0 2
PB7/GRX3/RK1
7
R30
R29
22R
0R
15
17
LED2
LED1
0402
0402
0402
PB8/GTXCK/PWMH2
PB9/GTXEN/PWML2
PB10/GTXER/RF1
PB11/GRXCK/RD1
PB12/GRXDV/PWMH3
PB13/GRXER/PWML3
PB14/GCRS/CANRX1
PB15/GCOL/CANTX1
PB16/GMDC
2;7
RX_DV/CLK125_EN
LED2/PHYAD1
LED1/PHYAD0
2
2
22R
DNP
R37
4k7
0402
PB10/GTXER/RF1
PB25/SCK1/GRX6
38
41
2
2;7
INT_N
PB11/RX_CLK
PB18/CLK125_NDO
top/bot
R34
22R
0 4 0 2
7
7
CLK125_NDO/LED_MODE
R36
1k
PB12/RX_DV
2;7
ETH_AVDDH
PB13/GRXER/PWML3
PB16/GMDC
PB17/GMDIO
36
37
42
2
7
7
MDC
PB14/GCRS/CANRX1
PB15/GCOL/CANTX1
PB16/GMDC
1
12
47
C84
C83
C85
10n/25V
10n/25V
10n/25V
2
MDIO
AVDDH
AVDDH
AVDDH
2
7
7
RESET_N
GND
R76
22R
0 4 0 2
PB17/GMDIO
place close
to KSZ9021RN
C82
22p/50V
Y4
top/bot
top/bot
46
45
PB17/GMDIO
XI
PB18/CLK125_NDO
R77
PB18/G125CK
7
2
XO
place close
to U3
ETH_DVDDH
PB19/MCI1_CDA/GTX4
PB20/MCI1_DA0/GTX5
PB21/MCI1_DA1/GTX6
PB22/MCI1_DA2/GTX7
PB23/MCI1_DA3/GRX4
0R
ETH_AVDDL
PB19/MCI1_CDA/GTX4
PB20/MCI1_DA0/GTX5
PB21/MCI1_DA1/GTX6
PB22/MCI1_DA2/GTX7
PB23/MCI1_DA3/GRX4
PB24/MCI1_CK/GRX5
PB25/SCK1/GRX6
PB26/CTS1/GRX7
PB27/RTS1/PWMH1
PB28/RXD1
2
2
2
2
2
R38
0402
DNP
48
ISET
CPX32-25.000MHz
4k99/1%
4
9
C89
C88
10n/25V
10n/25V
AVDDL
AVDDL
ETH_DVDDH
R39
D2
C87
10n/25V
10n/25V
16
34
40
GND
DVDDH
DVDDH
DVDDH
C86
22p/50V
M8 top/bot
PB24/MCI1_CK/GRX5
100k
BAS316
C91
C90
ETH_AVDDL_PLL
GND
T5
N9
V4
PB25/SCK1/GRX6
PB26/CTS1/GRX7
PB27/RTS1/PWMH1
PB28/RXD1
Cl=Cs+[C1xC2]/[C1+C2]
if C1=C2 =>
C1,2=2[Cl-Cs] !!!
Cl is load capacitance of the cristal.
CS is the stray capacitance on the
printed circuit board,
2;7
2
R40
0402
GND
NRST
44
43
2;6;8
AVDDL_PLL
LDO_O
10n/25V
ETH_DVDDL
14
2
DNP 0R
M9
P8
C93
C95
C94
C97
C96
C98
10n/25V
10n/25V
10n/25V
10n/25V
10n/25V
10n/25V
2
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
C99
1uF/10V
C121
PB29/TXD1
18
23
26
30
39
C122
PB29/TXD1
2
M10
R9
PB30/DRXD
typically
for calculation
a value of 5pf can be used
PB30/DRXD
2
PB31/DTXD
13
29
49
10n/25V
100n/10V
PB31/DTXD
2
VSS_PS
VSS
GND
SAMA5D3x
P_GND
GND
GND
GND
GND
L14
BLM15AG121SN1D
GND
SAMA5D3x-EK User Guide [USER GUIDE]
24
11180B–ATARM–29-Oct-13
4.3.9 Indicators
There are two LEDs on the SAMA5D3 series CM board that can be controlled by the user. Both are controlled by GPIO
lines PE24 and PE25 as shown below.
Figure 4-17. Embest/Flextronics LED Indicators
VCC_3V3
{3,7} PE[23..31]
R74
470R
D2
Blue
PE25
R75
100K
PE24
1
R76
470R
D3
red
2
3
Q1
IRLML2502
LED
Figure 4-18. Ronetix LED Indicators
VDD_IOM
VDD_IOM
LEDS
DL1
LED 0603 - RED - LTST-C190CKT
DL2
LED 0603 - BLUE - LTST-C193TBKT-5A
R46
1M
R47
200R
R49
200R
D
S
G
PE24/RTS2
2;6
PE25/RXD2/1-Wire
2;6
Q1
BSS138W-7-F
GND
SAMA5D3x-EK User Guide [USER GUIDE]
25
11180B–ATARM–29-Oct-13
4.3.10 SODIMM200 Interface
The SAMA5D3 series CM board uses SODIMM200 card edge connector to interface with the MB board.
Refer to Section 5.4.22 “SODIMM Card Edge Socket”.
4.3.11 Connectors
Figure 4-19 shows the mechanical dimensions of the SAMA5D3 series CM board outline and the mounting holes.
Figure 4-19.
CPU Module Board Dimensions
Holes for mounting screws on carrier board.
SAMA5D3x-EK User Guide [USER GUIDE]
26
11180B–ATARM–29-Oct-13
4.4
Embest/Flextronics Schematics
This SAMA5D3x-EK CM board manufactured by Embest/Flextronics is available in Revision D and Revision E. In this
section, schematics are provided for both revisions.
4.4.1 CPU Module Revision D Schematics
This section contains the following schematics:
Block diagram
SAMA5D3x power
SAMA5D3x NOR and NAND
4 Gb DDR2
SAMA5D3x DataFlash, 1-wire, LED
Ethernet
200-pin SODIMM
SAMA5D3x-EK User Guide [USER GUIDE]
27
11180B–ATARM–29-Oct-13
5
4
3
2
1
3V3 INPUT
VBAT
D
C
B
A
D
C
B
A
S
O
D
I
M
M
128Mb
NOR
FLASH
ANALOG Reference
USB A,B,C
DIB
ATMEL
4Gb
DDR2
SDRAM
SAMA5D3 SERIES
EBI
C
O
N
N
E
C
T
O
R
ARM CORTEX A5-BASED PROCESSOR
ICE
2Gb
NAND
FLASH
PIO A,...E
PIO A&D
PIO A,...E
PIO B&E
SERIAL
DATA
FLASH
10/100/1000 FAST
ETHERNET
ONE WIRE
EEPROM
SERIAL
EEPROM
PIO C
http://arm.embedinfo.com
Title:
SAMA5D3x-CM
Size:
A3
Document Number:
BLOCK DIAGRAM
Rev:
D
Draw By: Zhu Xueliang Date: Monday, September 17, 2012
1
Sheet: 1 of 7
5
4
3
2
5
4
3
2
1
TP1
SMD
L1
VCC_3V3
VDDIOP1
180ohm at 100MHz
1
2
VCC_1V2
MN15
VOUT
RT9018B-18GSP
VCC_3V3
C1
C2
100nF
NTRST
TDI
TP2
SMD
L2
180ohm at 100MHz
6
3
4
100nF
VIN
VDD
1
2
C131
100nF
C0603
C132
10uF
D
C
B
A
D
C
B
A
C134
10uF 23.7K 1%
C0805
R46
TP3
SMD
C14
10nF
C0402
1
7
5
2
PGOOD
ADJ
NC
EN
R0402
TP7
SMD
PWR_EN
TMS
TCK
TP4
SMD
VDDBU
R40
100K 1%
R0402
R51
47K 1%
R0402
R44
DNP
R0402
VDDIOP0
C12
TP5
SMD
TP8
SMD
TP6
SMD
C6
100nF
C7
100nF
C8
100nF
C3
100nF
C4
100nF
C9
100nF
C10
100nF
C5
100nF
SOP_8__50_154X193_69
C11
100nF
TDO
NRST
TP9
SMD
C15
4.7uF
100nF
VCC_3V3
VDDIOP0
VCC_3V3
TP10
SMD
VDDBU
VDDIODDR
MN16
RT8010GQW
VIN
VCC_3V3
TP12
SMD
2.2uH L15
R4
4
6
3
2
DNP
LX
10uF
C25
C0805
3D16-2
C13
22pF
TP11
SMD
R38
200K 1%
R0402
C128
100nF
C0603
C130
10uF
C0805
T9
VDDIOM
{7}
JTAGSEL
TDI
TMS
TCK
TDO
C0402
JTAGSEL
TDI
TMS
TCK
TDO
NTRST
NRST
TDI
TMS
TCK
TDO
NTRST
NRST
R8
N10
P9
M11
P11
V9
P12
T16
PWR_EN
{7}
{7}
{7}
{7}
{7}
PWR_EN
{7}
VDDIOM_1
VDDIOM_2
FB
EN
C17
100nF
C18
100nF
R39
100K 1%
R0402
R49
DNP
WDFN-6L_2X2
NTRST
R0402
{3,6,7} NRST
D13
F14
G10
G13
H11
VCC_3V3
VDDIODDR_1
VDDIODDR_2
VDDIODDR_3
VDDIODDR_4
VDDIODDR_5
R8
10K
U15
U9
TST
BMS
C19
100nF
C23
100nF
C20
C21
100nF
C24
100nF
{7}
BMS
100nF
R6
R7
100K
100K
VDDIOP0
VDDBU
WKUP
SHDN
T10
T12
{7}
{7}
WKUP
SHDN
WKUP
SHDN
FUSE_2V5
VCC_3V3
C27
20pF
R3
VDDFUSE
U8
V8
XIN
C28
100nF
C29
100nF
Y1
12MHz
U11
U13
R10
VDDOSC
VDDUTMII
VDDPLLA
VDDOSC
WKUP
SHDN
TP14
SMD
C30
C31
20pF
20pF
XOUT
XIN32
XOUT32
L6
10uH/150mA
MN2H
SAMA5D3x_BGA324
VDDOSC
VCC_3V3
TP15
SMD
TP16
SMD
L5
TP17
SMD
U16
V16
VDDPLLA
10uH/150mA
VCC_1V2
C34
100nF
C35
100nF
R11
1R
Y2
20pF
32.768 kHz
C32
100nF
C33
100nF
R10
1R
C36
C38
4.7uF
U6
V6
VCC_1V2
R111 0R
C37
4.7uF
{7}
{7}
DIBN
DIBP
DIBN
DIBP
V13
VDDUTMIC
VDDANA
ADVREF
C39
100nF
TP18
SMD
V10
U10
{7}
{7}
HHSDMA
HHSDPA
HHSDMA
HHSDPA
L7
VDDANA
10uH/150mA
VCC_3V3
V12
U12
L6
L5
GNDUTMI
{7}
{7}
HHSDMB
HHSDPB
HHSDMB
HHSDPB
C40
100nF
C41
100nF
R16
1R
V14
U14
{7}
{7}
HHSDMC
HHSDPC
HHSDMC
HHSDPC
ADVREF
TP19 C42
SMD 4.7uF
R11
VBG
C43
100nF
R19
C44
10pF
5.62K 1%
SUP1
GNDUTMI
GNDUTMI
MN14
XC6206P251MR-G
Voltage Detector
DNP
CA89405MF
FUSE_2V5
VCC_3V3
R109
0R
2
1
Vo
3
C121
1uF
Vin
Vss
http://arm.embedinfo.com
GNDUTMI
C127
1uF
Title:
SAMA5D3x-CM
Size:
A3
Document Number:
SAMA5D3x-I&POWER
Rev:
D
Draw By: Zhu Xueliang Date: Friday, September 21, 2012
1
Sheet: 2 of 7
5
4
3
2
5
4
3
2
1
MN2E
SAMA5D3x_BGA324
M_EBI_A0
TP21
SMD
MN2F
SAMA5D3x_BGA324
P13
R14
R13
V18
P14
U18
T18
R15
P17
P15
P18
R16
N16
R17
N17
R18
N18
P16
M18
N15
M15
N14
M17
M13
M16
N12
M14
M12
L13
L15
L14
L16
DDR_A[0..13] {4}
PE0_A0/NBS0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
PE24
PE1_A1
PE2_A2
PE3_A3
PE4_A4
PE5_A5
PE6_A6
PE7_A7
PE8_A8
PE9_A9
PE10_A10
PE11_A11
PE12_A12
PE13_A13
B10
C11
A9
D11
B9
E10
D10
A8
C10
B8
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
D
C
B
A
D
C
B
A
MN5
JS28F128P33TF70A
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
29
25
24
23
22
21
20
19
8
7
6
5
4
3
2
1
55
18
17
16
11
10
9
34
36
39
41
47
49
51
53
35
37
40
42
48
50
52
54
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
M_EBI_D8
M_EBI_D9
M_EBI_D10
M_EBI_D11
M_EBI_D12
M_EBI_D13
M_EBI_D14
M_EBI_D15
A1
A2
A3
A4
A5
A6
A7
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
F11
A7
D9
PE14_A14
A6
PE15_A15_SCK3
PE16_A16_CTS3
PE17_A17_RTS3
PE18_A18_RXD3
PE19_A19_TXD3
PE20_A20_SCK2
PE21_A21/NANDALE
PE22_A22/NANDCLE
PE23_A23_CTS2
PE24_A24_RTS2
PE25_A25_RXD2
PE26_NCS0_TXD2
PE27_NCS1_TIOA2
PE28_NCS2_TIOB2
PE29_NWR1/NBS1_TCLK2
PE30_NWAIT
PE31_IRQ_PWML1
DDR_D[0..31] {4}
H12
H17
H13
G17
G16
H15
F17
G15
F16
E17
G14
E16
D17
C18
D16
C17
B16
B18
C15
A18
C16
C14
D15
B14
A15
A14
E12
A11
B11
F12
A10
E11
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
M_EBI_A21
M_EBI_A22
M_EBI_A23
R20
R21
R22
27R
27R
27R
PE[23..31] {5,7}
PE25
PE26
PE27
PE28
PE29
PE30
PE31
R23
0R
56
46
WAIT
ADV#
R24
R25
R26
R28
0R
0R
0R
0R
PE23
26
27
13
RFU1
RFU2
NC
NANDCLE
NANDALE
NCS0
VDDIOM
R27
R29
R30
0R
45
44
15
CLK
100K
100K
RST#
WP#
VDDIOM
{2,6,7}
NRST
33
38
VCC
VCCQ
VDDIOM
30
32
14
C47
100nF
C48
100nF
CE#
OE#
WE#
NRD
NWE
12
28
31
VSS
VSS
VSS
43
R31
10K
VDDIOM
VPP
MN6
NL17SZ126
VDDIOM
NCS0
R34
470K
E9
B6
F9
1
2
3
5
4
DDR_BA0 {4}
DDR_BA1 {4}
DDR_BA2 {4}
{5} OE_Nandflash
DDR_BA0
DDR_BA1
DDR_BA2
OE
IN
VCC
NCS3
C49
100nF
OUT
G11
A5
DDR_RAS {4}
DDR_CAS {4}
DDR_RAS
DDR_CAS
GND
B7
B12
A12
MN7
DDR_CKE {4}
DDR_CLK {4}
DDR_CLKN {4}
DDR_CKE
DDR_CLK
DDR_CLKN
MT29F2G08ABAEAWP
NANDCLE
NANDALE
0R
16
17
8
18
9
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
CLE
ALE
RE
WE
CE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
C8
B5
NRD R41
DDR_CS {4}
DDR_WE {4}
DDR_CS
DDR_WE
NWE R43
NANDCE
R45
0R
G12
E15
B15
D12
470K
0R
470K
470K
VDDIOM
VDDIOM
DDR_DQM0 {4}
DDR_DQM1 {4}
DDR_DQM2 {4}
DDR_DQM3 {4}
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
MN2G
SAMA5D3x_BGA324
NANDRDY R48
R50
7
R/B
R52
19
WP
I/O8_N.C
I/O9_N.C
K12
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
M_EBI_D8
M_EBI_D9
M_EBI_D10
M_EBI_D11
M_EBI_D12
M_EBI_D13
M_EBI_D14
M_EBI_D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
E18
D18
G18
F18
B17
A17
B13
A13
K15
K14
K16
K13
K17
J12
K18
J14
J16
J13
J17
J15
J18
H16
H18
DDR_DQS0 {4}
DDR_DQS1 {4}
DDR_DQS2 {4}
DDR_DQS3 {4}
DDR_DQS0
DDR_DQSN0
DDR_DQS1
DDR_DQSN1
DDR_DQS2
DDR_DQSN2
DDR_DQS3
DDR_DQSN3
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
1
2
3
4
5
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
R58
DNP
6
10
11
14
15
20
23
24
35
21
22
38
VDDIOM
12
37
34
39
D9
VCC
VCC
VCC_N.C
VCC_N.C
C50
100nF
D10
D11
D12
D13
D14
D16
N.C9
C13
TP13
SMD
DDR_VREF {4}
DDR_VREF
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
C51
100nF
C52
100nF
VCC_3V3
VDDIOM
C12
E13
R62
200R 1%
VDDIODDR
1
2
DDR_CALN
DDR_CALP
13
36
25
48
VSS
VSS
VSS_N.C
VSS_N.C
L12
NCS3
L13
180ohm at 100MHz
NCS3
R63
200R 1%
L17
K11
NRD
NWE
NRD
NWE_NWR0
L18
NANDRDY
NANDRDY
http://arm.embedinfo.com
Title:
SAMA5D3x-CM
Size:
A3
Document Number:
SAMA5D3x-II&NOR&NAND
Rev:
D
Draw By: Zhu Xueliang Date: Wednesday, September 19, 2012
1
Sheet: 3 of 7
5
4
3
2
5
4
3
2
1
D
C
B
A
D
C
B
A
{3} DDR_D[0..31]
{3} DDR_A[0..13]
MN8
MN9
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DDR2 SDRAM
DDR2 SDRAM
MT47H128M16RT
MT47H128M16RT
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
{3}
{3}
{3}
DDR_BA0
DDR_BA1
DDR_BA2
BA0
BA1
BA2
BA0
BA1
BA2
VDDIODDR
VDDIODDR
VDDIODDR
A1
E1
J9
M9
R1
A1
E1
J9
M9
R1
VDDIODDR
R93 DNP
C53 100nF
C55 100nF
C57 100nF
C59 100nF
C61 100nF
C54 100nF
C56 100nF
C58 100nF
C60 100nF
C62 100nF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
K9
R91 DNP
K9
ODT
ODT
R92
0R
R94 0R
DDR_CKE
K2
DDR_CKE
K2
{3}
DDR_CKE
CKE
CKE
J1
J1
C63 100nF
C64 100nF
VDDL
VDDL
DDR_CLK
DDR_CLKN
J8
K8
DDR_CLK
DDR_CLKN
J8
K8
{3}
{3}
DDR_CLK
DDR_CLKN
CK
CK
CK
CK
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
C65 100nF
C67 100nF
C69 100nF
C71 100nF
C73 100nF
C75 100nF
C77 100nF
C79 100nF
C81 100nF
C83 100nF
C66 100nF
C68 100nF
C70 100nF
C72 100nF
C74 100nF
C76 100nF
C78 100nF
C80 100nF
C82 100nF
C84 100nF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR_CS
L8
DDR_CS
L8
{3}
DDR_CS
CS
CS
DDR_CAS
DDR_RAS
L7
K7
DDR_CAS
DDR_RAS
L7
K7
{3}
{3}
DDR_CAS
DDR_RAS
CAS
RAS
CAS
RAS
DDR_WE
K3
DDR_WE
K3
{3}
{3}
DDR_WE
WE
WE
J2
DDR_VREF
J2
DDR_VREF
VREF
VREF
B7
A8
B7
A8
DDR_DQS1
{3}
{3}
DDR_DQS3
DDR_DQS2
UDQS
UDQS
UDQS
UDQS
A3
E3
J3
N1
P9
A3
E3
J3
N1
P9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C85
100nF
C86
100nF
4.7K
4.7K
R98 4.7K
R99 4.7K
R100
R101
F7
E8
F7
E8
{3}
DDR_DQS0
LDQS
LDQS
LDQS
LDQS
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
B3
F3
B3
F3
{3}
{3}
DDR_DQM1
DDR_DQM0
{3}
{3}
DDR_DQM3
DDR_DQM2
UDM
LDM
UDM
LDM
A2
E2
R3
R7
A2
E2
R3
R7
RFU1
RFU2
RFU3
RFU4
RFU1
RFU2
RFU3
RFU4
DDR2 SDRAM
VDDIODDR
L8
10uH/150mA
TP22
SMD
C87
4.7uF
R64
C88
1R
R65
1.5K 1%
100nF
DDR_VREF
DDR_VREF {3}
C89
4.7uF
C90
100nF
R66
1.5K 1%
http://arm.embedinfo.com
Title:
SAMA5D3x-CM
Size:
A3
Document Number:
4Gb DDR2
Rev:
D
Draw By: Zhu Xueliang Date: Wednesday, September 19, 2012
1
Sheet: 4 of 7
5
4
3
2
5
4
3
2
1
VDDIOP1
R67
470K
MN10
AT25DF321A
VDDIOP1
D
C
B
A
D
C
B
A
PA[0..31] {7}
PC[0..31] {7}
MN2A
SAMA5D3x_BGA324
MN2C
SAMA5D3x_BGA324
PD11
PD10
PD12
(SPI0_MOSI) R68
(SPI0_MIS0) R69
(SPI0_SPCK) R70
0R
0R
0R
5
2
6
8
SI
VCC
SO
SCK
C91
100nF
E3
F5
D2
F4
D1
J10
G4
J9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
D8
A4
E8
A3
A2
F8
B3
G8
B4
F7
A1
D7
C6
E7
B2
F6
B1
E6
C3
D6
C4
D5
C2
G9
C1
H10
H9
D4
H8
G5
D3
E4
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
3
7
PA0_LCDDAT0
PC0_ETX0
WP
HOLD
PA1_LCDDAT1
PA2_LCDDAT2
PA3_LCDDAT3
PA4_LCDDAT4
PA5_LCDDAT5
PA6_LCDDAT6
PA7_LCDDAT7
PA8_LCDDAT8
PA9_LCDDAT9
PA10_LCDDAT10
PA11_LCDDAT11
PA12_LCDDAT12
PA13_LCDDAT13
PA14_LCDDAT14
PA15_LCDDAT15
PA16_LCDDAT16
PA17_LCDDAT17
PA18_LCDDAT18
PA19_LCDDAT19
PA20_LCDDAT20
PA21_LCDDAT21
PA22_LCDDAT22
PA23_LCDDAT23
PA24_LCDPWM
PA25_LCDDISP
PA26_LCDVSYNC
PA27_LCDHSYNC
PA28_LCDPCK
PA29_LCDDEN
PA30_TWD0
PC1_ETX1
PC2_ERX0
PC3_ERX1
PC4_ETXEN
PC5_ECRSDV
PC6_ERXER
PC7_EREFCK
PC8_EMDC
PC9_EMDIO
PC10
1
CS
4
GND
JP1
F3
J8
PA8
PA9
PC8
PC9
VDDIOP1
E2
K8
F2
G6
E1
H5
H3
H6
H4
H7
H2
J6
G2
J5
F1
J4
G3
J3
G1
K4
H1
K3
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
SERIAL DATAFLASH
R71
10K
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
MN11
NL17SZ126
VDDIOP1
OE_Dataflash
PD13
1
2
3
5
{3} OE_Nandflash
OE
IN
VCC
D1
4
C92
100nF
OUT
BAT54C
GND
{7} BOOT_CS_OFF
PC27
PC28
PC29
PC30
PA31_TWCK0
PC31
VDDIOM
PB[0..31] {6,7}
PD[0..31] {7}
R72
1.5K
MN2B
SAMA5D3x_BGA324
MN2D
SAMA5D3x_BGA324
MN12
DS2431P+
T2
N7
T3
N6
P5
T4
R4
U1
R5
P3
R6
V3
P6
V1
R7
U3
P7
V2
V5
T6
N8
U4
M7
U5
M8
T5
N9
V4
M9
P8
M10
R9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
K5
P1
K6
R1
L7
P2
L8
R2
K7
U2
K9
M5
K10
N4
L9
N3
L10
N5
M6
T1
N2
M3
M2
L3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB0_GTX0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
3
4
5
6
PB1_GTX1
PB2_GTX2
PB3_GTX3
PB4_GRX0
PB5_GRX1
PB6_GRX2
PB7_GRX3
PB8_GTXCK
PB9_GTXEN
PB10_GTXER
PB11_GRXCK
PB12_GRXDV
PB13_GRXER
PB14_GCRS
PB15_GCOL
PB16_GMDC
PB17_GMDIO
PB18_G125CK
PB19_GTX4
PB20_GTX5
PB21_GTX6
PB22_GTX7
PB23_GRX4
PB24_GRX5
PB25_GRX6
PB26_GRX7
PB27
NC1
PE25
R73
0R
2
IO
NC2
NC3
NC4
PB8
PB9
PD8
PD9
PD9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
1-WIRE EEPROM
VCC_3V3
{3,7} PE[23..31]
R74
470R
D2
Blue
PE25
PE24
M1
N1
L1
R75
100K
L2
K1
K2
J1
PB28
PB29
PB30
PB31
1
J2
R76
470R
D3
red
2
3
Q1
IRLML2502
LED
http://arm.embedinfo.com
Title:
SAMA5D3x-CM
Size:
A3
Document Number:
SAMA5D3x-III&DATAFLASH&1-WIRE,LED
Rev:
D
Draw By: Zhu Xueliang Date: Wednesday, September 19, 2012
1
Sheet: 5 of 7
5
4
3
2
5
4
3
2
1
AVDDL_PLL
R77
27R
D
C
B
A
D
C
B
A
NRST
{2,3,7}
+
C94
C95
C93
10uF
10nF
10nF
R78
R79
4.7K
1K
VDDIOP1
PB[0..31] {5,7}
R80
R81
R82
27R
27R
27R
G125CK
INT_GETHR PB25
GMDIO
PB18
L9
VDDIOP1 180ohm at 100MHz
AVDDH
PB17
1
2
VDDIOP1
+
C97
C98
10nF
C99
10nF
C96
10uF
10nF
R83
4.99K 1%
+
C100
10nF
C101
10nF
C102
10nF
C103
10uF
MN17
AVDDL
KSZ9021RN
VDDIOP1
+
C105
10nF
C106
10nF
C104
10uF
R90 R95 R96 R97
4.7K 4.7K 4.7K 4.7K
1
2
3
4
5
6
7
8
9
36
R84
R85
27R
27R
GMDC
GRXCK
PB16
PB11
AVDDH
MDC
35
{7}
{7}
ETH0_TX1+
ETH0_TX1-
TXRXP_A
TXRXM_A
AVDDL
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
AVDDL
RX_CLK
34
33
32
31
30
29
28
27
26
25
DVDDH
RX_DV
RXD0
RXD1
DVDDL
VSS
RXD2
RXD3
DVDDL
TX_EN
R102
27R
27R
27R
PB13
PB4
PB5
GRX_CTL
GRX0
GRX1
3
4
RR24C
RR24D
6
5
{7}
{7}
{7}
{7}
ETH0_RX1+
ETH0_RX1-
ETH0_TX2+
ETH0_TX2-
KSZ9021RN
48-pin QFN
RR25A
RR25B
1
2
8
7
27R
27R
GRX2
GRX3
PB6
PB7
10
11
12
{7}
{7}
ETH0_RX2+
ETH0_RX2-
TXRXP_D
TXRXM_D
AVDDH
R87
27R
GTX_CTL PB9
DVDDL
VDDIOP1
+
C108
10nF
C109
10nF
C110
10nF
C111
10nF
C112
10nF
C113
10nF
C107
10uF
R88
R89
4.7K
27R
GTXCK
PB8
3
4
1
2
RR25C
RR25D
RR26A
RR26B
6
5
8
7
27R
27R
27R
27R
GTX3
GTX2
GTX1
GTX0
PB3
PB2
PB1
PB0
{7}
{7}
LED2
LED1
MN13
SC189ASKTRT
VCC_3V3
L14
AVDDL_PMOS
L10
AVDDL_PLL
LQM2HPN1R0MG0L
180ohm at 100MHz
1
1
2
3
5
4
2
VIN
GND
EN
LX
C120
10nF
C115
10uF
C114
C119
20pF
XI
R32
2K 1%
VOUT
+
C118
22uF
C116
47uF
L11
180ohm at 100MHz
1
AVDDL
C117
10nF
Y3
25MHz
R33
10K 1%
2
20pF
XO
L12
180ohm at 100MHz
1
DVDDL
2
http://arm.embedinfo.com
Title:
SAMA5D3x-CM
Size:
A3
Document Number:
ETHERNET
Rev:
D
Draw By: Zhu Xueliang Date: Friday, September 21, 2012
1
Sheet: 6 of 7
5
4
3
2
5
4
3
2
1
VCC_5V
VCC_5V
J1
1
3
5
7
9
2
4
6
8
VCC_5V_1
VCC_5V_2
VCC_5V_4
VBAT
PE29
PE30
PE31
GND2
VDDIOM_2
PC24
VDDBU
VCC_5V_3
GND1
PE23
PE24
PE25
PE23
PE24
PE25
PE26
PE29
PE30
PE31
{5}
PA[0..31]
C122
1uF
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PA0
PA1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VDDIOM
PE26
PA2
PA3
VDDIOM
VDDIOM_1
PC25
PC23
PC21
GND3
PC18
PC16
PC8
PC6
PC4
PC2
PC0
PC25
PC23
PC21
PC24
PC22
PC20
PC19
PC17
PC9
PA4
PA5
PA6
PA7
PA8
PA9
C123
4.7uF
D
C
B
A
D
C
B
A
PC22
PC20
PC19
PC17
PC9
PC7
GND4
PC5
PC3
PC18
PC16
PC8
PC6
PC4
PC2
PC0
PC7
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PC5
PC3
PC1
PC1
Enable_1
{2}
PWR_EN
BOOT_CS_OFF {5}
Enable_0
KEY
VCC_3V3
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
VCC_3V3
VCC_3V3_1
VCC_3V3_3
Enable_2
NC1
PE27
PC10
GND5
PC12
PC14
PC27
PC29
PC31
VDDIOP0_1
PA0
PA2
GND7
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
GND9
PA21
PA23
PA25
PA27
PA28
PA30
VDDANA_1
PD30
GND11
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
GND13
PD12
PD10
PD8
PD6
PD5
PD3
PD1
VDDIOP1_1
GND15
PB10
PB14
PB19
VCC_3V3_2
VCC_3V3_4
Enable_3
ADVREF
PE28
PC11
PC13
PC15
PC26
PC28
GND6
PC30
VDDIOP0_2
PA1
C124
10uF
PE[23..31] {3,5}
PE27
PC10
PE28
PC11
PC13
PC15
PC26
PC28
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
ADVREF
PC12
PC14
PC27
PC29
PC31
C125
1uF
PC30
VDDIOP0
VDDIOP0
PA0
PA2
PA1
PA3
PA4
PA6
PA8
PA10
PA3
PA4
PA6
PA8
PA10
GND8
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
GND10
PA29
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
{5,6}
PB[0..31]
PB10
PB13
PB14
PB15
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
PD[0..31] {5}
PA21
PA23
PA25
PA27
PA28
PA30
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PA29
PA31
VDDANA
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
PA31
VDDANA
VDDANA_2
PD31
PD29
PD27
PD25
PD23
GND12
PD21
PD19
PD17
PD15
PD13
PD11
PD9
PD7
GND14
PD4
PD2
PD0
VDDIOP1_2
PB13
PB12
PB15
PB20
PB22
GND16
PB25
PB27
PB29
PB31
PB30
PB26
PB28
GND20
DIBP
PD30
PD31
PD29
PD27
PD25
PD23
C126
1uF
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD21
PD19
PD17
PD15
PD13
PD11
PD9
{5}
PC[0..31]
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD12
PD10
PD8
PD6
PD5
PD3
PD1
PD7
PD4
PD2
PD0
VDDIOP1
VDDIOP1
R104
PC8
PC9
PB10
PB14
PB19
PB21
PB23
PB24
DNP
0R
PB13
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PB15
PB20
PB22
R105
PB12
PB21
PB23
PB24
PB25
PB27
PB29
PB31
PB30
PB26
PB28
GND17
USBA_DP
USBA_DM
GND18
USBB_DP
USBB_DM
GND19
USBC_DP
USBC_DM
GND_ETH1
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
GND_ETH2
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
GND23
LED2
{2}
{2}
HHSDPA
HHSDMA
{2}
{2}
HHSDPB
HHSDMB
{2}
{2}
HHSDPC
HHSDMC
DIBP
DIBN
{2}
{2}
DIBN
GND22
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
GND24
{6}
{6}
{6}
{6}
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
JTAGSEL {2}
WKUP
SHDN
BMS
NRST
NTRST
TDI
TCK
TMS
TDO
{2}
{2}
{2}
{2,3,6}
{2}
{2}
{2}
{2}
{2}
{6}
{6}
{6}
{6}
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
http://arm.embedinfo.com
{6}
{6}
LED2
LED1
LED1
Title:
SODIMM_2
SAMA5D3x-CM
Size:
A3
Document Number:
200-PIN SODIMM
Rev:
D
Draw By: Zhu Xueliang Date: Monday, September 17, 2012
1
Sheet: 7 of 7
5
4
3
2
4.4.2 CPU Module Revision E Schematics
This section contains the following schematics:
Main sheet
SODIMM 200
Power supply
CPU power supply
DDR2 interface
FI: NAND, NOR, Serial, I2C, 1-wire
Ethernet
USB, JTAG, LEDs
Bus interface
SAMA5D3x-EK User Guide [USER GUIDE]
35
11180B–ATARM–29-Oct-13
5
4
3
2
1
3V3 INPUT
VBAT
D
C
B
A
D
C
B
A
S
O
D
I
M
M
128Mb
NOR
ANALOG Reference
USB A,B,C
DIB
FLASH
ATMEL
C
O
N
N
E
C
T
O
R
4Gb
DDR2
SDRAM
ARMA5 PROCESSOR
ATSAMA5D3x-CU
EBI
ICE
2Gb
NAND
FLASH
PIO A,...E
PIO A&D
PIO A,...E
PIO B&E
SERIAL
DATA
FLASH
10/100/1000 FAST
ETHERNET
ONE WIRE
EEPROM
TWO LED
PIO C
E
D
CW
CS
15-Apr-13
28-Sep-12
CW 30-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12 CW 3-Feb-12
C
B
CS
CS
A
CS
DES.
11-Nov-11 CW 12-Nov-11
REV MODIF.
DATE
VER.
DATE
SAMA5D3x-CM
BLOCK DIAGRAM
SCALE
REV.
S1HEET
7
1/1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
TP17
SMD
L12
VCC_3V3
VDDIOP1
180ohm at 100MHz
1
2
VCC_1V2
MN8
RT9018B-18GSP
VCC_3V3
C97
C73
100nF
NTRST
TDI
TP11
SMD
L11
180ohm at 100MHz
6
3
4
100nF
VOUT
VIN
VDD
1
2
C24
100nF
C23
10uF
D
C
B
A
D
C
B
A
C26
10uF
R31
TP14
SMD
C19
10nF
1
7
5
2
27K 1%
PGOOD
ADJ
NC
EN
TP2
PWR_EN
TMS
TP8
SMD
SMD
VDDBU
R30
100K
R29
47K 1%
R32
DNP
VDDIOP0
C75
VDDIOP0
TCK
TP21
SMD
TP16
SMD
TP13
SMD
C63
100nF
C46
100nF
C48
100nF
C79
100nF
C52
100nF
C80
100nF
C82
100nF
C81
100nF
C72
100nF
TDO
NRST
TP9
SMD
C101
4.7uF
100nF
VCC_3V3
VCC_3V3
TP4
VDDBU
SMD
VDDIODDR
MN7
RT8010GQW
VIN
VCC_3V3
TP1
SMD
2.2uH L6
R54
4
6
3
2
DNP
LX
10uF
C27
TP3
SMD
R28
200K 1%
C14
100nF
C13
10uF
C15
22pF
T9
R8
N10
P9
M11
P11
V9
VDDIOM
{7}
JTAGSEL
TDI
TMS
TCK
TDO
JTAGSEL
TDI
TMS
TCK
TDO
NTRST
NRST
TDI
TMS
TCK
TDO
NTRST
NRST
P12
T16
PWR_EN
{7}
{7}
{7}
{7}
{7}
PWR_EN
VDDIOM_1
VDDIOM_2
FB
EN
C51
100nF
C61
100nF
R27
100K 1%
{7}
R33
DNP
NTRST
{3,6,7} NRST
D13
F14
G10
G13
H11
VCC_3V3
VDDIODDR_1
VDDIODDR_2
VDDIODDR_3
VDDIODDR_4
VDDIODDR_5
R15
10K
U15
U9
TST
BMS
C74
100nF
C60
100nF
C71
C54
100nF
C4
100nF
{7}
BMS
100nF
R55
R53
100K
100K
VDDIOP0
VDDBU
WKUP
SHDN
T10
T12
{7}
{7}
WKUP
SHDN
WKUP
SHDN
FUSE_2V5
VCC_3V3
C11
20pF
R3
VDDFUSE
U8
V8
XIN
C86
100nF
C17
100nF
Y2
12MHz
U11
U13
R10
VDDOSC
VDDUTMII
VDDPLLA
VDDOSC
WKUP
SHDN
TP10
SMD
C10
C6
20pF
20pF
XOUT
XIN32
XOUT32
L10
MN4H
ATSAMA5D3x-CU
VDDOSC
10uH/150mA
VCC_3V3
TP18
SMD
TP5
SMD
L2
TP19
SMD
U16
V16
VDDPLLA
10uH/150mA
VCC_1V2
C91
100nF
C90
100nF
R21
1R
Y1
20pF
32.768 kHz
C5
100nF
C3
R17
1R
100nF
C8
C100
4.7uF
U6
V6
VCC_1V2
0R
C2
4.7uF
{7}
{7}
DIBN
DIBP
DIBN
DIBP
V13
VDDUTMIC
VDDANA
ADVREF
R16
C66
100nF
TP12
V10
U10
{7}
{7}
HHSDMA
HHSDPA
HHSDMA
HHSDPA
SMD
L5
VDDANA
10uH/150mA
VCC_3V3
V12
U12
L6
L5
GNDUTMI
{7}
{7}
HHSDMB
HHSDPB
HHSDMB
HHSDPB
C106
100nF
C16
100nF
R25
1R
V14
U14
{7}
{7}
HHSDMC
HHSDPC
HHSDMC
HHSDPC
ADVREF
TP15 C110
SMD
R11
4.7uF
VBG
C85
100nF
R52
C62
10pF
5.62K 1%
SUP1
GNDUTMI
GNDUTMI
MN11
XC6206P252MR-G
Voltage Detector
DNP
CA89405MF
FUSE_2V5
VCC_3V3
R51
0R
E
D
C
B
CW
CS
CS
15-Apr-13
28-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12
11-Nov-11 CW 12-Nov-11
DATE
2
1
Vo
CW 30-Sep-12
3
C89
1uF
Vin
Vss
GNDUTMI
CS
CW
3-Feb-12
C107
1uF
A
CS
DES.
REV MODIF.
VER.
DATE
SAMA5D3x-CM
SCALE
REV.
S2HEET
7
1/1
SAMA5D3x-I&POWER
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
MN4E
M_EBI_A0
TP7
MN4F
ATSAMA5D3x-CU
ATSAMA5D3x-CU
SMD
P13
R14
R13
V18
P14
U18
T18
R15
P17
P15
P18
R16
N16
R17
N17
R18
N18
P16
M18
N15
M15
N14
M17
M13
M16
N12
M14
M12
L13
L15
L14
L16
DDR_A[0..13] {4}
PE0_A0/NBS0
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
PE24
PE1_A1
PE2_A2
PE3_A3
PE4_A4
PE5_A5
PE6_A6
PE7_A7
PE8_A8
PE9_A9
B10
C11
A9
D11
B9
E10
D10
A8
C10
B8
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
D
C
B
A
D
C
B
A
MN10
JS28F128P33TF70A
FLASH_A1
FLASH_A2
FLASH_A3
FLASH_A4
FLASH_A5
FLASH_A6
FLASH_A7
FLASH_A8
FLASH_A9
FLASH_A10
FLASH_A11
FLASH_A12
FLASH_A13
FLASH_A14
FLASH_A15
FLASH_A16
FLASH_A17
FLASH_A18
FLASH_A19
FLASH_A20
FLASH_A21
FLASH_A22
FLASH_A23
29
25
24
23
22
21
20
19
8
7
6
5
4
3
2
1
55
18
17
16
11
10
9
34
36
39
41
47
49
51
53
35
37
40
42
48
50
52
54
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
M_EBI_D8
M_EBI_D9
M_EBI_D10
M_EBI_D11
M_EBI_D12
M_EBI_D13
M_EBI_D14
M_EBI_D15
PE10_A10
PE11_A11
PE12_A12
PE13_A13
A1
A2
A3
A4
A5
A6
A7
A8
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
F11
A7
D9
PE14_A14
A6
PE15_A15_SCK3
PE16_A16_CTS3
PE17_A17_RTS3
PE18_A18_RXD3
PE19_A19_TXD3
PE20_A20_SCK2
PE21_A21/NANDALE
PE22_A22/NANDCLE
PE23_A23_CTS2
PE24_A24_RTS2
PE25_A25_RXD2
PE26_NCS0_TXD2
PE27_NCS1_TIOA2
PE28_NCS2_TIOB2
PE29_NWR1/NBS1_TCLK2
PE30_NWAIT
PE31_IRQ_PWML1
DDR_D[0..31] {4}
H12
H17
H13
G17
G16
H15
F17
G15
F16
E17
G14
E16
D17
C18
D16
C17
B16
B18
C15
A18
C16
C14
D15
B14
A15
A14
E12
A11
B11
F12
A10
E11
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
M_EBI_A21
M_EBI_A22
M_EBI_A23
R12
R9
R8
27R
27R
27R
PE[23..31] {5,7}
PE25
PE26
PE27
PE28
PE29
PE30
PE31
R40
0R
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
56
46
WAIT
ADV#
R7
0R
0R
0R
0R
PE23
26
27
13
RFU1
RFU2
NC
R10
R11
R41
NANDCLE
NANDALE
NCS0
VDDIOM
R35
R36
R59
0R
45
44
15
CLK
100K
100K
RST#
WP#
VDDIOM
{2,6,7}
NRST
33
38
VCC
VCCQ
VDDIOM
30
32
14
C1
100nF
C12
100nF
CE#
OE#
WE#
NRD
NWE
12
28
31
VSS
VSS
VSS
43
R38
10K
VDDIOM
VPP
MN1
NL17SZ126
VDDIOM
NCS0
R37
470K
E9
B6
F9
1
2
3
5
4
DDR_BA0 {4}
DDR_BA1 {4}
DDR_BA2 {4}
{5} OE_Nandflash
DDR_BA0
DDR_BA1
DDR_BA2
OE
IN
VCC
NCS3
C32
100nF
OUT
G11
A5
DDR_RAS {4}
DDR_CAS {4}
DDR_RAS
DDR_CAS
GND
B7
B12
A12
MN3
DDR_CKE {4}
DDR_CLK {4}
DDR_CLKN {4}
DDR_CKE
DDR_CLK
DDR_CLKN
MT29F2G08ABAEAWP
NANDCLE
NANDALE
0R
16
17
8
18
9
29
30
31
32
41
42
43
44
26
27
28
33
40
45
46
47
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
CLE
ALE
RE
WE
CE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
C8
B5
NRD R4
NWE R3
NANDCE
DDR_CS {4}
DDR_WE {4}
DDR_CS
DDR_WE
0R
G12
E15
B15
D12
R39
470K
0R
470K
470K
VDDIOM
VDDIOM
DDR_DQM0 {4}
DDR_DQM1 {4}
DDR_DQM2 {4}
DDR_DQM3 {4}
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
MN4G
ATSAMA5D3x-CU
NANDRDY R6
7
R/B
R5
R2
19
WP
I/O8_N.C
I/O9_N.C
K12
M_EBI_D0
M_EBI_D1
M_EBI_D2
M_EBI_D3
M_EBI_D4
M_EBI_D5
M_EBI_D6
M_EBI_D7
M_EBI_D8
M_EBI_D9
M_EBI_D10
M_EBI_D11
M_EBI_D12
M_EBI_D13
M_EBI_D14
M_EBI_D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
E18
D18
G18
F18
B17
A17
B13
A13
K15
K14
K16
K13
K17
J12
K18
J14
J16
J13
J17
J15
J18
H16
H18
DDR_DQS0 {4}
DDR_DQS1 {4}
DDR_DQS2 {4}
DDR_DQS3 {4}
DDR_DQS0
DDR_DQSN0
DDR_DQS1
DDR_DQSN1
DDR_DQS2
DDR_DQSN2
DDR_DQS3
DDR_DQSN3
I/O10_N.C
I/O11_N.C
I/O12_N.C
I/O13_N.C
I/O14_N.C
I/O15_N.C
1
2
3
4
5
N.C1
N.C2
N.C3
N.C4
N.C5
N.C6
N.C7
N.C8
R1
DNP
6
10
11
14
15
20
23
24
35
21
22
38
VDDIOM
12
37
34
39
D9
VCC
VCC
VCC_N.C
VCC_N.C
C9
100nF
D10
D11
D12
D13
D14
D16
N.C9
C13
TP20
SMD
DDR_VREF {4}
DDR_VREF
N.C10
N.C11
N.C12
N.C13
N.C14
DNU1
DNU2
DNU3
C34
100nF
C33
100nF
VCC_3V3
VDDIOM
C12
E13
R43
200R 1%
VDDIODDR
1
2
DDR_CALN
DDR_CALP
13
36
25
48
VSS
VSS
VSS_N.C
VSS_N.C
L12
NCS3
L1
180ohm at 100MHz
NCS3
R18
200R 1%
L17
K11
NRD
NWE
NRD
NWE_NWR0
L18
NANDRDY
NANDRDY
E
D
C
B
A
CW
CS
CS
CS
CS
15-Apr-13
28-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12 CW 3-Feb-12
11-Nov-11 CW 12-Nov-11
DATE
CW 30-Sep-12
REV MODIF.
DES.
VER.
DATE
SAMA5D3x-CM
SCALE
REV.
S3HEET
7
1/1
SAMA5D3x-II&NOR&NAND
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
VDDIOP1
R71
470K
MN13
AT25DF321A
VDDIOP1
D
C
B
A
D
C
B
A
PA[0..31] {7}
PC[0..31] {7}
MN4A
ATSAMA5D3x-CU
MN4C
ATSAMA5D3x-CU
PD11
PD10
PD12
(SPI0_MOSI) R79
(SPI0_MIS0) R76
(SPI0_SPCK) R77
0R
0R
0R
5
2
6
8
SI
VCC
SO
SCK
C114
100nF
E3
F5
D2
F4
D1
J10
G4
J9
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
D8
A4
E8
A3
A2
F8
B3
G8
B4
F7
A1
D7
C6
E7
B2
F6
B1
E6
C3
D6
C4
D5
C2
G9
C1
H10
H9
D4
H8
G5
D3
E4
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
3
7
PA0_LCDDAT0
PC0_ETX0
WP
HOLD
PA1_LCDDAT1
PA2_LCDDAT2
PA3_LCDDAT3
PA4_LCDDAT4
PA5_LCDDAT5
PA6_LCDDAT6
PA7_LCDDAT7
PA8_LCDDAT8
PA9_LCDDAT9
PA10_LCDDAT10
PA11_LCDDAT11
PA12_LCDDAT12
PA13_LCDDAT13
PA14_LCDDAT14
PA15_LCDDAT15
PA16_LCDDAT16
PA17_LCDDAT17
PA18_LCDDAT18
PA19_LCDDAT19
PA20_LCDDAT20
PA21_LCDDAT21
PA22_LCDDAT22
PA23_LCDDAT23
PA24_LCDPWM
PA25_LCDDISP
PA26_LCDVSYNC
PA27_LCDHSYNC
PA28_LCDPCK
PA29_LCDDEN
PA30_TWD0
PC1_ETX1
PC2_ERX0
PC3_ERX1
PC4_ETXEN
PC5_ECRSDV
PC6_ERXER
PC7_EREFCK
PC8_EMDC
PC9_EMDIO
PC10
1
CS
4
GND
JP1
F3
J8
PA8
PA9
PC8
PC9
VDDIOP1
E2
K8
F2
G6
E1
H5
H3
H6
H4
H7
H2
J6
G2
J5
F1
J4
G3
J3
G1
K4
H1
K3
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
SERIAL DATAFLASH
R78
10K
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
MN12
NL17SZ126
VDDIOP1
OE_Dataflash
PD13
1
2
3
5
{3} OE_Nandflash
OE
IN
VCC
D3
4
C123
100nF
OUT
BAT54C
GND
{7} BOOT_CS_OFF
PC27
PC28
PC29
PC30
PA31_TWCK0
PC31
VDDIOM
PB[0..31] {6,7}
PD[0..31] {7}
R70
1.5K
MN4B
ATSAMA5D3x-CU
MN4D
ATSAMA5D3x-CU
MN14
DS2431P+
T2
N7
T3
N6
P5
T4
R4
U1
R5
P3
R6
V3
P6
V1
R7
U3
P7
V2
V5
T6
N8
U4
M7
U5
M8
T5
N9
V4
M9
P8
M10
R9
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
K5
P1
K6
R1
L7
P2
L8
R2
K7
U2
K9
M5
K10
N4
L9
N3
L10
N5
M6
T1
N2
M3
M2
L3
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PB0_GTX0
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
3
4
5
6
PB1_GTX1
PB2_GTX2
PB3_GTX3
PB4_GRX0
PB5_GRX1
PB6_GRX2
PB7_GRX3
PB8_GTXCK
PB9_GTXEN
PB10_GTXER
PB11_GRXCK
PB12_GRXDV
PB13_GRXER
PB14_GCRS
PB15_GCOL
PB16_GMDC
PB17_GMDIO
PB18_G125CK
PB19_GTX4
PB20_GTX5
PB21_GTX6
PB22_GTX7
PB23_GRX4
PB24_GRX5
PB25_GRX6
PB26_GRX7
PB27
NC1
PE25
R72
0R
2
IO
NC2
NC3
NC4
PB8
PB9
PD8
PD9
PD9
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
1-WIRE EEPROM
VCC_3V3
{3,7} PE[23..31]
R42
470R
D1
Blue
PE25
PE24
M1
N1
L1
R48
100K
L2
K1
K2
J1
PB28
PB29
PB30
PB31
1
J2
R44
470R
D2
red
2
3
Q1
IRLML2502
LED
E
D
C
B
A
CW
CS
CS
CS
CS
15-Apr-13
28-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12 CW 3-Feb-12
11-Nov-11 CW 12-Nov-11
DATE
CW 30-Sep-12
REV MODIF.
DES.
VER.
DATE
SAMA5D3x-CM
SCALE
REV.
S4HEET
7
1/1
SAMA5D3x-III&DATAFLASH&1-WIRE,LED
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
D
C
B
A
D
C
B
A
{3} DDR_D[0..31]
{3} DDR_A[0..13]
MN2
MN5
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DDR2 SDRAM
DDR2 SDRAM
MT47H128M16RT
MT47H128M16RT
DQ9
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
DDR_BA0
DDR_BA1
DDR_BA2
L2
L3
L1
{3}
{3}
{3}
DDR_BA0
DDR_BA1
DDR_BA2
BA0
BA1
BA2
BA0
BA1
BA2
VDDIODDR
VDDIODDR
VDDIODDR
A1
E1
J9
M9
R1
A1
E1
J9
M9
R1
VDDIODDR
R50
C35 100nF
C49 100nF
C55 100nF
C57 100nF
C36 100nF
C87 100nF
C84 100nF
C68 100nF
C92 100nF
C44 100nF
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
K9
R67 DNP
K9
DNP
ODT
ODT
R66
0R
0R
R49
DDR_CKE
K2
DDR_CKE
K2
{3}
DDR_CKE
CKE
CKE
J1
J1
C38 100nF
C93 100nF
VDDL
VDDL
DDR_CLK
DDR_CLKN
J8
K8
DDR_CLK
DDR_CLKN
J8
K8
{3}
{3}
DDR_CLK
DDR_CLKN
CK
CK
CK
CK
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
C56 100nF
C39 100nF
C45 100nF
C77 100nF
C58 100nF
C53 100nF
C50 100nF
C59 100nF
C43 100nF
C37 100nF
C95 100nF
C88 100nF
C67 100nF
C64 100nF
C83 100nF
C69 100nF
C94 100nF
C70 100nF
C78 100nF
C65 100nF
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
DDR_CS
L8
DDR_CS
L8
{3}
DDR_CS
CS
CS
DDR_CAS
DDR_RAS
L7
K7
DDR_CAS
DDR_RAS
L7
K7
{3}
{3}
DDR_CAS
DDR_RAS
CAS
RAS
CAS
RAS
DDR_WE
K3
DDR_WE
K3
{3}
{3}
DDR_WE
WE
WE
J2
DDR_VREF
J2
DDR_VREF
VREF
VREF
B7
A8
B7
A8
DDR_DQS1
{3}
{3}
DDR_DQS3
DDR_DQS2
UDQS
UDQS
UDQS
UDQS
A3
E3
J3
N1
P9
A3
E3
J3
N1
P9
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
C40
100nF
C76
100nF
4.7K
4.7K
R47 4.7K
R46 4.7K
R57
R56
F7
E8
F7
E8
{3}
DDR_DQS0
LDQS
LDQS
LDQS
LDQS
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
B3
F3
B3
F3
{3}
{3}
DDR_DQM1
DDR_DQM0
{3}
{3}
DDR_DQM3
DDR_DQM2
UDM
LDM
UDM
LDM
A2
E2
R3
R7
A2
E2
R3
R7
RFU1
RFU2
RFU3
RFU4
RFU1
RFU2
RFU3
RFU4
DDR2 SDRAM
VDDIODDR
L3
10uH/150mA
TP6
C7
4.7uF
R45
C42
1R
R13
1.5K 1%
SMD
100nF
DDR_VREF
DDR_VREF {3}
C47
4.7uF
C41
100nF
R14
1.5K 1%
E
D
CW
CS
15-Apr-13
28-Sep-12
CW 30-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12 CW 3-Feb-12
C
B
CS
CS
A
CS
DES.
11-Nov-11 CW 12-Nov-11
REV MODIF.
DATE
VER.
DATE
SAMA5D3x-CM
4Gb DDR2
SCALE
REV.
S5HEET
7
1/1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
AVDDL_PLL
R26
27R
D
C
B
A
D
C
B
A
NRST
{2,3,7}
+
C109
10nF
C112
10nF
C125
10uF
R69
R68
4.7K
1K
VDDIOP1
PB[0..31] {5,7}
R24
R23
R22
27R
27R
27R
G125CK
INT_GETHR PB25
GMDIO
PB18
L13
VDDIOP1 180ohm at 100MHz
AVDDH
PB17
1
2
VDDIOP1
+
C115
10nF
C122
10nF
C118
10nF
C121
10uF
R75
4.99K 1%
+
C105
10nF
C111
10nF
C99
10nF
C96
10uF
MN6
AVDDL
KSZ9021RNI
VDDIOP1
+
C120
10nF
C119
10nF
C124
10uF
R64 R63 R58 R61
4.7K 4.7K 4.7K 4.7K
1
2
3
4
5
6
7
8
9
36
R19
R20
27R
27R
GMDC
GRXCK
PB16
PB11
AVDDH
MDC
35
{7}
{7}
ETH0_TX1+
ETH0_TX1-
TXRXP_A
TXRXM_A
AVDDL
TXRXP_B
TXRXM_B
TXRXP_C
TXRXM_C
AVDDL
RX_CLK
34
33
32
31
30
29
28
27
26
25
DVDDH
RX_DV
RXD0
RXD1
DVDDL
VSS
RXD2
RXD3
DVDDL
TX_EN
R65
27R
27R
27R
PB13
PB4
PB5
GRX_CTL
GRX0
GRX1
RR1C
RR1D
3
4
6
5
{7}
{7}
{7}
{7}
ETH0_RX1+
ETH0_RX1-
ETH0_TX2+
ETH0_TX2-
KSZ9021RNI
48-pin QFN
RR2A
RR2B
1
2
8
7
27R
27R
GRX2
GRX3
PB6
PB7
10
11
12
{7}
{7}
ETH0_RX2+
ETH0_RX2-
TXRXP_D
TXRXM_D
AVDDH
R60
27R
GTX_CTL PB9
DVDDL
VDDIOP1
+
C103
10nF
C116
10nF
C102
10nF
C108
10nF
C98
10nF
C104
10nF
C126
10uF
R62
R34
4.7K
27R
GTXCK
PB8
RR2C
3
6
5
8
7
27R
27R
27R
27R
GTX3
GTX2
GTX1
GTX0
PB3
PB2
PB1
PB0
RR2D
RR3A
RR3B
4
1
2
{7}
{7}
LED2
LED1
MN9
C21
C18
20pF
XI
VCC_3V3
SC189ASKTRT
L4
AVDDL_PMOS
L8
AVDDL_PLL
LQM2HPN1R0MG0L
180ohm at 100MHz
1
2
3
5
4
1
2
VIN
GND
EN
LX
Y3
25MHz
C113
10nF
C25
10uF
R73
2K 1%
VOUT
+
C22
22uF
C20
47uF
L9
180ohm at 100MHz
AVDDL
20pF
XO
C117
10nF
R74
10K 1%
1
2
L7
180ohm at 100MHz
DVDDL
1
2
E
D
C
B
A
CW
CS
CS
CS
CS
15-Apr-13
28-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12 CW 3-Feb-12
11-Nov-11 CW 12-Nov-11
DATE
CW 30-Sep-12
REV MODIF.
DES.
VER.
DATE
SAMA5D3x-CM
ETHERNET
SCALE
REV.
S6HEET
7
1/1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
VCC_5V
VCC_5V
J1
1
3
5
7
9
2
4
6
8
VCC_5V_1
VCC_5V_2
VCC_5V_4
VBAT
PE29
PE30
PE31
GND2
VDDIOM_2
PC24
VDDBU
VCC_5V_3
GND1
PE23
PE24
PE25
PE23
PE24
PE25
PE26
PE29
PE30
PE31
{5}
PA[0..31]
C31
1uF
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
VDDIOM
C29
PE26
VDDIOM
VDDIOM_1
PC25
PC23
PC21
GND3
PC18
PC16
PC8
PC6
PC4
PC2
PC0
PC25
PC23
PC21
PC24
PC22
PC20
PC19
PC17
PC9
D
C
B
A
D
C
B
A
PC22
PC20
PC19
PC17
PC9
PC7
GND4
PC5
PC3
4.7uF
PC18
PC16
PC8
PC6
PC4
PC2
PC0
PA8
PA9
PC7
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PC5
PC3
PC1
PC1
Enable_1
{2}
PWR_EN
BOOT_CS_OFF {5}
Enable_0
KEY
VCC_3V3
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
VCC_3V3
VCC_3V3_1
VCC_3V3_3
Enable_2
NC1
PE27
PC10
GND5
PC12
PC14
PC27
PC29
PC31
VDDIOP0_1
PA0
PA2
GND7
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
GND9
PA21
PA23
PA25
PA27
PA28
PA30
VDDANA_1
PD30
GND11
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
GND13
PD12
PD10
PD8
PD6
PD5
PD3
PD1
VDDIOP1_1
GND15
PB10
PB14
PB19
VCC_3V3_2
VCC_3V3_4
Enable_3
ADVREF
PE28
PC11
PC13
PC15
PC26
PC28
GND6
PC30
VDDIOP0_2
PA1
PA3
PA4
PA6
PA8
PA10
GND8
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
GND10
PA29
C30
10uF
PE[23..31] {3,5}
PE27
PC10
PE28
PC11
PC13
PC15
PC26
PC28
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
ADVREF
PC12
PC14
PC27
PC29
PC31
C127
1uF
PC30
VDDIOP0
VDDIOP0
PA0
PA2
PA1
PA3
PA4
PA6
PA8
PA10
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
{5,6}
PB[0..31]
PB10
PB13
PB14
PB15
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
PD[0..31] {5}
PA21
PA23
PA25
PA27
PA28
PA30
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
98
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PA29
PA31
VDDANA
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
PA31
VDDANA
VDDANA_2
PD31
PD29
PD27
PD25
PD23
GND12
PD21
PD19
PD17
PD15
PD13
PD11
PD9
PD7
GND14
PD4
PD2
PD0
VDDIOP1_2
PB13
PB12
PB15
PB20
PB22
GND16
PB25
PB27
PB29
PB31
PB30
PB26
PB28
GND20
DIBP
PD30
PD31
PD29
PD27
PD25
PD23
C28
1uF
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PD21
PD19
PD17
PD15
PD13
PD11
PD9
{5}
PC[0..31]
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD12
PD10
PD8
PD6
PD5
PD3
PD1
PD7
PD4
PD2
PD0
VDDIOP1
VDDIOP1
R81
PC8
PC9
PB10
PB14
PB19
PB21
PB23
PB24
DNP
0R
PB13
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
PB15
PB20
PB22
R80
PB12
PB21
PB23
PB24
PB25
PB27
PB29
PB31
PB30
PB26
PB28
GND17
USBA_DP
USBA_DM
GND18
USBB_DP
USBB_DM
GND19
USBC_DP
USBC_DM
GND_ETH1
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
GND_ETH2
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
GND23
LED2
{2}
{2}
HHSDPA
HHSDMA
{2}
{2}
HHSDPB
HHSDMB
{2}
{2}
HHSDPC
HHSDMC
DIBP
DIBN
{2}
{2}
DIBN
GND22
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
GND24
{6}
{6}
{6}
{6}
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
JTAGSEL {2}
WKUP
SHDN
BMS
NRST
NTRST
TDI
TCK
TMS
TDO
{2}
{2}
{2}
{2,3,6}
{2}
{2}
{2}
{2}
{2}
{6}
{6}
{6}
{6}
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
E
D
C
B
A
CW
CS
CS
CS
CS
15-Apr-13
28-Sep-12
15-Mar-12 CW 16-Mar-12
1-Feb-12 CW 3-Feb-12
11-Nov-11 CW 12-Nov-11
DATE
CW 30-Sep-12
{6}
{6}
LED2
LED1
LED1
REV MODIF.
DES.
VER.
DATE
SODIMM_2
SAMA5D3x-CM
200-PIN SODIMM
SCALE
REV.
S7HEET
7
1/1
E
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
4.5
Ronetix Schematics
This section contains the schematics for the CM board manufactured by Ronetix:
Main sheet
SODIMM200
Power supply
CPU power supply
DDR2 interface
FI: NAND, NOR, Serial, I2C, 1-wire
Ethernet
USB, JTAG, LEDs
Bus interface
SAMA5D3x-EK User Guide [USER GUIDE]
43
11180B–ATARM–29-Oct-13
1
2
3
4
5
6
SCHEMATICS: SAMA5D3x-CM
SHEET #
1
SHEET NAME
MAIN
DATE:
DESCRIPTION
REVISION
2.0
STATUS
OPEN
SAMA5D3x-CM v2.0
SAMA5D3x-CM v2.0
15.03.2012
2
3
4
5
6
7
8
9
SODIM200
20.09.2012
2.0
CLOSE
POWER SUPPLY
CPU-POWER SUPPLY
DDR2 INTERFACE
Changes Rev2.0
1. SoDIMM200 change:
* PB13 pin 144 with 0R DNP
* PB12 pin 146 with 0R populated
2. VDD_CORE from 1.20V to 1.25V
3. US1 - From TPS71712DCKR to BU12TD3WG-TR and attribute DNP
4. Replaced Q2 with U15 SC189ASKTRT 1V0
Fl: NAND/NOR/SERIAL/I2C/1-WIRE
ETHERNET
5. Q1 from BSS138W(SOT323) to BSS138(SOT23)
6. C74 - from 47uF Tant to 22uF 0805
Added - C128 22uF 0805
C78 - from 47uF Tant to 22uF 0805
Added - C129 22uF 0805
C81 - from 47uF Tant to 22uF 0805
Added - C130 22uF 0805
C75 - from 47uF Tant to 22uF 0805
Added - C131 22uF 0805
USB/JTAG/LEDS
C80 - from 47uF Tant to 22uF 0805
Added - C132 22uF 0805
C92 - from 10u Tant to 10u 0805
BUS INTERFACE
7. R4 - Changed attribute Note from DNP to "empty"
8. Y1 changed to CM200C-32.768KDZF-UT
9. U6 changed to EN29GL128H-70BAIP
10. U8 changed to HY27UF082G2B-TPCB
Mechanical
Z6 Drill No plated 0.85mm
Z11 Passer 0.7 mm
Z12 Passer 0.7 mm
Z13 Passer 0.7 mm
Z14 Passer 0.7 mm
Z7 Drill No plated 0.85mm
Z5 Drill No plated 1.65mm
Z8 Drill No plated 1.65mm
Z9 Drill No plated 1.65mm
Z10 Drill No plated 1.65mm
Z1 Drill No plated 1.8 mm
Z2 Drill No plated 1.8 mm
Z3
Z4
Drill No plated 3.2 mm
Drill No plated 3.2 mm
PROJECT TITLE
SHEET TITLE
SAMA5D3x-CM
MAIN
Note: To each Signal Reference have one or more digits.
These are the numbers of sheets
to which is connected this signal.
FILE
SIZE
A4
SHEET NO
DROWN
ISSUED
OF
SAMA5D3x-CM v2.0f.scm
1
9
development tool
www.ronetix.at
REV
DATE
DESCRIPTION FILE
20.9.2012
1
2
3
4
5
6
A
B
C
D
CN1 Power Supply 2.5V
SODIM200_PCB_PADS
VCC 5V
VCC 5V
1
Vbat
A1
2
VCC 5V
VCC 5V
B1
B2
3
A2
4
5
A3
6
B3
B4
PE23/A23_NOR/CTS2
PE24/RTS2
7
6
A4
8
PE29/NWR1(NBS1)/TCLK2
PE30/NWAIT
6
6
6
9
6;8
6;8
6
A5
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
B5
PE25/RXD2/1-Wire
PE26/NCS0/TXD2
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
A6
PE31/IRQ/PWML1
B6
A7
B7
VDD_IOM
A8
B8
VDD_IOM
PC25/SPI1_NPCS0
PC23/SPI1_MOSI
PC21/RD0
9
9
9
A9
PC24/SPI1_SPCK
PC22/SPI1_MISO
PC20/RF0
B9
9
9
9
9
9
9
9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
PC19/RK0
PC18/TD0
9
9
9
9
9
9
9
3
PC17/TF0
PC16/TK0
PC9/EMDIO
PC8/EMDC/TCLK5
PC6/ERXER/TIOA5
PC4/ETXEN/TIOB4
PC2/ERX0/TCLK3
PC0/ETX0/TIOA3
POWER_ENABLE
PC7/EREFCK/TIOB5
PC5/ECRSDV/TCLK4
PC3/ERX1/TIOA4
9
9
9
6
PC1/ETX1/TIOB3
Enable_0
Enable_1
CS_BOOT_DISABLE
3V3
3V3
C1
41
43
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
A32
A33
A34
A35
A36
A37
A38
A39
A40
A41
A42
A43
A44
A45
A46
A47
A48
A49
A50
A51
A52
A53
A54
A55
A56
A57
A58
A59
A60
A61
A62
A63
A64
A65
A66
A67
A68
A69
A70
A71
A72
A73
A74
A75
A76
A77
A78
A79
A80
A81
A82
A83
A84
A85
A86
A87
A88
A89
A90
A91
A92
A93
A94
A95
A96
A97
A98
A99
A100
42
44
C2
100n/10V
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
B32
B33
B34
B35
B36
B37
B38
B39
B40
B41
B42
B43
B44
B45
B46
B47
B48
B49
B50
B51
B52
B53
B54
B55
B56
B57
B58
B59
B60
B61
B62
B63
B64
B65
B66
B67
B68
B69
B70
B71
B72
B73
B74
B75
B76
B77
B78
B79
B80
B81
B82
B83
B84
B85
B86
B87
B88
B89
B90
B91
B92
B93
B94
B95
B96
B97
B98
B99
B100
100n/10V
Enable_2
45
GND
46
Enable_3
GND
47
48
ADVREF
4
6
9
9
9
9
9
PE27/NCS1/TIOA2/LCDDAT22
PC10/MCI2_CDA//LCDDAT20
49
6
9
50
PE28/NCS2/TIOB2/LCDDAT23
PC11/MCI2_DA0//LCDDAT19
51
52
53
54
PC13/MCI2_DA2/TIOB1/LCDDAT17
PC15/MCI2_CK/PCK2/LCDDAT21
PC26/SPI1_NPCS1/TWD1/ISI_D11
PC28/SPI1_NPCS3/PWMFI0/ISI_D9
PC12/MCI2_DA1/TIOA1/LCDDAT18
PC14/MCI2_DA3/TCLK1/LCDDAT16
PC27/SPI1_NPCS2/TWCK1/ISI_D10
PC29/URXD0/PWMFI2/ISI_D8
PC31/FIQ/PWMFI1
55
9
9
9
9
9
56
57
58
59
60
61
62
63
64
PC30/UTXD0//ISI_PCK
9
65
VDD_IOP0
66
VDD_IOP0
PA0/LCDDAT0
67
9
9
68
PA1/LCDDAT1
9
9
9
9
9
9
PA2/LCDDAT2
69
70
PA3/LCDDAT3
PA4/LCDDAT4
PA6/LCDDAT6
PA8/LCDDAT8
PA10/LCDDAT10
71
72
PA5/LCDDAT5
73
9
9
9
9
9
9
9
9
74
PA7/LCDDAT7
75
76
PA9/LCDDAT9
77
78
PA11/LCDDAT11
79
80
PA12/LCDDAT12
81
82
PA13/LCDDAT13
PA15/LCDDAT15
9
9
9
9
9
9
9
9
PA14/LCDDAT14
83
84
PA16/LCDDAT16/ISI_D0
PA18/LCDDAT18/TWD2/ISI_D2
85
86
PA17/LCDDAT17/ISI_D1
PA19/LCDDAT19/TWCK2/ISI_D3
PA20/LCDDAT20/PWMH0
PA22/LCDDAT22/PWMH1
PA24/LCDPWM
87
88
89
90
PA21/LCDDAT21/PWML0/ISI_D5
PA23/LCDDAT23/PWML1/ISI_D7
PA25/LCDDISP
91
9
9
9
9
9
9
92
93
94
95
96
PA26/LCDVSYNC
PA27/LCDHSYNC
97
98
PA28/LCDPCK
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PA29/LCDDEN
9
9
PA30/TWD0/URXD1/ISI_VSYNC
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
PA31/TWCK0/UTXD1/SI_HSYNC
VDD_ANA
VDD_ANA
PD30/AD10
9
PD31/AD11
9
9
9
9
9
PD29/AD9
PD27/AD7
PD25/AD5
PD23/AD3
PD28/AD8
9
9
9
9
9
9
9
9
PD26/AD6
PD24/AD4
PD22/AD2
PD20/AD0
PD21/AD1
PD19/ADTRG
9
9
PD18/TXD0
PD16/RTS0/SPI0_NPCS3/PWMFI3
PD14/SCK0/SPI0_NPCS1/CANRX0
PD17/RXD0
9
PD15/CTS0/SPI0_NPCS2/CANTX0
PD13/SPI0_CS0
9
6;9
6;9
9
PD12/SPI0_SPCK
6;9
6;9
9
PD11/SPI0_MOSI
PD10/SPI0_MISO
PD9/MCI0_CK
PD8/MCI0_DA7//PWML3
PD6/MCI0_DA5/TIOB0/PWML2
PD5/MCI0_DA4/TIOA0/PWMH2
PD3/MCI0_DA2
PD7/MCI0_DA6/TCLK0/PWMH3
9
9
9
PD4/MCI0_DA3
PD2/MCI0_DA1
PD0/MCI0_CDA
9
9
9
9
PD1/MCI0_DA0
9
VDDIOP1
VDD_IOP1
VDDIOP1
R78
VDD_IOP1
0R DNP
PB13/GRXER/PWML3
PB12/RX_DV
0 4 0 2
0 4 0 2
7
7
7
7
7
PB10/GTXER/RF1
7
7
7
7
7
7
R74
0R
PB14/GCRS/CANRX1
PB19/MCI1_CDA/GTX4
PB21/MCI1_DA1/GTX6
PB23/MCI1_DA3/GRX4
PB24/MCI1_CK/GRX5
PB15/GCOL/CANTX1
PB20/MCI1_DA0/GTX5
PB22/MCI1_DA2/GTX7
PB25/SCK1/GRX6
7
PB27/RTS1/PWMH1
7
USBA_DP
USBA_DM
8
8
PB29/TXD1
7
PB31/DTXD
7
PB30/DRXD
7
USBB_DP
USBB_DM
8
8
PB26/CTS1/GRX7
7
PB28/RXD1
7
USBC_DP
USBC_DM
8
8
DIBP
8
DIBN
8
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
7
7
7
7
JTAGSEL
8
WKUP
8
SHDN
8
BMS
8
NRST
6;7;8
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
7
7
7
7
NTRST
TDI/SWD
8
8
8
8
8
TCK/SWCLK
TMS/SWDIO
TDO
LED2
LED1
7
7
RTCK
GND
SAMA5D3x-CM
GND
MECHANICAL KEYING SODDIM200 :
PROJECT TITLE
SHEET TITLE
Power Supply 2.5V -> distance between pin 39 and center notch = 1.80mm
Power Supply 1.8V -> distance between pin 39 and center notch = 2.70mm
SODIM200
FILE
SIZE
A4
SHEET NO
DROWN
ISSUED
OF
SAMA5D3x-CM v2.0f.scm
2
9
development tool
www.ronetix.at
REV
DATE
DESCRIPTION FILE
20.9.2012
A
B
C
D
1
2
3
4
5
6
Soft-Start Time
Typ
Min
100 us
EN Input High Threshold
EN Input Low Threshold
1.2
V
V
Max 0.4
SEE TABLE 1
VDD_CORE
RS1=(Vout-1)xRS2
TABLE 1
3V3
VDD_CORE
1.0V
1.2V
1.25V
2k5ohm 1%
10kOhm 1%
U1
L1
1
5
4
VIN
LX
RS1
RS2
US1
0R (JUMP)
DNP
2kOhm 1%
2k49ohm 1%
3V3
LQM2HPN1R0MG0L
10kOhm 1%
BU12TD3WG-TR
C3
2
GND
C4
22u/6V3
BU10TD3WG-TR
RS1
0402
22u/6V3
GND
3
EN
VOUT
R1
RS1
2k49/1%
100k
GND
RS2
GND
SC189ASKTRT 1V0
C5
10k/1%
POWER_ENABLE
SEE TABLE 1
2;3
GND
VDDIODDR
C7
3V3
U2
L2
1
5
4
VIN
GND
EN
LX
LQM2HPN1R0MG0L
C6
2
22u/6V3
R3 5k1/1%
0402
22u/6V3
GND
3
VOUT
GND
GND
SC189ASKTRT 1V0
C8
R2
6k34/1%
3V3
VDDFUSE
U13
MCP1700T-2502E/TT
GND
3
1
In
Out
GND
2
VDD_CORE
C123
C124
1uF/10V
1uF/10V
VDD_PLL
3V3
R4
0R
GND
GND
GND
TP1 3V3
3V3
US1 DNP
TP2 VDD_CORE
TP3 VDDIODDR
TP4 VDD_IOP0
TP5 VDD_IOP1
TP6 VDD_IOM
TP7 VDD_ANA
TP8 GND
VDD_CORE
VDDIODDR
VDD_IOP0
VDD_IOP1
VDD_IOM
1
5
4
VIN
VOUT
C9
2
GND
STBY
C10
1uF/10V
3
NC
1uF/10V
GND
GND
BU12TD3WG-TR
C11
10n/25V
VDD_ANA
OR BU10TD3WG-TR
SEE TABLE 1
Start Time
Typ
Min
50 us
GND
GND
GND
EN Input High Threshold
EN Input Low Threshold
1.2
V
V
Max 0.3
POWER_ENABLE
TP9 POWER_ENABLE
2;3
VDD_IOP0
VDD_IOP1
VDD_IOM
VDD_ANA
3V3
R5
R6
R7
R8
0R
0R
0R
0R
0603
0603
0603
0603
SODIM200 (65-66)
SODIM200 (141-142)
SODIM200 (15-16)
SODIM200 (103-104)
GND pins are provided and should be
connected as shortly as possible
to the system ground plane.
PROJECT TITLE
SHEET TITLE
SAMA5D3x-CM
POWER SUPPLY
FILE
SIZE
A4
SHEET NO
OF
SAMA5D3x-CM v2.0f.scm
3
9
development tool
www.ronetix.at
REV
DATE
DESCRIPTION FILE
DROWN
ISSUED
20.9.2012
1
2
3
4
5
6
1
2
3
4
5
6
ADVREF
TP10ADVREF
TP11GND
2;4
(3V3)
GND
VDD_IOM
VDD_IOP0 VDD_IOP1
VDD_CORE
U3-A
C12
C13
100n/10V
100n/10V
T16
C5
C7
C14
C16
C15
C18
C17
C19
C23
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
VDDIOM
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
VDDCORE
P12
VDDIOM
D14
T15
U17
V7
T17
J11
GNDIOM
GNDIOM
C20
C22
C21
C24
100n/10V
100n/10V
100n/10V
100n/10V
V11
G7
T7
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
M4
C9
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GNDCORE
GND
L11
N13
T8
U7
N11
J7
T14
V17
A16
GNDIOP
GNDIOP
GNDIOP
GNDIOP
GND
VDDIODDR
GND
Vbat
E5
D13
F14
G10
G13
H11
C26
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
VDDIODDR
C25
100n/10V
V15
T13
C28
C27
C30
C29
VDDBU
GNDBU
VDD_ANA
GND
L3
top/bot
L6
L4
VDDANA
GNDANA
BLM15AG121SN1D
C33
VDDFUSE
E14
F10
F13
F15
H14
GNDIODDR
GNDIODDR
GNDIODDR
GNDIODDR
GNDIODDR
GND
C31
4u7/6V3/X5R
R3
P4
VDDFUSE
GNDFUSE
C32
470n/16V/Y5V
AGND
0603
GND
GND
top/bot
R10
P10
VDDPLLA
GNDPLL
R9 0R
3V3
L4
GND
VDD_PLL
470p/50V
C34
VDD_PLL
top/bot
top/bot
U11
T11
top/bot
VDDOSC
GNDOSC
V13
U13
R12
BLM15AG121SN1D
VDDUTMIC
VDDUTMII
GNDUTMI
L5
C36
L5
ADVREF
4u7/6V3/X5R
BLM15AG121SN1D
C105
100n/10V
C35
470n/16V/Y5V
SAMA5D3x
C39
C37
470p/50V
4u7/6V3/X5R
C38
ADVREF
2;4
GND
UTMI_GND
470n/16V/Y5V
A cooper for UTMI_GND net
cover all USB Components
C40
100n/10V
GND
3V3
L6
GND
BLM15AG121SN1D
R57
0603
C41
C43
4u7/6V3/X5R
470p/50V
0R
C42
GND
UTMI_GND
470n/16V/Y5V
UTMI_GND
PROJECT TITLE
SHEET TITLE
SAMA5D3x-CM
CPU-POWER SUPPLY
FILE
SIZE
A4
SHEET NO
DROWN
ISSUED
OF
SAMA5D3x-CM v2.0f.scm
4
9
development tool
www.ronetix.at
REV
DATE
DESCRIPTION FILE
20.9.2012
1
2
3
4
5
6
1
2
3
4
5
6
DDR_ADDR
DDR_A[0-13]
Address and control traces may not exceed 1.3 inches (33.0 mm).
Address and control traces must be length-matched to within 0.1 inch (2.54 mm).
Address and control traces must match the data group trace lengths to within 0.25 inches (6.35 mm).
U3-H
12.09.2012
B10 DDR_A0
Chenged U4 and U5
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
C11 DDR_A1
From MT47H64M16HR-25H to MT47H128M16RT-3:C
A9 DDR_A2
group 3AB
L3 & L8
Zo=50 ohms
minimizing crosstalk with [DQ, DQS, DQM]
D11 DDR_A3
B9 DDR_A4
E10 DDR_A5
D10 DDR_A6
DDR_ADDR
DDR_A[0-13]
DDR_DATA
group 2A
L3 & L8
DDR_ADDR
DDR_A[0-13]
DDR_DATA
group 2B
L3 & L8
A8 DDR_A7
DDR_D[0-15]
DDR_D[16-31]
C10 DDR_A8
U4
U5
B8 DDR_A9
F11 DDR_A10
A7 DDR_A11
D9 DDR_A12
A6 DDR_A13
H12
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
A
G8
G2
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_A0
DDR_A1
DDR_A2
DDR_A3
DDR_A4
DDR_A5
DDR_A6
DDR_A7
DDR_A8
DDR_A9
DDR_A10
DDR_A11
DDR_A12
DDR_A13
M8
M3
M7
N2
N8
N3
N7
P2
P8
P3
M2
P7
R2
R8
R3
R7
L2
B
G8
G2
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
A0
DQ0
A0
DQ0
DQ1
DDR_DATA
A1
DQ1
DQ2
A1
H7
H3
H1
H9
F1
F9
C8
C2
D7
D3
D1
D9
B1
B9
A2
A2
DQ2
DDR_D[0-31]
A3
DQ3
A3
DQ3
A4
DQ4
A4
DQ4
DDR_D0
DDR_D1
A5
DQ5
A5
DQ5
H17
A6
DQ6
A6
DQ6
H13
DDR_D2
A7
DQ7
A7
DQ7
G17
DDR_D3
A8
DQ8
A8
DQ8
G16
DDR_D4
A9
DQ9
A9
DQ9
H15
DDR_D5
A10
A11
A12
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
A10
A11
A12
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
F17
DDR_D6
G15
DDR_D7
F16
DDR_D8
RFU(A13)
RFU
RFU(A13)
RFU
E17
DDR_D9
G14
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
RFU
RFU
E16
DDR_BA0
DDR_BA1
DDR_BA2
DDR_BA0
DDR_BA1
DDR_BA2
5
5
5
BA0
5
5
BA0
D17
L3
F7
E8
B7
A8
DDR_DQS0
L3
F7
E8
B7
A8
DDR_DQS2
4k7
0402
BA1
LDQS
5
BA1
LDQS
5
5
C18
DDR_CKE
L1
R72
4k7
DDR_CKE
L1
R70
R71
0402
5
BA2
LDQS#/NU
5
5
BA2
LDQS#/NU
D16
DDR_DQS1
DDR_DQS3
4k7
0402
UDQS
5
UDQS
C17
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
K3
L7
K7
L8
K9
R73
4k7
DDR_WE#
DDR_CAS#
DDR_RAS#
DDR_CS#
K3
L7
K7
L8
K9
0402
5
5
5
5
WE#
CAS#
RAS#
CS#
UDQS#/NU
5
5
5
5
WE#
CAS#
RAS#
CS#
UDQS#/NU
B16
B18
F3
B3
DDR_DQM0
DDR_DQM1
F3
B3
DDR_DQM2
DDR_DQM3
LDM
UDM
5
5
GND
LDM
UDM
5
5
GND
C15
A18
ODT
ODT
VDDIODDR
R50
VDDIODDR
C16
A2
E2
VDDIODDR
A2
E2
VDDIODDR
NC
NC
NC
NC
0R
0R
R52
0R
0R
C14
DNP
K2
J8
DNP
K2
J8
0402
0402
0402
0402
CKE
CK
CKE
CK
D15
R51
R53
B14
DDR_CK
K8
A1
E1
J9
C44 100n/10V
C109
DDR_CK
DDR_CK#
group 1AB
K8
A1
E1
J9
C46 100n/10V
C117
C47 100n/10V
C118
C50 100n/10V
C116
C51 100n/10V
5
5
CK#
VDD
VDD
5
5
CK#
VDD
VDD
A15
DDR_CK#
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
100n/10V
A14
group 1AB
A3
E3
J3
C45 100n/10V
C110
A3
E3
J3
GND
VSS
VDD
GND
VSS
VDD
E12
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
M9
R1
A9
C1
C3
C7
C9
E9
G1
G3
G7
G9
J1
VSS
VDD
VSS
VDD
A11
C48 100n/10V
C108
VSS
VDD
VSS
VDD
B11
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
N1
P9
A7
B2
B8
D2
D8
E7
F2
F8
H2
H8
J7
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
VSS
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDL
F12
C49 100n/10V
VSS
VSS
A10
C77 100n/10V
C52 100n/10V
C79 100n/10V
C53 100n/10V
C76 100n/10V
C56 100n/10V
C111 100n/10V
C57 100n/10V
C114 100n/10V
C115 100n/10V
C113 100n/10V
C119 100n/10V
C120 100n/10V
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSDL
E11
C54 100n/10V
C55 100n/10V
C58 100n/10V
C59 100n/10V
G12
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQSN0
DDR_DQSN1
DDR_DQSN2
DDR_DQSN3
DDR_CS
5
5
5
5
5
5
5
5
E15
B15
D12
E18
G18
B17
C112 100n/10V
B13
D18
J2
DDR_VREF
J2
DDR_VREF
VREF
5
VREF
5
GND
GND
F18
DDR_VREF
TP13
group 1AB
group 1AB
5
A17
MT47H128M16RT-3:C
MT47H128M16RT-3:C
GND
GND
A13
C60
C61
group 1AB
C8
TP12
DDR_CS#
5
100n/10V
100n/10V
B12
top/bot
top/bot
DDR_CK
DDR_CK#
DDR_CLK
5
5
Differential
100 ohms
A12
DDR_CLKN
DDR_CKE
B7
G11
A5
DDR_CKE
DDR_RAS#
5
GND
GND
VDDIODDR
VDDIODDR
DDR_RAS
5
5
5
5
5
5
DDR_CAS#
DDR_WE#
DDR_BA0
DDR_BA1
DDR_BA2
L7
DDR_CAS
B5
DDR_WE
E9
BLM15AG121SN1D
DDR_BA0
R10
B6
C62
R12
DDR_BA1
200R
Keep nets as short as possible, therefore, DDR2 devices have to be placed close as possible of MIURA.
The layout EBI DDR2 should use controlled impedance traces of ZO = 50Ohm characteristic impedance.
Trace width = 0.13mm: target 50Ohm impedance.
F9
R11
1R
DDR_BA2
1k5/1%
100n/10V
group 1AB
DDR_VREF
C12
E13
C13
DDR_CALN
DDR_CALP
DDR_VREF
top/bot
Trace space = 0.30 to 0.38 mm.
5
DDR_VREF
R13
C65
5
C63
100n/10V
R14
PROJECT TITLE
SHEET TITLE
SAMA5D3x-CM
DDR2 INTERFACE
SAMA5D3x
group 1AB
200R
C64
4u7/6V3/X5R
1k5/1%
100n/10V
FILE
SIZE
A4
SHEET NO
DROWN
ISSUED
OF
SAMA5D3x-CM v2.0f.scm
5
9
development tool
www.ronetix.at
REV
DATE
DESCRIPTION FILE
GND
GND
GND
GND
GND
20.9.2012
1
2
3
4
5
6
1
2
3
4
5
6
7
8
U3-G
P13
R14
R13
V18
P14
U18
T18
R15
P17
P15
P18
R16
N16
R17
N17
R18
N18
P16
M18
N15
M15
N14
M17
M13
M16
N12
M14
PE0/A0(NBS0)
PE1/A1
A1_NOR
A2_NOR
A3_NOR
A4_NOR
A5_NOR
A6_NOR
A7_NOR
A8_NOR
A9_NOR
A10_NOR
A11_NOR
A12_NOR
A13_NOR
A14_NOR
A15_NOR
A16_NOR
A17_NOR
A18_NOR
A19_NOR
A20_NOR
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
PE2/A2
VDD_IOM
PE3/A3
PE4/A4
VDD_IOM
PE5/A5
PE6/A6
NOR FLASH
R15
100k
PE7/A7
NAND FLASH
L3 & L8
PE8/A8
Zo=60 ohms +/-10%
R17
100k
L3 & L8
U6
PE9/A9
R16 22R
Zo=60 ohms +/-10%
D0
D1
D2
D3
D4
D5
D6
D7
E3
H3
E4
H4
H5
E5
H6
E6
F3
G3
F4
G4
F5
G6
F6
G7
F2
A5
G2
B5
F7
A4
PE26/NCS0/TXD2
U8
CLE
0402
PE10/A10
6
6
6
6
6
6
6
6
DQ0
E#
W#
2;6
NWE_NOR/NAND_WE
NRD_NOR/NAND_OE
A22_NOR/NAND_CLE
A21_NOR/NAND_ALE
NRD_NOR/NAND_OE
NWE_NOR/NAND_WE
16
17
8
29
30
31
32
41
42
43
44
D0
D1
D2
D3
D4
D5
D6
D7
PE11/A11
DQ1
6
6
6
6
6
6
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
6
6
6
6
6
6
6
6
PE12/A12
DQ2
G#
ALE
RE#
WE#
CE#
NRST
PE13/A13
DQ3
RP#
2;7;8
18
9
PE14/A14
DQ4
BYTE#
R/B#
NAND_CS_R/NCS3
R19
0R
0402
PE15/A15/SCK3
PE16/A16/CTS3
PE17/A17/RTS3
PE18/A18/RXD3
PE19/A19/TXD3
PE20/A20/SCK2
DQ5
6
DQ6
10
14
15
4
DQ7
NC
NC
NC
NC
NC
NC
NC
NC
D8
6
DQ8
D9
VDD_IOM
6
DQ9
D10
6
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
A21_NOR/NAND_ALE
A22_NOR/NAND_CLE
D11
5
PE21/A21(NANDALE)
PE22/A22(NANDCLE)
PE23/A23/CTS2
6
6
6
D12
6
6
PE23/A23_NOR/CTS2
PE24/RTS2
PE25/RXD2/1-Wire
PE26/NCS0/TXD2
D13
R23
100k
R24
10k
26
35
1
2
2;6
2;8
6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VDD_IOM
D14
6
PE24/A24/RTS2
D15
B4
3
PE25/A25/RXD2
2;6;8
6
VPP/WP#
R22 0R
NAND_RD/BY
7
11
20
21
22
23
24
27
28
33
40
45
46
0402
PE26/NCS0/TXD2
2;6
2
6
RD/BY#
WP#
M12 PE27/NCS1/TIOA2/LCDDAT22
L13 PE28/NCS2/TIOB2/LCDDAT23
A1_NOR
6
E2
D2
C2
A2
B2
D3
C3
A3
B6
A6
C6
D6
B7
A7
C7
D7
E7
B3
C4
D5
D4
C5
B8
D8
F1
G5
C66
C68
C67
100n/10V
100n/10V
100n/10V
NAND_WP
19
PE27/NCS1/TIOA2/LCDDAT22
PE28/NCS2/TIOB2/LCDDAT23
PE29/NWR1(NBS1)/TCLK2
PE30/NWAIT
A0
VCCQ
VCCQ
VCC
A2_NOR
2
6
A1
L15
L14
L16
PE29/NWR1(NBS1)/TCLK2
PE30/NWAIT
A3_NOR
6
VDD_IOM
2
A2
A4_NOR
2
6
A3
PE31/IRQ/PWML1
A5_NOR
6
34
39
25
48
PE31/IRQ/PWML1
2
A4
VCC!
VCC!
VSS!
VSS!
GND
A6_NOR
6
A5
K12
K15
K14
K16
K13
K17
J12
K18
J14
J16
J13
J17
J15
J18
H16
H18
L12
L18
L17
K11
D0
D1
D2
D3
D4
D5
D6
D7
A7_NOR
6
A1
A8
B1
C1
C8
D1
E1
F8
G1
G8
H1
H8
D0
6
6
6
6
6
6
6
6
A6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
A8_NOR
D1
6
A7
A9_NOR
6
D2
D3
A8
A10_NOR
C70
C71
100n/10V
100n/10V
12
37
13
36
38
6
A9
VCC
VCC
VSS
VSS
DNU
A11_NOR
6
D4
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A12_NOR
D5
6
A13_NOR
6
D6
A14_NOR
47
D7
6
DNU
D8
D9
A15_NOR
6
D8
6
6
6
6
6
6
6
6
6
6
6
6
GND
A16_NOR
HY27UF082G2B-TPCB
D9
6
D10
A17_NOR
6
MT29F2G08ABAEAWP-IT
D10
D11
D12
D13
D14
D15
A18_NOR
D11
6
Alternative component : MT29F2G08ABAEAWP-IT
A19_NOR
6
D12
A20_NOR
D13
6
A21_NOR/NAND_ALE
A22_NOR/NAND_CLE
E8
H2
H7
D14
6
6
VSS
VSS
VSS
D15
NAND_CS/NCS3
PE23/A23_NOR/CTS2
NCS3
NANDRDY
NRD
NWE(NWR0)
2;6
NAND_RD/BY
NRD_NOR/NAND_OE
NWE_NOR/NAND_WE
EN29GL128H-70BAIP
M29W128GL70ZA6E
GND
NAND_RD/BY
6
TP14
TP15
TP16
TP17
TP18
TP19
TP20
NAND_RD/BY
Alternative component : M29W128GL70ZA6E
NAND_CS/NCS3
NAND_CS/NCS3
PD13/SPI0_CS0
PD10/SPI0_MISO
PD11/SPI0_MOSI
PD12/SPI0_SPCK
GND
6
SAMA5D3x
PD13/SPI0_CS0
2;6;9
PD10/SPI0_MISO
2;6;9
PD11/SPI0_MOSI
2;6;9
PD12/SPI0_SPCK
2;6;9
VDD_IOM
VDD_IOM
GND
C69
100n/10V
GND
R21
10k
Populate either R25 or J1 /J2/
J2
5
U9
A
VCC
NAND_CS/NCS3
2
1
Y
4
NAND_CS_R/NCS3
HEADER TH 2x1/2mm/90dgr
6
6
VDD_IOP0
OE
J1
SERIAL FLASH
GND
3
HEADER SMD 2x1/2mm/90dgr
SN74LVC1G126DBVT
R26
100k
VDD_IOP0
VDD_IOP0
VDD_IOM
U10
1-Wire EEPROM
D1
BAT54CWT1G
R25 0R DNP
GND
VDD_IOP0
C72
CS_BOOT_DISABLE
1
8
0402
2
CS#
VCC
WP#
R18
PD10/SPI0_MISO
PD11/SPI0_MOSI
R65
22R
2
3
R27
10k
0402
2;6;9
2;6;9
SO (SOI)
SI (SIO)
SCK
5
6
1k5/1%
2
C73
100n/10V
U7
100n/10V
GND
R20 0R
0402
PE25/RXD2/1-Wire
3
2;6;8
IO
NC
NC
NC
NC
PD12/SPI0_SPCK
top/bot
VDD_IOP0
2;6;9
5
4
5
6
U11
A
7
4
HOLD#
GND
VCC
PD13/SPI0_CS0
2
1
Y
4
1
2;6;9
GND
AT25DF321A-SH
GND
OE
DS2431P
GND
GND
3
SN74LVC1G126DBVT
GND
PROJECT TITLE
SHEET TITLE
SAMA5D3x-CM
Fl: NAND/NOR/SERIAL/I2C/1-WIRE
SAMA5D3x-CM v2.0f.scm
FILE
SIZE
A3
SHEET NO
DROWN
ISSUED
OF
6
9
development tool
www.ronetix.at
REV
DATE
DESCRIPTION FILE
20.9.2012
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
ETH_DVDDL
L8
2A !
max 345mA-->
BLM21PG221SN1D
C74
C128
22u/6V3
22u/6V3
ETH_AVDDL
L11
2A !
GND
GND
max 205mA-->
BLM21PG221SN1D
C78
C129
ETH_AVDDH
VDD_IOP1
22u/6V3
22u/6V3
max ?mA-->
ETH_AVDDL_PLL
GND
GND
L9
2A !
U15
VIN
L13
0.5A !
L10
max ?mA-->
max 563mA-->
1
5
4
ETH_V1
max 13mA-->
LX
BLM21PG221SN1D
LQM2HPN1R0MG0L
BLM15AG121SN1D
C75
C131
2
C81
C130
GND
EN
C92
C106
C107
100n/10V
22u/6V3
22u/6V3
22u/6V3
GND
3
10u/6V3
0402
VOUT
10n/25V
RS3
2k/1%
SC189ASKTRT 1V0
C127
GND
GND
RS4
10k/1%
GND
GND
GND
GND
GND
ETH_DVDDH
GND GND
L12
2A !
max ?mA-->
BLM21PG221SN1D
C80
C132
RGMII Routing Constraints (Reduced Gigabit Media Independent Interface):
The RGMII signals must be length-matched by TX and RX groups.
That is, the TX group should be matched within 0.25 inch (6.35 mm),
and the RX group should be matched within 0.25 inch (6.35 mm).
Total length should not exceed 1.75 inch (44.5 mm).
ETH_DVDDH
22u/6V3
22u/6V3
There is no requirement to match the TX and RX groups
because their clocks are not related.
GND
GND
R28
4k7
U12
KSZ9021RN
PB0/GTX0
19
20
21
22
24
25
2
3
top/bot
top/bot
ETH0_TX1+
ETH0_TX1-
7
7
7
7
TXD0
TXRXP_A
TXRXM_A
2
2
PB1/GTX1
PB2/GTX2
PB3/GTX3
TXD1
TXD2
place close to CPU
U3-D
5
6
top/bot
top/bot
ETH0_RX1+
ETH0_RX1-
TXD3
TXRXP_B
TXRXM_B
2
2
T2
N7
T3
N6
P5
T4
R4
U1
R5
P3
R6
V3
P6
V1
R7
U3
P7
V2
V5
T6
N8
U4
M7
U5
R69
R68
R67
R66
22R
PB0/GTX0
ETH_DVDDH
PB8/GTX_CLK
PB9/GTXEN
top/bot
0402
0402
0402
0402
PB0/GTX0/PWMH0
PB1/GTX1/PWML0
PB2/GTX2/TK1
7
7
7
7
7
7
7
7
7
7
7
GTX_CLK
TX_EN
22R
22R
22R
PB1/GTX1
PB2/GTX2
7
ETH_DVDDH
place close to KSZ9021RN
7
8
top/bot
top/bot
ETH0_TX2+
ETH0_TX2-
TXRXP_C
TXRXM_C
2
2
PB3/GTX3
PB4/GRX0
R59
R60
R61
R62
R33
22R
22R
22R
22R
22R
32
31
28
27
35
33
0402
0402
0402
0402
PB3/GTX3/TF1
7
7
7
7
RXD0/MODE0
RXD1/MODE1
RXD2/MODE2
RXD3/MODE3
RX_CLK/PHYAD2
PB4/GRX0
PB5/GRX1
PB6/GRX2
PB7/GRX3
PB8/GTX_CLK
PB9/GTXEN
PB5/GRX1
PB4/GRX0/PWMH1
PB5/GRX1/PWML1
PB6/GRX2/TD1
R31
4k7
R32
PB6/GRX2
10
11
top/bot
top/bot
ETH0_RX2+
ETH0_RX2-
TXRXP_D
TXRXM_D
2
2
4k7
R35
4k7
PB7/GRX3
PB11/RX_CLK
PB12/RX_DV R75
0 4 0 2
PB7/GRX3/RK1
7
R30
R29
22R
22R
0R
15
17
LED2
LED1
0402
0402
0402
PB8/GTXCK/PWMH2
PB9/GTXEN/PWML2
PB10/GTXER/RF1
PB11/GRXCK/RD1
PB12/GRXDV/PWMH3
PB13/GRXER/PWML3
PB14/GCRS/CANRX1
PB15/GCOL/CANTX1
PB16/GMDC
2;7
RX_DV/CLK125_EN
LED2/PHYAD1
LED1/PHYAD0
2
2
DNP
R37
4k7
0402
PB10/GTXER/RF1
PB25/SCK1/GRX6
38
41
2
2;7
INT_N
PB11/RX_CLK
PB18/CLK125_NDO
top/bot
R34
22R
0 4 0 2
7
7
CLK125_NDO/LED_MODE
R36
1k
PB12/RX_DV
2;7
ETH_AVDDH
PB13/GRXER/PWML3
PB16/GMDC
PB17/GMDIO
36
37
42
2
7
7
MDC
PB14/GCRS/CANRX1
PB15/GCOL/CANTX1
PB16/GMDC
1
12
47
C84
C83
C85
10n/25V
10n/25V
10n/25V
2
MDIO
AVDDH
AVDDH
AVDDH
2
7
7
RESET_N
GND
R76
22R
0 4 0 2
PB17/GMDIO
place close
to KSZ9021RN
C82
22p/50V
Y4
top/bot
top/bot
46
45
PB17/GMDIO
XI
PB18/CLK125_NDO
R77
PB18/G125CK
7
2
XO
place close
to U3
ETH_DVDDH
PB19/MCI1_CDA/GTX4
PB20/MCI1_DA0/GTX5
PB21/MCI1_DA1/GTX6
PB22/MCI1_DA2/GTX7
PB23/MCI1_DA3/GRX4
0R
ETH_AVDDL
PB19/MCI1_CDA/GTX4
PB20/MCI1_DA0/GTX5
PB21/MCI1_DA1/GTX6
PB22/MCI1_DA2/GTX7
PB23/MCI1_DA3/GRX4
PB24/MCI1_CK/GRX5
PB25/SCK1/GRX6
PB26/CTS1/GRX7
PB27/RTS1/PWMH1
PB28/RXD1
2
2
2
2
2
R38
0402
DNP
48
ISET
CPX32-25.000MHz
4k99/1%
4
9
C89
C88
10n/25V
10n/25V
AVDDL
AVDDL
ETH_DVDDH
R39
D2
C87
10n/25V
10n/25V
16
34
40
GND
DVDDH
DVDDH
DVDDH
C86
22p/50V
M8 top/bot
PB24/MCI1_CK/GRX5
100k
BAS316
C91
C90
ETH_AVDDL_PLL
GND
T5
N9
V4
PB25/SCK1/GRX6
PB26/CTS1/GRX7
PB27/RTS1/PWMH1
PB28/RXD1
Cl=Cs+[C1xC2]/[C1+C2]
if C1=C2 =>
C1,2=2[Cl-Cs] !!!
2;7
2
R40
GND
NRST
44
43
0402
2;6;8
AVDDL_PLL
LDO_O
10n/25V
ETH_DVDDL
14
2
DNP 0R
Cl is load capacitance of the cristal.
CS is the stray capacitance on the
printed circuit board,
typically a value of 5pf can be used
for calculation
M9
P8
C93
C95
C94
C97
C96
C98
10n/25V
10n/25V
10n/25V
10n/25V
10n/25V
10n/25V
2
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
DVDDL
C99
1uF/10V
C121
PB29/TXD1
18
23
26
30
39
C122
PB29/TXD1
2
M10
R9
PB30/DRXD
PB30/DRXD
2
PB31/DTXD
13
29
49
10n/25V
100n/10V
PB31/DTXD
2
VSS_PS
VSS
GND
SAMA5D3x
P_GND
GND
GND
GND
GND
L14
BLM15AG121SN1D
GND
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2
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4
5
6
Cl=Cs+[C1xC2]/[C1+C2]
if C1=C2 =>
C1,2=2[Cl-Cs] !!!
SOFT MODEM
C100
U3-B
Cl is load capacitance of the cristal
CS is the stray capacitance on the printed circuit board,
typically a value of 5pf can be used for calculation
27p/50V
U8
top/bot
top/bot
Y3
XIN
V8
CPX32-12.000MHz
C101
XOUT
27p/50V
NX3215SA-32.768K
C102
VDD_IOP0
Vbat
18p/50V
Y1
U16 top/bot
XIN32
Y2
V16
top/bot
CM200C-32.768KDZF-UT
C103
XOUT32
DNP
R41
R42
0R
R43
10k
RA1
18p/50V
100k
4x100k
DNP
GND
T10
T12
U9
WKUP
WKUP
SHDN
BMS
2
2
2
SHDN
BMS
V9
NRST
NRST
2;6;7
T9
JTAGSEL
NTRST
JTAGSEL
NTRST
2
2
2
2
2
P11
R8
TDI/SWD
TDI/SWD
TCK/SWCLK
TMS/SWDIO
TDO
P9
TCK/SWCLK
TMS/SWDIO
N10
M11
TDO
2
2
U15
TST
V6
U6
DIBP
DIBN
DIBP
DIBN
R44
2
10k
SAMA5D3x
GND
VDD_IOM
VDD_IOM
LEDS
USB
U3-I
U14
V14
U12
V12
U10
V10
R11
top/bot
top/bot
top/bot
top/bot
top/bot
top/bot
USBC_DP
USBC_DM
USBB_DP
USBB_DM
USBA_DP
USBA_DM
90 ohms differential trace
impedance
HHSDPC
HHSDMC
HHSDPB
HHSDMB
HHSDPA
HHSDMA
VBG
2
2
2
2
2
2
DL1
LED 0603 - RED - LTST-C190CKT
DL2
LED 0603 - BLUE - LTST-C193TBKT-5A
90 ohms differential trace
impedance
R46
1M
R47
200R
90 ohms differential trace
impedance
R49
200R
D
S
Max trace-length mismatch
between USB signal pairs
should be no greater than 3.8mm
SAMA5D3x
G
PE24/RTS2
PE25/RXD2/1-Wire
2;6
2;6
R48
5k62/1%
C104
Q1
BSS138
10p/50V
GND
UTMI_GND
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2
3
4
5
6
A
B
C
D
U3-C
SAMA5D3x
PA0/LCDDAT0
E3
F5
D2
F4
D1
J10
G4
J9
PA0/LCDDAT0
PA1/LCDDAT1
PA2/LCDDAT2
PA3/LCDDAT3
PA4/LCDDAT4
PA5/LCDDAT5
PA6/LCDDAT6
PA7/LCDDAT7
PA8/LCDDAT8
PA9/LCDDAT9
PA10/LCDDAT10
PA11/LCDDAT11
PA12/LCDDAT12
PA13/LCDDAT13
PA14/LCDDAT14
PA15/LCDDAT15
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PA1/LCDDAT1
PA2/LCDDAT2
PA3/LCDDAT3
PA4/LCDDAT4
PA5/LCDDAT5
PA6/LCDDAT6
PA7/LCDDAT7
F3
J8
PA8/LCDDAT8
PA9/LCDDAT9
E2
K8
F2
G6
E1
H5
H3
H6
H4
H7
H2
J6
PA10/LCDDAT10
PA11/LCDDAT11
PA12/LCDDAT12
PA13/LCDDAT13
PA14/LCDDAT14
PA15/LCDDAT15
PA16/LCDDAT16/ISI_D0
PA17/LCDDAT17/ISI_D1
PA16/LCDDAT16/ISI_D0
PA17/LCDDAT17/ISI_D1
PA18/LCDDAT18/TWD2/ISI_D2
PA19/LCDDAT19/TWCK2/ISI_D3
PA20/LCDDAT20/PWMH0
PA21/LCDDAT21/PWML0/ISI_D5
PA22/LCDDAT22/PWMH1
PA23/LCDDAT23/PWML1/ISI_D7
PA24/LCDPWM
PA18/LCDDAT18/TWD2/ISI_D2
PA19/LCDDAT19/TWCK2/ISI_D3
PA20/LCDDAT20/PWMH0
PA21/LCDDAT21/PWML0/ISI_D5
PA22/LCDDAT22/PWMH1
PA23/LCDDAT23/PWML1/ISI_D7
PA24/LCDPWM
G2
J5
F1
J4
PA25/LCDDISP
PA25/LCDDISP
G3
J3
PA26/LCDVSYNC
PA26/LCDVSYNC
PA27/LCDHSYNC
PA27/LCDHSYNC
G1
K4
H1
K3
top/bot
PA28/LCDPCK
PA28/LCDPCK
2
PA29/LCDDEN
PA30/TWD0/URXD1/ISI_VSYNC
PA31/TWCK0/UTXD1/SI_HSYNC
PA29/LCDDEN
2
2
2
PA30/TWD0/URXD1/ISI_VSYNC
PA31/TWCK0/UTXD1/SI_HSYNC
U3-F
SAMA5D3x
PD0/MCI0_CDA
K5
P1
K6
R1
L7
PD0/MCI0_CDA
PD1/MCI0_DA0
2
2
2
2
2
2
2
2
2
PD1/MCI0_DA0
PD2/MCI0_DA1
PD2/MCI0_DA1
PD3/MCI0_DA2
PD3/MCI0_DA2
PD4/MCI0_DA3
PD4/MCI0_DA3
P2
L8
PD5/MCI0_DA4/TIOA0/PWMH2
PD6/MCI0_DA5/TIOB0/PWML2
PD7/MCI0_DA6/TCLK0/PWMH3
PD8/MCI0_DA7//PWML3
PD5/MCI0_DA4/TIOA0/PWMH2
PD6/MCI0_DA5/TIOB0/PWML2
PD7/MCI0_DA6/TCLK0/PWMH3
PD8/MCI0_DA7//PWML3
PD9/MCI0_CK
R2
K7
U2
K9
M5
K10
N4
L9
top/bot
PD9/MCI0_CK
2
PD10/SPI0_MISO
PD10/SPI0_MISO
PD11/SPI0_MOSI
PD12/SPI0_SPCK
PD13/SPI0_NPCS0
PD14/SCK0/SPI0_NPCS1/CANRX0
PD15/CTS0/SPI0_NPCS2/CANTX0
PD16/RTS0/SPI0_NPCS3/PWMFI3
PD17/RXD0
2;6
2;6
R63
R64
22R
22R
PD11/SPI0_MOSI
0402
0402
top/bot
PD12/SPI0_SPCK
2;6
PD13/SPI0_CS0
2;6
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PD14/SCK0/SPI0_NPCS1/CANRX0
PD15/CTS0/SPI0_NPCS2/CANTX0
PD16/RTS0/SPI0_NPCS3/PWMFI3
PD17/RXD0
N3
L10
N5
M6
T1
N2
M3
M2
L3
PD18/TXD0
PD18/TXD0
PD19/ADTRG
PD20/AD0
PD19/ADTRG
PD20/AD0
PD21/AD1
PD21/AD1
PD22/AD2
PD22/AD2
PD23/AD3
PD23/AD3
M1
N1
L1
PD24/AD4
PD24/AD4
PD25/AD5
PD25/AD5
PD26/AD6
PD26/AD6
L2
PD27/AD7
PD27/AD7
K1
K2
J1
PD28/AD8
PD28/AD8
PD29/AD9
PD29/AD9
PD30/AD10
PD30/AD10
J2
PD31/AD11
PD31/AD11
U3-E
SAMA5D3x
PC0/ETX0/TIOA3
PC1/ETX1/TIOB3
D8
A4
E8
A3
A2
F8
B3
G8
B4
F7
A1
D7
C6
E7
B2
F6
B1
E6
C3
D6
C4
D5
C2
G9
C1
H10
H9
D4
H8
G5
D3
E4
PC0/ETX0/TIOA3
PC1/ETX1/TIOB3
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
PC2/ERX0/TCLK3
PC2/ERX0/TCLK3
PC3/ERX1/TIOA4
PC3/ERX1/TIOA4
PC4/ETXEN/TIOB4
PC4/ETXEN/TIOB4
PC5/ECRSDV/TCLK4
PC5/ECRSDV/TCLK4
PC6/ERXER/TIOA5
PC6/ERXER/TIOA5
PC7/EREFCK/TIOB5
PC7/EREFCK/TIOB5
PC8/EMDC/TCLK5
PC8/EMDC/TCLK5
PC9/EMDIO
PC9/EMDIO
PC10/MCI2_CDA//LCDDAT20
PC11/MCI2_DA0//LCDDAT19
PC12/MCI2_DA1/TIOA1/LCDDAT18
PC13/MCI2_DA2/TIOB1/LCDDAT17
PC14/MCI2_DA3/TCLK1/LCDDAT16
PC10/MCI2_CDA//LCDDAT20
PC11/MCI2_DA0//LCDDAT19
PC12/MCI2_DA1/TIOA1/LCDDAT18
PC13/MCI2_DA2/TIOB1/LCDDAT17
PC14/MCI2_DA3/TCLK1/LCDDAT16
PC15/MCI2_CK/PCK2/LCDDAT21
PC16/TK0
top/bot
PC15/MCI2_CK/PCK2/LCDDAT21
2
PC16/TK0
PC17/TF0
2
2
2
2
2
2
2
2
PC17/TF0
PC18/TD0
PC18/TD0
PC19/RK0
PC19/RK0
PC20/RF0
PC20/RF0
PC21/RD0
PC21/RD0
PC22/SPI1_MISO
PC23/SPI1_MOSI
PC22/SPI1_MISO
PC23/SPI1_MOSI
top/bot
PC24/SPI1_SPCK
PC24/SPI1_SPCK
2
PC25/SPI1_NPCS0
PC26/SPI1_NPCS1/TWD1/ISI_D11
PC27/SPI1_NPCS2/TWCK1/ISI_D10
PC28/SPI1_NPCS3/PWMFI0/ISI_D9
PC29/URXD0/PWMFI2/ISI_D8
PC30/UTXD0//ISI_PCK
PC25/SPI1_NPCS0
2
2
2
2
2
2
2
PC26/SPI1_NPCS1/TWD1/ISI_D11
PC27/SPI1_NPCS2/TWCK1/ISI_D10
PC28/SPI1_NPCS3/PWMFI0/ISI_D9
PC29/URXD0/PWMFI2/ISI_D8
PC30/UTXD0//ISI_PCK
PC31/FIQ/PWMFI1
PC31/FIQ/PWMFI1
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5.
Main Board (MB)
5.1
Main Board Overview
The SAMA5D3 series main board (MB) hosts any of the SAMA5D31/33/34/35/36 CPU module boards (CM). The main
board features all necessary peripheral devices and interfaces for processor evaluation.
Figure 5-1.
Main Board Top View
SAMA5D3x-EK User Guide [USER GUIDE]
53
11180B–ATARM–29-Oct-13
Figure 5-2.
Annotated MB Layout
SAMA5D3x-EK User Guide [USER GUIDE]
54
11180B–ATARM–29-Oct-13
5.1.1 Equipment List
The SAMA5D3 series MB is a full-featured motherboard. It can be used with all available SAMA5D3 series CM boards.
5.1.2 Technical Specifications
Table 5-1.
MB Technical Specifications
Characteristic
Specifications
Supported Module
Expansion Slots
Mass Storage Interface
All SAMA5D3 series computer modules
One 200-pin SODIMM socket
Two high-speed memory card hosts
1 x SD card slot (can also read MMC cards)
1 x micro SD card slot
3 x 20 pin header
1 x 20 + 1 x 15 pin header LCD connector
1 x 10 pin header ISI connector (Image Sensor)
One 1-Wire EEPROM DS28EC20
One power LED
I/O
1 x Gigabit Ethernet
1 x 10/100 MHz Ethernet
2 x USB High-speed 2.0 Host
1 x USB High-speed 2.0 Host/Device
1 x USARTs, 1 x DBGU
Communication
2 x CAN connectors
1 x 10-pin header ZigBee connector
1 x Smart DAA (Softmodem interface)
Sound
Video
Wolfson's 8904 Mic in, Headphone out signals
1 x HDMI
LCD TFT Controller with overlay, alpha-blending, rotation, scaling and color
space conversion
LCD
ISI
ITU-R BT. 601/656 Image Sensor Interface
1 x On-board SAM-ICE™
Debug
1 x Bridge USB/UART DBGU
CMOS Battery
Power
On-board Lithium Battery for CMOS backup
System power: +5V DC +/-5%
Backup: +1.65V to 3.6V DC
RoHS status
Compliant
CE and FCC Part 15 status
Dimensions
Compliant
165 * 135 * 20 mm
Note: Some of the features mentioned in the above feature summary table are optional. Check the article number of
your module and compare it to the option information list on Table 3-1 “Evaluation Kit Features” of this user
guide to determine which options are available with your particular module.
SAMA5D3x-EK User Guide [USER GUIDE]
55
11180B–ATARM–29-Oct-13
5.1.3 Devices
List of the MB board peripherals:
Two EMAC PHY
One audio CODEC
Two high-speed MCI card interfaces
Two CAN transceivers
One RS232 port with level translator features USART1
One Smart DAA port
Two USB host ports
One USB host/device port
On-board power regulation
LCD/ISI extension interface
HDMI interface
ZigBee® interface
One-wire device
5.1.4
Board Interface Connection
Main power supply (J4)
200 positions socket (as defined in SODIMM 200), 0.6mm pitch (J12)
USB A Host/Device, support USB host/device using a micro AB connector (J20)
USB B Host, support USB host using a type A connector (J19, upper)
USB C Host, support USB host using a type A connector (J19, lower)
USB-to-serial bridge on DBGU, and JTAG-OB functionality (J14)
USART1 (RX, TX, RTS, CTS) connected to a 9-way male RS232 connector (J8)
JTAG, 20-pin IDC connector (J9)
MicroSD connector (J6)
SD/MMC connector (J7)
Gigabit Ethernet ETH0 (J17)
Ethernet ETH1 (J24)
Headphone (J15), line (J13)
Image sensor connector (J11)
HDMI connector (J25)
Expansion connector with all LCD controller signals for DM board connection (QTouch, TFT LCD display with
touchscreen and backlight (J21, J22))
DAA connecter RJ11 6P4C type (J16)
CAN bus connectors RJ12 6P6C type (J18, J27)
ZigBee connector (J10)
Battery socket (J5)
Three expansion connectors with PIO signals (J1, J2, J3)
Test points; various test points are located throughout the board
SAMA5D3x-EK User Guide [USER GUIDE]
56
11180B–ATARM–29-Oct-13
Figure 5-3.
MB Architecture
COM1 or
DBGU
RS232
On Board JTAG
Bridge
USB/DBGU
VCC 5V Jack
Audio
In
Audio
Out
MIC1
MCI0
CAN0 & 1
ZIGBEE
Modem
RJ11
RJ12
Micro
oooooo
oooooo
RJ12
8 bits
HeadPh
4 bits
interface
OnB JTAG
CONEXANT
interface
USART
USB/DBGU
U
RS232
Micro
input
RS232
Audio
output
ZIGBEE
MUX
Can0
System
Power
MCI1
Can1
MCI0
SAM3U
USART1
DBGU
Modem
Codec
1-Wire
Connector SoDIMM200
Ethernet
Ethernet
USB
ISI
LCD Part 1
LCD Part 2
RMII ETH1
RGMII ETH0
PIO
Host
Host
Device
LCD interface
RJ45
RJ45
oooooooo
oooooooo
oooooooo
oooooooo
oooooooooooooooo
oooooooooooooooo
oooooooooooooo
oooooooooooooo
Ethernet
RMII
Ethernet
RGMII
USB
Host * 2
USB
H/Device
ISI
HDMI
LCD
LCD
PIO
SAMA5D3x-MB
SAMA5D3x-EK User Guide [USER GUIDE]
57
11180B–ATARM–29-Oct-13
5.2
Function Blocks
5.2.1 Processor
The SAMA5D3 series MB board may be used with any of the SAMA5D31/D33/D34/D35/SAMA5D36 CPU modules.
Figure 5-4.
SODIMM Interface on MB
VDDIOP0
JP9 for BMS Config:
When Open,BMS=1: Boot on embeded ROM
When Close,BMS=0: Boot on External memory
5V
5V
R83
4.7k
J12
1
3
2
JP9
VCC5V_1
VCC5V_2
VCC5V_4
VBAT
4
VCC5V_3
GND1
PE23
BMS
1
2
5
6
8
VBAT
PE29
PE30
PE31
4,12
6,13
6,10,13
6,9,13
PE23
PE29
PE30
PE31
7
9
PE29
PE24
PE25
PE26
SIP2
12,13
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PE24
PE30
PE31
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PE25
PE25
PE26
GND13
VDDIOM_2
PC24
VDDIOM
VDDIOM
VDDIOM_1
PC25
PC23
PC21
GND2
PC18
PC16
PC8
PC25
PC23
PC21
PC24
PC22
PC20
PC19
PC17
PC9
PC24
6,13
6,13
7
PC23
PC21
PC22
PC22
6,13
PC20
7
PC20
PC19
PC17
PC9
7
7,9
10
PC19
PC18
PC16
PC8
PC6
PC4
PC2
PC0
7,9
7,9
10
10
10
10
PC18
PC16
PC8
PC6
PC4
PC2
PC17
PC9
PC7
PC7
PC7
10
10
PC6
GND14
PC5
PC5
PC3
PC1
PC4
PC5
PC3
PC1
10
PC2
PC3
PC1
Enable_1
10
10
4
PC0
PWR_EN
PC0
Enable_0
CS_BOOT_DISABLE 12
3V3
3V3
KEY
41
43
42
VCC3V3_1
VCC3V3_3
Enable_2
NC1
VCC3V3_2
VCC3V3_4
Enable_3
ADVREF
PE28
44
45
46
47
48
ADVREF 12
PE27
PC10
PE28
PC11
PC13
PC15
PC26
PC28
49
50
PE28
PC11
PC13
PC15
6,9,13
9,13
9,12,13
9,13
PE27
PC10
PE27
51
52
PC10
PC11
53
54
9,13
9,13
GND3
PC13
PC12
PC14
PC27
PC29
PC31
55
56
9,13
9,13
13
PC12
PC14
PC27
PC29
PC31
PC12
PC15
57
58
PC26
PC28
13
6,13
PC14
PC26
59
60
PC27
PC28
61
62
13
PC29
GND15
PC30
PC30
63
64
9
PC30
13
PC31
65
66
VDDIOP0
VDDANA
VDDIOP1
VDDIOP0
VDDIOP0_1
PA0
VDDIOP0_2
PA1
PA0
PA2
PA1
PA3
PA4
PA6
PA8
PA10
67
68
PA1
PA3
PA4
PA6
PA8
PA10
9,13
9,13
9,13
9,13
9,13
9,13
9,13
9,13
PA0
PA2
69
70
PA2
PA3
71
72
GND4
PA4
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
73
74
9,13
9,13
9,13
9,13
9,13
9,13
13
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
PA5
PA6
75
76
PA7
PA8
77
78
PA9
PA10
GND16
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
GND17
PA29
PA31
VDDANA_2
PD31
PD29
PD27
PD25
PD23
GND18
PD21
PD19
PD17
PD15
PD13
PD11
PD9
79
80
PA11
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
81
82
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
9,13
9,13
13
PA12
83
84
PA14
85
86
PA16
87
88
13
13
PA18
89
90
13
13
13
GND5
PA21
PA23
PA25
PA27
PA28
PA30
91
92
13
13
13
9,13
9,13
7,9,13
PA21
PA23
PA25
PA27
PA28
PA30
PA21
93
94
PA23
95
96
9,13
PA25
97
98
PA27
PA29
PA31
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PA29
PA31
9,13
7,9,13
PA28
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
PA30
VDDANA
VDDANA_1
PD30
PD30
PD31
PD29
PD27
PD25
PD23
PD31
9
7
PD30
PD29
PD27
PD25
PD23
11
11
11
13
GND6
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
11
11
13
13
13
5
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD28
PD26
PD24
PD22
PD21
PD19
PD17
PD15
PD21
PD19
13
13
PD20
PD18
7
6
PD17
PD15
5
6
PD16
PD14
PD14
DNP R120
DNP R51
22R PD13
22R PD11
GND7
PD12 R50
PD10 R6
22R DNP
22R DNP
PD12
PD9
PD7
PD9
PD7
5
5
PD10
PD8
PD6
PD5
PD3
PD1
5
5
5
5
5
PD8
PD6
PD5
PD3
PD1
PD8
PD7
PD6
GND19
PD4
PD4
PD2
PD0
PD4
PD2
PD0
5
5
5
PD5
PD3
PD2
PD0
PD1
VDDIOP1
VDDIOP1_1
GND8
VDDIOP1_2
NC2
PB10
PB14
PB19
PB21
PB23
PB24
PB12
PB15
PB20
PB22
PB12
PB15
PB20
PB22
5
5
6,13
5
5
5
5
PB10
PB14
PB19
PB21
PB23
PB24
PB10
PB12
6,13
PB14
PB15
5
5
PB19
PB20
PB21
PB22
PB23
GND20
PB25
PB25
PB27
PB29
PB31
PB30
PB26
PB28
PB24
PB27
PB29
PB31
PB30
PB26
PB28
6
6
6,14
6,14
6
GND23
USBA_DP
USBA_DM
GND10
USBB_DP
USBB_DM
GND11
USBC_DP
USBC_DM
GND_ETH1
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
GND_ETH2
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
GND12
LED2
PB27
11
11
USBA_DP
USBA_DM
PB29
PB31
PB30
11
11
USBB_DP
USBB_DM
PB26
PB28
6
GND9
DIBP
DIBP
DIBN
8
8
11
11
10
USBC_DP
USBC_DM
ETH0_GND
DIBN
GND21
JTAGSEL
WKUP
SHDN
BMS
10
10
10
10
10
10
10
10
10
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
ETH0_GND
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
WAKE UP 12
SHDN
4
BMS
NRST
10,12,14
nRST
nTRST
TDI
NTRST
TDI
TCK
TMS
14
14
14
14
TCK
TMS
TDO
RTCK
14
14
TDO
10
10
ETH0_LED2
ETH0_LED1
RTCK
GND22
LED1
1612618-1
SAMA5D3x-EK User Guide [USER GUIDE]
58
11180B–ATARM–29-Oct-13
5.2.2 Power Supplies
The SAMA5D3 series MB is supplied with a simple external 5 VCC power supply. The MB features one adjustable low-
dropout regulator (LDO). It accepts DC in 5V power and outputs a regulated +3.3V to most other circuits on the board
through four 3.3V rails.
5.2.2.1
Supply Group Configuration
The LDO is enabled through a dual FET scheme. The processor can assert SHDN (which is a VDDBU powered I/O) to
shut down the LDO to enter backup mode. The regulators on the CM board are also shut down by the action of the
SHDN signal.
If the 3V battery is mounted on J5, both the CM and the MB can be woken up by action on the BP2 button, which drives
the WKUP signal that is also a VDDBU powered I/O.
Figure 5-5.
MB Power Management
3V3
D1
JP4
5V
MN1
ZEN056V230A16LS
5V_INPUT
MN2
BAT54CLT1G
BNX002-01
3
1
2
J4
1
3
1
3
2
B
CB
VBAT
3,12
J5
SIP2
1
3
2
4
5
6
PSG CG1
CG2
C2
33u
C1
100n
C3
100n
CG3
DC POWER JACK
C4
100n
3V3
3V3
3V3
R25
10k
L1
PWR_EN
Q6
R1
100k
220ohm at 100MHz
PWR_EN
3
IRLML2402
C5
10n
47k
1
2
3
2
VDDISI
13
5V
MN3
5V
C120
1u
RT9018A
R2
R3
1
2
3
4
8
7
6
5
PGOOD
EN
VIN
VDD
GND
ADJ
VOUT
NC
POWER_EN
1
470R
R4
100k
R5
15k
C8
1u
C6
10u
C7
1u
C9
10u
D2
Red
PWR_EN#
Q1
6
5
2
4
3
Si1563EDH
C57
JP5
100n
SIP2
FORCE
POWER
ON
C10
1
5V
TP3
TP4
TP5
TP6
TP7
TP8
15p
TP1
TP2
3V3
R7
10k
R8
10k
VDDIOP0
VDDIOP1
VDDIOM
VDDANA
C22
1u
Place C22 near MN3.pin2
SHDN
SAMA5D3x-EK User Guide [USER GUIDE]
59
11180B–ATARM–29-Oct-13
5.2.3 Debug JTAG/ICE and DBGU
The MB includes a built-in SEGGER J-Link-on-Board device. The functionality is implemented with an ATSAM3U4C
microcontroller in an LQFP100 package.
The ATSAM3U4C provides the functions of JTAG and a bridge USB/Serial DBGU port.
Two LEDs D13 and D14 that are mounted on the main board signal the status of the J-Link-on-Board device.
The J-Link-OB-ATSAM3U4C was designed in order to provide an efficient, on-board alternative to the general J-Link.
J-Link-OB-ATSAM3U4C supports the following target interfaces:
JTAG
DBGU
An optional 20-pin header is provided on the board to allow for the JTAG connection. In order to use this functionality,
RR6 and RR7 must be removed and JP15 jumper must be in place.
Figure 5-6.
MB JTAG-OB
VCC_3V3_DEBUG
5V
VCC_3V3_DEBUG
MN17
J23
1
10
NRST_3U
TDI_3U
R65
R64
R62
0R
0R
0R
VCC RESET
2
3
4
5
9
8
7
6
TMS_3U R61
TCK_3U R131
0R
0R
TMS
GND1
TCK
NC2
51
54
56
55
TDI_3U
TDO_3U
TCK_3U
TMS_3U
TDI
TDI
26
27
28
29
30
31
32
33
37
38
39
40
41
10
11
12
13
14
17
18
19
20
5
TRSTIN
TRSTOUT
TDO/TRACESWO
TCK/SWCLK
TMS/SWDIO
PA0/PGMNCMD
PA1/PGMRDY
PA2/PGMNOE
PA3/PGMNVALID
PA4/PGMM0
PA5/PGMM1
PA6/PGMM2
PA7/PGMM3
PA8/PGMD0
PA9/PGMD1
PA10/PGMD2
PA11/PGMD3
PA12/PGMD4
PA13/PGMD5
PA14/PGMD6
PA15/PGMD7
PA16/PGMD8
PA17/PGMD9
PA18/PGMD10
PA19/PGMD11
PA20/PGMD12
PA21/PGMD13
PA22/PGMD12
PA23/PGMD15
PA24
NC1
TDO
TDO_3U
GND2
TRESIN
TRESOUT
TC2050-IDC
43
ERASE_3U
T1
ERASE
4
2
T3
T4
AD12BVREF
ADVREF
VCC_3V3_DEBUG
57
47
NRST_3U
C116
NRST
NRSTB
10n
RX_3U
TX_3U
TDIIN
R44
R45
0R
0R
SAM3U_LQFP100
3,6
3,6
PB31
PB30
44
48
TEST
JTAGSEL
R54
R66
0R DNP
6.8k/1%
VCC_3V3_DEBUG
VCC_3V3_DEBUG
78
TMSIN
VBG
VBUS_DEBUG
50
49
TCKOUT
TMSOUT
C117 10p
XIN32
XOUT32
XIN_3U
C119 15p
2
Y4
4
TDIOUT
TDOIN
TCKIN
ENSPI
TCKOUT
R145
47k
75
74
XIN
XOUT
21
23
24
25
96
84
85
6
J14
C121 15p
12MHz XOUT_3U
105017-0001
CDC Enabled,close to disable
JTAG Enabled,close to disable
JP16
JP15
42
2
2
1
1
R43
100k
VCC_3V3_DEBUG
FWUP
PA25
PA26
PA27
PA28
PA29
PA30
PA31
VCC_3V3_DEBUG
10
11
1
2
3
4
5
VCC_3V3_DEBUG
77
80
81
76
DHSDM
DHSDP
DHSDM
DFSDM
DFSDP
DHSDP
3V3
2
1
1
R68
R67
39R
39R
LED1_3U
LED2_3U
RTCKIN
D13
D14
Red
R69
R70
1k
1k
EARTH_USB2
2
Green
86
R186
R185
0R
0R
D12
TVS
D11
DNP
VBUS_DEBUG
MN18
L24
TVS
DNP
1
2
3
5
4
220ohm at 100MHz
DNP
VIN VOUT
GND
1
2
C95
10u
C96
100n
EARTH_USB2
EN
BYP
C94
10u
C47
2.2u
SPX3819
C98
100n
VCC_3V3_DEBUG
VDDIOP0
VCC_3V3_DEBUG
R79
R106 R107 R109
VCC_3V3_DEBUG
RR6
1
2
3
4
8
7
6
5
TRSTOUT
TRSTIN
R179
R180
R181
R182
150R
150R
150R
150R
0R NTRST
TDI
VDDIOP0
VDDIOP0
TMS
100k 100k 100k 100k
DNP DNP DNP
TCK
J9 DNP
DNP
2
4
6
8
10
12
14
16
18
20
1
C152
100n
C153
100n
C131 C146
100n 4.7u
C154
100n
C155 C156
100n 100n
C157 C158
C159 C160
DNP
DNP
3
5
7
TDIOUT
TDIIN
R113
R110
0R
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
3
3
3
3
3
100n 100n
100n 100n
9
11
13
15
17
19
0R
VDDBU
VDDANA
VDDIN
VDDUTMI
VDDIO
VDDIO
ADVREF
TMSOUT
TMSIN
3
R112
0R
10,12,3
DNP
R111
0R
DNP
TCKOUT
TCKIN
BR20-H
VDDOUT_3U
RR7
1
8
7
6
5
0R
ICE INTERFACE
2
3
4
RTCKIN
TDOIN
RTCK
TDO
NRST
C161 C147
100n 4.7u
C162
C163 C164 C165 C166 C167
100n 100n 100n 100n 100n
100n
TRESOUT
R183
150R
VDDOUT
VDDPLL
VDDCORE
SAMA5D3x-EK User Guide [USER GUIDE]
60
11180B–ATARM–29-Oct-13
5.2.3.1
Disabling J-Link-OB-ATSAM3U4C
Jumper JP15 disables the J-Link-OB-ATSAM3U4C JTAG functionality. When the jumper is installed, it grounds Pin 25 of
the ATSAM3U4C that is normally pulled high. This signals to the microcontroller it must not provide JTAG support.
Jumper JP15 not installed: J-Link-OB-ATSAM3U4C is enabled and fully functional
Jumper JP15 installed: JTAG functionality is disabled
Jumper J15 disables only J-Link functionality. The debug serial port (DBGU) that is emulated through a communication
device class (CDC) of the same USB connector remains operational.
The built-in JTAG controller does not have to be explicitly disabled to use an external JTAG controller through the 20-pin
JTAG port. The internal J-Link-OB connects to a target only after it receives a first command; otherwise, it remains
disabled.
5.2.3.2
Hardware UART via CDC
In addition to J-Link-OB functionality, the ATSAM3U4C microcontroller LAO provides a bridge to a debug serial port
(DBGU) of the processor on a CM board. The port is made accessible over the same USB connection used by JTAG by
implementing communication device class (CDC), which allows terminal communication with the target device.
This feature is enabled only if the microcontroller Pin 24 is not grounded. The pin is normally pulled high and controlled
by jumper JP16.
Jumper JP16 not installed: the device is enabled
Jumper JP16 installed: the CDC device is disabled
5.2.4 USART
The USART1 is used as a user serial communication port. This USART provides an RS-232 interface with transceiver
TXD, RXD lines and hardware flow control CTS/RTS lines. The device uses a DB-9 male connector. The software must
drive the appropriate PIO pins to enable the USART function.
Figure 5-7.
USART1 Com Port
VDDIOP1
MN4
C13
4.7u
C14
C16
C17
C19
100n
100n
100n
3
23
1
6
VCC
C1+
C1-
100n
VDDIOP1
J8
20
2
GND
V+
V-
1
6
2
7
3
8
4
9
5
C15
C18
100n
100n
C2+
C2-
USART1
21
19
5
4
R22 R23 R24
24
22
SD
EN
C3+
C3-
47k 47k
47k
RTSC1
TXDC1
R27
R28
0R
0R
0R
7
8
9
18
17
16
PB27
PB29
PB31
T1IN
T2IN
T3IN
T1OUT
T2OUT
T3OUT
R132
DNP
DNP
L5
R29
0R
220ohm at 100MHz
10
11
12
15
14
13
R1OUT
R2OUT
R3OUT
R1IN
R2IN
R3IN
CTSC1
RXDC1
R30
R31
R133
0R
0R
0R
1
2
PB26
PB28
PB30
ADM3312EARU
EARTH_RS232
SAMA5D3x-EK User Guide [USER GUIDE]
61
11180B–ATARM–29-Oct-13
5.2.5 USB Ports
The SAMA5D3 series MB features three USB communication ports:
Port A
Port B
Port C
High-speed (EHCI) and full-speed (OHCI) host multiplexed with USB Device
High-speed micro AB connector, J20
High-speed (EHCI) and full-speed (OHCI) host
Standard type A connector, J19 upper port
Full-speed (OHCI) only host
Standard type A connector, J19 lower port
All three USB host ports are equipped with 500 mA high-side power switch for self-powered and bus-powered
applications. The USB device port feature VBUS insert detection function through the resistor ladder R138 and R139.
Refer to the embedded MPU product datasheet for detailed programming information, available on www.atmel.com.
Figure 5-8.
USB Port A
3V3
L14
MN15
OUTA
R163
47k
1
2
8
7
1
2
13
5V_LCD
ENA
5V
C107
100n
C106 220ohm at 100MHz
33u
EN_PWRLCD
13
IN
FLGA
C108
100n
L15
6
5
3
4
OVCUR_USB
EN5V_HDA
PD28
GNG
FLGB
ENB
JP17
SIP2
OPEN:Enable LCD for D31,D33,D34
CLOSE:Disable LCD for D35
1
2
OUTB
C109
100n
220ohm at 100MHz
AIC1526-1GS
3V3
C75
10u
R137
47k
MN21
6
1
LCD_DETECT# 13
R138
47k
(VBUS_SENSE)
4
5
3
2
PD29
3
PD25
3
3V3
R139
82k
C111
15p
SN74LVC2GU04
J20
C99
100n
10
1
2
3
4
5
USBA_DM
USBA_DP
3
3
EARTH_USB
47589-0001
(IDUSBA)
11
USB A HOST/DEVICE INTERFACE
R140
47k
3V3
EARTH_USB
Figure 5-9.
USB Ports B and C
USBB_DP
USBB_DM
3
3
L12
MN19
MN14
OUTA
1
2
8
7
1
2
EN5V_HDB
ENA
5V
6
1
PD26
PD27
3
3
C102
100n
220ohm at 100MHz
OVCUR_USB
PD28
PD28
3
IN
FLGA
C103
33u
C101
100n
4
5
3
2
L13
6
5
3
4
GNG
FLGB
ENB
3V3
1
2
EN5V_HDC
OUTB
SN74LVC2GU04
C105
100n
C104
33u
220ohm at 100MHz
AIC1526-1GS
C97
100n
J19
Dual USB A
A1
A2
A3
A4
B1
B2
B3
B4
fi
fl
USBC_DM
USBC_DP
3
3
USB HOST B&C INTERFACE
L21
220ohm at 100MHz
1
2
3 4
1
2
EARTH_USB
EARTH_USB
SAMA5D3x-EK User Guide [USER GUIDE]
62
11180B–ATARM–29-Oct-13
5.2.6 Ethernet 10/100 (EMAC) Port
The main board contains a MICREL PHY device (KSZ8051) handling Ethernet connectivity at 10/100 Mbps. The device
supports MII and RMII interface modes.
There are two independent PHY devices placed on CM and MB boards that connect to two separate RJ-45 connectors
and that contain built-in magnetics and status LEDs. The LEDs are driven by PHY devices to indicate activity, link and
speed status for the respective Ethernet ports.
Figure 5-10. ETH0 Port
ETH0
J17
10Base-T/100Base-TX/1000BASE-T
8
3
3
ETH0_RX2+
ETH0_RX2-
C125 100n
C126 100n
C127 100n
C128 100n
7
9
ETH0_GND
ETH0_GND
ETH0_GND
ETH0_GND
3
3
3
ETH0_TX2+
ETH0_TX2-
1
2
4
3
3
ETH0_RX1+
ETH0_RX1-
6
5
11
12
3
3
ETH0_TX1+
ETH0_TX1-
10
13
15
17
3
3
ETH0_LED2
ETH0_LED1
L23
220ohm at 100MHz
R175
0R
1
2
3
ETH0_GND
J0G-0003NL
VDDIOP1
EARTH_ETH0
R165
R168
470R
470R
ETH0_GND
EARTH_ETH0
SAMA5D3x-EK User Guide [USER GUIDE]
63
11180B–ATARM–29-Oct-13
Figure 5-11. ETH1 Port
VDDIOP0
ETH1
C122
100n
10Base-T/100Base-TX
DNP
GND_ETH1
L20
C100
220ohm at 100MHz
10u
10V R136
0R
R170
49.9R
DNP
R162
49.9R
DNP
1
2
EARTH_ETH1
EARTH_ETH1
GND_ETH1
22R
RR17
MN20
J24
19
REF_CLK/B-CAST_OFF
E1_TXCK
E1_TX1
1
2
3
4
8
7
6
5
7
1
4
2
PC7
PC1
PC0
PC4
TXP
25
24
23
13
14
15
16
18
20
29
28
TXD1
TXD0
TXEN
PHYAD0
PHYAD1
RXD1/PHYAD2
RXD0/DUPLEX
CRS_DV/CONFIG2
RXER/ISO
CONFIG1
CONFIG0
E1_TX0
R176
R177
0R
0R
DNP
DNP
E1_TXEN
6
TXM
E1_RX1
1
2
3
4
8
7
6
5
E1_AVDDT
PC3
PC2
PC5
PC6
E1_RX0
E1_CRSDV
E1_RXER
5
3
5
6
RXP
22R
RR19
4
RXM
22R
RR18
R60
R59
1k
1k
VDDIOP0
C118
100n
C129
100n
E1_MDC
E1_MDIO
INT_ETH1
C39
2.2u
1
8
7
6
5
12
11
21
2
PC8
MDC
MDIO
INTRP/NAND
VDD_1V2
KSZ8051RNL
R171
49.9R
DNP
R172
49.9R
DNP
2
3
4
PC9
C124 100n
7
8
PE30
1
GND
PADDLE
NC1
NC2
NC3
REXT
E1_AVDDT
VDDIOP0
L2
220ohm at 100MHz
GND_ETH1
33
22
26
27
10
1
2
3
VDDA_3V3
C123
100n
DNP
VDDIOP0
R173
6.49k/1%
RR21
10k
C31
10u
C32
100n
RR20
10k
J00-0061NL
ETH1_XO
ETH1_XI
GND_ETH1
EARTH_ETH1
8
9
XO
XI
RR22
10k
VDDIOP0
VDDIOP0
17
VDDIO
VDDIOP0
At the De-Assertion of Reset:
PHYADD[2:0]:001
CONFIG[2:0]:001,Mode:RMII
Duplex Mode:Half Duplex
Isolate Mode:Disable
C34
10u
C38
100n
D9
D8
Yellow R134
470R
470R
30
31
2
2
1
1
LED0/NWAYEN
LED1/SPEED
Green
R135
C91
22p
C88
22p
32
3,12,14
NRST
RESET
Speed Mode:100Mbps
NwayAuto-Negotiation:Enable
KSZ8041NL:R162,R170,R171,R172,R176,R177,C122,C123 a
KSZ8051NL:R162,R170,R171,R172,R176,R177,C122,C123 a
re needed.
re not needed.
Y2
3
1
25MHz
SAMA5D3x-EK User Guide [USER GUIDE]
64
11180B–ATARM–29-Oct-13
5.2.7 Audio
The MB includes a WM8904 CODEC that provides route to handle audio in the digital domain. The interface includes
audio jacks for line input (J13) and headphone line output (J15). It also connects to an electret microphone, which is
conveniently installed on the main board.
This interface can be used to play and record audio. The WM8904 chip has left and right channel line inputs, a
microphone input and an on-board microphone, as well as a left and right headphone output. The line in and headphones
can be connected through two 2.5 mm J13 and J15 audio jacks. A stereo microphone input (or a second left/right line
input) and left/right line outputs are connected to a 5-pin header (J26). The header is not installed normally.
The SAMA5D3 series processor is configured in IIS slave mode to interface with the WM8904 CODEC.
Figure 5-12. Audio Interface
3V3
3V3
L27
220ohm at 100MHz
1
2
C140
4.7u
C141
100n
C137
10u
C142
100n
AUDIO_GND
L26
220ohm at 100MHz
AUD_1V8
AVDD1V8
AVDD1V8
C46
1
2
2.2u
AUDIO_GND
AUD_1V8
VDDIOP0
C138
10u
C139
100n
HEADPHONE
L6
R122
R123
1.5k
220ohm at 100MHz
1
AUDIO_GND
MN10
C135
100n
2
5
2
3
1.5k
L7
220ohm at 100MHz
1
15
13
14
3
R226
R234
0R
0R
PA30
PA31
13,3,9
13,3,9
HPOUTR
HPOUTL
HPOUTFB
SDA
2
SCLK
1
2
R227
33R
0R DNP
0R
PD30
PC16
PC19
PC20
PC17
PC21
PC18
3,9
3,9
3
C144
100n
C145
100n
R118
R119
20R C89
20R C90
100n
100n
DNP
DNP
R230
R231
R228
R229
R232
R233
28
29
30
31
32
MCLK
4
18
16
17
0R
DNP
DNP
3
LINEOUTR
LINEOUTL
LINEOUTFB
BCLK/GPIO4
LRCLK
STEREO_3.5mm
J15
C61
470p
C62
470p
J26
MD1x5 DNP
0R
3,9
3
3,9
0R
0R
ADCDAT
DACDAT
R84
20R
R85
20R
AUDIO_GND
5
4
3
2
1
1
8
PD16
3
IRQ/GPIO1
CPCA
25
27
21
20
MIC
IN1R/DMICDAT2
IN1L/DMICDAT1
VMIDC
AUDIO_GND
MP6027P
AUDIO_GND
AUDIO_GND
C76
C45
2.2u
MIC1
C143
C136
4.7u
4.7u
AUDIO_GND
1
2
1u
10
11
CPCB
CPVOUTP
MIC1
AUDIO_GND
MICBIAS
R126
2K2
12
CPVOUTN
24
26
C41
2.2u
IN2R
IN2L
AUDIO_GND
L3
C44
2.2u
R86
2K2
R87
2K2
WM8904
R178
0R
220ohm at 100MHz
LINE IN
5
1
2
C28
C29
1u
1u
AUDIO_GND
2
3V3
AUD_1V8
L4
220ohm at 100MHz
MN7
AUDIO_GND
AUDIO_GND
AUDIO_GND
1
2
3
5
4
1
1
2
VIN VOUT
GND
C33
C35
100n
R80
47k
DNP
R81
47k
DNP
EN
BYP
C30
4.7u
4.7u
4
3
C36
2.2u
SPX5205M5-L-1-8
STEREO_3.5mm
J13
C42
470p
C43
470p
C37
100n
AUDIO_GND
AUDIO_GND
AUDIO_GND
SAMA5D3x-EK User Guide [USER GUIDE]
65
11180B–ATARM–29-Oct-13
5.2.8 HDMI Transmitter Interface
The Main Board (MB) is equipped with an HDMI transmitter interface.
The SiI9022/9024 HDMI Tx provides a complete solution for transmitting HDMI compliant digital audio/video. Specialized
audio/video processing is available within the transmitter to easily and cost-effectively add HDMI capability to consumer
electronics devices.
The user must use an HDMI cable to connect to a monitor. This cable is not provided with the SAMA5D3 series-EK. A
standard HDMI cable can be used.
Important: Do not plug in the HDMI connector to a display with the evaluation kit powered on. Be certain that the EK
board is not powered, plug in the cable to the display and then power on the SAMA5D3 series EK board.
Figure 5-13. HDMI Interface
5V
R91
2K2
F1
13,3
3V3
PC29
1
2
D7
PVDD5
C87
1812L160/12
RB160M-60
Type A connector
3V3
R272
R273
0R
0R
13,3,7
13,3,7
PA30
PA31
R105
2K2
R104
2K2
100n
DNP
R89
4.7k
3V3
R90
4.7k
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
HPD_SiI
HPD
R88
4.7k
R108
0R
DDCSDA
DDCSCL
MN9
R71
0R
1
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
32
31
30
29
28
27
25
24
23
20
19
18
17
16
15
14
13
11
10
9
59
58
BLUE0
TX_C+
TX_C-
D15
TVS
D17
TVS
D18
TVS
L38 DNP
TXC-
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
12,13,3
13,3,6
PA0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
TXC+
TXC-
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
4
1
3
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
RED0
TX_C-
TXC-
RR24
22R
R164
47k
PA1
TXC+
TX0-
PA2
PA3
PA4
PA5
PA6
PA7
62
61
2
TX_0+
TX_0-
TX_C+
TXC+
TX0+
TX0-
NCMS20C900
0R
RR25
22R
R72
R73
TX0+
TX1-
65
64
TX_1+
TX_1-
TX1+
TX1-
0R
TX1+
TX2-
PA8
PA9
68
67
RR26
22R
TX_2+
TX_2-
DNP L39 NCMS20C900
4
TX2+
TX2-
3
2
1
TX_0-
TX0-
PA10
PA11
PA12
PA13
PA14
PA15
TX2+
56
1
2
EXT_SW
R265
4.3K/1%
TX_0+
TX0+
EXT_SWING
RR27
22R
HDM19SW-4-1R-H
R74
0R
J25
Close to Chip
1V2
PC14
RR28
22R
RED1
RED2
RED3
RED4
RED5
RED6
RED7
L18
PC13
PC12
PC11
PC10
PC15
PE27
PE28
60
66
1
2
AVCC12
R75
L40
0R
DNP
AVCC_1
AVCC_2
C53
100n 100n
C54
C50
1n
C51
1n
C52
1n
C48
8
7
6
4
C49
1n
EBMS321611A520
C82
10u
57
63
4
1
3
TX_1-
TX1-
RR29
22R
AGND_1
AGND_2
100n
2
TX_1+
TX1+
3V3
69
R42
1k DNP
R41
1k
IO_SEL
NCMS20C900
0R
L19
1
R76
R77
22
3
21
46
2
CLK_HDMI
IOVCC3V3
R260
1
2
3
4
22R
8
7
6
5
22R
10k
0R
33R
0R
13,3
PA28
CLK
IOVCC18_1
IOVCC18_2
IOVCC18_3
0R
35
34
33
51
45
44
VSYNC_HDMI
HSYNC_HDMI
DE_HDMI
RR30
22R
EBMS321611A520
13,3
13,3
13,3
3
PA26
PA27
PA29
VSYNC
HSYNC
DE
RESETN
SCLK
LRCLK
C55
100n
C56
100n
C58
100n
C81
10u
DNP L41 NCMS20C900
4
3
TX_2-
TX2-
RST#
R264
PC31
1
2
R184
R282
R270
R284
TX_2+
TX2+
3V3
3,7
3,7
3,7
PC16
PC17
PC18
R78
0R
1V2
41
40
39
37
5
I2S0
I2S1
I2S2
I2S3
CVCC12_1
CVCC12_2
CVCC12_3
CVCC12_4
CVCC12_5
CVCC12_6
12
26
42
47
53
L22
EBMS321611A520
1
2
CVCC12
R285
0R
MN12 RClamp0514M
5
38
36
6
7
8
9
R266
33R
TX2+
TX2-
TX2+
TX2-
3,7
PD30
MCLK
SPDIF
LINE4
NC4
NC2
LINE3
VCC
4
3
2
1
C59
100n
C60
100n
C77
100n
C83
10u
C78
100n
C79
100n
C80
100n
T2
TSPDIF
DNP
GND
LINE2
NC3
43
TX1+
TX1-
TX1+
TX1-
CGND
NC1
10
SiI9022ACUN
LINE1
MN13 RClamp0514M
5
6
7
TX0+
TX0-
TX0+
TX0-
LINE4
NC4
NC2
LINE3
VCC
4
3
2
1
8
GND
LINE2
NC3
3V3
1V2
9
10
TXC+
TXC-
TXC+
TXC-
MN8
NC1
LINE1
1
2
3
5
VIN VOUT
GND
C86
10u
4
C84
100n
C85
10u
EN
BYP
RT9013-12PB
SAMA5D3x-EK User Guide [USER GUIDE]
66
11180B–ATARM–29-Oct-13
5.2.9 1-Wire EEPROM
The MB also features a 1-wire device as a “software identification label” to store information such as chip type,
manufacture name, production date, etc.
Figure 5-14. 1-Wire on MB
3V3
ONE WIRE EEPROM
DNP
R144
1.5k
MN16
I/O
2
3
1
4
5
6
PE25
NC1
NC2
NC3
NC4
GND
DS28EC20P
5.2.10 CAN Bus
The MB offers two CPU-controlled Controller Area Network (CAN) interfaces with transceivers available through
connectors J18 and J27.
Figure 5-15. CAN on MB
JP7
R19
J18
1
2
CAN INTERFACE
MN5
RS
D
1
2
3
4
5
6
3V3
5V
R21
R20
10k
0R
SIP2
120R
8
1
5
4
7
6
CANH
CANL
PD15
CAN0
CAN1
VDDIOP0
R40
10k
3
2
VDDIOP1
EN
R
VCC
MJM0606GE06-H
PD14
GND
SN65HVD234DR
C20
100n
C21
10u
JP8
R34
J27
1
2
MN6
1
2
3
4
5
6
3V3
5V
R32
R33
10k
0R
SIP2
120R
8
1
5
4
RS
D
7
6
CANH
CANL
3,13
3,13
PB15
PB14
VDDIOP0
R35
10k
3
2
VDDIOP1
EN
VCC
R37
0R
MJM0606GE06-H
R
GND
SN65HVD234DR
C23
C24
10u
100n
SAMA5D3x-EK User Guide [USER GUIDE]
67
11180B–ATARM–29-Oct-13
5.2.11 Smart DAA
The SAMA5D3 series MB features a Smart DAA chip to drive an analog telephone line on RJ11 6P4C port (J16).
Figure 5-16. Smart DAA
L8
220ohm at 100MHz
R92
6.81M
1
2
MN11
J16
D3
MMBD3004S-7-F
2
C63
1
2
3
4
5
6
12
4
1
TEST
RAC
TAC
EIC
470p
D4
RJ11
D5 MMBD3004S-7-F
L9
220ohm at 100MHz
C64
15
2
5
1
2
PWR
DAA_GND
6.81M
TB3100M-13-F
470p
MJM0606GE06-H
C65
100n
R93
1
2
AVDD
C66
C67
100n
11
6
100n
DAA_GND
R94
DAA_GND
TX1
DAA_GND
C68
100R
Q3
47n
RXI
R166
R167
0R
0R
2
3
4
16
14
DIBN
DIBP
DIBN
DIBP
237K
R95
280R
R96
280R
R97
280R
R98
280R
C70
47pF
C69
10n
Q2
R99
1
10
9
1
EIO
EIF
MMBAT42 DAA_GND
LAN0066-50
C71
150pF
C72
8
TXO
TXF
150pF
Q5
MMBAT42
1
1
Q4
MMBAT42
7
1
DVDD
MMBAT42
1
DVDD
13
GPIO
C73
100n
R100
3.01R
R101
3.01R
CX20548-11Z
R102
110R
DAA_GND
C74
100n
R103
9R1
DAA_GND
DAA_GND
SAMA5D3x-EK User Guide [USER GUIDE]
68
11180B–ATARM–29-Oct-13
5.2.12 SD/MMC Interface
SD/MMC is a standard Secure Digital/MultiMedia Card interface.
The MB has two high-speed Multimedia Card Interfaces (MCI).
The first interface is used as an 8-bit interface (MCI0), connected to an SD/MMC card slot.
The second interface is used as a 4-bit interface (MCI1), connected to a MicroSD card slot.
Each power line is on by default and is connected to a MOSFET controlled by a PIO to switch on or off the SD card
power.
Note: The power is connected to VCC, which is 3.3V.
Figure 5-17. SD/MMC Interface
VDD_MCI0
VDD_MCI0
VDDIOP1
RR3
10k
MCI0
JP6
R15 R16 R17 R18 R26 R36 R38 R39
68k 68k 68k 68k 68k 68k 68k 68k
C40
C12
10u
100n
1
2
R49
10k
SIP2
(MCI0_WP)
(MCI0_CD)
PD17
RR4
VDDIOP1
J7
16
15
14
(MCI0_DA1)
(MCI0_DA0)
1
2
3
4
8
7
6
5
8
PD2
PD1
7
6
5
4
3
2
1
9
27R
(MCI0_CK)
PD9
RR5
27R
R58
0R
DNP
1
2
3
4
8
7
6
5
13
12
11
10
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
PD0
PD4
PD3
1
PB10
3
7SDMM-B0-2211
RR42
VDD_MCI0
27R
(MCI0_DA4)
(MCI0_DA5)
(MCI0_DA6)
(MCI0_DA7)
Q8
IRLML6402
R47
4.7k
1
2
3
4
8
7
6
5
PD5
PD6
PD7
PD8
RR4,RR5,RR42 near SODIMM place
SD/MMCPlus CARD INTERFACE - MCI0
VDDIOP1
VDD_MCI1
MCI1
R10 R11 R12 R13
R9
10k
R14
10k
VDDIOP1
68k 68k 68k 68k
(MCI1_CD)
3
PD18
Micro SD
J6
RR1 27R
R121
0R
DNP
10
SW 2
(MCI1_DA1)
(MCI1_DA0)
1
8
7
6
5
8
7
6
5
4
3
2
1
3
3
PB21
PB20
2
3
4
11
12
13
14
1
PB12
3
(MCI1_CK)
3
PB24
VDD_MCI1
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
1
2
3
4
8
7
6
5
3
3
3
PB19
PB23
PB22
Q9
IRLML6402
R48
4.7k
PJS008-2110-0
9
RR2 27R
C93
10u
C11
100n
RR1,RR2 near SODIMM place
SAMA5D3x-EK User Guide [USER GUIDE]
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11180B–ATARM–29-Oct-13
5.2.13 ZigBee
The MB has a 10-pin male connector for the Atmel RZ600 ZigBee module.
Not populated (DNP) 0 Ohm resistors have been implemented in series with the PIO lines that are used elsewhere in the
design This ensures that in case of a conflict in the user application, the lines can be disconnected individually.
Figure 5-18. ZigBee Interface
ZIGBEE INTERFACE
DNP
DNP
DNP
DNP
J10
R52
0R
0R
0R
0R
R53
R57
0R
0R
1
3
5
7
9
2
PE29
PE30
R56
R55
R82
4
6
PC28
PC22
8
10
2
1
3V3
DNP
DNP
JP10
BD10-H
C26
2.2n
C27 DNP DNP
2.2u
C25
15p
5.2.14 LED Indicators
The main board has one red LED (D2) that is on when the board is powered.
There are two additional LEDs on the main board that are associated with on-board JTAG port. See Section 5.2.3
“Debug JTAG/ICE and DBGU”.
5.2.15 Pushbutton Switches
One reset, board reset (BP1)
One wake-up, pushbutton to bring the processor out of low-power mode (BP2)
One user momentary pushbutton
One boot memory Chip Select (CS), disabling the pushbutton (refer to Section 4.2.4.1 “Boot Configuration”).
5.2.15.1
Reset
When pressed and released, this pushbutton causes a power-on reset of the SAMA5D3 series EK (MB, CM and DM
boards).
SAMA5D3x-EK User Guide [USER GUIDE]
70
11180B–ATARM–29-Oct-13
5.2.15.2 CS_BOOT Button
The CS_BOOT can be used to prevent the system from booting out of external memories (NANDFlash, SPI Flash). The
purpose is mainly to execute the SAM-BA part of the ROM code.
Two methods can be used:
1. Press the CS_BOOT and power-cycle the board.
2. Press the CS_BOOT and then press the NRST button.
Figure 5-19. Pushbutton
3V3
PUSH BUTTON
VBAT
R141
100k
R142
1.5k
PB1
PB2
PB3
NRST
NRST
3,10,14
WAKE UP
PB_USER1
WAKE UP
PE27
3
3,9,13
PB4
R46
0R
CS_BOOT_DISABLE
3
CS_BOOT
5.2.16 Analog Reference
The 3V voltage reference is based on an LM4040 (Precision Micropower Shunt Voltage Reference).
This ADVREF level can be set as 3V or 3.3V via the jumper JP14.
Figure 5-20. Analog Reference
VDDANA
5V
ANALOG Reference 3V
R143
1.5k
JP14
2
ADVREF
3V
C112
100n
C113
2.2u
D6
LM4040BIM3-3.0+T
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11180B–ATARM–29-Oct-13
5.2.17 Expansion Ports
Three 40-pin headers (J1, J2, J3) are provided on the board to allow for the PIO connection of various expansion cards
that could be developed by the users or other sources. Due to multiplexing, different signals can be provided on each pin.
Figure 5-21. I/O Expansion
VDDIOP1
1
5V
VDDIOP0
1
5V
VDDIOP0
JP1
5V
JP3
JP2
3
3
1
3
J3
J2
J1
MD2X20-H
MD2X20-H
MD2X20-H
1
3
2
1
3
5
7
9
2
1
3
2
4
4
4
PB10
PB31
5
7
6
8
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC16
5
6
6
8
PB12
PB14
PB15
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PE23
PE24
PE25
PE26
PE29
PE30
PE31
PD10
PD11
PD12
PD13
PD14
PD15
PD19
PD31
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
7
9
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PC9
PC10
PC11
PC12
PC13
PC14
PC15
VDDIOM
VDDIOM
VDDIOP0
VDDIOP0
VDDIOP0
Two connectors (J21, J22) are provided on-board to interface the optional LCD and touchscreen display module (DM)
board.
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11180B–ATARM–29-Oct-13
Figure 5-22. LCD Expansion
3V3
J21
LCD
1
3
2
4
5
6
8
R147
0R
0R
R148
R149
0R
0R
3,6
PE30
PC26
PA15
PA13
PA14
PA12
PA0
10,3,6
13,3
3,9
PE31
PC27
7
9
R146
13,3
10
12
14
16
18
20
22
24
26
28
30
1
8
7
6
5
8
7
6
5
3
4
11
13
15
17
19
21
23
25
27
29
2
3
4
1
2
3
4
RR13
22R
3,9
3,9
3,9
3,9
1
8
7
6
5
RR12
22R
3,9
PA2
3,9
PA1
2
3
4
1
2
RR11
22R
3,9
3,9
3,9
3,9
3,9
PA4
3,9
PA3
PA5
PA7
PA9
PA11
PA6
3,9
RR43C
PA8
3,9
RR43A
RR43B
8
7
6 RR43D
5
PA10
3,9
ESW-115-33-L-D
5V_LCD
J22
1
3
2
LCD/TSC
11
5V_LCD
4
1
8
7
6
5
5
6
8
1
2
3
4
8
7
6
5
3,9
3,9
3,9
PC13
3,9
3,9
3,9
PC14
PC12
PC10
PE27
2
3
4
7
9
RR16
RR23
22R
PC11
PC15
PE28
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
22R
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
12,3,9
3,6,9
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
3
3,9
3,9
PA24
PA27
PA28
3
PA25
PA26
PA29
RR14
22R
RR15
22R
13,3,9
3,9
R150
0R
0R
0R
R151
R153
R155
0R
0R
0R
3
3
3
PD21
PD23
PE25
3
3
12,3
PD20
PD22
PD24
R152
R154
R156
R158
R160
R169
0R
0R
0R
0R
R157
R159
R161
R174
0R
0R
0R
0R
3,6
3,6
11
PC23
PC28
3,6
PC22
PC24
EN_PWRLCD
PB14
13,3,6
LCD_DETECT# 11
3,6
3,6
PB15
ESW-120-33-L-D
DNP
R127
0R
3
PA27
13,3,9
PD19
All I/Os of the SAMA5D3 series Image Sensor Interface (ISI) are routed to connectors J11.
Figure 5-23. ISI Expansion
VDDIOP0
J11
TSW-115-07-L-D
R125
1.5k
ISI
1
3
2
4
VDDISI
4
5
6
PE29
3,6
3,6,9 PE28
3
7
9
8
PC26
3
PC27
10
12
14
16
18
20
22
24
26
28
30
PC15
PA30
PA31
PC30
PA16
PA18
PA20
PA22
PC29
PC27
3,9
R124
1.5k
11
13
15
17
19
21
23
25
27
29
VDDIOP0
3,7,9
3,7,9
3
3
3
3
3
3
3
3
PA17
PA19
PA21
PA23
PC28
PC26
3
3
3
3,6
3
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5.3
Configuration
Table 5-2 describes the PIO usage, the jumpers, the test points and the solder drops of a SAMA5D3 series EK board.
Table 5-2.
Reference
Jumpers and Solderdrops
Default
1-2
Function
JP1
JP2
VDDIOP0 or 5V selection for J1
VDDIOP0 or 5V selection for J2
VDDIOP0 or 5V selection for J3
Backup supply on/off
1-2
JP3
1-2
JP4
CLOSE
CLOSE
CLOSE
CLOSE
CLOSE
OPEN
OPEN
—
JP5
Force power on function
JP6
MCI0 write protect select
JP7
CAN0 diff termination select
CAN1 diff termination select
Default boot on embedded ROM, close boot on external memory
ZigBee power on/off select
JP8
JP9
JP10
JP11
JP12
JP13
JP14
JP15
JP16
—
—
1-2
ADVREF input selection
JTAG enable
OPEN
OPEN
CDC enable
OPEN
Enable LCD for D31, D33, D34
Disable LCD for D35
JP17
JP18
CLOSE
1-2
SAM3U powered by main 3V3
Table 5-3.
Default Not Populated Parts
Page
Reference
Function
3
R6,R51,R50,R120
Optional PD10, PD11, PD12, PD13 from MB
Optional for MCI0 power supply mode
Optional for MCI1 power supply mode
Optional ZigBee
R58
5
6
R121
R52,R53,R55,R56,R57,R82,JP10
R132,R133
Debug or USART1 option
Optional Audio Line out, MIC in
Optional MIC level setting
Optional audio TK
C89,C90,R118,R119,J26
7
9
R80,R81
R230
L38,L39,L40,L41
R89
Optional HDMI EMI filter
HDMI chip I2C address setting
Optional for I2S PCLK
R266
R42
Optional for LCD PCLK
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11180B–ATARM–29-Oct-13
Table 5-3.
Page
Default Not Populated Parts
Reference
Function
R162,R170,R171,R172,R176,R17
7,C122,C123
10
Optional for KSZ8041NL
12
13
R144
R127
Optional pull up for DS28EC20P
Optional for ADC trigger
R79,R106,R107,R109,R113,R110,
R112,R111,J9
Optional JTAG
R54
SAM3U JTAG selection
5V option
14
R63
D11,D12
R186
USB ESD protect option
Main 3V3 optional for VCC_3V3_DEBUG
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5.4
PIO Usage and Interface Connectors Details
5.4.1 Power Supply
Figure 5-24. Power Supply Connector J4
Table 5-4.
Power Supply Connector J4 Signal Description
Pin
1
Mnemonic
Signal Description
Center
+5V
2
GND
3
Floating
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5.4.2 JTAG/ICE Connector
Figure 5-25. JTAG J9
Table 5-5.
Pin
JTAG/ICE Connector J9 Signal Descriptions
Mnemonic
Signal Description
This is the target reference voltage. It is used to check if the target has
power, to create the logic-level reference for the input comparators, and
to control the output logic levels to the target. It is normally fed from VDD
on the target board and must not have a series resistor.
1
2
3
VTref 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility with
other equipment. Connect to VDD or leave open in target system.
Vsupply 3.3V power
JTAG Reset. Output from SAM-ICE to the Reset signal on the target
JTAG port. Typically connected to nTRST on the target CPU. This pin is
normally pulled High on the target to avoid unintentional resets when
there is no connection.
nTRST Target Reset - Active-low
output signal that resets the target.
4
5
6
GND
Common ground
TDI Test Data Input - Serial data
output line, sampled on the rising
edge of the TCK signal.
JTAG data input of target CPU. It is recommended that this pin is pulled
to a defined state on the target board. Typically connected to TDI on
target CPU.
GND
Common ground
JTAG mode set input of target CPU. This pin should be pulled up on the
target. Typically connected to TMS on target CPU. Output signal that
sequences the target's JTAG state machine, sampled on the rising edge
of the TCK signal.
7
TMS Test Mode Select.
8
9
GND
Common ground
TCK Test Clock - Output timing
signal, for synchronizing test logic
and control register access.
JTAG clock signal to target CPU. It is recommended that this pin is
pulled to a defined state on the target board. Typically connected to TCK
on target CPU.
10
GND
Common ground
Some targets must synchronize the JTAG inputs to internal clocks. To
assist in meeting this requirement, a returned and retimed TCK can be
used to dynamically control the TCK rate. SAM-ICE supports adaptive
clocking which waits for TCK changes to be echoed correctly before
making further changes. Connect to RTCK if available, otherwise to
GND.
RTCK - Input Return Test Clock
signal from the target.
11
12
13
GND
Common ground
TDO JTAG Test Data Output -
Serial data input from the target.
JTAG data output from target CPU. Typically connected to TDO on
target CPU.
14
15
GND
Common ground
nSRST RESET
Active-low reset signal. Target CPU reset signal.
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Table 5-5.
JTAG/ICE Connector J9 Signal Descriptions
Pin
16
17
18
19
20
Mnemonic
GND
Signal Description
Common ground
RFU
This pin is not connected in SAM-ICE.
Common ground
GND
RFU
This pin is not connected in SAM-ICE.
Common ground
GND
5.4.3 USB Type A Dual Port
Figure 5-26. USB Type A Dual Port J19
Table 5-6.
Pin
A1
USB Type A Dual Port J19 Signal Descriptions
Mnemonic
Vbus - USB_A
DM - USB_A
DP - USB_A
GND
PIO
Signal Description
5V power
A2
Data minus
A3
Data plus
A4
Common ground
5V power
B1
Vbus - USB_A
DM - USB_A
DP - USB_A
GND
B2
Data minus
B3
Data plus
B4
Common ground
Mechanical
pins
Shield
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5.4.4 USB MicroAB
Figure 5-27. USB Host/Device MicroAB Connector J20
Table 5-7.
USB Host/Device Micro AB Connector J20 Signal Descriptions
Pin
1
Mnemonic
Vbus
DM
PIO
Signal Description
5V power
2
Data minus
3
DP
Data plus
4
ID
On the Go identification
Common ground
5
GND
5.4.5 JTAG OB USB MicroAB
Figure 5-28. USB JTAG OB MicroAB connector J14
Table 5-8.
USB JTAG OB MicroAB connector J14 Signal Descriptions
Pin
1
Mnemonic
Vbus
DM
PIO
Signal description
5V power
2
Data minus
3
DP
Data plus
4
ID
On the Go Identification
Common ground
5
GND
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5.4.6 HDMI Connector
Figure 5-29. HDMI Female Type A Connector J25
Table 5-9.
LCD
HDMI Type A Female Connector J25
Pin Num
LCD
TMDS Data 2+
TMDS Data 2-
1
3
2
4
TMDS Data 2 Shield
TMDS Data 1+
TMDS Data 1-
TMDS Data 0 Shield
TMDS Clock +
TMDS Clock -
NC
TMDS Data 1 Shield
TMDS Data 0+
TMDS Data 0-
TMDS Clock Shield
NC
5
6
7
8
9
10
12
14
16
18
11
13
15
17
19
SCL
SDA
GND
+5V
Hot Plus Detect
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5.4.7 RS232 Connector with RTS/CTS Handshake Support
Figure 5-30. USART1 Connector J8
Table 5-10.
USART Connector J8 Signal Descriptions
Mnemonic
Pin
PIO
Signal Description
1, 4, 6, 9
No connection
2
3
5
7
8
RXD (Received Data)
TXD (Transmitted Data)
GND
PB28
PB29
RS232 serial data output signal
RS232 serial data input signal
Common ground
RTS (Request To Send)
CTS (Clear To Send)
PB27
PB26
Active-positive RS232 input signal
Active-positive RS232 output signal
Mechanical
pins
Shield
5.4.8 DAA RJ11 Socket (6P4C)
Figure 5-31. DAA RJ11 Socket J16
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11180B–ATARM–29-Oct-13
Table 5-11.
DAA RJ11 Socket J16 Signal Descriptions
Mnemonic
Pin
Signal Description
1, 2, 5, 6
No connection
3
4
RAC
TAC
RING side of ordinary telephone line
TIP side of ordinary telephone line
5.4.9 CAN RJ12 Socket (6P6C)
Figure 5-32. CAN RJ12 Socket J18, J27
Table 5-12.
CAN RJ12 Socket Signal Descriptions
Pin
1
Mnemonic
3V3
Signal Description
Power pin
2
5V
Power pin
4
CANL
CANH
GND
CAN bus differential pair
CAN bus differential pair
Common ground
5
3, 6
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5.4.10 SD/MMC Plus MCI0
Figure 5-33. SD Socket J7
Table 5-13.
MicroSD Socket J7 Signal Descriptions
Pin
1
Mnemonic
DAT3
CMD
VSS
PIO
PD4
PD0
Signal Description
Data bit
2
Command line
Command line
Supply voltage 3.3V
Clock / command line
Card detect
Data bit
3
4
VCC
5
CLK
PD9
PD17
PD1
PD2
PD3
PD5
PD6
PD7
PD8
JP6
6
CD
7
DAT0
DAT1
DAT2
DAT4
DAT5
DAT6
DAT7
WP
8
Data bit
9
Data bit
10
11
12
13
14
15
16
Data bit
Data bit
Data bit
Data bit
Protect
VSS
VSS
Common ground
Common ground
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5.4.11 MicroSD MCI1
Figure 5-34. MicroSD Socket J6
Table 5-14.
MicroSD Socket J6 Signal Descriptions
Pin
1
Mnemonic
DAT2
PIO
Signal Description
Data bit 2
PB22
PB23
PB19
2
CD/DAT3
CMD
Card detect / data bit 3
Command line
3
4
VCC
Supply voltage 3.3V
Clock / command line
Common ground
Data bit 0
5
CLK
PB24
6
VSS
7
DAT0
PB20
PB21
8
DAT1
Data bit 1
9
SW1
Not used, grounded
Card detect
10
CARD DETECT
PD18
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5.4.12 Gigabit Ethernet ETH0 RJ45 Socket J17
Figure 5-35. Gigabit Ethernet RJ45 Socket J17
5.4.13 Ethernet ETH1 RJ45 Socket J24
Figure 5-36. Ethernet RJ45 Socket J24
5.4.14
ZigBee Socket J10
Figure 5-37. ZigBee Socket J10
Table 5-15.
Function
ZigBee Socket J10 Signal Descriptions
Signal
Name
Signal
Name
Option on Misc. Port Set
by OR or Solder Shunts
Port
Pin
Pin
Port
Function
EEPROM for MAC address, cap array
settings and serial number
Reset
/RST
IRQ
1
2
Misc.
TST: test mode activation
CLKM: RF chip clock output
Interrupt
Request
3
4
SLP_TR
SLP_TR
SPI chip
select
/SEL
MISO
GND
5
7
9
6
8
MOSI
SCLK
VCC
SPI MOSI
SPI CLK
SPI MISO
Power
Supply
Voltage range: 1.8V to 5.5V,
regulated to 3.3V
GND
10
VCC
VCC
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5.4.15 LCD Socket J21
Figure 5-38. LCD Socket J21
Table 5-16.
LCD
LCD Socket J21 HE10 Female LCD 2*15p
Pin Number
LCD
VDD3V3
VDD3V3
ZB_IRQ0
TWCK1
GND
1
2
GND
3
4
GND
5
6
ZB_IRQ1
TWD1
7
8
9
10
12
14
16
18
20
22
24
26
28
30
LCDDAT15
LCDDAT13
LCDDAT14
LCDDAT12
LCDDAT0
LCDDAT2
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
GND
GND
11
13
15
17
19
21
23
25
27
29
GND
GND
GND
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT7
LCDDAT9
LCDDAT11
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5.4.16 LCD/TSC Socket J22
Figure 5-39. LCD/TSC Socket J22
Table 5-17.
LCD
LCD/TSC Socket J22 HE10 Female LCD/TSC/QT 2*20p
Pin Number
LCD
5V
5V_LCD
5V_LCD
1
2
GND
GND
GND
5V
3
4
GND
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT22
GND
5
6
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT23
GND
7
8
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
GND
GND
LCDDISP
LCDCSYNC
LCDDEN
GND
LCDPWM
LCDHSYNC
LCDPCK
GND
GND
TSC
TSC
TSC
GND
GND
TSC
TSC
AD0_XP
AD2_YP
AD4_LR
GND1
AD1_XM
AD3_YM
ONE_WIRE
GND
GND
SPI1_MISO
SPI1_SPCK
EN_PWRLCD
SPI1_MOSI
SPI1_NPCS3
LCD_DETECT#
LCD_DETECT
PB15
PB14
GND
GND
GND
GND
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5.4.17 ISI Socket J11
Figure 5-40. ISI Socket J11
Table 5-18.
ISI
ISI Socket J11 HE10 Female ISI 2*15p
Pin Number
ISI
VDDISI
VDDISI
ZB_SLPTR
TWCK1
GND
1
2
GND
3
4
GND
5
6
ZB_RST
TWD1
7
8
9
10
12
14
16
18
20
22
24
26
28
30
ISI_MCK
ISI_VSYNC
ISDI_HSYNC
ISI_PCK
ISI_D0
ISI_D2
ISI_D4
ISI_D6
ISI_D8
ISI_D10
GND
GND
11
13
15
17
19
21
23
25
27
29
GND
GND
GND
ISI_D1
ISI_D3
ISI_D5
ISI_D7
ISI_D9
ISI_D11
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5.4.18 PIO Usage
Table 5-19.
Power Rail
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
PIO A Pin Assignment and Signal Description
Signal
PA0
Signal
Signal
PIO
Signal
PU
SAMA5-CM
SAMA5-MB
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
ISI_D0
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT16
LCDDAT17
LCDDAT18
LCDDAT19
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
LCDPWM
LCDDISP
LCDVSYNC
LCDHSYNC
LCDPCK
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PA1
PIO
PU
PA2
PIO
PU
PA3
PIO
PU
PA4
PIO
PU
PA5
PIO
PU
PA6
PIO
PU
PA7
PIO
PU
PA8
PIO
PU
PA9
PIO
PU
PA10
PA11
PA12
PA13
PA14
PA15
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
PIO
PU
PIO
PU
PIO
PU
PIO
PU
PIO
PU
PIO
PU
ISI_D0
ISI_D1
TWD2
TWCK2
PWMH0
PWML0
PWMH1
PWML1
PIO
PIO
PIO
ISI_D1
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
PU
ISI_D2
ISI_D3
ISI_D4
ISI_D5
ISI_D6
ISI_D7
LCDPWM
LCDDISP
LCDVSYNC
LCDHSYNC
LCDPCK
LCDDEN
ISI_VSYNC
ISI_HSYNC
PIO
PU
PIO
PU
PIO
PU
PIO
PU
LCDDEN
PIO
PU
TWD0
URXD1
UTXD1
ISI_VSYNC
ISI_HSYNC
TWCK0
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11180B–ATARM–29-Oct-13
Table 5-20.
Power Rail
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP0
VDDIOP0
PIO B Pin Assignment and Signal Description
Signal
PB0
Signal
GTX0
Signal
PWMH0
PWML0
TK1
Signal
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PU
SAMA5-CM
SAMA5-MB
GETH CM
–
PB1
GTX1
GETH CM
–
PB2
GTX2
GETH CM
–
PB3
GTX3
TF1
GETH CM
–
PB4
GRX0
PWMH1
PWML1
TD1
GETH CM
–
PB5
GRX1
GETH CM
–
PB6
GRX2
GETH CM
–
PB7
GRX3
RK1
GETH CM
–
–
PB8
GTXCK
GTXEN
GTXER
GRXCK
GRXDV
GRXER
GCRS
PWMH2
PWML2
RF1
GETH CM
PB9
GETH CM
–
PB10
PB11
PB12
PB13
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
–
PWR_MCI0
–
RD1
GETH CM
PWMH3
PWML3
CANRX1
CANTX1
PIO
–
PWR_MCI1
RX_DV (KSZ9021)
CANRX1
CANTX1
–
GETH CM
–
GCOL
–
GMDC
GMDIO
G125CK
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_CK
SCK1
GETH CM
PIO
PU
GETH CM
–
PIO
PU
GETH CM
–
GTX4
GTX5
GTX6
GTX7
GRX4
GRX5
GRX6
GRX7
PWMH1
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PIO
PU
–
MCI1_CDA
MCI1_DA0
MCI1_DA1
MCI1_DA2
MCI1_DA3
MCI1_CK
–
–
–
–
–
–
INT_GETH0
CTS1
–
–
–
–
–
–
CTS1
RTS1
RTS1
RXD1
RXD1
TXD1
PIO
PU
TXD1
DRXD
PIO
PU
DRXD (DBGU)
DTXD (DBGU)
DTXD
PIO
PU
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11180B–ATARM–29-Oct-13
Table 5-21.
Power Rail
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
PIO C Pin Assignment and Signal Description
Signal
PC0
Signal
Signal
TIOA3
TIOB3
TCLK3
TIOA4
TIOB4
TCLK4
TIOA5
TIOB5
TCLK5
PIO
Signal
PIO
SAMA5-MB
ETX0
ETX0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PC1
ETX1
PIO
ETX1
PC2
ERX0
PIO
ERX0
PC3
ERX1
PIO
ERX1
PC4
ETXEN
PIO
ETXEN
PC5
ECRSDV
ERXER
EREFCK
EMDC
PIO
ECRSDV
ERXER
PC6
PIO
PC7
PIO
EREFCK
EMDC
PC8
PIO
PC9
EMDIO
PU
EMDIO
PC10
PC11
PC12
PC13
PC14
PC15
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
MCI2_CDA
MCI2_DA0
MCI2_DA1
MCI2_DA2
MCI2_DA3
MCI2_CK
TK0
LCDDAT20
LCDDAT19
TIOA1
TIOB1
TCLK1
PCK2
PIO
PIO
LCDDAT20
LCDDAT19
LCDDAT18
LCDDAT17
LCDDAT16
LCDDAT21
TK0 Audio
TF0 Audio
TD0 Audio
RK0 Audio
RF0 Audio
RD0 Audio
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
ISI_D11
PIO
LCDDAT18
LCDDAT17
LCDDAT16
LCDDAT21
PU
ISI_MCK
–
–
–
–
–
–
TF0
PIO
PU
TD0
PIO
PU
RK0
PIO
PU
RF0
PIO
PU
RD0
PIO
PU
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
SPI1_NPCS0
SPI1_NPCS1
SPI1_NPCS2
SPI1_NPCS3
URXD0
PIO
PU
SPI LCD
SPI LCD
SPI LCD
PIO
PU
PIO
PU
PIO
PU
–
TWD1
TWCK1
PWMFI0
PWMFI2
ISI_PCK
PWMFI1
ISI_D11
ISI_D10
ISI_D9
ISI_D8
PIO
TWI LCD
TWI LCD
SPI LCD
HDMI_INT
–
ISI_D10
ISI_D9
ISI_D8
UTXD0
ISI_PCK
–
FIQ
PIO
Reset_HDMI
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11180B–ATARM–29-Oct-13
Table 5-22.
Power Rail
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
PIO D Pin Assignment and Signal Description
Signal
PD0
Signal
Signal
PIO
Signal
PU
SAMA5-MB
MCI0_CDA
MCI0_CDA
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_DA4
MCI0_DA5
MCI0_DA6
MCI0_DA7
MCI0_CK
SPI0_MISO
SPI0_MOSI
SPI0_SPCK
SPI0_NPCS0
SCK0
–
PD1
PIO
PU
–
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_DA4
MCI0_DA5
MCI0_DA6
MCI0_DA7
MCI0_CK
–
PD2
PIO
PU
–
PD3
PIO
PU
–
PD4
PIO
PU
–
PD5
TIOA0
TIOB0
TCLK0
PWML3
PIO
PWMH2
PWML2
PWMH3
PIO
–
PD6
–
PD7
–
PD8
–
PD9
PU
–
PD10
PD11
PD12
PD13
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PD22
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
PD31
PIO
PU
CM_SerFlash
PIO
PU
CM_SerFlash
–
PIO
PU
CM_SerFlash
–
PIO
PU
CM_SerFlash
–
SPI0_NPCS1
SPI0_NPCS2
SPI0_NPCS3
PIO
CANRX0
CANTX0
PWMFI3
PU
–
CANRX0
CANTX0
–
CTS0
–
RTS0
INT_AUDIO
RXD0
–
MCI0_CD
MCI1_CD
ADTRG (HSYNC)
LCD TSC
LCD TSC
LCD TSC
LCD TSC
LCD TSC
EN5V_USBA
EN5V_USBB
EN5V_USBC
OVCUR_USB
VBUS_SENSE
MCLK_HDMI
ISI_MCK
TXD0
PIO
PU
–
ADTRG
AD0
PIO
PU
–
PIO
PU
–
AD1
PIO
PU
–
AD2
PIO
PU
–
AD3
PIO
PU
–
AD4
PIO
PU
–
AD5
PIO
PU
–
AD6
PIO
PU
–
AD7
PIO
PU
–
AD8
PIO
PU
–
AD9
PIO
PU
–
MCLK_AUDIO
–
AD10
PCK0
PCK1
PIO
AD11
PIO
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11180B–ATARM–29-Oct-13
Table 5-23.
Power Rail
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
VDDIOM
PIO E Pin Assignment and Signal Description
Signal
PE0
Signal
A0/NBS0
A1
Signal
SAMA5-CM
SAMA5-MB
I
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PE1
I
NOR
PE2
A2
I
NOR
PE3
A3
I
NOR
PE4
A4
I
NOR
PE5
A5
I
NOR
PE6
A6
I
NOR
PE7
A7
I
NOR
PE8
A8
I
NOR
PE9
A9
I
NOR
PE10
PE11
PE12
PE13
PE14
PE15
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
PE24
PE25
PE26
PE27
PE28
PE29
PE30
PE31
A10
I
NOR
A11
I
NOR
A12
I
NOR
A13
I
NOR
A14
I
NOR
A15
SCK3
CTS3
RTS3
RXD3
TXD3
SCK2
I
NOR
A16
NOR
A17
NOR
A18
NOR
A19
NOR
A20
NOR
A21/NANDALE
A22/NANDCLE
A23
NOR / NAND
NOR / NAND
NOR
I
CTS2
RTS2
RXD2
TXD2
TIOA2
TIOB2
TCLK2
I
A24
Power LED
ISI_RST
A25
1-Wire / User LED 1-Wire
CS NOR
NCS0
NCS1
NCS2
NWR1/NBS1
NWAIT
IRQ
–
–
–
–
–
–
PB_USER1
ZB_SLPTR
ZB_RST
LCDDAT22
LCDDAT23
–
ZB_IRQ1
ZB_IRQ0
INT_ETH1
HDMI_INT
PWML1
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11180B–ATARM–29-Oct-13
5.4.19 IO Expansion Port J1
Figure 5-41. IO Expansion Socket J1
Table 5-24.
Signal
VDDIOP0 / 5V
GND
IO Expansion Socket J1 HE10 Male 2*20 Signal Descriptions
Pin Number
Signal
VDDIOP0 / 5V
GND
1
2
3
4
PA0
5
6
PA16
PA1
7
8
PA17
PA2
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PA18
PA3
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PA19
PA4
PA20
PA5
PA21
PA6
PA22
PA7
PA23
PA8
PA24
PA9
PA25
PA10
PA11
PA26
PA27
PA12
PA13
PA14
PA15
GND
PA28
PA29
PA30
PA31
GND
VDDIOP0
VDDIOP0
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94
11180B–ATARM–29-Oct-13
5.4.20 IO Expansion Port J2
Figure 5-42. IO Expansion Socket J2
Table 5-25.
Signal
VDDIOP0 / 5V
GND
Expansion Socket J2 HE10 Male 2*20 Signal Descriptions
Pin Number
Signal
VDDIOP0 / 5V
GND
1
2
3
4
PC0
5
6
PC16
PC1
7
8
PC17
PC2
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PC18
PC3
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PC19
PC4
PC20
PC5
PC21
PC6
PC22
PC7
PC23
PC8
PC24
PC9
PC25
PC10
PC11
PC12
PC13
PC14
PC15
GND
PC26
PC27
PC28
PC29
PC30
PC31
GND
VDDIOP0
VDDIOP0
SAMA5D3x-EK User Guide [USER GUIDE]
95
11180B–ATARM–29-Oct-13
5.4.21 IO Expansion Port J3
Figure 5-43. IO Expansion Socket J3
Table 5-26.
Signal
VDDIOP0 / 5V
GND
Expansion Socket J3 HE10 Male 2*20 Signal Descriptions
Pin Number
Signal
VDDIOP0 / 5V
GND
1
2
3
4
PB10
5
6
PB31
PB12
7
8
PE23
PB14
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PE24
PB15
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PE25
PB19
PE26
PB20
PE29
PB21
PE30
PB22
PE31
PB23
PD10
PB24
PD11
PB25
PD12
PB26
PD13
PB27
PD14
PB28
PD15
PB29
PD19
PB30
PD31
GND
GND
VDDIOP0
VDDIOP0
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11180B–ATARM–29-Oct-13
5.4.22
SODIMM Card Edge Socket
The SAMA5D3 series-EK implements a SODIMM200 standard connector for to interface to the CM board.
Note this is not an industry standard pinout and is unlikely to be compatible with off-the-shelf SODIMM.
Figure 5-44. SODIMM200 Socket CON1
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97
11180B–ATARM–29-Oct-13
Table 5-27.
PIOC
SODIMM200 CON1 Signal Descriptions
PIOB
PIOA
SODIMM 200
PIOA
PIOB
PIOC
Front Side
VCC 5V
VCC 5V
A
1
B
Back Side
2
VCC 5V
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
4
VCC 5V
VBAT
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GND
5
6
CTS2
PE23
7
8
PE29
PE30
PE31
–
NWR1/NBS1
TCLK2
RTS2
PE24
PE25
PE26
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
NWAIT
IRQ
–
RXD2
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
PWML1
GND
–
TXD2
–
VDDIOM
SPI1_NPCS0
SPI1_MOSI
RD0
VDDIOM
PC25
PC23
PC21
PC24
PC22
PC20
PC19
PC17
PC9
SPI1_SPCK
SPI1_MISO
RF0
–
–
–
GND
RK0
–
TD0
PC18
PC16
PC8
TF0
–
TK0
EMDIO
EREFCK
–
PIO
TIOB5
GND
TCLK4
TIOA4
TIOB3
TCLK5
TIOA5
TIOB4
TCLK3
TIOA3
EMDC
ERXER
ETXEN
ERX0
PC7
PC6
–
PC4
PC5
ECRSDV
ERX1
PC2
PC3
ETX0
PC0
PC1
ETX1
Power Enable
Enable_0
Enable_1
CS Boot Disable
KEY
VCC 3V3
VCC 3V3
Enable_2
41
43
45
47
49
51
53
55
57
59
61
63
65
67
42
44
46
48
50
52
54
56
58
60
62
64
66
68
VCC 3V3
VCC 3V3
NC
–
–
–
–
–
–
–
–
–
–
–
–
Enable_3
–
NC
–
–
NC
ADVREF
–
LCDDAT22
–
–
TIOA2
NCS1
PE27
PC10
PE28
PC11
PC13
PC15
PC26
PC28
–
NCS2
TIOB2
LCDDAT23
PIO
LCDDAT20
–
MCI2_CDA
GND
MCI2_DA0
MCI2_DA2
MCI2_CK
SPI1_NPCS1
SPI1_NPCS3
GND
LCDDAT19
TIOB1
PCK2
–
–
–
LCDDAT17
LCDDAT21
ISI_D11
ISI_D9
–
LCDDAT18
LCDDAT16
ISI_D10
ISI_D8
–
TIOA1
TCLK1
–
MCI2_DA1
MCI2_DA3
SPI1_NPCS2
URXD0
PC12
PC14
PC27
PC29
PC31
PWMFI0
–
PWMFI2
PWMFI1
FIQ
PC30
UTXD0
ISI_PCK
–
VDDIOP0
LCDDAT0
VDDIOP0
–
–
PA0
PA1
LCDDAT1
–
–
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11180B–ATARM–29-Oct-13
Table 5-27.
SODIMM200 CON1 Signal Descriptions
PIOC
PIOB
PIOA
SODIMM 200
PIOA
PIOB
PIOC
–
–
–
–
–
–
–
–
–
LCDDAT2
GND
PA2
69
71
70
72
PA3
PA4
PA6
PA8
PA10
LCDDAT3
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
GND
–
–
–
–
–
–
–
–
–
–
–
–
LCDDAT5
LCDDAT7
LCDDAT9
LCDDAT11
LCDDAT12
LCDDAT14
LCDDAT16
LCDDAT18
GND
PA5
73
74
–
–
–
PA7
75
76
–
PA9
77
78
–
–
PA11
PA12
PA14
PA16
PA18
79
80
–
–
81
82
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
LCDDAT13
LCDDAT15
LCDDAT17
LCDDAT19
LCDDAT20
LCDDAT22
LCDPWM
LCDVSYNC
GND
–
–
83
84
–
–
ISI_D0
TWD2
85
86
ISI_D1
TWCK2
PWMH0
PWMH1
–
–
–
ISI_D2
87
88
ISI_D3
89
90
ISI_D4
–
–
–
ISI_D5
PWML0
LCDDAT21
LCDDAT23
LCDDISP
LCDHSYNC
LCDPCK
TWD0
PA21
PA23
PA25
PA27
PA28
PA30
91
92
ISI_D6
ISI_D7
PWML1
93
94
–
95
96
–
–
–
–
97
98
–
–
–
–
–
–
–
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
PA29
PA31
LCDDEN
TWCK0
–
ISI_VSYNC
URXD1
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
UTXD1
ISI_HSYNC
VDDANA
VDDANA
PCK1
PCK0
AD10
PD30
PD31
PD29
PD27
PD25
PD23
AD11
–
–
–
–
GND
–
AD9
–
–
–
–
–
–
–
–
AD8
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
AD7
–
–
–
AD6
AD5
–
–
–
–
–
AD4
AD3
–
AD2
GND
–
–
–
AD0
PD21
PD19
PD17
PD15
PD13
PD11
PD9
AD1
–
–
–
–
–
TXD0
ADTRG
RXD0
–
PWMFI3
SPI0_NPCS3
RTS0
PIO
–
CANRX0
SPI0_NPCS1
SCK0
CTS0
SPI0_NPCS2
CANTX0
GND
SPI0_NPCS0
SPI0_MOSI
MCI0_CK
MCI0_DA6
GND
–
–
–
–
–
SPI0_SPCK
SPI0_MISO
MCI0_DA7
MCI0_DA5
MCI0_DA4
MCI0_DA2
MCI0_DA0
PD12
PD10
PD8
PD6
PD5
PD3
PD1
–
–
–
–
–
–
PIO
–
–
PWML3
TIOB0
TIOA0
–
PD7
TCLK0
PWMH3
PWML2
PWMH2
–
–
–
–
–
–
–
–
–
PD4
PD2
PD0
MCI0_DA3
MCI0_DA1
MCI0_CDA
–
–
VDDIOP1
VDDIOP1
SAMA5D3x-EK User Guide [USER GUIDE]
99
11180B–ATARM–29-Oct-13
Table 5-27.
SODIMM200 CON1 Signal Descriptions
PIOC
–
PIOB
PIOA
SODIMM 200
PIOA
GRXER
GRXDV
GCOL
MCI1_DA0
MCI1_DA2
GND
PIOB
PWML3
PWMH3
CANTX1
GTX5
GTX7
–
PIOC
–
GND
–
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
PB13
PB12
PB15
PB20
PB22
–
RF1
GTXER
PB10
PB14
PB19
PB21
PB23
PB24
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CANRX1
GTX4
GCRS
–
–
MCI1_CDA
MCI1_DA1
MCI1_DA3
MCI1_CK
GND
GTX6
–
GRX4
GRX5
–
–
–
PB25
PB27
PB29
PB31
PB30
PB26
PB28
SCK1
RTS1
TXD1
DTXD
DRXD
CTS1
RXD1
GND
GRX6
PWMH1
PIO
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
USB A
USB A
–
USBA_DP
USBA_DM
GND
–
–
–
–
–
USB B
USB B
–
USBB_DP
USBB_DM
GND
GRX7
PIO
–
–
–
–
–
–
USB C
USB C
–
USBC_DP
USBC_DM
GND_ETH
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
GND_ETH
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
GND
DIB
DIB
DIBP
–
DIBN
–
–
GND
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
GIGA_ETH
GIGA_ETH
GIGA_ETH
GIGA_ETH
–
JTAGSEL
WKUP
SHDN
BMS
SYSC
SYSC
SYSC
RSTJTAG
SYSC
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
RSTJTAG
–
–
–
–
nRST
nTRST
TDI
–
GIGA_ETH
GIGA_ETH
GIGA_ETH
GIGA_ETH
–
–
–
TCK
–
TMS
–
–
TDO
LED2
RTCK
GND
–
–
LED1
–
–
SAMA5D3x-EK User Guide [USER GUIDE]
100
11180B–ATARM–29-Oct-13
5.5
Main Board Schematics
This section contains the following schematics:
Block diagram
General information
SODIMM
Power supply
HSMCI
CAN & ZigBee & USART1
Audio
Smart DAA
HDMI
ETH
USB interface
Miscellaneous
LCD and ISI
On-board JTAG interface
SAMA5D3x-EK User Guide [USER GUIDE]
101
11180B–ATARM–29-Oct-13
5
4
3
2
1
Sheet 4
POWER SUPPLY
Sheet 4
Sheet 12
ANALOG
3V
Battery
3V3 INPUT
VBAT
RJ11
USBA
USBB USBC
HOST
D
C
B
A
D
C
B
A
SmartDAA
HOST & DEVICE
HOST
Sheet 8
ANALOG Reference 3V
USB A,B,C
SmartDAA
Sheet 11
ICE
ICE
ICE
S
O
D
I
M
M
SAM3U
DBGU
USER
INTERFACE
ONE WIRE
EEPROM
C
O
N
N
E
C
T
O
R
Sheet 14
HE 14
HE 14
ISI
Sheet 12
LCD
INTERFACE
Sheet 13
HDMI
INTERFACE
PIO A,...E
PIO A,...E
Sheet 9
CAN0
CAN1
10/100 FAST
EHT1
ZIGBEE
INTERFACE
10/100/1000
ETH0
AUDIO
OUT
Sheet 7
MIC1
MIC2
RJ 45
RJ 45
PIO
A
USRAT1
Sheet 6
Sheet 10
Sheet 10
PIO C
CARD
READER
CARD
READER
PIO B&D&E
Sheet 5
Sheet 3
C
B
A
Derek 30-Sep-12 X.X
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X
XX-XXX-XX
XX-XXX-XX
DATE
REV MODIF.
DES.
DATE
VER.
SAMA5D3x-MB
BLOCK Diagram
SCALE
REV.
SHEET
1
14
1/1
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
1
5
4
3
2
5
4
3
2
1
REVISION HISTORY
SAMA5D3x config
SCHEMATICS CONVENTIONS
(1) Resistance Unit: "K" is "Kohm", "R" is "Ohm
REV
DATA
NOTE
SAMA5D31
SAMA5D33
SAMA5D34
SAMA5D35
A
B
C
2011.11
2012.03
2012.10
ORIGINAL RELEASED
SECOND RELEASED
THIRD RELEASED
CAN0
CAN1
GMAC
EMAC
HSMCI2
LCDC
USART0
USART1
ISI
(2) "DNP" means the component is not populated
by default
D
C
B
A
D
C
B
A
JUMPER and SOLDERDROP
PAGE
REFERENCE
DEFAULT
FUNCTION
TEST POINT
3
JP1
JP2
JP3
JP9
JP4
JP5
1-2
VDDIOP0 or 5V selection for J1
VDDIOP0 or 5V selection for J2
VDDIOP1 or 5V selection for J3
TC1
1-2
PAGE
REFERENCE
TP1, TP2
TP3
FUNCTION
GND
1-2
4
4
4
4
4
4
4
OPEN
CLOSE
CLOSE
Default boot on embedded ROM,Close boot on external memory
Backup supply on/off
5V
TP4
3V3
4
Force power on function
TP5
VDDIOP0
VDDIOP1
VDDIOM
VDDANA
TP6
5
6
JP6
JP7
JP8
JP10
CLOSE
CLOSE
CLOSE
OPEN
MCI0 write protect select
CAN0 diff termination select
CAN1 diff termination select
Zigbee Power on/off select
TP7
TP8
DEFAULT NO POPULATE PARTS
12
14
14
JP14
JP15
JP16
1-2
ADVREF input selection
PAGE
REFERENCE
FUNCTION
OPEN
OPEN
OPEN
CLOSE
JTAG Enabled,close to disable
CDC Enabled,close to disable
Enable LCD for D31,D33,D34
Disable LCD for D35
3
5
R6,R51,R50,R120
Optional PD10,PD11,PD12,PD13 from MB
R58
Optional for MCI0 Power supply mode
Optional for MCI1 Power supply mode
11
JP17
R121
6
7
R52, R53,R55,R56,R57,R82,JP10
R132,R133
Optional Zigbee
Debug or USART1 option
TABLE OF CONTENTS
PAGE
C89,C90,R118,R119,J26
Optional Audio Line out,mic in
Optional MIC level setting
Optional audio TK
DESCRIPTION
R80,R81
R230
1
Block Diagram
2
Describe
9
L38,L39,L40,L41
Optional HDMI EMI filter
HDMI chip I2C address setting
Optional for I2S PCLK
3
SODIMM
R89
4
POWER SUPPLY
HSMCI
R266
R42
5
Optional for LCD PCLK
6
CAN & ZIGBEE &USART1
AUDIO
7
10
12
13
14
R162,R170,R171,R172,R176,R177,C122,C123,
Optional for KSZ8041NL
Optional pull up for DS28EC20P
Optional for ADC triger
8
SmartDAA
R144
R127
9
HDMI
10
11
12
13
14
ETH
USB Interface
Miscellaneous
LCD&ISI
R79, R106,R107,R109,R113,R110,R112,R111,J9 Optional JTAG
R54
SAM3U JTAG selection
R63
5V Option
Segger-SAM3U
D11,D12
R186
USB ESD protect option
Main 3V3 Optional for VCC_3V3_DEBUG
PIO MUXING
PIOA
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
USAGE
LCDD0
PIOA
USAGE
PIOB
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
USAGE
PIOB
PB16
PB17
PB18
USAGE
PIOC
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
USAGE
PIOC
USAGE
PIOD
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
USAGE
MCI0_CDA
PIOD
USAGE
PIOE
PE0
USAGE
PIOE
PE16
PE17
PE18
PE19
PE20
PE21
PE22
PE23
USAGE
PA16 ISI_D0
PA17 ISI_D1
PA18 ISI_D2
PA19 ISI_D3
PA20 ISI_D4
PA21 ISI_D5
PA22 ISI_D6
PA23 ISI_D7
PA24 LCDPWM
PA25 LCDDISP
PA26 LCDVSYNC
PA27 LCDHSYNC
PA28 LCDPCK
PA29 LCDDEN
PA30 TWD0
E1_TX0
E1_TX1
E1_RX0
E1_RX1
E1_TXEN
PC16 TK0
PC17 TF0
PC18 TD0
PC19 RK0
PC20 RF0
PC21 RD0
PD16 INT_AUDIO
PD17 MCI0_CD
PD18 MCI1_CD
PD19 ADTRG
LCDD1
LCDD2
LCDD3
LCDD4
LCDD5
LCDD6
LCDD7
LCDD8
LCDD9
MCI0_DA0
MCI0_DA1
MCI0_DA2
MCI0_DA3
MCI0_DA4
MCI0_DA5
MCI0_DA6
MCI0_DA7
MCI0_CK
PE1
PE2
PB19 MCI1_CDA
PB20 MCI1_DA0
PB21 MCI1_DA1
PB22 MCI1_DA2
PB23 MCI1_DA3
PB24 MCI1_CK
PB25
PE3
PD20 AD0_XP
PE4
E1_CRSDV
E1_RXER
E1_TXCK
E1_MDC
PD21 AD1_XM
PE5
PC22 SPI1_MISO
PC23 SPI1_MOSI
PC24 SPI1_SPCK
PC25 SPI1_NPCS0
PC26 TWD1
PD22 AD2_YP
PE6
PD23 AD3_YM
PE7
PD24 AD4_LR
PE8
PE24 ISI_RST
E1_MDIO
PD25 EN5V_HDA
PD26 EN5V_HDB
PD27 EN5V_HDC
PD28 OVCUR_USB
PD29 VBUS_SENSE
PD30 PCK0(Audio,HDMI)
PD31 PCK1(ISI_MCK)
PE9
PE25 ONE_WIRE
PE26
PA10 LCDD10
PA11 LCDD11
PA12 LCDD12
PA13 LCDD13
PA14 LCDD14
PA15 LCDD15
PB10 PWR_MCI0
PB11
PB26 CTS1
PC10 LCDD20
PC11 LCDD19
PC12 LCDD18
PC13 LCDD17
PC14 LCDD16
PC15 LCDD21
ISI_D11
ISI_D10
ISI_D9
ISI_D8
PE10
PE11
PE12
PE13
PE14
PE15
PB27 RTS1
PC27 TWCK1
PE27 PB_USER1
PE28 ZB_SLPTR
PE29 ZB_RST
PE30 ZB_IRQ1
PE31 ZB_IRQ0
LCDD22
LCDD23
PB12 PWR_MCI1
PB13
PB28 RXD1
PC28 SPI1_NPCS3
PC29 HDMI_INT
PC30
PB29 TXD1
ISI_VSYNC PB14 CANRX1
ISI_HSYNC PB15 CANTX1
PB30 DRXD
PB31 DTXD
ISI_PCK PD14 CANRX0
PD15 CANTX0
INT_ETH1
PA31 TWCK0
PC31 RESET_HDMI
C
B
Derek
Derek
30-Sep-12
30-Mar-12
X.X
X.X
XX-XXX-XX
XX-XXX-XX
A
REV
Derek
DES.
11-Nov-11
DATE
X.X
VER.
XX-XXX-XX
DATE
MODIF.
SAMA5D3x-MB
SCALE
REV.
SHEET
2
14
1/1
Describe
C
Thisagreementisour property. Reproduction and publication withoutour written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
VDDIOP0
1
5V
VDDIOP0
JP9 for BMS Config:
JP1
J1
3
When Open,BMS=1: Boot on embeded ROM
When Close,BMS=0: Boot on External memory
5V
5V
R83
4.7k
J12
1
3
5
7
9
2
VCC5V_1
VCC5V_2
4
JP9
1
SIP2
2
VCC5V_3
GND1
PE23
PE24
PE25
PE26
VDDIOM_1
PC25
PC23
PC21
GND2
PC18
PC16
PC8
VCC5V_4
VBAT
PE29
6
8
BMS
MD2X20-H
12,4
13,6
10,13,6
13,6
VBAT
PE29
1
3
2
4
6
8
PE23
PE29
PE30
PE31
ZB_RSTN
ZB_IRQ1
ZB_IRQ0
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PE24
PE25
PE26
ISI_RST
INT_ETH1
13
12,13
PE24
PE25
PE30
PE31
GND13
VDDIOM_2
PC24
PC22
PC20
PC19
PC17
PC9
PC7
GND14
PC5
PC3
PC1
PE30
PE31
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
5
7
PA0
PA1
PA16
ONE_WIRE
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
9
10
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
VDDIOM
VDDIOM
D
C
B
A
D
C
B
A
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PC25
PC23
PC21
PC24
PC22
PC20
PC19
PC17
PC9
SPI1_SPCK
PC24
13,6
13,6
7
7
7,9
10
SPI1_MOSI
RD
SPI1_MISO
RF
13,6
7
PC23
PC21
PC22
PC20
PC19
RK
TF
PC18
PC16
PC8
PC6
PC4
PC2
PC0
TD
TK
E1_MDC
E1_RXER
E1_TXEN
E1_RX0
E1_TX0
7,9
7,9
10
10
10
10
10
4
PC18
PC16
PC8
PC6
PC4
PC2
PC17
PC9
PC7
E1_MDIO
E1_TXCK
PC7
10
PC6
PC4
PC2
PC0
PC5
PC3
PC1
E1_CRSDV
E1_RX1
E1_TX1
10
10
10
PC5
PC3
PC1
PC0
PWR_EN
12
Enable_0
Enable_1
CS_BOOT_DISABLE
3V3
3V3
KEY
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
42
VDDIOP0
VDDIOP0
VCC3V3_1
VCC3V3_3
Enable_2
NC1
PE27
PC10
GND3
PC12
PC14
PC27
PC29
PC31
VDDIOP0_1
PA0
PA2
GND4
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
GND5
PA21
PA23
PA25
PA27
PA28
PA30
VDDANA_1
PD30
GND6
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
GND7
PD12
PD10
PD8
PD6
PD5
PD3
PD1
VDDIOP1_1
GND8
PB10
PB14
PB19
PB21
PB23
PB24
VCC3V3_2
VCC3V3_4
Enable_3
ADVREF
PE28
PC11
PC13
PC15
PC26
PC28
GND15
PC30
VDDIOP0_2
PA1
44
VDDIOP0
1
5V
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
12
ADVREF
PE28
PC11
PC13
PC15
PC26
PC28
JP2
J2
PE27
PC10
PE28
PC11
PC13
PC15
PC26
PC28
PB_USER1
LCDD22
LCDD20
LCDD23
LCDD19
LCDD17
LCDD21
TWD1
ZB_SLPTR
ISI_D11
12,13,9
13,9
13,6,9
13,9
13,9
13,9
13
PE27
PC10
3
PC12
PC14
PC27
PC29
PC31
LCDD18
13,9
13,9
13
13,9
9
PC12
PC14
PC27
PC29
PC31
LCDD16
TWCK1
HDMI_INT
ISI_D10
ISI_D8
SPI1_NPCS3 ISI_D9
13,6
MD2X20-H
1
3
2
4
6
8
PC30
RESET_HDMI
ISI_PCK
13
PC30
VDDIOP0
VDDIOP0
5
7
9
PA0
PA2
PA1
PA3
PA4
PA6
PA8
PA10
PC0
PC1
PC2
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
LCDD0
LCDD2
LCDD1
13,9
13,9
PA1
PA3
PA4
PA6
PA8
PA10
13,9
13,9
13,9
13,9
13,9
13,9
PA0
PA2
LCDD3
LCDD4
LCDD6
LCDD8
LCDD10
PA3
PA4
PA6
PA8
10
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
LCDD5
LCDD7
LCDD9
LCDD11
LCDD12
LCDD14
13,9
13,9
13,9
13,9
13,9
13,9
13
PA5
PA7
PA9
PA11
PA12
PA14
PA16
PA18
PA10
GND16
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
LCDD13
LCDD15
ISI_D1
ISI_D3
ISI_D4
ISI_D6
LCDPWM
LCDVSYNC
PA13
PA15
PA17
PA19
PA20
PA22
PA24
PA26
13,9
13,9
13
13
13
13
13
13,9
ISI_D0
ISI_D2
13
PA21
PA23
PA25
PA27
PA28
PA30
ISI_D5
ISI_D7
13
13
13
13,9
13,9
13,7,9
PA21
PA23
PA25
PA27
PA28
PA30
93
95
97
LCDDISP
LCDHSYNC
LCDPCK
TWD0
GND17
PA29
PA31
99
PA29
PA31
LCDDEN
TWCK0
VDDANA
PA29
PA31
13,9
13,7,9
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
ISI_VSYNC
ISI_HSYNC
VDDANA
VDDIOP0
VDDIOP0
VDDANA_2
PD31
PD29
PD27
PD25
PD23
GND18
PD21
PD19
PD17
PD15
PD13
PD11
PD9
PD30
PD31
PD29
PD27
PD25
PD23
PCK0
PCK1(ISI_MCK)
7,9
PD31
13
11
11
11
13
PD30
VBUS_SENSE
EN5V_HDC
EN5V_HDA
AD3_YM
PD29
PD27
PD25
PD23
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
OVCUR_USB
EN5V_HDB
AD4_LR
11
11
13
13
13
5
PD28
PD26
PD24
PD22
PD20
PD18
PD16
PD14
VDDIOP1
1
5V
AD2_YP
AD0_XP
PD21
PD19
PD17
PD15
AD1_XM
PD21
PD19
PD17
PD15
13
13
5
JP3
J3
MCI1_CD
INT_AUDIO
CANRX0
3
MCI0_CD
CANTX0
DNPR120
DNPR51
MCI0_CK
MCI0_D6
7
6
6
22R PD13
22R PD11
PD12 R50
PD10 R6
22R DNP
22R DNP
PD9
PD7
5
5
PD9
PD7
PD8
PD6
PD5
PD3
PD1
MD2X20-H
MCI0_D7
5
5
5
5
5
PD8
PD6
PD5
PD3
PD1
PD7
1
3
5
7
2
4
6
8
MCI0_D5
MCI0_D4
MCI0_D2
MCI0_D0
GND19
PD4
PD2
PD4
PD2
PD0
MCI0_D3
MCI0_D1
MCI0_CDA
5
5
5
PD4
PD2
PD0
PB10
PB12
PB14
PB15
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
PB31
PE23
PE24
PE25
PE26
PE29
PE30
PE31
PD10
PD11
PD12
PD13
PD14
PD15
PD19
PD31
PD0
VDDIOP1_2
9
10
VDDIOP1
VDDIOP1
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
NC2
PB12
PB15
PB20
PB22
GND20
PB25
PB27
PB29
PB31
PB30
PB26
PB28
GND9
DIBP
PB10
PB14
PB19
PB21
PB23
PB24
PB12
PWR_MCI0
CANRX1
MCI1_CDA
MCI1_DA1
MCI1_DA3
MCI1_CK
PWR_MCI1
CANTX1
MCI1_DA0
MCI1_DA2
5
13,6
5
5
5
5
PB12
PB15
5
13,6
5
5
PB10
PB14
PB19
PB21
PB23
PB24
PB15
PB20
PB22
PB20
PB22
PB25
PB27
PB29
PB31
PB30
PB26
PB28
RTS1
TXD1
DTXD
DRXD
CTS1
RXD1
PB27
PB29
PB31
6
6
14,6
14,6
6
GND23
USBA_DP
USBA_DM
GND10
USBB_DP
USBB_DM
GND11
USBC_DP
USBC_DM
GND_ETH1
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
GND_ETH2
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
GND12
LED2
11
11
USBA_DP
USBA_DM
PB30
PB26
PB28
11
11
USBB_DP
USBB_DM
6
11
11
DIBP
DIBN
8
8
USBC_DP
USBC_DM
ETH0_GND
VDDIOM
VDDIOM
DIBN
10,3
10
10
10
10
10,3
10
10
10
10
GND21
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
GND22
ETH0_TX1+
ETH0_TX1-
ETH0_RX1+
ETH0_RX1-
ETH0_GND
ETH0_TX2+
ETH0_TX2-
ETH0_RX2+
ETH0_RX2-
12
4
WAKE UP
SHDN
BMS
10,12,14
14
14
14
14
14
14
NRST
NTRST
TDI
TCK
TMS
TDO
RTCK
10
10
ETH0_LED2
ETH0_LED1
LED1
1612618-1
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
REV MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
SODIMM
SCALE
REV.
SHEET
1/1
3
14
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
3V3
D1
JP4
5V
MN1
MN2
3 1
2
ZEN056V230A16LS
BNX002-01
BAT54CLT1G
VBAT
12,3
1
3
1
3
2
5V_INPUT
J4
D
C
B
A
D
C
B
A
B
CB
1
3
2
J5
SIP2
4
5
6
+
PSG CG1
CG2
C2
33u
C1
100n
C3
100n
CG3
DC POWER JACK
5V/2A Input
C4
100n
3V3
3V3
3V3
R25
10k
VOUT
0.8V
=
x
(Rtop
C5
+ Rbottom)/Rbottom
L1
220ohm at 100MHz
PWR_EN
Q6
IRLML2402
R1
100k
PWR_EN
5V
3
1
2
10n
47k
3
2
VDDISI
13
5V
MN3
RT9018B-18GSP
C120
1u
R2
1
8
7
6
5
R3
PGOOD
EN
VIN
GND
1
2
3
4
POWER_EN
ADJ
VOUT
NC
470R
VDD
R4
100k
R5
15k
C8
1u
C6
C7
1u
C9
D2
10u
10u
Red
PWR_EN#
Q1
6
5
2
4
Si1563EDH
C57
JP5
100n
5V
TP3
SIP2
FORCE
POWER
ON
TP1
TP2
TP4
TP5
TP6
TP7
TP8
3V3
C10
15p
1
3
VDDIOP0
VDDIOP1
VDDIOM
VDDANA
R7
10k
R8
10k
C22
1u
Place C22 near MN3.pin2
3
SHDN
ADHESIVE FEET
Z6
Z7
Z17
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
Bumpon
Bumpon
Bumpon
REV MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
SCALE
REV.
S4HEET
14
Z8
Z9
1/1
POWER SUPPLY
C
Bumpon
Bumpon
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
VDD_MCI0
VDD_MCI0
VDDIOP1
RR3
10k
MCI0
JP6
R15 R16 R17 R18 R26 R36 R38 R39
68k 68k 68k 68k 68k 68k 68k 68k
1
2
C40
C12
10u
100n
R49
10k
SIP2
D
C
B
A
D
C
B
A
(MCI0_WP)
(MCI0_CD)
3
PD17
RR4
VDDIOP1
16
15
14
J7
1
2
3
4
8
8
(MCI0_DA1)
(MCI0_DA0)
3
3
PD2
PD1
7
6
5
7
6
5
4
3
2
1
9
27R
(MCI0_CK)
3
PD9
1
2
3
4
8
7
6
5
13
12
11
10
RR5
27R
R58
0R
DNP
(MCI0_CDA)
(MCI0_DA3)
(MCI0_DA2)
3
3
3
PD0
PD4
PD3
1
3
PB10
7SDMM-B0-2211
RR42
VDD_MCI0
27R
1
2
3
4
8
7
6
5
(MCI0_DA4)
(MCI0_DA5)
(MCI0_DA6)
(MCI0_DA7)
Q8
IRLML6402
R47
4.7k
3
3
3
3
PD5
PD6
PD7
PD8
RR4,RR5,RR42 near SODIMM place
SD/MMCPlus CARD INTERFACE - MCI0
VDDIOP1
VDD_MCI1
MCI1
R10 R11 R12 R13
R9
10k
R14
10k
VDDIOP1
68k 68k 68k 68k
(MCI1_CD)
3
PD18
Micro SD
J6
10
8
RR1 27R
R121
0R
DNP
SW2
1
2
3
4
8
7
6
5
(MCI1_DA1)
(MCI1_DA0)
3
3
PB21
PB20
7
6
5
4
3
2
1
11
12
13
14
1
3
PB12
(MCI1_CK)
3
PB24
1
2
3
4
8
7
6
5
VDD_MCI1
(MCI1_CDA)
(MCI1_DA3)
(MCI1_DA2)
3
3
3
PB19
PB23
PB22
Q9
IRLML6402
R48
4.7k
PJS008-2110-0
9
RR2 27R
C93
10u
C11
100n
RR1,RR2 near SODIMM place
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
REV MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
SCALE
REV.
S5HEET
14
1/1
HSMCI
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
JP7
R19
J18
1
2
CAN INTERFACE
MN5
1
2
3
4
5
6
3V3
5V
8
1
5
4
R21
R20
10k
0R
SIP2
120R
RS
7
6
CANH
CANL
CANTX0
3
3
PD15
D
CAN0
VDDIOP0
3
2
R40
10k
VDDIOP1
EN
R
VCC
GND
MJM0606GE06-H
CANRX0
D
C
B
A
D
C
B
A
PD14
SN65HVD234DR
C20
100n
C21
10u
JP8
R34
J27
1
2
MN6
1
2
3
4
5
6
3V3
5V
8
1
5
4
R32
R33
10k
0R
SIP2
120R
RS
D
7
6
CANH
CANL
CAN1
CANTX1
13,3
13,3
PB15
PB14
VDDIOP0
3
2
R35
10k
VDDIOP1
EN
VCC
R37
0R
MJM0606GE06-H
CANRX1
R
GND
SN65HVD234DR
C23
C24
10u
100n
VDDIOP1
USART1
MN4
C13
C14
3
23
1
6
C16
100n
VCC
C1+
4.7u 100n
VDDIOP1
20
2
J8
GND
V+
C1-
C2+
C2-
C3+
C3-
1
6
2
7
3
8
4
9
5
C15
C18
100n
100n
C17
C19
100n
100n
21
19
5
4
R22 R23 R24
V-
24
22
SD
EN
47k 47k
47k
7
8
9
18
17
16
RTSC1
TXDC1
R27
R28
R132
0R
0R
0R
RTS1
TXD1
DTXD
3
3
14,3
PB27
PB29
PB31
T1IN
T2IN
T3IN
T1OUT
T2OUT
T3OUT
DNP
L5
10
11
12
15
14
13
R29
0R
220ohm at 100MHz
R1OUT
R2OUT
R3OUT
R1IN
R2IN
R3IN
1
2
CTSC1
RXDC1
R30
R31
R133
0R
0R
0R
CTS1
RXD1
DRXD
3
3
14,3
PB26
PB28
PB30
DNP
ADM3312EARU
EARTH_RS232
ZIGBEE INTERFACE
DNP
DNP
DNP
DNP
DNP
DNP
0R
J10
1
3
5
7
9
2
4
R52
R56
R55
R82
0R
R53
R57
ZB_RSTN
ZB_IRQ0
13,3
10,13,3
13,3
PE31
13,3
13,3,9
13,3
PE29
PE30
PC28
PC22
0R
0R
0R
0R
ZB_IRQ1
ZB_SLPTR
PE28
PC23
PC24
6
8
10
SPI1_NPCS3
SPI1_MISO
SPI1_MOSI
SPI1_SPCK
1
13,3
13,3
2
3V3
JP10
C
B
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
BD10-H
C26
2.2n
C27 DNPDNP
C25
15p
2.2u
A
REV MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
SCALE
REV.
S6HEET
14
1/1
CAN & ZIGBEE & USART1
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
3V3
3V3
L27
220ohm at 100MHz
1
2
C140
4.7u
C141
100n
C137
10u
C142
100n
D
C
B
A
D
C
B
A
AUDIO_GND
L26
220ohm at 100MHz
AUD_1V8
AVDD1V8
AVDD1V8
C46
1
2
2.2u
AUDIO_GND
AUD_1V8
VDDIOP0
C138
10u
C139
100n
HEADPHONE
L6
R122 R123
220ohm at 100MHz
1
AUDIO_GND
MN10
C135
100n
2
5
2
1.5k
1.5k
L7
220ohm at 100MHz
1
15
13
14
3
2
R226
R234
0R
0R
TWD0
TWCK0
PA30
PA31
13,3,9
13,3,9
HPOUTR
HPOUTL
HPOUTFB
SDA
SCLK
1
2
R227
33R
PCK0
PD30
PC16
PC19
PC20
PC17
PC21
PC18
3,9
3,9
3
3
3,9
3
C144
100n
C145
100n
R118
R119
20R C89
20R C90
100n
100n
R230
R231
R228
R229
R232
R233
0RDNP TK
28
29
30
31
32
0R
RK
MCLK
4
3
18
16
17
0R
0R
0R
0R
RF
DNP
DNP
DNP
DNP
LINEOUTR
LINEOUTL
LINEOUTFB
BCLK/GPIO4
LRCLK
STEREO_3.5mm
J15
C61
470p
C62
470p
J26
MD1x5 DNP
TF
RD
ADCDAT
DACDAT
R84
20R
R85
20R
AUDIO_GND
5
4
3
2
1
TD
3,9
1
8
INT_AUDIO
PD16
3
IRQ/GPIO1
CPCA
25
27
21
20
MIC
IN1R/DMICDAT2
IN1L/DMICDAT1
VMIDC
AUDIO_GND
AUDIO_GND
AUDIO_GND
C76
C45
2.2u
MIC1
C143
4.7u
4.7u
AUDIO_GND
OUT
GND
1
2
1u
10
11
CPCB
MIC1
C136
AUDIO_GND
MICBIAS
CPVOUTP
MP6027P
R126
2K2
12
CPVOUTN
24
26
C41
2.2u
IN2R
IN2L
AUDIO_GND
L3
C44
2.2u
R86
2K2
R87
2K2
WM8904
220ohm at 100MHz
LINE IN
1
2
C28
C29
1u
1u
5
2
3
L4
220ohm at 100MHz
AUDIO_GND
AUDIO_GND
AUDIO_GND
1
1
2
R80
47k
DNP
R81
47k
DNP
4
R178
0R
STEREO_3.5mm
J13
C42
470p
C43
470p
AUDIO_GND
MN7
3V3
AUD_1V8
AUDIO_GND
AUDIO_GND
AUDIO_GND
1
2
3
5
4
VIN VOUT
GND
EN
C33
4.7u
C35
100n
BYP
C30
4.7u
C36
2.2u
SPX5205M5-L-1-8
150mA capability
C
B
Derek 30-Sep-12 X.X
Derek 30-Mar-12 X.X XX-XXX-XX
XX-XXX-XX
C37
100n
A
Derek 11-Nov-11
DES. DATE
X.X
VER.
XX-XXX-XX
DATE
REV MODIF.
SCALE
REV.
SHEET
7
SAMA5D3x-MB
1/1
AUDIO
C
14
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
D
C
B
A
D
C
B
A
L8
220ohm at 100MHz
0805
1
2
R92
6.81M
MN11
J16
1
2
3
4
5
6
D3
MMBD3004S-7-F
2
C63
12
4
1
TEST
RAC
TAC
EIC
470p
D4
RJ11
D5 MMBD3004S-7-F
15
2
5
1
2
L9
220ohm at 100MHz
C64
PWR
DAA_GND
TB3100M-13-F
470p
MJM0606GE06-H
0805
1
2
C65
100n
R93
6.81M
AVDD
11
6
C66
100n
C67
100n
0R can be replaced by
bead to improve EMI
100V
C68 47n
DAA_GND
R94
DAA_GND
TX1
2
DAA_GND
RXI
3
4
16
14
R166
0R
3
3
DIBN
DIBP
DIBN
DIBP
237K
R95
R96
R97
R98
C70
47pF
C69
10n
280R
280R
280R
280R
1%
1206
Q2
1%
1%
1206
1%
1206
1
10
9
1
R167
0R
R99
100R
Q3
1206
EIO
EIF
MMBAT42 DAA_GND
LAN0066-50
C71
150pF
C72
8
TXO
TXF
1
1
150pF
Q5
MMBAT42
7
1
Q4
MMBAT42
1
DVDD
MMBAT42
DVDD
13
GPIO
C73
100n
R100
3.01R
1%
R101
3.01R
1%
CX20548-11Z
R102
110R
DAA_GND
C74
100n
R103
9R1
1%
R94,C68 should be placed near Pin6(RXI),
and should be no vias on the RXI Net.
1206
DAA_GND
DAA_GND
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
REV
MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
SmartDAA
SCALE
REV.
SHEET
1/1
8
14
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
5V
HDMI Spec.
+4.8V < PVDD5 < +5.3V
R91
2K2
HDMI_INT
F1
13,3
3V3
PC29
1
2
D7
PVDD5
C87
1812L160/12
RB160M-60
Type A connector
3V3
R272
R273
0R
0R
TWD0
TWCK0
13,3,7
13,3,7
PA30
PA31
R105
2K2
R104
2K2
100n
DNP
R89
4.7k
3V3
R90
4.7k
D
C
B
A
D
C
B
A
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
HPD_SiI
HPD
R88
4.7k
R108
0R
LOW:72h(Defult)
DDCSDA
DDCSCL
MN9
R71
0R
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
8
7
6
5
32
31
30
29
28
27
25
24
23
20
19
18
17
16
15
14
13
11
10
9
59
58
BLUE0
TX_C+
TX_C-
D15
TVS
D17
TVS
D18
TVS
L38 DNP
TXC-
LCDDAT0
LCDDAT1
LCDDAT2
LCDDAT3
LCDDAT4
LCDDAT5
LCDDAT6
LCDDAT7
LCDDAT8
LCDDAT9
LCDDAT10
LCDDAT11
LCDDAT12
LCDDAT13
LCDDAT14
LCDDAT15
LCDDAT16
LCDDAT17
LCDDAT18
LCDDAT19
LCDDAT20
LCDDAT21
LCDDAT22
LCDDAT23
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
13,3
12,13,3
13,3,6
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
D0
D1
D2
D3
D4
D5
D6
D7
TXC+
TXC-
4
1
3
2
BLUE1
BLUE2
BLUE3
BLUE4
BLUE5
BLUE6
BLUE7
GREEN0
GREEN1
GREEN2
GREEN3
GREEN4
GREEN5
GREEN6
GREEN7
RED0
RED1
RED2
RED3
RED4
RED5
RED6
RED7
Close to SiI902x
TX_C-
TXC-
RR24
22R
R164
47k
TXC+
TX0-
62
61
TX_0+
TX_0-
TX_C+
TXC+
TX0+
TX0-
NCMS20C900
0R
RR25
22R
R72
R73
TX0+
TX1-
65
64
TX_1+
TX_1-
TX1+
TX1-
0R
TX1+
TX2-
PA8
PA9
D8
D9
68
67
RR26
22R
TX_2+
TX_2-
DNP L39 NCMS20C900
4
TX2+
TX2-
3
TX_0-
TX_0+
TX0-
PA10
PA11
PA12
PA13
PA14
PA15
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
TX2+
56
1
2
EXT_SW R265
4.3K/1%
TX0+
EXT_SWING
RR27
22R
HDM19SW-4-1R-H
R74
0R
J25
Close to Chip
1V2
PC14
RR28
22R
L18
PC13
PC12
PC11
PC10
PC15
PE27
PE28
60
66
1
2
AVCC12
1n
R75
L40
0R
AVCC_1
AVCC_2
C53
C54
C50
1n
C51
1n
C52 C48
8
7
6
4
C49
1n
EBMS321611A520
C82
10u
DNP
3
57
63
4
1
TX_1-
TX_1+
TX1-
RR29
22R
AGND_1
AGND_2
100n 100n 100n
2
TX1+
3V3
69
R42
1kDNP
R41
1k
IO_SEL
NCMS20C900
0R
L19
1
R76
R77
22
3
21
46
2
CLK_HDMI
IOVCC3V3
R260
1
22R
8
LCDPCK
13,3
PA28
CLK
IOVCC18_1
IOVCC18_2
IOVCC18_3
0R
2
3
4
7
6
5
35
34
33
51
45
44
VSYNC_HDMI
HSYNC_HDMI
DE_HDMI
RR30
22R
EBMS321611A520
LCDVSYNC
LCDHSYNC
LCDDEN
13,3
13,3
13,3
3
PA26
PA27
PA29
VSYNC
HSYNC
DE
RESETN
SCLK
C55
100n
C56
100n
C58
100n
C81
10u
DNP L41 NCMS20C900
4
3
TX_2-
TX_2+
TX2-
IO_SEL:
LOW=3.3V
,HIGH=1.8V
RST#
R264
22R
10k
0R
33R
0R
RESET_HDMI
PC31
1
2
R184
R282
R270
R284
TX2+
3V3
BCLK
LRCLK
DAT
3,7
3,7
3,7
PC16
PC17
PC18
LRCLK
R78
0R
1V2
41
40
39
37
5
I2S0
I2S1
I2S2
I2S3
CVCC12_1
CVCC12_2
CVCC12_3
CVCC12_4
CVCC12_5
CVCC12_6
12
26
42
47
53
L22
To keep TMDS pair impedance maintain at 100 ohm
pls share common choke pad with shunted resistor
,
EBMS321611A520
1
2
CVCC12
R285
0R
MN12 RClamp0514M
38
36
6
7
8
9
10
5
4
3
2
1
R266
33R
TX2+
TX2-
TX2+
TX2-
PCK0
3,7
PD30
MCLK
SPDIF
LINE4
NC4
GND
LINE2
NC3
NC2
LINE3
VCC
NC1
LINE1
C59
100n
C60
100n
C77
100n
C83
10u
C78
C79
C80
100n
T2
TSPDIF
100n
100n
DNP
43
TX1+
TX1-
TX1+
TX1-
CGND
SiI9022ACUN
MN13 RClamp0514M
5
6
7
8
9
10
TX0+
TX0-
TX0+
TX0-
LINE4
NC4
NC2
LINE3
VCC
NC1
LINE1
4
3
2
1
GND
LINE2
NC3
3V3
1V2
TXC+
TXC-
TXC+
TXC-
MN8
1
2
3
5
VIN VOUT
GND
C86
10u
4
C84
100n
C85
10u
EN
BYP
RT9013-12PB
C
B
A
REV
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
HDMI
SCALE
REV.
SHEET
1/1
9
14
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
VDDIOP0
ETH1
C122
100n
10Base-T/100Base-TX
DNP
GND_ETH1
L20
C100
220ohm at 100MHz
10u
10V R136
1
2
0R
R170
49.9R
DNP
R162
49.9R
DNP
EARTH_ETH1
EARTH_ETH1
19
GND_ETH1
22R
RR17
MN20
J24
D
C
B
A
D
C
B
A
REF_CLK/B-CAST_OFF
TD+
CT
TX+
TX-
RX+
RX-
1
2
3
6
1
2
3
4
8
7
6
5
7
1
4
2
E1_TXCK
E1_TX1
E1_TX0
3
3
3
3
PC7
PC1
PC0
PC4
TXP
25
24
23
13
14
15
16
18
20
29
28
TXD1
TXD0
TXEN
PHYAD0
R176
0R DNP
E1_TXEN
TD-
6
TXM
PHYAD1
1
2
3
4
8
7
6
5
E1_RX1
E1_RX0
E1_CRSDV
E1_RXER
3
3
3
3
E1_AVDDT
PC3
PC2
PC5
PC6
RXD1/PHYAD2
RXD0/DUPLEX
CRS_DV/CONFIG2
RXER/ISO
CONFIG1
CONFIG0
5
3
5
6
RD+
CT
RXP
22R
R177
0R DNP
RR19
RD-
4
RXM
22R
RR18
R60
R59
1k
1k
VDDIOP0
C118
100n
C129
100n
1
2
3
4
8
7
6
5
12
11
21
2
E1_MDC
E1_MDIO
INT_ETH1
C39
2.2u
3
3
PC8
PC9
PE30
MDC
MDIO
INTRP/NAND
VDD_1V2
75 75
KSZ8051RNL
R171
49.9R
DNP
R172
49.9R
75
75
NC
4
5
7
8
7
8
C124 100n
13,3,6
1
DNP
GND
PADDLE
NC1
NC2
NC3
REXT
E1_AVDDT
33
22
26
27
10
VDDIOP0 L2
GND_ETH1
1nF
220ohm at 100MHz
1
2
3
VDDA_3V3
C123
100n
DNP
VDDIOP0
R173
6.49k/1%
RR21
10k
C31
10u
C32
100n
RR20
10k
J00-0061NL
EARTH_ETH1
8
9
ETH1_XO
ETH1_XI
GND_ETH1
XO
XI
RR22
10k
VDDIOP0
VDDIOP0
17
VDDIO
VDDIOP0
At the De-Assertion of Reset:
PHY ADD[2:0]:001
CONFIG[2:0]:001,Mode:RMII
Duplex Mode:Half Duplex
Isolate Mode:Disable
30
31
2
2
1
1
C34
10u
C38
100n
D9
D8
Yellow R134
Green R135
470R
470R
LED0/NWAYEN
LED1/SPEED
32
C91
22p
C88
22p
12,14,3
NRST
RESET
Speed Mode:100Mbps
Nway Auto-Negotiation:Enable
KSZ8041NL:R162,R170,R171,R172,R176,R177,C122,C123 are needed.
KSZ8051NL:R162,R170,R171,R172,R176,R177,C122,C123 are not needed.
Y2
1
3
25MHz
J17
TRD4+
T4/A
1:1
T4/B
T3/B
T2/B
T1/B
TRP4+
7
8
7
3
3
ETH0_RX2+
ETH0_RX2-
C125 100n
C126 100n
C127 100n
C128 100n
TRCT4
TRD4-
ETH0_GND
ETH0_GND
ETH0_GND
ETH0_GND
75 OHM
75 OHM
75 OHM
75 OHM
9
TRP4-
TRP3+
8
4
TRD3+ T3/A
TRCT3
3
3
3
ETH0_TX2+
ETH0_TX2-
1
5
3
TRD3-
1:1
TRP3-
TRP2+
2
4
T2/A
TRD2+
TRCT2
3
3
ETH0_RX1+
ETH0_RX1-
6
ETH0
10Base-T/100Base-TX/1000BASE-T
TRP2-
TRP1+
6
1
5
TRD2-
1:1
TRD1+ T1/A
TRCT1
11
12
3
3
ETH0_TX1+
ETH0_TX1-
10
13
15
17
TRD1-
1:1
TRP1-
2
YELLOW LED
3
3
ETH0_LED2
ETH0_LED1
1NF,2KV
GREEN LED
GREEN LED
(SHIELD)
L23
220ohm at 100MHz
1
2
R175
0R
C
B
A
REV
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
3
ETH0_GND
J0G-0003NL
VDDIOP1
MODIF.
DES.
DATE
VER.
DATE
EARTH_ETH0
R165
R168
470R
470R
SAMA5D3x-MB
ETH
SCALE
REV.
SHEET
1/1
ETH0_GND
EARTH_ETH0
10
14
C
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5
4
3
2
1
5
4
3
2
1
USB HOST B&C INTERFACE
USBB_DP
USBB_DM
3
3
L12
MN19
MN14
OUTA
D
C
B
A
D
C
B
A
1
2
8
7
1
2
EN5V_HDB
ENA
5V
6
1
1Y
1A
PD26
PD27
3
3
C102
100n
220ohm at 100MHz
OVCUR_USB
PD28
PD28
3
IN
FLGA
C103
33u
C101
100n
+
+
4
5
3
2
2Y
2A
L13
6
5
3
4
GNG
FLGB
ENB
3V3
GND
VCC
1
2
EN5V_HDC
OUTB
SN74LVC2GU04
C105
100n
C104
33u
220ohm at 100MHz
AIC1526-1GS
C97
J19
100n
Dual USB A
A1
B1
B2
B3
B4
A
B
A2
A3
A4
USBC_DM
USBC_DP
3
3
L21
220ohm at 100MHz
1 2
3 4
1
2
EARTH_USB
EARTH_USB
3V3
USB A HOST/DEVICE INTERFACE
L14
MN15
R163
47k
1
2
8
7
1
2
13
5V_LCD
OUTA
IN
ENA
5V
C107
100n
C106 220ohm at 100MHz
+
EN_PWRLCD
13
FLGA
33u
C108
100n
L15
6
5
3
4
OVCUR_USB
EN5V_HDA
PD28
GNG
FLGB
ENB
JP17 OPEN:Enable LCD for D31,D33,D34
CLOSE:Disable LCD for D35
SIP2
1
2
OUTB
C109
100n
220ohm at 100MHz
AIC1526-1GS
3V3
C75
10u
R137
47k
MN21
6
1
1Y
1A
LCD_DETECT# 13
R138
47k
(VBUS_SENSE)
4
5
3
2
2Y
2A
PD29
3
PD25
3
3V3
GND
VCC
R139
82k
C111
15p
SN74LVC2GU04
J20
C99
100n
10
1
2
3
4
5
VBUS
DM
DP
ID
GND
USBA_DM
USBA_DP
3
3
EARTH_USB
47589-0001
(IDUSBA)
11
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
R140
47k
3V3
REV MODIF.
DES.
DATE
VER.
DATE
SAMA5D3x-MB
SCALE
REV.
SHEET
1/1
11
14
EARTH_USB
5
USB INTERFACE
C
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
4
3
2
1
5
4
3
2
1
PUSH BUTTON
ANALOG Reference 3V
3V3
3,4
VBAT
VDDANA
5V
D
C
B
A
D
C
B
A
R141
100k
R142
1.5k
PB1
PB2
PB3
R143
1.5k
JP14
NRST
2
NRST
WAKE UP
PE27
10,14,3
3
3
ADVREF
3V
WAKE UP
PB_USER1
C112
100n
C113
2.2u
D6
PB_USER1
LM4040BIM3-3.0+T
13,3,9
PB4
R46
0R
CS_BOOT_DISABLE
3
CS_BOOT
3V3
ONE WIRE EEPROM
DNP
R144
1.5k
MN16
I/O
2
3
1
ONE_WIRE
13,3
PE25
NC1
4
NC2
5
NC3
6
GND NC4
DS28EC20P
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
REV MODIF.
DES.
DATE
VER.
DATE
SHEET
12
SAMA5D3x-MB
SCALE
REV.
1/1
Miscellaneous
C
14
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
3V3
J21
LCD
1
3
2
4
5
7
9
6
8
R147
R146
0R
0R
R148
R149
0R
0R
8
7
6
5
8
7
6
ZB_IRQ0
ZB_IRQ1
3,6
13,3
PE30
PC26
PA15
PA13
PA14
PA12
PA0
PA2
PA4
PA6
PA8
10,3,6
13,3
3,9
3,9
3,9
3,9
3,9
3,9
3,9
PE31
PC27
TWCK1(SPI1_NPCS2)
TWD1(SPI1_NPCS1)
LCDDAT15
10
12
14
16
18
20
22
24
26
28
30
1
11
13
15
17
19
21
23
25
27
29
2
3
4
1
2
3
4
RR13
22R
LCDDAT13
LCDDAT14
LCDDAT12
LCDDAT0
LCDDAT2
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
D
C
B
A
D
C
B
A
1
8
7
6
RR12
22R
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT7
LCDDAT9
LCDDAT11
3,9
PA1
2
3
4
1
2
RR11
22R
3,9
3,9
3,9
3,9
3,9
PA3
PA5
PA7
PA9
PA11
5
3
4
3,9
3,9
3,9
5
RR43C
6 RR43D
5
RR43A 8
RR43B 7
PA10
ESW-115-33-L-D
5V_LCD
J22
1
3
5
2
4
6
LCD/TSC
11
5V_LCD
1
8
7
6
5
1
2
3
4
8
7
6
5
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT22
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT23
3,9
3,9
3,9
12,3,9
PC13
PC11
PC15
PE28
3,9
3,9
3,9
PC14
PC12
PC10
PE27
2
3
4
7
9
8
RR16
22R
RR23
22R
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
3,6,9
1
2
3
4
8
7
6
1
2
3
4
8
7
6
LCDDISP
LCDVSYNC
LCDDEN
LCDPWM
LCDHSYNC
LCDPCK
3
3,9
3,9
PA24
PA27
PA28
3
PA25
PA26
PA29
RR14
22R
RR15
22R
13,3,9
3,9
5
5
R150
R152
R154
0R
0R
0R
R151
R153
R155
0R
0R
0R
AD0_XP
AD2_YP
AD4_LR
AD1_XM
3
3
3
PD21
PD23
PE25
3
3
PD20
PD22
PD24
AD3_YM
ONE_WIRE
12,3
R156
R158
R160
R169
0R
0R
0R
0R
R157
R159
R161
R174
0R
0R
0R
0R
SPI1_MISO
SPI1_SPCK
EN_PWRLCD
SPI1_MOSI
SPI1_NPCS3
3,6
3,6
11
PC23
PC28
LCD_DETECT# 11
3,6
13,3,6
PC22
PC24
EN_PWRLCD
PB14
3,6
3,6
PB15
ESW-120-33-L-D
DNP
VDDIOP0
R127
0R
3
PA27
13,3,9
PD19
J11
TSW-115-07-L-D
R125
1.5k
ISI
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
2
4
4
3
VDDISI
6
8
ISI_RST
TWCK1
ZB_RSTN
TWD1
PE29
3,6
PE24
PC27
13,3
PC26
13,3
10
12
14
16
18
20
22
24
26
28
30
PCK1(ISI_MCK)
ISI_VSYNC
ISI_HSYNC
ISI_PCK
ISI_D0
PD31
PA30
PA31
PC30
PA16
PA18
PA20
PA22
PC29
PC27
3
R124
1.5k
VDDIOP0
3,7,9
3,7,9
3
3
3
3
3
3,9
13,3
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
ISI_D1
ISI_D3
ISI_D5
ISI_D7
ISI_D9
ISI_D11
ISI_D2
3
3
3
3
PA17
PA19
PA21
PA23
PC28
PC26
ISI_D4
ISI_D6
REV MODIF.
DES.
DATE
VER.
DATE
SHEET
13
ISI_D8
ISI_D10
SAMA5D3x-MB
SCALE
REV.
13,3,6
13,3
1/1
LCD & ISI
C
14
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
5
4
3
2
1
VCC_3V3_DEBUG
5V
VCC_3V3_DEBUG
MN17
J23
1
2
3
4
5
10
R65
R64
R62
0R
0R
0R
NRST_3U
TDI_3U
VCC RESET
D
C
B
A
D
C
B
A
TMS_3U R61
TCK_3U R131
0R
0R
9
8
7
6
TMS
GND1
TCK
NC2
TDI
NC1
TDO
TDI_3U
TDO_3U
TCK_3U
TMS_3U
51
TDI
54
56
55
26
27
28
29
30
31
32
33
37
38
39
40
41
10
11
12
13
14
17
18
19
20
5
TRSTIN
TRSTOUT
TDO/TRACESWO
TCK/SWCLK
TMS/SWDIO
PA0/PGMNCMD
PA1/PGMRDY
PA2/PGMNOE
PA3/PGMNVALID
PA4/PGMM0
PA5/PGMM1
PA6/PGMM2
PA7/PGMM3
PA8/PGMD0
PA9/PGMD1
PA10/PGMD2
PA11/PGMD3
PA12/PGMD4
PA13/PGMD5
PA14/PGMD6
PA15/PGMD7
PA16/PGMD8
PA17/PGMD9
PA18/PGMD10
PA19/PGMD11
PA20/PGMD12
PA21/PGMD13
PA22/PGMD12
PA23/PGMD15
PA24
TDO_3U
GND2
TRESIN
TRESOUT
TC2050-IDC
T1
ERASE_3U43
ERASE
4
2
RXDaux
T3
AD12BVREF
ADVREF
VCC_3V3_DEBUG
VCC_3V3_DEBUG
T4 TXDaux
NRST_3U
C116
57
47
NRST
NRSTB
10n
DTXD
DRXD
RX_3U
TX_3U
TDIIN
R44
R45
0R
0R
SAM3U_LQFP100
3,6
3,6
PB31
PB30
44
48
TEST
JTAGSEL
R54
R66
C117 10p
XIN_3U
0RDNP
VCC_3V3_DEBUG
6.8k/1%
78
TMSIN
VBG
VBUS_DEBUG
50
49
TCKOUT
TMSOUT
XIN32
XOUT32
C119 15p
Y4
4
TDIOUT
TDOIN
TCKIN
ENSPI
TCKOUT
2
R145
47k
2
75
74
XIN
XOUT
J14
C121 15p
12MHz XOUT_3U
21
23
24
25
96
84
85
6
105017-0001
CDC Enabled,close to disable
JTAG Enabled,close to disable
JP16
JP15
R43
100k
42
1
1
VCC_3V3_DEBUG
FWUP
PA25
PA26
PA27
PA28
PA29
PA30
PA31
VCC_3V3_DEBUG
3V3
VCC_3V3_DEBUG
10
1
2
3
4
5
2
DHSDM
DHSDP
77
80
81
76
DHSDM
DFSDM
DFSDP
DHSDP
R68
R67
39R
39R
LED1_3U
LED2_3U
RTCKIN
2
D13
D14
1
Red
R69
1k
EARTH_USB2
JP18
2
11
2
1
Green
R70
1k
86
D12
TVS
D11
TVS
VBUS_DEBUG
C95
10u
C96
100n
MN18
L24
220ohm at 100MHz
DNP DNP
1
2
3
5
VIN VOUT
GND
1
2
EARTH_USB2
4
EN
BYP
C94
10u
C47
2.2u
SPX3819
500mA capability
C98
100n
VCC_3V3_DEBUG
VDDIOP0
R79
VCC_3V3_DEBUG
R106 R107 R109
VCC_3V3_DEBUG
RR6
TRSTOUT
TRSTIN
R179
R180
R181
R182
150R
150R
150R
150R
1
2
3
4
8
7
6
5
0R NTRST
TDI
VDDIOP0
VDDIOP0
TMS
TCK
100k 100k 100k 100k
DNP DNP DNP
J9DNP
DNP
C152
100n
C153
100n
C131 C146
100n 4.7u
C154
100n
C155 C156
100n 100n
C157 C158
C159 C160
2
4
6
1
3
5
7
DNP
TDIOUT
TDIIN
R113
0R
0R
NTRST
TDI
TMS
TCK
RTCK
TDO
NRST
NTRST
TDI
TMS
TCK
RTCK
TDO
3
3
3
3
3
3
100n 100n
100n 100n
8
10
12
14
16
18
20
9
11
13
15
17
19
R110
VDDBU VDDANA
VDDIN
VDDUTMI
VDDIO
VDDIO
ADVREF
TMSOUT
TMSIN
DNP
R112
DNP
0R
NRST
10,12,3
R111
0R
DNP
TCKOUT
TCKIN
BR20-H
VDDOUT_3U
RR7
1
2
3
4
8
0R
ICE INTERFACE
RTCKIN
TDOIN
7
6
5
RTCK
TDO
NRST
C161 C147
100n 4.7u
C162
100n
C163 C164 C165 C166 C167
100n 100n 100n 100n 100n
C
B
A
Derek 30-Sep-12 X.X XX-XXX-XX
Derek 30-Mar-12 X.X XX-XXX-XX
Derek 11-Nov-11 X.X XX-XXX-XX
REV MODIF.
DES.
DATE
VER.
DATE
SHEET
14
TRESOUT
TRESIN
R183
150R
VDDOUT VDDPLL
VDDCORE
SAMA5D3x-MB
Segger-SAM3U
SCALE
REV.
1/1
C
14
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
5
4
3
2
1
6.
Optional Display Module (DM) Board
6.1
DM Board Overview
The DM board integrates a 5.0” TFT LCD module with touchscreen, as well as four QTouch pads.
Figure 6-1.
DM Board
6.1.1 Equipment List
The DM board components are:
One 5.0” TFT LCD module
LCD back light driver
3.3V regulator
QTouch device
1-wire device
6.1.2 Function Blocks
6.1.2.1
3.3V Regulator
The 5-0_WVGA_R_AEA-DM Board features its own LDO for local power regulation. It accepts DC 5V power from 500
mA high-side power switch on EK and outputs a regulated +3.3V to most other circuits on the board.
Figure 6-2.
DM Power Supply
5V_INTER
3V3_LCD
MN3
1
2
3
5
4
VIN VOUT
C10
10u
GND
C11
100n
SELCONFIG
EN
BYP
C12
10u
C15
2.2u
SPX3819
500mA capability
C13
100n
SAMA5D3x-EK User Guide [USER GUIDE]
116
11180B–ATARM–29-Oct-13
6.1.3 TFT LCD with Touch Panel
The 5-0_WVGA_R_AEA-DM features an LCD controller. The 5” 800x480 LCD provides the DM with a low-power LCD
display feature, backlight unit and a touch panel, similar to that used on commercial PDAs.
Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24-bit data signals
(8bit x RGB by default) or 16-bit data signals (5+6+5bit x RGB in option). This allows the user to develop graphical user
interfaces for a wide variety of applications.
Warning:
Never connect/disconnect the LCD display from the board while the power supply is on. This can damage
both boards.
Figure 6-3.
LCD with Touch Panel
R1
R2
R3
R4
0R
0R
0R
0R
AD2_YP
AD1_XM
AD3_YM
AD0_XP
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
VLED+
VLED-
LED2+
LED2-
LED1+
LED1-
GND6
X1
Y1
X2
Y2
GND5
GND4
DE
VSYNC
HSYNC
STB
DOTCLK
GND3
B7
B6
B5
B4
B3
B2
B1
B0
G7
G6
G5
G4
G3
G2
G1
G0
R7
R6
R5
R4
R3
R2
R1
R0
VCC2
VCC1
GND2
GND1
C4
C1
C2
C3
M1
X_RIGHT
Y_LOW
X_LEFT
Y_UP
10n
10n
10n
10n
R64
220K
DNP
DNP DNP DNP DNP
LCDDEN
LCDVSYNC
LCDHSYNC
R7
27R
LCDDISP
LCDPCK
PIN 45
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
BLUE2
BLUE1
BLUE0
GREEN7
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
GREEN1
GREEN0
RED7
RED6
RED5
RED4
RED3
RED2
RED1
RED0
5'' LCD,
800(H)¡ÁRGB¡Á480(V)
PIN
1
BLUE[0..7]
B4 R10
R8
B3 R11
R9
B2 R12
R13
B1 R14
R15
0R DNP
0R
0R DNP
0R
0R DNP
0R
0R DNP
0R
LCDDAT4
LCDDAT3
LCDDAT2
LCDDAT1
LCDDAT0
BLUE7
BLUE6
BLUE5
BLUE4
BLUE3
LCDDAT7
LCDDAT6
LCDDAT5
LCDDAT4
LCDDAT3
B0 R16
R17
0R DNP
0R
GREEN[0..7]
8
7
6
5
4
3
2
1
FL500WVR00-A0T
BLUE2
BLUE1
BLUE0
R18
R20
R21
0R
0R
0R
LCDDAT2
LCDDAT1
LCDDAT0
3V3_LCD
C6
10u
C5
100n
G5 R24
R25
G4 R26
0R DNP
0R
0R DNP
0R
0R DNP
0R
0R DNP
0R
0R DNP
0R
0R DNP
0R
LCDDAT10
LCDDAT9
LCDDAT8
LCDDAT7
LCDDAT6
LCDDAT5
RED[0..7]
GREEN7
LCDDAT15
LCDDAT14
LCDDAT13
LCDDAT12
LCDDAT11
LCDDAT10
J1
GREEN6
GREEN5
GREEN4
GREEN3
GREEN2
R27
G3 R28
R29
G2 R30
R32
G1 R34
R33
G0 R35
R36
GREEN1
GREEN0
R38
R37
0R
0R
LCDDAT9
LCDDAT8
R4 R42
R43
R3 R44
R46
R2 R47
R48
0R DNP
0R
0R DNP
0R
0R DNP
0R
0R DNP
0R
LCDDAT15
LCDDAT14
LCDDAT13
LCDDAT12
LCDDAT11
RED7
LCDDAT23
LCDDAT22
LCDDAT21
LCDDAT20
LCDDAT19
RED6
RED5
RED4
RED3
R1 R49
R50
R0 R51
R52
0R DNP
0R
RED2
RED1
RED0
R53
R54
R55
0R
0R
0R
LCDDAT18
LCDDAT17
LCDDAT16
SAMA5D3x-EK User Guide [USER GUIDE]
117
11180B–ATARM–29-Oct-13
6.1.4 Backlight
The backlight voltage is generated from a CP2122ST/CP2123ST boost converter. It is powered directly by the 5V DC
from the EK board. The backlight level is controlled by a PWM signal generated from the SAMA5D3 series processor.
Figure 6-4.
DM Back Light Control
L1
22uH
880mA
5V_INTER
5V/217mA
24.5V/40mA
D1
VLED+
C7
10u
10V
RB160M-60
60V/1A
C9
2.2u
50V
MN1
VIN
5
4
1
2
3
SW
GND
FB
LCDPWM
SHDN#
CP2122ST
300mV
VLED-
R40
10k
R41
7R5
2 x 7 LEDs Back Light
2*20mA, 24.5V
6.1.5 QTouch
The 5-0_WVGA_R_AEA-DM board carries a QTouch device driven through a TWI interface. It manages four capacitive
touch buttons directly printed on the PCB.
There is dual footprint for the QTouch device. SOIC is the default mounted one.
Figure 6-5.
DM QTouch
3V3_LCD
MN5
C16
100n
1
2
3
4
5
6
7
14
13
12
11
10
9
VDD
VSS
R65
R66
R67
R68
4.7k
4.7k
4.7k
4.7k
MODE(VSS) KEY0
SDA
RESET
CHANGE
SCL
3V3_LCD
TWD0
KEY1
KEY2
KEY3
KEY4
KEY5
3V3_LCD
C14
RESET#
CHANGE#
TWCK0
R63 R56 R57 R58
DNPDNP
8
KEY6
100n
QT1070_SOIC
MN4
10k 4.7k 4.7k 4.7k
TWCK0
TWD0
15
12
14
13
SCL
SDA
CHANGE
RESET
CHANGE#
16
17
1
2
3
4
5
KEY6
KEY5
KEY4
KEY3
KEY2
KEY1
KEY0
RESET#
6
7
10
18
19
20
QT1070
DNP
KEY4 R59
KEY3 R60
KEY2 R61
KEY1 R62
4.7k DNP
4.7k DNP
4.7k DNP
4.7k DNP
KEY
KEY
NC5
K4
K3
NC4
NC3
NC2
NC1
NC0
KEY K2
KEY
K1
6.1.6 1-Wire
The 5-0_WVGA_R_AEA-DM board also uses a 1-wire device as a “soft label” to store the information such as chip type,
manufacture name, production date, etc.
Figure 6-6.
DM 1-Wire
3V3_LCD
R45
4.7k
MN2
1
2
3
4
8
7
6
5
NC1 NC6
NC2 NC5
DATA NC4
GND NC3
ONE_WIRE
DS2433S
SAMA5D3x-EK User Guide [USER GUIDE]
118
11180B–ATARM–29-Oct-13
6.2
Schematics
a l m h e T r
2 1
1 1
D
V D
V S
E
S D ( ) O M
9
V S S
8
E D P O S T I
n
o t r
o
o n C d u c
s
K N L I X F O
SAMA5D3x-EK User Guide [USER GUIDE]
119
11180B–ATARM–29-Oct-13
7.
Troubleshooting and Recommendations
7.1
Errata
7.1.1 Impedance Mismatch on Revision C of the SAMA5D3x Main Board
There is an impedance mismatch on the revision C of the SAMA5D3x main board, impacting the clock signal of the
Ethernet PHY chip (MN20, KSZ8051RNL).This leads to a non-optimal data transmission on the ETH1 channel (J24), with
timeouts and retrials occurring from time to time.
Resolution:
Figure 7-1.
Add a line termination on signal PC7.Connect PC7 to ground through a 200 Ohm resistor in series
with a 100pF ceramic capacitor. The connection point must be done at Pin 19 of Connector J2.
Figure 7-1 shows how and where to apply the fix.
Fixing An Impedance Mismatch on the Revision C of the SAMA5D3x Main Board
SAMA5D3x-EK User Guide [USER GUIDE]
120
11180B–ATARM–29-Oct-13
8.
Revision History
Table 8-1.
Document
Revision History
Change Request
Ref.
Comments
Changed document layout, including section numbering. Changed Embest to
Embest/Flextronics throughout document.
9364
In “Introduction” and“Contents”: Added SAMA5D36, SAMA5D36-EK and
SAMA5D36-CM to lists of available references and to information for display
modules (DM). Also throughout document.
9364
In Table 1-1 “Evaluation Kit Specifications”, removed information on
temperature and relative humidity. Added information on CE and FCC
compliancy. Added SAMA5D36-EK.
9363
In Table 4-1 “CM Board Implementation”, updated boards available from
manufacturers.
9360
9363
In Table 4-2 “CPU Module Specifications”, removed ‘optional’ from details on
NOR in Memory row.
In Section 4.2.3 “Configuration Items”, removed “Dual ON/OFF switch for
NAND Flash” and replaced with “One jumper for”.
In Table 4-3 “Boot Options”, in row BMS OPEN: Added “...followed by:” after
“ROM Boot” and added SAM-BA after TWI in column Type. In column Note,
changed “Default boot on embedded ROM” to “Default boot is from embedded
ROM”. In row BMS CLOSE, changed “Boot on external NOR Flash memory”
to “Boot from external NOR Flash memory”.
Section 4.2.4.1 “Boot Configuration”: Revised throughout.
Section 4.3.3 “Reset Circuitry”: Changed information on JTAG reset.
11180B
Section 4.3.6 “Serial Peripheral Interface Controller (SPI)”: Revised
throughout.
Section 4.3.9 “Indicators”: Removed specific information on red and blue
LEDs. Added information on control by GPIO lines.
Added Section 4.4.2 “CPU Module Revision E Schematics”.
9364
9363
Table 5-1 “MB Technical Specifications”, Mass Storage Interface: Updated
information on all types of cards supported.
- Added information on RoHS and CE and FCC compliancy.
- Removed temperature range information.
Section 5.2.3 “Debug JTAG/ICE and DBGU”: Modified details of ATSAM3U4C.
Section 5.2.3.1 “Disabling J-Link-OB-ATSAM3U4C”: Revised throughout.
Section 5.2.3.2 “Hardware UART via CDC”: Revised throughout.
Section 5.2.4 “USART”: Revised throughout.
9360
Section 5.2.6 “Ethernet 10/100 (EMAC) Port”: Revised throughout.
Section 5.2.10 “CAN Bus”: Removed mention of two ports for connector J27.
Section 5.2.14 “LED Indicators”: Revised throughout.
Section 5.2.15 “Pushbutton Switches”: Changed fourth bullet.
8803
Added Section 7.1 “Errata” with Section 7.1.1 “Impedance Mismatch on
Revision C of the SAMA5D3x Main Board”.
11180A
First issue
SAMA5D3x-EK User Guide [USER GUIDE]
121
11180B–ATARM–29-Oct-13
Atmel Corporation
Atmel Asia Limited
Atmel Munich GmbH
Atmel Japan G.K.
1600 Technology Drive
Unit 01-5 & 16, 19F
Business Campus
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San Jose, CA 95110
USA
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HONG KONG
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Tokyo 141-0032
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GERMANY
Tel: (+1) (408) 441-0311
Fax: (+1) (408) 487-2600
www.atmel.com
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Tel: (+81) (3) 6417-0300
Fax: (+81) (3) 6417-0370
Tel: (+852) 2245-6100
Fax: (+852) 2722-1369
© 2013 Atmel Corporation. All rights reserved. / Rev.: 11180B–ATARM–29-Oct-13
Atmel®, logo and combinations thereof, Enabling Unlimited Possibilities®, SAM-BA® and others are registered trademarks or trademarks of Atmel Corporation or its
subsidiaries. ARM®, Thumb® and others are registered trademarks or trademarks ARM Ltd. Other terms and product names may be trademarks of others.
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