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ATTINY87-XU [MICROCHIP]

IC MCU 8BIT 8KB FLASH 20TSSOP;
ATTINY87-XU
型号： ATTINY87-XU
厂家： MICROCHIP    MICROCHIP
描述：

IC MCU 8BIT 8KB FLASH 20TSSOP

时钟 ATM 异步传输模式 微控制器 光电二极管 外围集成电路 闪存
文件： 总16页 (文件大小：355K)
中文：  中文翻译
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Features  
• High Performance, Low Power AVR® 8-bit Microcontroller  
• Advanced RISC Architecture  
– 123 Powerful Instructions – Most Single Clock Cycle Execution  
– 32 x 8 General Purpose Working Registers  
– Fully Static Operation  
• Non-volatile Program and Data Memories  
– 8K/16K Bytes of In-System Programmable Flash Program Memory  
• Endurance: 10,000 Write/Erase Cycles  
– 512 Bytes of In-System Programmable EEPROM  
• Endurance: 100,000 Write/Erase Cycles  
– 512 Bytes of Internal SRAM  
– Data retention: 20 Years at 85°C / 100 Years at 25°C  
– In-System Programmable via SPI Port  
– Low size LIN/UART Software In-System Programmable  
– Programming Lock for Software Security  
• Peripheral Features  
8-bit Atmel  
Microcontroller  
with 8K/16K  
Bytes In-System  
Programmable  
Flash and LIN  
Controller  
– LIN 2.1 and 1.3 Controller or 8-bit UART  
– One 8-bit Asynchronous Timer/Counter with Prescaler  
• Output Compare or 8-bit PWM Channel  
– One 16-bit Synchronous Timer/Counter with Prescaler  
• External Event Counter  
• 2 Output Compare Units or PWM Channels each Driving up to 4 Output Pins  
– Master/Slave SPI Serial Interface  
– Universal Serial Interface with Start Condition Detector  
– 10-bit ADC  
ATtiny87  
• 11 Single Ended Channels  
ATtiny167  
• 8 Differential ADC Channel Pairs with Programmable Gain (8x or 20x)  
– On-chip Analog Comparator with Selectable Voltage Reference  
– 100 µA 10% Current Source for LIN Node Identification  
– On-chip Temperature Sensor  
Summary  
– Programmable Watchdog Timer with Separate On-chip Oscillator  
• Special Microcontroller Features  
– Software Controlled Clock Switching for Power Control, EMC Reduction  
– debugWIRE On-chip Debug System  
– External and Internal Interrupt Sources  
– Low Power Idle, ADC Noise Reduction, and Power-down Modes  
– Power-on Reset and Programmable Brown-out Detection  
– Internal 8MHz Calibrated Oscillator  
– 4-16 MHz and 32 KHz Crystal/Ceramic Resonator Oscillators  
• I/O and Packages  
– 16 Programmable I/O Lines  
– 20-pin SOIC, 32-pad VQFN and 20-pin TSSOP  
• Operating Voltage:  
– 1.8 – 5.5V for ATtiny87/167  
• Speed Grade:  
– 0 – 4 MHz @ 1.8 – 5.5V  
– 0 – 8 MHz @ 2.7 – 5.5V  
– 0 – 16 MHz @ 4.5 – 5.5V  
• Industrial Temperature Range  
Rev. 8265DS–AVR–01/2014  
1. Description  
1.1  
Comparison Between ATtiny87 and ATtiny167  
ATtiny87 and ATtiny167 are hardware and software compatible. They differ only in memory  
sizes as shown in Table 1-1.  
Table 1-1.  
Device  
Memory Size Summary  
Flash  
EEPROM  
SRAM  
Interrupt Vector size  
ATtiny167  
ATtiny87  
16K Bytes  
8K Bytes  
512 Bytes  
512 Bytes  
512 Bytes  
512 Bytes  
2-instruction-words / vector  
2-instruction-words / vector  
1.2  
Part Description  
The ATtiny87/167 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC  
architecture. By executing powerful instructions in a single clock cycle, the ATtiny87/167  
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize  
power consumption versus processing speed.  
The AVR core combines a rich instruction set with 32 general purpose working registers. All the  
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent  
registers to be accessed in one single instruction executed in one clock cycle. The resulting  
architecture is more code efficient while achieving throughputs up to ten times faster than con-  
ventional CISC microcontrollers.  
The ATtiny87/167 provides the following features: 8K/16K byte of In-System Programmable  
Flash, 512 bytes EEPROM, 512 bytes SRAM, 16 general purpose I/O lines, 32 general purpose  
working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high speed  
Timer/Counter, Universal Serial Interface, a LIN controller, Internal and External Interrupts, a  
11-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three  
software selectable power saving modes. The Idle mode stops the CPU while allowing the  
SRAM, Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning.  
The Power-down mode saves the register contents, disabling all chip functions until the next  
Interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O mod-  
ules except ADC, to minimize switching noise during ADC conversions.  
The device is manufactured using Atmel’s high density non-volatile memory technology. The  
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI  
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code  
running on the AVR core. The Boot program can use any interface to download the application  
program in the Flash memory. By combining an 8-bit RISC CPU with In-System Self-Program-  
mable Flash on a monolithic chip, the Atmel ATtiny87/167 is a powerful microcontroller that  
provides a highly flexible and cost effective solution to many embedded control applications.  
The ATtiny87/167 AVR is supported with a full suite of program and system development tools  
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,  
and Evaluation kits.  
2
ATtiny87/167  
8265DS–AVR–01/2014  
 
ATtiny87/167  
1.3  
Block Diagram  
Figure 1-1. Block Diagram  
Watchdog  
Timer  
Power  
Supervision  
POR / BOD &  
RESET  
debugWIRE  
Watchdog  
Oscillator  
PROGRAM  
LOGIC  
Oscillator  
Circuits /  
Clock  
Flash  
SRAM  
Generation  
CPU  
EEPROM  
AVCC  
AGND  
Timer/Counter-1  
SPI & USI  
Timer/Counter-0  
Analog Comp.  
A/D Conv.  
Internal  
Voltage  
References  
2
11  
PORT B (8)  
PORT A (8)  
LIN / UART  
RESET  
XTAL[1:2]  
PB[0:7]  
PA[0:7]  
3
8265DS–AVR–01/2014  
1.4  
Pin Configuration  
Figure 1-2. Pinout ATtiny87/167 - SOIC20 & TSSOP20  
(RXLIN / RXD / ADC0 / PCINT0) PA0  
(TXLIN / TXD / ADC1 / PCINT1) PA1  
(MISO / DO / OC0A / ADC2 / PCINT2) PA2  
(INT1 / ISRC / ADC3 / PCINT3) PA3  
AVCC  
1
20  
PB0 (PCINT8 / OC1AU / DI / SDA)  
PB1 (PCINT9 / OC1BU / DO)  
PB2 (PCINT10 / OC1AV / USCK / SCL)  
PB3 (PCINT11 / OC1BV)  
2
19  
18  
3
4
20-pin 17  
16  
5
GND  
AGND  
6
15  
14  
13  
12  
11  
VCC  
top  
view  
(MOSI / SDA / DI / ICP1 / ADC4 / PCINT4) PA4  
(SCK / SCL / USCK / T1 / ADC5 / PCINT5) PA5  
(SS / AIN0 / ADC6 / PCINT6) PA6  
(AREF / XREF / AIN1 / ADC7 / PCINT7) PA7  
7
PB4 (PCINT12 / OC1AW / XTAL1 / CLKI)  
PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO)  
PB6 (PCINT14 / ADC9 / OC1AX / INT0)  
PB7 (PCINT15 / ADC10 / OC1BX / RESET / dW)  
8
9
10  
Figure 1-3. Pinout ATtiny87/167 - QFN32/MLF32  
INDEX CORNER  
24 nc  
23 nc  
22 nc  
nc  
nc  
1
2
3
4
5
6
(INT1 / ISRC / ADC3 / PCINT3) PA3  
AVCC  
32-lead  
21  
GND  
20  
VCC  
AGND  
nc  
top view  
19  
PB4 (PCINT12 / OC1AW / XTAL1 / CLKI)  
18  
nc  
nc  
7
8
PB5 (PCINT13 / ADC8 / OC1BW / XTAL2 / CLKO)  
17 nc  
Bottom pad should be  
soldered to ground  
4
ATtiny87/167  
8265DS–AVR–01/2014  
ATtiny87/167  
2. Register Summary  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Page  
(0xFF)  
(0xFE)  
(0xFD)  
(0xFC)  
(0xFB)  
(0xFA)  
(0xF9)  
(0xF8)  
(0xF7)  
(0xF6)  
(0xF5)  
(0xF4)  
(0xF3)  
(0xF2)  
(0xF1)  
(0xF0)  
(0xEF)  
(0xEE)  
(0xED)  
(0xEC)  
(0xEB)  
(0xEA)  
(0xE9)  
(0xE8)  
(0xE7)  
(0xE6)  
(0xE5)  
(0xE4)  
(0xE3)  
(0xE2)  
(0xE1)  
(0xE0)  
(0xDF)  
(0xDE)  
(0xDD)  
(0xDC)  
(0xDB)  
(0xDA)  
(0xD9)  
(0xD8)  
(0xD7)  
(0xD6)  
(0xD5)  
(0xD4)  
(0xD3)  
(0xD2)  
(0xD1)  
(0xD0)  
(0xCF)  
(0xCE)  
(0xCD)  
(0xCC)  
(0xCB)  
(0xCA)  
(0xC9)  
(0xC8)  
(0xC7)  
(0xC6)  
(0xC5)  
(0xC4)  
(0xC3)  
(0xC2)  
(0xC1)  
(0xC0)  
(0xBF)  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
LINDAT  
LDATA7  
–
LDATA6  
–
LDATA5  
–
LDATA4  
–
LDATA3  
/LAINC  
LID3  
LDATA2  
LINDX2  
LID2  
LDATA1  
LINDX1  
LID1  
LDATA0  
LINDX0  
LID0  
page 186  
page 185  
page 185  
page 184  
page 184  
page 184  
page 183  
page 182  
page 182  
page 181  
page 180  
LINSEL  
LINIDR  
LP1  
LP0  
LID5 / LDL1  
LTXDL1  
–
LID4 / LDL0  
LTXDL0  
–
LINDLR  
LTXDL3  
–
LTXDL2  
–
LRXDL3  
LDIV11  
LDIV3  
LRXDL2  
LDIV10  
LDIV2  
LRXDL1  
LDIV9  
LRXDL0  
LDIV8  
LINBRRH  
LINBRRL  
LINBTR  
LDIV7  
LDISR  
LABORT  
–
LDIV6  
–
LDIV5  
LBT5  
LDIV4  
LBT4  
LDIV1  
LDIV0  
LBT3  
LBT2  
LBT1  
LBT0  
LINERR  
LTOERR  
–
LOVERR  
–
LFERR  
–
LSERR  
LENERR  
LERR  
LPERR  
LENIDOK  
LIDOK  
LCMD2  
LCERR  
LENTXOK  
LTXOK  
LCMD1  
LBERR  
LENRXOK  
LRXOK  
LCMD0  
LINENIR  
LINSIR  
LIDST2  
LSWRES  
LIDST1  
LIN13  
LIDST0  
LCONF1  
LBUSY  
LCONF0  
LINCR  
LENA  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
5
8265DS–AVR–01/2014  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Page  
(0xBE)  
(0xBD)  
(0xBC)  
(0xBB)  
(0xBA)  
(0xB9)  
(0xB8)  
(0xB7)  
(0xB6)  
(0xB5)  
(0xB4)  
(0xB3)  
(0xB2)  
(0xB1)  
(0xB0)  
(0xAF)  
(0xAE)  
(0xAD)  
(0xAC)  
(0xAB)  
(0xAA)  
(0xA9)  
(0xA8)  
(0xA7)  
(0xA6)  
(0xA5)  
(0xA4)  
(0xA3)  
(0xA2)  
(0xA1)  
(0xA0)  
(0x9F)  
(0x9E)  
(0x9D)  
(0x9C)  
(0x9B)  
(0x9A)  
(0x99)  
(0x98)  
(0x97)  
(0x96)  
(0x95)  
(0x94)  
(0x93)  
(0x92)  
(0x91)  
(0x90)  
(0x8F)  
(0x8E)  
(0x8D)  
(0x8C)  
(0x8B)  
(0x8A)  
(0x89)  
(0x88)  
(0x87)  
(0x86)  
(0x85)  
(0x84)  
(0x83)  
(0x82)  
(0x81)  
(0x80)  
(0x7F)  
(0x7E)  
(0x7D)  
Reserved  
Reserved  
USIPP  
USIPOS  
USIB0  
page 160  
page 156  
page 155  
page 156  
page 157  
USIBR  
USIB7  
USID7  
USISIF  
USISIE  
USIB6  
USID6  
USIOIF  
USIOIE  
USIB5  
USID5  
USIB4  
USID4  
USIB3  
USID3  
USIB2  
USID2  
USIB1  
USID1  
USIDR  
USID0  
USISR  
USIPF  
USIDC  
USIWM0  
USICNT3  
USICS1  
USICNT2  
USICS0  
USICNT1  
USICLK  
USICNT0  
USITC  
USICR  
USIWM1  
Reserved  
ASSR  
EXCLK  
TCN0UB  
–
AS0  
OCR0AUB  
–
TCR0AUB  
TCR0BUB  
page 102  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
OCR1BH  
OCR1BL  
OCR1AH  
OCR1AL  
ICR1H  
OCR1B15  
OCR1B7  
OCR1A15  
OCR1A7  
ICR115  
ICR17  
OCR1B14  
OCR1B6  
OCR1A14  
OCR1A6  
ICR114  
OCR1B13  
OCR1B5  
OCR1A13  
OCR1A5  
ICR113  
ICR15  
OCR1B12  
OCR1B4  
OCR1A12  
OCR1A4  
ICR112  
ICR14  
OCR1B11  
OCR1B3  
OCR1A11  
OCR1A3  
ICR111  
ICR13  
TCNT111  
TCNT13  
OC1AX  
–
OCR1B10  
OCR1B2  
OCR1A10  
OCR1A2  
ICR110  
ICR12  
TCNT110  
TCNT12  
OC1AW  
–
OCR1B9  
OCR1B1  
OCR1A9  
OCR1A1  
ICR19  
ICR11  
TCNT19  
TCNT11  
OC1AV  
–
OCR1B8  
OCR1B0  
OCR1A8  
OCR1A0  
ICR18  
ICR10  
TCNT18  
TCNT10  
OC1AU  
–
page 136  
page 136  
page 136  
page 136  
page 137  
ICR1L  
ICR16  
page 137  
TCNT1H  
TCNT1L  
TCCR1D  
TCCR1C  
TCCR1B  
TCCR1A  
DIDR1  
TCNT115  
TCNT17  
OC1BX  
FOC1A  
ICNC1  
TCNT114  
TCNT16  
OC1BW  
FOC1B  
TCNT113  
TCNT15  
OC1BV  
–
TCNT112  
TCNT14  
OC1BU  
–
page 136  
page 136  
page 135  
page 135  
ICES1  
–
WGM13  
COM1B0  
ADC8D  
ADC4D  
WGM12  
–
CS12  
CS11  
CS10  
page 134  
COM1A1  
–
COM1A0  
ADC10D  
COM1B1  
ADC9D  
ADC5D  
–
WGM11  
–
WGM10  
–
page 131  
–
–
page 209  
DIDR0  
ADC7D/AIN1D ADC6D/AIN0D  
ADC3D  
ADC2D  
ADC1D  
ADC0D  
page 208, page 213  
Reserved  
6
ATtiny87/167  
8265DS–AVR–01/2014  
ATtiny87/167  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Page  
(0x7C)  
(0x7B)  
ADMUX  
ADCSRB  
ADCSRA  
ADCH  
REFS1  
BIN  
REFS0  
ACME  
ADLAR  
ACIR1  
ADATE  
- / ADC7  
ADC5 / -  
–
MUX4  
ACIR0  
ADIF  
MUX3  
–
MUX2  
ADTS2  
MUX1  
ADTS1  
MUX0  
ADTS0  
page 204  
page 208, page 212  
page 206  
(0x7A)  
ADEN  
- / ADC9  
ADSC  
ADIE  
- / ADC5  
ADC3 / -  
–
ADPS2  
ADPS1  
ADPS0  
(0x79)  
- / ADC8  
- / ADC6  
ADC4 / -  
–
- / ADC4  
ADC2 / -  
AREFEN  
ADC9 / ADC3  
ADC1 / -  
XREFEN  
ADC8 / ADC2  
ADC0 /  
page 207  
(0x78)  
ADCL  
ADC7 / ADC1 ADC6 / ADC0  
page 207  
(0x77)  
AMISCR  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
TIMSK1  
TIMSK0  
Reserved  
PCMSK1  
PCMSK0  
Reserved  
EICRA  
–
–
ISRCEN  
page 189, page 209  
(0x76)  
(0x75)  
(0x74)  
(0x73)  
(0x72)  
(0x71)  
(0x70)  
(0x6F)  
–
–
–
–
ICIE1  
–
–
–
–
–
OCIE1B  
–
OCIE1A  
OCIE0A  
TOIE1  
TOIE0  
page 137  
page 104  
(0x6E)  
(0x6D)  
(0x6C)  
PCINT15  
PCINT7  
PCINT14  
PCINT6  
PCINT13  
PCINT5  
PCINT12  
PCINT4  
PCINT11  
PCINT3  
PCINT10  
PCINT2  
PCINT9  
PCINT1  
PCINT8  
PCINT0  
page 65  
page 65  
(0x6B)  
(0x6A)  
(0x69)  
–
–
–
–
–
–
–
–
ISC11  
–
ISC10  
–
ISC01  
PCIE1  
ISC00  
PCIE0  
page 63  
page 64  
(0x68)  
PCICR  
(0x67)  
Reserved  
OSCCAL  
Reserved  
PRR  
(0x66)  
CAL7  
CAL6  
CAL5  
CAL4  
CAL3  
CAL2  
CAL1  
CAL0  
page 37  
(0x65)  
(0x64)  
–
–
–
COUT  
–
PRLIN  
CSUT1  
–
PRSPI  
CSUT0  
CLKRDY  
–
PRTIM1  
CSEL3  
CLKC3  
CLKPS3  
WDE  
PRTIM0  
CSEL2  
CLKC2  
CLKPS2  
WDP2  
N
PRUSI  
CSEL1  
CLKC1  
CLKPS1  
WDP1  
Z
PRADC  
CSEL0  
CLKC0  
CLKPS0  
WDP0  
C
page 47  
page 40  
page 38  
page 38  
page 57  
page 9  
(0x63)  
CLKSELR  
CLKCSR  
CLKPR  
WDTCR  
SREG  
(0x62)  
CLKCCE  
CLKPCE  
WDIF  
I
(0x61)  
–
–
(0x60)  
WDIE  
T
WDP3  
H
WDCE  
S
0x3F (0x5F)  
0x3E (0x5E)  
0x3D (0x5D)  
0x3C (0x5C)  
0x3B (0x5B)  
0x3A (0x5A)  
0x39 (0x59)  
0x38 (0x58)  
0x37 (0x57)  
0x36 (0x56)  
0x35 (0x55)  
0x34 (0x54)  
0x33 (0x53)  
0x32 (0x52)  
0x31 (0x51)  
0x30 (0x50)  
0x2F (0x4F)  
0x2E (0x4E)  
0x2D (0x4D)  
0x2C (0x4C)  
0x2B (0x4B)  
0x2A (0x4A)  
0x29 (0x49)  
0x28 (0x48)  
0x27 (0x47)  
0x26 (0x46)  
0x25 (0x45)  
0x24 (0x44)  
0x23 (0x43)  
0x22 (0x42)  
0x21 (0x41)  
0x20 (0x40)  
0x1F (0x3F)  
0x1E (0x3E)  
0x1D (0x3D)  
0x1C (0x3C)  
0x1B (0x3B)  
V
SPH  
SP15  
SP7  
SP14  
SP6  
SP13  
SP5  
SP12  
SP4  
SP11  
SP3  
SP10  
SP9  
SP8  
page 11  
page 11  
SPL  
SP2  
SP1  
SP0  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
SPMCSR  
Reserved  
MCUCR  
MCUSR  
SMCR  
–
–
–
–
–
RWWSB  
SIGRD  
CTPB  
RFLB  
PGWRT  
–
PGERS  
–
SPMEN  
page 218  
–
–
–
PUD  
–
–
–
–
BODS  
BODSE  
–
WDRF  
–
–
–
page 47, page 75  
page 52  
–
–
–
–
BORF  
SM1  
EXTRF  
SM0  
PORF  
SE  
–
page 46  
Reserved  
DWDR  
DWDR7  
ACD  
DWDR6  
ACIRS  
DWDR5  
ACO  
DWDR4  
ACI  
DWDR3  
ACIE  
DWDR2  
ACIC  
DWDR1  
ACIS1  
DWDR0  
ACIS0  
page 215  
page 212  
ACSR  
Reserved  
SPDR  
SPD7  
SPIF  
SPD6  
WCOL  
SPD5  
–
SPD4  
–
SPD3  
–
SPD2  
–
SPD1  
–
SPD0  
SPI2X  
page 146  
page 146  
page 144  
page 23  
page 23  
SPSR  
SPCR  
SPIE  
SPE  
DORD  
GPIOR25  
GPIOR15  
MSTR  
GPIOR24  
GPIOR14  
CPOL  
CPHA  
SPR1  
SPR0  
GPIOR2  
GPIOR1  
Reserved  
OCR0A  
TCNT0  
GPIOR27  
GPIOR17  
GPIOR26  
GPIOR16  
GPIOR23  
GPIOR13  
GPIOR22  
GPIOR12  
GPIOR21  
GPIOR11  
GPIOR20  
GPIOR10  
OCR0A7  
TCNT07  
FOC0A  
OCR0A6  
TCNT06  
–
OCR0A5  
OCR0A4  
OCR0A3  
OCR0A2  
TCNT02  
CS02  
–
OCR0A1  
TCNT01  
CS01  
OCR0A0  
TCNT00  
CS00  
page 102  
page 102  
page 101  
page 99  
TCNT05  
TCNT04  
TCNT03  
TCCR0B  
TCCR0A  
Reserved  
GTCCR  
EEARH(1)  
EEARL  
–
–
–
–
–
–
COM0A1  
COM0A0  
WGM01  
WGM00  
TSM  
–
–
–
–
–
PSR0  
–
PSR1  
EEAR8  
EEAR0  
EEDR0  
EERE  
page 105, page 108  
page 21  
–
–
–
EEAR5  
EEDR5  
EEPM1  
GPIOR05  
–
–
EEAR4  
EEDR4  
EEPM0  
GPIOR04  
–
–
EEAR3  
EEDR3  
EERIE  
GPIOR03  
–
–
EEAR2  
EEDR2  
EEMPE  
GPIOR02  
–
EEAR7  
EEAR6  
EEAR1  
EEDR1  
EEPE  
GPIOR01  
INT1  
page 21  
EEDR  
EEDR7  
EEDR6  
page 22  
EECR  
–
–
page 22  
GPIOR0  
EIMSK  
GPIOR07  
GPIOR06  
GPIOR00  
INT0  
page 23  
–
–
–
–
–
–
page 63  
EIFR  
–
–
–
–
INTF1  
PCIF1  
INTF0  
page 64  
PCIFR  
–
–
–
–
PCIF0  
page 65  
7
8265DS–AVR–01/2014  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Page  
0x1A (0x3A)  
0x19 (0x39)  
0x18 (0x38)  
0x17 (0x37)  
0x16 (0x36)  
0x15 (0x35)  
0x14 (0x34)  
0x13 (0x33)  
0x12 (0x32)  
0x11 (0x31)  
0x10 (0x30)  
0x0F (0x2F)  
0x0E (0x2E)  
0x0D (0x2D)  
0x0C (0x2C)  
0x0B (0x2B)  
0x0A (0x2A)  
0x09 (0x29)  
0x08 (0x28)  
0x07 (0x27)  
0x06 (0x26)  
0x05 (0x25)  
0x04 (0x24)  
0x03 (0x23)  
0x02 (0x22)  
0x01 (0x21)  
0x00 (0x20)  
Reserved  
Reserved  
Reserved  
Reserved  
TIFR1  
–
–
–
–
ICF1  
–
–
–
–
–
OCF1B  
–
OCF1A  
OCF0A  
TOV1  
TOV0  
page 138  
page 104  
TIFR0  
Reserved  
Reserved  
PORTCR  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
PORTB  
–
–
BBMB  
BBMA  
–
–
PUDB  
PUDA  
page 75  
PORTB7  
DDB7  
PORTB6  
DDB6  
PORTB5  
DDB5  
PORTB4  
DDB4  
PORTB3  
DDB3  
PORTB2  
DDB2  
PORTB1  
DDB1  
PORTB0  
DDB0  
page 85  
page 85  
page 85  
page 85  
page 85  
page 85  
DDRB  
PINB  
PINB7  
PINB6  
PINB5  
PINB4  
PINB3  
PINB2  
PINB1  
PINB0  
PORTA  
PORTA7  
DDA7  
PORTA6  
DDA6  
PORTA5  
DDA5  
PORTA4  
DDA4  
PORTA3  
DDA3  
PORTA2  
DDA2  
PORTA1  
DDA1  
PORTA0  
DDA0  
DDRA  
PINA  
PINA7  
PINA6  
PINA5  
PINA4  
PINA3  
PINA2  
PINA1  
PINA0  
Notes: 1. Address bits exceeding EEAMSB (Table 21-8 on page 227) are don’t care.  
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses  
should never be written.  
3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these  
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.  
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI  
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The  
CBI and SBI instructions work with registers 0x00 to 0x1F only.  
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O  
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATtiny87/167 is a com-  
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN  
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD  
instructions can be used.  
8
ATtiny87/167  
8265DS–AVR–01/2014  
ATtiny87/167  
3. Ordering Information  
3.1  
ATtiny87  
Speed (MHz)  
Power Supply (V)  
Ordering Code  
Package(1)  
Operational Range  
ATtiny87-MU  
32PN  
32PN  
20S2  
20S2  
20X  
ATtiny87-MUR(2)  
ATtiny87-SU  
Industrial  
(-40C to +85C)(3)  
16  
1.8 – 5.5  
ATtiny87-SUR(2)  
ATtiny87-XU  
ATtiny87-XUR(2)  
20X  
Notes: 1. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-  
ous Substances (RoHS).  
2. Tape and reel.  
3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-  
tion and minimum quantities.  
Package Type  
32PN  
20S2  
20X  
32-lead, 0.5mm pitch, 5 x 5 mm Very Thin Quad Flat No Lead Package (VQFN) Sawn  
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)  
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)  
9
8265DS–AVR–01/2014  
 
 
 
3.2  
ATtiny167  
Speed (MHz)  
Power Supply (V)  
Ordering Code  
Package(1)  
Operational Range  
ATtiny167-MU  
32PN  
32PN  
20S2  
20S2  
20X  
ATtiny167-MUR(2)  
ATtiny167-SU  
Industrial  
(-40C to +85C)(3)  
16  
1.8 – 5.5  
ATtiny167-SUR(2)  
ATtiny167-XU  
ATtiny167-XUR(2)  
20X  
Notes: 1. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-  
ous Substances (RoHS).  
2. Tape and reel.  
3. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-  
tion and minimum quantities.  
Package Type  
32PN  
20S2  
20X  
32-lead, 0.5mm pitch, 5 x 5 mm Very Thin Quad Flat No Lead Package (VQFN) Sawn  
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)  
20-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)  
10  
ATtiny87/167  
8265DS–AVR–01/2014  
 
 
 
ATtiny87/167  
4. Packaging Information  
4.1  
32PN  
11  
8265DS–AVR–01/2014  
4.2  
20S2  
12  
ATtiny87/167  
8265DS–AVR–01/2014  
ATtiny87/167  
4.3  
20X  
Dimensions in Millimeters and (Inches).  
Controlling dimension: Millimeters.  
JEDEC Standard MO-153 AC  
INDEX MARK  
PIN  
1
6.50 (0.256)  
6.25 (0.246)  
4.50 (0.177)  
4.30 (0.169)  
6.60 (.260)  
6.40 (.252)  
1.20 (0.047) MAX  
0.65 (.0256) BSC  
0.15 (0.006)  
0.05 (0.002)  
SEATING  
PLANE  
0.30 (0.012)  
0.19 (0.007)  
0.20 (0.008)  
0.09 (0.004)  
0º ~ 8º  
0.75 (0.030)  
0.45 (0.018)  
10/23/03  
TITLE  
DRAWING NO. REV.  
2325 Orchard Parkway  
San Jose, CA 95131  
20X, (Formerly 20T), 20-lead, 4.4 mm Body Width,  
Plastic Thin Shrink Small Outline Package (TSSOP)  
20X  
C
R
13  
8265DS–AVR–01/2014  
5. Errata  
5.1  
Errata ATtiny87  
The revision letter in this section refers to the revision of the ATtiny87 device.  
5.1.1  
Rev. C  
• Gain control of the crystal oscillator.  
• ‘Disable Clock Source’ command remains enabled.  
5.1.2  
Rev. A - B  
Not sampled.  
5.2  
Errata ATtiny167  
The revision letter in this section refers to the revision of the ATtiny167 device.  
5.2.1  
Rev. C  
• Gain control of the crystal oscillator.  
• ‘Disable Clock Source’ command remains enabled.  
5.2.2  
Rev. A - B  
Not sampled.  
5.3  
Errata Description  
1. Gain control of the crystal oscillator.  
The crystal oscillator (0.4 -> 16 MHz) doesn’t latch its gain control (CKSEL/CSEL[2:0] bits):  
a. The ‘Recover System Clock Source’ command doesn’t returns CSEL[2:0] bits.  
b. The gain control can be modified on the fly if CLKSELR changes.  
Problem fix / workaround.  
a. No workaround.  
b. As soon as possible, after any CLKSELR modification, re-write the appropriate crystal  
oscillator setting (CSEL[3]=1 and CSEL[2:0] / CSUT[1:0] bits) in CLKSELR.  
Code example:  
; Select crystal oscillator ( 16MHz crystal, fast rising power)  
ldi  
sts  
temp1,((0x0F<<CSEL0)|(0x02<<CSUT0))  
CLKSELR, temp1  
; Enable clock source (crystal oscillator)  
ldi  
ldi  
sts  
sts  
temp2,(1<<CLKCCE)  
temp3,(0x02<<CLKC0)  
CLKCSR,temp2  
; CSEL = "0010"  
; Enable CLKCSR register access  
; Enable crystal oscillator clock  
CLKCSR,temp3  
; Clock source switch  
ldi  
sts  
sts  
temp3,(0x04<<CLKC0)  
; CSEL = "0100"  
CLKCSR,temp2  
CLKCSR,temp3  
; Enable CLKCSR register access  
; Clock source switch  
14  
ATtiny87/167  
8265DS–AVR–01/2014  
ATtiny87/167  
; Select watchdog clock ( 128KHz, fast rising power)  
ldi  
sts  
temp3,((0x03<<CSEL0)|(0x02<<CSUT0))  
CLKSELR, temp3 ; (*)  
; (*) !!! Loose gain control of crystal oscillator !!!  
; ==> WORKAROUND ...  
sts  
; ...  
CLKSELR, temp1  
3. ‘Disable Clock Source’ command remains enabled.  
In the Dynamic Clock Switch module, the ‘Disable Clock Source’ command remains running  
after disabling the targeted clock source (the clock source is set in the CLKSELR register).  
Problem fix / workaround.  
After a ‘Disable Clock Source’ command, reset the CLKCSR register writing 0x80.  
Code example:  
; Select crystal oscillator  
ldi  
sts  
temp1,(0x0F<<CSEL0)  
CLKSELR, temp1  
; Disable clock source (crystal oscillator)  
ldi  
ldi  
sts  
sts  
temp2,(1<<CLKCCE)  
temp3,(0x01<<CLKC0)  
CLKCSR,temp2  
; CSEL = "0001"  
; Enable CLKCSR register access  
; (*) Disable crystal oscillator clock  
CLKCSR,temp3  
; (*) !!! At this moment, if any other clock source is selected by CLKSELR,  
this clock source will also stop !!!  
; ==> WORKAROUND ...  
sts CLKCSR,temp2  
;
15  
8265DS–AVR–01/2014  
X
X X X X  
X
Atmel Corporation  
1600 Technology Drive, San Jose, CA 95110 USA  
T: (+1)(408) 441.0311  
F: (+1)(408) 436.4200  
|
www.atmel.com  
© 2014 Atmel Corporation. / Rev.: 8265DS-AVR-01/2014.  
Atmel®, Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries.  
Other terms and product names may be trademarks of others.  
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