ATWINC3400-MR210CA [MICROCHIP]
SMART MODULE ATWINC3400A-MU;
| 型号： | ATWINC3400-MR210CA |
| 厂家： | 
MICROCHIP |
| 描述： | SMART MODULE ATWINC3400A-MU |
| 文件： | 总37页 (文件大小：1027K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ATWINC3400-MR210
IEEE 802.11 b/g/n Link Controller with Integrated Low
Energy Bluetooth 4.0
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Description
Atmel® ATWINC3400-MR210 is an IEEE® 802.11 b/g/n RF/Baseband/MAC link
controller and Low Energy Bluetooth® 4.0 compliant module optimized for low-power
mobile applications. The ATWINC3400-MR210 supports single stream 1x1 802.11n
mode providing up to 72Mbps PHY rate. The ATWINC3400-MR210 module features
small form factor while fully integrating Power Amplifier, LNA, Switch, Power
Management, and Chip Antenna. It also feature an on-chip microcontroller and
integrated flash memory for system software. Implemented in 65nm CMOS
technology, the ATWINC3400-MR210 offers very low power consumption while
simultaneously providing high performance and minimal bill of materials.
The ATWINC3400-MR210 utilizes highly optimized 802.11-Bluetooth coexistence
protocols. The ATWINC3400-MR210 provides multiple peripheral interfaces including
UART, SPI, and I2C. The only external clock sources needed for the ATWINC3400-
MR210 is a 32.768kHz clock for sleep operation.
Features
IEEE 802.11
IEEE 802.11 b/g/n RF/PHY/MAC SOC
IEEE 802.11 b/g/n (1x1) for up to 72Mbps PHY rate
Single spatial stream in 2.4GHz ISM band
Integrated PA and T/R switch
Integrated chip antenna
Superior sensitivity and range via advanced PHY signal processing
Advanced equalization and channel estimation
Advanced carrier and timing synchronization
Wi-Fi Direct® and Soft-AP support
Supports IEEE 802.11 WEP, WPA, WPA2 security
Supports China WAPI security
Superior MAC throughput via hardware accelerated two-level A-MSDU/A-MPDU
frame aggregation and block acknowledgement
On-chip memory management engine to reduce host load
SPI, I2C, and UART host interfaces
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Operating temperature range of -40 to +85°C fast boot options:
Integrated flash memory for system software
SPI flash boot (firmware patches and state variables)
Low-leakage on-chip memory for state variables
Fast AP re-association (150ms)
On-Chip Network Stack to offload MCU:
– Integrated network IP stack to minimize host CPU requirements
Network features: TCP, UDP, DHCP, ARP, HTTP, SSL, and DNS
Bluetooth Low Energy
Bluetooth 4.0 (BLE)
– Bluetooth Certification
QD ID Controller (see declaration D029496)
QD ID Host (see declaration D029497)
High Speed
Class 1 and 2 transmission
Adaptive Frequency Hopping
HCI (Host Control Interface) via high speed UART
Integrated PA and T/R Switch
Superior sensitivity and range
UART host and audio interfaces
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Table of Contents
1
2
3
4
5
Ordering Information................................................................................................... 5
Package Information ................................................................................................... 5
Block Diagram ............................................................................................................. 6
Pinout Information....................................................................................................... 7
Power Management................................................................................................... 10
5.1 Power Consumption............................................................................................................................10
5.1.1 Description of Device States...................................................................................................10
5.1.2 Controlling the Device States .................................................................................................10
5.2 Power-up/down Sequence ..................................................................................................................11
5.3 Digital I/O Pin Behavior During Power-up Sequences.........................................................................12
6
7
Clocking ................................................................................................................... 13
6.1 Crystal Oscillation................................................................................................................................13
6.2 Low Power Oscillator...........................................................................................................................13
CPU and Memory Subsystem................................................................................... 14
7.1 Processor............................................................................................................................................14
7.2 Memory Subsystem.............................................................................................................................14
7.3 Non-Volatile Memory...........................................................................................................................14
8
9
WLAN Subsystem...................................................................................................... 16
8.1 MAC
..............................................................................................................................................16
8.1.1 Features .................................................................................................................................16
8.1.2 Description..............................................................................................................................16
8.2 PHY
..............................................................................................................................................17
8.2.1 Features .................................................................................................................................17
8.2.2 Description..............................................................................................................................17
Electrical Characteristics.......................................................................................... 18
9.1 Absolute Maximum Ratings.................................................................................................................18
9.2 Recommended Operating Conditions .................................................................................................18
9.3 DC Characteristics ..............................................................................................................................19
9.4 802.11 b/g/n Radio Performance ........................................................................................................20
9.4.1 Receiver Performance............................................................................................................20
9.4.2 Transmitter Performance........................................................................................................21
9.5 Bluetooth Low Energy (BLE) 4.0.........................................................................................................21
9.5.1 Receiver Performance............................................................................................................21
9.5.2 Transmitter Performance........................................................................................................22
10 External Interfaces .................................................................................................... 23
10.1 I2C Slave Interface ..............................................................................................................................24
10.1.1 Description..............................................................................................................................24
10.1.2 I2C Slave Timing.....................................................................................................................24
10.2 I2C Master Interface ............................................................................................................................25
10.2.1 Description..............................................................................................................................25
10.2.2 I2C Master Timing...................................................................................................................25
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10.3 SPI Slave Interface..............................................................................................................................26
10.3.1 Description..............................................................................................................................26
10.3.2 SPI Slave Modes....................................................................................................................26
10.3.3 SPI Slave Timing....................................................................................................................27
10.4 SPI Master Interface............................................................................................................................28
10.4.1 Description..............................................................................................................................28
10.4.2 SPI Master Timing..................................................................................................................28
10.5 UART Interface ...................................................................................................................................29
10.6 GPIOs ..............................................................................................................................................29
11 Reference Design ...................................................................................................... 31
12 Package Drawing....................................................................................................... 33
13 Reflow Profile Information........................................................................................ 34
13.1 Storage Condition................................................................................................................................34
13.1.1 Moisture Barrier Bag Before Opened .....................................................................................34
13.1.2 Moisture Barrier Bag Open.....................................................................................................34
13.2 Stencil Design .....................................................................................................................................34
13.3 Baking Conditions ...............................................................................................................................34
13.4 Soldering and Reflow Condition ..........................................................................................................34
13.4.1 Reflow Oven...........................................................................................................................34
14 Revision History ........................................................................................................ 36
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2
Ordering Information
Ordering code
Package
Description
ATWINC3400-MR210CA
22 x 15mm
With chip antenna
Package Information
Table 2-1.
ATWINC3400-MR210 Package Information (1)
Parameter
Value
22.3774 x 14.7320
36
Units
Tolerance
Package Size
Pad Count
mm
Total Thickness
Pad Pitch
2.0874
mm
mm
mm
mm
1.2040
Pad Width
0.8128
Ground Paddle Size
4.4 x 4.4
Note:
1. For details, see Chapter 12 - Package Drawing on page 33.
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Block Diagram
Figure 3-1.
ATWINC3400-MR210 Block Diagram
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Pinout Information
This package has an exposed paddle that must be connected to the system board ground. The module pin
assignment is shown in Figure 4-1. The ATWINC3400-MR210 pins are described in Table 4-1.
Figure 4-1.
ATWINC3400-MR210 Pin Assignment
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Table 4-1.
ATWINC3400-MR210 Pin Description
Pin #
Pin name
GND
Pin type
Description
1
GND
Ground
2
SPI CFG
N/C
Digital Input
None
Tie to VDDIO for SPI
3
No connect
4
N/C
None
No connect
5
N/C
None
No connect
6
N/C
None
No connect
7
RESETN
BT_TXD
BT_RXD
BT_RTS
Digital Input
Active-Low Hard Reset
GPIO_16/BLE UART Transmit Data Output
GPIO_15/BLE UART Receive Data Input
GPIO_14/BLE UART RTS output/I2C Slave Data
8
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
9
10
GPIO_13/BLE UART CTS Input/I2C Slave Clock/Wi-
Fi® UART TXD Output
11
BT_CTS
Digital I/O, Programmable Pull-Up
12
13
14
15
VDDIO
GND
Power
Digital I/O Power Supply
Ground
GND
GPIO3
GPIO4
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
GPIO_3/SPI Flash Clock Output
GPIO_4/SPI Flash SSN Output
GPIO_5/Wi-Fi UART TXD Output/SPI Flash TX
Output (MOSI)
16
17
UART_TXD
UART_RXD
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
GPIO_6/Wi-Fi UART RXD Input/SPI Flash RX Input
(MISO)
18
19
VBAT
Power
Battery Supply for DC/DC Converter AND PA
PMU Enable
CHIP_EN
Analog
RTC Clock Input/GPIO_1/Wi-Fi UART RXD In-
put/Wi-Fi UART TXD Output/BT UART CTS Input
20
21
22
RTC_CLK
GND
Digital I/O, Programmable Pull-Up
GND
Ground
GPIO_8/Wi-Fi UART RXD Input/BT UART CTS In-
put
GPIO8
Digital I/O, Programmable Pull-Up
23
24
25
26
SPI_SCK
SPI_MISO
SPI_SSN
SPI_MOSI
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
SPI Clock
SPI TX Data
SPI Slave Select
SPI RX Data
GPIO_7/Wi-Fi UART TXD output/BT UART RTS
Output
27
GPIO7
Digital I/O, Programmable Pull-Up
28
29
30
31
GND
GND
Ground
GPIO17
GPIO18
GPIO19
Digital I/O, Programmable Pull-Down
Digital I/O, Programmable Pull-Down
Digital I/O, Programmable Pull-Down
GPIO_17/
GPIO_18
GPIO_19
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Pin #
Pin name
GPIO20
Pin type
Description
32
Digital I/O, Programmable Pull-Down
GPIO_20
Host Interrupt Request Output/Wi-Fi UART RXD In-
put/BT UART RTS Output
33
34
IRQN
Digital I/O, Programmable Pull-Up
Digital I/O, Programmable Pull-Up
GPIO_21/RTC Clock/Wi-Fi UART RXD Input/Wi-Fi
UART TXD Output/BT UART RTS Output
I2C_SDA_M
35
36
49
I2C_SDL_M
GND
Digital I/O, Programmable Pull-Up
SLEEP Mode Control/Wi-Fi UART TXD output
Ground
GND
PADDLE VSS
Power
Connect to System Board Ground
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5
Power Management
5.1
Power Consumption
5.1.1 Description of Device States
ATWINC3400-MR210 has multiple device states, depending on the state of the 802.11 and BLE subsystems. It is
possible for both subsystems to be active at the same time. To simplify the device power consumption breakdown,
the following basic states are defined, for which only one subsystem can be active at a time:
WiFi_ON_Transmit
WiFi_ON_Receive
BT_ON_Transmit
BT_ON_Receive
Doze
-
-
-
-
-
-
Device is actively transmitting an 802.11 signal
Device is actively receiving an 802.11 signal
Device is actively transmitting a BLE signal
Device is actively receiving a BLE signal
Device is neither transmitting nor receiving (device state is retained)
Device is powered down with CHIP_EN low and supplies connected
Power_Down
5.1.2 Controlling the Device States
Table 5-1 shows how to switch between the device states using the following:
CHIP_EN
VDDIO
-
-
Module pad #19 used to enable DC/DC Converter
I/O supply voltage from external supply
Table 5-1.
ATWINC3400-MR210 Device States
Power consumption
Device state
WiFi_ON_Transmit
CHIP_EN
VDDIO
VDDIO
Remarks
IVBATT
<350mA
<92mA
IVDDIO
On
On
On
On
On
On
<2.7mA
<2.5mA
Output power = 14 - 15dBm
WiFi_ON_Receive
BT_ON_Transmit
BT_ON_Receive
Doze
VDDIO
VDDIO
VDDIO
VDDIO
GND
<45mA
<0.65mA
<0.5µA
<2.5mA
<7µA
Power_Down
<0.1µA
When no power is supplied to the device (the DC/DC Converter output and VDDIO are both off and at ground
potential) a voltage cannot be applied to the ATWINC3400-MR210 pins because each pin contains an ESD diode
from the pin to supply. This diode will turn on when voltage higher than one diode-drop is supplied to the pin.
If a voltage must be applied to the signal pads while the chip is in a low power state, the VDDIO supply must be
on, so the Power_Down state must be used. Similarly, to prevent the pin-to-ground diode from turning on, do not
apply a voltage that is more than one diode-drop below ground to any pin.
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5.2
Power-up/down Sequence
The power-up/down sequence for ATWINC3400-MR210 is shown in Figure 5-1. The timing parameters are
provided in Table 5-2.
Figure 5-1.
ATWINC3400-MR210 Power-up/down Sequence
VBATT
tA
tB
t C
tA'
VDDIO
tB'
CHIP_EN
RESETN
XO Clock
tC'
Table 5-2.
ATWINC3400-MR210 Power-up/down Sequence Timing
Parameter Min. Max. Unit
Description
Notes
VBATT and VDDIO can rise simultaneously or can
be tied together. VDDIO must not rise before
VBATT.
VBATT rise to VDDIO
rise
tA
tB
tC
0
0
5
ms
ms
ms
VDDIO rise to CHIP_EN
rise
CHIP_EN must not rise before VDDIO. CHIP_EN
must be driven high or low, not left floating.
This delay is needed because XO clock must stabi-
lize before RESETN removal. RESETN must be
driven high or low, not left floating.
CHIP_EN rise to
RESETN rise
VBATT and VDDIO can fall simultaneously or can be
tied together. VBATT must not fall before VDDIO.
tA’
tB’
tC’
0
0
0
ms
ms
ms
VDDIO fall to VBATT fall
CHIP_EN fall to VDDIO
fall
VDDIO must not fall before CHIP_EN. CHIP_EN and
RESETN can fall simultaneously.
RESETN fall to VDDIO
fall
VDDIO must not fall before RESETN. RESETN and
CHIP_EN can fall simultaneously.
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5.3
Digital I/O Pin Behavior During Power-up Sequences
Table 5-3 represents digital I/O Pin states corresponding to device power modes.
Table 5-3.
Digital I/O Pin Behavior in Different Device States
Pull up/down
resistor (96kΩ)
Device state
VDDIO
CHIP_EN
RESETN
Output driver
Input driver
Power_Down:
core supply off
High
Low
Low
Disabled (Hi-Z)
Disabled
Disabled
Enabled
Power-On Reset:
core supply on, hard
High
High
High
High
Low
Disabled (Hi-Z)
Disabled (Hi-Z)
Disabled
Enabled
reset on
Power-On Default:
core supply on, device
out of reset but not
High
Enabled
programmed yet
On_Doze/
Programmed by
firmware for each
pin: Enabled or
On_Transmit/
On_Receive:
Opposite of
Output Driver
state
Programmed by firm-
ware for each pin:
Enabled or Disabled
High
High
High
core supply on, device
programmed by firmware
Disabled
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Clocking
6.1
Crystal Oscillation
Table 6-1.
ATWINC3400-MR210 Crystal Oscillator Parameters
Parameter
Min.
Typ.
26
Max.
Unit
MHz
Ω
Crystal Resonant Frequency
Crystal Equivalent Series Resistance
Stability - Initial Offset (1)
50
150
100
25
-100
-25
ppm
ppm
Stability - Temperature and Aging
Note:
1. Initial offset must be calibrated to maintain ±25ppm in all operating conditions. This calibration is performed
during final production testing.
The block diagram in Figure 6-1 shows the internal Crystal Oscillator circuit that is contained within the module.
Figure 6-1.
Internal Crystal Oscillator Circuit, block diagram
XO_N
XO_P
ATWILC3000
6.2
Low Power Oscillator
ATWINC3400-MR210 requires an external 32.768kHz clock to be used for sleep operation, which is provided
through Pin J20. The frequency accuracy of the external clock has to be within ±200ppm.
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CPU and Memory Subsystem
7.1
Processor
ATWINC3400-MR210 has a Cortus APS3 32-bit processor. In 802.11 mode the processor performs many of the
MAC functions, including but not limited to association, authentication, power management, security key
management, and MSDU aggregation/de-aggregation. In addition, the processor provides flexibility for various
modes of operation, such as STA and AP modes. In BLE mode the processor handles multiple tasks of the BLE
protocol stack.
7.2
7.3
Memory Subsystem
The APS3 core uses a 256KB instruction/boot ROM (160KB for 802.11 and 96KB for BLE) along with a 420KB
instruction RAM (128KB for 802.11 and 292KB for BLE), and a 128KB data RAM (64KB for 802.11 and 64KB for
BLE). ATWINC3400 also has 8Mb of flash memory, which can be used for system software. In addition, the device
uses a 160KB shared/exchange RAM (128KB for 802.11 and 32KB for BLE), accessible by the processor and
MAC, which allows the processor to perform various data management tasks on the TX and RX data packets
Non-Volatile Memory
ATWINC3400-MR210 has 768 bits of non-volatile eFuse memory that can be read by the CPU after device reset.
This non-volatile one-time-programmable memory can be used to store customer-specific parameters, such as
802.11 MAC address, BLE address, various calibration information, such as TX power, crystal frequency offset,
etc., as well as other software-specific configuration parameters. The eFuse is partitioned into six 128-bit banks.
The bit map of the first and last banks is shown in Figure 7-1. The purpose of the first 80 bits in bank 0 and the first
56 bits in bank 5 is fixed, and the remaining bits are general-purpose software dependent bits, or reserved for
future use. Since each bank and each bit can be programmed independently, this allows for several updates of the
device parameters following the initial programming, e.g. updating 802.11 MAC address or BLE address (this can
be done by invalidating the last programmed bank and programming a new bank). Refer to ATWINC3400-MR210
Programming Guide for the eFuse programming instructions.
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Figure 7-1.
1 1
ATWINC3400-MR210 eFuse Bit Map
3
4
1
1
7
1
15
48
8
8
F
16
FO
Bank 0
Bank 1
Bank 2
Bank 3
Bank 4
Bank 5
MAC ADDR
G
8
F
48
BT ADDR
128 Bits
1
1
2
3
1
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8
WLAN Subsystem
The WLAN subsystem is composed of the Media Access Controller (MAC) and the Physical Layer (PHY). Sections
8.1 and 8.2 describe the MAC and PHY in detail.
8.1
MAC
8.1.1 Features
The ATWINC3400-MR210 IEEE802.11 MAC supports the following functions:
IEEE 802.11b/g/n
IEEE 802.11e WMM® QoS EDCA/HCCA/PCF multiple access categories traffic scheduling
Advanced IEEE 802.11n features:
–
–
–
–
Transmission and reception of aggregated MPDUs (A-MPDU)
Transmission and reception of aggregated MSDUs (A-MSDU)
Immediate Block Acknowledgement
Reduced Interframe Spacing (RIFS)
Support for IEEE 802.11i and WFA security with key management
–
–
–
WEP 64/128
WPA-TKIP
128-bit WPA2 CCMP (AES)
Support for WAPI security
Advanced power management
–
–
Standard 802.11 Power Save Mode
Wi-Fi Alliance® WMM-PS (U-APSD)
RTS-CTS and CTS-self support
Supports either STA or AP mode in the infrastructure basic service set mode
Supports independent basic service set (IBSS)
8.1.2 Description
The ATWINC3400-MR210 MAC is designed to operate at low power while providing high data throughput. The
IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control
logic, and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a programmable
processor provides optimal power efficiency and real-time response while providing the flexibility to accommodate
evolving standards and future feature enhancements.
Dedicated datapath engines are used to implement data path functions with heavy computational functions. For
example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine performs
all the required encryption and decryption operations for the WEP, WPA-TKIP, WPA2 CCMP-AES, and WAPI
security requirements.
Control functions, which have real-time requirements are implemented using hardwired control logic modules.
These logic modules offer real-time response while maintaining configurability via the processor. Examples of
hardwired control logic modules are the channel access control module (implements EDCA/HCCA, Beacon TX
control, interframe spacing, etc.), protocol timer module (responsible for the Network Access Vector, back-off
timing, timing synchronization function, and slot management), MPDU handling module, aggregation/de-
aggregation module, block ACK controller (implements the protocol requirements for burst block communication),
and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher engine, and the DMA
interface to the TX/RX FIFOs).
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The MAC functions implemented solely in software on the microprocessor have the following characteristics:
Functions with high memory requirements or complex data structures. Examples are association table
management and power save queuing.
Functions with low computational load or without critical real-time requirements. Examples are authentication
and association.
Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS
scheduling.
8.2
PHY
8.2.1 Features
The ATWINC3400-MR210 IEEE 802.11 PHY supports the following functions:
Single antenna 1x1 stream in 20MHz channels
Supports IEEE 802.11b DSSS-CCK modulation: 1, 2, 5.5, 11Mbps
Supports IEEE 802.11g OFDM modulation: 6, 9, 12,18, 24, 36, 48, 54Mbps
Supports IEEE 802.11n HT modulations MCS0-7, 20MHz, 800 and 400ns guard interval: 6.5, 7.2, 13.0, 14.4,
19.5, 21.7, 26.0, 28.9, 39.0, 43.3, 52.0, 57.8, 58.5, 65.0, 72.2Mbps
IEEE 802.11n mixed mode operation
Per packet TX power control
Advanced channel estimation/equalization, automatic gain control, CCA, carrier/symbol recovery, and frame
detection
8.2.2 Description
The ATWINC3400-MR210 WLAN PHY is designed to achieve reliable and power-efficient physical layer
communication specified by IEEE 802.11 b/g/n in single stream mode with 20MHz bandwidth. Advanced
algorithms have been employed to achieve maximum throughput in a real world communication environment with
impairments and interference. The PHY implements all the required functions such as FFT, filtering, FEC (Viterbi
decoder), frequency and timing acquisition and tracking, channel estimation and equalization, carrier sensing and
clear channel assessment, as well as the automatic gain control.
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9
Electrical Characteristics
9.1
Absolute Maximum Ratings
Table 9-1.
Symbol
ATWINC3400-MR210 Absolute Maximum Ratings
Characteristics
Digital I/O Supply Voltage
Min.
-0.3
-0.3
-0.3
-0.3
Max.
5.0
Unit
VDDIO
VBATT
Battery Supply Voltage
Digital Input Voltage
Analog Input Voltage
5.0
(1)
VIN
VDDIO
1.5
V
(2)
VAIN
-1000, -2000
(see notes below)
+1000, +2000
(see notes below)
(3)
VESDHBM
TA
ESD Human Body Model
Storage Temperature
Junction Temperature
RF input power max.
-65
150
125
23
ºC
dBm
Notes: 1. VIN corresponds to all the digital pins.
2. VAIN corresponds to the following analog pins:
3. For VESDHBM, each pin is classified as Class 1, or Class 2, or both:
The Class 1 pins include all the pins (both analog and digital)
The Class 2 pins include all digital pins only
VESDHBM is ±1kV for Class1 pins. VESDHBM is ±2kV for Class2 pins
9.2
Recommended Operating Conditions
Table 9-2.
ATWINC3400-MR210 Recommended Operating Conditions
Characteristic
Symbol
Min.
2.7
Typ.
3.3
Max.
3.6
Unit
V
I/O Supply Voltage (1)
VDDIO
VBATT
Battery Supply Voltage (2)
Operating Temperature
3.0
3.6
4.2
-40
85
ºC
Notes: 1. Battery supply voltage is applied to following pins: VBAT.
2. ATWINC3400-MR210 is functional across this range of voltages; however, optimal RF performance is guaranteed
for VBATT in the range 3.0V < VBATT < 4.2V.
3. Refer to Chapter 11 for the details of the power connections.
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9.3
DC Characteristics
Table 9-3 provides the DC characteristics for the ATWINC3400-MR210 digital pads.
Table 9-3.
ATWINC3400-MR210 DC Electrical Characteristics
Characteristic
Min.
-0.30
Typ.
Max.
0.60
Unit
Input Low Voltage VIL
Input High Voltage VIH
Output Low Voltage VOL
Output High Voltage VOH
Output Loading
VDDIO-0.60
VDDIO+0.30
0.45
V
VDDIO-0.50
20
6
pF
Digital Input Load
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9.4
802.11 b/g/n Radio Performance
9.4.1 Receiver Performance
Radio performance under typical conditions: VBATT = 3.3V; VDDIO = 3.3V; temp.: 25°C
Table 9-4.
ATWINC3400-MR210 802.11 Conducted Receiver Performance Nominal Conditions, 50Ω load/source
Parameter
Description
Min.
Typ.
Max.
Unit
Frequency
2,412
2,484
MHz
1Mbps DSS
2Mbps DSS
5.5Mbps DSS
11Mbps DSS
6Mbps OFDM
9Mbps OFDM
-98
-95
-93
-89
-90
-89
-87
-86
-83
-79
-76
-74
-89
-86
-84
-82
-79
-75
-73
-71
5
Sensitivity 802.11b
12Mbps OFDM
18Mbps OFDM
24Mbps OFDM
36Mbps OFDM
48Mbps OFDM
54Mbps OFDM
MCS 0
Sensitivity 802.11g
dBm
MCS 1
MCS 2
MCS 3
Sensitivity 802.11n
(BW=20MHz)
MCS 4
MCS 5
MCS 6
MCS 7
1-11Mbps DSS
-10
-10
-10
Maximum Receive Signal Level 6-54Mbps OFDM
MCS 0 - 7
-3
-3
1Mbps DSS (30MHz offset)
50
11Mbps DSS (25MHz offset)
43
6Mbps OFDM (25MHz offset)
54Mbps OFDM (25MHz offset)
MCS 0 – 20MHz BW (25MHz offset)
MCS 7 – 20MHz BW (25MHz offset)
40
Adjacent Channel Rejection
dB
25
40
20
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9.4.2 Transmitter Performance
Radio performance under typical conditions: VBATT = 3.3V; VDDIO = 3.3V; temp.: 25°C
Table 9-5.
ATWINC3400-MR210 802.11 Transmitter Performance Nominal Conditions, 50Ω load/source
Parameter
Description
Min.
Typ.
Max.
Unit
Frequency
2.412
2,484
MHz
Output Power
802.11b DSSS 1-11Mbps
802.11g OFDM 6-54Mbps
802.11n HT20 MCS 0-7
20 (1)
17.0 (1)
16 (1)
±1.5 (2)
30.0
dBm
TX Power Accuracy
Carrier Suppression
dB
dBc
Harmonic Output Power 2nd
3rd
-33
dBm/MHz
-38
Notes: 1. Measured at 802.11 spec. compliant EVM/Spectral Mask.
2. Without calibration.
9.5
Bluetooth Low Energy (BLE) 4.0
The Bluetooth subsystem implements all the mission critical real-time functions. It encodes/decodes HCI packets,
constructs baseband data packages, manages, and monitors the connection status, slot usage, data flow, routing,
segmentation, and buffer control. The Bluetooth subsystem supports Bluetooth Low Energy (BLE) modes of
operation.
Supports BLE profiles allowing connection to advanced low energy application such as:
Smart Energy
Consumer Wellness
Home Automation
Security
Proximity Detection
Entertainment
Sports and Fitness
Automotive
9.5.1 Receiver Performance
Radio performance under typical conditions: VBATT = 3.3V; VDDIO = 3.3V; Temp.: 25°C
Table 9-6.
ATWINC3400-MR210 BLE Receiver Performance Nominal Conditions, 50Ω load/source
Parameter
Description
Min.
Typ.
Max.
Unit
MHz
dBm
dBm
Frequency
2,402
2,480
Sensitivity Ideal TX
BLE (GFSK)
BLE (GFSK)
-96
0
Maximum Receive Signal Level
-10
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9.5.2 Transmitter Performance
Radio performance under typical conditions: VBATT = 3.3V; VDDIO = 3.3V; temp.: 25°C
Table 9-7.
ATWINC3400-MR210 BLE Transmitter Performance Nominal Conditions, 50Ω load/source
Parameter
Description
Min.
Typ.
Max.
2,480
4
Unit
MHz
dBm
Frequency
2,402
Output Power
Note:
BLE (GFSK)
1. The maximum output power may require board filtering to meet spurious emission limits.
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10 External Interfaces
ATWINC3400-MR210 external interfaces include: SPI Slave, and UART for 802.11 control and data transfer;
UART for BLE control, and data transfer; SPI Master for external Flash; I2C Master for external EEPROM, and
General Purpose Input/Output (GPIO) pins. With the exception of the SPI Slave interface, which are selected using
the dedicated SDIO_SPI_CFG pin, the other interfaces can be assigned to various pins by programming the
corresponding pin MUXing control register for each pin to a specific value between 0 and 6.The default values of
these registers are 0, which is GPIO mode. Each digital I/O pin also has a programmable pull-up or pull-down. The
summary of the available interfaces and their corresponding pin MUX settings is shown in Table 10-1. For specific
programming instructions, refer to ATWINC3400-MR210 Programming Guide.
Table 10-1. ATWINC3400-MR210 Pin-MUX Matrix of External Interfaces
Pin name
GPIO16
Pin # Pull
Mux0
GPIO_16
GPIO_15
GPIO_14
GPIO_13
GPIO_3
GPIO_4
GPIO_5
GPIO_6
GPIO_1
GPIO_8
MUX1
MUX2
MUX3
MUX4
MUX5
MUX6
8
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
Up
O_BT_UART1_TXD
I_BT_UART1_RXD
O_BT_UART1_RTS
I_BT_UART1_CTS
O_SPI_SCK_FLASH
O_SPI_SSN_FLASH
O_SPI_TXD_FLASH
I_SPI_RXD_FLASH
I_RTC_CLK
GPIO15
9
GPIO14
10
11
23
25
24
25
20
22
23
24
25
IO_I2C_SDA
IO_I2C_SCL
I_WAKEUP
GPIO13
O_WIFI_UART_TXD
I_WAKEUP
GPIO3
O_BT_UART2_TXD
I_BT_UART2_RXD
I_WAKEUP
GPIO4
GPIO5
O_WIFI_UART_TXD
I_WIFI_UART_RXD
I_WIFI_UART_RXD
I_WIFI_UART_RXD
GPIO6
I_WAKEUP
RTC_CLK
SD_CLK
O_WIFI_UART_TXD
I_BT_UART1_CTS
I_BT_UART1_CTS
I_SD_CLK
SD_CMD/SPI_SCK
SD_DAT0/SPI_TXD
SD_DAT1/SPI_SSN
IO_SD_CMD
IO_SPI_SCK
O_SPI_TXD
IO_SPI_SSN
I_SPI_RXD
IO_SD_DAT0
IO_SD_DAT1
SD_DAT2/SPI_RXD 26
IO_SD_DAT2
SD_DAT3
GPIO17
27
GPIO_7
IO_SD_DAT3
O_WIFI_UART_TXD
O_BT_UART1_RTS
29 Down GPIO_17
30 Down GPIO_18
31 Down GPIO_19
32 Down GPIO_20
IO_BT_PCM_CLK
IO_BT_PCM_SYNC
I_BT_PCM_D_IN
O_BT_PCM_D_OUT
O_IRQN
I_WAKEUP
I_WAKEUP
I_WAKEUP
I_WAKEUP
GPIO18
GPIO19
GPIO20
IRQN
33
34
35
Up
Up
Up
GPIO_2
GPIO_21
GPIO_0
I_WIFI_UART_RXD
I_WIFI_UART_RXD
O_WIFI_UART_TXD
O_BT_UART1_RTS
O_WIFI_UART_TXD
GPIO21
I_RTC_CLK
O_BT_UART1_RTS
IO_I2C_MASTER_SCL
IO_I2C_MASTER_SDA
HOST_WAKEUP
I_WAKEUP
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10.1 I2C Slave Interface
10.1.1 Description
The I2C Slave interface, used primarily for control by the host processor, is a two-wire serial interface consisting of
a serial data line (SDA) on Pin 16 (GPIO14) and a serial clock line (SCL) on Pin 17 (GPIO13). I2C Slave responds
to the seven bit address value 0x60. The ATWINC3400-MR210 I2C supports I2C bus Version 2.1 - 2000 and can
operate in standard mode (with data rates up to 100Kb/s) and fast mode (with data rates up to 400Kb/s).
The I2C Slave is a synchronous serial interface. The SDA line is a bidirectional signal and changes only while the
SCL line is low, except for STOP, START, and RESTART conditions. The output drivers are open-drain to perform
wire-AND functions on the bus. The maximum number of devices on the bus is limited by only the maximum
capacitance specification of 400pF. Data is transmitted in byte packages.
For specific information, refer to the Philips Specification entitled “The I2C -Bus Specification, Version 2.1”.
10.1.2 I2C Slave Timing
The I2C Slave timing is provided in Figure 10-1 and Table 10-2.
Figure 10-1. ATWINC3400-MR210 I2C Slave Timing Diagram
tPR
tHDDAT
tSUDAT
tBUF
tSUSTO
SDA
SCL
tHL
tLH
tLH
tHL
tWL
tHDSTA
tWH
tPR
tPR
fSCL
tSUSTA
Table 10-2.
ATWINC3400-MR210 I2C Slave Timing Parameters
Parameter
Symbol
fSCL
Min.
Max.
Unit
Remarks
SCL Clock Frequency
SCL Low Pulse Width
SCL High Pulse Width
SCL, SDA Fall Time
0
400
kHz
µs
tWL
tWH
tHL
1.3
0.6
µs
300
300
ns
This is dictated by external
components
SCL, SDA Rise Time
tLH
ns
START Setup Time
START Hold Time
SDA Setup Time
tSUSTA
tHDSTA
tSUDAT
0.6
0.6
µs
µs
ns
100
0
40
ns
µs
Slave and Master Default
Master Programming Option
SDA Hold Time
tHDDAT
STOP Setup Time
tSUSTO
tBUF
0.6
1.3
0
µs
µs
ns
Bus Free Time Between STOP and START
Glitch Pulse Reject
tPR
50
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10.2 I2C Master Interface
10.2.1 Description
ATWINC3400-MR210 provides an I2C bus master, which is intended primarily for accessing an external EEPROM
memory through a software-defined protocol. The I2C Master is a two-wire serial interface consisting of a serial
data line (SDA) and a serial clock line (SCL). SDA can be configured on pin 42 (HOST_WAKEUP) and SCL can be
configured on pin 41 (GPIO21).
10.2.2 I2C Master Timing
The I2C Master interface supports three speeds:
Standard mode (100kb/s)
Fast mode (400kb/s)
High-speed mode (3.4Mb/s)
The timing diagram of the I2C Master interface is the same as that of the I2C Slave interface (see Figure 10-1). The
timing parameters of I2C Master are shown in Table 10-3.
Table 10-3.
ATWINC3400-MR210 I2C Master Timing Parameters
Standard
mode
High-speed
mode
Fast mode
Parameter
Symbol
Unit
Min.
Max.
Min.
Max.
400
Min.
0
Max.
SCL Clock Frequency
SCL Low Pulse Width
SCL High Pulse Width
SCL Fall Time
fSCL
0
4.7
4
100
0
3400
kHz
µs
tWL
1.3
0.6
0.16
0.06
10
tWH
tHLSCL
tHLSDA
tLHSCL
tLHSDA
tSUSTA
tHDSTA
tSUDAT
tHDDAT
tSUSTO
tBUF
300
300
300
300
300
300
40
80
40
80
SDA Fall Time
10
ns
SCL Rise Time
1000
1000
10
SDA Rise Time
10
START Setup Time
START Hold Time
SDA Setup Time
4.7
4
0.6
0.6
100
40
0.16
0.16
10
µs
ns
250
5
SDA Hold Time
0
70
STOP Setup time
4
0.6
1.3
0
0.16
µs
ns
Bus Free Time Between STOP and START
Glitch Pulse Reject
4.7
tPR
50
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10.3 SPI Slave Interface
10.3.1 Description
ATWINC3400-MR210 provides a Serial Peripheral Interface (SPI) that operates as a SPI slave. The SPI Slave
interface can be used for control and for serial I/O of 802.11 data. The SPI Slave pins are mapped as shown in
Table 10-4. The RXD pin is the same as Master Output, Slave Input (MOSI), and the TXD pin is the same as
Master Input, Slave Output (MISO). The SPI Slave is a full-duplex slave-synchronous serial interface that is
available immediately following reset when Pin 12 (DVDDIO) is tied to VDDIO.
Table 10-4.
ATWINC3400-MR210 SPI Slave Interface Pin Mapping
SPI function
Pin #
J2
CFG: Must be tied to VDDIO
SSN: Active Low Slave Select
SCK: Serial Clock
J25
J23
J26
RXD: Serial Data Receive (MOSI)
TXD: Serial Data Transmit (MISO)
J24
When the SPI is not selected, i.e., when SSN is high, the SPI interface will not interfere with data transfers
between the serial-master and other serial-slave devices. When the serial slave is not selected, its transmitted data
output is buffered, resulting in a high impedance drive onto the serial master receive line.
The SPI Slave interface responds to a protocol that allows an external host to read or write any register in the chip
as well as initiate DMA transfers. For the details of the SPI protocol and more specific instructions, refer to
ATWINC3400-MR210 Programming Guide.
10.3.2 SPI Slave Modes
The SPI Slave interface supports four standard modes as determined by the Clock Polarity (CPOL) and Clock
Phase (CPHA) settings. These modes are illustrated in Table 10-5 and Figure 10-2. The red lines in Figure 10-2
correspond to Clock Phase = 0 and the blue lines correspond to Clock Phase = 1.
Table 10-5.
ATWINC3400-MR210 SPI Slave Modes
Mode
CPOL
CPHA
0
1
2
3
0
0
1
1
0
1
0
1
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10.3.3 SPI Slave Timing
The SPI Slave timing is provided in Figure 10-2, Figure 10-3, and Table 10-6.
Figure 10-2. ATWINC3400-MR210 SPI Slave Clock Polarity and Clock Phase Timing
CPOL = 0
SCK
CPOL = 1
SSN
CPHA = 0
CPHA = 1
z
1
2
3
4
5
6
7
8
z
RXD/TXD
(MOSI/MISO)
z
1
2
3
4
5
6
7
8
z
Figure 10-3. ATWINC3400-MR210 SPI Slave Timing Diagram
Table 10-6.
ATWINC3400-MR210 SPI Slave Timing Parameters
Parameter
Symbol
fSCK
Min.
Max.
Unit
MHz
ns
Clock Input Frequency
Clock Low Pulse Width
48
tWL
5
5
Clock High Pulse Width
Clock Rise Time
tWH
ns
tLH
5
5
ns
Clock Fall Time
tHL
ns
Input Setup Time
Input Hold Time
tISU
5
5
0
5
5
ns
tIHD
ns
Output Delay
tODLY
tSUSSN
tHDSSN
20
ns
Slave Select Setup Time
Slave Select Hold Time
ns
ns
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10.4 SPI Master Interface
10.4.1 Description
ATWINC3400-MR210 provides a SPI Master interface for accessing external flash memory. The SPI Master pins
are mapped as shown in Table 10-7. The TXD pin is the same as Master Output, Slave Input (MOSI), and the RXD
pin is the same as Master Input, Slave Output (MISO). The SPI Master interface supports all four standard modes
of clock polarity and clock phase shown in Table 10-5. External SPI flash memory is accessed by a processor
programming commands to the SPI Master interface, which in turn initiates a SPI master access to the flash. For
more specific instructions, refer to ATWINC3400-MR210 Programming Guide.
Table 10-7.
ATWINC3400-MR210 SPI Master Interface Pin Mapping
Pin name
Pin #
J23
SPI function
SPI_SCK
SPI_SSN
SPI_RXD
SPI_TXD
Serial Clock Output
J25
Active Low Slave Select Output
J26
RXD: Serial Data Transmit Output (MISO)
TXD: Serial Data Receive Input (MOSI)
J24
10.4.2 SPI Master Timing
The SPI Master timing is provided in Figure 10-4 and Table 10-8.
Figure 10-4. ATWINC3400-MR210 SPI Master Timing Diagram
fSCK
tLH
tWH
tWL
SCK
tHL
SSN,
TXD
tODLY
tISU
tIHD
RXD
Table 10-8.
ATWINC3400-MR210 SPI Master Timing Parameters
Parameter
Symbol
fSCK
tWL
tWH
tLH
Min.
Max.
Unit
Clock Output Frequency
Clock Low Pulse Width
Clock High Pulse Width
Clock Rise Time
48
MHz
5
5
5
5
Clock Fall Time
tHL
ns
Input Setup Time
Input Hold Time
tISU
tIHD
tODLY
5
5
0
Output Delay
5
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10.5 UART Interface
ATWINC3400-MR210 provides Universal Asynchronous Receiver/Transmitter (UART) interfaces for serial
communication. The BLE subsystem has two UART interfaces: a 4-pin interface for control, data transfer, and
audio (BT UART1), and a 2-pin interface for debugging (BT UART2). The 802.11 subsystem has one 2-pin UART
interface (Wi-Fi UART), which can be used for control, data transfer, or debugging. The UART interfaces are
compatible with the RS-232 standard, where ATWINC3400-MR210 operates as Data Terminal Equipment (DTE).
The 2-pin UART has the receive and transmit pins (RXD and TXD), and the 4-pin UART has two additional pins
used for flow control/handshaking; Request To Send (RTS) and Clear To Send (CTS).
The RTS and CTS are used for hardware flow control; they MUST be connected to the
host MCU UART and enabled for the UART interface to be functional.
The pins associated with each UART interfaces can be enabled on several alternative pins by programming their
corresponding pin MUX control registers (see Table 10-1 for available options).
The UART features programmable baud rate generation with fractional clock division, which allows transmission
and reception at a wide variety of standard and non-standard baud rates. The BLE UART input clock is selectable
between 104MHz, 52MHz, 26MHz, and 13MHz. The clock divider value is programmable as 13 integer bits and
three fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the
maximum supported baud rate of 10MHz/8.0 = 13MBd. The 802.11 UART input clock is selectable between
10MHz, 5MHz, 2.5MHz, and 1.25MHz. The clock divider value is programmable as 13 integer bits and three
fractional bits (with 8.0 being the smallest recommended value for normal operation). This results in the maximum
supported baud rate of 10MHz/8.0 = 1.25MBd.
The UART can be configured for seven or eight bit operation, with or without parity, with four different parity types
(odd, even, mark, or space), and with one or two stop bits. It also has RX and TX FIFOs, which ensure reliable
high speed reception and low software overhead transmission. FIFO size is 4 x 8 for both RX and TX direction.
The UART also has status registers showing the number of received characters available in the FIFO and various
error conditions, as well the ability to generate interrupts based on these status bits.
An example of UART receiving or transmitting a single packet is shown in Figure 10-5. This example shows 7-bit
data (0x45), odd parity, and two stop bits.
For more specific instructions, refer to ATWINC3400-MR210 Programming Guide.
Figure 10-5. Example of UART RX or TX Packet
10.6 GPIOs
18 General Purpose Input/Output (GPIO) pins, labeled GPIO 0-8 and 13-21, are available to allow for application
specific functions. Each GPIO pin can be programmed as an input (the value of the pin can be read by the host or
internal processor) or as an output (the output values can be programmed by the host or internal processor),
where the default mode after power-up is input.
ATWINC3400-MR210 provides programmable pull-up resistors on various pins (see Table 4-1). The purpose of
these resistors is to keep any unused input pins from floating, which can cause excess current to flow through the
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input buffer from the VDDIO supply. Any unused pin on the device should leave these pull-up resistors enabled so
the pin will not float. The default state at power up is for the pull-up resistor to be enabled. However, any pin which
is used should have the pull-up resistor disabled. The reason for this is that if any pins are driven to a low level
while the device is in the low power sleep state, current will flow from the VDDIO supply through the pull-up
resistors, increasing the current consumption of the module. Since the value of the pull-up resistor is approximately
100kΩ, the current through any pull-up resistor that is being driven low will be VDDIO/100K. For VDDIO = 3.3V,
the current would be approximately 33µA. Pins which are used and have had the programmable pull-up resistor
disabled should always be actively driven to either a high or low level and not be allowed to float. Refer to
ATWINC3400-MR210 Programming Guide for information on enabling/disabling the programmable pull-up
resistors.
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11 Reference Design
The ATWINC3400-MR210 application schematics are shown in Figure 11-1.
Module design information such as module schematics can be obtained under an NDA from Atmel.
Figure 11-1. ATWINC3400-MR210 Application Schematic for SPI Operation
R T C
2 J 0
A D _ P D G N
4 J 9
5 D G N
3 J 6
2 J 8
2 J 2
1 J 3
J 1
4 D G N
3 D G N
2 D G N
1 D G N
O I D V D
V B A T
1 J 2
1 J 8
O E
V D
3
4
N C 4
D
V S S
J 6
J 5
J 4
J 3
2
N C 3
N C 2
N C 1
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Table 11-1.
SPI Application Bill of Material
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12 Package Drawing
The ATWINC3400-MR210 module with Chip Antenna package details are shown in Figure 12-1.
Figure 12-1. ATWINC3400-MR210 Module with CA Connector Package Dimensions
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13 Reflow Profile Information
This chapter provides guidelines for reflow processes in getting the Atmel module soldered to the customer’s
design.
13.1 Storage Condition
13.1.1 Moisture Barrier Bag Before Opened
A moisture barrier bag must be stored in a temperature of less than 30°C with humidity under 85% RH.
The calculated shelf life for the dry-packed product shall be 12 months from the date the bag is sealed.
13.1.2 Moisture Barrier Bag Open
Humidity indicator cards must be blue, <30%.
13.2 Stencil Design
The recommended stencil is laser-cut, stainless-steel type with thickness of 100µm to 130µm and approximately a
1:1 ratio of stencil opening to pad dimension. To improve paste release, a positive taper with bottom opening 25µm
larger than the top can be utilized. Local manufacturing experience may find other combinations of stencil
thickness and aperture size to get good results.
13.3 Baking Conditions
This module is rated at MSL level 3. After sealed bag is opened, no baking is required within 168 hours so long as
the devices are held at <= 30oC/60% RH or stored at <10% RH.
The module will require baking before mounting if:
The sealed bag has been open for >168 hours
Humidity Indicator Card reads >10%
SIPs need to be baked for 8 hours at 125oC
13.4 Soldering and Reflow Condition
13.4.1 Reflow Oven
It is strongly recommended that a reflow oven equipped with more heating zones and Nitrogen atmosphere be
used for lead-free assembly. Nitrogen atmosphere has shown to improve the wet-ability and reduce temperature
gradient across the board. It can also enhance the appearance of the solder joints by reducing the effects of
oxidation.
The following bullet items should also be observed in the reflow process:
Some recommended pastes include NC-SMQ® 230 flux and Indalloy® 241 solder paste made up of 95.5
Sn/3.8 Ag/0.7 Cu or SENJU N705-GRN3360-K2-V Type 3, no clean paste
Allowable reflow soldering times: 2 times based on the following reflow soldering profile (see Figure 13-1).
Temperature profile: Reflow soldering shall be done according to the following temperature profile (see
Figure 13-1).
Peak temp: 250°C.
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Figure 13-1. Solder Reflow Profile
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14 Revision History
Doc Rev.
42535B
42535A
Date
Comments
1. Removed references to uFL as it is not yet supported.
2. Revised Ground Paddle size in Table 2-1.
3. Revised Block Diagram Figure 3-1.
4. Updated Pin Assignments Figure 4-1.
5. Revised Pin Description table Table 4-1.
6. Globally replaced Bluetooth with BLE.
7. Revised values in Table 5-1.
8. Simplified table Table 9-2 and added note 3.
9. Corrected VDDIO typo in Table 9-3.
03/2016
10. Revised values in Table 10-8.
11. Added notation about the using Flow Control pins in section 10.5.
12. Removed SDIO and PCM as they are not supported.
13. Revised Table 9-3 layout to be clearer.
14. Clarified the schematics for easier reading in section 11.
15. Revised Module drawings for easier reading in Figure 12-1.
16. Revised Reflow Profile content in section 13.
10/2015
Initial document release.
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Atmel Corporation
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