ATXMEGA128A4U-ANR_技术文档

8/16-bit Atmel XMEGA Microcontroller

ATxmega128A4U / ATxmega64A4U /

ATxmega32A4U / ATxmega16A4U

Features

z

High-performance, low-power Atmel^®AVR^®XMEGA^®8/16-bit Microcontroller

Nonvolatile program and data memories

z

16K - 128KB of in-system self-programmable flash

4K - 8KB boot section

1K - 2KB EEPROM

2K - 8KB internal SRAM

z

Peripheral Features

z

Four-channel DMA controller

Eight-channel event system

Five 16-bit timer/counters

z

Three timer/counters with 4 output compare or input capture channels

Two timer/counters with 2 output compare or input capture channels

High-resolution extensions on all timer/counters

Advanced waveform extension (AWeX) on one timer/counter

z

One USB device interface

z

USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant

32 Endpoints with full configuration flexibility

z

Five USARTs with IrDA support for one USART

Two Two-wire interfaces with dual address match (I²C and SMBus compatible)

Two serial peripheral interfaces (SPIs)

AES and DES crypto engine

CRC-16 (CRC-CCITT) and CRC-32 (IEEE^®802.3) generator

16-bit real time counter (RTC) with separate oscillator

One twelve-channel, 12-bit, 2msps Analog to Digital Converter

One two-channel, 12-bit, 1msps Digital to Analog Converter

Two Analog Comparators with window compare function, and current sources

External interrupts on all general purpose I/O pins

Programmable watchdog timer with separate on-chip ultra low power oscillator

QTouch^®library support

z

Capacitive touch buttons, sliders and wheels

z

Special microcontroller features

z

Power-on reset and programmable brown-out detection

Internal and external clock options with PLL and prescaler

Programmable multilevel interrupt controller

Five sleep modes

Programming and debug interfaces

z

PDI (program and debug interface)

I/O and packages

z

34 Programmable I/O pins

44 - lead TQFP

44 - pad VQFN/QFN

49 - ball VFBGA

z

Operating voltage

1.6 – 3.6V

Operating frequency

z

0 – 12MHz from 1.6V

0 – 32MHz from 2.7V

z

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1.

Ordering Information

Ordering code

Flash (bytes)

128K + 8K

64K + 4K

32K + 4K

16K + 4K

128K + 8K

64K + 4K

32K + 4K

16K + 4K

128K + 8K

64K + 4K

32K + 4K

16K + 4K

EEPROM (bytes)

SRAM (bytes)

Speed (MHz)

Power supply

Package ^(1)(2)(3)

Temp.

ATxmega128A4U-AU

2K

1K

2K

1K

2K

1K

8K

4K

2K

8K

4K

2K

8K

4K

2K

ATxmega128A4U-AUR⁽⁴⁾

ATxmega64A4U-AU

ATxmega64A4U-AUR⁽⁴⁾

ATxmega32A4U-AU

44A

ATxmega32A4U-AUR⁽⁴⁾

ATxmega16A4U-AU

ATxmega16A4U-AUR⁽⁴⁾

ATxmega128A4U-MH

ATxmega128A4U-MHR⁽⁴⁾

ATxmega64A4U-MH

ATxmega64A4U-MHR⁽⁴⁾

ATxmega32A4U-MH

ATxmega32A4U-MHR⁽⁴⁾

ATxmega16A4U-MH

ATxmega16A4U-MHR⁽⁴⁾

ATxmega128A4U-CU

ATxmega128A4U-CUR⁽⁴⁾

ATxmega64A4U-CU

PW

32

1.6 - 3.6V

-40°C - 85°C

44M1

ATxmega64A4U-CUR⁽⁴⁾

ATxmega32A4U-CU

49C2

ATxmega32A4U-CUR⁽⁴⁾

ATxmega16A4U-CU

ATxmega16A4U-CUR⁽⁴⁾

XMEGA A4U [DATASHEET]

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Ordering code

Flash (bytes)

128K + 8K

64K + 4K

32K + 4K

16K + 4K

128K + 8K

64K + 4K

32K + 4K

16K + 4K

EEPROM (bytes)

SRAM (bytes)

Speed (MHz)

Power supply

Package ^(1)(2)(3)

Temp.

ATxmega128A4U-AN

ATxmega128A4U-ANR⁽⁴⁾

ATxmega64A4U-AN

ATxmega64A4U-ANR⁽⁴⁾

ATxmega32A4U-AN

ATxmega32A4U-ANR⁽⁴⁾

ATxmega16A4U-AN

ATxmega16A4U-ANR⁽⁴⁾

ATxmega128A4U-M7

ATxmega128A4U-M7R⁽⁴⁾

ATxmega64A4U-M7

ATxmega64A4U-M7R⁽⁴⁾

ATxmega32A4U-M7

ATxmega32A4U-M7R⁽⁴⁾

ATxmega16A4U-M7

ATxmega16A4U-M7R⁽⁴⁾

2K

1K

2K

1K

8K

4K

2K

8K

4K

2K

44A

32

1.6 - 3.6V

0°C - 105°C

PW

44M1

Notes:

1.

2.

3.

4.

This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.

Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.

For packaging information, see “Instruction Set Summary” on page 63.

Tape and Reel

Package Type

44A

44-Lead, 10 x 10mm body size, 1.0mm body thickness, 0.8mm lead pitch, thin profile plastic quad flat package (TQFP)

44-Pad, 7x7x1mm body, lead pitch 0.50mm, 5.20mm exposed pad, thermally enhanced plastic very thin quad no lead package (VQFN)

49-Ball (7 x 7 Array), 0.65mm Pitch, 5.0 x 5.0 x 1.0mm, very thin, fine-pitch ball grid array package (VFBGA)

44M1

PW

49C2

Typical Applications

Industrial control

Climate control

RF and ZigBee^®

USB connectivity

Sensor control

Optical

Low power battery applications

Power tools

Factory automation

Building control

Board control

HVAC

Utility metering

White goods

Medical applications

XMEGA A4U [DATASHEET]

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2.

Pinout/Block Diagram

Figure 2-1. Block Diagram and QFN/TQFP pinout

Power

Programming, debug, test

Ground

Digital function

Analog function / Oscillators

External clock / Crystal pins

General Purpose I /O

Port R

XOSC

TOSC

PA5

1

2

33

32

31

30

29

28

27

26

25

24

23

PE3

PE2

VCC

GND

PE1

PE0

PD7

PD6

PD5

PD4

PD3

DATA BUS

OSC/CLK

Control

Internal

oscillators

Power

PA6

PA7

PB0

PB1

PB2

PB3

GND

VCC

PC0

PC1

Watchdog

Supervision

AREF

ADC

Sleep

Controller

Real Time

Counter

Watchdog

Timer

Reset

Controller

3

AC0:1

4

Event System

Controller

Crypto /

CRC

Prog/Debug

Interface

OCD

5

Interrupt

Controller

BUS

matrix

AREF

DAC

6

Internal

references

DMA

Controller

CPU

7

FLASH

EEPROM

SRAM

8

DATA BUS

9

EVENT ROUTING NETWORK

10

11

Port C

Port D

Port E

Note:

1. For full details on pinout and pin functions refer to “Pinout and Pin Functions” on page 55.

XMEGA A4U [DATASHEET]

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Figure 2-2. BGA pinout

Top view

Bottom view

1

2

3

4

5

6

7

6

5

4

3

2

1

A

B

C

D

E

F

A

B

C

D

E

F

G

Table 2-1. BGA pinout

1

2

3

4

5

6

7

A

B

PA3

AVCC

PA1

GND

PA0

PR1

PR0

PDI_DATA

PE2

PE3

RESET/

PA4

GND

VCC

PDI_CLK

GND

C

D

E

F

PA5

PB1

GND

VCC

PC1

PA2

PB2

GND

PC0

PC2

PA6

PB3

PC3

PC4

PC5

PA7

PB0

GND

PC6

PC7

PE1

PD7

PD5

PD1

VCC

GND

PE0

PD6

PD3

PD2

GND

PD4

PD0

G

GND

XMEGA A4U [DATASHEET]

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3.

Overview

The Atmel AVR XMEGA is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers

based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the AVR XMEGA

devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the

system designer to optimize power consumption versus processing speed.

The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly

connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,

executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times

faster than conventional single-accumulator or CISC based microcontrollers.

The AVR XMEGA A4U devices provide the following features: in-system programmable flash with read-while-write

capabilities; internal EEPROM and SRAM; four-channel DMA controller, eight-channel event system and

programmable multilevel interrupt controller, 34 general purpose I/O lines, 16-bit real-time counter (RTC); five flexible,

16-bit timer/counters with compare and PWM channels; five USARTs; two two-wire serial interfaces (TWIs); one full

speed USB 2.0 interface; two serial peripheral interfaces (SPIs); AES and DES cryptographic engine; one twelve-

channel, 12-bit ADC with programmable gain; one 2-channel 12-bit DAC; two analog comparators (ACs) with window

mode; programmable watchdog timer with separate internal oscillator; accurate internal oscillators with PLL and

prescaler; and programmable brown-out detection.

The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available.

The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the

SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down

mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,

USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to

run, allowing the application to maintain a timer base while the rest of the device is sleeping. In standby mode, the

external crystal oscillator keeps running while the rest of the device is sleeping. This allows very fast startup from the

external crystal, combined with low power consumption. In extended standby mode, both the main oscillator and the

asynchronous timer continue to run. To further reduce power consumption, the peripheral clock to each individual

peripheral can optionally be stopped in active mode and idle sleep mode.

Atmel offers a free QTouch library for embedding capacitive touch buttons, sliders and wheels functionality into AVR

microcontrollers.

The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory

can be reprogrammed in-system through the PDI. A boot loader running in the device can use any interface to

download the application program to the flash memory. The boot loader software in the boot flash section will continue

to run while the application flash section is updated, providing true read-while-write operation. By combining an 8/16-

bit RISC CPU with in-system, self-programmable flash, the AVR XMEGA is a powerful microcontroller family that

provides a highly flexible and cost effective solution for many embedded applications.

All Atmel AVR XMEGA devices are supported with a full suite of program and system development tools, including C

compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.

XMEGA A4U [DATASHEET]

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3.1

Block Diagram

Figure 3-1. XMEGA A4U Block Diagram

PR[0..1]

XTAL1/

TOSC1

Digital function

Analog function

Programming, debug, test

Oscillator/Crystal/Clock

General Purpose I/O

XTAL2/

TOSC2

Oscillator

Circuits/

Clock

Real Time

Counter

Watchdog

Oscillator

PORT R (2)

Generation

DATA BUS

SRAM

Watchdog

Timer

PA[0..7]

PORT A (8)

Event System

Controller

Oscillator

Control

VCC

GND

Power

Supervision

POR/BOD &

RESET

ACA

DMA

Controller

Sleep

Controller

ADCA

RESET/

AREFA

Int. Refs.

Tempref

AREFB

Prog/Debug

Controller

PDI_CLK

BUS Matrix

PDI

PDI_DATA

AES

DES

CRC

OCD

Interrupt

Controller

CPU

PB[0..7]

PORT B (8)

DACB

NVM Controller

Flash

EEPROM

IRCOM

DATA BUS

EVENT ROUTING NETWORK

PORT C (8)

PORT D (8)

PORT E (4)

TOSC1 (optional)

TOSC2

(optional)

PC[0..7]

PD[0..7]

PE[0..3]

XMEGA A4U [DATASHEET]

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4.

Resources

A comprehensive set of development tools, application notes and datasheets are available for download on

http://www.atmel.com/avr.

4.1

Recommended reading

z

Atmel AVR XMEGA AU manual

z

XMEGA application notes

This device data sheet only contains part specific information with a short description of each peripheral and module.

The XMEGA AU manual describes the modules and peripherals in depth. The XMEGA application notes contain

example code and show applied use of the modules and peripherals.

All documentation are available from www.atmel.com/avr.

5.

Capacitive touch sensing

The Atmel QTouch library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR

microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced

reporting of touch keys and includes Adjacent Key Suppression^®(AKS^®) technology for unambiguous detection of key

events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.

Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR

microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling

the touch sensing API’s to retrieve the channel information and determine the touch sensor states.

The QTouch library is FREE and downloadable from the Atmel website at the following location:

www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the QTouch library user

guide - also available for download from the Atmel website.

XMEGA A4U [DATASHEET]

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6.

AVR CPU

6.1

Features

z

8/16-bit, high-performance Atmel AVR RISC CPU

z 142 instructions

z Hardware multiplier

z

32x8-bit registers directly connected to the ALU

Stack in RAM

Stack pointer accessible in I/O memory space

Direct addressing of up to 16MB of program memory and 16MB of data memory

True 16/24-bit access to 16/24-bit I/O registers

Efficient support for 8-, 16-, and 32-bit arithmetic

Configuration change protection of system-critical features

6.2

6.3

Overview

All Atmel AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and

perform all calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute

the program in the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and

Programmable Multilevel Interrupt Controller” on page 29.

Architectural Overview

In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories

and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While

one instruction is being executed, the next instruction is pre-fetched from the program memory. This enables

instructions to be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.

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Figure 6-1. Block diagram of the AVR CPU architecture.

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and

a register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status

register is updated to reflect information about the result of the operation.

The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all

have single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or

between a register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program

and data space addressing, enabling efficient address calculations.

The memory spaces are linear. The data memory space and the program memory space are two different memory

spaces.

The data memory space is divided into I/O registers, SRAM, and external RAM. In addition, the EEPROM can be

memory mapped in the data memory.

All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the

I/O memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to

0x3F. The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be

accessed as data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.

The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five

different addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.

Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.

The program memory is divided in two sections, the application program section and the boot program section. Both

sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-

programming of the application flash memory must reside in the boot program section. The application section

contains an application table section with separate lock bits for write and read/write protection. The application table

section can be used for safe storing of nonvolatile data in the program memory.

6.4

ALU - Arithmetic Logic Unit

The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and

a register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general

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purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a

register and an immediate are executed and the result is stored in the register file. After an arithmetic or logic

operation, the status register is updated to reflect information about the result of the operation.

ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit

arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware

multiplier supports signed and unsigned multiplication and fractional format.

6.4.1 Hardware Multiplier

The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports

different variations of signed and unsigned integer and fractional numbers:

z

Multiplication of unsigned integers

Multiplication of signed integers

Multiplication of a signed integer with an unsigned integer

Multiplication of unsigned fractional numbers

Multiplication of signed fractional numbers

Multiplication of a signed fractional number with an unsigned one

A multiplication takes two CPU clock cycles.

6.5

Program Flow

After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The

program counter (PC) addresses the next instruction to be fetched.

Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole

address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.

During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the

general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the

SRAM. After reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write

accessible in the I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM

can easily be accessed through the five different addressing modes supported in the AVR CPU.

6.6

Status Register

The status register (SREG) contains information about the result of the most recently executed arithmetic or logic

instruction. This information can be used for altering program flow in order to perform conditional operations. Note that

the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many

cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The status register is not automatically stored when entering an interrupt routine nor restored when returning from an

interrupt. This must be handled by software.

The status register is accessible in the I/O memory space.

6.7

Stack and Stack Pointer

The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing

temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit

registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH

and POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that

pushing data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is

automatically loaded after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed,

it must be set to point above address 0x2000, and it must be defined before any subroutine calls are executed or

before interrupts are enabled.

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During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can

be two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program

memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For

devices with more than 128KB of program memory, the return address is three bytes, and hence the SP is

decremented/incremented by three. The return address is popped off the stack when returning from interrupts using

the RETI instruction, and from subroutine calls using the RET instruction.

The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by

one when data is popped off the stack using the POP instruction.

To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable

interrupts for up to four instructions or until the next I/O memory write.

After reset the stack pointer is initialized to the highest address of the SRAM. See Figure 7-1 on page 16.

6.8

Register File

The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The

register file supports the following input/output schemes:

z

One 8-bit output operand and one 8-bit result input

Two 8-bit output operands and one 8-bit result input

Two 8-bit output operands and one 16-bit result input

One 16-bit output operand and one 16-bit result input

Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling

efficient address calculations. One of these address pointers can also be used as an address pointer for lookup tables

in flash program memory.

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7.

Memories

7.1

Features

z

Flash program memory

z One linear address space

z In-system programmable

z Self-programming and boot loader support

z Application section for application code

z Application table section for application code or data storage

z Boot section for application code or boot loader code

z Separate read/write protection lock bits for all sections

z Built in fast CRC check of a selectable flash program memory section

z

Data memory

z One linear address space

z Single-cycle access from CPU

z SRAM

z EEPROM

z

Byte and page accessible

z

Optional memory mapping for direct load and store

z I/O memory

z

Configuration and status registers for all peripherals and modules

16 bit-accessible general purpose registers for global variables or flags

z

z Bus arbitration

z

Deterministic priority handling between CPU, DMA controller, and other bus masters

z Separate buses for SRAM, EEPROM and I/O memory

z

Simultaneous bus access for CPU and DMA controller

z

Production signature row memory for factory programmed data

z ID for each microcontroller device type

z Serial number for each device

z Calibration bytes for factory calibrated peripherals

User signature row

z One flash page in size

z Can be read and written from software

z Content is kept after chip erase

7.2

Overview

The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable

code can reside only in the program memory, while data can be stored in the program memory and the data memory.

The data memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are

linear and require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and

read/write operations. This prevents unrestricted access to the application software.

A separate memory section contains the fuse bytes. These are used for configuring important system functions, and

can only be written by an external programmer.

The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has

a Flash memory signature row for calibration data, device identification, serial number etc.

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7.3

Flash Program Memory

The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The

flash memory can be accessed for read and write from an external programmer through the PDI or from application

software running in the device.

All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is

organized in two main sections, the application section and the boot loader section. The sizes of the different sections

are fixed, but device-dependent. These two sections have separate lock bits, and can have different levels of

protection. The store program memory (SPM) instruction, which is used to write to the flash from the application

software, will only operate when executed from the boot loader section.

The application section contains an application table section with separate lock settings. This enables safe storage of

nonvolatile data in the program memory.

Table 7-1. Flash Program Memory (Hexadecimal address).

Word Address

ATxmega128A4U

ATxmega64A4U

ATxmega32A4U

ATxmega16A4U

0

Application Section

(128K/64K/32K/16K)

...

EFFF

F000

/

77FF

7800

7FFF

8000

87FF

/

37FF

3800

3FFF

4000

47FF

/

17FF

1800

1FFF

2000

27FF

Application Table Section

(8K/4K/4K/4K)

FFFF

10000

10FFF

Boot Section

(8K/4K/4K/4K)

7.3.1 Application Section

The Application section is the section of the flash that is used for storing the executable application code. The

protection level for the application section can be selected by the boot lock bits for this section. The application section

can not store any boot loader code since the SPM instruction cannot be executed from the application section.

7.3.2 Application Table Section

The application table section is a part of the application section of the flash memory that can be used for storing data.

The size is identical to the boot loader section. The protection level for the application table section can be selected by

the boot lock bits for this section. The possibilities for different protection levels on the application section and the

application table section enable safe parameter storage in the program memory. If this section is not used for data,

application code can reside here.

7.3.3 Boot Loader Section

While the application section is used for storing the application code, the boot loader software must be located in the

boot loader section because the SPM instruction can only initiate programming when executing from this section. The

SPM instruction can access the entire flash, including the boot loader section itself. The protection level for the boot

loader section can be selected by the boot loader lock bits. If this section is not used for boot loader software,

application code can be stored here.

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7.3.4 Production Signature Row

The production signature row is a separate memory section for factory programmed data. It contains calibration data

for functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to

the corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and

written to the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical

Characteristics” on page 72.

The production signature row also contains an ID that identifies each microcontroller device type and a serial number

for each manufactured device. The serial number consists of the production lot number, wafer number, and wafer

coordinates for the device. The device ID for the available devices is shown in Table 7-2.

The production signature row cannot be written or erased, but it can be read from application software and external

programmers.

Table 7-2. Device ID bytes for Atmel AVR XMEGA A4U devices.

Device

Device ID bytes

Byte 2

41

Byte 1

94

Byte 0

1E

ATxmega16A4U

ATxmega32A4U

ATxmega64A4U

ATxmega128A4U

41

95

1E

46

96

1E

46

97

1E

7.3.5 User Signature Row

The user signature row is a separate memory section that is fully accessible (read and write) from application software

and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as

calibration data, custom serial number, identification numbers, random number seeds, etc. This section is not erased

by chip erase commands that erase the flash, and requires a dedicated erase command. This ensures parameter

storage during multiple program/erase operations and on-chip debug sessions.

7.4

Fuses and Lock bits

The fuses are used to configure important system functions, and can only be written from an external programmer.

The application software can read the fuses. The fuses are used to configure reset sources such as brownout detector

and watchdog, and startup configuration.

The lock bits are used to set protection levels for the different flash sections (that is, if read and/or write access should

be blocked). Lock bits can be written by external programmers and application software, but only to stricter protection

levels. Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip

erase, the lock bits are erased after the rest of the flash memory has been erased.

An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value

zero.

Both fuses and lock bits are reprogrammable like the flash program memory.

7.5

Data Memory

The data memory contains the I/O memory, internal SRAM, optionally memory mapped EEPROM, and external

memory if available. The data memory is organized as one continuous memory section, see Figure 7-1. To simplify

development, I/O Memory, EEPROM and SRAM will always have the same start addresses for all Atmel AVR

XMEGA devices.

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Figure 7-1. Data memory map (Hexadecimal address).

Byte Address

ATxmega64A4U

I/O Registers (4K)

Byte Address

ATxmega32A4U

I/O Registers (4K)

Byte Address

ATxmega16A4U

I/O Registers (4K)

0

FFF

1000

17FF

FFF

1000

13FF

FFF

1000

13FF

EEPROM (2K)

RESERVED

EEPROM (1K)

RESERVED

EEPROM (1K)

RESERVED

2000

2FFF

2000

2FFF

2000

27FF

Internal SRAM (4K)

Internal SRAM (2K)

Byte Address

ATxmega128A4U

I/O Registers (4K)

0

FFF

1000

17FF

EEPROM (2K)

RESERVED

2000

3FFF

Internal SRAM (8K)

7.6

7.7

EEPROM

All devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space (default) or

memory mapped and accessed in normal data space. The EEPROM supports both byte and page access. Memory

mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this, EEPROM

is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal address

0x1000.

I/O Memory

The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O

memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,

which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT

instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,

single-cycle instructions for manipulation and checking of individual bits are available.

The I/O memory address for all peripherals and modules in XMEGA A4U is shown in the “Peripheral Module Address

Map” on page 61.

7.7.1 General Purpose I/O Registers

The lowest 16 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for

storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

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7.8

7.9

Data Memory and Bus Arbitration

Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA

controller read and DMA controller write, etc.) can access different memory sections at the same time.

Memory Timing

Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read

from SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write)

takes one cycle, and three cycles are required for read. For burst read, new data are available every second cycle.

Refer to the instruction summary for more details on instructions and instruction timing.

7.10 Device ID and Revision

Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device

type. A separate register contains the revision number of the device.

7.11 I/O Memory Protection

Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock

the I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the

lock is enabled, all related I/O registers are locked and they can not be written from the application software. The lock

registers themselves are protected by the configuration change protection mechanism.

7.12 Flash and EEPROM Page Size

The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for

the flash and byte accessible for the EEPROM.

Table 7-3 on page 17 shows the Flash Program Memory organization and Program Counter (PC) size. Flash write

and erase operations are performed on one page at a time, while reading the Flash is done one byte at a time. For

Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in the address (FPAGE) give the

page number and the least significant address bits (FWORD) give the word in the page.

Table 7-3. Number of words and pages in the flash.

Devices

PC size

Flash size

Page Size

FWORD

FPAGE

Application

Boot

No of

pages

No of

pages

bits

bytes

words

Size

ATxmega16A4U

ATxmega32A4U

ATxmega64A4U

ATxmega128A4U

14

15

16

17

16K + 4K

32K + 4K

64K + 4K

128K + 8K

128

Z[6:0]

Z[13:7]

Z[14:7]

Z[15:7]

Z[16:7]

16K

64

4K

16

32K

64K

128

4K

8K

16

256

16

128K

512

32

Table 7-4 shows EEPROM memory organization for the Atmel AVR XMEGA A4U devices. EEEPROM write and

erase operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a

time. For EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in

the address (E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the

page.

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Table 7-4. Number of bytes and pages in the EEPROM.

Devices

EEPROM

Page Size

E2BYTE

E2PAGE

No of Pages

Size

bytes

ATxmega16A4U

ATxmega32A4U

ATxmega64A4U

ATxmega128A4U

1K

2K

32

ADDR[4:0]

ADDR[10:5]

32

64

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8.

DMAC – Direct Memory Access Controller

8.1

Features

z

Allows high speed data transfers with minimal CPU intervention

z from data memory to data memory

z from data memory to peripheral

z from peripheral to data memory

z from peripheral to peripheral

z

Four DMA channels with separate

z transfer triggers

z interrupt vectors

z addressing modes

z

Programmable channel priority

From 1 byte to 16MB of data in a single transaction

z Up to 64KB block transfers with repeat

z 1, 2, 4, or 8 byte burst transfers

z

Multiple addressing modes

z Static

z Incremental

z Decremental

Optional reload of source and destination addresses at the end of each

z Burst

z Block

z Transaction

z

Optional interrupt on end of transaction

Optional connection to CRC generator for CRC on DMA data

8.2

Overview

The four-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and

thus offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees

up CPU time. The four DMA channels enable up to four independent and parallel transfers.

The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between

peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from

communication modules. The DMA controller can also read from memory mapped EEPROM.

Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from

1 byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source

and destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination

addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,

peripherals, and events can trigger DMA transfers.

The four DMA channels have individual configuration and control settings. This include source, destination, transfer

triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a

transaction is complete or when the DMA controller detects an error on a DMA channel.

To allow for continuous transfers, two channels can be interlinked so that the second takes over the transfer when the

first is finished, and vice versa.

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9.

Event System

9.1

Features

z

System for direct peripheral-to-peripheral communication and signaling

z

Peripherals can directly send, receive, and react to peripheral events

z CPU and DMA controller independent operation

z 100% predictable signal timing

z Short and guaranteed response time

z

Eight event channels for up to eight different and parallel signal routing configurations

Events can be sent and/or used by most peripherals, clock system, and software

Additional functions include

z Quadrature decoders

z Digital filtering of I/O pin state

z

Works in active mode and idle sleep mode

9.2

Overview

The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one

peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system

for short and predictable response times between peripherals. It allows for autonomous peripheral control and

interaction without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the

complexity, size and execution time of application code. It also allows for synchronized timing of actions in several

peripheral modules.

A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt

conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event

routing network. How events are routed and used by the peripherals is configured in software.

Figure 9-1 on page 20 shows a basic diagram of all connected peripherals. The event system can directly connect

together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR

communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA

controller). Events can also be generated from software and the peripheral clock.

Figure 9-1. Event system overview and connected peripherals.

CPU /

Software

DMA

Controller

Event Routing Network

clk_PER

Prescaler

ADC

AC

Real Time

Counter

Event

System

Controller

Timer /

Counters

DAC

USB

Port pins

IRCOM

The event routing network consists of eight software-configurable multiplexers that control how events are routed and

used. These are called event channels, and allow for up to eight parallel event routing configurations. The maximum

routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.

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10. System Clock and Clock options

10.1 Features

z

Fast start-up time

Safe run-time clock switching

Internal oscillators:

z 32MHz run-time calibrated and tuneable oscillator

z 2MHz run-time calibrated oscillator

z 32.768kHz calibrated oscillator

z 32kHz ultra low power (ULP) oscillator with 1kHz output

z

External clock options

z 0.4MHz - 16MHz crystal oscillator

z 32.768kHz crystal oscillator

z External clock

PLL with 20MHz - 128MHz output frequency

z Internal and external clock options and 1x to 31x multiplication

z Lock detector

z

Clock prescalers with 1x to 2048x division

Fast peripheral clocks running at two and four times the CPU clock

Automatic run-time calibration of internal oscillators

External oscillator and PLL lock failure detection with optional non-maskable interrupt

10.2 Overview

Atmel AVR XMEGA A4U devices have a flexible clock system supporting a large number of clock sources. It

incorporates both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency

phase locked loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A

calibration feature (DFLL) is available, and can be used for automatic run-time calibration of the internal oscillators to

remove frequency drift over voltage and temperature. An oscillator failure monitor can be enabled to issue a non-

maskable interrupt and switch to the internal oscillator if the external oscillator or PLL fails.

When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the

device will always start up running from the 2MHz internal oscillator. During normal operation, the system clock

source and prescalers can be changed from software at any time.

Figure 10-1 on page 22 presents the principal clock system in the XMEGA A4U family of devices. Not all of the clocks

need to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and

power reduction registers, as described in “Power Management and Sleep Modes” on page 24.

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Figure 10-1. The clock system, clock sources and clock distribution.

Real Time

Counter

Non-Volatile

Memory

Peripherals

RAM

AVR CPU

clk_PER

clk_PER2

clk_PER4

clk_CPU

USB

clk_USB

System Clock Prescalers

clk_SYS

Brown-out

Detector

Watchdog

Timer

Prescaler

clk_RTC

System Clock Multiplexer

(SCLKSEL)

RTCSRC

USBSRC

PLL

PLLSRC

XOSCSEL

32 kHz

Int. ULP

32.768 kHz

Int. OSC

32.768 kHz

TOSC

0.4 – 16 MHz

XTAL

32 MHz

Int. Osc

2 MHz

Int. Osc

10.3 Clock Sources

The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock

sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,

depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other

clock sources, DFLLs and PLL, are turned off by default.

The internal oscillators do not require any external components to run. For details on characteristics and accuracy of

the internal oscillators, refer to the device datasheet.

10.3.1 32kHz Ultra Low Power Internal Oscillator

This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low

power clock source, and it is not designed for high accuracy. The oscillator employs a built-in prescaler that provides

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a 1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the

device. This oscillator can be selected as the clock source for the RTC.

10.3.2 32.768kHz Calibrated Internal Oscillator

This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default

frequency close to its nominal frequency. The calibration register can also be written from software for run-time

calibration of the oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz

output and a 1.024kHz output.

10.3.3 32.768kHz Crystal Oscillator

A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low

frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator

can be used as a clock source for the system clock and RTC, and as the DFLL reference clock.

10.3.4 0.4 - 16MHz Crystal Oscillator

This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4 - 16MHz.

10.3.5 2MHz Run-time Calibrated Internal Oscillator

The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during

production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-

time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.

10.3.6 32MHz Run-time Calibrated Internal Oscillator

The 32MHz run-time calibrated internal oscillator is a high-frequency oscillator. It is calibrated during production to

provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for

automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the

oscillator accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz.

The production signature row contains 48MHz calibration values intended used when the oscillator is used a full-

speed USB clock source.

10.3.7 External Clock Sources

The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.

XTAL1 can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated to driving a

32.768kHz crystal oscillator.

10.3.8 PLL with 1x-31x Multiplication Factor

The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-

selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output

frequencies from all clock sources.

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11. Power Management and Sleep Modes

11.1 Features

z

Power management for adjusting power consumption and functions

z

Five sleep modes

z Idle

z Power down

z Power save

z Standby

z Extended standby

z

Power reduction register to disable clock and turn off unused peripherals in active and idle modes

11.2 Overview

Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.

This enables the Atmel AVR XMEGA microcontroller to stop unused modules to save power.

All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application

code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the

device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals

and all enabled reset sources can restore the microcontroller from sleep to active mode.

In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When

this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This

reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power

management than sleep modes alone.

11.3 Sleep Modes

Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power.

XMEGA microcontrollers have five different sleep modes tuned to match the typical functional stages during

application execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to

wake the device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep

mode. When an enabled interrupt occurs, the device will wake up and execute the interrupt service routine before

continuing normal program execution from the first instruction after the SLEEP instruction. If other, higher priority

interrupts are pending when the wake-up occurs, their interrupt service routines will be executed according to their

priority before the interrupt service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for

four cycles before execution starts.

The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device

will reset, start up, and execute from the reset vector.

11.3.1 Idle Mode

In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed),

but all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled

interrupt will wake the device.

11.3.2 Power-down Mode

In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only

of asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the

two-wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.

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11.3.3 Power-save Mode

Power-save mode is identical to power down, with one exception. If the real-time counter (RTC) is enabled, it will keep

running during sleep, and the device can also wake up from either an RTC overflow or compare match interrupt.

11.3.4 Standby Mode

Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running

while the CPU, peripheral, and RTC clocks are stopped. This reduces the wake-up time.

11.3.5 Extended Standby Mode

Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources

are kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.

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12. System Control and Reset

12.1 Features

z

Reset the microcontroller and set it to initial state when a reset source goes active

z

Multiple reset sources that cover different situations

z Power-on reset

z External reset

z Watchdog reset

z Brownout reset

z PDI reset

z Software reset

z

Asynchronous operation

z No running system clock in the device is required for reset

Reset status register for reading the reset source from the application code

12.2 Overview

The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where

operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a

reset source goes active, the device enters and is kept in reset until all reset sources have released their reset. The

I/O pins are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set

to their initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the

content of the accessed location can not be guaranteed.

After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts

running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to

move the reset vector to the lowest address in the boot section.

The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software

reset feature makes it possible to issue a controlled system reset from the user software.

The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows

which sources have issued a reset since the last power-on.

12.3 Reset Sequence

A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is

active. When all reset requests are released, the device will go through three stages before the device starts running

again:

z

Reset counter delay

Oscillator startup

Oscillator calibration

If another reset requests occurs during this process, the reset sequence will start over again.

12.4 Reset Sources

12.4.1 Power-on Reset

A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the V_CCrises and

reaches the POR threshold voltage (V_POT), and this will start the reset sequence.

The POR is also activated to power down the device properly when the V_CCfalls and drops below the V_POTlevel.

The V_POTlevel is higher for falling V_CCthan for rising V_CC. Consult the datasheet for POR characteristics data.

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12.4.2 Brownout Detection

The on-chip brownout detection (BOD) circuit monitors the V_CClevel during operation by comparing it to a fixed,

programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during

chip erase and when the PDI is enabled.

12.4.3 External Reset

The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin

is driven below the RESET pin threshold voltage, V_RST, for longer than the minimum pulse period, t_EXT. The reset will

be held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.

12.4.4 Watchdog Reset

The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from

the software within a programmable timeout period, a watchdog reset will be given. The watchdog reset is active for

one to two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 28.

12.4.5 Software Reset

The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the

reset control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to

execute any instruction from when a software reset is requested until it is issued.

12.4.6 Program and Debug Interface Reset

The program and debug interface reset contains a separate reset source that is used to reset the device during

external programming and debugging. This reset source is accessible only from external debuggers and

programmers.

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13. WDT – Watchdog Timer

13.1 Features

z

Issues a device reset if the timer is not reset before its timeout period

Asynchronous operation from dedicated oscillator

1kHz output of the 32kHz ultra low power oscillator

11 selectable timeout periods, from 8ms to 8s

Two operation modes:

z Normal mode

z Window mode

z

Configuration lock to prevent unwanted changes

13.2 Overview

The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to

recover from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined

timeout period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue

a microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the

application code.

The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT

must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.

Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.

The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent

clock source, and will continue to operate to issue a system reset even if the main clocks fail.

The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For

increased safety, a fuse for locking the WDT settings is also available.

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14. Interrupts and Programmable Multilevel Interrupt Controller

14.1 Features

z

Short and predictable interrupt response time

Separate interrupt configuration and vector address for each interrupt

Programmable multilevel interrupt controller

z Interrupt prioritizing according to level and vector address

z Three selectable interrupt levels for all interrupts: low, medium and high

z Selectable, round-robin priority scheme within low-level interrupts

z Non-maskable interrupts for critical functions

z

Interrupt vectors optionally placed in the application section or the boot loader section

14.2 Overview

Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can

have one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and

configured, it will generate an interrupt request when the interrupt condition is present. The programmable multilevel

interrupt controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is

acknowledged by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can

be executed.

All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts

are prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level

interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level,

the interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the

highest interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all

interrupts are serviced within a certain amount of time.

Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.

14.3 Interrupt vectors

The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts

in each peripheral. The base addresses for the Atmel AVR XMEGA A4U devices are shown in Table 14-1 on page 30.

Offset addresses for each interrupt available in the peripheral are described for each peripheral in the XMEGA AU

manual. For peripherals or modules that have only one interrupt, the interrupt vector is shown in Table 14-1 on page

30. The program address is the word address.

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Table 14-1. Reset and interrupt vectors

Program address

(base address)

0x000

0x002

0x004

0x008

0x00C

0x014

0x018

0x01C

0x028

0x030

0x032

0x038

0x03E

0x040

0x044

0x056

0x05A

0x05E

0x06A

0x074

0x080

0x084

0x088

0x08E

0x09A

0x0A6

0x0AE

0x0B0

0x0B6

0x0FA

Source

Interrupt description

RESET

OSCF_INT_vect

PORTC_INT_base

PORTR_INT_base

DMA_INT_base

RTC_INT_base

TWIC_INT_base

TCC0_INT_base

TCC1_INT_base

SPIC_INT_vect

Crystal oscillator failure interrupt vector (NMI)

Port C interrupt base

Port R interrupt base

DMA controller interrupt base

Real time counter interrupt base

Two-Wire Interface on Port C interrupt base

Timer/counter 0 on port C interrupt base

Timer/counter 1 on port C interrupt base

SPI on port C interrupt vector

USARTC0_INT_base

USARTC1_INT_base

AES_INT_vect

USART 0 on port C interrupt base

USART 1 on port C interrupt base

AES interrupt vector

NVM_INT_base

PORTB_INT_base

PORTE_INT_base

TWIE_INT_base

TCE0_INT_base

TCE1_INT_base

USARTE0_INT_base

PORTD_INT_base

PORTA_INT_base

ACA_INT_base

ADCA_INT_base

TCD0_INT_base

TCD1_INT_base

SPID_INT_vector

USARTD0_INT_base

USARTD1_INT_base

USB_INT_base

Nonvolatile Memory interrupt base

Port B interrupt base

Port E interrupt base

Two-wire Interface on Port E interrupt base

Timer/counter 0 on port E interrupt base

Timer/counter 1 on port E interrupt base

USART 0 on port E interrupt base

Port D interrupt base

Port A interrupt base

Analog Comparator on Port A interrupt base

Analog to Digital Converter on Port A interrupt base

Timer/counter 0 on port D interrupt base

Timer/counter 1 on port D interrupt base

SPI on port D interrupt vector

USART 0 on port D interrupt base

USART 1 on port D interrupt base

USB on port D interrupt base

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15. I/O Ports

15.1 Features

z

34 general purpose input and output pins with individual configuration

z

Output driver with configurable driver and pull settings:

z Totem-pole

z Wired-AND

z Wired-OR

z Bus-keeper

z Inverted I/O

z

Input with synchronous and/or asynchronous sensing with interrupts and events

z Sense both edges

z Sense rising edges

z Sense falling edges

z Sense low level

z

Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations

Optional slew rate control

Asynchronous pin change sensing that can wake the device from all sleep modes

Two port interrupts with pin masking per I/O port

Efficient and safe access to port pins

z Hardware read-modify-write through dedicated toggle/clear/set registers

z Configuration of multiple pins in a single operation

z Mapping of port registers into bit-accessible I/O memory space

z

Peripheral clocks output on port pin

Real-time counter clock output to port pin

Event channels can be output on port pin

Remapping of digital peripheral pin functions

z Selectable USART, SPI, and timer/counter input/output pin locations

15.2 Overview

One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with

configurable driver and pull settings. They also implement synchronous and asynchronous input sensing with

interrupts and events for selectable pin change conditions. Asynchronous pin-change sensing means that a pin

change can wake the device from all sleep modes, included the modes where no clocks are running.

All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins

have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor

configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other

pin.

The port pin configuration also controls input and output selection of other device functions. It is possible to have both

the peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to

events from the event system that can be used to synchronize and control external functions. Other digital

peripherals, such as USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to

optimize pin-out versus application needs.

The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, and PORTR.

15.3 Output Driver

All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to

reduce electromagnetic emission.

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15.3.1 Push-pull

Figure 15-1. I/O configuration - Totem-pole.

DIRn

OUTn

INn

Pn

15.3.2 Pull-down

Figure 15-2. I/O configuration - Totem-pole with pull-down (on input).

DIRn

OUTn

INn

Pn

15.3.3 Pull-up

Figure 15-3. I/O configuration - Totem-pole with pull-up (on input).

DIRn

OUTn

INn

Pn

15.3.4 Bus-keeper

The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last

level was ‘1’, and pull-down if the last level was ‘0’.

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Figure 15-4. I/O configuration - Totem-pole with bus-keeper.

DIRn

OUTn

INn

Pn

15.3.5 Others

Figure 15-5. Output configuration - Wired-OR with optional pull-down.

OUTn

Pn

INn

Figure 15-6. I/O configuration - Wired-AND with optional pull-up.

INn

Pn

OUTn

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15.4 Input sensing

Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is

shown in Figure 15-7.

Figure 15-7. Input sensing system overview.

Asynchronous sensing

EDGE

DETECT

Interrupt

Control

IREQ

Event

Synchronous sensing

Pn

Synchronizer

INn

EDGE

DETECT

Q

D

INVERTED I/O

R

When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.

15.5 Alternate Port Functions

Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function

is enabled, it might override the normal port pin function or pin value. This happens when other peripherals that

require pins are enabled or configured to use pins. If and how a peripheral will override and use pins is described in

the section for that peripheral. “Pinout and Pin Functions” on page 55 shows which modules on peripherals that

enable alternate functions on a pin, and which alternate functions that are available on a pin.

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16. TC0/1 – 16-bit Timer/Counter Type 0 and 1

16.1 Features

z

Five 16-bit timer/counters

z Three timer/counters of type 0

z Two timer/counters of type 1

z Split-mode enabling two 8-bit timer/counter from each timer/counter type 0

z

32-bit timer/counter support by cascading two timer/counters

Up to four compare or capture (CC) channels

z Four CC channels for timer/counters of type 0

z Two CC channels for timer/counters of type 1

z

Double buffered timer period setting

Double buffered capture or compare channels

Waveform generation:

z Frequency generation

z Single-slope pulse width modulation

z Dual-slope pulse width modulation

z

Input capture:

z Input capture with noise cancelling

z Frequency capture

z Pulse width capture

z 32-bit input capture

z

Timer overflow and error interrupts/events

One compare match or input capture interrupt/event per CC channel

Can be used with event system for:

z Quadrature decoding

z Count and direction control

z Capture

z

Can be used with DMA and to trigger DMA transactions

High-resolution extension

z Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)

z

Advanced waveform extension:

z Low- and high-side output with programmable dead-time insertion (DTI)

Event controlled fault protection for safe disabling of drivers

16.2 Overview

Atmel AVR XMEGA devices have a set of five flexible 16-bit Timer/Counters (TC). Their capabilities include accurate

program execution timing, frequency and waveform generation, and input capture with time and frequency

measurement of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-

bit capture.

A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be

used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC

channels can be used together with the base counter to do compare match control, frequency generation, and pulse

width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either

capture or compare functions, but cannot perform both at the same time.

A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.

The event system can also be used for direction control and capture trigger or to synchronize operations.

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There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and

timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.

Only Timer/Counter 0 has the split mode feature that split it into two 8-bit Timer/Counters with four compare channels

each.

Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced

waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and

high-side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It

can also generate a synchronized bit pattern across the port pins.

The advanced waveform extension can be enabled to provide extra and more advanced features for the

Timer/Counter. This are only available for Timer/Counter 0. See “AWeX – Advanced Waveform Extension” on page

38 for more details.

The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times

by using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High

Resolution Extension” on page 39 for more details.

Figure 16-1. Overview of a Timer/Counter and closely related peripherals.

Timer/Counter

Base Counter

Prescaler

clk_PER

Timer Period

Counter

Control Logic

Event

System

clk_PER4

Compare/Capture Channel D

Compare/Capture Channel C

Compare/Capture Channel B

Compare/Capture Channel A

AWeX

Pattern

Generation

Fault

Dead-Time

Insertion

Capture

Comparator

Control

Protection

Waveform

Generation

Buffer

PORTC and PORTD each has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Conter0.

Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1 and TCE0, respectively.

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17. TC2 - Timer/Counter Type 2

17.1 Features

z

Six eight-bit timer/counters

z Three Low-byte timer/counter

z Three High-byte timer/counter

Up to eight compare channels in each Timer/Counter 2

z Four compare channels for the low-byte timer/counter

z Four compare channels for the high-byte timer/counter

Waveform generation

z Single slope pulse width modulation

z

Timer underflow interrupts/events

One compare match interrupt/event per compare channel for the low-byte timer/counter

Can be used with the event system for count control

Can be used to trigger DMA transactions

17.2 Overview

There are four Timer/Counter 2. These are realized when a Timer/Counter 0 is set in split mode. It is then a system of

two eight-bit timer/counters, each with four compare channels. This results in eight configurable pulse width

modulation (PWM) channels with individually controlled duty cycles, and is intended for applications that require a

high number of PWM channels.

The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte

timer/counter, respectively. The difference between them is that only the low-byte timer/counter can be used to

generate compare match interrupts, events and DMA triggers. The two eight-bit timer/counters have a shared clock

source and separate period and compare settings. They can be clocked and timed from the peripheral clock, with

optional prescaling, or from the event system. The counters are always counting down.

PORTC, and PORTD each has one Timer/Counter 2.

Notation of these are TCC2 (Time/Counter C2) and TCD2, respectively.

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18. AWeX – Advanced Waveform Extension

18.1 Features

z

Waveform output with complementary output from each compare channel

z

Four dead-time insertion (DTI) units

z 8-bit resolution

z Separate high and low side dead-time setting

z Double buffered dead time

z Optionally halts timer during dead-time insertion

z

Pattern generation unit creating synchronised bit pattern across the port pins

z Double buffered pattern generation

z Optional distribution of one compare channel output across the port pins

Event controlled fault protection for instant and predictable fault triggering

18.2 Overview

The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation

(WG) modes. It is primarily intended for use with different types of motor control and other power control applications.

It enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down

external drivers. It can also generate a synchronized bit pattern across the port pins.

Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when

any AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the

non-inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS

switching. The DTI output will override the normal port value according to the port override setting.

The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In

addition, the WG output from compare channel A can be distributed to and override all the port pins. When the pattern

generator unit is enabled, the DTI unit is bypassed.

The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will

disable the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the

selection of fault triggers.

The AWeX is available for TCC0. The notation of this is AWEXC.

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19. Hi-Res – High Resolution Extension

19.1 Features

z

Increases waveform generator resolution up to 8x (three bits)

Supports frequency, single-slope PWM, and dual-slope PWM generation

Supports the AWeX when this is used for the same timer/counter

19.2 Overview

The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output from

a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or dual-slope

PWM generation. It can also be used with the AWeX if this is used for the same timer/counter.

The hi-res extension uses the peripheral 4x clock (Clk_PER4). The system clock prescalers must be configured so the

peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res

extension is enabled.

There are three hi-res extensions that each can be enabled for each timer/counters pair on PORTC, PORTD and

PORTE. The notation of these are HIRESC, HIRESD and HIRESE, respectively.

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20. RTC – 16-bit Real-Time Counter

20.1 Features

z

16-bit resolution

z

Selectable clock source

z 32.768kHz external crystal

z External clock

z 32.768kHz internal oscillator

z 32kHz internal ULP oscillator

z

Programmable 10-bit clock prescaling

One compare register

One period register

Clear counter on period overflow

Optional interrupt/event on overflow and compare match

20.2 Overview

The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes,

to keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.

The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the

configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC

needs a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz

internal oscillator or the 32kHz internal ULP oscillator.

The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the

counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the

maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the

maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event

when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period

register value.

Figure 20-1. Real-time counter overview.

External Clock

TOSC1

32.768kHz Crystal Osc

TOSC2

32.768kHz Int. Osc

32kHz int ULP (DIV32)

PER

RTCSRC

TOP/

clk_RTC

10-bit

=

Overflow

CNT

prescaler

”match”/

Compare

COMP

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21. USB – Universal Serial Bus Interface

21.1 Features

z

One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface

Integrated on-chip USB transceiver, no external components needed

16 endpoint addresses with full endpoint flexibility for up to 31 endpoints

z One input endpoint per endpoint address

z One output endpoint per endpoint address

z

Endpoint address transfer type selectable to

z Control transfers

z Interrupt transfers

z Bulk transfers

z Isochronous transfers

z

Configurable data payload size per endpoint, up to 1023 bytes

Endpoint configuration and data buffers located in internal SRAM

z Configurable location for endpoint configuration data

z Configurable location for each endpoint's data buffer

z

Built-in direct memory access (DMA) to internal SRAM for:

z Endpoint configurations

z Reading and writing endpoint data

Ping-pong operation for higher throughput and double buffered operation

z Input and output endpoint data buffers used in a single direction

z CPU/DMA controller can update data buffer during transfer

Multipacket transfer for reduced interrupt load and software intervention

z Data payload exceeding maximum packet size is transferred in one continuous transfer

z No interrupts or software interaction on packet transaction level

Transaction complete FIFO for workflow management when using multiple endpoints

z Tracks all completed transactions in a first-come, first-served work queue

z

Clock selection independent of system clock source and selection

Minimum 1.5MHz CPU clock required for low speed USB operation

Minimum 12MHz CPU clock required for full speed operation

Connection to event system

On chip debug possibilities during USB transactions

21.2 Overview

The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.

The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total

of 31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be

configured for any of the four transfer types; control, interrupt, bulk, or isochronous. The data payload size is also

selectable, and it supports data payloads up to 1023 bytes.

No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration

for each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint

configurations and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to

the number of endpoints in use and the configuration of these. The USB module has built-in direct memory access

(DMA), and will read/write data from/to the SRAM when a USB transaction takes place.

To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and

output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer

while the USB module writes/reads the others, and vice versa. This gives double buffered communication.

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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as

multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB

transfers.

For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle

and a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any

sleep mode.

PORTD has one USB. Notation of this is USB.

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22. TWI – Two-Wire Interface

22.1 Features

z

Two Identical two-wire interface peripherals

z

Bidirectional, two-wire communication interface

z Phillips I²C compatible

z System Management Bus (SMBus) compatible

z

Bus master and slave operation supported

z Slave operation

z Single bus master operation

z Bus master in multi-master bus environment

z Multi-master arbitration

Flexible slave address match functions

z 7-bit and general call address recognition in hardware

z 10-bit addressing supported

z Address mask register for dual address match or address range masking

z Optional software address recognition for unlimited number of addresses

z

Slave can operate in all sleep modes, including power-down

Slave address match can wake device from all sleep modes

100kHz and 400kHz bus frequency support

Slew-rate limited output drivers

Input filter for bus noise and spike suppression

Support arbitration between start/repeated start and data bit (SMBus)

Slave arbitration allows support for address resolve protocol (ARP) (SMBus)

22.2 Overview

The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I²C and System Management

Bus (SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each

bus line.

A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing

a slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or

several masters that can take control of the bus. An arbitration process handles priority if more than one master tries

to transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.

The TWI module supports master and slave functionality. The master and slave functionality are separated from each

other, and can be enabled and configured separately. The master module supports multi-master bus operation and

arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick

command and smart mode can be enabled to auto-trigger operations and reduce software complexity.

The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit

addressing is also supported. A dedicated address mask register can act as a second address match register or as a

register for address range masking. The slave continues to operate in all sleep modes, including power-down mode.

This enables the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the

address matching to let this be handled in software instead.

The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors,

collision, and clock hold on the bus are also detected and indicated in separate status flags available in both master

and slave modes.

It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an

external TWI bus driver. This can be used for applications where the device operates from a different V_CCvoltage than

used by the TWI bus.

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PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE.

23. SPI – Serial Peripheral Interface

23.1 Features

z

Two Identical SPI peripherals

Full-duplex, three-wire synchronous data transfer

Master or slave operation

Lsb first or msb first data transfer

Eight programmable bit rates

Interrupt flag at the end of transmission

Write collision flag to indicate data collision

Wake up from idle sleep mode

Double speed master mode

23.2 Overview

The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It

allows fast communication between an Atmel AVR XMEGA device and peripheral devices or between several

microcontrollers. The SPI supports full-duplex communication.

A device connected to the bus must act as a master or slave. The master initiates and controls all data transactions.

PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID.

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24. USART

24.1 Features

z

Five identical USART peripherals

Full-duplex operation

Asynchronous or synchronous operation

z Synchronous clock rates up to 1/2 of the device clock frequency

z Asynchronous clock rates up to 1/8 of the device clock frequency

z

Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits

Fractional baud rate generator

z Can generate desired baud rate from any system clock frequency

z No need for external oscillator with certain frequencies

z

Built-in error detection and correction schemes

z Odd or even parity generation and parity check

z Data overrun and framing error detection

z Noise filtering includes false start bit detection and digital low-pass filter

Separate interrupts for

z Transmit complete

z Transmit data register empty

z Receive complete

z

Multiprocessor communication mode

z Addressing scheme to address a specific devices on a multidevice bus

z Enable unaddressed devices to automatically ignore all frames

Master SPI mode

z Double buffered operation

z Operation up to 1/2 of the peripheral clock frequency

IRCOM module for IrDA compliant pulse modulation/demodulation

24.2 Overview

The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial

communication module. The USART supports full-duplex communication and asynchronous and synchronous

operation. The USART can be configured to operate in SPI master mode and used for SPI communication.

Communication is frame based, and the frame format can be customized to support a wide range of standards. The

USART is buffered in both directions, enabling continued data transmission without any delay between frames.

Separate interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and

buffer overflow are detected in hardware and indicated with separate status flags. Even or odd parity generation and

parity check can also be enabled.

The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud

rates from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific

frequency to achieve a required baud rate. It also supports external clock input in synchronous slave operation.

When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive

buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both

modes. The registers are used in both modes, but their functionality differs for some control settings.

An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and

demodulation for baud rates up to 115.2Kbps.

PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these peripherals are USARTC0,

USARTC1, USARTD0, USARTD1 and USARTE0, respectively.

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25. IRCOM – IR Communication Module

25.1 Features

z

Pulse modulation/demodulation for infrared communication

IrDA compatible for baud rates up to 115.2Kbps

Selectable pulse modulation scheme

z 3/16 of the baud rate period

z Fixed pulse period, 8-bit programmable

z Pulse modulation disabled

z

Built-in filtering

Can be connected to and used by any USART

25.2 Overview

Atmel AVR XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud

rates up to 115.2Kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that

USART.

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26. AES and DES Crypto Engine

26.1 Features

z

Data Encryption Standard (DES) CPU instruction

Advanced Encryption Standard (AES) crypto module

DES Instruction

z Encryption and decryption

z DES supported

z Encryption/decryption in 16 CPU clock cycles per 8-byte block

z

AES crypto module

z Encryption and decryption

z Supports 128-bit keys

z Supports XOR data load mode to the state memory

z Encryption/decryption in 375 clock cycles per 16-byte block

26.2 Overview

The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards

for cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the

communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.

DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the

register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.

The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data

must be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375

peripheral clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out,

and an optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when

encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.

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27. CRC – Cyclic Redundancy Check Generator

27.1 Features

z

Cyclic redundancy check (CRC) generation and checking for

z Communication data

z Program or data in flash memory

z Data in SRAM and I/O memory space

z

Integrated with flash memory, DMA controller and CPU

z Continuous CRC on data going through a DMA channel

z Automatic CRC of the complete or a selectable range of the flash memory

z CPU can load data to the CRC generator through the I/O interface

z

CRC polynomial software selectable to

z CRC-16 (CRC-CCITT)

z CRC-32 (IEEE 802.3)

Zero remainder detection

27.2 Overview

A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data,

and it is commonly used to determine the correctness of a data transmission, and data present in the data and

program memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that

can be appended to the data and used as a checksum. When the same data are later received or read, the device or

application repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains

a data error. The application will then detect this and may take a corrective action, such as requesting the data to be

sent again or simply not using the incorrect data.

Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n

bits (any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2^-nof all longer

error bursts. The CRC module in Atmel AVR XMEGA devices supports two commonly used CRC polynomials; CRC-

16 (CRC-CCITT) and CRC-32 (IEEE 802.3).

z

CRC-16:

Polynomial:

Hex value:

x¹⁶+x¹²+x⁵+1

0x1021

CRC-32:

Polynomial:

Hex value:

x³²+x²⁶+x²³+x²²+x¹⁶+x¹²+x¹¹+x¹⁰+x⁸+x⁷+x⁵+x⁴+x²+x+1

0x04C11DB7

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28. ADC – 12-bit Analog to Digital Converter

28.1 Features

z

One Analog to Digital Converter (ADC)

12-bit resolution

Up to two million samples per second

z Two inputs can be sampled simultaneously using ADC and 1x gain stage

z Four inputs can be sampled within 1.5µs

z Down to 2.5µs conversion time with 8-bit resolution

z Down to 3.5µs conversion time with 12-bit resolution

z

Differential and single-ended input

z Up to 12 single-ended inputs

z 12x4 differential inputs without gain

z 8x4 differential inputs with gain

Built-in differential gain stage

z

1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options

z

Single, continuous and scan conversion options

Four internal inputs

z Internal temperature sensor

z DAC output

z AV_CCvoltage divided by 10

z 1.1V bandgap voltage

z

Four conversion channels with individual input control and result registers

z Enable four parallel configurations and results

z

Internal and external reference options

Compare function for accurate monitoring of user defined thresholds

Optional event triggered conversion for accurate timing

Optional DMA transfer of conversion results

Optional interrupt/event on compare result

28.2 Overview

The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to

two million samples per second (msps). The input selection is flexible, and both single-ended and differential

measurements can be done. For differential measurements, an optional gain stage is available to increase the

dynamic range. In addition, several internal signal inputs are available. The ADC can provide both signed and

unsigned results.

This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows a high sample rate at

a low system clock frequency. It also means that a new input can be sampled and a new ADC conversion started

while other ADC conversions are still ongoing. This removes dependencies between sample rate and propagation

delay.

The ADC has four conversion channels (0-3) with individual input selection, result registers, and conversion start

control. The ADC can then keep and use four parallel configurations and results, and this will ease use for

applications with high data throughput or for multiple modules using the ADC independently. It is possible to use DMA

to move ADC results directly to memory or peripherals when conversions are done.

Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with

the ADC. The output from the DAC, AV_CC/10 and the bandgap voltage can also be measured by the ADC.

The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software

intervention required.

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Figure 28-1. ADC overview.

ADC0

Compare

•

ADC11

Internal

<

>

V_INP

signals

ADC0

CH0 Result

CH1 Result

CH2 Result

CH3 Result

•

Threshold

(Int Req)

ADC7

½x - 64x

ADC4

•

ADC7

Int. signals

Internal

signals

V_INN

ADC0

•

Internal 1.00V

Internal AVCC/1.6V

Internal AVCC/2

AREFA

Reference

Voltage

ADC3

Int. signals

AREFB

Two inputs can be sampled simultaneously as both the ADC and the gain stage include sample and hold circuits, and

the gain stage has 1x gain setting. Four inputs can be sampled within 1.5µs without any intervention by the

application.

The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from

3.5µs for 12-bit to 2.5µs for 8-bit result.

ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when

the result is represented as a signed integer (signed 16-bit number).

PORTA has one ADC. Notation of this peripheral is ADCA.

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29. DAC – 12-bit Digital to Analog Converter

29.1 Features

z

One Digital to Analog Converter (DAC)

12-bit resolution

Two independent, continuous-drive output channels

Up to one million samples per second conversion rate per DAC channel

Built-in calibration that removes:

z

Offset error

Gain error

z

Multiple conversion trigger sources

z

On new available data

Events from the event system

High drive capabilities and support for

z

Resistive loads

Capacitive loads

Combined resistive and capacitive loads

z

Internal and external reference options

DAC output available as input to analog comparator and ADC

Low-power mode, with reduced drive strength

Optional DMA transfer of data

29.2 Overview

The digital-to-analog converter (DAC) converts digital values to voltages. The DAC has two channels, each with 12-bit

resolution, and is capable of converting up to one million samples per second (msps) on each channel. The built-in

calibration system can remove offset and gain error when loaded with calibration values from software.

Figure 29-1. DAC overview.

DMA req

(Data Empty)

D

A

T

12

Output

Driver

CH0DATA

DAC0

A

To

AC/ADC

Int.

driver

Trigger

Select

Enable

CTRLA

Enable

AVCC

Internal 1.00V

AREFA

Reference

selection

CTRLB

Internal Output

enable

AREFB

Trigger

Select

D

A

T

12

Output

Driver

CH1DATA

DAC1

A

DMA req

(Data Empty)

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A DAC conversion is automatically started when new data to be converted are available. Events from the event

system can also be used to trigger a conversion, and this enables synchronized and timed conversions between the

DAC and other peripherals, such as a timer/counter. The DMA controller can be used to transfer data to the DAC.

The DAC has high drive strength, and is capable of driving both resistive and capacitive loads, aswell as loads which

combine both. A low-power mode is available, which will reduce the drive strength of the output. Internal and external

voltage references can be used. The DAC output is also internally available for use as input to the analog comparator

or ADC.

PORTB has one DAC. Notation of this peripheral is DACB.

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30. AC – Analog Comparator

30.1 Features

z

Two Analog Comparators (ACs)

Selectable propagation delay versus current consumption

Selectable hysteresis

z No

z Small

z Large

z

Analog comparator output available on pin

Flexible input selection

z All pins on the port

z Output from the DAC

z Bandgap reference voltage

z A 64-level programmable voltage scaler of the internal AV_CCvoltage

z

Interrupt and event generation on:

z Rising edge

z Falling edge

z Toggle

Window function interrupt and event generation on:

z Signal above window

z Signal inside window

z Signal below window

Constant current source with configurable output pin selection

30.2 Overview

The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this

comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several

different combinations of input change.

Two important properties of the analog comparator’s dynamic behavior are: hysteresis and propagation delay. Both of

these parameters may be adjusted in order to achieve the optimal operation for each application.

The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler.

The analog comparator output state can also be output on a pin for use by external devices.

A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,

external resistors used to charge capacitors in capacitive touch sensing applications.

The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and

analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be

set in window mode to compare a signal to a voltage range instead of a voltage level.

PORTA has one AC pair. Notation is ACA.

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Figure 30-1. Analog comparator overview.

Pin Input

AC0OUT

Pin Input

Hysteresis

DAC

Enable

Interrupt

Interrupts

Events

Interrupt

Mode

Sensititivity

Control

&

Voltage

Scaler

ACnMUXCTRL

ACnCTRL

WINCTRL

Window

Function

Enable

Bandgap

Hysteresis

Pin Input

AC1OUT

Pin Input

The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in

Figure 30-2.

Figure 30-2. Analog comparator window function.

+

AC0

Upper limit of window

-

Interrupts

Interrupt

Input signal

sensitivity

Events

control

+

AC1

Lower limit of window

-

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31. Programming and Debugging

31.1 Features

z

Programming

z External programming through PDI interface

z

Minimal protocol overhead for fast operation

z

Built-in error detection and handling for reliable operation

z Boot loader support for programming through any communication interface

z

Debugging

z Nonintrusive, real-time, on-chip debug system

z No software or hardware resources required from device except pin connection

z Program flow control

z

Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor

z Unlimited number of user program breakpoints

z Unlimited number of user data breakpoints, break on:

z

Data location read, write, or both read and write

Data location content equal or not equal to a value

Data location content is greater or smaller than a value

Data location content is within or outside a range

z No limitation on device clock frequency

z

Program and Debug Interface (PDI)

z Two-pin interface for external programming and debugging

z Uses the Reset pin and a dedicated pin

z No I/O pins required during programming or debugging

31.2 Overview

The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip

debugging of a device.

The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the

user signature row.

Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any

software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete

program flow control and support for an unlimited number of program and complex data breakpoints. Application

debug can be done from a C or other high-level language source code level, as well as from an assembler and

disassembler level.

Programming and debugging can be done through the PDI physical layer. This is a two-pin interface that uses the

Reset pin for the clock input (PDI_CLK) and one other dedicated pin for data input and output (PDI_DATA). Any

external programmer or on-chip debugger/emulator can be directly connected to this interface.

32. Pinout and Pin Functions

The device pinout is shown in “Pinout/Block Diagram” on page 4. In addition to general purpose I/O functionality, each

pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual

pin. Only one of the pin functions can be used at time.

32.1 Alternate Pin Function Description

The tables below show the notation for all pin functions available and describe its function.

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32.1.1 Operation/Power Supply

V_CC

Digital supply voltage

AV_CC

GND

Analog supply voltage

Ground

32.1.2 Port Interrupt functions

SYNC

Port pin with full synchronous and limited asynchronous interrupt function

Port pin with full synchronous and full asynchronous interrupt function

ASYNC

32.1.3 Analog functions

ACn

Analog Comparator input pin n

ACnOUT

ADCn

DACn

A_REF

Analog Comparator n Output

Analog to Digital Converter input pin n

Digital to Analog Converter output pin n

Analog Reference input pin

32.1.4 Timer/Counter and AWEX functions

OCnxLS

OCnxHS

Output Compare Channel x Low Side for Timer/Counter n

Output Compare Channel x High Side for Timer/Counter n

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32.1.5 Communication functions

SCL

Serial Clock for TWI

SDA

Serial Data for TWI

SCLIN

SCLOUT

SDAIN

SDAOUT

XCKn

RXDn

TXDn

SS

Serial Clock In for TWI when external driver interface is enabled

Serial Clock Out for TWI when external driver interface is enabled

Serial Data In for TWI when external driver interface is enabled

Serial Data Out for TWI when external driver interface is enabled

Transfer Clock for USART n

Receiver Data for USART n

Transmitter Data for USART n

Slave Select for SPI

MOSI

MISO

SCK

Master Out Slave In for SPI

Master In Slave Out for SPI

Serial Clock for SPI

D-

Data- for USB

D+

Data+ for USB

32.1.6 Oscillators, Clock and Event

TOSCn

XTALn

Timer Oscillator pin n

Input/Output for Oscillator pin n

Peripheral Clock Output

Event Channel Output

CLKOUT

EVOUT

RTCOUT

RTC Clock Source Output

32.1.7 Debug/System functions

RESET

Reset pin

PDI_CLK

PDI_DATA

Program and Debug Interface Clock pin

Program and Debug Interface Data pin

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32.2 Alternate Pin Functions

The tables below show the primary/default function for each pin on a port in the first column, the pin number in the

second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral

that enable and use the alternate pin functions.

For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under

the first table where this apply.

Table 32-1. Port A - alternate functions.

PORT A

PIN #

INTERRUPT

ADCA POS/

GAINPOS

ADCA NEG

ADCA

GAINNEG

ACA POS

ACA NEG

ACAOUT

REFA

GND

AVCC

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

38

39

40

41

42

43

44

1

SYNC

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

ADC6

ADC7

ADC0

ADC1

ADC2

ADC3

AC0

AC1

AC2

AC3

AC4

AC5

AC6

AC0

AC1

AREF

SYNC/ASYNC

SYNC

AC3

AC5

AC7

SYNC

ADC4

ADC5

ADC6

ADC7

SYNC

2

SYNC

AC1OUT

AC0OUT

3

SYNC

Table 32-2. Port B - alternate functions.

PORT B

PB0

PIN #

INTERRUPT

SYNC

ADCA POS

DACB

REFB

4

5

6

7

ADC8

ADC9

AREF

PB1

SYNC

PB2

SYNC/ASYNC

SYNC

ADC10

ADC11

DAC0

DAC1

PB3

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Table 32-3. Port C - alternate functions.

PORT C

PIN #

INTERRUPT

TCC0

AWEXC

TCC1

USART

C0⁽³⁾

USART

C1

SPIC⁽⁴⁾

TWIC

w/ext

driver

CLOCKOUT

EVENTOUT

(1)(2)

(5)

(6)

GND

8

VCC

PC0

PC1

9

10

11

SYNC

OC0A

OC0B

OC0ALS

OC0AHS

SDA

SCL

SDAIN

SCLIN

XCK0

RXD0

TXD0

SYNC/

ASYNC

PC2

12

OC0C

OC0D

OC0BLS

SDAOUT

SCLOUT

PC3

PC4

PC5

PC6

PC7

13

14

15

16

17

SYNC

OC0BHS

OC0CLS

OC0CHS

OC0DLS

OC0DHS

OC1A

OC1B

SS

XCK1

RXD1

TXD1

MOSI

MISO

SCK

clk_RTC

clk_PER

EVOUT

Notes:

1. Pin mapping of all TC0 can optionally be moved to high nibble of port

2. If TC0 is configured as TC2 all eight pins can be used for PWM output.

3. Pin mapping of all USART0 can optionally be moved to high nibble of port.

4. Pins MOSI and SCK for all SPI can optionally be swapped.

5. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.

6. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.

Table 32-4. Port D - alternate functions.

PORT D

GND

VCC

PD0

PIN #

18

INTERRUPT

TCD0

TCD1

USB

USARTD0

USARTD1

SPID

CLOCKOUT

EVENTOUT

19

20

SYNC

OC0A

OC0B

OC0C

OC0D

PD1

21

XCK0

RXD0

TXD0

PD2

22

SYNC/ASYNC

SYNC

PD3

23

PD4

24

SYNC

OC1A

OC1B

SS

PD5

25

SYNC

XCK1

RXD1

TXD1

MOSI

MISO

SCK

PD6

26

SYNC

D-

PD7

27

SYNC

D+

clk_PER

EVOUT

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Table 32-5. Port E - alternate functions.

PORT E

PE0

PIN #

28

INTERRUPT

SYNC

TCE0

OC0A

OC0B

USARTE0

TWIE

SDA

SCL

PE1

29

SYNC

XCK0

GND

VCC

PE2

30

31

32

SYNC/ASYNC

SYNC

OC0C

OC0D

RXD0

TXD0

PE3

33

Table 32-6. Port R - alternate functions.

PORT R

PDI

PIN #

34

INTERRUPT

PDI

XTAL

TOSC⁽¹⁾

PDI_DATA

PDI_CLOCK

RESET

PR0

35

36

SYNC

XTAL2

XTAL1

TOSC2

TOSC1

PR1

37

Note:

1. TOSC pins can optionally be moved to PE2/PE3.

XMEGA A4U [DATASHEET]

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60

33. Peripheral Module Address Map

The address maps show the base address for each peripheral and module in Atmel AVR XMEGA A4U. For complete

register description and summary for each peripheral module, refer to the XMEGA AU manual.

Table 33-1. Peripheral module address map.

Base address

0x0000

0x0010

0x0014

0x0018

0x001C

0x0030

0x0040

0x0048

0x0050

0x0060

0x0068

0x0070

0x0078

0x0080

0x0090

0x00A0

0x00B0

0x00C0

0x00D0

0x0100

0x0180

0x01C0

0x0200

0x0380

0x0400

0x0480

0x04A0

0x04C0

0x0600

Name

GPIO

Description

General Purpose IO Registers

Virtual Port 0

VPORT0

VPORT1

VPORT2

VPORT3

CPU

Virtual Port 1

Virtual Port 2

CPU

CLK

Clock Control

SLEEP

OSC

Sleep Controller

Oscillator Control

DFLLRC32M

DFLLRC2M

PR

DFLL for the 32MHz Internal RC Oscillator

DFLL for the 2MHz RC Oscillator

Power Reduction

RST

Reset Controller

WDT

Watch-Dog Timer

MCU

MCU Control

PMIC

Programmable MUltilevel Interrupt Controller

Port Configuration

PORTCFG

AES

AES Module

CRC

CRC Module

DMA

DMA Module

EVSYS

NVM

Event System

Non Volatile Memory (NVM) Controller

Analog to Digital Converter on port A

Analog Comparator pair on port A

Real Time Counter

ADCA

ACA

RTC

TWIC

Two Wire Interface on port C

Two Wire Interface on port E

Universal Serial Bus Interface

Port A

TWIE

USB

PORTA

XMEGA A4U [DATASHEET]

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Base address

0x0620

0x0640

0x0660

0x0680

0x07E0

0x0800

0x0840

0x0880

0x0890

0x08A0

0x08B0

0x08C0

0x08F8

0x0900

0x0940

0x0990

0x09A0

0x09B0

0x09C0

0x0A00

0x0A80

0x0A90

0x0AA0

Name

PORTB

PORTC

PORTD

PORTE

PORTR

TCC0

Description

Port B

Port C

Port D

Port E

Port R

Timer/Counter 0 on port C

Timer/Counter 1 on port C

Advanced Waveform Extension on port C

High Resolution Extension on port C

USART 0 on port C

TCC1

AWEXC

HIRESC

USARTC0

USARTC1

SPIC

USART 1 on port C

Serial Peripheral Interface on port C

Infrared Communication Module

Timer/Counter 0 on port D

Timer/Counter 1 on port D

High Resolution Extension on port D

USART 0 on port D

IRCOM

TCD0

TCD1

HIRESD

USARTD0

USARTD1

SPID

USART 1 on port D

Serial Peripheral Interface on port D

Timer/Counter 0 on port E

Advanced Waveform Extensionon port E

High Resolution Extension on port E

USART 0 on port E

TCE0

AWEXE

HIRESE

USARTE0

XMEGA A4U [DATASHEET]

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62

34. Instruction Set Summary

Mnemonic

s

Operand

s

#Clock

s

Description

Operation

Flags

Arithmetic and Logic Instructions

ADD

ADC

ADIW

SUB

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add without Carry

Rd

←

Rd + Rr

Z,C,N,V,S,H

Z,C,N,V,S

Z,C,N,V,S,H

Z,C,N,V,S

Z,N,V,S

Z,C,N,V,S

Z,C,N,V,S,H

Z,N,V,S

None

1

2

1

2

1

2

1/2

Add with Carry

Rd + Rr + C

Rd + 1:Rd + K

Rd - Rr

Add Immediate to Word

Subtract without Carry

Subtract Immediate

Subtract with Carry

Subtract Immediate with Carry

Subtract Immediate from Word

Logical AND

SUBI

SBC

Rd - K

Rd - Rr - C

Rd - K - C

Rd + 1:Rd - K

Rd • Rr

SBCI

SBIW

AND

ANDI

OR

Rd + 1:Rd

Rd

Logical AND with Immediate

Logical OR

Rd

Rd • K

Rd

Rd v Rr

ORI

Logical OR with Immediate

Exclusive OR

Rd

Rd v K

EOR

COM

NEG

SBR

Rd

Rd ⊕ Rr

One’s Complement

Two’s Complement

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd

$FF - Rd

Rd

$00 - Rd

Rd,K

Rd

Rd v K

CBR

INC

Rd

Rd • ($FFh - K)

Rd + 1

Rd

DEC

TST

Rd

Decrement

Rd

Rd - 1

Rd

Test for Zero or Minus

Clear Register

Rd

Rd • Rd

CLR

Rd

Rd ⊕ Rd

SER

Rd

Set Register

Rd

$FF

MUL

MULS

MULSU

FMUL

FMULS

FMULSU

DES

Rd,Rr

K

Multiply Unsigned

R1:R0

Rd x Rr (UU)

Rd x Rr (SS)

Rd x Rr (SU)

Rd x Rr<<1 (UU)

Rd x Rr<<1 (SS)

Rd x Rr<<1 (SU)

Z,C

Multiply Signed

Z,C

Multiply Signed with Unsigned

Fractional Multiply Unsigned

Fractional Multiply Signed

Fractional Multiply Signed with Unsigned

Data Encryption

Z,C

if (H = 0) then R15:R0

else if (H = 1) then R15:R0

←

Encrypt(R15:R0, K)

Decrypt(R15:R0, K)

Branch instructions

RJMP

IJMP

k

Relative Jump

PC

←

PC + k + 1

None

2

Indirect Jump to (Z)

PC(15:0)

PC(21:16)

←

Z,

0

EIJMP

JMP

Extended Indirect Jump to (Z)

Jump

PC(15:0)

PC(21:16)

←

Z,

EIND

None

2

3

PC

←

k

XMEGA A4U [DATASHEET]

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63

Mnemonic

s

Operand

s

#Clock

s

Description

Operation

Flags

None

RCALL

ICALL

k

Relative Call Subroutine

Indirect Call to (Z)

PC

←

PC + k + 1

2 / 3 ⁽¹⁾

PC(15:0)

PC(21:16)

←

Z,

0

EICALL

Extended Indirect Call to (Z)

PC(15:0)

PC(21:16)

←

Z,

EIND

None

3 ⁽¹⁾

CALL

RET

k

call Subroutine

PC

←

k

None

I

3 / 4 ⁽¹⁾

4 / 5 ⁽¹⁾

1 / 2 / 3

1

Subroutine Return

STACK

PC + 2 or 3

RETI

Interrupt Return

PC

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC

None

Z,C,N,V,S,H

None

Rd,Rr

Rd - Rr

CPC

Rd,Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd,K

Compare with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b) = 0) PC

if (Rr(b) = 1) PC

if (I/O(A,b) = 0) PC

If (I/O(A,b) =1) PC

if (SREG(s) = 1) then PC

if (SREG(s) = 0) then PC

if (Z = 1) then PC

if (Z = 0) then PC

if (C = 1) then PC

if (C = 0) then PC

if (C = 1) then PC

if (N = 1) then PC

if (N = 0) then PC

if (N ⊕ V= 0) then PC

if (N ⊕ V= 1) then PC

if (H = 1) then PC

if (H = 0) then PC

if (T = 1) then PC

if (T = 0) then PC

if (V = 1) then PC

if (V = 0) then PC

if (I = 1) then PC

if (I = 0) then PC

←

PC + 2 or 3

PC + k + 1

1 / 2 / 3

2 / 3 / 4

1 / 2

Rr, b

A, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

1 / 2

k

Branch if Not Equal

1 / 2

k

Branch if Carry Set

1 / 2

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

1 / 2

k

1 / 2

k

1 / 2

k

Branch if Minus

1 / 2

k

Branch if Plus

1 / 2

k

Branch if Greater or Equal, Signed

Branch if Less Than, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

k

1 / 2

Data transfer instructions

MOV

Rd, Rr

Copy Register

Rd

←

Rr

None

1

XMEGA A4U [DATASHEET]

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Mnemonic

s

Operand

s

#Clock

s

Description

Operation

Flags

None

MOVW

LDI

Rd, Rr

Rd, K

Rd, k

Copy Register Pair

Load Immediate

Rd+1:Rd

←

Rr+1:Rr

1

Rd

K

1

LDS

LD

Load Direct from data space

Load Indirect

(k)

(X)

2 ⁽¹⁾⁽²⁾

1 ⁽¹⁾⁽²⁾

Rd, X

Rd, X+

LD

Load Indirect and Post-Increment

Rd

X

←

(X)

X + 1

LD

Rd, -X

Load Indirect and Pre-Decrement

X ← X - 1,

Rd ← (X)

←

X - 1

(X)

None

2 ⁽¹⁾⁽²⁾

LD

Rd, Y

Load Indirect

Rd ← (Y)

←

(Y)

None

1 ⁽¹⁾⁽²⁾

Rd, Y+

Load Indirect and Post-Increment

Rd

Y

←

(Y)

Y + 1

LD

Rd, -Y

Load Indirect and Pre-Decrement

Y

Rd

←

Y - 1

(Y)

None

2 ⁽¹⁾⁽²⁾

LDD

LD

Rd, Y+q

Rd, Z

Load Indirect with Displacement

Load Indirect

Rd

←

(Y + q)

(Z)

None

2 ⁽¹⁾⁽²⁾

1 ⁽¹⁾⁽²⁾

LD

Rd, Z+

Load Indirect and Post-Increment

Rd

Z

←

(Z),

Z+1

LD

Rd, -Z

Load Indirect and Pre-Decrement

Z

Rd

←

Z - 1,

(Z)

None

2 ⁽¹⁾⁽²⁾

LDD

STS

ST

Rd, Z+q

k, Rr

Load Indirect with Displacement

Store Direct to Data Space

Store Indirect

Rd

(k)

(X)

←

(Z + q)

Rd

None

2 ⁽¹⁾⁽²⁾

2 ⁽¹⁾

X, Rr

Rr

1 ⁽¹⁾

ST

X+, Rr

Store Indirect and Post-Increment

(X)

X

←

Rr,

X + 1

1 ⁽¹⁾

ST

-X, Rr

Store Indirect and Pre-Decrement

X

(X)

←

X - 1,

Rr

None

2 ⁽¹⁾

ST

Y, Rr

Store Indirect

(Y)

←

Rr

None

1 ⁽¹⁾

Y+, Rr

Store Indirect and Post-Increment

(Y)

Y

←

Rr,

Y + 1

ST

-Y, Rr

Store Indirect and Pre-Decrement

Y

(Y)

←

Y - 1,

Rr

None

2 ⁽¹⁾

STD

ST

Y+q, Rr

Z, Rr

Store Indirect with Displacement

Store Indirect

(Y + q)

(Z)

←

Rr

None

2 ⁽¹⁾

1 ⁽¹⁾

ST

Z+, Rr

Store Indirect and Post-Increment

(Z)

Z

←

Rr

Z + 1

ST

-Z, Rr

Store Indirect and Pre-Decrement

Store Indirect with Displacement

Load Program Memory

Z

(Z + q)

R0

←

Z - 1

Rr

None

2 ⁽¹⁾

3

STD

LPM

Z+q,Rr

(Z)

Rd, Z

Load Program Memory

Rd

(Z)

3

Rd, Z+

Load Program Memory and Post-Increment

Rd

Z

←

(Z),

Z + 1

3

ELPM

Extended Load Program Memory

R0

Rd

←

(RAMPZ:Z)

None

3

Rd, Z

XMEGA A4U [DATASHEET]

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Mnemonic

s

Operand

s

#Clock

s

Description

Operation

Flags

ELPM

Rd, Z+

Extended Load Program Memory and Post-

Increment

Rd

Z

←

(RAMPZ:Z),

Z + 1

None

3

SPM

Store Program Memory

(RAMPZ:Z)

←

R1:R0

None

-

Z+

Store Program Memory and Post-Increment

by 2

(RAMPZ:Z)

Z

←

R1:R0,

Z + 2

IN

Rd, A

A, Rr

Rr

In From I/O Location

Out To I/O Location

Rd

I/O(A)

STACK

Rd

←

I/O(A)

Rr

None

1

OUT

PUSH

POP

XCH

Push Register on Stack

Pop Register from Stack

Exchange RAM location

Rr

1 ⁽¹⁾

2 ⁽¹⁾

2

Rd

STACK

Z, Rd

Temp

Rd

(Z)

←

Rd,

(Z),

Temp

LAS

LAC

LAT

Z, Rd

Load and Set RAM location

Load and Clear RAM location

Load and Toggle RAM location

Temp

Rd

(Z)

←

Rd,

(Z),

Temp v (Z)

None

2

Temp

Rd

(Z)

←

Rd,

(Z),

($FFh – Rd) z (Z)

Temp

Rd

(Z)

←

Rd,

(Z),

Temp ⊕ (Z)

Bit and bit-test instructions

LSL

Rd

Logical Shift Left

Rd(n+1)

Rd(0)

C

←

Rd(n),

0,

Rd(7)

Z,C,N,V,H

Z,C,N,V

1

LSR

ROL

ROR

Logical Shift Right

Rd(n)

Rd(7)

C

←

Rd(n+1),

0,

Rd(0)

Rotate Left Through Carry

Rotate Right Through Carry

Rd(0)

Rd(n+1)

C

←

C,

Rd(n),

Rd(7)

Z,C,N,V,H

Z,C,N,V

Rd(7)

Rd(n)

C

←

C,

Rd(n+1),

Rd(0)

ASR

SWAP

BSET

BCLR

SBI

Rd

Arithmetic Shift Right

Swap Nibbles

Rd(n)

←

↔

←

Rd(n+1), n=0..6

Z,C,N,V

1

Rd

Rd(3..0)

Rd(7..4)

None

s

Flag Set

SREG(s)

1

SREG(s)

s

Flag Clear

SREG(s)

0

SREG(s)

A, b

Rr, b

Rd, b

Set Bit in I/O Register

Clear Bit in I/O Register

Bit Store from Register to T

Bit load from T to Register

Set Carry

I/O(A, b)

1

None

T

CBI

I/O(A, b)

0

BST

BLD

SEC

CLC

SEN

CLN

SEZ

T

Rr(b)

Rd(b)

T

1

0

1

0

1

None

C

N

Z

Clear Carry

C

Set Negative Flag

Clear Negative Flag

Set Zero Flag

N

Z

XMEGA A4U [DATASHEET]

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66

Mnemonic

s

Operand

s

#Clock

s

Description

Operation

Flags

CLZ

SEI

Clear Zero Flag

Z

I

←

0

1

0

1

0

1

0

1

0

1

0

Z

I

1

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

CLI

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S

V

T

H

S

V

T

H

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

Clear T in SREG

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

MCU control instructions

BREAK

NOP

Break

(See specific descr. for BREAK)

None

1

No Operation

Sleep

SLEEP

WDR

(see specific descr. for Sleep)

(see specific descr. for WDR)

Watchdog Reset

Notes:

1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.

2. One extra cycle must be added when accessing Internal SRAM.

XMEGA A4U [DATASHEET]

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67

35. Packaging information

35.1 44A

PIN 1 IDENTIFIER

PIN 1

e

B

E1

E

D1

D

C

0°~7°

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

NOM

–

NOTE

SYMBOL

A

A1

A2

D

0.05

0.95

11.75

9.90

11.75

9.90

0.30

0.09

0.45

–

0.15

1.00

1.05

12.00

10.00

12.00

10.00

0.37

12.25

D1

E

10.10 Note 2

12.25

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ACB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

10.10 Note 2

0.45

C

(0.17)

0.60

0.20

3. Lead coplanarity is 0.10mm maximum.

L

0.75

e

0.80 TYP

06/02/2014

44A, 44-lead, 10 x 10mm body size, 1.0mm body thickness,

0.8 mm lead pitch, thin profile plastic quad flat package (TQFP)

44A

C

XMEGA A4U [DATASHEET]

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68

35.2 PW

XMEGA A4U [DATASHEET]

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69

35.3 44M1

D

Marked Pin# 1 I D

E

SE ATING PLAN

E

A1

A3

TOP VIE W

A

K

L

Pin #1 Co rner

SIDE VIEW

D2

Pin #1

Triangle

Option A

COMMON DIMENSIONS

(Unit of Measure = mm)

1

2

3

MIN

0.80

–

MAX

1.00

0.05

NOM

0.90

NOTE

SYMBOL

A

E2

Option B

Option C

A1

A3

b

0.02

Pin #1

Cham fer

(C 0.30)

0.20 REF

0.23

0.18

6.90

5.00

6.90

0.30

7.10

5.40

7.10

D

7.00

D2

E

5.20

K

Pin #1

Notch

(0.20 R)

e

b

7.00

E2

e

5.00

5.20

0.50 BSC

0.64

5.40

B OTTOM VIE W

L

0.59

0.20

0.69

0.41

Note: JEDEC Standard MO-220, Fig

. 1 (S AW Singulation) VKKD-3 .

K

0.26

02/13/2014

GPC

ZWS

DRAWING NO.

TITLE

REV.

44M1, 44-pad, 7 x 7 x 1.0mm body, lead

pitch 0.50mm, 5.20mm exposed pad, thermally

enhanced plastic very thin quad flat no

lead package (VQFN)

Package Drawing Contact:

packagedrawings@atmel.com

44M1

H

XMEGA A4U [DATASHEET]

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70

35.4 49C2

E

A1 BALL ID

0.10

D

A1

A2

TOP VIEW

A

SIDE VIEW

E1

G

F

e

E

D

C

B

A

D1

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.00

–

NOM

–

NOTE

SYMBOL

A

1

2

3

4

5

6

7

A1

A2

D

0.20

0.65

4.90

–

A1 BALL CORNER

49 - Ø0.35 0.05

b

e

–

5.00

5.10

BOTTOM VIEW

D1

E4.90

E1

b

3.90 BSC

5.10

5.00

0.30

3.90 BSC

0.35

0.40

e

0.65 BSC

3/14/08

GPC

CBD

DRAWING NO.

TITLE

REV.

49C2, 49-ball (7 x 7 array), 0.65mm pitch,

5.0 x 5.0 x 1.0mm, very thin, ﬁne-pitch

ball grid array package (VFBGA)

Package Drawing Contact:

packagedrawings@atmel.com

49C2

A

XMEGA A4U [DATASHEET]

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36. Electrical Characteristics

All typical values are measured at T = 25°C unless other temperature condition is given. All minimum and maximum

values are valid across operating temperature and voltage unless other conditions are given.

36.1 ATxmega16A4U

36.1.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 36-1 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or other conditions beyond those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 36-1. Absolute maximum ratings.

Symbol

V_CC

I_VCC

I_GND

V_PIN

I_PIN

Parameter

Condition

Min.

Typ.

Max.

4

Units

V

Power supply voltage

Current into a V_CCpin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V_CC

I/O pin sink/source current

Storage temperature

-0.3

200

mA

V

200

-0.5

-25

-65

V_CC+0.5

25

mA

°C

T_A

150

T_j

Junction temperature

150

°C

36.1.2 General Operating Ratings

The device must operate within the ratings listed in Table 36-2 in order for all other electrical characteristics and

typical characteristics of the device to be valid.

Table 36-2. General operating conditions.

Symbol

V_CC

Parameter

Condition

Min.

1.60

-40

Typ.

Max.

3.6

Units

V

Power supply voltage

Analog supply voltage

Temperature range

Junction temperature

AV_CC

T_A

3.6

V

85

°C

T_j

-40

105

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Table 36-3. Operating voltage and frequency.

Symbol

Parameter

Condition

V_CC= 1.6V

V_CC= 1.8V

V_CC= 2.7V

V_CC= 3.6V

Min.

Typ.

Max.

12

Units

0

12

Clk_CPU

CPU clock frequency

MHz

32

The maximum CPU clock frequency depends on V_CC. As shown in Figure 36-1 the Frequency vs. V_CCcurve is linear

between 1.8V < V_CC< 2.7V.

Figure 36-1. Maximum Frequency vs. V_CC

.

MHz

32

Safe Operating Area

12

V

1.6

1.8

2.7

3.6

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36.1.3 Current consumption

Table 36-4. Current consumption for Active mode and sleep modes.

Symbol Parameter

Condition

Min.

Typ.

40

Max.

Units

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

32kHz, Ext. Clk

80

230

480

430

0.9

9.6

2.4

3.9

62

µA

1MHz, Ext. Clk

Active power

consumption ⁽¹⁾

600

1.4

12

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

V_CC= 3.0V

mA

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

1MHz, Ext. Clk

2MHz, Ext. Clk

µA

Idle power

118

125

240

3.8

0.1

1.2

3.5

consumption ⁽¹⁾

225

350

5.5

1.0

4.5

6.0

V_CC= 3.0V

32MHz, Ext. Clk

T = 25°C

mA

I_CC

T = 85°C

V_CC= 3.0V

T = 105°C

WDT and Sampled BOD enabled,

T = 25°C

Power-down power

consumption

1.3

2.4

4.5

3.0

6.0

8.0

µA

WDT and Sampled BOD enabled,

T = 85°C

V_CC= 3.0V

WDT and Sampled BOD enabled,

T = 105°C

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

1.2

1.3

0.6

0.7

0.8

1.0

320

RTC from ULP clock, WDT and sampled

BOD enabled, T = 25°C

2.0

3.0

Power-save power

consumption ⁽²⁾

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

µA

RTC from low power 32.768kHz TOSC,

T = 25°C

Reset power consumption Current through RESET pin substracted

Notes:

1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

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Table 36-5. Current consumption for modules and peripherals.

Symbol Parameter

Condition ⁽¹⁾

Min.

Typ.

1.0

27

Max.

Units

µA

ULP oscillator

32.768kHz int. oscillator

µA

85

2MHz int. oscillator

32MHz int. oscillator

µA

DFLL enabled with 32.768kHz int. osc. as reference

115

270

460

20x multiplication factor,

PLL

220

µA

32MHz int. osc. DIV4 as reference

Watchdog timer

1.0

138

1.2

100

95

Continuous mode

BOD

µA

Sampled mode, includes ULP oscillator

Internal 1.0V reference

Temperature sensor

µA

I_CC

3.0

2.6

2.1

1.6

1.9

CURRLIMIT = LOW

250ksps

ADC

mA

V_REF= Ext ref

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

250ksps

Normal mode

DAC

AC

V_REF= Ext ref

No load

mA

µA

Low Power mode

1.1

High speed mode

Low power mode

330

130

108

16

DMA

615kbps between I/O registers and SRAM

µA

mA

Timer/counter

USART

Rx and Tx enabled, 9600 BAUD

2.5

4.0

Flash memory and EEPROM programming

8.0

Note:

1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V_CC= 3.0V, Clk_SYS= 1MHz external

clock without prescaling, T = 25°C unless other conditions are given.

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36.1.4 Wake-up time from sleep modes

Table 36-6. Device wake-up time from sleep modes with various system clock sources.

Symbol Parameter

Condition

External 2MHz clock

Min.

Typ. ⁽¹⁾

2.0

Max.

Units

Wake-up time from idle,

standby, and extended standby

mode

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

External 2MHz clock

120

2.0

0.2

t_wakeup

µs

4.5

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

320

9.0

Wake-up time from power-save

and power-down mode

5.0

Note:

1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2. All peripherals and modules

start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-2. Wake-up time definition.

Wakeup time

Wakeup request

Clock output

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36.1.5 I/O Pin Characteristics

The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 36-7. I/O pin characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

(1)

I_OH

I_OL

/

I/O pin source/sink current

-20

20

mA

(2)

V_CC= 2.7 - 3.6V

2.0

0.7*V_CC

0.8*V_CC

-0.3

V_CC+0.3

0.8

V_IH

High level input voltage

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 2.7- 3.6V

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 3.0 - 3.6V

V

V_IL

Low level input voltage

-0.3

0.3*V_CC

0.2*V_CC

-0.3

I_OH= -2mA

I_OH= -1mA

I_OH= -2mA

I_OH= -8mA

I_OH= -6mA

I_OH= -2mA

I_OL= 2mA

I_OL= 1mA

I_OL= 2mA

I_OL= 15mA

I_OL= 10mA

I_OL= 5mA

2.4

0.94*V_CC

0.96*V_CC

0.92*V_CC

2.9

2.0

V_CC= 2.3 - 2.7V

1.7

V_OH

High level output voltage

V

V_CC= 3.3V

2.6

V_CC= 3.0V

2.1

2.6

V_CC= 1.8V

1.4

1.6

V_CC= 3.0 - 3.6V

0.05*V_CC

0.03*V_CC

0.06*V_CC

0.4

V_CC= 2.3 - 2.7V

0.7

V_OL

Low level output voltage

V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 1.8V

T = 25°C

0.76

0.64

0.46

0.1

0.3

0.2

I_IN

Input leakage current

<0.01

24

µA

R_P

Pull/buss keeper resistor

kΩ

4.0

t_r

Rise time

No load

ns

slew rate limitation

7.0

Notes:

1. The sum of all I_OHfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OHfor PORTC must not exceed 200mA.

The sum of all I_OHfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OHfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

2. The sum of all I_OLfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OLfor PORTC must not exceed 200mA.

The sum of all I_OLfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OLfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

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36.1.6 ADC characteristics

Table 36-8. Power supply, reference and input range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1.0

Typ.

Max.

Units

V

AV_CC

V_REF

Analog supply voltage

Reference voltage

V_CC+ 0.3

AV_CC- 0.6

V

R_in

C_sample

R_AREF

C_AREF

V_IN

Input resistance

Switched

4.0

4.4

>10

7.0

kΩ

pF

MΩ

pF

V

Input capacitance

Switched

Reference input resistance

(leakage only)

Reference input capacitance Static load

Input range

-0.1

-V_REF

-ΔV

AV_CC+0.1

V_REF

Conversion range

Fixed offset voltage

Differential mode, Vinp - Vinn

V

Single ended unsigned mode, Vinp

V_REF-ΔV

V

∆V

190

LSB

Table 36-9. Clock and timing.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Maximum is 1/4 of peripheral clock

frequency

100

2000

Clk_ADC

ADC Clock frequency

kHz

Measuring internal signals

Current limitation (CURRLIMIT) off

CURRLIMIT = LOW

100

0.25

125

2000

1500

1000

500

5

f_ADC

Sample rate

ksps

µs

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

Sampling time

1/2 Clk_ADCcycle

(RES+2)/2+(GAIN !=0)

RES (Resolution) = 8 or 12

Clk_ADC

cycles

Conversion time (latency)

5

8

Clk_ADC

cycles

Start-up time

ADC clock cycles

12

24

After changing reference or input mode

After ADC flush

7

1

7

1

Clk_ADC

cycles

ADC settling time

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Table 36-10. Accuracy characteristics.

Symbol

Parameter

Condition ⁽²⁾

Min.

Typ.

12

Max.

12

Units

RES

INL ⁽¹⁾

DNL ⁽¹⁾

Resolution

Programmable to 8 or 12 bit

8

Bits

V_CC-1.0V < V_REF< V_CC-0.6V

±1.2

±1.5

±1.0

±1.5

<±0.8

-1.0

±2.0

±3.0

±2.0

±3.0

<±1.0

500ksps

All V_REF

V_CC-1.0V < V_REF< V_CC-0.6V

All V_REF

Integral non-linearity

lsb

2000ksps

Differential non-linearity

Offset error

guaranteed monotonic

lsb

mV

Temperature drift

<0.01

<0.6

-1.0

mV/K

mV/V

Operating voltage drift

External reference

AV_CC/1.6

AV_CC/2.0

Bandgap

10

Differential

mode

mV

8.0

Gain error

±5.0

<0.02

<0.5

Temperature drift

mV/K

mV/V

Operating voltage drift

Differential mode, shorted input

2msps, V_CC= 3.6V, Clk_PER= 16MHz

mV

rms

Noise

0.4

Notes:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V_REFis used.

Table 36-11. Gain stage characteristics.

Symbol

Parameter

Condition

Switched in normal mode

Gain stage output

Min.

Typ.

4.0

Max.

Units

kΩ

pF

R_in

Input resistance

Input capacitance

Signal range

C_sample

4.4

0

V_CC- 0.6

V

Clk_ADC

cycles

Propagation delay

Sample rate

ADC conversion rate

Same as ADC

500ksps

1.0

100

1000

±4

kHz

lsb

All gain

settings

INL ⁽¹⁾

Integral non-linearity

±1.5

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

-0.8

-2.5

-3.5

Gain error

%

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Symbol

Parameter

Condition

1x gain, normal mode

Min.

Typ.

-2

Max.

Units

Offset error,

input referred

8x gain, normal mode

64x gain, normal mode

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

-5

mV

-4

0.5

1.5

11

V_CC= 3.6V

Ext. V_REF

mV

rms

Noise

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

36.1.7 DAC Characteristics

Table 36-12. Power supply, reference and output range.

Symbol Parameter Condition

Min.

V_CC

Typ.

Max.

Units

-

AV_CC

Analog supply voltage

V_CC+ 0.3

V

0.3

AV_REF

External reference voltage

DC output impedance

1.0

V_CC- 0.6

50

V

Ω

R_channel

Linear output voltage range

Reference input resistance

Reference input capacitance Static load

Minimum resistance load

0.15

1.0

AV_CC-0.15

V

R_AREF

>10

7

MΩ

pF

kΩ

pF

nF

CAREF

100

1.0

Maximum capacitance load

1000Ω serial resistance

Operating within accuracy specification

Safe operation

AV_CC/1000

10

Output sink/source

mA

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Table 36-13. Clock and timing.

Symbol

Parameter

Condition

Normal mode

Low power mode

Min.

Typ.

Max.

1000

500

Units

0

C_load=100pF,

maximum step size

f_DAC

Conversion rate

ksps

Table 36-14. Accuracy characteristics.

Symbol

Parameter

Condition

Min.

Typ.

Max.

12

Units

RES

Input resolution

Bits

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

±2.0

±1.5

±2.0

±1.5

±5.0

±1.5

±0.6

±1.0

±0.6

±4.5

<4.0

4.0

±3

V_REF= Ext 1.0V

V_REF=AV_CC

±2.5

±4

INL ⁽¹⁾

Integral non-linearity

lsb

±4

V_REF=INT1V

V_REF=Ext 1.0V

V_REF=AV_CC

3.0

1.5

3.5

1.5

DNL ⁽¹⁾

Differential non-linearity

lsb

V_REF=INT1V

Gain error

After calibration

lsb

Gain calibration step size

Gain calibration drift

Offset error

V_REF= Ext 1.0V

After calibration

<0.2

<1.0

1.0

mV/K

lsb

Offset calibration step size

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.

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36.1.8 Analog Comparator Characteristics

Table 36-15. Analog Comparator characteristics.

Symbol

V_off

Parameter

Condition

Min.

Typ.

<±10

<1.0

Max.

Units

mV

nA

Input offset voltage

Input leakage current

Input voltage range

AC startup time

I_lk

-0.1

AV_CC

V

100

0

µs

V_hys1

Hysteresis, none

mV

mode = High Speed (HS)

mode = Low Power (LP)

mode = HS

13

V_hys2

Hysteresis, small

Hysteresis, large

mV

30

V_hys3

mode = LP

60

V_CC= 3.0V, T= 85°C

mode = HS

V_CC= 3.0V, T= 85°C

mode = HS

30

90

500

0.5

30

t_delay

Propagation delay

ns

mode = LP

130

0.3

mode = LP

64-level voltage scaler

Integral non-linearity (INL)

lsb

36.1.9 Bandgap and Internal 1.0V Reference Characteristics

Table 36-16. Bandgap and Internal 1.0V reference characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

As reference for ADC or DAC

As input voltage to ADC and AC

1 Clk_PER+ 2.5µs

Startup time

µs

1.5

1.1

Bandgap voltage

V

INT1V

Internal 1.00V reference

Variation over voltage and temperature

T= 85°C, after calibration

0.99

1.0

1.01

Relative to T= 85°C, V_CC= 3.0V

±1.5

%

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36.1.10 Brownout Detection Characteristics

Table 36-17. Brownout detection characteristics.

Symbol Parameter

BOD level 0 falling V_CC

BOD level 1 falling V_CC

BOD level 2 falling V_CC

Condition

Min.

Typ.

1.62

1.8

Max.

Units

1.60

1.72

2.0

BOD level 3 falling V_CC

V_BOT

2.2

V

BOD level 4 falling V_CC

2.4

BOD level 5 falling V_CC

BOD level 6 falling V_CC

BOD level 7 falling V_CC

2.6

2.8

3.0

Continuous mode

Sampled mode

0.4

t_BOD

Detection time

Hysteresis

µs

%

1000

1.2

V_HYST

36.1.11 External Reset Characteristics

Table 36-18. External reset characteristics.

Symbol Parameter

Condition

Min.

Typ.

95

Max.

Units

t_EXT

Minimum reset pulse width

1000

ns

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

0.60×V_CC

0.50×V_CC

0.40×V_CC

25

Reset threshold voltage (V_IH)

V_RST

V

Reset threshold voltage (V_IL)

Reset pin Pull-up Resistor

R_RST

kΩ

36.1.12 Power-on Reset Characteristics

Table 36-19. Power-on reset characteristics.

Symbol Parameter

Condition

Min.

Typ.

1.0

Max.

Units

V_CCfalls faster than 1V/ms

V_CCfalls at 1V/ms or slower

0.4

0.8

(1)

V_POT-

POR threshold voltage falling V_CC

V

1.0

V_POT+

POR threshold voltage rising V_CC

1.3

1.59

Note:

1. V_POT-values are only valid when BOD is disabled. When BOD is enabled V_POT-= V_POT+.

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36.1.13 Flash and EEPROM Memory Characteristics

Table 36-20. Endurance and data retention.

Symbol Parameter

Condition

Min.

10K

2K

Typ.

Max.

Units

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

Write/Erase cycles

Cycle

Flash

100

25

Data retention

Year

Cycle

Year

10

100K

30K

100

25

Write/Erase cycles

Data retention

EEPROM

10

Table 36-21. Programming time.

Symbol Parameter

Condition

Min.

Typ.⁽¹⁾

Max.

Units

ms

16KB Flash, EEPROM⁽²⁾and

SRAM Erase

Chip Erase

45

Application Erase

Section erase

6

4

8

4

8

ms

Page erase

Flash

Page write

ms

Atomic page erase and write

Page erase

EEPROM

Page write

Atomic page erase and write

Notes:

1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

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36.1.14 Clock and Oscillator Characteristics

36.1.14.1 Calibrated 32.768kHz Internal Oscillator characteristics

Table 36-22. 32.768kHz internal oscillator characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

kHz

%

Frequency

32.768

Factory calibration accuracy

User calibration accuracy

T = 85°C, V_CC= 3.0V

-0.5

0.5

%

36.1.14.2 Calibrated 2MHz RC Internal Oscillator characteristics

Table 36-23. 2MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

1.8

2.2

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration stepsize

2.0

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.21

%

36.1.14.3 Calibrated and tunable 32MHz internal oscillator characteristics

Table 36-24. 32MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

30

55

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration step size

32

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.22

%

36.1.14.4 32kHz Internal ULP Oscillator characteristics

Table 36-25. 32kHz internal ULP oscillator characteristics.

Symbol Parameter

Output frequency

Accuracy

Condition

Min.

Typ.

Max.

Units

kHz

%

32

-30

30

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36.1.14.5 Internal Phase Locked Loop (PLL) characteristics

Table 36-26. Internal PLL characteristics.

Symbo

l

Parameter

Condition

Output frequency must be within f_OUT

V_CC= 1.6 - 1.8V

Min.

0.4

20

Typ.

Max.

64

Units

f_IN

Input frequency

MHz

48

f_OUT

Output frequency ⁽¹⁾

MHz

V_CC= 2.7 - 3.6V

20

128

Start-up time

Re-lock time

25

µs

Note:

1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.1.14.6 External clock characteristics

Figure 36-3. External clock drive waveform

t_CH

t_CR

t_CF

V_IH1

V_IL1

t_CL

t_CK

Table 36-27. External clock used as system clock without prescaling.

Symbol

Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

0

Typ.

Max.

12

Units

1/t_CK

Clock Frequency ⁽¹⁾

MHz

0

32

83.3

31.5

30.0

12.5

30.0

12.5

t_CK

t_CH

t_CL

t_CR

Clock Period

ns

Clock High Time

Clock Low Time

10

3

Rise Time (for maximum frequency)

10

3

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

10

Note:

1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

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Table 36-28. External clock with prescaler ⁽¹⁾for system clock.

Symbol Parameter Condition

Clock Frequency ⁽²⁾

Min.

0

Typ.

Max.

90

Units

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

1/t_CK

MHz

0

142

11

7

t_CK

Clock Period

ns

4.5

2.4

4.5

2.4

t_CH

Clock High Time

t_CL

Clock Low Time

1.5

1.0

1.5

1.0

10

t_CR

Rise Time (for maximum frequency)

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

Notes:

1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

36.1.14.7 External 16MHz crystal oscillator and XOSC characteristic

Table 36-29. External 16MHz crystal oscillator and XOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

<10

Max.

Units

FRQRANGE=0

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

Cycle to cycle jitter

FRQRANGE=1, 2, or 3

<1.0

ns

<1.0

FRQRANGE=0

<6.0

Long term jitter

Frequency error

FRQRANGE=1, 2, or 3

<0.5

ns

%

<0.5

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

<0.1

XOSCPWR=0

XOSCPWR=1

<0.05

<0.005

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Symbol Parameter

Condition

Min.

Typ.

40

Max.

Units

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

XOSCPWR=0

XOSCPWR=1

42

Duty cycle

%

45

48

0.4MHz resonator,

CL=100pF

2.4k

XOSCPWR=0,

FRQRANGE=0

1MHz crystal, CL=20pF

2MHz crystal, CL=20pF

2MHz crystal

8.7k

2.1k

4.2k

250

195

360

285

155

365

200

105

435

235

125

495

270

145

305

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

8MHz crystal

9MHz crystal

8MHz crystal

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

9MHz crystal

12MHz crystal

9MHz crystal

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

Negative impedance ⁽¹⁾

Ω

R_Q

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

12MHz crystal

16MHz crystal

12MHz crystal

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

16MHz crystal

12MHz crystal

16MHz crystal

160

380

205

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

ESR

SF = Safety factor

min(R_Q)/SF

kΩ

Parasitic capacitance

XTAL1 pin

C_XTAL1

C_XTAL2

C_LOAD

5.4

7.1

pF

Parasitic capacitance

XTAL2 pin

pF

Parasitic capacitance

load

3.07

Note:

1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.

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36.1.14.8 External 32.768kHz crystal oscillator and TOSC characteristics

Table 36-30. External 32.768kHz crystal oscillator and TOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

60

Units

Crystal load capacitance 6.5pF

Crystal load capacitance 9.0pF

Recommended crystal equivalent

ESR/R1

C_TOSC1

C_TOSC2

kΩ

series resistance (ESR)

35

5.4

4.0

7.1

4.0

Parasitic capacitance TOSC1 pin

pF

Alternate TOSC location

Parasitic capacitance TOSC2 pin

Recommended safety factor

Alternate TOSC location

capacitance load matched to

crystal specification

3

Note:

1. See Figure 36-4 for definition.

Figure 36-4. TOSC input capacitance.

C_L1

C_L2

Device internal

External

TOSC1

TOSC2

32.768kHz crystal

The parasitic capacitance between the TOSC pins is C_L1+ C_L2in series as seen from the crystal when oscillating

without external capacitors.

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36.1.15 SPI Characteristics

Figure 36-5. SPI timing requirements in master mode.

SS

t_MOS

t_SCKR

t_SCKF

SCK

(CPOL = 0)

t_SCKW

SCK

(CPOL = 1)

t_SCKW

t_MIS

t_MIH

t_SCK

MISO

(Data input)

MSB

LSB

t_MOH

MOSI

(Data output)

MSB

LSB

Figure 36-6. SPI timing requirements in slave mode.

SS

t_SSS

t_SCKR

t_SCKF

t_SSH

SCK

(CPOL = 0)

t_SSCKW

SCK

(CPOL = 1)

t_SSCKW

t_SIS

t_SIH

t_SSCK

MOSI

(Data input)

MSB

LSB

t_SOSSS

t_SOS

t_SOSSH

MISO

(Data output)

MSB

LSB

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Table 36-31. SPI timing characteristics and requirements.

Symbol Parameter Condition

Min.

Typ.

Max.

Units

(See Table 21-4 in

XMEGA AU Manual)

t_SCK

SCK period

Master

t_SCKW

t_SCKR

t_SCKF

t_MIS

SCK high/low width

SCK rise time

Master

Slave

0.5*SCK

2.7

SCK fall time

MISO setup to SCK

MISO hold after SCK

MOSI setup SCK

MOSI hold after SCK

Slave SCK Period

SCK high/low width

SCK rise time

10

t_MIH

10

t_MOS

t_MOH

t_SSCK

t_SSCKW

t_SSCKR

t_SSCKF

t_SIS

0.5*SCK

1

4*t Clk_PER

2*t Clk_PER

ns

1600

SCK fall time

MOSI setup to SCK

MOSI hold after SCK

SS setup to SCK

SS hold after SCK

MISO setup SCK

MISO hold after SCK

MISO setup after SS low

MISO hold after SS high

3

t Clk_PER

21

t_SIH

t_SSS

t_SSH

20

t_SOS

8

13

11

8

t_SOH

t_SOSS

t_SOSH

36.1.16 Two-Wire Interface Characteristics

Table 36-32 on page 92 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel

AVR XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols

refer to Figure 36-7 on page 91.

Figure 36-7. Two-wire interface bus timing.

t_of

t_HIGH

t_LOW

t_r

SCL

SDA

t_HD;DAT

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;STA

t_BUF

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Table 36-32. Two-wire interface characteristics.

Symbol Parameter

Condition

Min.

0.7*V_CC

0.5

Typ.

Max.

Units

V

V_IH

V_IL

Input high voltage

V_CC+0.5

0.3*V_CC

Input low voltage

V

(1)

V_hys

Hysteresis of Schmitt trigger inputs

Output low voltage

0.05*V_CC

0

V

V_OL

3mA, sink current

0.4

300

250

50

V

(1)(2)

t_r

t_of

Rise time for both SDA and SCL

Output fall time from V_IHminto V_ILmax

Spikes suppressed by input filter

Input current for each I/O Pin

Capacitance for each I/O Pin

SCL clock frequency

20+0.1C_b

0

ns

µA

pF

kHz

(1)(2)

10pF < C_b< 400pF ⁽²⁾

0.1V_CC< V_I< 0.9V_CC

t_SP

I_I

-10

10

C_I

10

f_SCL

f_PER⁽³⁾>max(10f_SCL, 250kHz)

0

400

f_SCL≤ 100kHz

100ns

C_b

--------------

V_CC– 0.4V

---------------------------

3mA

R_P

Value of pull-up resistor

Ω

300ns

f_SCL> 100kHz

--------------

C_b

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

0

t_HD;STA

Hold time (repeated) START condition

Low period of SCL clock

µs

ns

µs

t_LOW

t_HIGH

High period of SCL clock

Set-up time for a repeated START

condition

t_SU;STA

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

3.45

0.9

Data hold time

0

250

100

4.0

0.6

4.7

1.3

Data setup time

Setup time for STOP condition

Bus free time between a STOP and

START condition

Notes:

1. Required only for f_SCL> 100kHz.

2. C_b= Capacitance of one bus line in pF.

3.

f_PER= Peripheral clock frequency.

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36.2 ATxmega32A4U

36.2.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 36-33 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or other conditions beyond those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 36-33. Absolute maximum ratings.

Symbol

V_CC

I_VCC

I_GND

V_PIN

I_PIN

Parameter

Condition

Min.

Typ.

Max.

4

Units

V

Power supply voltage

Current into a V_CCpin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V_CC

I/O pin sink/source current

Storage temperature

-0.3

200

mA

V

200

-0.5

-25

-65

V_CC+0.5

25

mA

°C

T_A

150

T_j

Junction temperature

150

°C

36.2.2 General Operating Ratings

The device must operate within the ratings listed in Table 36-34 in order for all other electrical characteristics and

typical characteristics of the device to be valid.

Table 36-34. General operating conditions.

Symbol

V_CC

Parameter

Condition

Min.

1.60

-40

Typ.

Max.

3.6

Units

V

Power supply voltage

Analog supply voltage

Temperature range

Junction temperature

AV_CC

T_A

3.6

V

85

°C

T_j

-40

105

Table 36-35. Operating voltage and frequency.

Symbol

Parameter

Condition

V_CC= 1.6V

V_CC= 1.8V

V_CC= 2.7V

V_CC= 3.6V

Min.

Typ.

Max.

12

Units

0

12

Clk_CPU

CPU clock frequency

MHz

32

The maximum CPU clock frequency depends on V_CC. As shown in Figure 36-8 the Frequency vs. V_CCcurve is linear

between 1.8V < V_CC< 2.7V.

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Figure 36-8. Maximum Frequency vs. V_CC

.

MHz

32

Safe Operating Area

12

V

1.6

1.8

2.7

3.6

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36.2.3 Current consumption

Table 36-36. Current consumption for Active mode and sleep modes.

Symbol Parameter

Condition

Min.

Typ.

40

Max.

Units

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

32kHz, Ext. Clk

80

230

480

430

0.9

9.6

2.4

3.9

62

µA

1MHz, Ext. Clk

Active power

consumption⁽¹⁾

600

1.4

12

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

V_CC= 3.0V

mA

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

1MHz, Ext. Clk

2MHz, Ext. Clk

µA

Idle power

consumption⁽¹⁾

118

125

240

3.8

0.1

1.2

3.5

225

350

5.5

1.0

4.5

6.0

V_CC= 3.0V

32MHz, Ext. Clk

T = 25°C

mA

I_CC

T = 85°C

V_CC= 3.0V

T = 105°C

WDT and sampled BOD enabled,

T = 25°C

Power-down power

consumption

1.3

2.4

4.5

3.0

6.0

8.0

µA

WDT and sampled BOD enabled,

T = 85°C

V_CC= 3.0V

WDT and sampled BOD enabled,

T = 105°C

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

1.2

1.3

0.6

0.7

0.8

1.0

RTC from ULP clock, WDT and

sampled BOD enabled, T = 25°C

2.0

3.0

Power-save power

consumption⁽²⁾

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

µA

RTC from low power 32.768kHz

TOSC, T = 25°C

Current through RESET pin

substracted

Reset power consumption

V_CC= 3.0V

320

Notes:

1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

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Table 36-37. Current consumption for modules and peripherals.

Symbol Parameter

Condition ⁽¹⁾

Min.

Typ.

1.0

27

Max.

Units

µA

ULP oscillator

32.768kHz int. oscillator

µA

85

2MHz int. oscillator

32MHz int. oscillator

µA

DFLL enabled with 32.768kHz int. osc. as reference

115

270

460

20x multiplication factor,

PLL

220

µA

32MHz int. osc. DIV4 as reference

Watchdog timer

1.0

138

1.2

100

95

Continuous mode

BOD

µA

Sampled mode, includes ULP oscillator

Internal 1.0V reference

Temperature sensor

µA

I_CC

3.0

2.6

2.1

1.6

1.9

CURRLIMIT = LOW

250ksps

ADC

mA

V_REF= Ext ref

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

250ksps

Normal mode

DAC

AC

V_REF= Ext ref

No load

mA

µA

Low power mode

1.1

High speed mode

Low power mode

330

130

108

16

DMA

615kbps between I/O registers and SRAM

µA

mA

Timer/counter

USART

Rx and Tx enabled, 9600 BAUD

2.5

4.0

Flash memory and EEPROM programming

8.0

Note:

1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V_CC= 3.0V, Clk_SYS= 1MHz external

clock without prescaling, T = 25°C unless other conditions are given.

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36.2.4 Wake-up time from sleep modes

Table 36-38. Device wake-up time from sleep modes with various system clock sources.

Symbol Parameter

Condition

External 2MHz clock

Min.

Typ. ⁽¹⁾

2.0

Max.

Units

Wake-up time from idle,

standby, and extended standby

mode

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

External 2MHz clock

120

2.0

µs

0.2

t_wakeup

4.5

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

320

9.0

Wake-up time from power-save

and power-down mode

µs

5.0

Note:

1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-9. All peripherals and modules

start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-9. Wake-up time definition.

Wakeup time

Wakeup request

Clock output

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36.2.5 I/O Pin Characteristics

The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 36-39. I/O pin characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

(1)

I_OH

/

I/O pin source/sink current

-20

20

mA

(2)

I_OL

V_CC= 2.7 - 3.6V

2.0

0.7*V_CC

0.8*V_CC

-0.3

V_CC+0.3

0.8

V_IH

High level input voltage

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 2.7- 3.6V

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 3.0 - 3.6V

V

V_IL

Low level input voltage

-0.3

0.3*V_CC

0.2*V_CC

-0.3

I_OH= -2mA

I_OH= -1mA

I_OH= -2mA

I_OH= -8mA

I_OH= -6mA

I_OH= -2mA

I_OL= 2mA

I_OL= 1mA

I_OL= 2mA

I_OL= 15mA

I_OL= 10mA

I_OL= 5mA

2.4

0.94*V_CC

0.96*V_CC

0.92*V_CC

2.9

2.0

V_CC= 2.3 - 2.7V

1.7

V_OH

High level output voltage

V

V_CC= 3.3V

2.6

V_CC= 3.0V

2.1

2.6

V_CC= 1.8V

1.4

1.6

V_CC= 3.0 - 3.6V

0.05*V_CC

0.03*V_CC

0.06*V_CC

0.4

V_CC= 2.3 - 2.7V

0.7

V_OL

Low level output voltage

V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 1.8V

T = 25°C

0.76

0.64

0.46

0.1

0.3

0.2

I_IN

Input leakage current

<0.01

24

µA

R_P

Pull/buss keeper resistor

kΩ

4.0

t_r

Rise time

No load

ns

slew rate limitation

7.0

Notes:

1. The sum of all I_OHfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OHfor PORTC must not exceed 200mA.

The sum of all I_OHfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OHfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

2. The sum of all I_OLfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OLfor PORTC must not exceed 200mA.

The sum of all I_OLfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OLfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

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36.2.6 ADC characteristics

Table 36-40. Power supply, reference and input range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1

Typ.

Max.

Units

V

AV_CC

V_REF

Analog supply voltage

Reference voltage

V_CC+ 0.3

AV_CC- 0.6

V

R_in

C_sample

R_AREF

C_AREF

V_IN

Input resistance

Switched

4.0

4.4

>10

7

kΩ

pF

MΩ

pF

V

Input capacitance

Switched

Reference input resistance

(leakage only)

Reference input capacitance Static load

Input range

-0.1

-V_REF

-ΔV

AV_CC+0.1

V_REF

Conversion range

Fixed offset voltage

Differential mode, Vinp - Vinn

V

Single ended unsigned mode, Vinp

V_REF-ΔV

V

∆V

190

LSB

Table 36-41. Clock and timing.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Maximum is 1/4 of peripheral clock

frequency

100

2000

Clk_ADC

ADC clock frequency

kHz

Measuring internal signals

Current limitation (CURRLIMIT) off

CURRLIMIT = LOW

100

0.25

125

2000

1500

1000

500

5

f_ADC

Sample rate

ksps

µs

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

Sampling time

1/2 Clk_ADCcycle

(RES+2)/2+(GAIN !=0)

RES (Resolution) = 8 or 12

Clk_ADC

cycles

Conversion time (latency)

5

8

Clk_ADC

cycles

Start-up time

ADC clock cycles

12

24

After changing reference or input mode

After ADC flush

7

1

7

1

Clk_ADC

cycles

ADC settling time

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Table 36-42. Accuracy characteristics.

Symbol

Parameter

Condition ⁽²⁾

Min.

Typ.

12

Max.

12

Units

RES

INL⁽¹⁾

DNL⁽¹⁾

Resolution

Programmable to 8 or 12 bit

8

Bits

V_CC-1.0V < V_REF< V_CC-0.6V

±1.2

±1.5

±1.0

±1.5

<±0.8

-1.0

±2.0

±3.0

±2.0

±3.0

<±1.0

500ksps

All V_REF

V_CC-1.0V < V_REF< V_CC-0.6V

All V_REF

Integral non-linearity

lsb

2000ksps

Differential non-linearity

Offset error

guaranteed monotonic

lsb

mV

Temperature drift

<0.01

<0.6

-1.0

mV/K

mV/V

Operating voltage drift

External reference

AV_CC/1.6

AV_CC/2.0

Bandgap

10

Differential

mode

mV

8.0

Gain error

±5.0

<0.02

<0.5

Temperature drift

mV/K

mV/V

Operating voltage drift

Differential mode, shorted input

2msps, V_CC= 3.6V, Clk_PER= 16MHz

mV

rms

Noise

0.4

Notes:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V_REFis used.

Table 36-43. Gain stage characteristics.

Symbol

Parameter

Condition

Switched in normal mode

Gain stage output

Min.

Typ.

4.0

Max.

Units

kΩ

pF

R_in

Input resistance

Input capacitance

Signal range

C_sample

4.4

0

V_CC- 0.6

V

Clk_ADC

cycles

Propagation delay

Sample rate

ADC conversion rate

Same as ADC

500ksps

1.0

100

1000

±4.0

kHz

lsb

All gain

settings

INL ⁽¹⁾

Integral non-linearity

±1.5

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

-0.8

-2.5

-3.5

Gain error

%

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Symbol

Parameter

Condition

1x gain, normal mode

Min.

Typ.

-2.0

-5.0

-4.0

0.5

Max.

Units

Offset error,

input referred

8x gain, normal mode

64x gain, normal mode

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

mV

V_CC= 3.6V

Ext. V_REF

mV

rms

Noise

1.5

11

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

36.2.7 DAC Characteristics

Table 36-44. Power supply, reference and output range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1.0

Typ.

Max.

V_CC+ 0.3

V_CC- 0.6

50

Units

V

AV_CC

AV_REF

R_channel

Analog supply voltage

External reference voltage

DC output impedance

V

Ω

Linear output voltage range

Reference input resistance

Reference input capacitance Static load

Minimum Resistance load

0.15

1.0

AV_CC-0.15

V

R_AREF

>10

7.0

MΩ

pF

kΩ

pF

nF

CAREF

100

1.0

Maximum capacitance load

1000Ω serial resistance

Operating within accuracy specification

Safe operation

AV_CC/1000

10

Output sink/source

mA

Table 36-45. Clock and timing.

Symbol

Parameter

Condition

Min.

Typ.

Max.

1000

500

Units

Normal mode

0

C_load=100pF,

maximum step size

f_DAC

Conversion rate

ksps

Low power mode

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Table 36-46. Accuracy characteristics.

Symbol

Parameter

Condition

Min.

Typ.

Max.

12

Units

RES

Input resolution

Bits

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

±2.0

±1.5

±2.0

±1.5

±5.0

±1.5

±0.6

±1.0

±0.6

±4.5

<4.0

4.0

±3.0

±2.5

±4.0

V_REF= Ext 1.0V

V_REF=AV_CC

INL ⁽¹⁾

Integral non-linearity

lsb

V_REF=INT1V

V_REF=Ext 1.0V

V_REF=AV_CC

3.0

1.5

3.5

1.5

DNL ⁽¹⁾

Differential non-linearity

lsb

V_REF=INT1V

Gain error

After calibration

lsb

Gain calibration step size

Gain calibration drift

Offset error

V_REF= Ext 1.0V

After calibration

<0.2

<1.0

1.0

mV/K

lsb

Offset calibration step size

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.

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36.2.8 Analog Comparator Characteristics

Table 36-47. Analog Comparator characteristics.

Symbol

V_off

Parameter

Condition

Min.

Typ.

<±10

<1

Max.

Units

mV

nA

Input offset voltage

Input leakage current

Input voltage range

AC startup time

I_lk

-0.1

AV_CC

V

100

0

µs

V_hys1

Hysteresis, none

mV

mode = High Speed (HS)

mode = Low Power (LP)

mode = HS

13

V_hys2

Hysteresis, small

Hysteresis, large

mV

30

V_hys3

mode = LP

60

V_CC= 3.0V, T= 85°C

mode = HS

V_CC= 3.0V, T= 85°C

mode = HS

30

90

500

0.5

30

t_delay

Propagation delay

ns

mode = LP

130

0.3

mode = LP

64-level voltage scaler

Integral non-linearity (INL)

lsb

36.2.9 Bandgap and Internal 1.0V Reference Characteristics

Table 36-48. Bandgap and Internal 1.0V reference characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

As reference for ADC or DAC

As input voltage to ADC and AC

1 Clk_PER+ 2.5µs

Startup time

µs

1.5

1.1

Bandgap voltage

V

INT1V

Internal 1.00V reference

Variation over voltage and temperature

T= 85°C, after calibration

0.99

1.0

1.01

Relative to T= 85°C, V_CC= 3.0V

±1.5

%

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36.2.10 Brownout Detection Characteristics

Table 36-49. Brownout detection characteristics.

Symbol Parameter

BOD level 0 falling V_CC

BOD level 1 falling V_CC

BOD level 2 falling V_CC

Condition

Min.

Typ.

1.62

1.8

Max.

Units

1.60

1.72

2.0

BOD level 3 falling V_CC

V_BOT

2.2

V

BOD level 4 falling V_CC

2.4

BOD level 5 falling V_CC

BOD level 6 falling V_CC

BOD level 7 falling V_CC

2.6

2.8

3.0

Continuous mode

Sampled mode

0.4

t_BOD

Detection time

Hysteresis

µs

%

1000

1.2

V_HYST

36.2.11 External Reset Characteristics

Table 36-50. External reset characteristics.

Symbol Parameter

Condition

Min.

Typ.

95

Max.

Units

t_EXT

Minimum reset pulse width

1000

ns

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

0.60*V_CC

0.50*V_CC

0.40*V_CC

25

Reset threshold voltage (V_IH)

V_RST

V

Reset threshold voltage (V_IL)

Reset pin Pull-up Resistor

R_RST

kΩ

36.2.12 Power-on Reset Characteristics

Table 36-51. Power-on reset characteristics.

Symbol Parameter

Condition

V_CCfalls faster than 1V/ms

V_CCfalls at 1V/ms or slower

Min.

0.4

Typ.

1.0

Max.

Units

(1)

V_POT-

POR threshold voltage falling V_CC

V

0.8

1.0

V_POT+

POR threshold voltage rising V_CC

1.3

1.59

Note:

1. V_POT-values are only valid when BOD is disabled. When BOD is enabled V_POT-= V_POT+.

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36.2.13 Flash and EEPROM Memory Characteristics

Table 36-52. Endurance and data retention.

Symbol Parameter

Condition

Min.

10K

2K

Typ.

Max.

Units

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

Write/Erase cycles

Cycle

Flash

100

25

Data retention

Year

Cycle

Year

10

100K

30K

100

25

Write/Erase cycles

Data retention

EEPROM

10

Table 36-53. Programming time.

Symbol Parameter

Condition

Min.

Typ.⁽¹⁾

Max.

Units

ms

Chip Erase

32KB Flash, EEPROM⁽²⁾and SRAM erase

Section erase

50

6

Application Erase

ms

Page erase

4

Flash

Page write

4

ms

Atomic page erase and write

Page erase

8

4

EEPROM

Page write

4

Atomic page erase and write

8

Notes:

1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

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36.2.14 Clock and Oscillator Characteristics

36.2.14.1 Calibrated 32.768kHz Internal Oscillator characteristics

Table 36-54. 32.768kHz internal oscillator characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

kHz

%

Frequency

32.768

Factory calibration accuracy

User calibration accuracy

T = 85°C, V_CC= 3.0V

-0.5

0.5

%

36.2.14.2 Calibrated 2MHz RC Internal Oscillator characteristics

Table 36-55. 2MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

1.8

2.2

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration stepsize

2.0

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.21

%

36.2.14.3 Calibrated and tunable 32MHz internal oscillator characteristics

Table 36-56. 32MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

30

55

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration step size

32

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.22

%

36.2.14.4 32kHz Internal ULP Oscillator characteristics

Table 36-57. 32kHz internal ULP oscillator characteristics.

Symbol Parameter

Output frequency

Accuracy

Condition

Min.

Typ.

Max.

Units

kHz

%

32

-30

30

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36.2.14.5 Internal Phase Locked Loop (PLL) characteristics

Table 36-58. Internal PLL characteristics.

Symbo

l

Parameter

Condition

Output frequency must be within f_OUT

V_CC= 1.6 - 1.8V

Min.

0.4

20

Typ.

Max.

64

Units

f_IN

Input frequency

MHz

48

f_OUT

Output frequency ⁽¹⁾

MHz

V_CC= 2.7 - 3.6V

20

128

Start-up time

Re-lock time

25

µs

Note:

1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.2.14.6 External clock characteristics

Figure 36-10. External clock drive waveform

t_CH

t_CR

t_CF

V_IH1

V_IL1

t_CL

t_CK

Table 36-59. External clock used as system clock without prescaling.

Symbol

Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

0

Typ.

Max.

12

Units

1/t_CK

Clock Frequency ⁽¹⁾

MHz

0

32

83.3

31.5

30.0

12.5

30.0

12.5

t_CK

t_CH

t_CL

t_CR

Clock Period

ns

Clock High Time

Clock Low Time

10

3

Rise Time (for maximum frequency)

10

3

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

10

Note:

1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

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Table 36-60. External clock with prescaler ⁽¹⁾for system clock.

Symbol Parameter Condition

Clock Frequency ⁽²⁾

Min.

0

Typ.

Max.

90

Units

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

1/t_CK

MHz

0

142

11

7

t_CK

Clock Period

ns

4.5

2.4

4.5

2.4

t_CH

Clock High Time

t_CL

Clock Low Time

1.5

1.0

1.5

1.0

10

t_CR

Rise Time (for maximum frequency)

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

Notes:

1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

36.2.14.7 External 16MHz crystal oscillator and XOSC characteristic

Table 36-61. External 16MHz crystal oscillator and XOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

<10

<1

Max.

Units

FRQRANGE=0

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

Cycle to cycle jitter

FRQRANGE=1, 2, or 3

ns

<1

FRQRANGE=0

<6

Long term jitter

Frequency error

FRQRANGE=1, 2, or 3

<0.5

<0.1

<0.05

<0.005

40

ns

%

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

42

Duty cycle

%

45

48

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Symbol Parameter

Condition

Min.

Typ.

Max.

Units

0.4MHz resonator,

CL=100pF

2.4k

XOSCPWR=0,

FRQRANGE=0

1MHz crystal, CL=20pF

2MHz crystal, CL=20pF

2MHz crystal

8.7k

2.1k

4.2k

250

195

360

285

155

365

200

105

435

235

125

495

270

145

305

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

8MHz crystal

9MHz crystal

8MHz crystal

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

9MHz crystal

12MHz crystal

9MHz crystal

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

Negative

R_Q

Ω

impedance ⁽¹⁾

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

12MHz crystal

16MHz crystal

12MHz crystal

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

16MHz crystal

12MHz crystal

16MHz crystal

160

380

205

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

ESR

SF = Safety factor

min(R_Q)/SF

kΩ

Parasitic

C_XTAL1

capacitance XTAL1

5.4

pF

Parasitic

C_XTAL2

capacitance XTAL2

7.1

pF

Parasitic

capacitance load

C_LOAD

3.07

Note:

1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.

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36.2.14.8 External 32.768kHz crystal oscillator and TOSC characteristics

Table 36-62. External 32.768kHz crystal oscillator and TOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

60

Units

Crystal load capacitance 6.5pF

Crystal load capacitance 9.0pF

Recommended crystal equivalent

ESR/R1

C_TOSC1

C_TOSC2

kΩ

series resistance (ESR)

35

5.4

4.0

7.1

4.0

Parasitic capacitance TOSC1 pin

pF

Alternate TOSC location

Parasitic capacitance TOSC2 pin

Recommended safety factor

Alternate TOSC location

capacitance load matched to

crystal specification

3.0

Note:

1. See Figure 36-11 for definition.

Figure 36-11.TOSC input capacitance.

C_L1

C_L2

Device internal

External

TOSC1

TOSC2

32.768kHz crystal

The parasitic capacitance between the TOSC pins is C_L1+ C_L2in series as seen from the crystal when oscillating

without external capacitors.

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36.2.15 SPI Characteristics

Figure 36-12. SPI timing requirements in master mode.

SS

t_MOS

t_SCKR

t_SCKF

SCK

(CPOL = 0)

t_SCKW

SCK

(CPOL = 1)

t_SCKW

t_MIS

t_MIH

t_SCK

MISO

(Data input)

MSB

LSB

t_MOH

MOSI

(Data output)

MSB

LSB

Figure 36-13. SPI timing requirements in slave mode.

SS

t_SSS

t_SCKR

t_SCKF

t_SSH

SCK

(CPOL = 0)

t_SSCKW

SCK

(CPOL = 1)

t_SSCKW

t_SIS

t_SIH

t_SSCK

MOSI

(Data input)

MSB

LSB

t_SOSSS

t_SOS

t_SOSSH

MISO

(Data output)

MSB

LSB

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Table 36-63. SPI timing characteristics and requirements.

Symbol Parameter Condition

Min.

Typ.

Max.

Units

(See Table 21-4 in

XMEGA AU Manual)

t_SCK

SCK period

Master

t_SCKW

t_SCKR

t_SCKF

t_MIS

SCK high/low width

SCK rise time

Master

Slave

0.5×SCK

2.7

SCK fall time

2.7

MISO setup to SCK

MISO hold after SCK

MOSI setup SCK

MOSI hold after SCK

Slave SCK Period

SCK high/low width

SCK rise time

10

t_MIH

10

t_MOS

t_MOH

t_SSCK

t_SSCKW

t_SSCKR

t_SSCKF

t_SIS

0.5×SCK

1.0

4×t Clk_PER

2×t Clk_PER

ns

1600

SCK fall time

MOSI setup to SCK

MOSI hold after SCK

SS setup to SCK

SS hold after SCK

MISO setup SCK

MISO hold after SCK

MISO setup after SS low

MISO hold after SS high

3.0

t Clk_PER

21

t_SIH

t_SSS

t_SSH

20

t_SOS

8.0

13

t_SOH

t_SOSS

t_SOSH

11

8.0

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36.2.16 Two-Wire Interface Characteristics

Table 36-64 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR

XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer

to Figure 36-14.

Figure 36-14. Two-wire interface bus timing.

t_of

t_HIGH

t_LOW

t_r

SCL

SDA

t_HD;DAT

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;STA

t_BUF

Table 36-64. Two-wire interface characteristics.

Symbol Parameter

Condition

Min.

0.7V_CC

0.5

Typ.

Max.

Units

V

V_IH

V_IL

Input high voltage

V_CC+0.5

0.3×V_CC

Input low voltage

V

(1)

V_hys

Hysteresis of Schmitt trigger inputs

Output low voltage

0.05V_CC

0

V

V_OL

3mA, sink current

0.4

300

250

50

V

(1)(2)

t_r

t_of

Rise time for both SDA and SCL

Output fall time from V_IHminto V_ILmax

Spikes suppressed by Input filter

Input current for each I/O Pin

Capacitance for each I/O Pin

SCL clock frequency

20+0.1C_b

0

ns

µA

pF

kHz

10pF < C_b< 400pF ⁽²⁾

0.1V_CC< V_I< 0.9V_CC

t_SP

I_I

-10

10

C_I

10

f_SCL

f_PER⁽³⁾>max(10f_SCL, 250kHz)

0

400

f_SCL≤ 100kHz

100ns

C_b

--------------

V_CC– 0.4V

---------------------------

3mA

R_P

Value of pull-up resistor

Ω

300ns

f_SCL> 100kHz

--------------

C_b

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

t_HD;STA

Hold time (repeated) START condition

Low period of SCL Clock

µs

t_LOW

t_HIGH

High period of SCL Clock

Set-up time for a repeated START

condition

t_SU;STA

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Symbol Parameter

Condition

f_SCL≤ 100kHz

Min.

0

Typ.

Max.

3.45

0.9

Units

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

Data hold time

µs

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

0

250

100

4.0

0.6

4.7

1.3

Data setup time

ns

µs

Setup time for STOP condition

Bus free time between a STOP and

START condition

Notes:

1. Required only for f_SCL> 100kHz.

2. C_b= Capacitance of one bus line in pF.

3.

f_PER= Peripheral clock frequency.

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36.3 ATxmega64A4U

36.3.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 36-65 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or other conditions beyond those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 36-65. Absolute maximum ratings.

Symbol

V_CC

I_VCC

I_GND

V_PIN

I_PIN

Parameter

Condition

Min.

Typ.

Max.

4.0

Units

V

Power supply voltage

Current into a V_CCpin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V_CC

I/O pin sink/source current

Storage temperature

-0.3

200

mA

V

200

-0.5

-25

-65

V_CC+0.5

25

mA

°C

T_A

150

T_j

Junction temperature

150

°C

36.3.2 General Operating Ratings

The device must operate within the ratings listed in Table 36-66 in order for all other electrical characteristics and

typical characteristics of the device to be valid.

Table 36-66. General operating conditions.

Symbol

V_CC

Parameter

Condition

Min.

1.60

-40

Typ.

Max.

3.6

Units

V

Power supply voltage

Analog supply voltage

Temperature range

Junction temperature

AV_CC

T_A

3.6

V

85

°C

T_j

-40

105

Table 36-67. Operating voltage and frequency.

Symbol

Parameter

Condition

V_CC= 1.6V

V_CC= 1.8V

V_CC= 2.7V

V_CC= 3.6V

Min.

Typ.

Max.

12

Units

0

12

Clk_CPU

CPU clock frequency

MHz

32

The maximum CPU clock frequency depends on V_CC. As shown in Figure 36-15 the Frequency vs. V_CCcurve is linear

between 1.8V < V_CC< 2.7V.

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Figure 36-15.Maximum Frequency vs. V_CC

.

MHz

32

Safe Operating Area

12

V

1.6

1.8

2.7

3.6

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36.3.3 Current consumption

Table 36-68. Current consumption for Active mode and sleep modes.

Symbol Parameter

Condition

Min.

Typ.

52

Max.

Units

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

32kHz, Ext. Clk

132

223

476

400

0.8

8.2

2.4

3.5

57

µA

1MHz, Ext. Clk

Active power

consumption ⁽¹⁾

600

1.4

12

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

V_CC= 3.0V

mA

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

1MHz, Ext. Clk

2MHz, Ext. Clk

µA

Idle power

110

115

216

3.5

0.1

1.2

2.4

consumption ⁽¹⁾

225

350

5.5

1.0

4.5

6.0

V_CC= 3.0V

32MHz, Ext. Clk

T = 25°C

mA

I_CC

T = 85°C

V_CC= 3.0V

T = 105°C

WDT and Sampled BOD enabled,

T = 25°C

Power-down power

consumption

1.4

2.4

3.5

3.0

6.0

8.0

µA

WDT and Sampled BOD enabled,

T = 85°C

V_CC= 3.0V

WDT and Sampled BOD enabled,

T = 105°C

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

1.2

1.5

0.6

0.7

0.8

1.0

140

RTC from ULP clock, WDT and

sampled BOD enabled, T = 25°C

2.0

3.0

Power-save power

consumption ⁽²⁾

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

µA

RTC from low power 32.768kHz TOSC,

T = 25°C

Reset power consumption Current through RESET pin substracted V_CC= 3.0V

Notes:

1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

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Table 36-69. Current consumption for modules and peripherals.

Symbol Parameter

Condition ⁽¹⁾

Min.

Typ.

1.0

29

Max.

Units

µA

ULP oscillator

32.768kHz int. oscillator

µA

85

2MHz int. oscillator

32MHz int. oscillator

µA

DFLL enabled with 32.768kHz int. osc. as reference

120

300

465

20x multiplication factor,

PLL

320

µA

32MHz int. osc. DIV4 as reference

Watchdog timer

1.0

138

1.0

103

100

3.0

2.6

2.1

1.6

1.9

Continuous mode

BOD

µA

Sampled mode, includes ULP oscillator

Internal 1.0V reference

Temperature sensor

µA

I_CC

CURRLIMIT = LOW

250ksps

ADC

mA

V_REF= Ext ref

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

250ksps

Normal mode

DAC

AC

V_REF= Ext ref

No load

mA

µA

Low power mode

1.1

High speed mode

Low pPower mode

330

130

108

16

DMA

615KBps between I/O registers and SRAM

µA

mA

Timer/counter

USART

Rx and Tx enabled, 9600 BAUD

2.5

8.0

Flash memory and EEPROM programming

Note:

1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V_CC= 3.0V, Clk_SYS= 1MHz external

clock without prescaling, T = 25°C unless other conditions are given.

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36.3.4 Wake-up time from sleep modes

Table 36-70. Device wake-up time from sleep modes with various system clock sources.

Symbol Parameter

Condition

External 2MHz clock

Min.

Typ. ⁽¹⁾

2.0

Max.

Units

Wake-up time from idle,

standby, and extended standby

mode

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

External 2MHz clock

120

2.0

µs

0.2

t_wakeup

4.5

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

320

9.0

Wake-up time from power-save

and power-down mode

µs

4.0

Note:

1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-16. All peripherals and modules

start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-16.Wake-up time definition.

Wakeup time

Wakeup request

Clock output

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36.3.5 I/O Pin Characteristics

The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 36-71. I/O pin characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

(1)

I_OH

I_OL

/

I/O pin source/sink current

-20

20

mA

(2)

V_CC= 2.7- 3.6V

2.0

0.7*V_CC

0.8*V_CC

-0.3

V_CC+0.3

0.8

V_IH

High level input voltage

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 2.7- 3.6V

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 3.0 - 3.6V

V

V_IL

Low level input voltage

-0.3

0.3*V_CC

0.2*V_CC

-0.3

I_OH= -2mA

I_OH= -1mA

I_OH= -2mA

I_OH= -8mA

I_OH= -6mA

I_OH= -2mA

I_OL= 2mA

I_OL= 1mA

I_OL= 2mA

I_OL= 15mA

I_OL= 10mA

I_OL= 5mA

2.4

0.94*V_CC

0.96*V_CC

0.92*V_CC

2.9

2.0

V_CC= 2.3 - 2.7V

1.7

V_OH

High level output voltage

V

V_CC= 3.3V

2.6

V_CC= 3.0V

2.1

2.6

V_CC= 1.8V

1.4

1.6

V_CC= 3.0 - 3.6V

0.02*V_CC

0.01*V_CC

0.02*V_CC

0.4

V_CC= 2.3 - 2.7V

0.7

V_OL

Low level output voltage

V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 1.8V

T = 25°C

0.76

0.64

0.46

0.1

0.3

0.2

<0.01

I_IN

Input leakage current

µA

XOSC and

TOSC pins

<0.02

1.1

R_P

t_r

Pull/buss keeper resistor

Rise time

24

4.0

7.0

kΩ

No load

ns

slew rate limitation

Notes:

1. The sum of all I_OHfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OHfor PORTC must not exceed 200mA.

The sum of all I_OHfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OHfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

2. The sum of all I_OLfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OLfor PORTC must not exceed 200mA.

The sum of all I_OLfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OLfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

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36.3.6 ADC characteristics

Table 36-72. Power supply, reference and input range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1.0

Typ.

Max.

Units

V

AV_CC

V_REF

Analog supply voltage

Reference voltage

V_CC+ 0.3

AV_CC- 0.6

V

R_in

C_sample

R_AREF

C_AREF

V_IN

Input resistance

Switched

4.0

4.4

>10

7.0

kΩ

pF

MΩ

pF

V

Input capacitance

Switched

Reference input resistance

(leakage only)

Reference input capacitance Static load

Input range

-0.1

-V_REF

-ΔV

AV_CC+0.1

V_REF

Conversion range

Fixed offset voltage

Differential mode, Vinp - Vinn

V

Single ended unsigned mode, Vinp

V_REF-ΔV

V

∆V

190

lsb

Table 36-73. Clock and timing.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Maximum is 1/4 of peripheral clock

frequency

100

2000

Clk_ADC

ADC clock frequency

kHz

Measuring internal signals

Current limitation (CURRLIMIT) off

CURRLIMIT = LOW

100

0.25

125

2000

1500

1000

500

5

f_ADC

Sample rate

ksps

µs

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

Sampling time

1/2 Clk_ADCcycle

(RES+2)/2+(GAIN !=0)

RES (Resolution) = 8 or 12

Clk_ADC

cycles

Conversion time (latency)

5

8

Clk_ADC

cycles

Start-up time

ADC clock cycles

12

24

After changing reference or input mode

After ADC flush

7

1

7

1

Clk_ADC

cycles

ADC settling time

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Table 36-74. Accuracy characteristics.

Symbol

Parameter

Condition ⁽²⁾

Min.

Typ.

12

Max.

12

Units

RES

INL ⁽¹⁾

DNL ⁽¹⁾

Resolution

Programmable to 8 or 12 bit

8

Bits

V_CC-1.0V < V_REF< V_CC-0.6V

±1.2

±1.5

±1.0

±1.5

<±0.8

-1

±2

500ksps

All V_REF

V_CC-1.0V < V_REF< V_CC-0.6V

All V_REF

±3

Integral non-linearity

lsb

±2

2000ksps

±3

Differential non-linearity

Offset error

guaranteed monotonic

<±1

lsb

mV

Temperature drift

<0.01

<0.6

-1

mV/K

mV/V

Operating voltage drift

External reference

AV_CC/1.6

AV_CC/2.0

Bandgap

10

Differential

mode

mV

8

Gain error

±5

Temperature drift

<0.02

<0.5

mV/K

mV/V

Operating voltage drift

Differential mode, shorted input

2msps, V_CC= 3.6V, Clk_PER= 16MHz

mV

rms

Noise

0.4

Notes:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V_REFis used.

Table 36-75. Gain stage characteristics.

Symbol

Parameter

Condition

Switched in normal mode

Gain stage output

Min.

Typ.

4.0

Max.

Units

kΩ

pF

R_in

Input resistance

Input capacitance

Signal range

C_sample

4.4

0

V_CC- 0.6

V

Clk_ADC

cycles

Propagation delay

Sample rate

ADC conversion rate

Same as ADC

500ksps

1.0

100

1000

±4.0

kHz

lsb

All gain

settings

INL ⁽¹⁾

Integral non-linearity

±1.5

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

-0.8

-2.5

-3.5

Gain error

%

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Symbol

Parameter

Condition

1x gain, normal mode

Min.

Typ.

-2

Max.

Units

Offset error,

input referred

8x gain, normal mode

64x gain, normal mode

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

-5

mV

-4

0.5

1.5

11

V_CC= 3.6V

Ext. V_REF

mV

rms

Noise

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

36.3.7 DAC Characteristics

Table 36-76. Power supply, reference and output range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1.0

Typ.

Max.

V_CC+ 0.3

V_CC- 0.6

50

Units

V

AV_CC

AV_REF

R_channel

Analog supply voltage

External reference voltage

DC output impedance

V

Ω

Linear output voltage range

Reference input resistance

Reference input capacitance Static load

Minimum resistance load

0.15

1.0

AV_CC-0.15

V

R_AREF

>10

7

MΩ

pF

kΩ

pF

nF

CAREF

100

1.0

Maximum capacitance load

1000Ω serial resistance

Operating within accuracy specification

Safe operation

AV_CC/1000

10

Output sink/source

mA

Table 36-77. Clock and timing.

Symbol Parameter

Condition

Min.

Typ.

Max.

1000

500

Units

Normal mode

0

C_load=100pF,

maximum step size

f_DAC

Conversion rate

ksps

Low power mode

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Table 36-78. Accuracy characteristics.

Symbol

Parameter

Condition

Min.

Typ.

Max.

12

Units

RES

Input resolution

Bits

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

±2.0

±1.5

±2.0

±1.5

±5.0

±1.5

±0.6

±1.0

±0.6

±4.5

<4.0

4.0

±3.0

±2.5

±4.0

V_REF= Ext 1.0V

V_REF=AV_CC

INL ⁽¹⁾

Integral non-linearity

lsb

V_REF=INT1V

V_REF=Ext 1.0V

V_REF=AV_CC

3.0

1.5

3.5

1.5

DNL ⁽¹⁾

Differential non-linearity

lsb

V_REF=INT1V

Gain error

After calibration

lsb

Gain calibration step size

Gain calibration drift

Offset error

V_REF= Ext 1.0V

After calibration

<0.2

<1.0

1.0

mV/K

lsb

Offset calibration step size

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.

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36.3.8 Analog Comparator Characteristics

Table 36-79. Analog Comparator characteristics.

Symbol

V_off

Parameter

Condition

Min.

Typ.

<±10

<1

Max.

Units

mV

nA

Input offset voltage

Input leakage current

Input voltage range

AC startup time

I_lk

-0.1

AV_CC

V

100

0

µs

V_hys1

Hysteresis, none

mV

mode = High Speed (HS)

mode = Low Power (LP)

mode = HS

20

V_hys2

Hysteresis, small

Hysteresis, large

mV

30

35

V_hys3

mode = LP

60

V_CC= 3.0V, T= 85°C

mode = HS

mode = LP

30

90

500

0.5

30

t_delay

Propagation delay

ns

V_CC= 3.0V, T= 85°C

mode = LP

130

0.3

Integral non-linearity (INL)

64-level voltage scaler

lsb

36.3.9 Bandgap and Internal 1.0V Reference Characteristics

Table 36-80. Bandgap and Internal 1.0V reference characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

As reference for ADC or DAC

As input voltage to ADC and AC

1 Clk_PER+ 2.5µs

Startup time

µs

1.5

1.1

1

Bandgap voltage

V

INT1V

Internal 1.00V reference

Variation over voltage and temperature

T= 85°C, after calibration

0.99

1.01

Relative to T= 85°C, V_CC= 3.0V

±1.5

%

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36.3.10 Brownout Detection Characteristics

Table 36-81. Brownout detection characteristics.

Symbol Parameter

BOD level 0 falling V_CC

BOD level 1 falling V_CC

BOD level 2 falling V_CC

Condition

Min.

Typ.

1.62

1.8

Max.

Units

1.50

1.72

2.0

BOD level 3 falling V_CC

V_BOT

2.2

V

BOD level 4 falling V_CC

2.4

BOD level 5 falling V_CC

BOD level 6 falling V_CC

BOD level 7 falling V_CC

2.6

2.8

3.0

Continuous mode

Sampled mode

0.4

t_BOD

Detection time

Hysteresis

µs

%

1000

1.2

V_HYST

36.3.11 External Reset Characteristics

Table 36-82. External reset characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

t_EXT

Minimum reset pulse width

1000

95

ns

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

0.60×V_CC

0.50×V_CC

0.40×V_CC

25

Reset threshold voltage (V_IH)

V_RST

V

Reset threshold voltage (V_IL)

Reset pin Pull-up Resistor

R_RST

kΩ

36.3.12 Power-on Reset Characteristics

Table 36-83. Power-on reset characteristics.

Symbol Parameter

Condition

Min.

Typ.

1.0

Max.

Units

V_CCfalls faster than 1V/ms

V_CCfalls at 1V/ms or slower

0.4

0.8

(1)

V_POT-

POR threshold voltage falling V_CC

V

1.0

V_POT+

POR threshold voltage rising V_CC

1.3

1.59

Note:

1. V_POT-values are only valid when BOD is disabled. When BOD is enabled V_POT-= V_POT+.

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36.3.13 Flash and EEPROM Memory Characteristics

Table 36-84. Endurance and data retention.

Symbol Parameter

Condition

Min.

10K

2K

Typ.

Max.

Units

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

Write/Erase cycles

Cycle

Flash

100

25

Data retention

Year

Cycle

Year

10

100K

30K

100

25

Write/Erase cycles

Data retention

EEPROM

10

Table 36-85. Programming time.

Symbol Parameter

Chip Erase

Condition

Min.

Typ.⁽¹⁾

Max.

Units

ms

64KB Flash, EEPROM⁽²⁾and SRAM Erase

Section erase

55

6

Application Erase

ms

Page erase

4

Flash

Page write

4

ms

Atomic page erase and write

Page erase

8

4

EEPROM

Page write

4

Atomic page erase and write

8

Notes:

1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

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36.3.14 Clock and Oscillator Characteristics

36.3.14.1 Calibrated 32.768kHz Internal Oscillator characteristics

Table 36-86. 32.768kHz internal oscillator characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

kHz

%

Frequency

32.768

Factory calibration accuracy

User calibration accuracy

T = 85°C, V_CC= 3.0V

-0.5

0.5

%

36.3.14.2 Calibrated 2MHz RC Internal Oscillator characteristics

Table 36-87. 2MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

1.8

2.2

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration stepsize

2.0

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.21

%

36.3.14.3 Calibrated and tunable 32MHz internal oscillator characteristics

Table 36-88. 32MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

30

55

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration step size

32

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.22

%

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36.3.14.4 32kHz Internal ULP Oscillator characteristics

Table 36-89. 32kHz internal ULP oscillator characteristics.

Symbol Parameter

Factory calibrated frequency

Condition

Min.

Typ.

Max.

Units

kHz

%

32

Factory calibrated accuracy

Accuracy

T = 85°C, V_CC= 3.0V

-12

-30

12

30

%

36.3.14.5 Internal Phase Locked Loop (PLL) characteristics

Table 36-90. Internal PLL characteristics.

Symbo

l

Parameter

Condition

Output frequency must be within f_OUT

V_CC= 1.6 - 1.8V

Min.

0.4

20

Typ.

Max.

64

Units

f_IN

Input frequency

MHz

48

f_OUT

Output frequency ⁽¹⁾

MHz

V_CC= 2.7 - 3.6V

20

128

Start-up time

Re-lock time

25

µs

Note:

1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.3.14.6 External clock characteristics

Figure 36-17. External clock drive waveform

t_CH

t_CR

t_CF

V_IH1

V_IL1

t_CL

t_CK

Table 36-91. External clock used as system clock without prescaling.

Symbol

Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

0

Typ.

Max.

12

Units

1/t_CK

Clock Frequency ⁽¹⁾

MHz

0

32

83.3

31.5

30.0

12.5

t_CK

Clock Period

ns

t_CH

Clock High Time

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Symbol

Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

30.0

12.5

Typ.

Max.

Units

t_CL

Clock Low Time

ns

10

3

t_CR

Rise Time (for maximum frequency)

ns

10

3

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

10

Note:

1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

Table 36-92. External clock with prescaler ⁽¹⁾for system clock.

Symbol Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

0

Typ.

Max.

90

Units

1/t_CK

Clock Frequency ⁽²⁾

Clock Period

MHz

0

142

11

7

t_CK

ns

4.5

2.4

4.5

2.4

t_CH

Clock High Time

t_CL

Clock Low Time

1.5

1.0

1.5

1.0

10

t_CR

Rise Time (for maximum frequency)

ns

t_CF

Fall Time (for maximum frequency)

Δt_CK

Change in period from one clock cycle to the next

%

Notes:

1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

36.3.14.7 External 16MHz crystal oscillator and XOSC characteristic

Table 36-93. External 16MHz crystal oscillator and XOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

<10

<1

Max.

Units

FRQRANGE=0

XOSCPWR=0

XOSCPWR=1

Cycle to cycle jitter

FRQRANGE=1, 2, or 3

ns

<1

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Symbol Parameter

Condition

Min.

Typ.

<6

Max.

Units

FRQRANGE=0

XOSCPWR=0

XOSCPWR=1

Long term jitter

FRQRANGE=1, 2, or 3

<0.5

<0.1

<0.05

<0.005

40

ns

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

Frequency error

%

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

42

Duty cycle

45

48

0.4MHz resonator,

CL=100pF

2.4k

XOSCPWR=0,

FRQRANGE=0

1MHz crystal, CL=20pF

2MHz crystal, CL=20pF

2MHz crystal

8.7k

2.1k

4.2k

250

195

360

285

155

365

200

105

435

235

125

495

270

145

305

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

8MHz crystal

9MHz crystal

8MHz crystal

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

9MHz crystal

12MHz crystal

9MHz crystal

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

Negative impedance ⁽¹⁾

Ω

R_Q

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

12MHz crystal

16MHz crystal

12MHz crystal

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

16MHz crystal

12MHz crystal

16MHz crystal

160

380

205

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

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Symbol Parameter

Condition

Min.

Typ.

Max.

Units

ESR

SF = Safety factor

min(R_Q)/SF

kΩ

Parasitic capacitance

XTAL1 pin

C_XTAL1

C_XTAL2

C_LOAD

5.60

7.62

3.23

pF

Parasitic capacitance

XTAL2 pin

Parasitic capacitance

load

Note:

1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization

36.3.14.8 External 32.768kHz crystal oscillator and TOSC characteristics

Table 36-94. External 32.768kHz crystal oscillator and TOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

60

Units

Crystal load capacitance 6.5pF

Crystal load capacitance 9.0pF

Recommended crystal equivalent

ESR/R1

C_TOSC1

C_TOSC2

kΩ

series resistance (ESR)

35

5.4

4.0

7.1

4.0

pF

Parasitic capacitance TOSC1 pin

Alternate TOSC location

pF

Parasitic capacitance TOSC2 pin

Recommended safety factor

Alternate TOSC location

capacitance load matched to

crystal specification

3

Note:

1. See Figure 36-18 for definition.

Figure 36-18. TOSC input capacitance.

C_L1

C_L2

Device internal

External

TOSC1

TOSC2

32.768kHz crystal

The parasitic capacitance between the TOSC pins is C_L1+ C_L2in series as seen from the crystal when oscillating

without external capacitors.

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36.3.15 SPI Characteristics

Figure 36-19.SPI timing requirements in master mode.

SS

t_MOS

t_SCKR

t_SCKF

SCK

(CPOL = 0)

t_SCKW

SCK

(CPOL = 1)

t_SCKW

t_MIS

t_MIH

t_SCK

MISO

(Data input)

MSB

LSB

t_MOH

MOSI

(Data output)

MSB

LSB

Figure 36-20.SPI timing requirements in slave mode.

SS

t_SSS

t_SCKR

t_SCKF

t_SSH

SCK

(CPOL = 0)

t_SSCKW

SCK

(CPOL = 1)

t_SSCKW

t_SIS

t_SIH

t_SSCK

MOSI

(Data input)

MSB

LSB

t_SOSSS

t_SOS

t_SOSSH

MISO

(Data output)

MSB

LSB

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Table 36-95. SPI timing characteristics and requirements.

Symbol Parameter Condition

Min.

Typ.

Max.

Units

(See Table 21-4 in

XMEGA AU Manual)

t_SCK

SCK period

Master

t_SCKW

t_SCKR

t_SCKF

t_MIS

SCK high/low width

SCK rise time

Master

Slave

0.5*SCK

2.7

SCK fall time

2.7

MISO setup to SCK

MISO hold after SCK

MOSI setup SCK

MOSI hold after SCK

Slave SCK Period

SCK high/low width

SCK rise time

11

t_MIH

0

t_MOS

t_MOH

t_SSCK

t_SSCKW

t_SSCKR

t_SSCKF

t_SIS

0.5*SCK

1.0

4*t Clk_PER

2*t Clk_PER

ns

1600

SCK fall time

MOSI setup to SCK

MOSI hold after SCK

SS setup to SCK

SS hold after SCK

MISO setup SCK

MISO hold after SCK

MISO setup after SS low

MISO hold after SS high

3.0

t_PER

20

t_SIH

t_SSS

t_SSH

20

t_SOS

8.0

13.0

11.0

8.0

t_SOH

t_SOSS

t_SOSH

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36.3.16 Two-Wire Interface Characteristics

Table 36-96 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR

XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer

to Figure 36-21.

Figure 36-21.Two-wire interface bus timing.

t_of

t_HIGH

t_LOW

t_r

SCL

SDA

t_HD;DAT

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;STA

t_BUF

Table 36-96. Two-wire interface characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

V_CC+0.5

0.3*V_CC

0

Units

V

V_IH

V_IL

Input high voltage

0.7*V_CC

-0.5

Input low voltage

V

(1)

V_hys

Hysteresis of Schmitt trigger inputs

Output low voltage

0.05*V_CC

0

V

V_OL

3mA, sink current

0.4

V

(1)(2)

t_r

t_of

Rise time for both SDA and SCL

Output fall time from V_IHminto V_ILmax

Spikes suppressed by input filter

Input current for each I/O pin

Capacitance for each I/O pin

SCL clock frequency

20+0.1C_b

0

ns

µA

pF

kHz

(1)(2)

10pF < C_b< 400pF ⁽²⁾

0.1V_CC< V_I< 0.9V_CC

20+0.1C_b

300

50

t_SP

I_I

0

-10

0

10

C_I

10

f_SCL

f_PER⁽³⁾>max(10f_SCL, 250kHz)

0

400

f_SCL≤ 100kHz

100ns

C_b

--------------

V_CC– 0.4V

---------------------------

3mA

R_P

Value of pull-up resistor

Ω

300ns

f_SCL> 100kHz

--------------

C_b

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

t_HD;STA

Hold time (repeated) START condition

Low period of SCL clock

µs

t_LOW

t_HIGH

High period of SCL clock

Set-up time for a repeated START

condition

t_SU;STA

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Symbol Parameter

Condition

f_SCL≤ 100kHz

Min.

0

Typ.

Max.

3.45

0.9

Units

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

Data hold time

µs

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

0

250

100

4.0

0.6

4.7

1.3

Data setup time

ns

µs

Setup time for STOP condition

Bus free time between a STOP and

START condition

Notes:

1. Required only for f_SCL> 100kHz.

2. C_b= Capacitance of one bus line in pF.

3.

f_PER= Peripheral clock frequency.

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36.4 ATxmega128A4U

36.4.1 Absolute Maximum Ratings

Stresses beyond those listed in Table 36-97 may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or other conditions beyond those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect

device reliability.

Table 36-97. Absolute maximum ratings.

Symbol

V_CC

I_VCC

I_GND

V_PIN

I_PIN

Parameter

Condition

Min.

Typ.

Max.

4

Units

V

Power supply voltage

Current into a V_CCpin

Current out of a Gnd pin

Pin voltage with respect to Gnd and V_CC

I/O pin sink/source current

Storage temperature

-0.3

200

mA

V

200

-0.5

-25

-65

V_CC+0.5

25

mA

°C

T_A

150

T_j

Junction temperature

150

°C

36.4.2 General Operating Ratings

The device must operate within the ratings listed in Table 36-98 in order for all other electrical characteristics and

typical characteristics of the device to be valid.

Table 36-98. General operating conditions.

Symbol

V_CC

Parameter

Condition

Min.

1.60

-40

Typ.

Max.

3.6

Units

V

Power supply voltage

Analog supply voltage

Temperature range

Junction temperature

AV_CC

T_A

3.6

V

85

°C

T_j

-40

105

Table 36-99. Operating voltage and frequency.

Symbol

Parameter

Condition

V_CC= 1.6V

V_CC= 1.8V

V_CC= 2.7V

V_CC= 3.6V

Min.

Typ.

Max.

12

Units

0

12

Clk_CPU

CPU clock frequency

MHz

32

The maximum CPU clock frequency depends on V_CC. As shown in Figure 36-22 the Frequency vs. V_CCcurve is linear

between 1.8V < V_CC< 2.7V.

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Figure 36-22.Maximum Frequency vs. V_CC

.

MHz

32

Safe Operating Area

12

V

1.6

1.8

2.7

3.6

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36.4.3 Current consumption

Table 36-100.Current consumption for Active mode and sleep modes.

Symbol Parameter

Condition

Min.

Typ.

55

Max.

Units

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

32kHz, Ext. Clk

135

255

535

460

1.0

9.5

2.9

3.9

62

µA

1MHz, Ext. Clk

Active power

consumption ⁽¹⁾

600

1.4

12

2MHz, Ext. Clk

32MHz, Ext. Clk

32kHz, Ext. Clk

V_CC= 3.0V

mA

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

1MHz, Ext. Clk

2MHz, Ext. Clk

µA

Idle power

118

125

240

3.8

0.1

1.5

0.1

consumption ⁽¹⁾

225

350

5.5

1.0

4.5

8.6

V_CC= 3.0V

32MHz, Ext. Clk

T = 25°C

mA

I_CC

T = 85°C

T = 105°C

µA

WDT and Sampled BOD enabled,

T = 25°C

Power-down power

consumption

1.4

2.8

1.4

3.0

6.0

8.8

V_CC= 3.0V

WDT and Sampled BOD enabled,

T = 85°C

WDT and Sampled BOD enabled,

T = 105°C

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

V_CC= 1.8V

V_CC= 3.0V

1.2

1.5

0.6

0.7

0.8

1.0

RTC from ULP clock, WDT and

sampled BOD enabled, T = 25°C

2.0

3.0

Power-save power

consumption ⁽²⁾

RTC from 1.024kHz low power

32.768kHz TOSC, T = 25°C

µA

RTC from low power 32.768kHz

TOSC, T = 25°C

Current through RESET pin

substracted

Reset power consumption

V_CC= 3.0V

300

Notes:

1. All Power Reduction Registers set.

2. Maximum limits are based on characterization, and not tested in production.

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Table 36-101.Current consumption for modules and peripherals.

Symbol Parameter

Condition ⁽¹⁾

Min.

Typ.

1.0

29

Max.

Units

µA

ULP oscillator

32.768kHz int. oscillator

µA

85

2MHz int. oscillator

32MHz int. oscillator

µA

DFLL enabled with 32.768kHz int. osc. as reference

115

270

440

20x multiplication factor,

PLL

320

µA

32MHz int. osc. DIV4 as reference

Watchdog timer

1.0

138

1.2

260

250

3.0

2.6

2.1

1.6

1.9

Continuous mode

BOD

µA

Sampled mode, includes ULP oscillator

Internal 1.0V reference

Temperature sensor

µA

I_CC

mA

CURRLIMIT = LOW

250ksps

ADC

V_REF= Ext ref

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

250ksps

Normal mode

DAC

AC

V_REF= Ext ref

No load

mA

µA

Low power mode

1.1

High speed mode

Low power mode

330

130

108

16

DMA

615kbps between I/O registers and SRAM

µA

mA

Timer/counter

USART

Rx and Tx enabled, 9600 BAUD

2.5

4.0

Flash memory and EEPROM programming

8.0

Note:

1. All parameters measured as the difference in current consumption between module enabled and disabled. All data at V_CC= 3.0V, Clk_SYS= 1MHz external

clock without prescaling, T = 25°C unless other conditions are given.

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36.4.4 Wake-up time from sleep modes

Table 36-102. Device wake-up time from sleep modes with various system clock sources.

Symbol Parameter

Condition

External 2MHz clock

Min.

Typ. ⁽¹⁾

2.0

Max.

Units

Wake-up time from idle,

standby, and extended standby

mode

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

External 2MHz clock

120

2.0

µs

0.2

t_wakeup

4.5

32.768kHz internal oscillator

2MHz internal oscillator

32MHz internal oscillator

320

9.0

Wake-up time from power-save

and power-down mode

µs

5.0

Note:

1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-23. All peripherals and modules

start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.

Figure 36-23.Wake-up time definition.

Wakeup time

Wakeup request

Clock output

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36.4.5 I/O Pin Characteristics

The I/O pins comply with the JEDEC LVTTL and LVCMOS specification and the high- and low level input and output

voltage limits reflect or exceed this specification.

Table 36-103.I/O pin characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

(1)

I_OH

/

I/O pin source/sink current

-20

20

mA

(2)

I_OL

V_CC= 2.7 - 3.6V

2.0

0.7*V_CC

0.8*V_CC

-0.3

V_CC+0.3

0.8

V_IH

High level input voltage

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 2.7- 3.6V

V_CC= 2.0 - 2.7V

V_CC= 1.6 - 2.0V

V_CC= 3.0 - 3.6V

V

V_IL

Low level input voltage

-0.3

0.3*V_CC

0.2*V_CC

-0.3

I_OH= -2mA

I_OH= -1mA

I_OH= -2mA

I_OH= -8mA

I_OH= -6mA

I_OH= -2mA

I_OL= 2mA

I_OL= 1mA

I_OL= 2mA

I_OL= 15mA

I_OL= 10mA

I_OL= 5mA

2.4

0.94*V_CC

0.96*V_CC

0.92*V_CC

2.9

2.0

V_CC= 2.3 - 2.7V

1.7

V_OH

High level output voltage

V

V_CC= 3.3V

2.6

V_CC= 3.0V

2.1

2.6

V_CC= 1.8V

1.4

1.6

V_CC= 3.0 - 3.6V

0.05

0.03

0.06

0.4

V_CC= 2.3 - 2.7V

0.7

V_OL

Low level output voltage

V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 1.8V

T = 25°C

0.76

0.64

0.46

0.1

0.3

0.2

I_IN

Input leakage current

<0.01

24

µA

R_P

Pull/buss keeper resistor

kΩ

4.0

t_r

Rise time

No load

ns

slew rate limitation

7.0

Notes:

1. The sum of all I_OHfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OHfor PORTC must not exceed 200mA.

The sum of all I_OHfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OHfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

2. The sum of all I_OLfor PORTA and PORTB must not exceed 100mA.

The sum of all I_OLfor PORTC must not exceed 200mA.

The sum of all I_OLfor PORTD and pins PE[0-1] on PORTE must not exceed 200mA.

The sum of all I_OLfor PE[2-3] on PORTE, PORTR and PDI must not exceed 100mA.

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36.4.6 ADC characteristics

Table 36-104.Power supply, reference and input range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1

Typ.

Max.

Units

V

AV_CC

V_REF

R_in

Analog supply voltage

Reference voltage

V_CC+ 0.3

AV_CC- 0.6

V

Input resistance

Switched

4.0

4.4

>10

7

kΩ

pF

MΩ

pF

V

C_sample

R_AREF

C_AREF

V_IN

Input capacitance

Switched

Reference input resistance

(leakage only)

Reference input capacitance Static load

Input range

-0.1

-V_REF

-ΔV

AV_CC+0.1

V_REF

Conversion range

Fixed offset voltage

Differential mode, Vinp - Vinn

V

Single ended unsigned mode, Vinp

V_REF-ΔV

V

∆V

190

lsb

Table 36-105.Clock and timing.

Symbol

Parameter

Condition

Min.

Typ.

Max.

Units

Maximum is 1/4 of Peripheral clock

frequency

100

2000

Clk_ADC

ADC Clock frequency

kHz

Measuring internal signals

Current limitation (CURRLIMIT) off

CURRLIMIT = LOW

100

0.25

125

2000

1500

1000

500

5

f_ADC

Sample rate

ksps

µs

CURRLIMIT = MEDIUM

CURRLIMIT = HIGH

Sampling time

1/2 Clk_ADCcycle

(RES+2)/2+(GAIN !=0)

RES (Resolution) = 8 or 12

Clk_ADC

cycles

Conversion time (latency)

5

8

Clk_ADC

cycles

Start-up time

ADC clock cycles

12

24

After changing reference or input mode

After ADC flush

7

1

7

1

Clk_ADC

cycles

ADC settling time

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Table 36-106. Accuracy characteristics.

Symbol

Parameter

Condition ⁽²⁾

Min.

Typ.

12

Max.

12

Units

Bits

lsb

RES

INL ⁽¹⁾

DNL ⁽¹⁾

Resolution

Programmable to 8 or 12 bit

8

V_CC-1.0V < V_REF< V_CC-0.6V

±1.2

±1.5

±1.0

±1.5

<±0.8

-1.0

<0.01

<0.6

-1

±2

500ksps

All V_REF

V_CC-1.0V < V_REF< V_CC-0.6V

All V_REF

±3

Integral non-linearity

±2

2000ksps

±3

Differential non-linearity

Offset error

guaranteed monotonic

<±1

lsb

mV

Temperature drift

mV/K

mV/V

Operating voltage drift

External reference

AV_CC/1.6

AV_CC/2.0

Bandgap

10

Differential

mode

mV

8.0

Gain error

±5

Temperature drift

<0.02

<0.5

mV/K

mV/V

Operating voltage drift

Differential mode, shorted input

2msps, V_CC= 3.6V, Clk_PER= 16MHz

mV

rms

Noise

0.4

Notes:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external V_REFis used.

Table 36-107. Gain stage characteristics.

Symbol

Parameter

Condition

Switched in normal mode

Gain stage output

Min.

Typ.

4.0

Max.

Units

kΩ

pF

R_in

Input resistance

Input capacitance

Signal range

C_sample

4.4

0

V_CC- 0.6

V

Clk_ADC

cycles

Propagation delay

Sample rate

ADC conversion rate

Same as ADC

500ksps

1.0

100

1000

±4.0

kHz

lsb

All gain

settings

INL ⁽¹⁾

Integral Non-Linearity

±1.5

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

-0.8

-2.5

-3.5

Gain error

%

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Symbol

Parameter

Condition

1x gain, normal mode

Min.

Typ.

-2.0

-5.0

-4.0

0.5

Max.

Units

Offset error,

input referred

8x gain, normal mode

64x gain, normal mode

1x gain, normal mode

8x gain, normal mode

64x gain, normal mode

mV

V_CC= 3.6V

Ext. V_REF

mV

rms

Noise

1.5

11

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.

36.4.7 DAC Characteristics

Table 36-108. Power supply, reference and output range.

Symbol Parameter Condition

Min.

V_CC- 0.3

1.0

Typ.

Max.

V_CC+ 0.3

V_CC- 0.6

50

Units

AV_CC

AV_REF

R_channel

Analog supply voltage

External reference voltage

DC output impedance

V

Ω

Linear output voltage range

Reference input resistance

Reference input capacitance Static load

Minimum Resistance load

0.15

AV_CC-0.15

V

R_AREF

>10

7.0

MΩ

pF

kΩ

pF

nF

CAREF

1

100

Maximum capacitance load

1000Ω serial resistance

1

AV_CC/1000

10

Operating within accuracy specification

Safe operation

Output sink/source

mA

Table 36-109. Clock and timing.

Symbol

Parameter

Condition

Min.

Typ.

Max.

1000

500

Units

Normal mode

0

C_load=100pF,

maximum step size

f_DAC

Conversion rate

ksps

Low power mode

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Table 36-110.Accuracy characteristics.

Symbol

Parameter

Condition

Min.

Typ.

Max.

12

Units

RES

Input resolution

Bits

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

V_CC= 1.6V

V_CC= 3.6V

±2.0

±1.5

±2.0

±1.5

±5.0

±1.5

±0.6

±1.0

±0.6

±4.5

<4.0

4.0

±3.0

±2.5

±4.0

V_REF= Ext 1.0V

V_REF=AV_CC

INL ⁽¹⁾

Integral non-linearity

lsb

V_REF=INT1V

V_REF=Ext 1.0V

V_REF=AV_CC

3.0

1.5

3.5

1.5

DNL ⁽¹⁾

Differential non-linearity

lsb

V_REF=INT1V

Gain error

After calibration

lsb

Gain calibration step size

Gain calibration drift

Offset error

V_REF= Ext 1.0V

After calibration

<0.2

<1.0

1.0

mV/K

lsb

Offset calibration step size

Note:

1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.

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36.4.8 Analog Comparator Characteristics

Table 36-111. Analog Comparator characteristics.

Symbol

V_off

Parameter

Condition

Min.

Typ.

<±10

<1

Max.

Units

mV

nA

Input offset voltage

Input leakage current

Input voltage range

AC startup time

I_lk

-0.1

AV_CC

V

100

0

µs

V_hys1

Hysteresis, none

mV

mode = High Speed (HS)

mode = Low Power (LP)

mode = HS

13

V_hys2

Hysteresis, small

Hysteresis, large

mV

30

V_hys3

mode = LP

60

V_CC= 3.0V, T= 85°C

mode = HS

V_CC= 3.0V, T= 85°C

mode = HS

30

90

500

0.5

30

t_delay

Propagation delay

ns

mode = LP

130

0.3

mode = LP

64-level voltage scaler

Integral non-linearity (INL)

lsb

36.4.9 Bandgap and Internal 1.0V Reference Characteristics

Table 36-112. Bandgap and Internal 1.0V reference characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

As reference for ADC or DAC

As input voltage to ADC and AC

1 Clk_PER+ 2.5µs

Startup time

µs

1.5

1.1

Bandgap voltage

V

INT1V

Internal 1.00V reference

Variation over voltage and temperature

T= 85°C, after calibration

0.99

1.0

1.01

Relative to T= 85°C, V_CC= 3.0V

±1.5

%

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36.4.10 Brownout Detection Characteristics

Table 36-113. Brownout detection characteristics.

Symbol Parameter

BOD level 0 falling V_CC

BOD level 1 falling V_CC

BOD level 2 falling V_CC

Condition

Min.

Typ.

1.62

1.8

Max.

Units

1.50

1.72

2.0

BOD level 3 falling V_CC

V_BOT

2.2

V

BOD level 4 falling V_CC

2.4

BOD level 5 falling V_CC

BOD level 6 falling V_CC

BOD level 7 falling V_CC

2.6

2.8

3.0

Continuous mode

Sampled mode

0.4

t_BOD

Detection time

Hysteresis

µs

%

1000

1.2

V_HYST

36.4.11 External Reset Characteristics

Table 36-114. External reset characteristics.

Symbol Parameter

Condition

Min.

Typ.

95

Max.

Units

t_EXT

Minimum reset pulse width

1000

ns

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 2.7V

0.60×V_CC

Reset threshold voltage (V_IH)

V_RST

V

0.50×V_CC

0.40×V_CC

Reset threshold voltage (V_IL)

Reset pin Pull-up Resistor

R_RST

25

kΩ

36.4.12 Power-on Reset Characteristics

Table 36-115. Power-on reset characteristics.

Symbol Parameter

Condition

Min.

0.4

Typ.

1.0

Max.

Units

V

V_CCfalls faster than 1V/ms

V_CCfalls at 1V/ms or slower

(1)

V_POT-

POR threshold voltage falling V_CC

0.8

1.0

V_POT+

POR threshold voltage rising V_CC

1.3

1.59

mV

Note:

1. V_POT-values are only valid when BOD is disabled. When BOD is enabled V_POT-= V_POT+.

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36.4.13 Flash and EEPROM Memory Characteristics

Table 36-116. Endurance and data retention.

Symbol Parameter

Condition

Min.

10K

2K

Typ.

Max.

Units

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

25°C

85°C

105°C

Write/Erase cycles

Cycle

Flash

100

25

Data retention

Year

Cycle

Year

10

100K

30K

100

25

Write/Erase cycles

Data retention

EEPROM

10

Table 36-117. Programming time.

Symbol Parameter

Chip Erase

Condition

Min.

Typ.⁽¹⁾

Max.

Units

ms

128KB Flash, EEPROM⁽²⁾and SRAM Erase

Section erase

75

6

Application Erase

ms

Page erase

4

Flash

Page write

4

ms

Atomic page erase and write

Page erase

8

4

EEPROM

Page write

4

Atomic page erase and write

8

Notes:

1. Programming is timed from the 2MHz internal oscillator.

2. EEPROM is not erased if the EESAVE fuse is programmed.

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36.4.14 Clock and Oscillator Characteristics

36.4.14.1 Calibrated 32.768kHz Internal Oscillator characteristics

Table 36-118. 32.768kHz internal oscillator characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

Units

kHz

%

Frequency

32.768

Factory calibration accuracy T = 85°C, V_CC= 3.0V

-0.5

0.5

User calibration accuracy

%

36.4.14.2 Calibrated 2MHz RC Internal Oscillator characteristics

Table 36-119. 2MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

1.8

2.2

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration stepsize

2.0

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.21

%

36.4.14.3 Calibrated and tunable 32MHz internal oscillator characteristics

Table 36-120. 32MHz internal oscillator characteristics.

Symbol Parameter

Frequency range

Condition

Min.

Typ.

Max.

Units

DFLL can tune to this frequency over

voltage and temperature

30

55

MHz

Factory calibrated frequency

Factory calibration accuracy

User calibration accuracy

DFLL calibration step size

32

MHz

%

T = 85°C, V_CC= 3.0V

-1.5

-0.2

1.5

0.2

%

0.22

%

36.4.14.4 32kHz Internal ULP Oscillator characteristics

Table 36-121. 32kHz internal ULP oscillator characteristics.

Symbol Parameter

Output frequency

Accuracy

Condition

Min.

Typ.

Max.

Units

kHz

%

32

-30

30

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36.4.14.5 Internal Phase Locked Loop (PLL) characteristics

Table 36-122. Internal PLL characteristics.

Symbo

l

Parameter

Condition

Output frequency must be within f_OUT

V_CC= 1.6 - 1.8V

Min.

0.4

20

Typ.

Max.

64

Units

f_IN

Input frequency

MHz

48

f_OUT

Output frequency ⁽¹⁾

MHz

V_CC= 2.7 - 3.6V

20

128

Start-up time

Re-lock time

25

µs

Note:

1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than four times the maximum CPU frequency.

36.4.14.6 External clock characteristics

Figure 36-24. External clock drive waveform

t_CH

t_CR

t_CF

V_IH1

V_IL1

t_CL

t_CK

Table 36-123.External clock used as system clock without prescaling.

Symbol

Parameter

Condition

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

Min.

0

Typ.

Max.

12

Units

1/t_CK

Clock Frequency ⁽¹⁾

MHz

0

32

83.3

31.5

30.0

12.5

30.0

12.5

t_CK

t_CH

t_CL

t_CR

Clock Period

ns

Clock High Time

Clock Low Time

10

3

Rise Time (for maximum frequency)

10

3

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

10

Note:

1. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

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Table 36-124. External clock with prescaler ⁽¹⁾for system clock.

Symbol Parameter Condition

Clock Frequency ⁽²⁾

Min.

0

Typ.

Max.

90

Units

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

V_CC= 1.6 - 1.8V

V_CC= 2.7 - 3.6V

1/t_CK

MHz

0

142

11

7

t_CK

Clock Period

ns

4.5

2.4

4.5

2.4

t_CH

Clock High Time

t_CL

Clock Low Time

1.5

1.0

1.5

1.0

10

t_CR

Rise Time (for maximum frequency)

t_CF

Fall Time (for maximum frequency)

ns

%

Δt_CK

Change in period from one clock cycle to the next

Notes:

1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.

2. The maximum frequency vs. supply voltage is linear between 1.6V and 2.7V, and the same applies for all other parameters with supply voltage conditions.

36.4.14.7 External 16MHz crystal oscillator and XOSC characteristic

Table 36-125. External 16MHz crystal oscillator and XOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

<10

Max.

Units

FRQRANGE=0

XOSCPWR=0

XOSCPWR=1

XOSCPWR=0

XOSCPWR=1

Cycle to cycle jitter

FRQRANGE=1, 2, or 3

<1

ns

<1

FRQRANGE=0

<6

Long term jitter

Frequency error

FRQRANGE=1, 2, or 3

<0.5

<0.1

<0.05

<0.005

ns

%

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

XOSCPWR=0

XOSCPWR=1

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Symbol Parameter

Condition

Min.

Typ.

40

Max.

Units

FRQRANGE=0

FRQRANGE=1

FRQRANGE=2 or 3

XOSCPWR=0

XOSCPWR=1

42

Duty cycle

%

45

48

0.4MHz resonator,

CL=100pF

2.4k

XOSCPWR=0,

FRQRANGE=0

1MHz crystal, CL=20pF

2MHz crystal, CL=20pF

2MHz crystal

8.7k

2.1k

4.2k

250

195

360

285

155

365

200

105

435

235

125

495

270

145

305

XOSCPWR=0,

FRQRANGE=1,

CL=20pF

8MHz crystal

9MHz crystal

8MHz crystal

XOSCPWR=0,

FRQRANGE=2,

CL=20pF

9MHz crystal

12MHz crystal

9MHz crystal

XOSCPWR=0,

FRQRANGE=3,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

Negative impedance ⁽¹⁾

Ω

R_Q

XOSCPWR=1,

FRQRANGE=0,

CL=20pF

12MHz crystal

16MHz crystal

9MHz crystal

XOSCPWR=1,

FRQRANGE=1,

CL=20pF

12MHz crystal

16MHz crystal

12MHz crystal

XOSCPWR=1,

FRQRANGE=2,

CL=20pF

16MHz crystal

12MHz crystal

16MHz crystal

160

380

205

XOSCPWR=1,

FRQRANGE=3,

CL=20pF

ESR

SF = Safety factor

min(RQ)/SF

kΩ

Parasitic capacitance

XTAL1 pin

C_XTAL1

C_XTAL2

C_LOAD

5.45

7.51

3.16

pF

Parasitic capacitance

XTAL2 pin

pF

Parasitic capacitance

load

Note:

1. Numbers for negative impedance are not tested in production but guaranteed from design and characterization.

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36.4.14.8 External 32.768kHz crystal oscillator and TOSC characteristics

Table 36-126. External 32.768kHz crystal oscillator and TOSC characteristics.

Symbol Parameter

Condition

Min.

Typ.

Max.

60

Units

Crystal load capacitance 6.5pF

Crystal load capacitance 9.0pF

Recommended crystal equivalent

ESR/R1

C_TOSC1

C_TOSC2

kΩ

series resistance (ESR)

35

5.4

4.0

7.1

4.0

Parasitic capacitance TOSC1 pin

pF

Alternate TOSC location

Parasitic capacitance TOSC2 pin

Recommended safety factor

Alternate TOSC location

capacitance load matched to

crystal specification

3

Note:

1. See Figure 36-25 for definition.

Figure 36-25. TOSC input capacitance.

C_L1

C_L2

Device internal

External

TOSC1

TOSC2

32.768kHz crystal

The parasitic capacitance between the TOSC pins is C_L1+ C_L2in series as seen from the crystal when oscillating

without external capacitors.

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36.4.15 SPI Characteristics

Figure 36-26. SPI timing requirements in master mode.

SS

t_MOS

t_SCKR

t_SCKF

SCK

(CPOL = 0)

t_SCKW

SCK

(CPOL = 1)

t_SCKW

t_MIS

t_MIH

t_SCK

MISO

(Data input)

MSB

LSB

t_MOH

MOSI

(Data output)

MSB

LSB

Figure 36-27. SPI timing requirements in slave mode.

SS

t_SSS

t_SCKR

t_SCKF

t_SSH

SCK

(CPOL = 0)

t_SSCKW

SCK

(CPOL = 1)

t_SSCKW

t_SIS

t_SIH

t_SSCK

MOSI

(Data input)

MSB

LSB

t_SOSSS

t_SOS

t_SOSSH

MISO

(Data output)

MSB

LSB

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Table 36-127. SPI timing characteristics and requirements.

Symbol Parameter Condition

Min.

Typ.

Max.

Units

(See Table 21-4 in

XMEGA AU Manual)

t_SCK

SCK Period

Master

t_SCKW

t_SCKR

t_SCKF

t_MIS

SCK high/low width

SCK Rise time

Master

Slave

0.5×SCK

2.7

SCK Fall time

2.7

MISO setup to SCK

MISO hold after SCK

MOSI setup SCK

MOSI hold after SCK

Slave SCK Period

SCK high/low width

SCK Rise time

10

t_MIH

10

0.5×SCK

1

t_MOS

t_MOH

t_SSCK

t_SSCKW

t_SSCKR

t_SSCKF

t_SIS

4×t Clk_PER

2×t Clk_PER

ns

1600

SCK Fall time

MOSI setup to SCK

MOSI hold after SCK

SS setup to SCK

3

t Clk_PER

21

t_SIH

t_SSS

t_SSH

SS hold after SCK

MISO setup SCK

MISO hold after SCK

MISO setup after SS low

MISO hold after SS high

20

t_SOS

8

13

11

8

t_SOH

t_SOSS

t_SOSH

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36.4.16 Two-Wire Interface Characteristics

Table 36-128 describes the requirements for devices connected to the Two-Wire Interface Bus. The Atmel AVR

XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions. Timing symbols refer

to Figure 36-28.

Figure 36-28. Two-wire interface bus timing.

t_of

t_HIGH

t_LOW

t_r

SCL

SDA

t_HD;DAT

t_SU;STA

t_SU;STO

t_SU;DAT

t_HD;STA

t_BUF

Table 36-128. Two-wire interface characteristics.

Symbol Parameter

Condition

Min.

0.7V_CC

0.5

Typ.

Max.

Units

V

V_IH

V_IL

Input High Voltage

V_CC+0.5

0.3×V_CC

Input Low Voltage

V

(1)

V_hys

Hysteresis of Schmitt Trigger Inputs

Output Low Voltage

0.05V_CC

0

V

V_OL

3mA, sink current

0.4

300

250

50

V

(1)(2)

t_r

t_of

Rise Time for both SDA and SCL

Output Fall Time from V_IHminto V_ILmax

Spikes Suppressed by Input Filter

Input Current for each I/O Pin

Capacitance for each I/O Pin

SCL Clock Frequency

20+0.1C_b

0

ns

µA

pF

kHz

10pF < C_b< 400pF ⁽²⁾

0.1V_CC< V_I< 0.9V_CC

t_SP

I_I

-10

10

C_I

10

f_SCL

f_PER⁽³⁾>max(10f_SCL, 250kHz)

0

400

f_SCL≤ 100kHz

100ns

C_b

--------------

V_CC– 0.4V

---------------------------

3mA

R_P

Value of Pull-up resistor

Ω

300ns

f_SCL> 100kHz

--------------

C_b

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

4.0

0.6

4.7

1.3

4.0

0.6

4.7

0.6

t_HD;STA

Hold Time (repeated) START condition

Low Period of SCL Clock

µs

t_LOW

t_HIGH

High Period of SCL Clock

Set-up time for a repeated START

condition

t_SU;STA

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Symbol Parameter

Condition

f_SCL≤ 100kHz

Min.

0

Typ.

Max.

3.45

0.9

Units

t_HD;DAT

t_SU;DAT

t_SU;STO

t_BUF

Data hold time

µs

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

f_SCL≤ 100kHz

f_SCL> 100kHz

0

250

100

4.0

0.6

4.7

1.3

Data setup time

ns

µs

Setup time for STOP condition

Bus free time between a STOP and

START condition

Notes:

1. Required only for f_SCL> 100kHz.

2. C_b= Capacitance of one bus line in pF.

3.

f_PER= Peripheral clock frequency.

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37. Typical Characteristics

37.1 ATxmega16A4U

37.1.1 Current consumption

37.1.1.1 Active mode supply current

Figure 37-1. Active supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

600

540

480

420

360

300

240

180

120

60

3.3V

3.0V

2.7V

2.2V

1.8V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [MHz]

Figure 37-2. Active supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

12

10

8

3.3V

3.0V

2.7V

6

2.2V

4

1.8V

2

0

4

8

12

16

20

24

28

32

Frequency [MHz]

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Figure 37-3. Active mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

270

250

230

210

190

170

150

130

110

90

-40 °C

25 °C

85 °C

105 °C

70

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-4. Active mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

800

700

600

500

400

300

200

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

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Figure 37-5. Active mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator.

1600

1400

1200

1000

800

-40 °C

25 °C

85 °C

105 °C

600

400

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-6. Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

5900

-40 °C

25 °C

5400

4900

4400

3900

3400

2900

2400

1900

1400

85 °C

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

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Figure 37-7. Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

5650

5425

5200

4975

4750

4525

4300

4075

3850

3625

3400

-40 °C

25 °C

85 °C

105 °C

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

V_CC[V]

37.1.1.2 Idle mode supply current

Figure 37-8. Idle mode supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

140

120

100

80

3.3V

3.0V

2.7V

2.2V

1.8V

60

40

20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency [MHz]

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Figure 37-9. Idle mode supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

3.3V

3.0V

2.7V

2.2V

1.8V

0.5

0

4

8

12

16

20

24

28

32

Frequency [MHz]

Figure 37-10. Idle mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

35

34

33

32

31

30

29

28

27

105 °C

-40 °C

85 °C

25 °C

1.6

1.8

2

2.2

2.4

2.6

V_CC[V]

2.8

3

3.2

3.4

3.6

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Figure 37-11. Idle mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

158

146

134

122

110

98

105 °C

85 °C

25 °C

-40 °C

86

74

62

50

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-12. Idle mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator.

410

385

360

335

310

285

260

235

210

185

160

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

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Figure 37-13. Idle mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

2000

-40 °C

25 °C

1800

1600

1400

1200

1000

800

85 °C

105 °C

600

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-14. Idle mode current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

5650

5425

5200

4975

4750

4525

4300

4075

3850

3625

3400

-40 °C

25 °C

85 °C

105 °C

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

V_CC[V]

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37.1.1.3 Power-down mode supply current

Figure 37-15. Power-down mode supply current vs. temperature.

All functions disabled.

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-16. Power-down mode supply current vs. V_CC

.

All functions disabled.

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

105 °C

85 °C

25 °C

-

40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

VCC [V]

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Figure 37-17. Power-down mode supply current vs. V_CC

.

Watchdog and sampled BOD enabled.

5.1

4.6

4.1

3.6

3.1

2.6

2.1

1.6

1.1

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

37.1.1.4 Power-save mode supply current

Figure 37-18. Power-save mode supply current vs.V_CC

.

Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.

0.9

Normal mode

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Low-power mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

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37.1.1.5 Standby mode supply current

Figure 37-19. Standby supply current vs. V_CC

.

Standby, f_SYS= 1MHz.

12.5

11.5

10.5

9.5

105 °C

85 °C

8.5

25 °C

-40 °C

7.5

6.5

5.5

4.5

3.5

2.5

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-20. Standby supply current vs. V_CC

.

25°C, running from different crystal oscillators.

480

440

400

360

320

280

240

200

160

16MHz

12MHz

8MHz

2MHz

0.454MHz

3.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.6

V_CC[V]

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37.1.2 I/O Pin Characteristics

37.1.2.1 Pull-up

Figure 37-21. I/O pin pull-up resistor current vs. input voltage.

V_CC= 1.8V.

72

64

56

48

40

32

24

16

8

-40 °C

25 °C

85 °C

105 °C

0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

V_PIN[V]

Figure 37-22. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.0V.

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

V_PIN[V]

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Figure 37-23. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.3V.

135

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

V_PIN[V]

37.1.2.2 Output Voltage vs. Sink/Source Current

Figure 37-24. I/O pin output voltage vs. source current.

V_CC= 1.8V.

1.8

1.6

1.4

1.2

1.0

0.8

-40 °C

25 °C

0.6

0.4

0.2

0.0

105 °C

85 °C

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

I_PIN[mA]

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Figure 37-25. I/O pin output voltage vs. source current.

V_CC= 3.0V.

3.0

2.7

2.4

2.1

1.8

1.5

1.2

-40°C

0.9

25 °C

85 °C

0.6

105 °C

0.3

0.0

-32

-28

-24

-20

-16

-12

-8

-4

0

I_PIN[mA]

Figure 37-26. I/O pin output voltage vs. source current.

V_CC= 3.3V.

3.3

3.0

2.7

2.4

2.1

1.8

1.5

-40 °C

1.2

0.9

0.6

0.3

0.0

25 °C

105 °C

85 °C

-32

-28

-24

-20

-16

-12

-8

-4

0

I_PIN[mA]

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Figure 37-27. I/O pin output voltage vs. source current.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.6V

3.3V

3.0V

2.7V

2.3V

1.8V

-24

-21

-18

-15

-12

-9

-6

-3

0

I_PIN[mA]

Figure 37-28. I/O pin output voltage vs. sink current.

V_CC= 1.8V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

2

4

6

8

10

12

14

16

I_PIN[mA]

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Figure 37-29. I/O pin output voltage vs. sink current.

V_CC= 3.0V.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

2

4

6

8

10

12

14

16

18

20

I_PIN[mA]

Figure 37-30. I/O pin output voltage vs. sink current.

V_CC= 3.3V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

4

8

12

16

20

24

28

32

I_PIN[mA]

Figure 37-31. I/O pin output voltage vs. sink current.

1.5

1.8V

1.2

0.9

0.6

0.3

0

2.3V

2.7V

3.0V

3.3V

3.6V

0

5

10

15

20

25

30

I_PIN[mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

173

37.1.2.3 Thresholds and Hysteresis

Figure 37-32. I/O pin input threshold voltage vs. V_CC.

T = 25°C.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VIH

VIL

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Vcc [V]

Figure 37-33. I/O pin input threshold voltage vs. V_CC

.

V_IHI/O pin read as “1”.

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

174

Figure 37-34. I/O pin input threshold voltage vs. V_CC

.

V_ILI/O pin read as “0”.

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-35. I/O pin input hysteresis vs. V_CC

.

0.32

0.29

0.26

0.23

-40 °C

25 °C

0.20

0.17

85 °C

0.14

0.11

105 °C

0.08

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

175

37.1.3 ADC Characteristics

Figure 37-36. INL error vs. external V_REF

.

T = 25°C, V_CC= 3.6V, external reference.

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

Differential Signed

Single-ended Unsigned

0.9

0.8

0.7

Single-ended Signed

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

Figure 37-37. INL error vs. sample rate.

T = 25°C, V_CC= 3.6V, V_REF= 3.0V external.

1.4

1.35

1.3

Differential Mode

1.25

1.2

Single-ended Unsigned

1.15

1.1

1.05

1

Single-ended Signed

0.95

0.9

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC Sample Rate [kSPS]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

176

Figure 37-38. INL error vs. input code

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

0

512

1024

1536

2048

2560

3072

3584

4096

ADC input code

Figure 37-39. DNL error vs. external V_REF

.

T = 25°C, V_CC= 3.6V, external reference.

0.9

0.88

0.86

0.84

0.82

0.8

Differential Mode

Single-ended Signed

0.78

0.76

0.74

0.72

Single-ended Unsigned

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

177

Figure 37-40. DNL error vs. sample rate.

T = 25°C, V_CC= 3.6V, V_REF= 3.0V external.

0.9

0.89

0.88

0.87

0.86

0.85

0.84

0.83

0.82

0.81

0.8

Differential Signed

Single-ended Signed

Single-ended Unsigned

0.79

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC Sample Rate [kSPS]

Figure 37-41. DNL error vs. input code.

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

0

512

1024

1536

2048

2560

3072

3584

4096

ADC Input Code

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

178

Figure 37-42. Gain error vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

3

Single-ended Signed

Differential Mode

2

1

0

-1

-2

-3

-4

Single-ended Unsigned

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

_REF[V]

V

Figure 37-43. Gain error vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

2.2

1.9

1.6

1.3

1

Single-ended Signed

Differential Mode

0.7

0.4

0.1

-0.2

-0.5

Single-ended Unsigned

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

179

Figure 37-44. Offset error vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

-1

-1.1

-1.2

-1.3

-1.4

-1.5

-1.6

-1.7

-1.8

-1.9

-2

Differential Mode

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

_REF[V]

V

Figure 37-45. Gain error vs. temperature.

V_CC= 3.0V, V_REF= external 2.0V.

4

3

2

1

0

Single-ended signed mode

Differential mode

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

-1

-2

-3

-4

Single-ended unsigned mode

Temperature [ºC]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

180

Figure 37-46. Offset error vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

Differential Signed

-1.1

-1.2

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-47. Noise vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

1.3

Single-ended Signed

1.15

1

Single-ended Unsigned

0.85

0.7

0.55

0.4

Differential Signed

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

181

Figure 37-48. Noise vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

1.3

1.2

1.1

1

Single-ended Signed

0.9

0.8

0.7

0.6

0.5

0.4

0.3

Single-ended Unsigned

Differential Signed

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

37.1.4 DAC Characteristics

Figure 37-49. DAC INL error vs. V_REF

.

V_CC= 3.6V.

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-40°C

25°C

85°C

105°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

182

Figure 37-50. DNL error vs. V_REF

.

V_CC= 3.6V.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

- 40°C

25ºC

85°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

Figure 37-51. DAC noise vs. temperature.

V_CC= 3.0V, V_REF= 2.4V .

0.185

0.180

0.175

0.170

0.165

0.160

0.155

0.150

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [ºC]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

183

37.1.5 Analog Comparator Characteristics

Figure 37-52. Analog comparator hysteresis vs. V_CC

.

High-speed, small hysteresis.

18

17

16

15

14

13

12

11

10

9

105 °C

85 °C

-40 C

°

25 C

8

7

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-53. Analog comparator hysteresis vs. V_CC

.

Low power, small hysteresis.

35

34

33

32

31

30

29

28

27

26

25

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

184

Figure 37-54. Analog comparator hysteresis vs. V_CC

.

High-speed mode, large hysteresis.

42

40

38

36

34

32

30

28

26

24

22

20

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-55. Analog comparator hysteresis vs. V_CC

.

Low power, large hysteresis.

77

74

71

68

65

62

59

56

53

50

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

185

Figure 37-56. Analog comparator current source vs. calibration value.

Temperature = 25°C.

7.4

6.8

6.2

5.6

5.0

4.4

3.8

3.2

2.6

2.0

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CURRCALIBA[3..0]

Figure 37-57. Analog comparator current source vs. calibration value.

V_CC= 3.0V.

CC

7

6.5

6

5.5

5

-40 °C

4.5

4

25 °C

85 °C

105 °C

3.5

3

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CURRCALIBA[3..0]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

186

Figure 37-58. Voltage scaler INL vs. SCALEFAC.

T = 25°C, V_CC= 3.0V.

0.050

0.025

0

-0.025

-0.050

-0.075

-0.100

-0.125

-0.150

25°C

0

10

20

30

40

50

60

70

SCALEFAC

37.1.6 Internal 1.0V reference Characteristics

Figure 37-59. ADC/DAC Internal 1.0V reference vs. temperature.

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

0.988

0.986

1.6 V

1.8 V

2.2 V

2.7 V

3.0 V

3.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

187

37.1.7 BOD Characteristics

Figure 37-60. BOD thresholds vs. temperature.

BOD level = 1.6V.

1.635

Rising Vcc

Falling Vcc

1.630

1.625

1.620

1.615

1.610

1.605

1.600

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-61. BOD thresholds vs. temperature.

BOD level = 3.0V.

3.06

3.05

3.04

3.03

3.02

3.01

3.00

2.99

2.98

2.97

Rising Vcc

Falling Vcc

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

188

37.1.8 External Reset Characteristics

Figure 37-62. Minimum Reset pin pulse width vs. V_CC

.

130

125

120

115

110

105

100

95

105 °C

85 °C

90

25 °C

-40 °C

85

80

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

Figure 37-63. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 1.8V.

72

64

56

48

40

32

24

16

8

-40 °C

25 °C

85 °C

105 °C

0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

V_RESET[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

189

Figure 37-64. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 3.0V.

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

V_RESET[V]

Figure 37-65. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 3.3V.

140

120

100

80

60

40

-40 °C

25 °C

85 °C

105 °C

20

0

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

V_RESET[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

190

Figure 37-66. Reset pin input threshold voltage vs. V_CC.

V_IH- Reset pin read as “1”.

2.20

2.05

1.90

1.75

1.60

1.45

1.30

1.15

1.00

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-67. Reset pin input threshold voltage vs. V_CC.

V_IL- Reset pin read as “0”.

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

0.40

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

191

37.1.9 Power-on Reset Characteristics

Figure 37-68. Power-on reset current consumption vs. V_CC

.

BOD level = 3.0V, enabled in continuous mode.

700

600

500

400

300

200

100

0

-40 °C

25 °C

85 °C

105 °C

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

V_CC[V]

Figure 37-69. Power-on reset current consumption vs. V_CC

.

BOD level = 3.0V, enabled in sampled mode.

650

585

520

455

390

325

260

195

130

65

-40 °C

25 °C

85°C

°

105°°C

0

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

192

37.1.10 Oscillator Characteristics

37.1.10.1 Ultra Low-Power internal oscillator

Figure 37-70. Ultra Low-Power internal oscillator frequency vs. temperature.

32.8

32.4

32.0

31.6

31.2

30.8

30.4

30.0

29.6

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

37.1.10.2 32.768kHz Internal Oscillator

Figure 37-71. 32.768kHz internal oscillator frequency vs. temperature.

32.875

32.850

32.825

32.800

32.775

32.750

32.725

32.700

32.675

32.650

3.6 V

3.0 V

2.2 V

2.7 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

193

Figure 37-72. 32.768kHz internal oscillator frequency vs. calibration value.

V_CC= 3.0V, T = 25°C.

55

50

45

40

35

30

25

20

0

26

52

78

104

130

156

182

208

234

260

RC32KCAL[7..0]

37.1.10.3 2MHz Internal Oscillator

Figure 37-73. 2MHz internal oscillator frequency vs. temperature.

DFLL disabled.

2.16

2.14

2.12

2.10

2.08

2.06

2.04

2.02

2.00

1.98

1.96

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

194

Figure 37-74. 2MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator .

2.0085

2.0070

2.0055

2.0040

2.0025

2.0010

1.9995

1.9980

1.9965

1.9950

3.6 V

1.6 V

2.2 V

1.8 V

3.0 V

2.7 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-75. 2MHz internal oscillator CALA calibration step size.

V_CC= 3V.

0.31 %

0.29 %

0.27 %

0.25 %

0.23 %

0.21 %

0.19 %

0.17 %

0.15 %

-40 °C

25 °C

85 °C

105 °C

0

16

32

48

64

80

96

112

128

CALA

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

195

37.1.10.4 32MHz Internal Oscillator

Figure 37-76. 32MHz internal oscillator frequency vs. temperature.

DFLL disabled.

36.0

35.5

35.0

34.5

34.0

33.5

33.0

32.5

32.0

31.5

31.0

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-77. 32MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator.

32.145

32.120

32.095

32.070

32.045

32.020

31.995

31.970

31.945

31.920

3.6 V

1.6 V

1.8 V

2.2 V

2.7 V

3.0 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

196

Figure 37-78. 32MHz internal oscillator CALA calibration step size.

V_CC= 3.0V.

0.38 %

0.34 %

0.30 %

0.26 %

0.22 %

0.18 %

0.14 %

0.10 %

85°C

105°C

25°C

-40°C

0

16

32

48

64

80

96

112

128

CALA

Figure 37-79. 32MHz internal oscillator frequency vs. CALB calibration value.

V_CC= 3.0V.

75

70

65

60

55

50

45

40

35

30

25

- 40°C

25°C

85°C

105°C

0

8

16

24

32

40

48

56

64

CALB

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

197

37.1.10.5 32MHz internal oscillator calibrated to 48MHz

Figure 37-80. 48MHz internal oscillator frequency vs. temperature.

DFLL disabled.

54

53

52

51

50

49

48

47

46

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-81. 48MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator.

48.25

48.20

48.15

48.10

48.05

48.00

47.95

47.90

47.85

47.80

3.6 V

1.6 V

1.8 V

2.7 V

2.2 V

3.0 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

198

Figure 37-82. 48MHz internal oscillator CALA calibration step size.

V_CC= 3.0V.

CC

0.34 %

0.31 %

0.28 %

0.25 %

0.22 %

0.19 %

0.16 %

0.13 %

0.10 %

-40 °C

25 °C

85 °C

105 °C

0

16

32

48

64

80

96

112

128

CALA

37.1.11 Two-Wire Interface characteristics

Figure 37-83. SDA hold time vs. supply voltage.

300

295

290

285

280

275

270

265

260

105°C

85°C

25°C

- 40°C

2.6

2.7

2.8

2.9

3.0

3.1

Vcc [V]

3.2

3.3

3.4

3.5

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

199

37.1.12 PDI characteristics

Figure 37-84. Maximum PDI frequency vs. V_CC

.

34

31

28

25

22

19

16

13

10

25 °C

105 °C

-40 °C

85 °C

1.6

1.8

2

2.2

2.4

2.6

V_CC[V]

2.8

3

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

200

37.2 ATxmega32A4U

37.2.1 Current consumption

37.2.1.1 Active mode supply current

Figure 37-85.Active supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

600

540

480

420

360

300

240

180

120

60

3.3V

3.0V

2.7V

2.2V

1.8V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [MHz]

Figure 37-86.Active supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

12

10

8

3.3V

3.0V

2.7V

6

2.2V

4

1.8V

2

0

4

8

12

16

20

24

28

32

Frequency [MHz]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

201

Figure 37-87.Active mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

270

250

230

210

190

170

150

130

110

90

-40 °C

25 °C

85 °C

105 °C

70

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-88.Active mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

800

700

600

500

400

300

200

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

202

Figure 37-89.Active mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator.

1600

1400

1200

1000

800

-40 °C

25 °C

85 °C

105 °C

600

400

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-90.Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

5900

-40 °C

25 °C

5400

4900

4400

3900

3400

2900

2400

1900

1400

85 °C

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

203

Figure 37-91.Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

5650

5425

5200

4975

4750

4525

4300

4075

3850

3625

3400

-40 °C

25 °C

85 °C

105 °C

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

V_CC[V]

37.2.1.2 Idle mode supply current

Figure 37-92.Idle mode supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

140

120

100

80

3.3V

3.0V

2.7V

2.2V

1.8V

60

40

20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

Frequency [MHz]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

204

Figure 37-93.Idle mode supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

3.3V

3.0V

2.7V

2.2V

1.8V

0.5

0

4

8

12

16

20

24

28

32

Frequency [MHz]

Figure 37-94. Idle mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

35

34

33

32

31

30

29

28

27

105 °C

-40 °C

85 °C

25 °C

1.6

1.8

2

2.2

2.4

2.6

V_CC[V]

2.8

3

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

205

Figure 37-95. Idle mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

158

146

134

122

110

98

105 °C

85 °C

25 °C

-40 °C

86

74

62

50

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-96. Idle mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator.

410

385

360

335

310

285

260

235

210

185

160

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

206

Figure 37-97. Idle mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

2000

-40 °C

25 °C

1800

1600

1400

1200

1000

800

85 °C

105 °C

600

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-98. Idle mode current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

5650

5425

5200

4975

4750

4525

4300

4075

3850

3625

3400

-40 °C

25 °C

85 °C

105 °C

2.7

2.8

2.9

3

3.1

3.2

3.3

3.4

3.5

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

207

37.2.1.3 Power-down mode supply current

Figure 37-99. Power-down mode supply current vs. temperature.

All functions disabled.

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-100. Power-down mode supply current vs. V_CC

.

All functions disabled.

3.6

3.2

2.8

2.4

2.0

1.6

1.2

0.8

0.4

0.0

105 °C

85 °C

25 °C

-

40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

VCC [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

208

Figure 37-101. Power-down mode supply current vs. V_CC

.

Watchdog and sampled BOD enabled.

5.1

4.6

4.1

3.6

3.1

2.6

2.1

1.6

1.1

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

37.2.1.4 Power-save mode supply current

Figure 37-102. Power-save mode supply current vs.V_CC

.

Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.

0.9

Normal mode

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Low-power mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

209

37.2.1.5 Standby mode supply current

Figure 37-103. Standby supply current vs. V_CC

.

Standby, f_SYS= 1MHz.

12.5

11.5

10.5

9.5

105 °C

85 °C

8.5

25 °C

-40 °C

7.5

6.5

5.5

4.5

3.5

2.5

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-104. Standby supply current vs. V_CC

.

25°C, running from different crystal oscillators.

480

440

400

360

320

280

240

200

160

16MHz

12MHz

8MHz

2MHz

0.454MHz

3.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

210

37.2.2 I/O Pin Characteristics

37.2.2.1 Pull-up

Figure 37-105. I/O pin pull-up resistor current vs. input voltage.

V_CC= 1.8V.

72

64

56

48

40

32

24

16

8

-40 °C

25 °C

85 °C

105 °C

0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

V_PIN[V]

Figure 37-106. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.0V.

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

V_PIN[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

211

Figure 37-107. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.3V.

135

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

V_PIN[V]

37.2.2.2 Output Voltage vs. Sink/Source Current

Figure 37-108. I/O pin output voltage vs. source current.

V_CC= 1.8V.

1.8

1.6

1.4

1.2

1.0

0.8

-40 °C

25 °C

0.6

0.4

0.2

0.0

105 °C

85 °C

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

I_PIN[mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

212

Figure 37-109. I/O pin output voltage vs. source current.

V_CC= 3.0V.

3.0

2.7

2.4

2.1

1.8

1.5

1.2

-40°C

0.9

25 °C

85 °C

0.6

105 °C

0.3

0.0

-32

-28

-24

-20

-16

-12

-8

-4

0

I_PIN[mA]

Figure 37-110. I/O pin output voltage vs. source current.

V_CC= 3.3V.

3.3

3.0

2.7

2.4

2.1

1.8

1.5

-40 °C

1.2

0.9

0.6

0.3

0.0

25 °C

105 °C

85 °C

-32

-28

-24

-20

-16

-12

-8

-4

0

I_PIN[mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

213

Figure 37-111. I/O pin output voltage vs. source current.

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

3.6V

3.3V

3.0V

2.7V

2.3V

1.8V

-24

-21

-18

-15

-12

-9

-6

-3

0

I_PIN[mA]

Figure 37-112. I/O pin output voltage vs. sink current.

V_CC= 1.8V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

2

4

6

8

10

12

14

16

I_PIN[mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

214

Figure 37-113. I/O pin output voltage vs. sink current.

V_CC= 3.0V.

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

2

4

6

8

10

12

14

16

18

20

I_PIN[mA]

Figure 37-114. I/O pin output voltage vs. sink current.

V_CC= 3.3V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

4

8

12

16

20

24

28

32

I_PIN[mA]

Figure 37-115. I/O pin output voltage vs. sink current.

1.5

1.8V

1.2

0.9

0.6

0.3

0

2.3V

2.7V

3.0V

3.3V

3.6V

0

5

10

15

20

25

30

I_PIN[mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

215

37.2.2.3 Thresholds and Hysteresis

Figure 37-116. I/O pin input threshold voltage vs. V_CC.

T = 25°C.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VIH

VIL

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Vcc [V]

Figure 37-117. I/O pin input threshold voltage vs. V_CC

.

V_IHI/O pin read as “1”.

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

216

Figure 37-118. I/O pin input threshold voltage vs. V_CC

.

V_ILI/O pin read as “0”.

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-119. I/O pin input hysteresis vs. V_CC

.

0.32

0.29

0.26

0.23

-40 °C

25 °C

0.20

0.17

85 °C

0.14

0.11

105 °C

0.08

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

217

37.2.3 ADC Characteristics

Figure 37-120. INL error vs. external V_REF

.

T = 25°C, V_CC= 3.6V, external reference.

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

Differential Signed

Single-ended Unsigned

0.9

0.8

0.7

Single-ended Signed

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

Figure 37-121. INL error vs. sample rate.

T = 25°C, V_CC= 3.6V, V_REF= 3.0V external.

1.4

1.35

1.3

Differential Mode

1.25

1.2

Single-ended Unsigned

1.15

1.1

1.05

1

Single-ended Signed

0.95

0.9

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC Sample Rate [kSPS]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

218

Figure 37-122. INL error vs. input code

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

0

512

1024

1536

2048

2560

3072

3584

4096

ADC input code

Figure 37-123. DNL error vs. external V_REF

.

T = 25°C, V_CC= 3.6V, external reference.

0.9

0.88

0.86

0.84

0.82

0.8

Differential Mode

Single-ended Signed

0.78

0.76

0.74

0.72

Single-ended Unsigned

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

219

Figure 37-124. DNL error vs. sample rate.

T = 25°C, V_CC= 3.6V, V_REF= 3.0V external.

0.9

0.89

0.88

0.87

0.86

0.85

Differential Signed

Single-ended Signed

0.84

0.83

0.82

0.81

0.8

Single-ended Unsigned

0.79

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC Sample Rate [kSPS]

Figure 37-125. DNL error vs. input code.

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

0

512

1024

1536

2048

2560

3072

3584

4096

ADC Input Code

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

220

Figure 37-126. Gain error vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

3

Single-ended Signed

Differential Mode

2

1

0

-1

-2

-3

-4

Single-ended Unsigned

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

_REF[V]

V

Figure 37-127. Gain error vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

2.2

1.9

1.6

1.3

1

Single-ended Signed

Differential Mode

0.7

0.4

0.1

-0.2

-0.5

Single-ended Unsigned

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

221

Figure 37-128. Offset error vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

-1

-1.1

-1.2

-1.3

-1.4

-1.5

-1.6

-1.7

-1.8

-1.9

-2

Differential Mode

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

_REF[V]

V

Figure 37-129. Gain error vs. temperature.

V_CC= 3.0V, V_REF= external 2.0V.

4

3

2

1

0

Single-ended signed mode

Differential mode

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

-1

-2

-3

-4

Single-ended unsigned mode

Temperature [ºC]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

222

Figure 37-130. Offset error vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

Differential Signed

-1.1

-1.2

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-131. Noise vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

1.3

Single-ended Signed

1.15

1

Single-ended Unsigned

0.85

0.7

0.55

0.4

Differential Signed

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

223

Figure 37-132. Noise vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

1.3

1.2

1.1

1

Single-ended Signed

0.9

0.8

0.7

0.6

0.5

0.4

0.3

Single-ended Unsigned

Differential Signed

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

37.2.4 DAC Characteristics

Figure 37-133. DAC INL error vs. V_REF

.

V_CC= 3.6V.

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-40°C

25°C

85°C

105°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

224

Figure 37-134. DNL error vs. V_REF

.

V_CC= 3.6V.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

- 40°C

25ºC

85°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

Figure 37-135. DAC noise vs. temperature.

V_CC= 3.0V, V_REF= 2.4V .

0.185

0.180

0.175

0.170

0.165

0.160

0.155

0.150

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [ºC]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

225

37.2.5 Analog Comparator Characteristics

Figure 37-136. Analog comparator hysteresis vs. V_CC

.

High-speed, small hysteresis.

18

17

16

15

14

13

12

11

10

9

105 °C

85 °C

-40 C

°

25 C

8

7

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-137. Analog comparator hysteresis vs. V_CC

.

Low power, small hysteresis.

35

34

33

32

31

30

29

28

27

26

25

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

226

Figure 37-138. Analog comparator hysteresis vs. V_CC

.

High-speed mode, large hysteresis.

42

40

38

36

34

32

30

28

26

24

22

20

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-139. Analog comparator hysteresis vs. V_CC

.

Low power, large hysteresis.

77

74

71

68

65

62

59

56

53

50

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

227

Figure 37-140. Analog comparator current source vs. calibration value.

Temperature = 25°C.

7.4

6.8

6.2

5.6

5.0

4.4

3.8

3.2

2.6

2.0

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CURRCALIBA[3..0]

Figure 37-141. Analog comparator current source vs. calibration value.

V_CC= 3.0V.

CC

7

6.5

6

5.5

5

-40 °C

4.5

4

25 °C

85 °C

105 °C

3.5

3

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CURRCALIBA[3..0]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

228

Figure 37-142. Voltage scaler INL vs. SCALEFAC.

T = 25°C, V_CC= 3.0V.

0.050

0.025

0

-0.025

-0.050

-0.075

-0.100

-0.125

-0.150

25°C

0

10

20

30

40

50

60

70

SCALEFAC

37.2.6 Internal 1.0V reference Characteristics

Figure 37-143. ADC/DAC Internal 1.0V reference vs. temperature.

1.004

1.002

1.000

0.998

0.996

0.994

0.992

0.990

0.988

0.986

1.6 V

1.8 V

2.2 V

2.7 V

3.0 V

3.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

229

37.2.7 BOD Characteristics

Figure 37-144. BOD thresholds vs. temperature.

BOD level = 1.6V.

1.635

Rising Vcc

Falling Vcc

1.630

1.625

1.620

1.615

1.610

1.605

1.600

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-145. BOD thresholds vs. temperature.

BOD level = 3.0V.

3.06

3.05

3.04

3.03

3.02

3.01

3.00

2.99

2.98

2.97

Rising Vcc

Falling Vcc

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

230

37.2.8 External Reset Characteristics

Figure 37-146. Minimum Reset pin pulse width vs. V_CC

.

130

125

120

115

110

105

100

95

105 °C

85 °C

90

25 °C

-40 °C

85

80

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

Figure 37-147. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 1.8V.

72

64

56

48

40

32

24

16

8

-40 °C

25 °C

85 °C

105 °C

0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

V_RESET[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

231

Figure 37-148. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 3.0V.

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

V_RESET[V]

Figure 37-149. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 3.3V.

140

120

100

80

60

40

-40 °C

25 °C

85 °C

105 °C

20

0

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

V_RESET[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

232

Figure 37-150. Reset pin input threshold voltage vs. V_CC.

V_IH- Reset pin read as “1”.

2.20

2.05

1.90

1.75

1.60

1.45

1.30

1.15

1.00

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-151. Reset pin input threshold voltage vs. V_CC.

V_IL- Reset pin read as “0”.

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

0.40

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

233

37.2.9 Power-on Reset Characteristics

Figure 37-152. Power-on reset current consumption vs. V_CC

.

BOD level = 3.0V, enabled in continuous mode.

700

600

500

400

300

200

100

0

-40 °C

25 °C

85 °C

105 °C

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

V_CC[V]

Figure 37-153. Power-on reset current consumption vs. V_CC

.

BOD level = 3.0V, enabled in sampled mode.

650

585

520

455

390

325

260

195

130

65

-40 °C

25 °C

85°C

°

105°°C

0

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

234

37.2.10 Oscillator Characteristics

37.2.10.1 Ultra Low-Power internal oscillator

Figure 37-154. Ultra Low-Power internal oscillator frequency vs. temperature.

32.8

32.4

32.0

31.6

31.2

30.8

30.4

30.0

29.6

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

37.2.10.2 32.768kHz Internal Oscillator

Figure 37-155. 32.768kHz internal oscillator frequency vs. temperature.

32.875

32.850

32.825

32.800

32.775

32.750

32.725

32.700

32.675

32.650

3.6 V

3.0 V

2.2 V

2.7 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

235

Figure 37-156. 32.768kHz internal oscillator frequency vs. calibration value.

V_CC= 3.0V, T = 25°C.

55

50

45

40

35

30

25

20

0

26

52

78

104

130

156

182

208

234

260

RC32KCAL[7..0]

37.2.10.3 2MHz Internal Oscillator

Figure 37-157. 2MHz internal oscillator frequency vs. temperature.

DFLL disabled.

2.16

2.14

2.12

2.10

2.08

2.06

2.04

2.02

2.00

1.98

1.96

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

236

Figure 37-158. 2MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator .

2.0085

2.0070

2.0055

2.0040

2.0025

2.0010

1.9995

1.9980

1.9965

1.9950

3.6 V

1.6 V

2.2 V

1.8 V

3.0 V

2.7 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-159. 2MHz internal oscillator CALA calibration step size.

V_CC= 3V.

0.31 %

0.29 %

0.27 %

0.25 %

0.23 %

0.21 %

0.19 %

0.17 %

0.15 %

-40 °C

25 °C

85 °C

105 °C

0

16

32

48

64

80

96

112

128

CALA

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

237

37.2.10.4 32MHz Internal Oscillator

Figure 37-160. 32MHz internal oscillator frequency vs. temperature.

DFLL disabled.

36.0

35.5

35.0

34.5

34.0

33.5

33.0

32.5

32.0

31.5

31.0

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-161. 32MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator.

32.145

32.120

32.095

32.070

32.045

32.020

31.995

31.970

31.945

31.920

3.6 V

1.6 V

1.8 V

2.2 V

2.7 V

3.0 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

238

Figure 37-162. 32MHz internal oscillator CALA calibration step size.

V_CC= 3.0V.

0.38 %

0.34 %

0.30 %

0.26 %

0.22 %

0.18 %

0.14 %

0.10 %

85°C

105°C

25°C

-40°C

0

16

32

48

64

80

96

112

128

CALA

Figure 37-163. 32MHz internal oscillator frequency vs. CALB calibration value.

V_CC= 3.0V.

75

70

65

60

55

50

45

40

35

30

25

- 40°C

25°C

85°C

105°C

0

8

16

24

32

40

48

56

64

CALB

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

239

37.2.10.5 32MHz internal oscillator calibrated to 48MHz

Figure 37-164. 48MHz internal oscillator frequency vs. temperature.

DFLL disabled.

54

53

52

51

50

49

48

47

46

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

Figure 37-165. 48MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator.

48.25

48.20

48.15

48.10

48.05

48.00

47.95

47.90

47.85

47.80

3.6 V

1.6 V

1.8 V

2.7 V

2.2 V

3.0 V

-40

-25

-10

5

20

35

50

65

80

95

110

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

240

Figure 37-166. 48MHz internal oscillator CALA calibration step size.

V_CC= 3.0V.

0.34 %

0.31 %

0.28 %

0.25 %

0.22 %

0.19 %

0.16 %

0.13 %

0.10 %

-40 °C

25 °C

85 °C

105 °C

0

16

32

48

64

80

96

112

128

CALA

37.2.11 Two-Wire Interface characteristics

Figure 37-167. SDA hold time vs. supply voltage.

300

295

290

285

280

275

270

265

260

105°C

85°C

25°C

- 40°C

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

Vcc [V]

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37.2.12 PDI characteristics

Figure 37-168. Maximum PDI frequency vs. V_CC

.

34

31

28

25

22

19

16

13

10

25 °C

105 °C

-40 °C

85 °C

1.6

1.8

2

2.2

2.4

2.6

V_CC[V]

2.8

3

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

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37.3 ATxmega64A4U

37.3.1 Current consumption

37.3.1.1 Active mode supply current

Figure 37-169. Active supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

700

600

500

400

300

200

100

0

3.6V

3.0V

2.7V

2.2V

1.8V

1.6V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [MHz]

Figure 37-170. Active supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

12

10

8

3.6V

3.0V

2.7V

6

4

2.2V

2

1.8V

1.6V

0

4

8

12

16

Frequency [MHz]

20

24

28

32

XMEGA A4U [DATASHEET]

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Figure 37-171. Active mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

250

230

210

190

170

150

130

110

90

- 40°C

25°C

85°C

105°C

70

50

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-172. Active mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

680

630

580

530

480

430

380

330

280

230

180

- 40°C

25°C

85°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-173. Active mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator.

1300

1200

1100

1000

900

- 40°C

25°C

85°C

105°C

800

700

600

500

400

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-174. Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

4.8

4.4

4.0

3.6

3.2

2.8

2.4

2.0

1.6

1.2

- 40°C

25°C

85°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

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Figure 37-175. Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

12.0

11.5

11.0

10.5

10.0

9.5

- 40°C

25°C

85°C

105°C

9.0

8.5

8.0

7.5

7.0

2.7

2.8

2.9

3.0

3.1

V_CC[V]

3.2

3.3

3.4

3.5

3.6

37.3.1.2 Idle mode supply current

Figure 37-176. Idle mode supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

150

135

120

105

90

3.6 V

3.0 V

2.7 V

75

2.2 V

60

1.8 V

1.6 V

45

30

15

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [MHz]

XMEGA A4U [DATASHEET]

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Figure 37-177. Idle mode supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

4.5

4.0

3.5

3.0

2.5

2.0

1.5

3.6 V

3.0 V

2.7 V

2.2 V

1.0

1.8 V

0.5

0.0

1.6 V

0

4

8

12

16

20

24

28

32

Figure 37-178. Idle mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

SYS

34.75

34.00

33.25

32.50

31.75

31.00

30.25

29.50

28.75

28.00

105°C

- 40°C

85°C

25°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-179. Idle mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

153

141

129

117

105

93

105°C

85°C

25°C

- 40°C

81

69

57

45

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

Figure 37-180. Idle mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator.

400

375

350

325

300

275

250

225

200

175

150

- 40°C

25°C

85°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

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Figure 37-181. Idle mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

1850

- 40°C

25°C

1700

1550

1400

1250

1100

950

85°C

105°C

800

650

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-182. Idle mode current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

5.1

- 40°C

25°C

85°C

105°C

4.9

4.7

4.5

4.3

4.1

3.9

3.7

3.5

3.3

3.1

2.7

2.8

2.9

3.0

3.1

V_CC[V]

3.2

3.3

3.4

3.5

3.6

XMEGA A4U [DATASHEET]

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37.3.1.3 Power-down mode supply current

Figure 37-183. Power-down mode supply current vs. temperature.

All functions disabled.

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0.0

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

Figure 37-184. Power-down mode supply current vs. V_CC

.

All functions disabled.

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0.0

105°C

85°C

25°C

- 40°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

250

Figure 37-185. Power-down mode supply current vs. V_CC

.

Watchdog and sampled BOD enabled.

4.10

3.80

3.50

3.20

2.90

2.60

2.30

2.00

1.70

1.40

1.10

105°C

85°C

25°C

- 40°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

37.3.1.4 Power-save mode supply current

Figure 37-186. Power-save mode supply current vs.V_CC

.

Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.

0.9

Normal mode

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Low-power mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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37.3.1.5 Standby mode supply current

Figure 37-187. Standby supply current vs. V_CC

.

Standby, f_SYS= 1MHz.

12.5

11.5

10.5

9.5

105 °C

85 °C

8.5

25 °C

-40 °C

7.5

6.5

5.5

4.5

3.5

2.5

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-188. Standby supply current vs. V_CC

.

25°C, running from different crystal oscillators.

480

16MHz

12MHz

440

400

360

320

280

240

200

160

8MHz

2MHz

0.454MHz

3.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.6

V_CC[V]

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37.3.2 I/O Pin Characteristics

37.3.2.1 Pull-up

Figure 37-189. I/O pin pull-up resistor current vs. input voltage.

V_CC= 1.8V.

70

60

50

40

30

20

10

0

- 40°C

25°C

85°C

105°C

0.0

0.2

0.4

0.6

0.8

V_PIN[V]

1.0

1.2

1.4

1.6

1.8

Figure 37-190. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.0V.

120

105

90

75

60

45

30

15

0

- 40°C

25°C

85°C

105°C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

V_PIN[V]

XMEGA A4U [DATASHEET]

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Figure 37-191. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.3V.

135

120

105

90

75

60

45

30

15

0

- 40°C

25°C

85°C

105°C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

V_PIN[V]

37.3.2.2 Output Voltage vs. Sink/Source Current

Figure 37-192. I/O pin output voltage vs. source current.

V_CC= 1.8V.

1.9

1.7

1.5

1.3

- 40°C

1.1

25°C

0.9

105°C

85°C

0.7

0.5

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

I_PIN[mA]

XMEGA A4U [DATASHEET]

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Figure 37-193. I/O pin output voltage vs. source current.

V_CC= 3.0V.

3.2

2.8

2.4

2.0

1.6

- 40°C

1.2

25°C

85°C

0.8

0.4

0.0

105°C

-30

-27

-24

-21

-18

-15

-12

-9

-6

-3

0

I_PIN[mA]

Figure 37-194. I/O pin output voltage vs. source current.

V_CC= 3.3V.

3.6

3.2

2.8

2.4

- 40°C

2.0

1.6

25°C

1.2

105°C

0.8

85°C

0.4

0.0

-30

-27

-24

-21

-18

-15

-12

-9

-6

-3

0

I_PIN[mA]

XMEGA A4U [DATASHEET]

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Figure 37-195. I/O pin output voltage vs. source current.

3.7

3.3

2.9

2.5

2.1

1.7

1.3

0.9

0.5

3.6 V

3.3 V

3.0 V

2.7 V

1.8 V

1.6 V

-24

-21

-18

-15

-12

-9

-6

-3

0

I_PIN[mA]

Figure 37-196. I/O pin output voltage vs. sink current.

V_CC= 1.8V.

1.0

0.9

0.8

0.7

85°C

25°C

- 40°C

105°C

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0

2

4

6

8

10

12

14

16

18

20

I_PIN[mA]

XMEGA A4U [DATASHEET]

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Figure 37-197. I/O pin output voltage vs. sink current.

V_CC= 3.0V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105°C

85°C

25°C

- 40°C

0

3

6

9

12

15

18

21

24

27

30

I_PIN[mA]

Figure 37-198. I/O pin output voltage vs. sink current.

V_CC= 3.3V.

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105°C

85°C

25°C

- 40°C

0

3

6

9

12

15

18

21

24

27

30

I_PIN[mA]

XMEGA A4U [DATASHEET]

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Figure 37-199. I/O pin output voltage vs. sink current.

1.50

1.6 V

1.8 V

1.35

1.20

1.05

0.90

0.75

0.60

0.45

0.30

0.15

0.00

2.7 V

3.0 V

3.3 V

3.6 V

0

3

6

9

12

15

18

21

24

27

30

I_PIN[mA]

37.3.2.3 Thresholds and Hysteresis

Figure 37-200. I/O pin input threshold voltage vs. V_CC.

T = 25°C.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VIH

VIL

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

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Figure 37-201. I/O pin input threshold voltage vs. V_CC

.

V_IHI/O pin read as “1”.

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

Figure 37-202. I/O pin input threshold voltage vs. V_CC

.

V_ILI/O pin read as “0”.

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-203. I/O pin input hysteresis vs. V_CC

.

0.32

0.29

0.26

0.23

-40 °C

25 °C

0.20

0.17

85 °C

0.14

0.11

105 °C

0.08

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

37.3.3 ADC Characteristics

Figure 37-204. INL error vs. external V_REF

.

T = 25°C, V_CC= 3.6V, external reference.

2.7

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0.0

Single-ended unsigned mode

Differential mode

Single-ended signed mode

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

XMEGA A4U [DATASHEET]

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Figure 37-205. INL error vs. sample rate.

T = 25°C, V_CC= 2.7V, V_REF= 1.0V external.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

Single-ended signed mode

Differential mode

Single-ended signed mode

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC sample rate [kSps]

Figure 37-206. INL error vs. input code

2.0

1.5

1.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

0

512

1024

1536

2048

2560

3072

3584

4096

ADC input code

XMEGA A4U [DATASHEET]

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261

Figure 37-207. DNL error vs. external V_REF

.

T = 25°C, V_CC= 3.6V, external reference.

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

Single-ended unsigned mode

Differential mode

Single-ended signed mode

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

Figure 37-208. DNL error vs. sample rate.

T = 25°C, V_CC= 2.7V, V_REF= 1.0V external.

0.43

0.41

0.38

0.36

0.33

0.31

0.28

0.26

0.23

Single-ended unsigned mode

Differential mode

Single-ended signed mode

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC sample rate [kSps]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

262

Figure 37-209. DNL error vs. input code.

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512

1024

1536

2048

2560

3072

3584

4096

ADC input code

Figure 37-210. Gain error vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

12

10

8

Single-ended signed mode

Single-ended unsigned mode

6

4

2

Differential mode

0

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

263

Figure 37-211. Gain error vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

7

6

5

4

3

2

1

0

Single-ended signed mode

Single-ended unsigned mode

Differential mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

Figure 37-212. Offset error vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

-1.0

-1.1

-1.2

-1.3

-1.4

-1.5

Differential mode

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

XMEGA A4U [DATASHEET]

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Figure 37-213. Gain error vs. temperature.

V_CC= 2.7V, V_REF= external 1.0V.

8

7

Single-ended signed mode

6

5

4

3

2

1

0

Single-ended unsigned mode

Differential mode

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [oC]

Figure 37-214. Offset error vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1.0

-1.1

Differential mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

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Figure 37-215. Noise vs. V_REF

.

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps.

0.9

Single-ended signed mode

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Single-ended unsigend mode

Differential mode

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

Figure 37-216. Noise vs. V_CC

.

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps.

0.8

Single-ended signed mode

Single-ended unsigned mode

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

Differential mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

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37.3.4 DAC Characteristics

Figure 37-217. DAC INL error vs. V_REF

.

V_CC= 3.6V.

2.4

2.1

1.8

1.5

1.2

0.9

0.6

0.3

0.0

- 40°C

25°C

85°C

105°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

Figure 37-218. DNL error vs. V_REF

.

V_CC= 3.6V.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

- 40°C

25°C

85°C

105°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

Vref [V]

XMEGA A4U [DATASHEET]

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Figure 37-219. DAC noise vs. temperature.

V_CC= 2.7V, V_REF= 1.0V .

0.178

0.176

0.174

0.172

0.170

0.168

0.166

0.164

0.162

0.160

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [oC]

37.3.5 Analog Comparator Characteristics

Figure 37-220. Analog comparator hysteresis vs. V_CC

.

High-speed, small hysteresis.

25

105°C

85°C

24

23

22

21

20

19

18

17

16

15

25°C

- 40°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-221. Analog comparator hysteresis vs. V_CC

.

Low power, small hysteresis.

36

34

32

30

28

26

24

22

20

105°C

85°C

25°C

- 40°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-222. Analog comparator hysteresis vs. V_CC

.

High-speed mode, large hysteresis.

47

45

43

41

39

37

35

33

31

29

27

105°C

85°C

25°C

- 40°C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-223. Analog comparator hysteresis vs. V_CC

.

Low power, large hysteresis.

76

73

70

67

64

61

58

55

52

49

46

105°C

85°C

25°C

- 40°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

Figure 37-224. Analog comparator current source vs. calibration value.

Temperature = 25°C.

8

7

6

5

4

3

2

3.6V

3.0V

2.7V

2.2V

1.8V

1.6V

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

CURRCALIBA[3..0]

XMEGA A4U [DATASHEET]

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Figure 37-225. Analog comparator current source vs. calibration value.

V_CC= 3.0V.

7.2

6.8

6.4

6.0

5.6

5.2

4.8

4.4

4.0

3.6

- 40°C

25°C

85°C

105°C

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CURRCALIBA[3..0]

Figure 37-226. Voltage scaler INL vs. SCALEFAC.

T = 25°C, V_CC= 3.0V.

0.15

0.12

0.09

0.06

0.03

0.00

-0.03

-0.06

-0.09

-0.12

-0.15

0

8

16

24

32

40

48

56

64

SCALEFAC

XMEGA A4U [DATASHEET]

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37.3.6 Internal 1.0V reference Characteristics

Figure 37-227. ADC/DAC Internal 1.0V reference vs. temperature.

1.004

1.002

1.000

0.998

0.996

0.994

0.992

1.6 V

1.8 V

2.2 V

2.7 V

3.0 V

3.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

37.3.7 BOD Characteristics

Figure 37-228. BOD thresholds vs. temperature.

BOD level = 1.6V.

1.644

1.641

1.638

1.635

1.632

1.629

1.626

1.623

1.620

1.617

Rising Vcc

Falling Vcc

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

272

Figure 37-229. BOD thresholds vs. temperature.

BOD level = 3.0V.

3.08

3.07

3.06

3.05

3.04

3.03

3.02

3.01

3.00

Rising Vcc

Falling Vcc

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

37.3.8 External Reset Characteristics

Figure 37-230. Minimum Reset pin pulse width vs. V_CC

.

135

130

125

120

115

110

105

100

95

105°C

85°C

90

25°C

- 40°C

85

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-231. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 1.8V.

80

70

60

50

40

30

20

10

0

- 40°C

25°C

85°C

105°C

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

V_RESET[V]

Figure 37-232. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 3.0V.

120

105

90

75

60

45

30

15

0

- 40°C

25°C

85°C

105°C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

V_RESET[V]

XMEGA A4U [DATASHEET]

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Figure 37-233. Reset pin pull-up resistor current vs. reset pin voltage.

V_CC= 3.3V.

150

135

120

105

90

75

60

45

- 40°C

25°C

30

15

85°C

105°C

0

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

V_RESET[V]

Figure 37-234. Reset pin input threshold voltage vs. V_CC.

V_IH- Reset pin read as “1”.

2.2

2.1

1.9

1.8

1.6

1.5

- 40°C

25°C

85°C

105°C

1.3

-

1.2

1.0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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Figure 37-235. Reset pin input threshold voltage vs. V_CC.

V_IL- Reset pin read as “0”.

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

0.40

- 40°C

25°C

85°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

37.3.9 Power-on Reset Characteristics

Figure 37-236. Power-on reset current consumption vs. V_CC

.

BOD level = 3.0V, enabled in continuous mode.

300

250

200

150

100

50

105°C

85°C

25°C

- 40°C

0

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

V

[V]

CC

XMEGA A4U [DATASHEET]

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276

Figure 37-237. Power-on reset current consumption vs. V_CC

.

BOD level = 3.0V, enabled in sampled mode.

300

250

200

150

100

50

105°C

85°C

25°C

- 40°C

0

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

V

[V]

CC

37.3.10 Oscillator Characteristics

37.3.10.1 Ultra Low-Power internal oscillator

Figure 37-238. Ultra Low-Power internal oscillator frequency vs. temperature.

34.0

33.7

33.4

33.1

32.8

32.5

32.2

31.9

31.6

31.3

31.0

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

XMEGA A4U [DATASHEET]

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37.3.10.2 32.768kHz Internal Oscillator

Figure 37-239. 32.768kHz internal oscillator frequency vs. temperature.

32.85

32.82

32.79

32.76

32.73

32.70

32.67

32.64

32.61

32.58

32.55

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

Figure 37-240. 32.768kHz internal oscillator frequency vs. calibration value.

V_CC= 3.0V, T = 25°C.

53

50

47

44

41

38

35

32

29

26

23

0

30

60

90

120

150

180

210

240

270

RC32KCAL[7..0]

XMEGA A4U [DATASHEET]

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37.3.10.3 2MHz Internal Oscillator

Figure 37-241. 2MHz internal oscillator frequency vs. temperature.

DFLL disabled.

2.12

2.10

2.08

2.06

2.04

2.02

2.00

1.98

1.96

1.94

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

Figure 37-242. 2MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator .

2.010

2.008

2.006

2.004

2.002

2.000

1.998

1.996

1.994

1.992

1.990

1.988

3.6 V

1.8 V

2.2 V

3.0 V

1.6 V

2.7 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

XMEGA A4U [DATASHEET]

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279

Figure 37-243. 2MHz internal oscillator CALA calibration step size.

V_CC= 3V.

0.28 %

0.26 %

0.24 %

0.22 %

0.20 %

0.18 %

0.16 %

0.14 %

0.12 %

- 40°C

25°C

105°C

85°C

0

16

32

48

64

80

96

112

128

CALA

37.3.10.4 32MHz Internal Oscillator

Figure 37-244. 32MHz internal oscillator frequency vs. temperature.

DFLL disabled.

35.5

35.0

34.5

34.0

33.5

33.0

32.5

32.0

31.5

31.0

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

280

Figure 37-245. 32MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator.

32.12

32.08

32.04

32.00

3.6 V

31.96

31.92

3.0 V

31.88

31.84

31.80

2.7 V

2.2 V

1.8 V

1.6 V

-30

-45

-15

0

15

30

45

60

75

90

105

Temperature [°C]

Figure 37-246. 32MHz internal oscillator CALA calibration step size.

V_CC= 3.0V.

0.34 %

0.31 %

0.28 %

0.25 %

0.22 %

0.19 %

0.16 %

0.13 %

0.10 %

- 40°C

85°C

105°C

25°C

0

15

30

45

60

CALA

75

90

105

120

135

XMEGA A4U [DATASHEET]

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Figure 37-247. 32MHz internal oscillator CALB calibration step size.

V_CC= 3.0V

2.80 %

2.60 %

2.40 %

2.20 %

2.00 %

1.80 %

1.60 %

1.40 %

1.20 %

1.00 %

0.80 %

- 40°C

25°C

85°C

105°C

0

8

16

24

32

40

48

56

64

CALB

37.3.10.5 32MHz internal oscillator calibrated to 48MHz

Figure 37-248. 48MHz internal oscillator frequency vs. temperature.

DFLL disabled.

53.4

52.6

51.8

51.0

50.2

49.4

48.6

47.8

47.0

46.2

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

XMEGA A4U [DATASHEET]

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282

Figure 37-249. 48MHz internal oscillator frequency vs. temperature.

DFLL enabled, from the 32.768kHz internal oscillator.

48.15

48.10

48.05

48.00

47.95

47.90

47.85

47.80

47.75

47.70

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-30

-15

0

15

30

45

60

75

90

105

Temperature [°C]

Figure 37-250. 48MHz internal oscillator CALA calibration step size.

V_CC= 3.0V

0.30 %

0.28 %

0.26 %

0.24 %

0.22 %

0.20 %

0.18 %

0.16 %

0.14 %

0.12 %

0.10 %

- 40°C

105°C

25°C

85°C

0

16

32

48

64

80

96

112

128

CALA

XMEGA A4U [DATASHEET]

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37.3.11 Two-Wire Interface characteristics

Figure 37-251. SDA hold time vs. supply voltage.

300

295

290

285

280

275

270

265

260

105°C

85°C

25°C

- 40°C

2.6

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

Vcc [V]

37.3.12 PDI characteristics

Figure 37-252. Maximum PDI frequency vs. V_CC

.

30

28

26

24

-

- 40°C

85°C

22

20

18

16

14

12

10

25°C

105°C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

VCC [V]

XMEGA A4U [DATASHEET]

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37.4 ATxmega128A4U

37.4.1 Current consumption

37.4.1.1 Active mode supply current

Figure 37-253. Active supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C.

800

700

600

500

400

300

200

100

0

3.6V

3.0V

2.7V

2.2V

1.8V

1.6V

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [MHz]

Figure 37-254. Active supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C.

13.5

12.0

10.5

9.0

3.6V

3.0V

2.7V

7.5

6.0

4.5

2.2V

3.0

1.8V

1.5

0

4

8

12

16

Frequency [MHz]

20

24

28

32

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

285

Figure 37-255. Active mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator

270

240

210

180

150

120

90

- 40 °C

25 °C

85 °C

105 °C

60

30

0

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

VCC [V]

Figure 37-256. Active mode supply current vs. V_CC

.

f_SYS= 1MHz external clock.

800

700

600

500

400

300

200

100

0

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

286

Figure 37-257. Active mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator

-40 °C

25 °C

85 °C

1400

1225

1050

875

700

525

350

175

0

105 °C

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Vcc [V]

Figure 37-258. Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz.

5800

-40 °C

5200

4600

4000

3400

2800

2200

1600

1000

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

VCC [V]

XMEGA A4U [DATASHEET]

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Figure 37-259. Active mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator.

13.4

12.6

11.8

11.0

10.2

9.4

-40 °C

25 °C

85 °C

105 °C

8.6

7.8

7.0

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

VCC [V]

37.4.1.2 Idle mode supply current

Figure 37-260. Idle mode supply current vs. frequency.

f_SYS= 0 - 1MHz external clock, T = 25°C

160

140

120

100

80

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

60

40

20

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Frequency [MHz]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

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Figure 37-261. Idle mode supply current vs. frequency.

f_SYS= 1 - 32MHz external clock, T = 25°C

5.4

4.8

4.2

3.6

3.0

2.4

1.8

1.2

3.6V

3.0V

2.7V

2.2V

1.8V

0.6

0

4

8

12

16

20

24

28

32

Frenquecy [MHz]

Figure 37-262. Idle mode supply current vs. V_CC

.

f_SYS= 32.768kHz internal oscillator.

38

37

36

35

34

33

32

31

30

29

28

27

105 °C

-40 °C

85 °C

25 °C

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

289

Figure 37-263. Idle mode supply current vs. V_CC

.

f_SYS= 1MHz external clock

160

150

140

130

120

110

100

90

105 °C

85 °C

25 °C

-40 °C

80

70

60

50

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

VCC [V]

Figure 37-264. Idle mode supply current vs. V_CC

.

f_SYS= 2MHz internal oscillator

105 °C

85 °C

25 °C

-40 °C

330

310

290

270

250

230

210

190

170

150

130

110

90

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

290

Figure 37-265. Idle mode supply current vs. V_CC

.

f_SYS= 32MHz internal oscillator prescaled to 8MHz

2000

-40 °C

25 °C

1800

1600

1400

1200

1000

800

85 °C

105 °C

600

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

Figure 37-266. Idle mode current vs. V_CC

.

f_SYS= 32MHz internal oscillator

5000

-40 °C

25 °C

4750

4500

4250

4000

3750

3500

3250

3000

85 °C

105 °C

2.7

2.8

2.9

3.0

3.1

3.2

3.3

3.4

3.5

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

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291

37.4.1.3 Power-down mode supply current

Figure 37-267. Power-down mode supply current vs. temperature.

All functions disabled

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

3.6 V

3.0 V

2.7 V

2.2 V

1.8 V

1.6 V

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [°C]

Figure 37-268. Power-down mode supply current vs. V_CC

.

All functions disabled

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

105 °C

85 °C

25 °C

-40 °C

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

292

Figure 37-269. Power-down mode supply current vs. V_CC

.

Watchdog and sampled BOD enabled

7.3

6.8

6.3

5.8

5.3

4.8

4.3

3.8

3.3

2.8

2.3

1.8

1.3

0.8

105 °C

85 °C

25 °C

-40 °C

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

37.4.1.4 Power-save mode supply current

Figure 37-270. Power-save mode supply current vs.V_CC

.

Real Time Counter enabled and running from 1.024kHz output of 32.768kHz TOSC.

0.9

Normal mode

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

Low-power mode

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

293

37.4.1.5 Standby mode supply current

Figure 37-271. Standby supply current vs. V_CC

.

Standby, f_SYS= 1MHz

12.5

11.5

10.5

9.5

105 °C

85 °C

8.5

25 °C

-40 °C

7.5

6.5

5.5

4.5

3.5

2.5

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-272. Standby supply current vs. V_CC

.

T = 25°C, running from different crystal oscillators

480

440

400

360

320

280

240

200

160

16MHz

12MHz

8MHz

2MHz

0.454MHz

3.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

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294

37.4.2 I/O Pin Characteristics

37.4.2.1 Pull-up

Figure 37-273. I/O pin pull-up resistor current vs. input voltage.

V_CC= 1.8V

72

64

56

48

40

32

24

16

8

-40 °C

25 °C

85 °C

105 °C

0

0.1

0.3

0.5

0.7

0.9

1.1

1.3

1.5

1.7

Vpin [V]

Figure 37-274. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.0V

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.1

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vpin [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

295

Figure 37-275. I/O pin pull-up resistor current vs. input voltage.

V_CC= 3.3V.

135

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.1

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

3.1

3.4

Vpin [V]

37.4.2.2 Output Voltage vs. Sink/Source Current

Figure 37-276. I/O pin output voltage vs. source current.

V_CC= 1.8V

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

0.7

0.6

0.5

-40 °C

25 °C 85 °C 105 °C

-10

-9

-8

-7

-6

-5

-4

-3

-2

-1

0

Ipin [mA]

XMEGA A4U [DATASHEET]

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296

Figure 37-277. I/O pin output voltage vs. source current.

V_CC= 3.0V

3.30

2.95

2.60

2.25

1.90

1.55

-40 °C

-27

85 °C

-21

105 °C

25 °C

-24

1.20

0.85

0.50

-30

-18

-15

Ipin [mA]

-12

-9

-6

-3

0

Figure 37-278. I/O pin output voltage vs. source current.

V_CC= 3.3V

3.5

3.2

2.9

2.6

2.3

2.0

-40 °C

1.7

1.4

25 °C

1.1

105 °C

85 °C

-27

0.8

0.5

-30

-24

-21

-18

-15

-12

-9

-6

-3

0

Ipin [mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

297

Figure 37-279. I/O pin output voltage vs. source current

3.65

3.30

2.95

2.60

2.25

1.90

1.55

1.20

0.85

0.50

3.6 V

3.3 V

3.0 V

2.7 V

1.8 V

1.6 V

-24

-21

-18

-15

-12

-9

-6

-3

0

Ipin [mA]

Figure 37-280. I/O pin output voltage vs. sink current.

V_CC= 1.8V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

85 °C

105 °C

25 °C

-40 °C

0

2

4

6

8

10

12

14

16

18

20

Ipin [mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

298

Figure 37-281. I/O pin output voltage vs. sink current.

V_CC= 3.0V

1.1

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

3

6

9

12

15

18

21

24

27

30

Ipin [mA]

Figure 37-282. I/O pin output voltage vs. sink current.

V_CC= 3.3V

1.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

105 °C

85 °C

25 °C

-40 °C

0

3

6

9

12

15

18

21

24

27

30

Ipin [mA]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

299

Figure 37-283. I/O pin output voltage vs. sink current

1.50

1.35

1.20

1.05

1.8 V

2.7 V

3.0 V

3.3 V

3.6 V

1.6 V

0.90

0.75

0.60

0.45

0.30

0.15

0.00

0

3

6

9

12

15

18

21

24

27

30

Ipin [mA]

37.4.2.3 Thresholds and Hysteresis

Figure 37-284. I/O pin input threshold voltage vs. V_CC.

T = 25°C

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

VIH

VIL

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

300

Figure 37-285. I/O pin input threshold voltage vs. V_CC

.

V_IHI/O pin read as “1”

105 °C

85 °C

25 °C

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1.0

0.9

0.8

-40 °C

1.6

1.8

2.0

2.2

2.4

2.6

Vcc [V]

2.8

3.0

3.2

3.4

3.6

Figure 37-286. I/O pin input threshold voltage vs. V_CC

.

V_ILI/O pin read as “0”

1.75

1.60

1.45

1.30

1.15

1.00

0.85

0.70

0.55

0.40

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

301

Figure 37-287. I/O pin input hysteresis vs. V_CC

0.41

0.39

0.37

0.35

0.33

-40 °C

0.31

25 °C

0.29

0.27

0.25

85 °C

0.23

0.21

105 °C

0.19

0.17

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

37.4.3 ADC Characteristics

Figure 37-288. INL error vs. external V_REF

T = 25°C, V_CC= 3.6V, external reference

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

1

Differential Signed

Single-ended Unsigned

0.9

0.8

0.7

Single-ended Signed

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

302

Figure 37-289. INL error vs. sample rate

T = 25°C, V_CC= 3.6V, V_REF= 3.0V external

1.4

1.35

1.3

Differential Mode

1.25

1.2

Single-ended Unsigned

1.15

1.1

1.05

1

Single-ended Signed

0.95

0.9

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC Sample Rate [kSPS]

Figure 37-290. INL error vs. input code

2.0

1.5

1.0

0.5

0

-0.5

-1.0

-1.5

-2.0

0

512

1024

1536

2048

2560

3072

3584

4096

ADC input code

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

303

Figure 37-291. DNL error vs. external V_REF

T = 25°C, V_CC= 3.6V, external reference

0.9

0.88

0.86

Differential Mode

0.84

0.82

0.8

Single-ended Signed

0.78

0.76

0.74

0.72

Single-ended Unsigned

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

Figure 37-292. DNL error vs. sample rate

T = 25°C, V_CC= 3.6V, V_REF= 3.0V external

0.9

0.89

0.88

0.87

0.86

0.85

0.84

0.83

0.82

0.81

0.8

Differential Signed

Single-ended Signed

Single-ended Unsigned

0.79

500

650

800

950

1100

1250

1400

1550

1700

1850

2000

ADC Sample Rate [kSPS]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

304

Figure 37-293. DNL error vs. input code

0.8

0.6

0.4

0.2

0

-0.2

-0.4

-0.6

0

512

1024

1536

2048

2560

3072

3584

4096

ADC Input Code

Figure 37-294. Gain error vs. V_REF

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps

3

Single-ended Signed

Differential Mode

2

1

0

-1

-2

-3

-4

Single-ended Unsigned

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

_REF[V]

V

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

305

Figure 37-295. Gain error vs. V_CC

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps

2.2

1.9

1.6

1.3

1

Single-ended Signed

Differential Mode

0.7

0.4

0.1

-0.2

-0.5

Single-ended Unsigned

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

Figure 37-296. Offset error vs. V_REF

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps

-1

-1.1

-1.2

-1.3

-1.4

-1.5

-1.6

-1.7

-1.8

-1.9

-2

Differential Mode

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

_REF[V]

V

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

306

Figure 37-297. Gain error vs. temperature

V_CC= 3.0V, V_REF= external 2.0V

3

2

Single-ended Signed

1

Differential Signed

0

-1

-2

-3

-4

Single-ended Unsigned

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

Temperature [ºC]

Figure 37-298. Offset error vs. V_CC

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps

-0.3

-0.4

-0.5

-0.6

-0.7

-0.8

-0.9

-1

Differential Signed

-1.1

-1.2

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

307

Figure 37-299. Noise vs. V_REF

T = 25°C, V_CC= 3.6V, ADC sampling speed = 500ksps

1.3

1.15

1

Single-ended Signed

Single-ended Unsigned

0.85

0.7

0.55

0.4

Differential Signed

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

Figure 37-300. Noise vs. V_CC

T = 25°C, V_REF= external 1.0V, ADC sampling speed = 500ksps

1.3

1.2

1.1

1

Single-ended Signed

0.9

0.8

0.7

0.6

0.5

0.4

0.3

Single-ended Unsigned

Differential Signed

1.6

1.8

2

2.2

2.4

2.6

2.8

3

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

308

37.4.4 DAC Characteristics

Figure 37-301. DAC INL error vs. V_REF

V_CC= 3.6V

1.9

1.8

1.7

1.6

1.5

1.4

1.3

1.2

1.1

25°C

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

V_REF[V]

Figure 37-302. DNL error vs. V_REF

.

T = 25°C, V_CC= 3.6V.

0.9

0.85

0.8

0.75

0.7

0.65

0.6

25ºC

1.6

1.8

2

2.2

2.4

2.6

2.8

3

V_REF[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

309

Figure 37-303. DAC noise vs. temperature

V_CC= 3.0V, V_REF= 2.4V

0.185

0.180

0.175

0.170

0.165

0.160

0.155

0.150

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [ºC]

37.4.5 Analog Comparator Characteristics

Figure 37-304. Analog comparator hysteresis vs. V_CC

.

High-speed, small hysteresis

14

13

12

11

10

9

105°

C

85°C

25°C

-40°

8

7

6

5

4

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

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Figure 37-305. Analog comparator hysteresis vs. V_CC

.

Low power, small hysteresis

30

28

26

24

22

20

18

16

14

12

105°C

85°C

25°C

-40°C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

Figure 37-306. Analog comparator hysteresis vs. V_CC

.

High-speed mode, large hysteresis

32

30

28

26

24

22

20

18

16

14

105°C

85°C

25°C

-40°C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

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Figure 37-307. Analog comparator hysteresis vs. V_CC

.

Low power, large hysteresis

68

64

60

56

52

48

44

40

36

32

105°C

85°C

25°C

-40°C

1.6

1.8

2.0

2.2

2.4

2.6

V_CC[V]

2.8

3.0

3.2

3.4

3.6

Figure 37-308. Analog comparator current source vs. calibration value.

Temperature = 25°C

8

7.5

7

6.5

6

5.5

5

3.6V

4.5

4

3.0V

3.5

3

2.2V

1.8V

2.5

2

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CURRCALIBA[3..0]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

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Figure 37-309. Analog comparator current source vs. calibration value.

V_CC= 3.0V.

7

6.5

6

5.5

5

4.5

4

-40°C

25°C

85°C

3.5

3

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

CURRCALIBA[3..0]

Figure 37-310. Voltage scaler INL vs. SCALEFAC.

T = 25°C, V_CC= 3.0V.

0.050

0.025

0

-0.025

-0.050

-0.075

-0.100

-0.125

-0.150

25°C

0

10

20

30

40

50

60

70

SCALEFAC

XMEGA A4U [DATASHEET]

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37.4.6 Internal 1.0V reference Characteristics

Figure 37-311. ADC/DAC Internal 1.0V reference vs. temperature

1.0024

1.0020

1.0016

1.0012

1.0008

1.0004

1.0000

0.9996

0.9992

0.9988

1.6V

1.8V

2.7V

3.0V

3.6V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

37.4.7 BOD Characteristics

Figure 37-312. BOD thresholds vs. temperature.

BOD level = 1.6V

1.596

1.593

1.590

1.587

1.584

1.581

1.578

1.575

1.572

Rising Vcc

Falling Vcc

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

314

Figure 37-313. BOD thresholds vs. temperature.

BOD level = 3.0V

3.03

3.02

3.01

3.00

2.99

2.98

2.97

2.96

2.95

2.94

Rising Vcc

Falling Vcc

-45

-35

-25

-15

-5

5

15

25

35

45

55

65

75

85

95

105

Temperature [°C]

37.4.8 External Reset Characteristics

Figure 37-314. Minimum Reset pin pulse width vs. V_CC

135

130

125

120

115

110

105

100

95

105 °C

85 °C

90

25 °C

85

-40 °C

80

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

315

Figure 37-315. Reset pin pull-up resistor current vs. reset pin voltage

V_CC= 1.8V

80

72

64

56

48

40

32

24

16

8

-40 °C

25 °C

85 °C

105 °C

0

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

Vreset [V]

Figure 37-316. Reset pin pull-up resistor current vs. reset pin voltage

V_CC= 3.0V

135

120

105

90

75

60

45

30

15

0

-40 °C

25 °C

85 °C

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

Vreset [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

316

Figure 37-317. Reset pin pull-up resistor current vs. reset pin voltage

V_CC= 3.3V

150

135

120

105

90

75

60

45

30

-40 °C

25 °C

15

85 °C

0

105 °C

0.0

0.3

0.6

0.9

1.2

1.5

1.8

2.1

2.4

2.7

3.0

3.3

Vreset [V]

Figure 37-318. Reset pin input threshold voltage vs. V_CC

V_IH- Reset pin read as “1”

2.20

2.05

1.90

1.75

1.60

1.45

1.30

1.15

1.00

-40 °C

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

317

Figure 37-319. Reset pin input threshold voltage vs. V_CC

V_IL- Reset pin read as “0”

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

105 °C

85 °C

25 °C

-40 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

VCC [V]

37.4.9 Power-on Reset Characteristics

Figure 37-320. Power-on reset current consumption vs. V_CC

BOD level = 3.0V, enabled in continuous mode

700

600

500

400

300

200

100

0

-40 °C

25 °C

85 °C

105 °C

0.4

0.7

1.0

1.3

1.6

1.9

2.2

2.5

2.8

V_CC[V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

318

Figure 37-321. Power-on reset current consumption vs. V_CC

BOD level = 3.0V, enabled in sampled mode

650

585

520

455

390

325

260

195

130

65

-40 °C

25 °C

85°C

°

105°°C

0

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

V_CC[V]

37.4.10 Oscillator Characteristics

37.4.10.1 Ultra Low-Power internal oscillator

Figure 37-322. Ultra Low-Power internal oscillator frequency vs. temperature.

33.75

33.50

33.25

33.00

32.75

32.50

32.25

32.00

31.75

31.50

31.25

31.00

30.75

3.6 V

3.3 V

3.0 V

2.7 V

1.8 V

1.6 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

319

37.4.10.2 32.768kHz Internal Oscillator

Figure 37-323. 32.768kHz internal oscillator frequency vs. temperature

32.82

32.79

32.76

32.73

32.70

32.67

32.64

32.61

32.58

32.55

32.52

32.49

32.46

3.6 V

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

Figure 37-324. 32.768kHz internal oscillator frequency vs. calibration value

V_CC= 3.0V, T = 25°C

52

49

46

43

40

37

34

31

28

25

22

3.0 V

0

24

48

72

96

120

144

168

192

216

240

264

RC32KCAL[7..0]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

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37.4.10.3 2MHz Internal Oscillator

Figure 37-325. 2MHz internal oscillator frequency vs. temperature

DFLL disabled

2.16

2.14

2.12

2.10

2.08

2.06

2.04

2.02

2.00

1.98

1.96

3.6 V

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

Figure 37-326. 2MHz internal oscillator frequency vs. temperature

DFLL enabled, from the 32.768kHz internal oscillator

2.006

2.004

2.002

2.000

1.998

1.996

1.994

1.992

1.990

1.988

1.986

1.984

1.982

1.980

3.6 V

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

321

Figure 37-327. 2MHz internal oscillator CALA calibration step size

V_CC= 3V

0.30

0.28

0.26

0.24

0.22

0.20

0.18

0.16

0.14

-40 °C

25 °C

85 °C

105 °C

0

10

20

30

40

50

60

70

80

90

100

110

120

130

CALA

37.4.10.4 32MHz Internal Oscillator

Figure 37-328. 32MHz internal oscillator frequency vs. temperature

DFLL disabled

36.00

35.55

35.10

34.65

34.20

33.75

33.30

32.85

32.40

31.95

31.50

31.05

3.6 V

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

322

Figure 37-329. 32MHz internal oscillator frequency vs. temperature

DFLL enabled, from the 32.768kHz internal oscillator

32.05

32.02

31.99

31.96

31.93

31.90

31.87

31.84

31.81

31.78

31.75

31.72

31.69

31.66

1.8 V

2.2 V

2.7 V

3.0 V

3.3 V

3.6 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

Figure 37-330. 32MHz internal oscillator CALA calibration step size

V_CC= 3.0V

0.32

0.29

0.26

0.23

0.20

0.17

0.14

-40 °C

105 °C

85 °C

25 °C

0

10

20

30

40

50

60

70

80

90

100

110

120

130

CALA

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

323

37.4.10.5 32MHz internal oscillator calibrated to 48MHz

Figure 37-331. 48MHz internal oscillator frequency vs. temperature

DFLL disabled

53.9

53.2

52.5

51.8

51.1

50.4

49.7

49.0

48.3

47.6

46.9

46.2

3.6 V

3.3 V

3.0 V

2.7 V

2.2 V

1.8 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

Figure 37-332. 48MHz internal oscillator frequency vs. temperature

DFLL enabled, from the 32.768kHz internal oscillator

48.3

48.2

48.1

48.0

47.9

47.8

47.7

47.6

47.5

1.8 V

2.2 V

2.7 V

3.0 V

3.3 V

3.6 V

-40

-30

-20

-10

0

10

20

30

40

50

60

70

80

90

100

Temperature [°C]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

324

Figure 37-333. 48MHz internal oscillator CALA calibration step size

V_CC= 3V

0.28

0.26

0.24

0.22

0.2

-40 °C

105 °C

85 C

25 °C

0.18

0.16

0.14

°

0

10

20

30

40

50

60

70

80

90

100

110

120

130

CALA

37.4.11 Two-Wire Interface characteristics

Figure 37-334. SDA hold time vs. supply voltage

300

295

290

285

280

275

270

265

260

105°C

85°C

25°C

- 40°C

2.6

2.7

2.8

2.9

3.0

3.1

Vcc [V]

3.2

3.3

3.4

3.5

3.6

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

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37.4.12 PDI characteristics

Figure 37-335. Maximum PDI frequency vs. V_CC

-40 °C

31

28

25

22

19

16

13

10

25 °C

85 °C

105 °C

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

3.2

3.4

3.6

Vcc [V]

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

326

38. Errata

38.1 ATxmega16A4U

38.1.1 Rev. E

z

ADC may have missing codes in SE unsigned mode at low temp and low Vcc

CRC fails for Range CRC when end address is the last word address of a flash section

AWeX fault protection restore is not done correct in Pattern Generation Mode

1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc

The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.

Problem fix/Workaround

Use the ADC in SE signed mode.

2. CRC fails for Range CRC when end address is the last word address of a flash section

If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If applica-

tion table read lock is enabled, the range CRC cannot end on the last address before the application table.

Problem fix/Workaround

Ensure that the end address used in Range CRC does not end at the last address before a section with read lock

enabled. Instead, use the dedicated CRC commands for complete applications sections.

3. AWeX fault protection restore is not done correct in Pattern Generation Mode

When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN

is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode

(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation

Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.

Problem fix/Workaround

For CWCM no workaround is required.

For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set cor-

rect OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable

the correct outputs again.

38.1.2 Rev. A - D

Not sampled.

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

327

38.2 ATxmega32A4U

38.2.1 Rev. E

z

ADC may have missing codes in SE unsigned mode at low temp and low Vcc

CRC fails for Range CRC when end address is the last word address of a flash section

AWeX fault protection restore is not done correct in Pattern Generation Mode

1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc

The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.

Problem fix/Workaround

Use the ADC in SE signed mode.

2. CRC fails for Range CRC when end address is the last word address of a flash section

If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If applica-

tion table read lock is enabled, the range CRC cannot end on the last address before the application table.

Problem fix/Workaround

Ensure that the end address used in Range CRC does not end at the last address before a section with read lock

enabled. Instead, use the dedicated CRC commands for complete applications sections.

3. AWeX fault protection restore is not done correct in Pattern Generation Mode

When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN

is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode

(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation

Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.

Problem fix/Workaround

For CWCM no workaround is required.

For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set cor-

rect OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable

the correct outputs again.

38.2.2 Rev. A - D

Not sampled.

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

328

38.3 ATxmega64A4U

38.3.1 Rev. D

z

ADC may have missing codes in SE unsigned mode at low temp and low Vcc

CRC fails for Range CRC when end address is the last word address of a flash section

1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc

The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.

Problem fix/Workaround

Use the ADC in SE signed mode.

2. CRC fails for Range CRC when end address is the last word address of a flash section

If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If applica-

tion table read lock is enabled, the range CRC cannot end on the last address before the application table.

Problem fix/Workaround

Ensure that the end address used in Range CRC does not end at the last address before a section with read lock

enabled. Instead, use the dedicated CRC commands for complete applications sections.

38.3.2 Rev. C

ADC may have missing codes in SE unsigned mode at low temp and low Vcc

z

CRC fails for Range CRC when end address is the last word address of a flash section

AWeX fault protection restore is not done correct in Pattern Generation Mode

1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc

The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.

Problem fix/Workaround

Use the ADC in SE signed mode.

2. CRC fails for Range CRC when end address is the last word address of a flash section

If boot read lock is enabled, the range CRC cannot end on the last address of the application section. If applica-

tion table read lock is enabled, the range CRC cannot end on the last address before the application table.

Problem fix/Workaround

Ensure that the end address used in Range CRC does not end at the last address before a section with read lock

enabled. Instead, use the dedicated CRC commands for complete applications sections.

XMEGA A4U [DATASHEET]

Atmel-8387H-AVR-ATxmega16A4U-34A4U-64A4U-128A4U-Datasheet_09/2014

329

3. AWeX fault protection restore is not done correct in Pattern Generation Mode

When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN

is restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode

(CWCM), this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation

Mode (PGM), OUTOVEN should instead have been restored according to the DTLSBUF register.

Problem fix/Workaround

For CWCM no workaround is required.

For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set cor-

rect OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable

the correct outputs again.

38.3.3 Rev. A - B

Not sampled.

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38.4 ATxmega128A4U

38.4.1 rev. A

z

ADC may have missing codes in SE unsigned mode at low temp and low Vcc

1. ADC may have missing codes in SE unsigned mode at low temp and low Vcc

The ADC may have missing codes i single ended (SE) unsigned mode below 0C when Vcc is below 1.8V.

Problem fix/Workaround

Use the ADC in SE signed mode.

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39. Datasheet Revision History

Please note that the referring page numbers in this section are referred to this document. The referring revision in this

section are referring to the document revision.

39.1 8387H –09/2014

Updated “Ordering Information” on page 2. Added ordering information for ATxmega16A4U/32A4U/64A4U/128A4U @

105°C

1.

2.

3.

Updated the Application Table Section from 4K/4K/4K/4K to 8K/4K/4K/4K in the Figure 7-1 on page 14

Updated Table 36-4 on page 74, Table 36-36 on page 95, Table 36-68 on page 117 and Table 36-100 on page 139. Added

Icc Power-down power consumption for T=105°C for all functions disabled and for WDT and sampled BOD enabled

Updated Table 36-20 on page 84, Table 36-52 on page 105, Table 36-84 on page 127 and Table 36-116 on page 149.

Updated all tables to include values for T=85°C and T=105°C. Removed T=55°C

4.

5.

Added 105°C Typical Characterization plots for:

ATxmega16A4U

ATxmega32A4U

ATxmega64A4U

ATxmega128A4U

Changed Vcc to AVcc in Figure 28-1 on page 50 and in the text in Section 28. “ADC – 12-bit Analog to Digital Converter” on

page 49 andSection 30. “AC – Analog Comparator” on page 53.

6.

7.

8.

Changed values for 128A4U in Table 7-3 on page 17. Page size = 128, FWORD = Z(6:0)

Changed unit notation for parameter t_SU;DATto ns in Table 36-32 on page 92, Table 36-64 on page 113, and Table 36-128

on page 157.

39.2 8387G – 03/2014

1.

2.

Removed “Preliminary” from the datasheet

Updated “Errata” on page 327: added ERRATA “Rev. D” and “Rev. C” for “ATxmega64A4U” on page 329

39.3 8387F – 01/2014

1.

2.

Removed JTAG references from the datasheet

Updated Figure 30-1 on page 54. The positive Mux has two “Input” while the negative Mux has four “Input”

39.4 8387E – 11/2013

Updated Flash size column in “Ordering Information” on page 2 for:

ATxmega128A4U-AU, ATxmega128A4U-AUR, ATxmega128A4U-MH and ATxmega128A4U-MHR

1.

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39.5 8387D – 02/2013

1.

2.

3.

4.

5.

6.

7.

Updated typos in “Ordering Information” on page 2.

Updated PE2 and PE3 pins in “Pinout/Block Diagram” on page 4 to indicate that these can be used as TOSC pins.

Renamed pin 19 from VDD to VCC in Figure 2-1 on page 4.

Updated page size for ATxmega128A4U in Table 7-3 on page 17.

Added column for TWI using external driver interface in Table 32-3 on page 59.

Updated ATxmega16A4U leakage current in Table 36-7 on page 77.

Added application erase time for ATxmega16A4U in Table 36-21 on page 84.

Updated limits for VIH and VIL:

ATxmega16A4U: Table 36-7 on page 77

ATxmega32A4U: Table 36-39 on page 98

ATxmega64A4U: Table 36-71 on page 120

ATxmega128A4U:Table 36-103 on page 142

8.

Updated DAC clock and timing characteristics:

ATxmega16A4U: Table 36-13 on page 81

ATxmega32A4U: Table 36-45 on page 101

ATxmega64A4U: Table 36-77 on page 123

ATxmega128A4U: Table 36-109 on page 145.

9.

10.

11.

Updated ATxmega16A4U “ External clock characteristics” on page 86.

Added ESR parameter to the External 16MHz crystal oscillator and XOSC characteristics:

ATxmega16A4U: Table 36-29 on page 87

ATxmega32A4U: Table 36-61 on page 108

ATxmega64A4U: Table 36-93 on page 130

ATxmega128A4U: Table 36-125 on page 152.

12.

13.

14.

Updated ATxmega32A4U leakage current in Table 36-39 on page 98.

Added application erase time for ATxmega32A4U in Table 36-53 on page 105.

Updated ATxmega32A4U “ External clock characteristics” on page 107.

Updated ATxmega32A4U current consumption in electrical characteristics section, see “Current consumption” on

page 117.

15.

16.

17.

18.

19.

Updated electrical characteristics for “ATxmega64A4U” on page 115.

Updated typical characteristics for “ATxmega64A4U” on page 243.

Added application erase time for ATxmega128A4U in Table 36-117 on page 149.

Updated ATxmega128A4U “ External clock characteristics” on page 151.

39.6 8387C – 03/2012

1.

2.

3.

4.

Updated “Ordering Information” on page 2. Added a new package PW.

Updated “Packaging information” on page 68. A new package PW added.

Updated the Table 36-4 on page 74 with new values for I_CCactive power consumption.

Updated all typical characteristics in “ Active mode supply current” on page 159.

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5.

Updated all typical characteristics in “Power-down mode supply current” on page 166.

Added electrical characteristics for “ATxmega32A4U” on page 93.

Added electrical characteristics for “ATxmega64A4U” on page 115.

Added electrical characteristics for “ATxmega128A4U” on page 137.

Added typical characteristics for “ATxmega64A4U” on page 243

Added typical characteristics for “ATxmega64A4U” on page 243.

Added typical characteristics for “ATxmega128A4U” on page 285.

Updated “Errata” on page 327.

6.

7.

8.

9.

10.

12.

13.

14.

Used Atmel new datasheet template that includes Atmel new addresses on the last page.

39.7 8387B – 12/2011

1.

Updated Figure 2-1 on page 4: “Block Diagram and QFN/TQFP pinout”

2.

Updated Figure 3-1 on page 7: “XMEGA A4U Block Diagram”

Updated “Overview” on page 13.

3.

4.

Updated “ADC – 12-bit Analog to Digital Converter” on page 49.

Updated Figure 28-1 on page 50: “ADC overview.”

5.

6.

Updated “Instruction Set Summary” on page 63.

7.

Updated “Electrical Characteristics” on page 72.

8.

Updated “Typical Characteristics” on page 159.

9.

The order of several figures in the chapter “Typical Characteristics” has been changed

Several new figures have been added to and some figures have been removed from chapter “Typical Characteristics”

Several minor changes/corrections in text and figures have been performed

Table 32-2 on page 59 has been corrected

10.

11.

12.

13.

14.

15.

16.

Table 32-4 on page 60 has been corrected

Table 36-29 on page 85 has been corrected

Table 36-30 on page 86 has been corrected

The heading ”I/O Pin Characteristics” on page 164 has been corrected (the text “and Reset” has been removed)

39.8 8387A – 07/2011

1.

Initial revision.

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Table of Contents

1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1

Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

4.1

Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.1

6.2

6.3

6.4

6.5

6.6

6.7

6.8

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

7.1

7.2

7.3

7.4

7.5

7.6

7.7

7.8

7.9

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.11 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

7.12 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

8.2

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9.1

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

9.2

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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11.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

11.3 Sleep Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

12.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

13.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . . . . . . . . . . . 29

14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

14.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

14.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

15.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

15.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

16. TC0/1 – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

16.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

17. TC2 - Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

17.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

18.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

19.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

20.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

21.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

22. TWI – Two-Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

22.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

23.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

24.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

25.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

26. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

26.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

27.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

28. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

28.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

29. DAC – 12-bit Digital to Analog Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

29.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

30.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

31.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

32.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

32.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

35. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

35.1 44A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

35.2 PW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

35.3 44M1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

35.4 49C2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

36.1 ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

36.2 ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

36.3 ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

36.4 ATxmega128A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

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37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

37.1 ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159

37.2 ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201

37.3 ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

37.4 ATxmega128A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

38. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

38.1 ATxmega16A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327

38.2 ATxmega32A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

38.3 ATxmega64A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

38.4 ATxmega128A4U . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

39.1 8387H – 05/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

39.2 8387G – 03/2014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

39.3 8387F – 01/2014. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

39.4 8387E – 11/2013. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

39.5 8387D – 02/2013 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332

39.6 8387C – 03/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333

39.7 8387B – 12/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

39.8 8387A – 07/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334

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X

X X X X

X

Atmel Corporation

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型号：	ATXMEGA128A4U-ANR
厂家：	MICROCHIP
描述：	IC MCU 8BIT 128KB FLASH 44TQFP 时钟 ATM 异步传输模式外围集成电路
文件：	总339页 (文件大小：24148K)
中文：	中文翻译
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ATXMEGA128A4U-ANR [MICROCHIP]

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