DSC400-0113Q0001KI1T [MICROCHIP]

Configurable Four Output, Low Jitter Crystal-lessâ¢ Clock Generator;


型号：	DSC400-0113Q0001KI1T
厂家：	MICROCHIP
描述：	Configurable Four Output, Low Jitter Crystal-lessâ¢ Clock Generator
文件：	总20页 (文件大小：258K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSC400

Configurable Four Output, Low Jitter Crystal-less™ Clock Generator

Features

General Description

• Low RMS Phase Jitter: <1 ps (typ.)

• High Stability: ±25 ppm, ±50 ppm

• Wide Temperature Range:

The DSC400 is a four output crystal-less™ clock

generator. It utilizes proven PureSilicon™ MEMS

technology to provide excellent jitter and stability while

incorporating additional device functionality.

- Industrial –40°C to +85°C

The nominal frequencies of the outputs can be identical

or independently derived from common PLLs.

- Ext. Commercial –20°C to +70°C

• High Supply Noise Rejection: –50 dBc

• Four Format-Configurable Outputs:

- LVPECL, LVDS, HCSL, LVCMOS

• Available Pin-Selectable Frequency Table

- 1 Pin per Bank for 2 Frequency Sets

• Wide Frequency Range:

Each output may be configured independently to

support a single-ended LVCMOS interface or a

differential interface. Differential options include

LVPECL, LVDS, or HCSL.

The DSC400 provides two independent select lines for

choosing between two sets of pre-configured

frequencies per bank. It also has two OE pins to allow

for enabling and disabling outputs.

- 2.3 MHz – 460 MHz

• 20-Pin QFN Footprint (5.0 mm x 3.2 mm)

• Excellent Shock and Vibration Immunity

• High Reliability

The DSC400 is packaged in a 20-pin QFN (5 mm x

3.2 mm) and is available in extended commercial and

industrial temperature grades.

- 20x better MTF than quartz-based devices

• Wide Supply Range of 2.25V to 3.6V

• Lead Free and RoHS-Compliant

• AEC-Q100 Automotive Qualified

Block Diagram

CONTROL

CIRCUITRY

CLK0+

CLK0-

Applications

BANK 1

• Communications and Networks

CLK3+

CLK3-

PLL

MEMS

• Ethernet

OUTPUT

CONTROL

AND

- 1G, 10GBASE-T/KR/LR/SR, and FCoE

• Storage Area Networks

- SATA, SAS, Fibre Channel

• Passive Optical Networks

- EPON, 10G-EPON, GPON, 10G-PON

• HD/SD/SDI Video and Surveillance

• Automotive

PLL

DIVIDERS

OE1

OE2

CLK1+

CLK1-

BANK 2

FSB1

FSB2

CLK2+

CLK2-

• Media and Video

• Embedded and Industrial

 2016 Microchip Technology Inc.

DS20005612A-page 1

DSC400

1.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Supply Voltage .......................................................................................................................................... –0.3V to +4.0V

Input Voltage .......................................................................................................................................–0.3V to V_DD+0.3V

ESD Protection (HBM) ...............................................................................................................................................4 kV

ESD Protection (MM) ................................................................................................................................................400V

ESD Protection (CDM) ............................................................................................................................................1.5 kV

† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operational sections of this specification is not intended. Exposure to maximum rating conditions for extended

periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

Specifications: V_DD= 3.3V; T_A= +25°C unless otherwise specified.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Supply Voltage (Note 1)

V_DD

2.25

—

3.6

—

Core Supply Current (Note 2) I_DDCORE

OE(1:2) = 0. All outputs

disabled.

Frequency Stability

∆f

—

±25

±50

±5

ppm

All temperature and V_DD

ranges.

Aging - First Year

∆f_Y1

ppm One year at +25°C

Aging - After First Year

∆f_Y2

<±1

ppm/yr Year two and beyond at

+25°C

Start-up Time (Note 3)

Input Logic Levels

t_SU

V_IH

V_IL

t_DA

—

T = +25°C

0.75 x V_DD

—

0.25 x V_DD

Input logic high

Input logic low

—

Output Disable Time (Note 4)

Output Enable Time (Note 4)

Pull-Up Resistor

kΩ

OE(1:2) transition

from 1 to 0

t_EN

—

OE(1:2) transition

from 0 to 1

R_PU

All input pins have an

internal pull-up

Note 1: V_DDpins should be filtered with a 0.1 µF capacitor connected between V_DDand V_SS

2: The addition of I_DDCOREand I_DDIOprovides the total current consumption of the device.

3: t_SUis time to 100 ppm stable output frequency after V_DDis applied and outputs are enabled.

4: See the Output Waveform section for more information.

DS20005612A-page 2

 2016 Microchip Technology Inc.

DSC400

TEMPERATURE SPECIFICATIONS (Note 1)

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max.

Units

Conditions

T_A

T_J

T_S

—

–20

–40

—

+70

+85

°C

Ordering Option E

Operating Temperature Range (T)

Ordering Option I

Junction Temperature

+150

+260

—

Storage Temperature Range

Soldering Temperature

–40

—

40 sec. max.

Note 1: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable

junction temperature, and the thermal resistance from junction to air (i.e., T_A, T_J, _JA). Exceeding the

maximum allowable power dissipation will cause the device operating junction temperature to exceed the

maximum +125°C rating. Sustained junction temperatures above +125°C can impact the device reliability.

 2016 Microchip Technology Inc.

DS20005612A-page 3

DSC400

2.0

PIN DESCRIPTIONS

20 19 18 17 16 15

OE1

VSS

OE2

FIGURE 2-1:

Pin Configuration, 20-Pin QFN (5.0 mm x 3.2 mm)

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

Pin Number

PIN FUNCTION TABLE

Pin Name

Pin Type

Description

OE1

Output Enable for Bank1 (CLK0 and CLK3); Active-High. See

Table 3-1.

N/A

PWR

Leave unconnected or connect to ground.

Ground.

V_SS

Ground.

CLK0–

CLK0+

CLK1–

CLK1+

V_DD2

Complement output of differential pair 0 (off when in LVCMOS format).

True output of differential pair 0 or LVCMOS output 0.

Complement output of differential pair 1 (off when in LVCMOS format).

True output of differential pair 1 or LVCMOS output 1.

Power Supply for Bank2 (CLK1 and CLK2).

PWR

FSB2

Input for selecting pre-configured frequencies on Bank2 (CLK1 and

CLK2).

OE2

Output Enable for Bank2 (CLK1 and CLK2); Active-High. See

Table 3-1.

N/A

PWR

Leave unconnected or connect to ground.

Ground.

V_SS

Ground.

CLK2–

CLK2+

CLK3–

CLK3+

V_DD1

Complement output of differential pair 2 (off when in LVCMOS format).

True output of differential pair 2 or LVCMOS output 2.

Complement output of differential pair 3 (off when in LVCMOS format).

True output of differential pair 3 or LVCMOS output 3.

Power Supply for Bank1 (CLK0 and CLK3).

PWR

FSB1

Input for selecting pre-configured frequencies on Bank1 (CLK0 and

CLK3).

DS20005612A-page 4

 2016 Microchip Technology Inc.

DSC400

chosen from 2.3 MHz to 460 MHz for differential

outputs and from 2.3 MHz to 170 MHz on LVCMOS

outputs.

3.0

OPERATIONAL DESCRIPTION

The DSC400 is a crystal-less™ clock generator. Unlike

older clock generators in the industry, it does not

require an external crystal to operate; it relies on the

integrated MEMS resonator that interfaces with internal

PLLs. This technology enhances performance and

reliability by allowing tighter frequency stability over a

far wider temperature range. In addition, the higher

resistance to shock and vibration decreases the aging

rate to allow for much improved product life in the

system.

3.3

Power

V_DD1and V_DD2supply the power to banks 1 and 2

respectively. Each V_DDmay each have a different

supply voltage from the other as long as it is within the

2.25V to 3.6V range. Each V_DDpin should have a

0.1 µF capacitor to filter high-frequency noise. V_SSis

common to the entire device.

3.1

Inputs

There are four input signals in the device. Each has an

internal (40 kꢀ) pull-up to default the selection to a high

(1). Inputs can be controlled through hardware

strapping method with a resistor to ground to assert the

input low (0). Inputs may also be controlled by other

components’ GPIOs

In case more than one frequency set is desired, FSB1

and FSB2 are used to independently select one of two

sets per bank. FSB1 selects the pre-configured set on

Bank1 (CLK0 and CLK3) and FSB2 selects the

pre-configured set on Bank2 (CLK1 and CLK2), as

shown in Table 1-1 in the Product Identification System

section.

If there is a requirement to disable outputs, the inputs

OE1 and OE2 are used in conjunction to disable the

banks of outputs. Outputs are disabled in tri-state (Hi-Z)

mode. See Table 3-1 for more information.

TABLE 3-1:

OUTPUT ENABLE

SELECTION TABLE

Bank 1

(CLK0 & CLK3)

Bank 2

(CLK1 & CLK2)

OE1 OE2

Hi-Z

Running

Hi-Z

Running

3.2

Outputs

The four outputs are grouped into two banks. Each

bank is supplied by an independent V_DDto allow for

optimized noise isolation between the two banks. Each

bank provides two synchronous outputs generated by

a common PLL:

• Bank1 is composed of outputs CLK0 and CLK3.

• Bank2 is composed of outputs CLK1 and CLK2.

Each output may be pre-configured independently to

be one of the following formats: LVCMOS, LVDS,

LVPECL or HCSL. In case the output is configured to

be single-ended LVCMOS, the frequency is generated

on the true output (CLKx+) and the complement output

(CLKx–) is shut off in a low state. Frequencies can be

 2016 Microchip Technology Inc.

DS20005612A-page 5

DSC400

4.0

4.1

TERMINATION SCHEMES

LVPECL

V_DD

130 Ω

82 Ω

100 Ω

82 Ω

FIGURE 4-1:

Typical LVPECL Termination Scheme.

TABLE 4-1:

Parameter

LVPECL OUTPUTS (Note 1)

Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

V_OH

V_OL

—

V_DD– 1.08

—

V_DD– 1.55

—

Output Logic High, R_L= 50ꢀ to V_DD–2V

Output Logic Low, R_L= 50ꢀ to V_DD–2V

Single-Ended

—

Peak-to-Peak

Output Swing

800

Output

Transition Time

(Note 2)

t_R

t_F

—

250

—

Rise Time. 20% to 80%; R_L= 50ꢀ to

V_DD–2V

Fall Time. 20% to 80%; R_L= 50ꢀ to

V_DD–2V

Frequency

f₀

2.3

—

460

MHz Single Frequency

Output Duty

Cycle

SYM

Differential

IO Supply

Current (Note 3)

I_DDIO

J_PER

J_PH

—

Per Output at 125 MHz

Period Jitter

(Note 4)

2.5

ps_RMSCLK(0:3) = 156.25 MHz

Integrated

Phase Noise

—

0.25

0.38

1.7

—

ps_RMS200 kHz to 20 MHz @ 156.25 MHz

100 kHz to 20 MHz @ 156.25 MHz

12 kHz to 20 MHz @ 156.25 MHz

Note 1: LVPECL applicable to extended commercial temperature only.

2: See the Output Waveform section for more information.

3: The addition of I_DDCOREand I_DDIOprovides the total current consumption of the device.

4: Period jitter includes crosstalk from adjacent output.

DS20005612A-page 6

 2016 Microchip Technology Inc.

DSC400

4.2

LVDS

100 Ω

Load (receiver IC)

FIGURE 4-2:

Typical LVDS Termination Scheme.

If the 100ꢀ clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and

placed as close as possible to the receiver.

TABLE 4-2:

Parameter

LVDS OUTPUTS

Symbol

Min.

Typ.

Max.

Units

Condition

R = 100ꢀ Differential

Output Offset

Voltage

V_OS

1.125

—

1.4

Delta Offset

Voltage

ꢁV_OS

V_PP

t_R

—

Peak-to-Peak

Output Swing

350

200

Single-Ended

Output

Transition Time

(Note 1)

Rise Time, 20% to 80%, R_L= 50ꢀ,

C_L= 2 pF

t_F

Fall Time, 20% to 80%, R_L= 50ꢀ,

C_L= 2 pF

Frequency

f₀

2.3

—

460

MHz Single Frequency

Output Duty

Cycle

SYM

Differential

IO Supply

Current (Note 2)

I_DDIO

—

Per Output at 125 MHz.

—

Period Jitter

J_PER

J_PH

—

2.5

0.28

0.4

—

ps_RMS

Integrated

Phase Noise

ps_RMS200 kHz to 20 MHz @ 156.25 MHz

100 kHz to 20 MHz @ 156.25 MHz

12 kHz to 20 MHz @156.25 MHz

—

1.7

2.0

Note 1: See the Output Waveform section for more information.

2: The addition of I_DDCOREand I_DDIOprovides the total current consumption of the device.

 2016 Microchip Technology Inc.

DS20005612A-page 7

DSC400

4.3

HCSL

R_S

100 Ω

50 Ω

FIGURE 4-3:

Typical HCSL Termination Scheme.

R_Sis a series resistor implemented to match the trace impedance. Depending on the board layout, the value may range

from 0ꢀ to 30ꢀ.

TABLE 4-3:

Parameter

HCSL OUTPUTS

Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

V_OH

V_OL

—

0.725

—

0.1

—

Output Logic High, R_L= 50ꢀ

Output Logic Low, R_L= 50ꢀ

Single-Ended

Peak-to-Peak

Output Swing

—

750

Output

Transition Time

(Note 1)

t_R

t_F

200

—

400

Rise Time, 20% to 80%, R_L= 50ꢀ,

C_L= 2 pF

Fall Time, 20% to 80%, R_L= 50ꢀ,

C_L= 2 pF

Frequency

f₀

2.3

—

460

MHz Single Frequency

Output Duty

Cycle

SYM

Differential

IO Supply

I_DDIO

—

Per Output at 125 MHz.

Current (Note 2)

Period Jitter

J_PER

J_PH

—

2.5

0.25

0.37

1.7

—

ps_RMS

—

Integrated

Phase Noise

ps_RMS200 kHz to 20 MHz @ 156.25 MHz

100 kHz to 20 MHz @ 156.25 MHz

12 kHz to 20 MHz @156.25 MHz

—

2.0

Note 1: See the Output Waveform section for more information.

2: The addition of I_DDCOREand I_DDIOprovides the total current consumption of the device.

DS20005612A-page 8

 2016 Microchip Technology Inc.

DSC400

4.4

LVCMOS

50 Ω

R_S

FIGURE 4-4:

Typical LVCMOS Termination Scheme.

R_Sis a series resistor implemented to match the trace impedance to that of the clock output. Depending on the board

layout, the value may range from 0ꢀ to 27ꢀ.

TABLE 4-4:

Parameter

LVCMOS OUTPUTS

Symbol

Min.

Typ.

Max.

Units

Condition

Output Logic

Levels

V_OH

V_OL

t_R

0.9 x V_DD

—

0.1 x V_DD

2.0

Output Logic High, I = ±6 mA

Output Logic Low, I = ±6 mA

—

Output

Transition Time

(Note 1)

1.1

1.3

Rise Time, 20% to 80%, C_L= 15 pF

Fall Time, 20% to 80%, C_L= 15 pF

t_F

2.0

Frequency

f₀

2.3

—

170

MHz All Temperature Ranges, Except

Automotive

—

100

Automotive Temperature Range

Output Duty

Cycle

SYM

I_DDIO

—

IO Supply

—

Per Output at 125 MHz, C_L= 15 pF

Current (Note 2)

Period Jitter

J_PER

J_PH

—

ps_RMSCLK(0:3) = 125 MHz

Integrated

Phase Noise

0.3

0.38

1.7

ps_RMS200 kHz to 20 MHz @ 125 MHz

100 kHz to 20 MHz @ 125 MHz

12 kHz to 20 MHz @125 MHz

—

2.0

Note 1: See the Output Waveform section for more information.

2: The addition of I_DDCOREand I_DDIOprovides the total current consumption of the device.

 2016 Microchip Technology Inc.

DS20005612A-page 9

DSC400

5.0

OUTPUT WAVEFORM

t_R

t_F

Clk

80%

50%

20%

t_EN

1/f₀

t_DA

V_IH

V_IL

FIGURE 5-1:

Differential Output (LVDS, LVPECL, HCSL).

t_R

t_F

V_OH

Clk

V_OL

t_EN

1/f₀

t_DA

V_IH

V_IL

FIGURE 5-2:

LVCMOS Output.

DS20005612A-page 10

 2016 Microchip Technology Inc.

DSC400

6.0

CONNECTION DIAGRAM

The connection diagram below includes recommended capacitors to be placed on each V_DDfor noise filtering.

V_DD

Clock 3 Output

0.1μF

Clock 2 Output

Frequency Select 1

Output Enable 1

OE1

VSS

OE2

V_DD

0.1μF

Frequency Select 2

Output Enable 2

Clock 1 Output

Clock 0 Output

FIGURE 6-1:

DSC400 Connection Diagram.

 2016 Microchip Technology Inc.

DS20005612A-page 11

DSC400

7.0

SOLDER REFLOW PROFILE

Temperature

8 minutes max.

20-40

seconds

260°C

217°C

200°C

150°C

60-180

60-150

seconds

25°C

Preheat

Reflow

Cooldown

Time

MSL 1 @ 260°C refer to JSTD-020C

Ramp-Up Rate (200°C to Peak Temp)

Preheat Time 150°C to 200°C

Time Maintained above 217°C

Peak Temperature

3°C/sec. max.

60-180 sec.

60-150 sec.

255°C to 260°C

20-40 sec.

Time within 5°C of Actual Peak

Ramp-Down Rate

6°C/sec. max.

8 minutes max.

Time 25°C to Peak Temperature

DS20005612A-page 12

 2016 Microchip Technology Inc.

DSC400

8.0

PACKAGE MARKING INFORMATION

20-Lead QFN 5.0 mm x 3.2 mm Package Outline and Recommended Land Pattern

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging.

 2016 Microchip Technology Inc.

DS20005612A-page 13

DSC400

NOTES:

DS20005612A-page 14

 2016 Microchip Technology Inc.

DSC400

APPENDIX A: REVISION HISTORY

Revision A (September 2016)

• Converted Micrel data sheet DSC400 to Micro-

chip DS20005612A.

• Minor text changes throughout.

 2016 Microchip Technology Inc.

DS20005612A-page 15

DSC400

NOTES:

DS20005612A-page 16

 2016 Microchip Technology Inc.

DSC400

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.

Qxxxx

PART NO.

CLK2

Output

Format

Device CLK3

Output

Freq.

Code

CLK1 CLK0

Output Output

Format Format

Package

Temp. Stability

Range

Packing

Format

Examples:

Device:

DSC400:

Configurable Four Output, Low Jitter

Crystal-less Clock Generator

DSC400-2143QxxxxKE1T:

Configurable Four Output, Low Jitter Crystal-less

Clock Generator; LVPECL CLK3; LVCMOS CLK2;

HCSL CLK1; LVDS CLK0; Frequency Code; 20-Pin

QFN; –20°C to +70°C Temp. Range; ±50 ppm Stabil-

ity; Tape & Reel

CLK3 Output

Format:

OFF

LVCMOS

LVPECL

LVDS

HCSL

DSC400-4132QxxxxKI2T:

CLK2 Output

Format:

LVCMOS

LVPECL

LVDS

Configurable Four Output, Low Jitter Crystal-less

Clock Generator; HCSL CLK3; LVCMOS CLK2;

LVDS CLK1; LVPECL CLK0; Frequency Code; 20-

Pin QFN; –40°C to +85°C Temp. Range; ±25 ppm

Stability; Tape & Reel

HCSL

CLK1 Output

Format:

OFF

LVCMOS

LVPECL

LVDS

DSC400-0202QxxxxKE2T:

HCSL

Configurable Four Output, Low Jitter Crystal-less

Clock Generator; OFF CLK3; LVPECL CLK2; OFF

CLK1; LVPECL CLK0; Frequency Code; 20-Pin QFN;

–20°C to +70°C Temp. Range; ±25 ppm Stability;

Tape & Reel

CLK0 Output

Format:

LVCMOS

LVPECL

LVDS

HCSL

DSC400-1111QxxxxKI1T:

Frequency Code:

Package:

Qxxxx

This code is assigned by the factory. See the

table in this section for more information.

Configurable Four Output, Low Jitter Crystal-less

Clock Generator; LVCMOS CLK3 through CLK0;

Frequency Code; 20-Pin QFN; –40°C to +85°C Temp.

Range; ±50 ppm Stability; Tape & Reel

20-Pin QFN

Temperature

Range:

–20°C to +70°C

–40°C to +85°C

Stability:

Packing:

±50 ppm

±25 ppm

Tape & Reel

1.0

FACTORY CONFIGURATION CODE ASSIGNMENT OF QXXXX

The DSC400 is meant for customers to define their own frequency requirements at the four available outputs. The Qxxxx

number identifies these specific customer requirements and is assigned by the factory.

TABLE 1-1:

EXAMPLE OF HOW FSB1 & FSB2 ARE APPLIED & THE QXXXX ASSIGNMENT

FSB1

FSB2

Qxxxx Number

Outputs

1 (default)

125 MHz

50 MHz

Bank1

CLK0

CLK3

150 MHz

25 MHz

Q0001

Outputs

1 (default)

156.25 MHz

Bank2

CLK1

CLK2

100 MHz

 2016 Microchip Technology Inc.

DS20005612A-page 17

DSC400

NOTES:

DS20005612A-page 18

 2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate,

dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq,

KeeLoq logo, Kleer, LANCheck, LINK MD, MediaLB, MOST,

MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo,

RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O

are registered trademarks of Microchip Technology

Incorporated in the U.S.A. and other countries.

ClockWorks, The Embedded Control Solutions Company,

ETHERSYNCH, Hyper Speed Control, HyperLight Load,

IntelliMOS, mTouch, Precision Edge, and QUIET-WIRE are

registered trademarks of Microchip Technology Incorporated

in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut,

BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM,

dsPICDEM.net, Dynamic Average Matching, DAM, ECAN,

EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip

Connectivity, JitterBlocker, KleerNet, KleerNet logo, MiWi,

motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,

MPLINK, MultiTRAK, NetDetach, Omniscient Code

Generation, PICDEM, PICDEM.net, PICkit, PICtail,

PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker,

Serial Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total

Endurance, TSHARC, USBCheck, VariSense, ViewSpan,

WiperLock, Wireless DNA, and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

Silicon Storage Technology is a registered trademark of

Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip

Technology Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

CERTIFIEDꢀBYꢀDNVꢀ

ISBN: 978-1-5224-0985-4

== ISO/TSꢀ16949ꢀ==ꢀ

 2016 Microchip Technology Inc.

DS20005612A-page 19

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

Fax: 91-80-3090-4123

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Web Address:

www.microchip.com

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

Germany - Dusseldorf

Tel: 49-2129-3766400

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Beijing

Tel: 86-10-8569-7000

Fax: 86-10-8528-2104

Germany - Karlsruhe

Tel: 49-721-625370

India - Pune

Tel: 91-20-3019-1500

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Austin, TX

Tel: 512-257-3370

Japan - Osaka

Tel: 81-6-6152-7160

Fax: 81-6-6152-9310

Boston

China - Chongqing

Tel: 86-23-8980-9588

Fax: 86-23-8980-9500

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Japan - Tokyo

Tel: 81-3-6880- 3770

Fax: 81-3-6880-3771

China - Dongguan

Tel: 86-769-8702-9880

Italy - Venice

Tel: 39-049-7625286

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

China - Guangzhou

Tel: 86-20-8755-8029

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Hangzhou

Tel: 86-571-8792-8115

Fax: 86-571-8792-8116

Korea - Seoul

Cleveland

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Poland - Warsaw

Tel: 48-22-3325737

Independence, OH

Tel: 216-447-0464

Fax: 216-447-0643

China - Hong Kong SAR

Tel: 852-2943-5100

Fax: 852-2401-3431

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Sweden - Stockholm

Tel: 46-8-5090-4654

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Novi, MI

Tel: 248-848-4000

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Houston, TX

Tel: 281-894-5983

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Taiwan - Kaohsiung

Tel: 886-7-213-7828

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

06/23/16

DS20005612A-page 20

 2016 Microchip Technology Inc.

DSC400-0113Q0001KI1T [MICROCHIP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E