DSC501-051144KE0T [MICROCHIP]

OTHER CLOCK GENERATOR;
DSC501-051144KE0T
型号: DSC501-051144KE0T
厂家: MICROCHIP    MICROCHIP
描述:

OTHER CLOCK GENERATOR

时钟 外围集成电路
文件: 总7页 (文件大小:653K)
中文:  中文翻译
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DSC501-05  
Crystal-lessFour Output MFP Clock Generator  
General Description  
Features  
The DSC501-05 is a Crystal-less, four  
Three CMOS Outputs  
output multifunction printer clock generator.  
The clock generator uses proven silicon  
MEMS technology to provide excellent jitter  
and stability over a wide range of supply  
voltages and temperatures. By eliminating  
the external quartz crystal, MEMS clock  
generators significantly enhance reliability  
and accelerate product development, while  
meeting stringent clock performance criteria  
for a variety of applications.  
o 60MHz  
o 66.6667MHz  
o 60MHz or 100MHz selectable  
One PCIe 100MHz HCSL Output  
Available Output Formats:  
o CMOS, HCSL, LVPECL, or LVDS  
o Mixed Outputs: CMOS/LVPECL/HCSL/LVDS  
DSC501-05 has an Output Enable / Disable  
feature allowing it to disable all outputs  
when OE1 and OE2 are low. See the OE  
Wide Temperature Range  
o Ext. Industrial: -40° to 105° C  
function diagram for more detail.  
The  
o Industrial: -40° to 85° C  
device is available in a 20 pin QFN.  
Additional output formats are in any  
combination of CMOS, LVPECL, LVDS, and  
HCSL.  
o Ext. commercial: -20° to 70° C  
Supply Range of 2.25 to 3.6 V  
Low Power Consumption  
o 30% lower than competing devices  
Excellent Shock & Vibration Immunity  
o Qualified to MIL-STD-883  
Block Diagram  
Available Footprints:  
o 20 QFN  
Lead Free & RoHS Compliant  
Short Lead Time: 2 Weeks  
AEC-Q100 Automotive Qualified  
Applications  
o Multifunction Printer  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 1  
Crystal-less Four Output MFP Clock Generator  
DSC501-05  
Specifications (Unless specified otherwise: T=25° C, VDD =3.3V)  
Parameter  
Condition  
Min.  
Typ.  
Max.  
Unit  
Supply Voltage1  
VDD  
IDD  
2.25  
3.6  
V
EN pin low outputs are  
disabled  
EN pin high outputs are  
enabled  
Supply Current  
42  
46  
mA  
mA  
Supply Current2  
(Four HCSL Outputs)  
IDD  
120  
RL=50 Ω,  
FO1=FO2=FO3= FO4=100 MHz  
Includes frequency variations  
due to initial tolerance, temp.  
and power supply voltage  
T=25°C  
±100  
Frequency Stability  
Δf  
ppm  
ms  
V
±50  
5
Startup Time3  
Input Logic Levels  
Input logic high  
Input logic low  
tSU  
VIH  
VIL  
0.75xVDD  
-
-
0.25xVDD  
Output Disable Time4  
Output Enable Time  
Pull-Up Resistor2  
tDA  
5
ns  
ns  
tEN  
20  
Pull-up on OE pin  
40  
kΩ  
HCSL Outputs6  
Condition  
Parameter  
Min.  
Typ.  
750  
Max.  
Unit  
V
Output Logic Levels  
Output logic high  
Output logic low  
VOH  
VOL  
RL=50Ω  
0.725  
-
-
0.1  
Pk to Pk Output Swing  
Output Transition time4  
Rise Time  
Single-Ended  
mV  
ps  
20% to 80%  
RL=50Ω, CL= 2pF  
tR  
tF  
200  
400  
Fall Time  
Frequency  
f0  
Single Frequency  
Differential  
2.3  
48  
1007  
460  
52  
MHz  
%
Output Duty Cycle  
Period Jitter5  
SYM  
JPER  
FO1=FO2= FO3 = FO4 =100 MHz  
2.5  
psRMS  
TJ  
PCIe Gen 1.1  
22.7  
86.08  
psp-p  
Jitter, Phase  
(Common Clock  
Architecture)  
JRMS-CCHF  
JRMS-CCLF  
JRMS-CC  
PCIe Gen 2.1, 1.5MHz to Nyquist  
PCIe Gen 2.1, 10 kHz to 1.5 MHz  
PCIe Gen 3.0  
2.20  
0.08  
0.37  
3.18  
3.08  
1.08  
psRMS  
psRMS  
psRMS  
JRMS-DCHF  
PCIe Gen 2.1, 1.5MHz to Nyquist  
2.15  
4.08  
7.58  
1.08  
psRMS  
Integrated Phase Noise  
(Data Clock  
Architecture)  
JRMS-DCLF  
JRMS-DC  
PCIe Gen 2.1, 10 kHz to 1.5 MHz  
PCIe Gen 3.0  
0.06  
0.32  
psRMS  
psRMS  
Notes:  
1. Each VDD pin should be filtered with 0.01uf capacitor.  
2. Output is enabled if OE pin is floated or not connected.  
3. tsu is time to 100PPM stable output frequency after VDD is applied and outputs are enabled.  
4. Output Waveform and Connection Diagram define the parameters.  
5. Period Jitter includes crosstalk from adjacent output.  
6. Contact Sales@Discera.com for alternate output options (LVPECL, LVDS, LVCMOS).  
7. Contact Sales@Discera.com for alternative frequency options  
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 2  
Crystal-less Four Output MFP Clock Generator  
DSC501-05  
Absolute Maximum Ratings  
Item  
Min  
-0.3  
-0.3  
-
Max  
+4.0  
Unit  
V
Condition  
Supply Voltage  
Input Voltage  
Junction Temp  
Storage Temp  
Soldering Temp  
VDD+0.3  
+150  
V
°C  
°C  
°C  
V
-55  
-
+150  
+260  
40sec max.  
ESD  
HBM  
MM  
-
4000  
400  
CDM  
1500  
Solder Reflow Profile  
20-40  
Sec  
260°C  
217°C  
200°C  
60-150  
Sec  
Reflow  
60-180  
Sec  
150°C  
Cool  
Pre heat  
25°C  
Time  
8 min max  
20 QFN  
MSL 1 @ 260°C refer to JSTD-020C  
Ramp-Up Rate (200°C to Peak Temp)  
Preheat Time 150°C to 200°C  
Time maintained above 217°C  
Peak Temperature  
Time within 5°C of actual Peak  
Ramp-Down Rate  
3°C/Sec Max.  
60-180 Sec  
60-150 Sec  
255-260°C  
20-40 Sec  
6°C/Sec Max.  
8 min Max.  
Time 25°C to Peak Temperature  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 3  
Crystal-less Four Output MFP Clock Generator  
DSC501-05  
Pin Description (20 QFN)  
Pin No.  
Pin Name  
OE1  
Pin Type  
Description  
1
2
3
4
5
6
7
I
NA  
Power  
Power  
O
Output Enable; active high  
Leave unconnected or grounded  
Ground  
NC  
VSS  
VSS  
CLK0-  
CLK0+  
CLK1-  
Ground  
Complement output of differential pair  
O
O
True output of differential pair (60MHz LVCMOS Default)  
Complement output of differential pair  
True output of differential pair  
(66.6667MHz LVCMOS Default)  
Power Supply  
8
9
CLK1+  
VDD  
NC  
OE2  
NC  
O
Power  
NA  
I
NA  
Power  
Power  
O
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
Leave unconnected or grounded  
Output Enable; active high  
Leave unconnected or grounded  
Ground  
VSS  
VSS  
Ground  
CLK2-  
CLK2+  
CLK3-  
CLK3+  
VDD  
FS  
Complement output of differential pair  
True output of differential pair (100MHz HCSL Default)  
Complement output of differential pair  
True output of differential pair  
O
O
O
Power  
I
Power Supply  
0, CLK3 = 60MHz; 1, CLK3 = 100MHz (LVCMOS Default)  
Pin Diagram (20 QFN)  
Connection Diagram  
(20 QFN Four HCSL Outputs)  
20 19 18 17 16 15  
OE1  
NC  
1
2
3
4
14  
13  
12  
11  
VSS  
VSS  
NC  
VSS  
VSS  
OE2  
5
6
7
8
9
10  
20 QFN 5.0 x 3.2mm  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 4  
Crystal-less Four Output MFP Clock Generator  
DSC501-05  
OE Function and Output Waveform: HCSL or CMOS (CLK+ ONLY)  
tR  
tF  
CLK+  
80%  
50%  
20%  
675mV  
CLK-  
1/f0  
tDA  
tEN  
VIH  
OE  
VIL  
CLK1/CLK2 Synchronous  
OE1  
OE2  
CLK0 CLK1 CLK2 CLK3  
0
0
1
1
0
1
0
1
Hi-Z  
Hi-Z  
EN  
Hi-Z  
EN  
Hi-Z  
EN  
Hi-Z  
EN  
Hi-Z  
EN  
Hi-Z  
Hi-Z  
EN  
EN  
EN  
CLK0/CLK3 Synchronous  
Ordering Information  
DSC501-05 1 3 1 1 K I 0 T  
CLK 3 Output Format  
1: LVCMOS  
2: LVPECL  
Packing  
T: Tape & Reel  
3: LVDS  
4: HCSL  
Stability  
0: ±100ppm  
1: ±50ppm  
CLK 2 Output Format  
1: LVCMOS  
2: LVPECL  
3: LVDS  
4: HCSL  
Temp Range  
E: -20 to 70  
I: -40 to 85  
L: -40 to 105  
CLK 1 Output Format  
1: LVCMOS  
2: LVPECL  
Package  
K: 20 QFN  
3: LVDS  
4: HCSL  
CLK 0 Output Format  
1: LVCMOS  
2: LVPECL  
3: LVDS  
4: HCSL  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 5  
Crystal-less Four Output MFP Clock Generator  
DSC501-05  
Package Dimensions  
20 QFN, 5.0 x 3.2 mm  
Top View  
units: mm[inches]  
Bottom View  
units: mm[inches]±  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 6  
Crystal-less Four Output MFP Clock Generator  
DSC501-05  
Side View  
units: mm[inches]  
Recommended Solder Pad Layout  
units: mm[inches]  
*Connect the center pad to VSS for best thermal performance  
Disclaimer:  
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a  
warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license,  
whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of  
sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including  
liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.  
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to  
result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose  
failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or  
systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale.  
MICREL, Inc.  
Phone: +1 (408) 944-0800  
2180 Fortune Drive,  
Fax: +1 (408) 474-1000  
San Jose, California  
95131  
USA  
Email: hbwhelp@micrel.com  
www.micrel.com  
______________________________________________________________________________________________________________________________________________  
DSC501-05 Page 7  

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