DSPIC30F3011A-20E/P [MICROCHIP]
DSPIC30F3011A-20E/P;型号: | DSPIC30F3011A-20E/P |
厂家: | MICROCHIP |
描述: | DSPIC30F3011A-20E/P |
文件: | 总56页 (文件大小:6590K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
dsPIC30F
Family Overview
dsPIC® High Performance 16-bit
Digital Signal Controller
2003 Microchip Technology Inc.
Advance Information
DS70043D
Note the following details of the code protection feature on Microchip devices:
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and
PowerSmart are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, microID, MXDEV, MXLAB, PICMASTER, SEEVAL
and The Embedded Control Solutions Company are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Accuron, Application Maestro, dsPICDEM, dsPICDEM.net,
ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,
In-Circuit Serial Programming, ICSP, ICEPIC, microPort,
Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,
PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo,
PowerMate, PowerTool, rfLAB, rfPIC, Select Mode,
SmartSensor, SmartShunt, SmartTel and Total Endurance are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
Serialized Quick Turn Programming (SQTP) is a service mark
of Microchip Technology Incorporated in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2003, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received QS-9000 quality system
certification for its worldwide headquarters,
design and wafer fabrication facilities in
Chandler and Tempe, Arizona in July 1999
and Mountain View, California in March 2002.
The Company’s quality system processes and
procedures are QS-9000 compliant for its
PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals,
non-volatile memory and analog products. In
addition, Microchip’s quality system for the
design and manufacture of development
systems is ISO 9001 certified.
DS70043D-page ii
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
dsPIC® High Performance 16-bit
Digital Signal Controller Family Overview
Operating Range
On-Chip Flash, Data EEPROM and SRAM
• DC - 30 MIPS (30 MIPS @ 4.5-5.5V, -40 to 85°C)
• Wide VDD range: 2.5-5.5V
• Flash program memory: up to 144 Kbytes
- 1M erase/write cycles typ (-40 to 85°C)
• Data EEPROM: up to 4 Kbytes
• Ind.(-40 to 85°C) and ext. (-40 to 125°C)
- 1M erase/write cycle typ (-40 to 85°C)
- Data EEPROM Retention > 20 years
• Data SRAM: up to 8 Kbytes
High Performance DSC CPU
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
System Management
• 24-bit wide instructions
• Flexible clock options:
• Linear program memory addressing up to 4M
Instruction words
- External, crystal, resonator, internal RC
- Fully integrated PLL (4X, 8X, 16X)
- Extremely low jitter PLL
• Linear data memory addressing up to 64 Kbytes
• 84 base instructions: mostly 1 word/1 cycle
• 16 16-bit general purpose registers
• 2 40-bit accumulators
• Programmable power-up timer
• Oscillator start-up timer/stabilizer
• Watchdog timer with its own RC oscillator
• Fail-safe clock monitor
- With rounding and saturation options
• Flexible and powerful addressing modes
- Indirect, modulo and bit-reversed
• Software stack
• Reset by Multiple Sources
Power Management
• 16 x 16 fractional/integer multiply
• 32/16 and 16/16 divide
• Switch between clock sources in real time
• Power management by peripheral
• Programmable low-voltage detect
• Programmable brown-out reset
• Single cycle multiply-and-accumulate
- Accumulator write back for DSP operations
- Dual data fetch
• Idle and Sleep modes with fast wake-up
• 40-stage barrel shifter
Timers/Capture/Compare/PWM
Interrupt Controller
• Timer/counters: up to 5 16-bit timers
- Can pair up to make 32-bit timers
• 5 cycle latency
• Up to 45 interrupt sources, up to 5 external
• 7 programmable priority levels
• 4 processor exceptions and software traps
- 1 timer can run as real time clock with external
32 KHz oscillator
- Programmable prescaler
• Input capture: up to 8 channels
- Capture on up, down or both edges
- 16-bit Capture input functions
- 4-deep FIFO on each capture
• Output compare: up to 8 channels
- Single or dual 16-bit compare mode
- 16-bit glitchless PWM mode
Digital I/O
• Up to 54 programmable digital I/O pins
• Wake-up/Interrupt-on-change on up to 24 pins
• 25 mA sink and source on all I/O pins
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 1
dsPIC30F
Communication Modules
Analog-to-Digital Converters
• 3-wire SPI™: up to 2 modules
• 10-bit 500 ksps A/D converter module
- 2 or 4 simultaneous samples
- Framing supports I/O interface to simple
codecs
- Up to 16 input channels with auto scanning
- 16 deep result buffer
- 4-bit to 16-bit data
2
• I C™ full multi-master slave mode support
- Conversion start can be synchronized with
1of 3 trigger sources
- 7-bit and 10-bit addressing
- Bus collision detection and arbitration
• UART: up to 2 modules
- Conversion possible in Sleep mode
• 12-bit 100 ksps A/D converter module
- Up to 16 input channels with auto scanning
- 16 deep result buffer
- Interrupt-on-address bit detect
- Wake-up-on-Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
• Data Conversion Interface (DCI) module
- Codec interface
- Conversion possible in Sleep mode
CMOS Technology:
2
- Supports I S and AC97 protocols
• Low power, high speed Flash technology
• Fully static design
• CAN 2.0B active: up to 2 modules
- 3 transmit and 2 receive buffers
- Wake-up on CAN message
• Wide operating voltage range (2.5V to 5.5V)
• Industrial and extended temperature ranges
• Low power consumption
Motor Control Peripherals
• Motor Control PWM: up to 8 channels
- 4 duty cycle generators
Packaging:
• 80-pin TQFP
- Independent or complementary mode
- Programmable dead-time and output polarity
- Edge or center aligned
• 64-pin TQFP
• 40-pin DIP, 44-pin TQFP
• 28-pin DIP (300 mil), 28-pin SOIC
• 18-pin DIP (300 mil), 18-pin SOIC
- Manual output override control
- Up to 2 fault inputs
Note:
See Table 1-1, Table 1-2 and Table 1-3 for
exact peripheral features per device.
- Trigger for A/D conversions
• Quadrature encoder interface module
- Phase A, Phase B and index pulse input
- 16-bit up/down position counter
- Count direction status
- Position Measurement (x2 and x4) mode
- Programmable digital noise filters on inputs
- Alternate 16-bit Timer/Counter mode
- Interrupt on position counter rollover/
underflow
DS70043D-page 2
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
1.0
dsPIC30F PRODUCT FAMILIES
1.1
General Purpose Family
The dsPIC30F General Purpose Family (Table 1-1) is
ideal for a wide variety of 16-bit MCU class embedded
applications. The variants with Codec interfaces are
well suited for audio applications.
TABLE 1-1:
dsPIC30F GENERAL PURPOSE FAMILY VARIANTS
Program Memory
Output
Compare/
Std PWM
SRAM EEPROM Timer Input
Codec
A/D 12-bit
Device
Pins
Bytes
Bytes
16-bit Capt.
Interface 100 Ksps
Bytes
Instructions
dsPIC30F3014 40/44
dsPIC30F4013 40/44
24K
48K
8K
2048
2048
4096
6144
8192
4096
6144
8192
1024
1024
1024
2048
4096
1024
2048
4096
3
5
5
5
5
5
5
5
2
4
8
8
8
8
8
8
2
4
8
8
8
8
8
8
—
13 ch
13 ch
16 ch
16 ch
16 ch
16 ch
16 ch
16 ch
2
2
2
2
2
2
2
2
1
1
2
2
2
2
2
2
1
1
1
1
1
1
1
1
—
1
16K
22K
44K
48K
22K
44K
48K
AC97, I2S
AC97, I2S
—
dsPIC30F5011
dsPIC30F6011
dsPIC30F6012
dsPIC30F5013
dsPIC30F6013
dsPIC30F6014
64
64
64
80
80
80
66K
2
132K
144K
66K
2
AC97, I2S
AC97, I2S
—
2
2
132K
144K
2
AC97, I2S
2
motors, and switch reluctance motors. These products
are also well suited for uninterruptable power supply
(UPS), inverters, switched mode power supplies and
power factor correction and also for controlling the
power management module in servers, telecom
equipment and other industrial equipment.
1.2
Motor Control and Power
Conversion Family
This family of dsPIC30F controllers (see Table 1-2)
supports a variety of motor control applications such as
brushless DC motors, single and 3-phase induction
TABLE 1-2:
dsPIC30F MOTOR CONTROL AND POWER CONVERSION FAMILY VARIANTS
Program Memory
Output
Motor
SRAM EEPROM Timer Input
A/D 10-bit
500 Ksps
Device
Pins
Compare/ Control
Bytes
Bytes
16-bit Capt.
Bytes Instructions
Std PWM
PWM
dsPIC30F2010
dsPIC30F3010
dsPIC30F4012
dsPIC30F3011
dsPIC30F4011
dsPIC30F5015
dsPIC30F6010
28
28
12K
24K
48K
24K
48K
66K
144K
4K
8K
512
1024
1024
1024
1024
1024
1024
4096
3
5
5
5
5
5
5
4
4
4
4
4
4
8
2
2
2
4
4
4
8
6 ch
6 ch
6 ch
6 ch
6 ch
8 ch
8 ch
6 ch
6 ch
1
1
1
1
1
1
1
1
1
1
2
2
1
2
1
1
1
1
1
2
2
1
1
1
1
1
1
1
—
—
1
1024
2048
1024
2048
2048
8192
28
16K
8K
6 ch
40/44
40/44
64
9 ch
—
1
16K
22K
48K
9 ch
16 ch
16 ch
1
80
2
1.3
Sensor Family
The dsPIC30F Sensor Family products (Table 1-3)
have features designed to support high-performance,
low-cost embedded control applications. The 18- and
28-pin packages are designed to fit space-critical
applications.
TABLE 1-3:
dsPIC30F SENSOR PROCESSOR FAMILY VARIANTS
Program Memory
SRAM
Bytes
EEPROM
Bytes
Timer
16-bit
Input
Cap
Output Comp/
Std PWM
A/D 12-bit
100 Ksps
Device
Pins
Bytes
12K
Instructions
dsPIC30F2011
dsPIC30F3012
dsPIC30F2012
dsPIC30F3013
18
18
28
28
4K
8K
4K
8K
1024
2048
1024
2048
0
3
3
3
3
2
2
2
2
2
2
2
2
8 ch
8 ch
1
1
1
2
1
1
1
1
1
1
1
1
24K
1024
0
12K
10 ch
10 ch
24K
1024
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 3
dsPIC30F
1.4
Product Identification System
Figure 1-1 illustrates the part number structure.
To order or obtain information, e.g., on pricing or
delivery, refer to the factory or the listed sales office
FIGURE 1-1:
PART NUMBER STRUCTURE
dsPIC30LF1001AT-30I/PT-000
Custom ID
Package
Trademark
Architecture
I/O Voltage
PT = TQFP 10x10
PT = TQFP 12x12
PF = TQFP 14x14
SO = SOIC
SP = SDIP
Memory
Type
S
= Die (Waffle Pack)
= DIP
P
Flash = F
Memory Size in Bytes
W
= Die (Wafers)
0 = ROM-less
1 = 1K to 6K
Temperature
2 = 7K to 12K
I = Industrial -40°C to +85°C
3 = 13K to 24K
4 = 25K to 48K
5 = 49K to 96K
6 = 97K to 192K
7 = 193K to 384K
8 = 385K to 768K
9 = 769K and Up
E = Extended High Temp -40°C to +125°C
20 = 20MIPS
Speed
30 = 30MIPS
T = Tape and Reel
A,B,C… = Revision
Device ID
2.0
DEVICE OVERVIEW FOR
GENERAL PURPOSE AND
SENSOR FAMILY
Note:
The device(s) depicted in Figure 2-1 are
representative of this family. Other devices
of the same family may vary in terms of
number of pins and multiplexing of pin
functions. Typically, smaller devices in the
family contain a subset of the peripherals
present in the device(s) shown here.
Figure 2-1 shows a sample device block diagram
typical of the dsPIC30F General Purpose Product
Family.
Table 2-1 describes the pin functionality. Figure 2-2
illustrates the 80-pin TQFP pin out for the
dsPIC30F5013 and dsPIC30F6014. Figure 2-3
illustrates the 80-pin TQFP pin out for the
dsPIC30F6013.
DS70043D-page 4
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
FIGURE 2-1:
dsPIC30F5013/6013/6014 BLOCK DIAGRAM
RA6/CN22
RA7/CN23
REF-/RA9
REF+/RA10
Y Data Bus
X Data Bus
V
16 16
16
V
16
INT1/RA12
INT2/RA13
INT3/RA14
INT4/RA15
Data Latch
Data Latch
Interrupt
PSV & Table
Data Access
Control Block
Controller
Y Data
RAM
X Data
RAM
8
16
24
(4 Kbytes)
(4 Kbytes)
PORTA
16
Address
Latch
Address
Latch
24
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/CN5/RB3
16 16
16
X RAGU
X WAGU
24
Y AGU
PCH PCL
PCU
AN4/CN6/RB4
AN5/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
(144 Kbytes)
AN8/RB8
AN9/RB9
Data EEPROM
(4 Kbytes)
AN10/RB10
Effective Address
AN11/RB11
16
Data Latch
AN12/RB12
AN13/RB13
AN14/RB14
ROM Latch
16
AN15/OCFB/CN12/RB15
24
PORTB
T2CK/RC1
IR
T3CK/RC2
T4CK/RC3
16
16
T5CK/RC4
16 x 16
EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
W Reg Array
Decode
Instruction
Decode &
Control
PORTC
16
16
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
Control Signals
DSP
OC4/RD3
Divide
Unit
to Various Blocks
Power-up
Engine
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/RD7
IC1/RD8
Timer
Oscillator
Timing
Generation
OSC1/CLKI
Start-up Timer
ALU<16>
POR/BOR
Reset
IC2/RD9
IC3/RD10
IC4/RD11
16
16
Watchdog
Timer
MCLR
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
Low Voltage
Detect
VDD, VSS
AVDD, AVSS
PORTD
C1RX/RF0
C1TX/RF1
U1RX/RF2
U1TX/RF3
Input
Output
CAN1,
CAN2
2
I C
Capture
Module
Compare
Module
12-bit ADC
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
SPI1,
SPI2
UART1,
UART2
DCI
EMUD3/SDO1/RF8
Timers
PORTF
C2RX/RG0
C2TX/RG1
SCL/RG2
SDA/RG3
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
CSDI/RG12
CSDO/RG13
CSCK/RG14
COFS/RG15
PORTG
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 5
dsPIC30F
Table 2-1 provides a brief description of device I/O
pinouts and functions that may be multiplexed to a port
pin. Multiple functions may exist on one port pin. When
multiplexing occurs, the peripheral module’s functional
requirements may force an override of the data
direction of the port pin.
TABLE 2-1:
PINOUT I/O DESCRIPTIONS
Pin
Buffer
Type
Pin Name
Description
Type
AN0-AN15
I
Analog
Analog input channels.
AN0 and AN1 are also used for device programming data and clock
inputs, respectively.
AVDD
AVSS
CLKI
P
P
I
P
P
Positive supply for analog module.
Ground reference for analog module.
ST/CMOS
External clock source input. Always associated with OSC1 pin
function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs. Can be software programmed for
internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
I/O
I/O
I
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
CSDO
O
C1RX
C1TX
C2RX
C2TX
I
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN2 bus transmit pin.
O
I
ST
—
O
EMUD
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Primary data I/O pin for ICD Communication Channel.
Primary clock input pin for ICD Communication Channel.
Alternate 1 data I/O pin for ICD Communication Channel.
Alternate 1 clock input pin for ICD Communication Channel.
Alternate 2 data I/O pin for ICD Communication Channel.
Alternate 2 clock input pin for ICD Communication Channel.
Alternate 3 data I/O pin for ICD Communication Channel.
Alternate 3 clock input pin for ICD Communication Channel.
EMUC
I
I/O
I
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I
I/O
I
IC1-IC8
I
ST
Capture inputs 1 through 8.
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
LVDIN
MCLR
I
Analog
ST
Low Voltage Detect input.
I/P
Master Clear (Reset) input or programming voltage input. This pin is
an active low Reset to the device.
OCFA
I
I
ST
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OCFB
OC1-OC8
O
OSC1
OSC2
I
ST/CMOS
Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power
DS70043D-page 6
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
TABLE 2-1:
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
Pin Name
Description
PORTA is a bidirectional I/O port.
Type
RA6-RA7
I/O
I/O
I/O
ST
ST
ST
RA9-RA10
RA12-RA15
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
RC1-RC4
I/O
I/O
ST
ST
RC13-RC15
RD0-RD15
RF0-RF8
I/O
I/O
ST
ST
PORTD is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
PORTG is a bidirectional I/O port.
RG0-RG3
RG6-RG9
RG12-RG15
I/O
I/O
I/O
ST
ST
ST
SCK1
SDI1
SDO1
SS1
I/O
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
I
O
I
SPI1 Data Out.
ST
ST
ST
—
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
SPI2 Data Out.
ST
SPI2 Slave Synchronization.
2
Synchronous serial clock input/output for I C.
SCL
SDA
I/O
I/O
ST
ST
2
Synchronous serial data input/output for I C.
SOSCI
I
ST/CMOS
—
32 kHz low power oscillator crystal input; CMOS otherwise.
32 kHz low power oscillator crystal output.
SOSCO
O
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1RX
U1TX
I
O
I
ST
—
UART1 Receive.
UART1 Transmit.
U1ARX
U1ATX
U2RX
U2TX
ST
—
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
O
I
ST
—
O
UART2 Transmit.
VDD
P
P
I
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Analog Voltage Reference (High) input.
Analog Voltage Reference (Low) input.
VSS
—
VREF+
VREF-
Analog
Analog
I
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 7
dsPIC30F
FIGURE 2-2:
PIN DIAGRAM FOR 80-PIN GENERAL PURPOSE CONTROLLER
WITH CODEC MODULE
80-Pin TQFP
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
EMUC2/OC1/RD0
IC4/RD11
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
9
COFS/RG15
T2CK/RC1
T3CK/RC2
T4CK/RC3
IC3/RD10
T5CK/RC4
IC2/RD9
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
IC1/RD8
INT4/RA15
INT3/RA14
VSS
dsPIC30F5013
SS2/CN11/RG9
VSS
10
11
12
13
14
15
16
17
18
19
20
OSC2/CLKO/RC15
OSC1/CLKI
dsPIC30F6014
VDD
VDD
INT1/RA12
INT2/RA13
AN5/CN7/RB5
SCL/RG2
SDA/RG3
EMUC3/SCK1/INT0/RF6
SDI1/RF7
AN4/CN6/RB4
AN3/CN5/RB3
EMUD3/SDO1/RF8
U1RX/RF2
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
U1TX/RF3
DS70043D-page 8
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
FIGURE 2-3:
PIN DIAGRAM FOR 80-PIN GENERAL PURPOSE CONTROLLER
WITHOUT CODEC MODULE
80-Pin TQFP
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
EMUC2/OC1/RD0
IC4/RD11
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
RG15
T2CK/RC1
3
T3CK/RC2
T4CK/RC3
4
IC3/RD10
T5CK/RC4
5
IC2/RD9
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
6
IC1/RD8
7
INT4/RA15
8
INT3/RA14
VSS
9
SS2/CN11/RG9
10
dsPIC30F6013
OSC2/CLKO/RC15
OSC1/CLKI
VSS
11
12
13
14
15
16
17
18
19
20
VDD
VDD
INT1/RA12
SCL/RG2
SDA/RG3
INT2/RA13
AN5/CN7/RB5
AN4/CN6/RB4
AN3/CN5/RB3
EMUC3/SCK1/INT0/RF6
SDI1/RF7
EMUD3/SDO1/RF8
U1RX/RF2
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
U1TX/RF3
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 9
dsPIC30F
3.0
DEVICE OVERVIEW FOR
MOTOR CONTROL FAMILY
Note:
The device(s) depicted in Figure 3-1 are
representative of this family. Other devices
of the same family may vary in terms of
number of pins and multiplexing of pin
functions. Typically, smaller devices in the
family contain a subset of the peripherals
present in the device(s) shown here.
Figure 3-1 shows a sample device block diagram
typical of the dsPIC30F Motor Control Product Family.
Table 3-1 describes the pin functionality. Figure 3-2
illustrates the pin out of the 80-pin TQFP Device.
FIGURE 3-1:
dsPIC30F6010 BLOCK DIAGRAM
Y Data Bus
X Data Bus
16 16
16
16
VREF-/RA9
16
VREF+/RA10
Data Latch
Data Latch
Interrupt
Controller
INT3/RA14
INT4/RA15
PSV & Table
Data Access
Control Block
X Data
RAM
Y Data
RAM
8
16
24
(4 Kbytes)
(4 Kbytes)
PORTA
Address
Latch
Address
Latch
24
PGD/EMUD/AN0/CN2/RB0
PGC/EMUC/AN1/CN3/RB1
AN2/SS1/LVDIN/CN4/RB2
AN3/INDX/CN5/RB3
16
16
16
X RAGU
X WAGU
24
Y AGU
PCH PCL
PCU
AN4/QEA/CN6/RB4
AN5/QEB/CN7/RB5
AN6/OCFA/RB6
AN7/RB7
Program Counter
Stack
Control
Logic
Loop
Control
Logic
Address Latch
Program Memory
(144 Kbytes)
AN8/RB8
AN9/RB9
Data EEPROM
(4 Kbytes)
AN10/RB10
Effective Address
AN11/RB11
16
Data Latch
AN12/RB12
AN13/RB13
AN14/RB14
ROM Latch
16
AN15/OCFB/CN12/RB15
24
PORTB
T2CK/RC1
IR
T4CK/RC3
16
EMUD1/SOSCI/CN1/RC13
EMUC1/SOSCO/T1CK/CN0/RC14
OSC2/CLKO/RC15
16
16 x 16
W Reg Array
Decode
PORTC
Instruction
Decode &
Control
16 16
EMUC2/OC1/RD0
EMUD2/OC2/RD1
OC3/RD2
Control Signals
to Various Blocks
DSP
Engine
OC4/RD3
Divide
Unit
Power-up
OC5/CN13/RD4
OC6/CN14/RD5
OC7/CN15/RD6
OC8/CN16/UPDN/RD7
IC1/RD8
Timer
Timing
Generation
Oscillator
OSC1/CLKI
Start-up Timer
ALU<16>
POR/BOR
Reset
IC2/RD9
IC3/RD10
IC4/RD11
16
16
Watchdog
Timer
MCLR
IC5/RD12
IC6/CN19/RD13
IC7/CN20/RD14
IC8/CN21/RD15
Low Voltage
Detect
VDD, VSS
AVDD, AVSS
PORTD
PWM1L/RE0
PWM1H/RE1
PWM2L/RE2
PWM2H/RE3
PWM3L/RE4
PWM3H/RE5
PWM4L/RE6
PWM4H/RE7
FLTA/INT1/RE8
FLTB/INT2/RE9
Input
Output
Compare
Module
CAN1,
2
I C
Capture
Module
10-bit ADC
CAN2
UART1,
UART2
SPI1,
SPI2
Motor Control
PWM
QEI
Timers
PORTE
C1RX/RF0
C2RX/RG0
C1TX/RF1
C2TX/RG1
SCL/RG2
SDA/RG3
U1RX/RF2
U1TX/RF3
U2RX/CN17/RF4
U2TX/CN18/RF5
EMUC3/SCK1/INT0/RF6
SDI1/RF7
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
SS2/CN11/RG9
EMUD3/SDO1/RF8
PORTG
PORTF
DS70043D-page 10
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
Table 3-1 provides a brief description of device I/O
pinouts and the functions that may be multiplexed to a
port pin. Multiple functions may exist on one port pin.
When multiplexing occurs, the peripheral module’s
functional requirements may force an override of the
data direction of the port pin.
TABLE 3-1:
PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY
Pin
Buffer
Type
Pin Name
Description
Type
AN0-AN15
I
Analog
Analog input channels.
AN0 and AN1 are also used for device programming data and clock inputs, respectively.
Positive supply for analog module.
AVDD
AVSS
P
P
P
P
Ground reference for analog module.
CLKI
I
ST/CMOS External clock source input. Always associated with OSC1 pin function.
CLKO
O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always
associated with OSC2 pin function.
CN0-CN23
I
ST
Input change notification inputs.
Can be software programmed for internal weak pull-ups on all inputs.
COFS
CSCK
CSDI
I/O
I/O
I
ST
ST
ST
—
Data Converter Interface frame synchronization pin.
Data Converter Interface serial clock input/output pin.
Data Converter Interface serial data input pin.
Data Converter Interface serial data output pin.
CSDO
O
C1RX
C1TX
C2RX
C2TX
I
ST
—
CAN1 bus receive pin.
CAN1 bus transmit pin.
CAN2 bus receive pin.
CAN2 bus transmit pin.
O
I
ST
—
O
EMUD
I/O
ST
ST
ST
ST
ST
ST
ST
ST
Primary data I/O pin for ICD Communication Channel.
Primary clock input pin for ICD Communication Channel.
Alternate 1 data I/O pin for ICD Communication Channel.
Alternate 1 clock input pin for ICD Communication Channel.
Alternate 2 data I/O pin for ICD Communication Channel.
Alternate 2 clock input pin for ICD Communication Channel.
Alternate 3 data I/O pin for ICD Communication Channel.
Alternate 3 clock input pin for ICD Communication Channel.
EMUC
I
I/O
I
EMUD1
EMUC1
EMUD2
EMUC2
EMUD3
EMUC3
I/O
I
I/O
I
IC1-IC8
I
ST
Capture inputs 1 through 8.
INDX
QEA
I
I
ST
ST
Quadrature Encoder Index Pulse input.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Quadrature Encoder Phase A input in QEI mode.
Auxiliary Timer External Clock/Gate input in Timer mode.
Position Up/Down Counter Direction State.
QEB
I
ST
UPDN
O
CMOS
INT0
INT1
INT2
INT3
INT4
I
I
I
I
I
ST
ST
ST
ST
ST
External interrupt 0.
External interrupt 1.
External interrupt 2.
External interrupt 3.
External interrupt 4.
LVDIN
I
Analog
Low Voltage Detect Reference Voltage input pin.
FLTA
I
ST
ST
—
—
—
—
—
—
—
—
PWM Fault A input.
PWM Fault B input.
PWM 1 Low output.
PWM 1 High output.
PWM 2 Low output.
PWM 2 High output.
PWM 3 Low output.
PWM 3 High output.
PWM 4 Low output.
PWM 4 High output.
FLTB
I
PWM1L
PWM1H
PWM2L
PWM2H
PWM3L
PWM3H
PWM4L
PWM4H
O
O
O
O
O
O
O
O
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 11
dsPIC30F
TABLE 3-1:
PINOUT I/O DESCRIPTIONS FOR MOTOR CONTROL FAMILY (CONTINUED)
Pin
Buffer
Type
Pin Name
Description
Type
MCLR
I/P
ST
Master Clear (Reset) input or programming voltage input. This pin is an active low
Reset to the device.
OCFA
I
I
ST
ST
—
Compare Fault A input (for Compare channels 1, 2, 3 and 4).
Compare Fault B input (for Compare channels 5, 6, 7 and 8).
Compare outputs 1 through 8.
OCFB
OC1-OC8
O
OSC1
OSC2
I
ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise.
I/O
—
Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode.
Optionally functions as CLKO in RC and EC modes.
PGD
PGC
I/O
I
ST
ST
In-Circuit Serial Programming data input/output pin.
In-Circuit Serial Programming clock input pin.
RA9-RA10
I/O
I/O
ST
ST
PORTA is a bidirectional I/O port.
RA14-RA15
RB0-RB15
I/O
ST
PORTB is a bidirectional I/O port.
PORTC is a bidirectional I/O port.
RC1
I/O
I/O
I/O
ST
ST
ST
RC3
RC13-RC15
RD0-RD15
RE0-RE9
RF0-RF8
I/O
I/O
I/O
ST
ST
ST
PORTD is a bidirectional I/O port.
PORTE is a bidirectional I/O port.
PORTF is a bidirectional I/O port.
PORTG is a bidirectional I/O port.
RG0-RG3
RG6-RG9
I/O
I/O
ST
ST
SCK1
SDI1
SDO1
SS1
I/O
ST
ST
—
Synchronous serial clock input/output for SPI1.
SPI1 Data In.
I
O
I
SPI1 Data Out.
ST
ST
ST
—
SPI1 Slave Synchronization.
Synchronous serial clock input/output for SPI2.
SPI2 Data In.
SCK2
SDI2
SDO2
SS2
I/O
I
O
I
SPI2 Data Out.
ST
SPI2 Slave Synchronization.
2
Synchronous serial clock input/output for I C.
SCL
SDA
I/O
I/O
ST
ST
2
Synchronous serial data input/output for I C.
SOSCI
I
ST/CMOS 32 kHz low power oscillator crystal input; CMOS otherwise.
SOSCO
O
—
32 kHz low power oscillator crystal output.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Timer1 external clock input.
Timer2 external clock input.
Timer3 external clock input.
Timer4 external clock input.
Timer5 external clock input.
U1RX
U1TX
I
O
I
ST
—
UART1 Receive.
UART1 Transmit.
U1ARX
U1ATX
U2RX
U2TX
ST
—
UART1 Alternate Receive.
UART1 Alternate Transmit.
UART2 Receive.
O
I
ST
—
O
UART2 Transmit.
VDD
P
P
I
—
Positive supply for logic and I/O pins.
Ground reference for logic and I/O pins.
Analog Voltage Reference (High) input.
Analog Voltage Reference (Low) input.
VSS
—
VREF+
VREF-
Analog
Analog
I
Legend: CMOS = CMOS compatible input or output Analog = Analog input
ST = Schmitt Trigger input with CMOS levels O = Output I = Input P = Power
DS70043D-page 12
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
FIGURE 3-2:
PIN DIAGRAM FOR 80-PIN MOTOR CONTROLLER DEVICE
80-Pin TQFP
EMUC1/SOSCO/T1CK/CN0/RC14
EMUD1/SOSCI/CN1/RC13
EMUD2/OC1/RD0
IC4/RD11
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
PWM3H/RE5
PWM4L/RE6
2
3
PWM4H/RE7
T2CK/RC1
4
IC3/RD10
T4CK/RC3
5
IC2/RD9
SCK2/CN8/RG6
SDI2/CN9/RG7
SDO2/CN10/RG8
MCLR
6
IC1/RD8
7
INT4/RA15
8
INT3/RA14
VSS
9
SS2/CN11/RG9
VSS
10
11
12
13
14
15
16
17
18
19
20
dsPIC30F6010
OSC2/CLKO/RC15
OSC1/CLKI
VDD
VDD
FLTA/INT1/RE8
FLTB/INT2/RE9
AN5/QEB/CN7/RB5
SCL/RG2
SDA/RG3
AN4/QEA/CN6/RB4
AN3/INDX/CN5/RB3
EMUC3/SCK1/INT0/RF6
SDI1/RF7
AN2/SS1/LVDIN/CN4/RB2
PGC/EMUC/AN1/CN3/RB1
PGD/EMUD/AN0/CN2/RB0
EMUD3/SDO1/RF8
U1RX/RF2
U1TX/RF3
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 13
dsPIC30F
Overhead-free circular buffers (modulo addressing) are
supported in both X and Y address spaces. This is
primarily intended to remove the loop overhead for
DSP algorithms.
4.0
CORE ARCHITECTURE
OVERVIEW
4.1
Core Overview
The X AGU also supports bit-reversed addressing on
destination effective addresses, to greatly simplify input
or output data reordering for radix-2 FFT algorithms.
The dsPIC30F core is a 16-bit (data) modified Harvard
architecture with an enhanced instruction set, including
significant support for DSP. The core has a 24-bit
instruction word. The Program Counter (PC) is 23-bits
wide, with the Least Significant (LS) bit always clear
and the Most Significant (MS) bit is ignored during
normal program execution, except for certain
specialized instructions. Thus, the PC can address up
to 4M instruction words of user program space. An
instruction pre-fetch mechanism is used to help
maintain throughput. Unconditional overhead free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any point.
The core supports Inherent (no operand), Relative,
Literal, Memory Direct, Register Direct, Register
Indirect and Register Offset Addressing modes.
Instructions are associated with predefined Addressing
modes, depending upon their functional requirements.
For most instructions, the core is capable of executing
a data (or program data) memory read, a working
register (data) read, a data memory write and a
program (instruction) memory read per instruction
cycle. As
a result, 3-operand instructions are
supported, allowing C=A+B type operations to be
executed in a single cycle.
The working register array consists of 16 x 16-bit
registers, each of which can act as data, address or
offset registers. One working register (W15) operates
as a software stack pointer for interrupts and calls.
A DSP engine has been included to significantly
enhance the core arithmetic capability and throughput.
It features a high-speed 17-bit by 17-bit multiplier, a
40-bit ALU, two 40-bit saturating accumulators and a
40-bit bidirectional barrel shifter. Data in the
accumulator, or any working register, can be shifted up
to 15 bits right or 16 bits left in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MAC class of instructions can
concurrently fetch two data operands from memory,
while multiplying two W registers in one instruction
cycle. To enable this concurrent fetching of data
operands, the data space is split for these instructions
and linear for all others. This is achieved in a
transparent and flexible manner through dedicating
certain working registers to each address space for the
MACclass of instructions.
The data space is 64 Kbytes (32K words), and is split
into two blocks, referred to as X and Y data memory.
Each block has its own independent Address
Generation Unit (AGU). Most instructions operate
solely through the X memory AGU, which combines the
X and Y memory into a single unified data space. The
Multiply-Accumulate (MAC) class of dual source DSP
instructions operate through both the X and Y AGUs,
splitting the data address space into two parts. The X
and Y data space boundary is device specific and
cannot be altered by the user. Each data word consists
of 2 bytes, and most instructions can address data
either as words or bytes.
There are two methods of accessing data stored in
program memory:
The core does not support a multi-stage instruction
pipeline. However, a single stage instruction pre-fetch
mechanism is used, which accesses and partially
pre-decodes instructions a cycle ahead to maximize
available execution time. Most instructions execute in a
single cycle, with certain exceptions, as outlined in
Section 4.1.2 Instruction Fetch Mechanism.
• The upper 32 Kbytes of data space memory can
optionally be mapped into the lower half (user
space) of program space at any 16K program
word boundary defined by the 8-bit Program
Space Visibility Page (PSVPAG) register. This lets
any instruction access program space as if it were
data space, with the sole limitation that the access
requires an additional cycle. Only the lower 16
bits of each instruction word can be accessed
using this method.
The core features a vectored exception processing
structure for traps and interrupts, with 62 independent
vectors. The exceptions consist of up to 8 traps and 54
interrupts. Each interrupt is prioritized, based on a user
assigned priority between 1 and 7 (1 being the lowest
priority and 7 being the highest), in conjunction with a
predetermined ‘natural order’.
• Linear indirect access of 32K word pages within
program space is also possible, using any
working register via table read and write
instructions. Table read and write instructions can
be used to access all 24 bits of an instruction
word.
DS70043D-page 14
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
4.1.1
COMPILER DRIVEN
ENHANCEMENTS
4.2
Programmer’s Model
The programmer’s model is shown in Figure 4-1 and
consists of 16 x 16-bit working registers (W0 through
W15), 2 x 40-bit accumulators (ACCA and ACCB),
Status Register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT), and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 is the W register for all instructions that
perform file register addressing.
In addition to DSP performance requirements, the core
architecture was strongly influenced by recommenda-
tions which would lead to a more efficient (code size
and speed) C compiler.
1. For most instructions, the core is capable of
executing a data (or program data) memory
read, a working register (data) read, a data
memory write and a program (instruction)
memory read per instruction cycle. As a result,
3-operand instructions can be supported,
allowing C=A+B operations to be executed in a
single cycle.
Some of these registers have a shadow register
associated with them, as shown in Figure 4-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon some event occurring. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
2. Instruction Addressing modes are extremely
flexible to meet compiler needs.
3. The working register array is comprised of 16 x
16-bit registers, each of which can act as data,
address or offset registers. One working register
(W15) operates as the software stack pointer for
interrupts and calls.
• PUSH.Sand POP.S
W0...W3, SR (DC, N, OV, Z and C bits only)
4. Linear indirect access of all data space is
possible, plus the memory direct address range
is up to 8 Kbytes. This, together with the addition
of 16-bit direct address MOVbased instructions,
has provided a contiguous linear addressing
space.
transferred
• DOinstruction
DOSTART, DOEND, DCOUNT shadows pushed
on loop start, popped on loop end
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte wide data memory space accesses.
5. Linear indirect access of 32K word (64 Kbyte)
pages within program space is possible, using
any working register via new table read and
write instructions.
6. Part of data space can be mapped into program
space, allowing constant data to be accessed as
if it were in data space.
4.2.1
SOFTWARE STACK POINTER/
FRAME POINTER
W15 is the dedicated software stack pointer (SP), and
will be automatically modified by exception processing
and subroutine calls and returns. However, W15 can be
referenced by any instruction in the same manner as all
other W registers. This simplifies the reading, writing
and manipulation of the stack pointer (e.g., creating
stack frames).
4.1.2
INSTRUCTION FETCH MECHANISM
A one-stage pre-fetching mechanism accesses each
instruction a cycle ahead to maximize available
execution time. Most instructions execute in a single
cycle. Exceptions are:
1. Flow control instructions (such as Program
Branches, Calls, Returns) take 2 cycles, since
the IR (instruction register) and pre-fetch buffer
must be flushed and refilled.
In order to protect against misaligned stack accesses,
W15<0> is always clear.
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space greater than 0x0800.
2. Instructions where one operand is to be fetched
from program space (using any method). These
operations consume 2 cycles (with the notable
exception of instructions executed within a
REPEAT loop, which execute in 1 cycle).
W14 has been dedicated as a stack frame pointer, as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
3. Double-word move based instructions.
Most instructions access data as required during
instruction execution. Instructions which utilize the
multiplier array must have data available at the
beginning of the instruction cycle. Consequently, this
data must be pre-fetched, usually by the preceding
instruction, resulting in a simple out of order data
processing model.
The stack pointer always points to the first available
free word and grows from lower addresses towards
higher addresses. It pre-decrements for stack pops
(reads) and post-increments for stack pushes (writes).
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 15
dsPIC30F
FIGURE 4-1:
PROGRAMMER’S MODEL
15
0
W0/WREG
W1
PUSH.S Shadow
DO Shadow
DIV and MUL
Result Registers
W2
W3
Legend
W4
MAC Operand
Registers
W5
W6
W7
Working Registers
W8
W9
MAC Address
Registers
W10
W11
W12/MAC Offset
W13/MAC Write Back
W14/Frame Pointer
W15*/Stack Pointer
*W15 and SPLIM not shadowed
SPLIM*
Stack Pointer Limit Register
15
39
31
0
DSP
ACCA
Accumulators
ACCB
22
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEAT Loop Counter
15
DCOUNT
DO Loop Counter
22
0
DOSTART
DO Loop Start Address
DO Loop End Address
22
0
DOEND
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
RA
N
Z
C
IPL2 IPL1 IPL0
OV
Status Register
SRH
SRL
DS70043D-page 16
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
TABLE 5-1:
EFFECT OF INVALID
MEMORY ACCESSES
5.0
DATA ADDRESS SPACE
The core has two data spaces. The data spaces can
be considered either separate (for some DSP
instructions), or as one unified linear address range (for
MCU instructions). The data spaces are accessed
using two Address Generation Units (AGUs) and
separate data paths.
Attempted Operation
Data Returned
EA = an unimplemented address
0x0000
W8 or W9 used to access Y data
0x0000
space in a MACinstruction
W10 or W11 used to access X data
0x0000
space in a MACinstruction
5.1
Data Spaces
The X data space is used by all instructions and sup-
ports all addressing modes. There are separate read
and write data buses. The X read data bus is the return
data path for all instructions that view data space as
combined X and Y address space. It is also the X
address space data path for the dual operand read
instructions (MAC class). The X write data bus is the
only write path to data space for all instructions.
5.2
Data Space Width
The core data width is 16-bits. All internal registers are
organized as 16-bit wide words. Data space memory is
organized in byte addressable, 16-bit wide blocks.
Figure 5-1 depicts a sample data space memory map
for the dsPIC30F.
5.3
Data Alignment
The X data space also supports Modulo Addressing
for all instructions, subject to addressing mode restric-
tions. Bit-Reversed Addressing is only supported for
writes to X data space.
To help maintain backward compatibility with
PICmicro® devices and improve data space memory
usage efficiency, the dsPIC30F instruction set supports
both word and byte operations. Data is aligned in data
memory and registers as words, but all data space EAs
resolve to bytes. Data byte reads will read the complete
word which contains the byte, using the LS bit of any
EA to determine which byte to select. The selected byte
is placed onto the LS byte of the X data path (no byte
accesses are possible from the Y data path as the MAC
class of instruction can only fetch words). That is, data
memory and registers are organized as two parallel
byte wide entities with shared (word) address decode,
but separate write lines. Data byte writes only write to
the corresponding side of the array or register which
matches the byte address.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths. No writes
occur across the Y bus. This class of instructions
dedicates two W register pointers, W10 and W11, to
always address Y data space, independent of X data
space, whereas W8 and W9 always address X data
space. Note that during accumulator write back, the
data address space is considered a combination of X
and Y data spaces, so the write occurs across the X
bus. Consequently, it can be to any address in the
entire data space.
As a consequence of this byte accessibility, all effective
address calculations (including those generated by the
DSP operations, which are restricted to word sized
data) are internally scaled to step through word aligned
memory. For example, the core would recognize that
Post-Modified Register Indirect Addressing mode,
[Ws++], will result in a value of Ws+1 for byte
operations and Ws+2 for word operations.
The Y data space can only be used for the data
pre-fetch operation associated with the MAC class of
instructions. It also supports Modulo Addressing for
automated circular buffers. Of course, all other
instructions can access the Y data address space
through the X data path, as part of the composite linear
space.
The boundary between the X and Y data spaces is
defined as shown in Figure 5-1 and is not user
programmable. Should an EA point to data outside its
own assigned address space, or to a location outside
physical memory, an all zero word/byte will be returned.
For example, although Y address space is visible by all
non-MAC instructions using any addressing mode, an
attempt by a MAC instruction to fetch data from that
space, using W8 or W9 (X space pointers), will return
0x0000.
All word accesses must be aligned to an even address.
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. Should
a misaligned read or write be attempted, an address
error trap will be forced. If the error occurred on a read,
the instruction underway is completed, whereas if it
occurred on a write, the instruction will be inhibited and
the PC will not be incremented. In either case, a trap
will then be executed, allowing the system and/or user
to examine the machine state prior to execution of the
address fault.
All effective addresses are 16-bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes or 32K words.
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 17
dsPIC30F
FIGURE 5-1:
SAMPLE DATA SPACE MEMORY MAP
MS Byte
Address
LS Byte
Address
16-bits
MSB
LSB
0x0000
0x0001
SFR Space
2 Kbyte
SFR Space
0x07FE
0x0800
0x07FF
0x0801
X Data RAM (X)
8 Kbyte
0x17FF
0x1801
0x17FE
0x1800
SRAM Space
0x1FFF
0x1FFE
Y Data RAM (Y)
0x27FF
0x2801
0x27FE
0x2800
8 Kbyte
SRAM boundary
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
DS70043D-page 18
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2003 Microchip Technology Inc.
dsPIC30F
6.2
Data Accumulators and Adder/
Subtractor
6.0
DSP ENGINE
Concurrent operation of the DSP engine with MCU
instruction flow is not possible, though both the MCU
ALU and DSP engine resources may be used
concurrently by the same instruction (e.g., ED and
EDACinstructions).
The data accumulators have a 40-bit adder/subractor
with automatic sign-extension logic. It can select one of
two accumulators (A or B) as its pre-accumulation
source and post-accumulation destination. For the ADD
and LAC instructions, the data to be accumulated or
loaded can be optionally scaled via the barrel shifter
prior to accumulation.
The DSP engine consists of a high speed 17-bit x 17-bit
multiplier, a barrel shifter and a 40-bit adder/subtractor
with two target accumulators, round and saturation
logic. The 17-bit x 17-bit multiplier is also utilized for
MCU based multiply instructions.
6.2.1
ADDER/SUBTRACTOR, OVERFLOW
AND SATURATION
Data input to the DSP engine is derived from one of the
following:
The adder/subtractor is a 40-bit adder with an optional
zero input into one side and either true or complement
data into the other input. In the case of addition, the
Carry/Borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the Carry/Borrow input is active low and
the other input is complemented. The adder/subtractor
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the Status Register:
1. Directly from the W array (registers W4, W5, W6
or W7) via the X and Y data buses for the MAC
class of instructions (MAC,MSC,MPY,MPY.N,
ED,EDAC,CLR and MOVSAC).
2. From the X-bus for all other DSP instructions.
3. From the X-bus for all MCU instructions which
use the barrel shifter.
Data output from the DSP engine is written to one of the
following:
• Overflow from bit 39. This is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
1. The target accumulator, as defined by the DSP
instruction being executed.
• Overflow into guard bits 32 through 39. This is a
recoverable overflow. This bit (OA/OB) is set
whenever all the guard bits are not identical to
each other.
2. The X-bus for MAC, MSC, CLR and MOVSAC
accumulator writes, where the EA is derived
from W13 only (MPY,MPY.N,ED and EDACdo
not offer an accumulator write option).
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B and ACCSAT mode
control bits to determine when to saturate and to what
value to saturate.
3. The X-bus for all MCU instructions which use
the barrel shifter.
The DSP engine also has the capability to perform
inherent accumulator-to-accumulator operations, which
require no additional data. These instructions are ADD,
SUB and NEG.
6.2.2
ROUNDING LOGIC
A block diagram of the DSP engine is shown in
Figure 6-1.
The rounding logic is a combinational block, which
performs conventional (biased) or convergent
a
(unbiased) round function during an accumulator write
(store). The Round mode is determined by the state of
the RND bit in the CORCON register. It generates a
16-bit, 1.15 data value, which is passed to the data
space write saturation logic. If rounding is not indicated
by the instruction, a truncated 1.15 data value is stored
and the LS Word is simply discarded.
6.1
Multiplier
The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31), or 32-bit
integer results. Integer data is inherently represented
as a signed two’s complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
6.2.3
DATA SPACE WRITE SATURATION
N-1
N-1
an N-bit two’s complement integer is -2
to 2
– 1.
In addition to adder/subtractor saturation, writes to data
space may also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round logic. These are
combined and used to select the appropriate 1.15
fractional value as output to write to data space memory.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF), including 0. For a 32-bit integer, the
data range is -2,147,483,648 (0x8000 0000) to
2,147,483,645 (0x7FFF FFFF).
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 19
dsPIC30F
FIGURE 6-1:
DSP ENGINE BLOCK DIAGRAM
S
a
40
t
16
40-bit Accumulator A
40-bit Accumulator B
40
Round
Logic
u
r
a
t
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
e
Enable
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
Operand Latches
16
16
To/From W Array
DS70043D-page 20
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
FIGURE 7-1:
PROGRAM SPACE
MEMORY MAP
7.0
EXCEPTION PROCESSING
The dsPIC30F has four processor exceptions (traps)
and up to 45 sources of interrupts, which must be arbi-
trated based on a priority scheme.
Reset - GOTOInstruction
Reset - Target Address
000000
000002
000004
Reserved
The processor core is responsible for reading the
Interrupt Vector Table (IVT) and transferring the
address contained in the interrupt vector to the
program counter.
Osc. Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Arithmetic Warn. Trap Vector
Reserved Vector
Reserved Vector
Reserved Vector
The Interrupt Vector Table (IVT) and Alternate Interrupt
Vector Table (AIVT) are placed near the beginning of
program memory (0x000004).
Interrupt 0 Vector
000014
Interrupt 1 Vector
The interrupt controller and processor exceptions are
responsible for pre-processing the interrupts prior
to them being presented to the processor core.
The interrupts and traps are enabled, prioritized and
controlled using centralized special function registers:
Interrupt 52 Vector
Interrupt 53 Vector
Reserved
00007E
000080
000084
Alternate Vector Table
0000FE
000100
• IFS0<15:0>, IFS1<15:0>, IFS2<15:0>
All interrupt request flags are maintained in these
three registers. The flags are set by their
respective peripherals or external signals, and
they are cleared via software.
User Flash
Program Memory
(48K instructions)
017FFE
018000
• IEC0<15:0>, IEC1<15:0>, IEC2<15:0>
All interrupt enable control bits are maintained in
these three registers. These control bits are used
to individually enable interrupts from the
peripherals or external signals.
Reserved
(Read 0’s)
7FEFFE
7FF000
Data EEPROM
(4 Kbytes)
7FFFFE
800000
• IPC0<15:0>... IPC11<7:0>
The user assignable priority level associated with
each of the 45 interrupts is held centrally in these
twelve registers.
Reserved
• IPL<2:0> The current CPU priority level is stored
in the 16-bit Status register that resides in the
processor core.
• INTCON1<15:0>, INTCON2<15:0>
Global interrupt control functions are derived from
these two registers. INTCON1 contains the
control and status flags for the processor
exceptions. The INTCON2 register controls the
external interrupt request signal behavior and the
use of the alternate vector table.
8005BE
8005C0
UNITID (32 instr.)
8005FE
800600
Reserved
Note:
Interrupt flag bits get set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit. User
software should ensure the appropriate
interrupt flag bits are clear prior to
enabling an interrupt.
F7FFFE
F80000
Device Configuration
Registers
F8000E
F80010
All interrupt sources can be user assigned to one of 8
priority levels, 1 through 7 via the IPCx registers. Each
interrupt source is associated with an interrupt vector.
Levels 7 and 1 represent the highest and lowest
maskable priorities, respectively. A priority level of 0
disables the interrupt.
Reserved
FEFFFE
FF0000
FFFFFE
DEVID (2)
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Advance Information
DS70043D-page 21
dsPIC30F
Certain interrupts have specialized control bits for
features like edge or level triggered interrupts,
interrupt-on-change, etc. Control of these features
remains within the peripheral module, which generates
the interrupt.
7.1
Interrupt Priority
The user assignable Interrupt Priority Control
(IP<2:0>) bits for each individual interrupt source are
located in the three LS bits of each nibble within the
IPCx register(s). Bit 3 of each nibble is not used and is
read as a ‘0’. These bits define the priority level
assigned to a particular interrupt by the user.
The DISI instruction can be used to disable the
processing of interrupts of priorities 6 and lower for a
certain number of instruction cycles, during which the
DISI bit remains set.
Note:
The user selectable priority levels start at
0 as the lowest priority and level 7 as the
highest priority.
When an interrupt is serviced, the PC is loaded with
the address stored in the vector location in program
memory that corresponds to the interrupt. There are
62 different vectors within the IVT. These vectors are
contained in locations 0x000004 through 0x00007E of
program memory. These locations contain 24-bit
addresses and in order to preserve robustness, an
address error trap will take place should the PC
attempt to fetch any of these words during normal exe-
cution. This prevents execution of random data
through accidentally decrementing a PC into vector
space, accidentally mapping a data space address
into vector space, or the PC rolling over to 0x000000
after reaching the end of implemented program
memory space. Execution of a CALL or GOTO
instruction to this vector space will also generate an
address error trap.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given
level. This method is called “Natural Order Priority”.
The Natural Order Priority of an interrupt is numerically
identical to its Vector Number.The natural order priority
scheme has 0 as the highest priority and 53 as the
lowest priority. The natural order priority number is the
same as the vector number.
The ability for the user to assign every interrupt to one
of eight priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. For example: the PLVD (Low
Voltage Detect) can be given a priority of 7, and the
INT0 (external interrupt 0) may be assigned to priority
level 1, thus giving it a very low effective priority.
DS70043D-page 22
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
The FRC (Fast RC) internal oscillator runs at a nominal
8 MHz. The LPRC (Low Power RC) internal oscIllator
is connected to the Watchdog Timer, and it runs at a
nominal 512 kHz. The External RC (EXTRC) oscillator
uses an external resistor and capacitor connected to
the OSC1 pin. Frequency of operation is up to 4 MHz.
8.0
DEVICE SYSTEM
MANAGEMENT
System management services provided by the
dsPIC30F device family include:
• Control of clock options and oscillators
• Program control of power-up timer
• Oscillator start-up timer/stabilizer
• Watchdog timer with RC oscillator
• Fail-safe clock monitor
The OSC1 pin may also be used as an input from an
external clock source; this mode is called “EC”.
The dsPIC30F oscillator system provides:
• Various external and internal oscillator options as
clock sources
• Reset by multiple sources
• An on-chip PLL to boost internal operating
frequency
8.1
Clock Options and Oscillators
• Clock switching between various clock sources
There are three primary clock oscillators: XTL, XT and
HS. The XTL oscillator is designed for crystals or
ceramic resonators in the range of 200 kHz to 4 MHz.
The XT oscillator is designed for crystals and ceramic
resonators in the range of 4 to 10 MHz. The HS (High-
Speed) oscillator is for crystals in the 10 to 25 MHz
range. These oscillators use the OSC1 and OSC2 pins.
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
• A Clock Control register (OSCCON)
• Non-volatile configuration bits for main oscillator
selection.
The secondary (LP) oscillator is designed for low power
and uses a 32 kHz crystal or ceramic resonator. The LP
oscillator uses the SOSC1 and SOSC2 pins.
A simplified block diagram of the oscillator system is
shown in Figure 8-1.
FIGURE 8-1:
OSCILLATOR SYSTEM BLOCK DIAGRAM
Oscillator Configuration bits
PWRSAV Instruction
Wake-up Request
PLL
OSC1
OSC2
PLL
x4, x8, x16
Primary
Oscillator
Primary Osc
Primary Osc
Stability
Detector
Oscillator
Start-up
Timer
Clock
POR
Switchingand
Programmable
Control
Secondary Osc
Clock
Block
FOSC
Divider
Secondary
Osc Stability
Detector
Secondary
Oscillator
32 kHz
SOSCO
SOSCI
Internal Fast
RC (FRC)
Oscillator
Internal Low
Power RC
(LPRC) Osc
Fail-Safe
Clock Monitor
(FSCM)
Oscillator Trap
To Timer1
2003 Microchip Technology Inc.
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DS70043D-page 23
dsPIC30F
8.2
Programmable Power-up Timer
8.4
Watchdog Timer (WDT)
There are two timers that offer necessary delays on
power-up. One is the Power-up Timer (PWRT), which
provides a delay on power-up only. The PWRT keeps
the part in Reset while the power supply stabilizes. The
other is the Oscillator Start-up Timer (OST), intended to
keep the chip in Reset until the crystal oscillator is sta-
ble. With these two timers on-chip, most applications
need no external Reset circuitry.
The primary function of the Watchdog Timer (WDT) is
to reset the processor in the event of a software
malfunction. The WDT is a free running timer that runs
off an on-chip RC oscillator, requiring no external com-
ponent. The WDT timer continues to operate even if the
main processor clock (e.g., the crystal oscillator) fails.
The Watchdog Timer can be “Enabled” or “Disabled”
only through a configuration bit (WDTEN) in the
Configuration register.
8.3
Oscillator Start-up Timer/Stabilizer
WDTEN = 1 enables the Watchdog Timer. The
enabling is done when programming the device. By
default, after chip erase, the Watchdog Timer is
enabled. Any device programmer capable of program-
ming dsPIC devices (such as Microchip’s PRO MATE®
II and PICSTART® Plus programmers) allows
programming of this and other configuration bits to the
desired state. If enabled, the WDT increments until it
overflows or “times out”. A WDT time-out forces a
device Reset (except during Sleep). To prevent a WDT
time-out, the application program must clear the
Watchdog Timer using a CLRWDTinstruction.
In order to ensure that a crystal oscillator (or ceramic
resonator) has started and stabilized, an Oscillator
Start-up Timer (OST) is included. The OST is a simple
10-bit counter that counts 1024 TOSC cycles before
releasing the oscillator clock to the rest of the system.
The time-out period is designated as TOST. The TOST
time is involved every time the oscillator has to restart,
i.e., on POR, BOR and wake-up from Sleep. The oscil-
lator start-up timer is applied to the LP oscillator, XT,
XTL and HS modes (upon wake-up from Sleep, POR
and BOR) for the primary oscillator.
If a WDT times out during Sleep, the device will
wake up. The STATUS bit is cleared (“0”) to indicate a
wake-up resulting from WDT time-out.
The WDT continues to operate even if the system clock
source (e.g., the crystal oscillator) fails. A block
diagram of the WDT is shown in Figure 8-2.
FIGURE 8-2:
WATCHDOG TIMER BLOCK DIAGRAM
SWDTEN
FWDTEN
Enable WDT
2
FWPSA1
FWPSA0
LPRC
Control
F
= 128 kHz
Programmable Prescaler A
1:1, 1:8, 1:64, 1:512
WC
LPRC
512 kHz
÷
4
Oscillator
Wake-up from
Sleep
Programmable Prescaler B
1:1, 1:2, 1:3,... 1:15, 1:16
8-bit Watchdog Timer
WDT Overflow
Reset
FWPSB3
FWPSB2
FWPSB1
FWPSB0
Reset
WDT
4
CLRWDT Instruction
PWRSAVInstruction
All Device Resets
Sleep or Idle State
DS70043D-page 24
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2003 Microchip Technology Inc.
dsPIC30F
FIGURE 8-3:
RESET SYSTEM BLOCK
DIAGRAM
8.5
Fail-Safe Clock Monitor
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the watchdog timer.
RESETInstruction
Glitch
Filter
MCLR
Sleep or Idle
WDT
Module
In the event of an oscillator failure, the FSCM gener-
ates a Clock Failure Trap event and switches the
system clock over to an alternate clock oscillator
source. The application program then can either
attempt to restart the oscillator, or execute a controlled
shutdown. The Trap can be treated as a warm Reset by
simply loading the Reset address into the oscillator fail
trap vector.
VDD Rise
POR
SYSRST
Detect
BOR
VDD
Brown-out
Reset
BOREN
Trap Conflict
Illegal Opcode
Uninitialized W Register
8.6
Reset System
The Reset system combines all Reset sources and
controls the device Master Reset Signal SYSRST, as
shown in Figure 8-3
Device Reset sources include:
• POR: Power-on Reset
• EXTR: RESETinstruction
• WDTR: Watchdog Timer Reset
• BOR: Brown-out Reset
• TRAPR: Trap Conflict Reset
• IOPR: Illegal Opcode Reset
• UWR: Uninitialized W Register Reset
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 25
dsPIC30F
FIGURE 9-1:
LVD MODULE BLOCK
DIAGRAM
9.0
DEVICE POWER
MANAGEMENT
External LVD input pin
4
Power management services provided by the
dsPIC30F device include:
LVDL<3.0>
VDD
LVDIN
• Real-time Clock Source Switching
• Power Management by Peripheral
• Programmable low-voltage detection
• Programmable brown-out reset
+
LVDIF
-
• Idle and Sleep modes with fast wake-up
9.1
Real Time Clock Source Switching
Configuration bits determine the clock source upon
Power-on Reset (POR) and Brown-out Reset (BOR).
Thereafter, the clock source can be changed between
permissible clock sources. The OSCCON register
controls the clock switching and reflects system clock
related status bits.
LVDEN
Internally Generated
Reference Voltage
9.2
Power Management by Peripheral
Figure 9-1 is a block diagram of the LVD module. A
comparator uses an internally generated reference
voltage as the set point. When the selected tap output
of the device voltage is lower than the reference volt-
age, the LVDF bit (IFS2<10>) is set. Each node of the
resistor divider represents a “trip point” voltage. The
voltage is software programmable to any of 16 values.
Peripheral Module Disable (PMD) registers provide a
method to disable a peripheral module by stopping all
clock sources supplied to that module. When a periph-
eral is disabled via the appropriate PMD control bit, the
peripheral is in a minimum power consumption state.
The control and status registers associated with the
peripheral are also disabled, so writes to those
registers have no effect and read values are invalid.
9.4
Programmable Brown-out Reset
A peripheral module is only enabled if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC30F
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
The BOR (Brown-out Reset) module is based on an
internal voltage reference circuit. The main purpose of
the BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains, i.e.,
missing portions of the AC cycle waveform due to bad
power transmission lines or voltage sags due to exces-
sive current draw when a large inductive load is turned
on.
Note:
If a PMD bit is set, the corresponding
module is disabled after a delay of 1
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of 1 instruction cycle
(assuming the module control registers
are already configured to enable module
operation).
The BOR module allows selection of one of the
following voltage trip points:
• 2.0V
• 2.7V
• 4.2V
• 4.5V
9.3
Low Voltage Detect (LVD)
The LVD module is used with battery operated applica-
tions to detect when the battery voltage (the VDD of the
device) drops below a threshold, which is near the end
of the battery life for the application. The LVD allows the
application to gracefully shut down its operation.
Note:
The BOR voltage trip points indicated here
are nominal values provided for design
guidance only. Refer to the Electrical
Specifications in the specific device data
sheet for BOR voltage limit specifications.
A BOR generates a Reset pulse which resets the
device.
DS70043D-page 26
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
The processor exits (wakes up) from Sleep on one of
these events:
9.5
Watchdog Timer (WDT) and Power
Saving Modes
• Any interrupt source that is individually enabled.
• Any form of device Reset.
The dsPIC30F devices have two reduced power
modes that can be entered through execution of the
PWRSAVinstruction.
• A WDT time-out.
• Sleep Mode: The CPU, system clock source and
any peripherals that operate on the system clock
source are disabled. This is the lowest power
mode of the device.
9.5.2
IDLE MODE
When the device enters Idle mode, these events occur:
• CPU stops executing instructions
• WDT is automatically cleared
• Idle Mode: The CPU is disabled, but the system
clock source continues to operate. Peripherals
continue to operate, but can optionally be
disabled.
• System clock source remains active and
peripheral modules, by default, continue to
operate normally from the system clock source.
Peripherals optionally can be shut down in Idle
mode using their ‘stop-in-idle’ control bit.
The WDT, when enabled, operates from the internal
LPRC clock source and can be used to detect system
software malfunctions by resetting the device if the
WDT has not been cleared in software. Various WDT
time-out periods can be selected using the WDT
postscaler. The WDT can also be used to wake the
device from Sleep or Idle mode.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The processor wakes from Idle mode on these events:
• Any interrupt that is individually enabled.
• Any source of device Reset.
• A WDT time-out.
9.5.1
SLEEP MODE
Sleep mode incorporates these characteristics:
Upon wake up from Idle, the clock is re-applied to the
CPU and instruction execution begins immediately
starting with the instruction following the PWRSAV
instruction, or the first instruction in the ISR.
• System clock source is shut down. If an on-chip
oscillator is used, it is turned off.
• Device current consumption is at minimum,
provided that no I/O pin is sourcing current.
• Fail-Safe Clock Monitor (FSCM) does not operate
during Sleep mode because the system clock
source is disabled.
• LPRC clock continues to run in Sleep mode if the
WDT is enabled.
• Low Voltage Detect circuit, if enabled, remains
operative during Sleep mode.
• BOR circuit, if enabled, remains operative during
Sleep mode
• WDT, if enabled, is automatically cleared prior to
entering Sleep mode.
• Some peripherals may continue to operate in
Sleep mode. These peripherals include I/O pins
that detect a change in the input signal, or
peripherals that use an external clock input. Any
peripheral that is operating on the system clock
source is disabled in Sleep mode.
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 27
dsPIC30F
10.1.1
10-BIT HIGH-SPEED A/D MODULE
10.0 dsPIC30F PERIPHERALS
• 10-bit resolution
The Digital Signal Controller (DSC) family of 16-bit
MCU devices will provide the integrated functionality of
many peripheral functions. The functions that are
utilized (one or more) on the DSC devices are as
follows:
• Uni-polar differential sample/hold amplifiers
• Up to 16 input channels
• Selectable reference inputs
•
1 LSB max DNL
2 LSB max INL
• Analog-to-Digital Converters
- 10-bit High-Speed A/D Converter
- 12-bit High-Resolution A/D Converter
• General Purpose 16-bit timers
• Watchdog Timer module
•
• Four on-chip sample and hold amplifiers
• Automated channel scanning
• Single supply operation: 2.7-5.5V
• 500 ksps sampling rate at 5V
• Motor Control PWM module
• Quadrature Encoder module
• Input Capture module
• 100 ksps sampling rate at 2.7V
• Ability to convert during CPU Sleep and Idle
modes
• Output Compare/PWM module
• Data Converter Interface
• Conversion start can be synchronized with 1 of 3
trigger sources
• Serial Peripheral Interface (SPITM) module
• UART module
10.1.2
12-BIT HIGH RESOLUTION A/D
MODULE
2
• I CTM module
• 12-bit resolution
• Controller Area Network (CAN) module
• I/O pins
• Uni-polar differential sample/hold amplifiers
• Up to 16 input channels
• Selectable reference inputs
10.1 Analog-to-Digital Converters
•
1 LSB max DNL
2 LSB max INL
The Analog-to-Digital (A/D) Converters provide up to
16 analog inputs with both single ended and differential
inputs. These modules offer on-board sample and hold
circuitry.
•
• One on-chip sample and hold amplifier
• Automated channel scanning
• Single supply operation: 2.7-5.5V
• 100 ksps sampling rate at 5V
• 50 ksps sampling rate at 2.7V
To minimize control loop errors due to finite update
times (conversion plus computations), a high speed
low latency ADC is required.
• Ability to convert during CPU Sleep and Idle
modes
In addition, several hardware features have been
added to the peripheral interface to improve real-time
performance in a typical DSP based application.
• Conversion start can be synchronized with 1 of 3
trigger sources
• Result alignment options
• Automated sampling
10.2 General Purpose Timer Module
• Automated channel scanning
• Dual Port data buffer
The General Purpose (GP) Timer module provides the
time-base elements for Input Capture, Output
Compare/PWM and can be configured for a real-time
clock operation, as well as various timer/counter
modes.
• External conversion start control
There are two versions of A/D converters available for
the dsPIC30F family of devices:
• 10-bit high-speed A/D module
The dsPIC30F device will support up to five 16-bit
timers. Four of the 16-bit timers can be configured as
two 32-bit timers. Each timer has several selectable
operating modes.
• 12-bit high-resolution A/D module
• 16-bit timer/counter
• 32-bit timer/counter
• Gated time acumulation mode
• 32.768 kHz watch crystal support for real time
clock
• Individual period registers for each timer
DS70043D-page 28
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
These four modes are selected by the PTMOD<1:0>
bits in the PTCON SFR. The Up/Down Counting modes
support center aligned PWM generation. The Single-
Shot mode allows the PWM module to support pulse
control of certain electronically commutated motors
(ECMs).
10.3 Motor Control PWM Module
This module simplifies the task of generating multiple,
synchronized Pulse Width Modulated (PWM) outputs.
In particular, the following power and motion control
applications are supported by the PWM module:
• Three-Phase AC Induction Motor
• Switched Reluctance (SR) Motor
• Brushless DC (BLDC) Motor
10.4 QEI Module
The Quadrature Encoder Interface (QEI) module
provides the interface to incremental encoders for
obtaining motor positioning data. Incremental encoders
are very useful and specific to motor control
applications.
• Uninterruptible Power Supply (UPS)
The PWM module has these characteristics:
• 8 PWM I/O pins with 4 duty cycle generators
• Up to 16-bit resolution
The Quadrature Encoder Interface (QEI) is a key
feature requirement for several motor control
applications, such as Switched Reluctance (SR) Motor
and AC Induction Motor (ACIM). The operational
features of the QEI are, but not limited to:
• ‘On-the-Fly’ PWM frequency changes
• Edge and Center Aligned Output modes
• Single Pulse Generation mode
• Interrupt support for asymmetrical updates in
Center Aligned mode
• Three input channels for two-phase signals and
index pulse
• Output override control for electrically commutated
motor (ECM) operation
• 16-bit up/down position counter
• Dead-time control for Complementary mode
• Count direction status
• ‘Special Event’ comparator for scheduling other
peripheral events, such as A/D conversions
• Position Measurement (x2 and x4) mode
• Programmable digital noise filters on inputs
• Alternate 16-bit Timer/Counter mode
• Quadrature Encoder Interface interrupts
This module contains
4 duty cycle generators,
numbered 1 through 4. The module has 8 PWM output
pins, numbered 0 through 7. The eight I/O pins are
grouped into odd numbered/even numbered pairs. For
complementary loads, the even PWM pins must always
be the complement of the corresponding odd I/O pins
to prevent damage to the power transistor devices.
Consequently, the signals on the even numbered I/O
pins have certain limitations when the module is in the
Complementary Operating mode.
10.5 Input Capture Module
The Input Capture module is useful in applications
requiring Frequency (Period) and Pulse measurement.
The dsPIC30F device will support up to eight input
capture channels. The key operational features are:
• Capture every falling edge
• Capture every rising edge
10.3.1
PWM TIME-BASE
• Capture every 4th rising edge
• Capture every 16th rising edge
• Capture every rising and falling edge
The PWM time-base is provided by a 15-bit timer with
a prescaler and postscaler. Bit 15 of the PTMR Special
Function Register contains a read only status bit,
PTDIR, that indicates the present count direction of the
PWM time-base. If the PTDIR status bit is cleared,
PTMR is counting upwards. If PTDIR is set, PTMR is
counting downwards. The PWM time-base is
configured via a Special Function Register (SFR).
• Capture timer values based on internal or external
clocks
• Timer2 or Timer3 time-base selection
• Device wake-up from capture pin during CPU
Sleep and Idle modes
The PWM time-base can be configured for four
different modes of operation:
• Interrupt on input capture event
• 4-word FIFO buffer for capture values
• Free Running mode
These operating modes are determined by setting the
appropriate control and configuration bits.
• Single-Shot mode
• Continuous Up/Down Count mode
Input capture is useful for such modes as:
• Continuous Up/Down Count mode with interrupts
for double-updates
• Frequency/Period/Pulse Measurements
• Additional sources of external interrupts
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 29
dsPIC30F
In Master mode operation, SCK is clock output, but in
Slave mode, it is clock input.
10.6 Output Compare/PWM Module
The Output Compare module features are quite useful
in applications requiring operational modes, such as:
A series of eight or sixteen clock pulses (depending on
mode) shift out the 8 or 16 bits from the SPISR to SDO
pin and simultaneously shift in 8 or 16 bits data from
SDI pin. An interrupt is generated when the transfer is
complete (interrupt flag bit SPIIF). This interrupt can
be disabled through the interrupt enable bit SPIIE.
• Generation of Variable Width Output Pulses
• Simple PWM Operation
The dsPIC30F device will support up to eight Output
Compare channels with the following key operational
features:
The receive operation is double buffered. When a
complete byte is received, it is transferred from SPISR
to SPIBUF.
• Timer2 and Timer3 Selection mode
• Simple Output Compare Match mode
• Dual Output Compare Match mode
• Simple Glitchless PWM mode
If the receive buffer is full when the protocol needs to
transfer data from SPISR to SPIBUF, the module will
set the SPIROV bit, indicating an overflow condition.
The module will not complete the transfer of the data
from SPISR to SPIBUF. The module will not respond
to SCL transitions while SPIROV is ‘1’, effectively
disabling the module until software reads SPIBUF.
• Output Compare during CPU Sleep and Idle
mode
• Interrupt on Output Compare/PWM event
• Interrupt on PWM Fault Detect condition
Transmit writes are double buffered. The user writes to
the SPIBUF. Once all the data is received, the
contents of the SPISR are transferred to the SPIRB,
while the contents of SPITXB are transferred to the
SPISR.
10.7 Data Converter Interface Module
The dsPIC30F Data Converter Interface (DCI) module
allows simple interfacing of devices such as audio
coder/decoders (codecs), A/D converters, and D/A
converters. The following interfaces are supported:
In Master mode, data is transmitted as soon as
SPIBUF is written. The interrupt is raised at the middle
of the last bit duration (i.e., after the last bit in is
latched).
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
2
• Inter-IC Sound (I S) Interface
In Slave mode, data is transmitted and received as
external clock pulses appear on SCK. Again, the
interrupt is set as the last bit is latched in. If SS control
bit is enabled, then transmission and reception are
enabled only when SS = low. SDO output will be
disabled in SS mode, with SS = high.
• AC-Link Compliant mode
The DCI module has the following hardware features:
• Programmable word size up to 16-bits
• Support for up to 16 time slots, for a maximum
frame size of 256 bits
• Data buffering for up to 4 samples without CPU
overhead
10.9 UART Module
The dsPIC products will have one or more UART’s.
The key features of the UART module are:
10.8 SPITM Module
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface, useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be Serial EEPROMs, shift
registers, display drivers, A/D converters, etc. It is
compatible with Motorola's SPI and SIOP interfaces.
• Full-duplex operation with 8- or 9-bit data
• Even, Odd or No Parity options (for 8-bit data)
• One or two STOP bits
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates range from up to 2.5 Mbps and down
to 38 Hz at 30 MIPs
This SPI module includes all SPI modes. A Frame
Synchronization mode is also included for support of
voice band codecs.
• 4-character deep transmit data buffer
• 4-character deep receive data buffer
The serial port consists of a 16-bit shift register, SPISR,
used for shifting data in and out and a buffer register,
SPIBUF. A control register, SPICON, configures the
module. Additionally, a status register, SPISTAT,
indicates various status conditions.
• Parity, Framing and Buffer Overrun error detection
• 16x Baud Clock output for IrDA® support
• Support for interrupt only on Address Detect
(9th bit = 1)
• Separate Transmit and Receive interrupts
• Loopback mode for diagnostics
• Alternate TX/RX pins
Four pins make up the serial interface: SDI, serial data
input; SDO, serial data output; SCK, shift clock input or
output; SS, active low slave select, which also serves
as the FSYNC, frame synchronization pulse.
DS70043D-page 30
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2003 Microchip Technology Inc.
dsPIC30F
2
10.10 I CTM Module
• 2 full acceptance filter masks, one each
associated with the high and low priority receive
buffers
2
The I C module is a synchronous serial interface,
useful for communicating with other peripheral or
microcontroller devices. These peripheral devices may
be Serial EEPROMs, shift registers, display drivers,
A/D converters, etc.
• Three transmit buffers with application specified
prioritization and abort capability
• Programmable wake-up functionality with
integrated low-pass filter
2
The Inter-Integrated Circuit (I C) module offers full
• Programmable Loopback mode and
programmable state clocking supports self-test
operation
hardware support for both Slave and Multi-Master
operations.
2
The key features of the I C module are:
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
2
• I C interface supports both Master and Slave
operation.
2
• I C Slave operation supports 7- and 10-bit address.
10.12 I/O Pins
2
• I C Master operation supports 7- and 10-bit
Some pins for the I/O pin functions are multiplexed with
an alternate function for the peripheral features on the
device. In general, when a peripheral is enabled, that
pin may not be used as a general purpose I/O pin.
address.
2
• I C port allows bidirectional transfers between
master and slaves.
2
• Serial clock synchronization for I C port can be
All I/O port pins have three registers directly associated
with the operation of the port pin. The Data Direction
register determines whether the pin is an input or an
output. The Port Data Latch register provides latched
output data for the I/O pins. The Port register provides
visibility of the logic state of the I/O pins. Reading the
Port register provides the I/O pin logic state, while
writes to the Port register write the data to the port Data
Latch register.
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
2
• I C supports Multi-Master operation. Detects bus
collision and will arbitrate accordingly.
• Slew Rate Control for 100 kHz and 400 kHz bus
speeds.
2
In I C mode, pin SCL is clock and pin SDA is data. The
module will override the data direction bits for these
2
pins. The pins that are used for I C modes are
10.12.1 I/O PIN FEATURES
configured as open drain.
• Schmitt Trigger input
• Open drain output
10.11 Controller Area Network (CAN)
Module
• TTL input levels
• CMOS output drivers
• Weak internal pull-up
• Interrupt-on-change feature (inputs only)
The Controller Area Network (CAN) is a serial
communications protocol, which efficiently supports
distributed real-time control.
The dsPIC30F CAN module satisfies the Version 2.0B
specification, which allows message identifier lengths of
11- and/or 29-bits to be used (an identifier length of
29-bits allows over 536 million message identifiers).
Version 2.0B CAN is also referred to as “Extended CAN”.
10.12.2 I/O PORT LATCH
I/O port pins have latch bits (LAT register). The LAT
register, when read, will yield the contents of the I/O
latch, and when written, will modify the contents of the
I/O latch, thus modifying the value driven out on a pin if
the corresponding Data Direction register bit is
configured for output. This can be used in read-modify-
write instructions that allow the user to modify the
contents of the latch register, regardless of the status of
the corresponding pins.
The module will support CAN 1.2, CAN 2.0A, CAN
2.0B Passive, and CAN 2.0B Active versions of the
protocol. The module features are:
• Standard and extended data frames
• 0-8 bytes data length
• Programmable bit rate up to 1 Mb/sec
• Support for remote frames
• Double buffered receiver with two prioritized
received message storage buffers
• 6 full (standard/extended identifier) acceptance
filters, 2 associated with the high priority receive
buffer, and 4 associated with the low priority
receive buffer
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Advance Information
DS70043D-page 31
dsPIC30F
11.2.1
MULTI-CYCLE INSTRUCTIONS
11.0 dsPIC30F INSTRUCTION SET
As the instruction summary tables show, most
instructions execute in a single cycle, with the following
exceptions:
11.1 Introduction
The dsPIC30F instruction set provides a broad suite of
instructions, which supports traditional microcontroller
applications and a class of instructions, which supports
math intensive applications. Since almost all of the
functionality of the PICmicro instruction set has been
maintained, this hybrid instruction set allows a friendly
DSP migration path for users already familiar with the
PICmicro microcontroller.
• Instructions DO, MOV.D, POP.D, PUSH.D,
TBLRDH, TBLRDL, TBLWTHand TBLWTL
require 2 cycles to execute.
• Instructions DIVF, DIV.S, DIV.U are single
cycle instructions, which should be executed 18
consecutive times as the target REPEAT
instruction.
• Instructions that change the program counter also
require 2 cycles to execute, with the extra cycle
executed as a NOP. SKIPinstructions, which skip
over a 2-word instruction, require 3 instruction
cycles to execute, with 2 cycles executed as a
NOP.
11.2 Instruction Set Overview
The dsPIC30F instruction set contains 84 instructions,
which can be grouped into the ten functional categories
shown in Table 11-1. Table 11-2 defines the symbols
used in the instruction summary tables, Table 11-3
through Table 11-12. These tables define the syntax,
description, storage and execution requirements for
each instruction. Storage requirements are repre-
sented in 24-bit instruction words, and execution
requirements are represented in instruction cycles.
Most instructions have several different Addressing
modes and execution flows, which require different
instruction variants. For instance, there are six unique
ADD instructions and each instruction variant has its
own instruction encoding.
• The RETFIE, RETLW and RETURN are a
special case of an instruction that changes the
program counter. These execute in 3 cycles,
unless an exception is pending and then they
execute in 2 cycles.
Note:
Instructions which access program
memory as data, using Program Space
Visibility, will incur some cycle count
overhead. See the dsPIC30F Family
Reference Manual for details.
11.2.2
MULTI-WORD INSTRUCTIONS
TABLE 11-1: dsPIC30F INSTRUCTION
GROUPS
As the instruction summary tables show, almost all
instructions consume one instruction word (24 bits),
with the exception of the CALL, DO and GOTO
instructions, which are flow instructions listed in
Table 11-9. These instructions require two words of
memory, because their opcodes embed large literal
operands.
Functional Group
Move Instructions
Summary Table
Table 11-3
Table 11-4
Table 11-5
Table 11-6
Table 11-7
Table 11-8
Table 11-9
Table 11-10
Table 11-11
Table 11-12
Math Instructions
Logic Instructions
Rotate/Shift Instructions
Bit Instructions
Compare/Skip Instructions
Program Flow Instructions
Shadow/Stack Instructions
Control Instructions
DSP Instructions
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2003 Microchip Technology Inc.
dsPIC30F
TABLE 11-2: SYMBOLS USED IN SUMMARY TABLES
Symbol Description
#
Literal operand designation
Acc
AWB
bit4
Expr
f
Accumulator A or Accumulator B
Accumulator Write Back
4-bit wide bit position (0:15)
Absolute address, label or expression (resolved by the linker)
File register address
lit1
1-bit literal (0:1)
lit4
4-bit literal (0:15)
lit5
5-bit literal (0:31)
lit8
8-bit literal (0:255)
lit10
lit14
lit16
lit23
Slit4
Slit6
Slit10
Slit16
TOS
Wb
10-bit literal (0:255 for Byte mode, 0:1023 for Word mode)
14-bit literal (0:16383)
16-bit literal (0:65535)
23-bit literal (0:8388607)
Signed 4-bit literal (-8:7)
Signed 6-bit literal (-16:16)
Signed 10-bit literal (-512:511)
Signed 16-bit literal (-32768:32767)
Top-of-Stack
Base working register
Wd
Destination working register (direct and indirect addressing)
Working register divide pair (dividend, divisor)
Working register multiplier pair (same source register)
Working register multiplier pair (different source registers)
Both source and destination working register (direct addressing)
Destination working register (direct addressing)
Source working register (direct addressing)
Default working register
Wm, Wn
Wm*Wm
Wm*Wn
Wn
Wnd
Wns
WREG
Ws
Source working register (direct and indirect addressing)
Wx
Source Addressing mode and working register for X data bus pre-fetch
Destination working register for X data bus pre-fetch
Wxd
Wy
Source Addressing mode and working register for Y data bus pre-fetch
Destination working register for Y data bus pre-fetch
Wyd
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Advance Information
DS70043D-page 33
dsPIC30F
TABLE 11-3: MOVE INSTRUCTIONS
Assembly
EXCH
MOV
Syntax
Description
Words
Cycles
Wns,Wnd
f {,WREG}
WREG,f
f,Wnd
Swap Wns and Wnd
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
2
2
2
2
Move f to destination
MOV
Move WREG to f
MOV
Move f to Wnd
MOV
Wns,f
Move Wns to f
MOV.b
MOV
#lit8,Wnd
#lit16,Wnd
[Ws+Slit10],Wnd
Wns,[Wd+Slit10]
Ws,Wd
Move 8-bit literal to Wnd
Move 16-bit literal to Wnd
Move [Ws + signed 10-bit offset] to Wnd
Move Wns to [Wd + signed 10-bit offset]
Move Ws to Wd
MOV
MOV
MOV
MOV.D
MOV.D
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
Note:
Ws,Wnd
Wns,Wd
Wn
Move double Ws to Wnd:Wnd + 1
Move double Wns:Wns + 1 to Wd
Wn = byte or nibble swap Wn
Read high program word to Wd
Read low program word to Wd
Write Ws to high program word
Write Ws to low program word
Ws,Wd
Ws,Wd
Ws,Wd
Ws,Wd
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
Note:
Table 11-3 through Table 11-12 present the base instruction syntax for the dsPIC30F. These instructions do
not include all the available addressing modes. For example, some instructions show the Byte Addressing
mode and others do not. Please refer to the dsPIC30F Programmer’s Reference Manual for details on each
instruction.
DS70043D-page 34
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2003 Microchip Technology Inc.
dsPIC30F
TABLE 11-4: MATH INSTRUCTIONS
Assembly Syntax Description
Words
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
1
ADD
f {,WREG}
Destination = f + WREG
Wn = lit10 + Wn
ADD
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
Wn
1
ADD
Wd = Wb + lit5
1
ADD
Wd = Wb + Ws
1
ADDC
ADDC
ADDC
ADDC
DAW.B
DEC
Destination = f + WREG + (C)
Wn = lit10 + Wn + (C)
Wd = Wb + lit5 + (C)
1
1
1
Wd = Wb + Ws + (C)
1
Wn = decimal adjust Wn
Destination = f – 1
1
f {,WREG}
Ws,Wd
1
DEC
Wd = Ws – 1
1
DEC2
DEC2
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
f {,WREG}
Ws,Wd
Destination = f – 2
1
Wd = Ws – 2
1
Wm,Wn
Signed 16/16-bit integer divide
Signed 32/16-bit integer divide
Unsigned 16/16-bit integer divide
Unsigned 32/16-bit integer divide
Signed 16/16-bit fractional divide
Destination = f + 1
18
18
18
18
18
1
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
INC
f {,WREG}
Ws,Wd
INC
Wd = Ws + 1
1
INC2
f {,WREG}
Ws,Wd
Destination = f + 2
1
INC2
Wd = Ws + 2
1
MUL
f
W3:W2 = f * WREG
1
MUL.SS
MUL.SU
MUL.SU
MUL.US
MUL.UU
MUL.UU
SE
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,#lit5,Wnd
Wb,Ws,Wnd
Ws,Wnd
{Wnd+1,Wnd} = sign(Wb) * sign(Ws)
{Wnd+1,Wnd} = sign(Wb) * unsign(lit5)
{Wnd+1,Wnd} = sign(Wb) * unsign(Ws)
{Wnd+1,Wnd} = unsign(Wb) * sign(Ws)
{Wnd+1,Wnd} = unsign(Wb) * unsign(lit5)
{Wnd+1,Wnd} = unsign(Wb) * unsign(Ws)
Wnd = sign-extended Ws
Destination = f – WREG
Wn = Wn – lit10
1
1
1
1
1
1
1
SUB
f {,WREG}
#lit10, Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
#lit10, Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
Wb,#lit5,Wd
Wb,Ws,Wd
Ws,Wnd
1
SUB
1
SUB
Wd = Wb – lit5
1
SUB
Wd = Wb – Ws
1
SUBB
SUBB
SUBB
SUBB
SUBBR
SUBBR
SUBBR
SUBR
SUBR
SUBR
ZE
Destination = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – lit5 – (C)
1
1
1
Wd = Wb – Ws – (C)
1
Destination = WREG – f – (C)
Wd = lit5 – Wb – (C)
1
1
Wd = Ws – Wb – (C)
1
Destination = WREG – f
Wd = lit5 – Wb
1
1
Wd = Ws – Wb
1
Wnd = zero-extended Ws
1
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 35
dsPIC30F
TABLE 11-5: LOGIC INSTRUCTIONS
Assembly
AND
AND
AND
AND
CLR
Syntax
Description
Words
Cycles
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f
Destination = f .AND. WREG
Wn = lit10 .AND. Wn
Wd = Wb .AND. lit5
Wd = Wb .AND. Ws
f = 0x0000
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CLR
WREG
WREG = 0x0000
Wd = 0x0000
CLR
Wd
COM
COM
IOR
f {,WREG}
Ws,Wd
Destination = f
Wd = Ws
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
f {,WREG}
Ws,Wd
Destination = f .IOR. WREG
Wn = lit10 .IOR. Wn
Wd = Wb .IOR. lit5
Wd = Wb .IOR. Ws
Destination = f + 1
Wd = Ws + 1
IOR
IOR
IOR
NEG
NEG
SETM
SETM
SETM
XOR
XOR
XOR
XOR
Note:
f
f = 0xFFFF
WREG
WREG = 0xFFFF
Wd = 0xFFFF
Wd
f {,WREG}
#lit10,Wn
Wb,#lit5,Wd
Wb,Ws,Wd
Destination = f .XOR. WREG
Wn = lit10 .XOR. Wn
Wd = Wb .XOR. lit5
Wd = Wb .XOR. Ws
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
DS70043D-page 36
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
TABLE 11-6: ROTATE/SHIFT INSTRUCTIONS
Assembly
ASR
ASR
ASR
ASR
LSR
Syntax
Description
Words
Cycles
f {,WREG}
Ws,Wd
Destination = arithmetic right shift f
Wd = arithmetic right shift Ws
Wnd = arithmetic right shift Wb by lit4
Wnd = arithmetic right shift Wb by Wns
Destination = logical right shift f
Wd = logical right shift Ws
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
LSR
LSR
Wb,#lit4,Wnd
Wb,Wns,Wnd
f {,WREG}
Ws,Wd
Wnd = logical right shift Wb by lit4
Wnd = logical right shift Wb by Wns
Destination = rotate left through Carry f
Wd = rotate left through Carry Ws
Destination = rotate left (no Carry) f
Wd = rotate left (no Carry) Ws
Destination = rotate right through Carry f
Wd = rotate right through Carry Ws
Destination = rotate right (no Carry) f
Wd = rotate right (no Carry) Ws
Destination = left shift f
LSR
RLC
RLC
RLNC
RLNC
RRC
RRC
RRNC
RRNC
SL
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
f {,WREG}
Ws,Wd
SL
Wd = left shift Ws
SL
Wb,#lit4,Wnd
Wb,Wns,Wnd
Wnd = left shift Wb by lit4
SL
Wnd = left shift Wb by Wns
Note:
When the optional {,WREG} operand is specified, the destination of the instruction is WREG. When
{,WREG} is not specified, the destination of the instruction is the file register f.
TABLE 11-7: BIT INSTRUCTIONS
Assembly
BCLR
Syntax
f,#bit4
Description
Words
Cycles
Bit clear f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
BCLR
Ws,#bit4
f,#bit4
Bit clear Ws
BSET
Bit set f
BSET
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Bit set Ws
BSW.C
BSW.Z
BTG
Write C bit to Ws<Wb>
Write SZ bit to Ws<Wb>
Bit toggle f
BTG
Ws,#bit4
f,#bit4
Bit toggle Ws
BTST
Bit test f
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
BTSTS.C
BTSTS.Z
FBCL
Ws,#bit4
Ws,#bit4
Ws,Wb
Ws,Wb
f,#bit4
Bit test Ws to C
Bit test Ws to SZ
Bit test Ws<Wb> to C
Bit test Ws<Wb> to SZ
Bit test f then set f
Bit test Ws to C then set Ws
Bit test Ws to SZ then set Ws
Find bit change from left (MSb) side
Find first one from left (MSb) side
Find first one from right (LSb) side
Ws,#bit4
Ws,#bit4
Ws,Wnd
Ws,Wnd
Ws,Wnd
FF1L
FF1R
Note:
Bit positions are specified by bit4 (0:15) for word operations.
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 37
dsPIC30F
TABLE 11-8: COMPARE/SKIP INSTRUCTIONS
Assembly Syntax
Description
Words
Cycles
BTSC
BTSC
BTSS
BTSS
CP
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
f
Bit test f, skip if clear
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 (2 or 3)
Bit test Ws, skip if clear
1 (2 or 3)
Bit test f, skip if set
1 (2 or 3)
Bit test Ws, skip if set
1 (2 or 3)
Compare (f – WREG)
1
CP
Wb,#lit5
Wb,Ws
f
Compare (Wb – lit5)
1
CP
Compare (Wb – Ws)
1
CP0
Compare (f – 0x0000)
1
CP0
Ws
Compare (Ws – 0x0000)
1
1
CPB
f
Compare with Borrow (f – WREG – C)
Compare with Borrow (Wb – lit5 – C)
Compare with Borrow (Wb – Ws – C)
Compare Wb with Wn, Skip if Equal (Wb = Wn)
Signed Compare Wb with Wn, Skip if Greater Than (Wb > Wn)
Signed Compare Wb with Wn, Skip if Less Than (Wb < Wn)
Signed Compare Wb with Wn, Skip if Not Equal (Wb ≠ Wn)
CPB
Wb,#lit5
Wb,Ws
Wb,Wn
Wb,Wn
Wb,Wn
Wb,Wn
1
CPB
1
CPSEQ
CPSGT
CPSLT
CPSNE
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
1 (2 or 3)
Note 1: Bit positions are specified by bit4 (0:15) for word operations.
2: Conditional skip instructions execute in 1 cycle if the skip is not taken, 2 cycles if the skip is taken over a
one-word instruction and 3 cycles if the skip is taken over a two-word instruction.
DS70043D-page 38
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
TABLE 11-9: PROGRAM FLOW INSTRUCTIONS
Assembly
BRA
Syntax
Expr
Description
Words
Cycles
2
Branch unconditionally
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
2
2
2
1
1
1
1
1
1
1
1
BRA
Wn
Computed branch
2
BRA
C,Expr
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Z,Expr
Expr
Branch if Carry (no Borrow)
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
BRA
BRA
BRA
BRA
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
BRA
BRA
BRA
BRA
Branch if unsigned less than
Branch if Negative
BRA
BRA
Branch if not Carry (Borrow)
Branch if not Negative
BRA
BRA
Branch if not Overflow
BRA
Branch if not Zero
BRA
Branch if Accumulator A Overflow
Branch if Accumulator B Overflow
Branch if Overflow
BRA
BRA
BRA
Branch if Accumulator A Saturate
Branch if Accumulator B Saturate
Branch if Zero
BRA
BRA
CALL
CALL
DO
Call subroutine
Wn
Call indirect subroutine
2
#lit14,Expr
Wn,Expr
Expr
Do code through PC + Expr, (lit14 + 1) times
Do code through PC + Expr, (Wn + 1) times
Go to address
2
DO
2
GOTO
GOTO
RCALL
RCALL
REPEAT
REPEAT
RETFIE
RETLW
RETURN
2
Wn
Go to address indirectly
Relative call
2
Expr
2
Wn
Computed call
2
#lit14
Repeat next instruction (lit14 + 1) times
Repeat next instruction (Wn + 1) times
Return from interrupt enable
Return with lit10 in Wn
2
Wn
2
3 (2)
3 (2)
3 (2)
#lit10,Wn
Return from subroutine
Note 1: Conditional branch instructions execute in 1 cycle if the branch is not taken, or 2 cycles if the branch is
taken.
2: RETURNnormally executes in 3 cycles. However, it executes in 2 cycles if an interrupt is pending.
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 39
dsPIC30F
TABLE 11-10: SHADOW/STACK INSTRUCTIONS
Assembly Syntax
Description
Words Cycles
LNK
#lit14
f
Link frame pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
2
1
1
POP
Pop TOS to f
POP
Wd
Wnd
Pop TOS to Wd
POP.D
POP.S
PUSH
PUSH
PUSH.D
PUSH.S
ULNK
Double pop from TOS to Wnd:Wnd + 1
Pop shadow registers
Push f to TOS
f
Ws
Wns
Push Ws to TOS
Push double Wns:Wns + 1 to TOS
Push shadow registers
Unlink frame pointer
TABLE 11-11: CONTROL INSTRUCTIONS
Assembly Syntax
Description
Words Cycles
CLRWDT
Clear Watchdog Timer
Disable interrupts for (lit14 + 1) instruction cycles
No operation
1
1
1
1
1
1
1
1
1
1
1
1
DISI
#lit14
NOP
NOPR
PWRSAV
Reset
No operation
#lit1
Enter Power Saving mode lit1
Software device Reset
TABLE 11-12: DSP INSTRUCTIONS
Assembly
ADD
Syntax
Description
Words Cycles
Acc
Add accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ADD
Ws,#Slit4,Acc
16-bit signed add to Acc
Clear Acc
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wm,Acc,Wx,Wy,Wxd
Wm*Wm,Acc,Wx,Wy,Wxd
Ws,#Slit4,Acc
ED
Euclidean distance (no accumulate)
Euclidean distance
EDAC
LAC
Load Acc
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Acc
Multiply and accumulate
Square and accumulate
Move Wx to Wxd and Wy to Wyd
Multiply Wn by Wm to Acc
Square to Acc
MAC
MOVSAC
MPY
MPY
MPY.N
MSC
-(Multiply Wn by Wm) to Acc
Multiply and subtract from Acc
Negate Acc
NEG
SAC
Acc,#Slit4,Wd
Store Acc
SAC.R
SFTAC
SFTAC
SUB
Acc,#Slit4,Wd
Store rounded Acc
Acc,#Slit6
Arithmetic shift Acc by Slit6
Arithmetic shift Acc by (Wn)
Subtract accumulators
Acc,Wn
Acc
DS70043D-page 40
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
party tools manufacturers for additional dsPIC30F
device support. Table 12-1 lists development tools that
support the dsPIC30F family. The paragraphs that
follow describe each of the tools in more detail.
12.0 MICROCHIP DEVELOPMENT
TOOL SUPPORT
Microchip offers comprehensive development tools
and libraries to support the dsPIC30F architecture. In
addition, the company is partnering with many third
TABLE 12-1: DSPIC30F DEVELOPMENT TOOLS
Development
Description
Tool
List
Part #
From
Price*
®
MPLAB IDE 6.xx Integrated Development Environment
—
Microchip
Free
(see 12.1)
MPLAB ASM30
Assembler (included in MPLAB IDE)
—
Microchip
Microchip
Microchip
Microchip
Free
Free
Free
$895
(see 12.2)
MPLAB SIM30
Software Simulator (Included in MPLAB IDE)
—
—
(see 12.3)
MPLAB VDI
Visual Device Initializer for dsPIC30F
(included in MPLAB IDE)
(see 12.4)
MPLAB C30
ANSI C Compiler, Assembler, Linker and Librarian
SW006012
(see 12.5)
MPLAB ICD 2
In-Circuit Debugger and Device Programmer
DV164005
DV164030
Microchip
Microchip
$159
$209
(see 12.6)
In-Circuit Debugger and Device Programmer
With dsPIC30F “Getting Started” Development Board
In-Circuit Emulator Pod
ICE4000
PMF30XA1
DAF30-2
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
$2560
$595
$295
$295
$295
$295
$695
$349
$189
$189
$159
$159
$159
$159
$895
$189
$189
$189
$189
$189
$189
Processor Module for dsPIC30F
Device Adapter for 80L TQFP Devices
Device Adapter for 64L TQFP Devices
Device Adapter for 44L TQFP Devices
Device Adapter for 18L/28L/40L DIP Devices
Full Featured Device Programmer, Base Unit
ICSP Socket Module
MPLAB ICE 4000
(see 12.7)
DAF30-2
DAF30-3
DAF30-4
DV007003
AC004004
AC30F005
AC30F004
AC30F003
AC30F006
AC30F002
AC30F001
DV007004
AC164301
AC164302
AC164302
AC164305
AC164313
AC164314
Socket Module for 18L DIP/SOIC Devices
Socket Module for 28L DIP/SOIC Devices
Socket Module for 40L DIP Devices
MPLAB
®
PRO MATE II
(see 12.8)
Socket Module for 44L TQFP Devices
Socket Module for 64L TQFP Devices (14 mm x 14 mm)
Socket Module for 80L TQFP Devices (14 mm x 14 mm)
Full Featured Device Programmer, Base Unit
Socket Module for 18/28/40L DIP Devices
Socket Module for 18L SOIC Devices
Socket Module for 28L SOIC Devices
Socket Module for 44L TQFP Devices
Socket Module for 64L TQFP Devices (14 mm x 14 mm)
Socket Module for 80L TQFP Devices (14 mm x 14 mm)
MPLAB PM3
(see 12.9)
* List Prices are subject to change without notice
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 41
dsPIC30F
®
12.1 MPLAB Integrated Development
• Integrated MPLAB SIM30 instruction simulator
• User interface for PRO MATE II and PICSTART
Plus device programmers (sold separately)
Environment V6.XX Software
The MPLAB Integrated Development Environment
(IDE) is available at no cost. The MPLAB IDE lets you
edit, compile and emulate from a single user interface,
as depicted in Figure 12-1. You can design and
develop code for the dsPIC devices in the same design
environment that you have used for PICmicro®
microcontrollers. The MPLAB IDE is a 32-bit Windows®
based application that provides many advanced
features for the critical engineer in a modern, easy to
use interface. MPLAB IDE integrates:
• User interface for MPLAB ICE 4000 In-Circuit
Emulator (sold separately)
• User interface for MPLAB ICD 2 In-Circuit
Debugger (sold separately)
The MPLAB IDE allows:
• Editing of source files in either assembly or ‘C’
• One-touch compiling and downloading to dsPIC
emulator or simulator
• Debugging using:
• Full featured, color coded text editor
• Easy to use project manager with visual display
• Source level debugging
- Source files
- Machine code
- Mixed mode source and machine code
• Enhanced source level debugging for ‘C’
(structures, automatic variables, etc.)
The ability to use the MPLAB IDE with multiple
development and debugging targets provides easy
transition from the cost effective simulator to MPLAB
ICD 2 or to a full featured emulator with minimal
retraining.
• Customizable toolbar and key mapping
• Dynamic status bar displays processor condition
• Context sensitive, interactive on-line help
FIGURE 12-1:
MPLAB IDE DESKTOP
Set break/trace points with
a click of the mouse
Powerful Project Manager handles
multiple projects and all file types
Simply move your mouse over a
variable to view or modify
Color keyed editor makes
source code debug easier
Fullycustomizable watch windows
to view and modify registers and
memory locations
Status bar updates on
singlestep or run
DS70043D-page 42
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
FIGURE 12-2:
MPLAB VDI DISPLAY
12.2 MPLAB ASM30 Assembler/Linker/
Librarian
MPLAB ASM30 is a full-featured Macro Assembler.
User-defined macros, conditional assembly and a
variety of assembler directives make the MPLAB
ASM30 a powerful code generation tool.
The accompanying MPLAB LINK30 Linker and MPLAB
LIB30 Librarian modules allow efficient linking, library
creation and maintenance.
12.3 MPLAB SIM30 Software Simulator
The MPLAB SIM30 software simulator provides code
development for the dsPIC30F family in a PC-hosted
environment by simulating the dsPIC30F device on an
instruction level. On any instruction you can examine or
modify the data areas and apply stimuli to any of the
pins from a file or by pressing a user-defined key
12.5 MPLAB C30 Compiler/Linker/
Librarian
The execution can be performed in Single Step,
Execute Until Break or Trace mode. The MPLAB
SIM30 software simulator fully supports symbolic
debugging using the MPLAB C30 compiler and assem-
bler. The software simulator gives you the flexibility to
develop and debug code outside of the laboratory envi-
ronment, making it an excellent multi-project software
development tool. Complex stimuli can be injected from
files, synchronous clocks or user-defined keys. Output
files log register activity for sophisticated post analysis.
The Microchip Technology MPLAB C30 provides C
language support for the dsPIC30F family. This C
compiler is a fully ANSI compliant product with
standard libraries. It is highly optimizing for the
dsPIC30F family and takes advantage of many
dsPIC30F architecture specific features to help you
generate efficient software code.
MPLAB C30 also provides extensions that allow for
excellent support of the hardware, such as interrupts
and peripherals. It is fully integrated with the MPLAB
IDE for high level, source debugging.
12.4 MPLAB Visual Device Initializer
Software Library
• 16-bit native data types
The MPLAB Visual Device Initializer (VDI) simplifies
the task of configuring the dsPIC30F. MPLAB VDI
software allows you to configure the entire processor
graphically (see Figure 12-2). And when you’re done, a
mouse click generates your code in Assembly or
C programs. MPLAB VDI performs extensive error
checking on assignments and conflicts on pins,
memories and interrupts as well as selection of
operating conditions. Generated code files are
integrated seamlessly with the rest of our application
code through MPLAB Project.
• Efficient use of register based, 3-operand
instructions
• Complex Addressing modes
• Efficient multi-bit shift operations
• Efficient signed/unsigned comparisons
MPLAB C30 comes complete with its own assembler,
linker and librarian. These allow Mixed mode C and
assembly programs and link the resulting object files
into a single executable file. The compiler is sold
separately. The assembler, linker and librarian are
available for free with MPLAB C30.
Detailed resource assignment and configuration
reports simplify project documentation. Key features of
MPLAB VDI include:
• Drag-and-drop feature selection
• One click configuration
• Extensive error checking
• Generates initialization code
• Integrates seamlessly in MPLAB Project
• Printed reports ease project documentation
requirements
• MPLAB Visual Device Initializer is included in
MPLAB IDE
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 43
dsPIC30F
FIGURE 12-3:
RELATIVE CODE SIZE (IN BYTES)
FIGURE 12-4:
MPLAB ICD 2 IN-CIRCUIT
DEBUGGER
12.6 MPLAB ICD 2 In-Circuit Debugger
The MPLAB ICD 2 In-Circuit Debugger is a powerful, low
cost, run-time development tool that uses in-circuit
debugging capability built into the dsPIC30F Flash
devices. This feature, along with Microchip’s In-Circuit
Serial ProgrammingTM protocol, gives you cost effective,
in-circuit debugging from the graphical user interface of
MPLAB. It lets you develop and debug source code by
watching variables, single-stepping and setting break-
points as well as run at full speed to test hardware in
real-time.
• Full speed operation to the range of the device
• Serial or USB PC connector
• USB powered from PC interface
• Low noise power (VPP and VDD) for use with
analog and other noise sensitive applications
• Operation down to 2.0 V
• Can be used as debugger and inexpensive serial
programmer
• Some device resources required (RAM and 2
pins)
DS70043D-page 44
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
®
12.8 PRO MATE II Universal Device
12.7 MPLAB ICE 4000 In-Circuit
Emulator
Programmer
The MPLAB ICE 4000 In-Circuit Emulator gives you a
complete hardware design tool for dsPIC30F devices.
Software control of the emulator by MPLAB IDE lets
you edit, build, download and source debug from a
single environment. The MPLAB ICE 4000 is a full fea-
tured emulator system with enhanced trace, trigger and
data monitoring features. Interchangeable processor
modules allow you to easily reconfigure the system to
emulate different processors. In addition to the
dsPIC30F family of digital signal controllers, the
MPLAB ICE 4000 supports the extended, high-end
PICmicro microcontrollers, the PIC18CXXX and
PIC18FXXX devices. The modular architecture of the
MPLAB ICE in-circuit emulator allows expansion to
support new devices.
The PRO MATE II universal device programmer is a
full-featured, CE-compliant programming tool, capable
of operating in both stand-alone and PC-hosted
modes. The PRO MATE II universal device program-
mer has programmable VDD and VPP supplies, which
allow it to verify programmed memory at VDDMIN and
VDDMAX for maximum reliability. It has an LCD display
for instructions and error messages, keys to enter
commands and interchangeable socket modules for all
package types. In Stand-Alone mode, the PRO MATE
II universal device programmer can read, verify or
program PICmicro and dsPIC30F devices. It can also
set code protection in this mode. PRO MATE II features
include:
• Runs under MPLAB IDE
The MPLAB ICE in-circuit emulator system has been
designed as a real-time emulation system, with
advanced features that are generally found on more
expensive development tools.
• Field upgradable firmware
• Host, Safe and “Stand-Alone” operation
• Automatic downloading of object file
• SQTPSM serialization adds unique serial number
to each device programmed
• Full speed emulation, up to 50 MHz bus speed, or
200 MHz external clock speed
• In-Circuit Serial Programming Kit (sold separately)
• Low voltage emulation down to 1.8 volts
• Interchangeable socket modules supports all
package options (sold separately)
• Configured with 2 Mb program emulation memory,
additional modular memory up to 16 Mb
If you already own a PRO MATE II universal device
programmer, the dsPIC30F family is fully supported
through a new set of socket modules.
• 64K x 216-bit wide Trace Memory
• Unlimited software breakpoints
• Complex break, trace and trigger logic
• Multi-level trigger up to 4 levels
12.9 MPLAB PM3 Device Programmer
• Filter trigger functions to trace specific event
The MPLAB PM3 is a new full-featured, production-
• 16-bit Pass counter for triggering on sequential
events
quality
universal
device
programmer.
Using
interchangeable socket modules, the MPLAB PM3
supports virtually all Microchip programmable devices.
• 16-bit Delay counter
• 48-bit time stamp
MPLAB PM3 helps you cut programming time and
gives you a built-in interface for robust In-Circuit Serial
Programming™ (ICSP™). Please check the Microchip
‘web site (www.microchip.com) for availability.
• Stopwatch feature
• Time between events
• USB and parallel printer port PC connection
FIGURE 12-6:
MPLAB PM3 DEVICE
PROGRAMMER
FIGURE 12-5:
MPLAB ICE 4000
IN-CIRCUIT EMULATOR
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 45
dsPIC30F
Table 13-1 presents a summary of the available and
planned dsPIC30F software tools and libraries.
Microchip also provides our customers with additional
value added services such as skilled/certified technical
applications contacts, reference designs and hardware
and software developers.
13.0 dsPIC30F DEVELOPMENT TOOLS
AND APPLICATION LIBRARIES
Microchip is offering a comprehensive set of tools and
libraries to help with rapid development of dsPIC30F
based application(s). Also, Microchip is partnering with
key third party tool manufacturers to develop quality
hardware and software tools in support of the
dsPIC30F product family.
TABLE 13-1: SOFTWARE DEVELOPMENT TOOLS AND APPLICATION LIBRARIES
List
Development Tool
Description
Part #
From
Price*
dsPIC30F Math
Double Precision and Floating Point Library
(ASM, C Wrapper)
SW300020
Microchip
Free
Free
Library (see 13.1)
dsPIC30F
Peripheral Initialization, Control and Utility Routines (C)
SW300021
Microchip
Peripheral Library
(see 13.2)
dsPIC30F DSP
Essential DSP algorithm suite (Filters, FFT)
SW300022
SW300023
SW300001
Microchip
Microchip
Microchip
CMX
Free
Free
Library (see 13.3)
dsPICworks™
Graphical data analysis and conversion tool for DSP
algorithms
(see 13.4)
Digital Filter
Graphical IIR and FIR filter design package for
dsPIC30F
$249
Design (see 13.5)
CMX-RTX
Fully preemptive Real Time Operating System (RTOS)
for dsPIC30F (from CMX)
CMX-RTX
for dsPIC
$4000
$4000
$3000
$3000
Free
®
for dsPIC
(see13.6)
Fully preemptive Real Time Operating System (RTOS)
for dsPIC30F
SW300031
Microchip
CMX
CMX-Tiny+
for dsPIC
(see 13.6)
Preemptive Real Time Operating System (RTOS)
for dsPIC30F (from CMX)
CMX-Tiny+
for dsPIC
Preemptive Real Time Operating System (RTOS)
for dsPIC30F
SW300032
Microchip
Microchip
CMX
dsPIC Scheduler
Multi-tasking, preemptive scheduler for dsPIC30F
(CMX-Scheduler™)
SW300030
(see 13.6)
Contact
Vendor
TCP/IP Library
CMX-MicroNet for dsPIC30F
CMX-
(see 13.7)
TCP/IP connectivity and protocol support
MicroNet
for dsPIC30F
Soft Modem
Library
V.22bis/V.22 Soft Modem Library
V.32bis/V.32 Soft Modem Library
SW300002
SW300003
Microchip
Microchip
Free
Contact
Microchip
(see 13.8)
Contact
Vendor
V.32 (non-trellis) Soft Modem Library
VOCAL
Technologies
Contact
Speech
Automatic speech recognition system including a PC-
based speech training sub-system and a speech
recognition software library
SW300010
Microchip
Microchip
Recognition
System (see 13.9)
Contact
Vendor
CANbedded
for dsPIC
CAN Driver Library for dsPIC30F
Vector
Informatik
(see13.10)
Contact
Vendor
osCAN for dsPIC
OSEK/VDX v2.2
Vector
(see 13.11)
Informatik
Contact
Vendor
Embedded
Workbench for
dsPIC30F
ISO/ANSI C and Embedded C++ Compiler in a
professional, extensible IDE (Windows 98/ME/NT4/
2000/XP) Special DSP support library
EWdsPIC 1
IAR
C Compiler
C Compiler
ANSI C Compiler for dsPIC30F
C Compiler for dsPIC30F
dsPICC
PCDSP
PCWHD
HI-TECH
CSS
$950
$200
$550
C Compiler
with IDE
C Compiler for dsPIC30F with IDE
CSS
* Prices are subject to change without notice
DS70043D-page 46
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
13.1 Math Library
13.3 DSP Algorithm Library
The DSP library supports multiple filtering, convolution,
vector and matrix functions. Among the supported
functions are:
The Math Library supports several standard
functions, such as, but not limited to:
C
• sin(), cos(), tan()
• asin(), acos(), atan(),
• log(), log(10)
• Cascaded Infinite Impulse Response (IIR) Filters
• Correlation
• Convolution
• sqrt(), power()
• ceil(), floor()
• Finite Impulse Response (FIR) Filters
• Windowing Functions
• FFTs
• fmod(), frexp()
The math function routines (IEEE-754 compliant) are
developed and optimized in dsPIC30F assembly
language and are callable from both assembly and C
language. Floating point and double precision versions
of each function are provided. The Microchip MPLAB
C30 and IAR C compilers are supported.
• LMS Filter
• Vector Addition and Subtraction
• Vector Dot Product
• Vector Power
• Matrix Addition and Subtraction
• Matrix Multiplication
Electronic documentation accompanies the math
library to help you comprehend and adapt the library
functions to your needs.
Some DSP functions use double precision and floating
point arithmetic. All DSP routines are developed and
optimized in dsPIC30F assembly language and are
callable from both assembly and C language. The
Microchip MPLAB C30 and IAR C compilers are
supported.
13.2 Peripheral Driver Library
Microchip offers a peripheral driver library that supports
the setup and control of dsPIC30F hardware
peripherals, such as, but not limited to:
Electronic documentation is included with the DSP
library to help you comprehend and implement the
library functions.
• Analog-to-Digital Converter
• Motor Control PWM
• Quadrature Encoder Interface
• UART
• SPI
• Data Converter Interface
2
• I C
• General Purpose Timers
• Input Capture
• Output Compare/Simple PWM
In addition to the hardware peripherals, the library sup-
ports software generated peripherals, such as standard
LCDs, which support a Hitachi style controller.
All peripheral driver routines are developed and
optimized using the MPLAB C30 C Compiler.
Electronic documentation accompanies the peripheral
library to help you comprehend and implement the
library functions.
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 47
dsPIC30F
13.4 dsPICworks™ Visual Algorithm
Analyzer
13.5 Digital Filter Design Software
Utility
The dsPICworks Visual Algorithm Analyzer tool (see
Figure 13-1) makes it easy for you to evaluate and
analyze DSP algorithms. You can run a variety of DSP
operations and analyze your data in the time or
frequency domain.
Microchip offers a digital filter design software tool that
lets you develop optimized assembly code for Low-
pass, High-pass, Band-pass and Band-stop IIR and
FIR filters, including16-bit fractional data size filter
coefficients, from a graphical user interface. You enter
the required filter frequency specifications and the soft-
ware tool develops the filter code and coefficients. Ideal
filter frequency response and time domain plots are
generated for analysis (see Figure 13-2).
Key features include:
• Visually analyze time and frequency domain data
• DSP operations: FFT, convolution, correlation
• Waveform synthesis
FIR filter lengths up to 513 taps, and IIR filter lengths up
to10 cascaded sections, are supported.
• Real-time data acquisition capabilities
• Import data directly from MPLAB IDE
All IIR and FIR routines are generated in assembly
language and are callable from both assembly and C
language. The Microchip MPLAB C30 C compiler is
supported.
FIGURE 13-1:
dsPICworks VISUAL
ALGORITHM ANALYZER
Key features include:
• Low pass, high pass, band pass and band stop
filter support
• FIR filters with up to 513 taps
• IIR filter with up to 10 taps for low pass and high
pass filters
• IIR filter with up to 20 taps for band pass and band
stop filters
• Generates ASM code and filter coefficient files for
export to MPLAB IDE or C Compiler
FIGURE 13-2:
DIGITAL FILTER DESIGN
TOOL INTERFACE
DS70043D-page 48
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
Various configurations, such as a minimal UDP/IP stack
13.6 Real-Time Operating Systems
are available for limited connectivity requirements
.
Real-Time Operating System (RTOS) solutions for the
dsPIC30F product family provide the necessary func-
tion calls and operating system routines to enable you
to write efficient C and/or assembly code for multi-
tasking applications. RTOS is especially suited for
applications where program, and more importantly data
memory resources, are limited. Configurable and
optimized kernels support various RTOS application
requirements.
Most stack protocol functions are developed and
optimized in Microchip’s MPLAB C30 C language.
Assembly language coding is developed for specific
dsPIC30F hardware peripherals and Ethernet drivers
to optimize code size and execution time. These
assembly language specific routines are assembly and
C callable.
Electronic documentation accompanies the TCP/IP
protocol stack to help comprehend and implement the
protocol stack in your application.
The dsPIC30F RTOS solutions are three-tiered:
• CMX-RTX™ full-featured fully-preemptive
multitasking RTOS
The initial product is the CMX-MicroNet™ tool,
featuring:
• CMX-Tiny+™ fully-preemptive scaled-down
version of CMX-RTX
• RFC compliant protocol stack
• Seam support of CMX RTOS
• Ethernet NIC driver
• dsPIC Scheduler (CMX-Scheduler™)
fully-preemptive multitasking mini RTOS (FREE)
Depending on the RTOS implementation, some of the
function calls provided in the system kernel are:
13.8
Soft Modem Application Library
• control tasks
Microchip offers V.22/V.22bis (1200/2400 bps) and
V.32/V.32bis (9600/14400 bps) ITU-T specifications to
support a range of “connected” applications.
• send and receive messages
• handle events
Applications that will benefit from these modem
specifications include:
• control resources
• control semaphores
• Internet enabled home security systems
• Internet connected power, gas and water meters
• Internet connected vending machines
• Smart Appliances
• regulate timing in a variety of ways
• provide memory management
• handle interrupts and swap tasks
Most functions are written in ANSI C, with the exception
of time critical functions, which are optimized in
assembly to reduce execution time and provide
maximum code efficiency. The ANSI C and assembly
routines are supported by the Microchip MPLAB C30 C
compiler.
• Industrial Monitoring
• POS Terminals
• Set Top Boxes
• Drop Boxes
• Fire Panels
Electronic documentation accompanies RTOS
solutions to help you comprehend and adapt RTOS to
your application.
The ITU-T specification modules are written in C and
Assembly language, yielding optimal performance.
Some specific dsPIC30F hardware peripherals and key
transmitter and receiver filtering routines use assembly
language to optimize code size and execution time.
13.7 TCP/IP Library
Microchip offers a Transmission Control Protocol/
Internet Protocol (TCP/IP) Stack solution for Internet
connectivity applications implemented on the
dsPIC30F product family. Configurable stack
implementations are provided, which allow you to
select the optimum TCP/IP stack solution for your
application.
Electronic documentation accompanies the modem
library to help you comprehend and implement the
library functions.
Protocols supported include:
• FTP, TFTP and SMTP application protocol layers
• ICMP, IP, TCP and UDP transport and internet
layers
• PPP, SLIP, ARP and DHCP network access
layers
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 49
dsPIC30F
13.9 Speech Recognition Software
Utility
13.11 OSEK Operating Systems
The dsPIC30F product family supports Operating
Systems for the OSEK/VDX vehicle software standard.
The functionality of OSEK “Offene Systeme und deren
Schnittstellen für die Elektronik im Kraftfahrzeug” (open
systems and the corresponding interfaces for automo-
tive electronics) is harmonized with VDX “Vehicle
Distributed eXecutive” yielding OSEK/VDX.
Automatic Speech Recognition (ASR) for the
dsPIC30F family will support a wide range of voice-
activated applications. A speech training subsystem
and a speech recognition software library will make up
the ASR software suite. Key features of the ASR
application software could include:
Structured and modular RTOS software implementa-
tions are provided based on standardized interfaces
and protocols. Structured and modular implementa-
tions provide for portability and extendability for
distributed control units for vehicles.
• Speaker independent/dependent recognition
• PC-based custom training tool
• Up to 100 word vocabulary
• Supports multiple noise profiles
• Suitable for many voice control applications
Microchip also provides Internal and External CAN
driver support. The physical layer is integrated into the
communication controller’s hardware and is not
covered by the OSEK specifications.
13.10 CAN Driver Library
Microchip offers a CAN driver library that supports the
dsPIC30F CAN peripheral. Some of the CAN functions
which are supported include:
Vector Informatik GmbH has created
a dsPIC
®
architecture version of their osCAN operating system,
along with various support utilities.
• Initialize CAN Module
• Set CAN Operational Mode
• Set CAN Baud Rate
• Set CAN Mask
13.12 Third Party C Compilers
In addition to the Microchip MPLAB® C30 C compiler,
the dsPIC30F is supported by ANSI C compilers
developed by IAR, Hi-Tech and Custom Computer
Services (CCS).
• Set CAN Filter
• Send CAN Message
• Receive CAN Message
• Abort CAN Sequence
• Provide error notification
The compilers allow dsPIC application code to be
written in high level C language, and then be fully
converted into machine object code for programming of
the microcontroller. Each compiler tool provides
several options for compiling to let you select those that
will maximize the efficiency of the generated code
characteristics.
All CAN driver routines are developed and optimized in
dsPIC30F C language and are callable from C
language. Support for the Microchip MPLAB C30 C
Compiler is provided.
Electronic documentation accompanies the CAN
library to help you comprehend and implement the
library functions.
Multiple C compiler solutions come with different price
targets and features, enabling you to select the
compiler best suited for your application requirements.
Vector Informatik GmbH, a dsPIC30F development
partner, has created a dsPIC architecture version of
Most module functions are developed in ANSI C with
the exception of time critical functions and peripheral
utilization, which are optimized in assembly, thereby
reducing execution time for maximum code efficiency.
The Microchip MPLAB C30 C compiler is supported.
®
their CANbedded tool, along with various support
utilities.
DS70043D-page 50
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
board features key dsPIC30F peripherals and supports
Microchip’s MPLAB In-Circuit Debugger (ICD 2) tool for
cost effective debugging and programming of the
dsPIC30F device. The three initial boards to be
provided are shown in Table 14-1.
14.0 dsPIC30F HARDWARE
DEVELOPMENT BOARDS
Microchip currently provides three hardware develop-
ment boards. These boards are tools to help quickly
prototype and validate key design requirements. Each
TABLE 14-1: HARDWARE DEVELOPMENT BOARDS
Development Tool
Description
Part #
From
List
Price*
General Purpose
Development
(see 14.1)
dsPICDEM™ 1.1 Development Board for 80L TQFP
devices
DM300014
Microchip
$299
Motor Control
and
dsPICDEM MC1 Motor Control Development Board
dsPICDEM MC1H 3-Phase High Voltage Power Module
3-Phase ACIM High Voltage Motor (208/460V)
dsPICDEM MC1L 3-Phase Low Voltage Power Module
3-Phase BLDC Low Voltage Motor (24V)
DM300020
DM300021
AC300021
DM300022
AC300020
DM300004-1
Microchip
Microchip
Microchip
Microchip
Microchip
Microchip
$300
$800
$120
$700
$120
$389
Power Conversion
Development
(see 14.2)
Connectivity
Development
(see 14.3)
dsPICDEM.net™ 1 with FCC/JATE and Ethernet NIC
support (Global compliant)
dsPICDEM.net 2 with PSTN and Ethernet NIC support
(Global compliant)
DM300004-2
DM300016
Microchip
Microchip
$389
$79
“Getting Started”
Development
Board
dsPICDEM Starter Demonstration Board with 64-pin
dsPIC30F6012 General Purpose MCU Sample.
Plug-in Sample
Daughter PC board with 80-pin dsPIC30F6014 general
purpose MCU sample. Easy to plug in/remove from
development board.
MA300011
MA300013
Microchip
Microchip
$25
$25
(see 14.4)
Daughter PC board with 80-pin dsPIC30F6010 motor
control MCU sample. Easy to plug in/remove from
development board.
* Prices are subject to change without notice
The general purpose development board is shipped
with 9V power supply, RS-232 I/O cable,
14.1 dsPICDEM 1.1 Development Board
a
The dsPICDEM 1.1 general purpose development
board provides you with a low cost development tool
with which to familiarize yourself with the dsPIC30F
16-bit architecture, high performance peripherals and
powerful instruction set. This development board is an
ideal prototyping tool to help you quickly develop and
validate key design requirements.
pre-programmed dsPIC30F device, example software
and appropriate documentation to enable you
to exercise the development board demonstration
programs.
FIGURE 14-1:
dsPICDEM 1.1
DEVELOPMENT BOARD
Some key features and attributes of the dsPICDEM 1.1
development board include:
• Supports dsPIC30F6014 device
• CAN communication channel
• RS-232 and RS-485 communication channels
• Voiceband codec interface with line in/out jacks
• In-Circuit Debugger interface (MPLAB ICD 2)
• ICE 4000 Emulator interface
• Microchip temperature sensor
• Microchip Digital Potentiometer
• 122x32 Dot Addressable LCD
• General purpose prototyping area
• Various LEDS, switches and potentiometers
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 51
dsPIC30F
The high voltage power module is optimized for
3-phase motor applications that require DC bus volt-
ages up to 400 volts and can deliver up to 1 kW power
output. The high voltage module has an active power
factor correction circuit that is controlled by the
dsPIC30F device. This power module is intended for
AC induction motor and power inverter applications.
FIGURE 14-2:
dsPIC30F MOTOR
CONTROLDEVELOPMENT
SYSTEM
Both power modules have automatic fault protection
and the high voltage module is electrically isolated from
the control interface. Both power module boards
provide pre-conditioned voltage and current signals to
the main control board. All position feedback devices
that are isolated from the motor control circuitry, such
as incremental encoders, hall-effect sensors or
tachometer sensors, can be directly connected to the
main control board. Both modules are equipped with
motor braking circuits.
Some key features and attributes of the motor control
main development board are:
• dsPIC30F Motor Control Main Board supporting
the dsPIC30F6010
• RS-232 and RS-485 interface channels
• 2x16 LCD
• In-Circuit Debugger interface (MPLAB ICD 2)
• ICE 4000 Emulator interface
• General purpose prototyping area
• Custom interface header system
• Various LEDS, switches and potentiometers
The motor control development system is shipped with
a 9V power supply for the control board, RS-232 I/O
cable, pre-programmed dsPIC30F device, example
software and documentation that allows you to
exercise the development board demo programs. A list
of motors that are compatible with the development
system is also provided to facilitate rapid evaluation.
14.2 Motor Control Development Board
The dsPIC30F motor control development board
provides you with three main components for quick
prototyping and validation of BLDC, PMAC and ACIM
applications. The three main components are:
• dsPIC30F Motor Control Main Board
• 3-phase low voltage power module
• 3-phase high voltage power module
The main control board supports the dsPIC30F6010
device, various peripheral interfaces and a custom
interface header system, which allows different motor
power modules to be connected to the PCB. The
control board also has connectors for mechanical
position sensors, such as incremental rotary encoders
and hall effect sensors, and a breadboard area for
custom circuits. The main control board receives its
power from a standard plug-in transformer.
The low voltage power module is optimized for 3-phase
motor applications that require a DC bus voltage less
than 50 volts and can deliver up to 400W power output.
The 3-phase low voltage power module is intended to
power BLDC and PMAC motors.
DS70043D-page 52
Advance Information
2003 Microchip Technology Inc.
dsPIC30F
FIGURE 14-3:
dsPICDEM.net™
CONNECTIVITY
DEVELOPMENT BOARD
14.3 dsPICDEM.net Development
Board
The dsPICDEM.net connectivity development board
provides you with a basic platform for developing and
evaluating various connectivity solutions, implementing
TCP/IP protocol layers, combined with V.32/V.32bis
and V.22/V.22bis ITU-T specifications over PSTN or
Ethernet communication channels.
Some key features and attributes of the dsPICDEM.net
development board are:
• Supports dsPIC30F6014 device
• 10-Base T Ethernet support
• PSTN interface with DAA/AFE
• RS-232 and RS-485 communication channels
• In-Circuit Debugger interface (MPLAB ICD 2)
• ICE 4000 Emulator interface
14.4 Plug-in Samples
• Microchip temperature sensor
The various dsPIC30F Development boards (presently
four types) allow for the use of plug in samples for the
dsPIC30F silicon devices. Since the boards support the
ICE 4000 Emulator Device Adapter through the use of
header pins on the PCB, they also are used to provide
flexibility for the replacement of the dsPIC30F silicon.
There are presently two different plug-in sample types
that support the 80-pin TQFP package types for
General Purpose (dsPIC30F6014) and Motor Control
(dsPIC30F6010) samples and the 64-pin TQFP
General Purpose (dsPIC30F6012) samples. The use
of plug in samples is considered to be an interim
development board mechanization.
• Microchip Dual Channel Digital Potentiometer
• 2x16 LCD
• General purpose prototyping area
• Various LEDs, switches and potentiometers
• External 64K x 16 SRAM
• External EE memory for storing HTML pages
• Expansion header for user applications
The connectivity development board is shipped with a
9V power supply, RS-232 I/O cable, pre-programmed
dsPIC30F devices with example connectivity software
and appropriate documentation to enable you to
exercise the development board connectivity demo
program.
2003 Microchip Technology Inc.
Advance Information
DS70043D-page 53
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Tri-Atria Office Building
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Denmark
32255 Northwestern Highway, Suite 190
Farmington Hills, MI 48334
Tel: 248-538-2250 Fax: 248-538-2260
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200 Fax: 852-2401-3431
China - Shanghai
Microchip Technology Nordic ApS
Regus Business Centre
Lautrup hoj 1-3
Microchip Technology Consulting (Shanghai)
Co., Ltd.
Kokomo
2767 S. Albright Road
Kokomo, IN 46902
Room 701, Bldg. B
Ballerup DK-2750 Denmark
Tel: 45-4420-9895 Fax: 45-4420-9910
Far East International Plaza
No. 317 Xian Xia Road
Tel: 765-864-8360 Fax: 765-864-8387
Los Angeles
France
Shanghai, 200051
18201 Von Karman, Suite 1090
Irvine, CA 92612
Microchip Technology SARL
Parc d’Activite du Moulin de Massy
43 Rue du Saule Trapu
Tel: 86-21-6275-5700 Fax: 86-21-6275-5060
China - Shenzhen
Tel: 949-263-1888 Fax: 949-263-1338
Microchip Technology Consulting (Shanghai)
Co., Ltd., Shenzhen Liaison Office
Batiment A - ler Etage
Phoenix
91300 Massy, France
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7966 Fax: 480-792-4338
Rm. 1812, 18/F, Building A, United Plaza
No. 5022 Binhe Road, Futian District
Shenzhen 518033, China
Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79
Germany
Microchip Technology GmbH
Steinheilstrasse 10
Tel: 86-755-82901380 Fax: 86-755-8295-1393
San Jose
China - Qingdao
Microchip Technology Inc.
2107 North First Street, Suite 590
San Jose, CA 95131
D-85737 Ismaning, Germany
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Rm. B505A, Fullhope Plaza,
No. 12 Hong Kong Central Rd.
Qingdao 266071, China
Tel: 408-436-7950 Fax: 408-436-7955
Italy
Tel: 86-532-5027355 Fax: 86-532-5027205
Toronto
Microchip Technology SRL
Via Quasimodo, 12
20025 Legnano (MI)
Milan, Italy
India
6285 Northam Drive, Suite 108
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699 Fax: 905-673-6509
Microchip Technology Inc.
India Liaison Office
Marketing Support Division
Divyasree Chambers
1 Floor, Wing A (A3/A4)
No. 11, O’Shaugnessey Road
Bangalore, 560 025, India
Tel: 91-80-2290061 Fax: 91-80-2290062
Japan
Tel: 39-0331-742611 Fax: 39-0331-466781
Netherlands
ASIA/PACIFIC
Australia
Microchip Technology Netherlands
P. A. De Biesbosch 14
Microchip Technology Australia Pty Ltd
Marketing Support Division
Suite 22, 41 Rawson Street
Epping 2121, NSW
NL-5152 SC Drunen, Netherlands
Tel: 31-416-690399 Fax: 31-416-690340
United Kingdom
Australia
Microchip Technology Japan K.K.
Benex S-1 6F
Microchip Ltd.
Tel: 61-2-9868-6733 Fax: 61-2-9868-6755
505 Eskdale Road
3-18-20, Shinyokohama
Winnersh Triangle
Kohoku-Ku, Yokohama-shi
Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166 Fax: 81-45-471-6122
Wokingham
Berkshire, England RG41 5TU
Tel: 44-118-921-5869 Fax: 44-118-921-5820
07/10/03
DS70043D-page 54
Advance Information
2003 Microchip Technology Inc.
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