DSPIC33EP64GS808T-E/SO [MICROCHIP]
16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators;
| 型号： | DSPIC33EP64GS808T-E/SO |
| 厂家： | 
MICROCHIP |
| 描述： | 16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators |
| 文件： | 总484页 (文件大小：5042K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
dsPIC33EPXXXGS70X/80X FAMILY
16-Bit Digital Signal Controllers for Digital Power Applications with
Interconnected High-Speed PWM, ADC, PGA and Comparators
Operating Conditions
Advanced Analog Features
• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS
• High-Speed ADC module:
- 12-bit with four dedicated SAR ADC cores
and one shared SAR ADC core
Flash Architecture
- Configurable resolution (up to 12-bit) for each
ADC core
• Dual Partition Flash Program Memory with
LiveUpdate:
- Up to 3.25 Msps conversion rate per channel
at 12-bit resolution
- Supports programming while operating
- Supports partition soft swap
- 11 to 22 single-ended inputs
- Dedicated result buffer for each analog channel
- Flexible and independent ADC trigger sources
- Two digital comparators
Core: 16-Bit dsPIC33E CPU
• Code-Efficient (C and Assembly) Architecture
• Two 40-Bit Wide Accumulators
- Two oversampling filters for increased
resolution
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL plus
Hardware Divide
•
Four Rail-to-Rail Comparators with Hysteresis:
- Dedicated 12-bit Digital-to-Analog Converter
(DAC) for each analog comparator
• 32-Bit Multiply Support
• Four Additional Working Register Sets (reduces
context switching)
- Up to two DAC reference outputs
- Up to two external reference inputs
• Two Programmable Gain Amplifiers:
- Single-ended or independent ground reference
- Five selectable gains (4x, 8x, 16x, 32x and 64x)
- 40 MHz gain bandwidth
Clock Management
• ±0.9% Internal Oscillator
• Programmable PLLs and Oscillator Clock Sources
• Fail-Safe Clock Monitor (FSCM)
• Independent Watchdog Timer (WDT)
• Fast Wake-up and Start-up
Interconnected SMPS Peripherals
• Reduces CPU Interaction to Improve Performance
• Flexible PWM Trigger Options for
ADC Conversions
Power Management
• Low-Power Management modes (Sleep,
Idle, Doze)
• High-Speed Comparator Truncates PWM
(15 ns typical):
• Integrated Power-on Reset and Brown-out Reset
• 0.5 mA/MHz Dynamic Current (typical)
• 20 μA IPD Current (typical)
- Supports Cycle-by-Cycle Current-mode control
- Current Reset mode (variable frequency)
Timers/Output Compare/Input Capture
High-Speed PWM
• Five 16-Bit and up to Two 32-Bit Timers/Counters
• Eight PWM Generators (two outputs per generator)
• Individual Time Base and Duty Cycle for each PWM
• Four Output Compare (OC) modules, Configurable
as Timers/Counters
• 1.04 ns PWM Resolution (frequency, duty cycle,
dead time and phase)
• Four Input Capture (IC) modules
• Supports Center-Aligned, Redundant, Complementary
and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC
and Lighting
2016-2018 Microchip Technology Inc.
DS70005258C-page 1
dsPIC33EPXXXGS70X/80X FAMILY
Communication Interfaces
Qualification and Class B Support
• Two UART modules (15 Mbps):
- Supports LIN/J2602 protocols and IrDA®
• AEC-Q100 REVG (Grade 1, -40°C to +125°C)
• Class B Safety Library, IEC 60730
• Three Variable Width SPI modules with Operating
modes:
• The 6x6x0.55 mm UQFN Package is Designed
and Optimized to ease IPC9592B 2nd Level
Temperature Cycle Qualification
- 3-wire SPI
- 8x16 or 8x8 FIFO mode
- I2S mode
Debugger Development Support
• Two I2C modules (up to 1 Mbaud) with SMBus
Support
• In-Circuit and In-Application Programming
• Five Program and Three Complex
Data Breakpoints
• Up to Two CAN modules
• Four-Channel DMA
• IEEE 1149.2 Compatible (JTAG) Boundary Scan
• Trace and Run-Time Watch
Input/Output
• Constant-Current Source (10 µA nominal)
Digital Peripherals
• Sink/Source up to 12 mA/15 mA, respectively;
Pin-Specific for Standard VOH/VOL
• Four Configurable Logic Cells
• Peripheral Trigger Generator
• 5V Tolerant Pins
• Selectable, Open-Drain Pull-ups and Pull-Downs
• External Interrupts on all I/O Pins
• Peripheral Pin Select (PPS) to allow Function
Remap with Six Virtual I/Os
12-Bit
ADC
Remappable Peripherals
Device
dsPIC33EP128GS702 28 128K 8K 20
5
4
4
2
3
8x2
4
0
1
2
4
1
11
5
2
0
4
1
1
SOIC,
QFN-S,
UQFN
dsPIC33EP64GS804 44 64K 8K 33
dsPIC33EP128GS704 44 128K 8K 33
dsPIC33EP128GS804 44 128K 8K 33
dsPIC33EP64GS805 48 64K 8K 33
dsPIC33EP128GS705 48 128K 8K 33
dsPIC33EP128GS805 48 128K 8K 33
dsPIC33EP64GS806 64 64K 8K 51
dsPIC33EP128GS706 64 128K 8K 51
dsPIC33EP128GS806 64 128K 8K 51
dsPIC33EP64GS708 80 64K 8K 67
dsPIC33EP64GS808 80 64K 8K 67
dsPIC33EP128GS708 80 128K 8K 67
dsPIC33EP128GS808 80 128K 8K 67
5
5
5
5
5
5
5
5
5
5
5
5
5
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
4
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
8x2
8x2
8x2
8x2
8x2
8x2
8x2
8x2
8x2
8x2
8x2
8x2
8x2
4
4
4
4
4
4
4
4
4
4
4
4
4
2
0
2
2
0
2
2
0
2
0
2
0
2
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
17
17
17
17
17
17
22
22
22
22
22
22
22
5
5
5
5
5
5
5
5
5
5
5
5
5
2
2
2
2
2
2
2
2
2
2
2
2
2
4
0
4
4
0
4
4
0
4
0
4
0
4
4
4
4
4
4
4
4
4
4
4
4
4
4
1
1
1
1
1
1
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
QFN,
TQFP
TQFP
TQFP
TQFP
Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable.
2: PWM4 through PWM8 are remappable on 28/44/48-pin devices; on 64-pin devices, only PWM7/PWM8 are remappable.
3: External interrupts, INT0 and INT4, are not remappable.
DS70005258C-page 2
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Pin Diagrams
28-Pin SOIC
MCLR
RA0
RA1
RA2
RB0
RB9
AVDD
VSS
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
AVDD
AVSS
RA3
2
3
4
RA4
5
RB14
RB13
RB12
RB11
VCAP
VSS
6
7
8
RB1
RB2
RB3
RB4
VDD
9
10
11
12
13
14
RB7
RB6
RB5
RB8
RB15
Pin
Pin Function
Pin
Pin Function
1
2
MCLR
AN0/CMP1A/PGA1P1/RP16/RA0
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PGEC3/SCL2/RP47/RB15
TDO/AN19/PGA2N2/RP37/RB5
PGED1/TDI/AN20/SCL1/RP38/RB6
PGEC1/AN21/SDA1/RP39/RB7
VSS
3
AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1
AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
AVDD
4
5
6
VCAP
7
TMS/PWM3H/RP43/RB11
TCK/PWM3L/RP44/RB12
PWM2H/RP45/RB13
PWM2L/RP46/RB14
PWM1H/RP20/RA4
PWM1L/RP19/RA3
AVSS
8
VSS
9
OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
PGED2/DACOUT1/AN18/INT0/RP35/RB3
PGEC2/ADTRG31/EXTREF1/RP36/RB4
VDD
10
11
12
13
14
PGED3/SDA2/FLT31/RP40/RB8
AVDD
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.
2016-2018 Microchip Technology Inc.
DS70005258C-page 3
dsPIC33EPXXXGS70X/80X FAMILY
Pin Diagrams (Continued)
28-Pin QFN-S, UQFN
28 27 26 25 24 23 22
1
2
3
4
5
6
7
21
20
19
18
17
16
15
RA2
RB0
RB9
AVDD
VSS
RB14
RB13
RB12
RB11
VCAP
VSS
dsPIC33EP128GS702
RB1
RB2
RB7
8
9
10 11 12 13 14
Pin
Pin Function
Pin
Pin Function
1
2
AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
AVDD
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PGEC1/AN21/SDA1/RP39/RB7
VSS
3
VCAP
4
TMS/PWM3H/RP46/RB11
TCK/PWM3L/RP44/RB12
PWM2H/RP45/RB13
PWM2L/RP46/RB14
PWM1H/RP20/RA4
PWM1L/RP19/RA3
AVSS
5
VSS
6
OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
PGED2/DACOUT1/AN18/INT0/RP35/RB3
PGEC2/ADTRG31/EXTREF1/RP36/RB4
VDD
7
8
9
10
11
12
13
14
PGED3/SDA2/FLT31/RP40/RB8
PGEC3/SCL2/RP47/RB15
AVDD
MCLR
TDO/AN19/PGA2N2/RP37/RB5
PGED1/TDI/AN20/SCL1/RP38/RB6
AN0/CMP1A/PGA1P1/RP16/RA0
AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.
DS70005258C-page 4
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Pin Diagrams (Continued)
44-Pin QFN, TQFP
1
33
32 RB1
RB7
RC4
RB2
2
3
31
30
29
28
27
26
25
24
23
RC5
RC1
VSS
4
RC6
5
RC3
VDD
6
VSS
RC10
RC9
AVDD
RB9
RB0
RA2
dsPIC33EPXXXGSX04
7
VCAP
RB11
RB12
RB13
RB14
8
9
10
11
Pin
Pin Function
Pin
Pin Function
1
2
PGEC1/AN21/SDA1/RP39/RB7
AN1ALT/RP52/RC4
AN0ALT/RP53/RC5
AN17/RP54/RC6
RP51/RC3
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
AVDD
3
4
5
AN11/PGA1N3/RP57/RC9
EXTREF2/AN10/PGA1P4/RP58/RC10
VDD
6
VSS
7
VCAP
8
TMS/PWM3H/RP43/RB11
TCK/PWM3L/RP44/RB12
PWM2H/RP45/RB13
PWM2L/RP46/RB14
PWM1H/RP20/RA4
PWM1L/RP19/RA3
FLT12/RP48/RC0
FLT11/RP61/RC13
AVSS
VSS
9
AN8/CMP4C/PGA2P4/RP49/RC1
OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
PGED2/DACOUT1/AN18/INT0/RP35/RB3
PGEC2/ADTRG31/RP36/RB4
EXTREF1/AN9/CMP4D/RP50/RC2
ASDA1/RP55/RC7
10
11
12
13
14
15
16
17
18
19
20
21
22
ASCL1/RP56/RC8
AVDD
VSS
MCLR
VDD
AVDD
PGED3/SDA2/FLT31/RP40/RB8
PGEC3/SCL2/RP47/RB15
TDO/AN19/PGA2N2/RP37/RB5
PGED1/TDI/AN20/SCL1/RP38/RB6
AN14/PGA2N3/RP60/RC12
AN0/CMP1A/PGA1P1/RP16/RA0
AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.
2016-2018 Microchip Technology Inc.
DS70005258C-page 5
dsPIC33EPXXXGS70X/80X FAMILY
Pin Diagrams (Continued)
48-Pin TQFP
RB7
RC4
RC5
RC6
RC3
1
2
3
36
35
34
33
32
31
30
29
28
27
26
25
RB2
RB1
RC1
N/C
4
5
6
7
Vss
VSS
VDD
RC10
RC9
AVDD
RB9
RB0
RA2
dsPIC33EPXXXGSX05
VCAP
RD4
8
9
10
11
12
RB11
RB12
RB13
RB14
Pin
Pin Function
Pin
Pin Function
1
2
PGEC1/AN21/SDA1/RP39/RB7
AN1ALT/RP52/RC4
AN0ALT/RP53/RC5
AN17/RP54/RC6
RP51/RC3
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
AVDD
3
4
5
AN11/PGA1N3/RP57/RC9
EXTREF2/AN10/PGA1P4/RP58/RC10
VDD
6
VSS
7
VCAP
8
RP68/RD4
VSS
9
TMS/PWM3H/RP43/RB11
TCK/PWM3L/RP44/RB12
PWM2H/RP45/RB13
PWM2L/RP46/RB14
PWM1H/RP20/RA4
PWM1L/RP19/RA3
FLT12/RP48/RC0
FLT11/RP61/RC13
CLC4OUT/FLT10/RP74/RD10
AVSS
N/C
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
AN8/CMP4C/PGA2P4/RP49/RC1
OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
PGED2/DACOUT1/AN18/INT0/RP35/RB3
PGEC2/ADTRG31/RP36/RB4
EXTREF1/AN9/CMP4D/RP50/RC2
ASDA1/RP55/RC7
ASCL1/RP56/RC8
VSS
AVDD
VDD
MCLR
CLC3OUT/RD14
AVDD
PGED3/SDA2/FLT31/RP40/RB8
PGEC3/SCL2/RP47/RB15
TDO/AN19/PGA2N2/RP37/RB5
PGED1/TDI/AN20/SCL1/RP38/RB6
AN14/PGA2N3/RP60/RC12
AN0/CMP1A/PGA1P1/RP16/RA0
AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.
DS70005258C-page 6
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Pin Diagrams (Continued)
64-Pin TQFP
1
2
RD3
RA4
RA3
48 RB6
47
RD0
RB5
3
46
4
RC0
45 RD11
44
43 RB8
5
RC13
RD10
MCLR
RD12
VSS
RB15
6
7
8
9
42
41
40
39
38
37
36
RD8
VSS
RD9
RD14
VDD
dsPIC33EPXXXGSX06
10
11
12
13
14
15
16
VDD
AVDD
RC12
RA0
RA1
RA2
RC8
RC7
35 RC2
34 RC14
33 RB4
RB0
Pin
Pin Function
Pin
Pin Function
1
2
PWM4L/RP67/RD3
33 PGEC2/ADTRG31/RP36/RB4
34 RP62/RC14
PWM1H/RP20/RA4
PWM1L/RP19/RA3
FLT12/RP48/RC0
FLT11/RP61/RC13
3
35 EXTREF1/AN9/CMP4D/RP50/RC2
36 ASDA1/RP55/RC7
4
5
37 ASCL1/RP56/RC8
6
CLC4OUT/FLT10/RP74/RD10
38
VDD
7
MCLR
39 CLC3OUT/RD14
8
T5CK/FLT9/RP76/RD12
40 SCK3/RP73/RD9
9
VSS
41
VSS
10
11
VDD
AVDD
42 AN5/CMP2D/CMP3B/ISRC3/RP72RD8
43 PGED3/SDA2/FLT31/RP40/RB8
44 PGEC3/SCL2/RP47/RB15
45 INT4/RP75/RD11
12 AN14/PGA2N3/RP60/RC12
13 AN0/CMP1A/PGA1P1/RP16/RA0
14 AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1
15 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
16 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
17 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
18 AVDD
46 TDO/AN19/PGA2N2/RP37/RB5
47 T4CK/RP64/RD0
48 PGED1/TDI/AN20/SCL1/RP38/RB6
49 PGEC1/AN21/SDA1/RP39/RB7
50 AN1ALT/RP52/RC4
19 AVDD
51 AN0ALT/RP53/RC5
20 AVSS
52 AN17/RP54/RC6
21 AN15/RP71/RD7
53 AN12/ISRC1/RP69/RD5
54 PWM5H/RP70/RD6
22 DACOUT2/AN13/RD13
23 AN11/PGA1N3/RP57/RC9
24 EXTREF2/AN10/PGA1P4/RP58/RC10
55 PWM5L/RP51/RC3
56
57
VCAP
VDD
25
26
VSS
VDD
58 PWM6H/RP68/RD4
59 PWM6L/RD15
27 AN8/CMP4C/PGA2P4/RP49/RC1
28 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
29 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
30 AN16/RP66/RD2
60 TMS/PWM3H/RP43/RB11
61 TCK/PWM3L/RP44/RB12
62 PWM2H/RP45/RB13
63 PWM2L/RP46/RB14
64 PWM4H/RP65/RD1
31 ASDA2/RP63/RC15
32 PGED2/DACOUT1/AN18/ASCL2/INT0/RP35/RB3
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.
2016-2018 Microchip Technology Inc.
DS70005258C-page 7
dsPIC33EPXXXGS70X/80X FAMILY
Pin Diagrams (Continued)
80-Pin TQFP
RD3
RA4
1
2
3
4
5
6
7
8
9
60 RB6
59 RD0
58 RB5
RA3
RD11
RE0
57
RE1
56 RB15
55 RB8
RC0
RD8
54
53
52
51
RC13
RD10
MCLR
RE11
RE10
V
SS
RD12 10
dsPIC33EPXXXGSX08
50 RD9
11
DD 12
V
SS
49 RD14
V
48
VDD
RE2 13
RE3 14
AVDD 15
RC12 16
RA0 17
RA1 18
RA2 19
RB0 20
47 RC8
46 RC7
45 RC2
44 RE9
43 RE8
42 RC14
41 RB4
Pin
Pin Function
Pin
Pin Function
1
2
3
4
5
6
7
8
9
PWM4L/RP67/RD3
PWM1H/RP20/RA4
PWM1L/RP19/RA3
PWM8L/RE0
41 PGEC2/ADTRG31/RP36/RB4
42 RP62/RC14
43 RE8
44 RE9
PWM8H/RE1
45 EXTREF1/AN9/CMP4D/RP50/RC2
46 ASDA1/RP55/RC7
47 ASCL1/RP56/RC8
FLT12/RP48/RC0
FLT11/RP61/RC13
CLC4OUT/FLT10/RP74/RD10
48
VDD
MCLR
49 CLC3OUT/RD14
10 T5CK/FLT9/RP76/RD12
50 SCK3/RP73/RD9
11
12
VSS
VDD
51
VSS
52 FLT21/RE10
13 FLT17/RE2
53 FLT22/RE11
14 FLT18/RE3
54 AN5/CMP2D/CMP3B/ISRC3/RP72/RD8
55 PGED3/SDA2/FLT31/RP40/RB8
56 PGEC3/SCL2/RP47/RB15
57 INT4/RP75/RD11
15 AVDD
16 AN14/PGA2N3/RP60/RC12
17 AN0/CMP1A/PGA1P1/RP16/RA0
18 AN1/CMP1B/PGA1P2/PGA2P1/RP17/RA1
19 AN2/CMP1C/CMP2A/PGA1P3/PGA2P2/RP18/RA2
20 AN3/CMP1D/CMP2B/PGA2P3/RP32/RB0
21 AN4/CMP2C/CMP3A/ISRC4/RP41/RB9
22 RE4
58 TD0/AN19/PGA2N2/RP37/RB5
59 T4CK/RP64/RD0
60 PGED1/TDI/AN20/SCL1/RP38/RB6
61 PGEC1/AN21/SDA1/RP39/RB7
62 AN1ALT/RP52/RC4
63 RE12
23 RE5
24 AVDD
64 RE13
25 AVDD
65 AN0ALT/RP53/RC5
66 AN17/RP54/RC6
26 AVSS
27 AN15/RP71/RD7
67 AN12/ISRC1/RP69/RD5
68 PWM5H/RP70/RD6
69 PWM5L/RP51/RC3
28 DACOUT2/AN13/RD13
29 AN11/PGA1N3/RP57/RC9
30 EXTREF2/AN10/PGA1P4/RP58/RC10
70
71
VCAP
VDD
31
32
VSS
VDD
72 PWM6H/RP68/RD4
73 PWM6L/RD15
33 AN8/CMP4C/PGA2P4/RP49/RC1
34 OSCI/CLKI/AN6/CMP3C/CMP4A/ISRC2/RP33/RB1
35 OSC2/CLKO/AN7/CMP3D/CMP4B/PGA1N2/RP34/RB2(1)
36 AN16/RP66/RD2
74 PWM7L/RE14
75 PWM7H/RE15
76 TMS/PWM3H/RP43/RB11
77 TCK/PWM3L/RP44/RB12
78 PWM2H/RP45/RB13
79 PWM2L/RP46/RB14
80 PWM4H/RP65/RD1
37 FLT19/RE6
38 FLT20/RE7
39 ASDA2/RP63/RC15
40 PGED2/DACOUT1/AN18/ASCL2/INT0/RP35/RB3
Legend: Shaded pins are up to 5 VDC tolerant.
RPn represents remappable peripheral functions. See Table 11-12 and Table 11-13 for the complete list of remappable sources.
Note 1: At device power-up (POR), a pulse with an amplitude around 2V and a duration greater than 500 µs, may be observed on this
device pin independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being
driven can endure this active duration.
DS70005258C-page 8
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 13
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 17
3.0 CPU............................................................................................................................................................................................ 23
4.0 Memory Organization................................................................................................................................................................. 33
5.0 Flash Program Memory.............................................................................................................................................................. 63
6.0 Resets ....................................................................................................................................................................................... 71
7.0 Interrupt Controller ..................................................................................................................................................................... 75
8.0 Direct Memory Access (DMA).................................................................................................................................................... 91
9.0 Oscillator Configuration............................................................................................................................................................ 105
10.0 Power-Saving Features............................................................................................................................................................ 117
11.0 I/O Ports ................................................................................................................................................................................... 127
12.0 Timer1 ...................................................................................................................................................................................... 171
13.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 175
14.0 Input Capture............................................................................................................................................................................ 179
15.0 Output Compare....................................................................................................................................................................... 183
16.0 High-Speed PWM..................................................................................................................................................................... 189
17.0 Peripheral Trigger Generator (PTG) Module............................................................................................................................ 217
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 233
2
19.0 Inter-Integrated Circuit (I C)..................................................................................................................................................... 249
20.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 257
21.0 Configurable Logic Cell (CLC).................................................................................................................................................. 263
22.0 High-Speed, 12-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 277
23.0 Controller Area Network (CAN) Module (dsPIC33EPXXXGS80X Devices Only) .................................................................... 311
24.0 High-Speed Analog Comparator .............................................................................................................................................. 337
25.0 Programmable Gain Amplifier (PGA) ....................................................................................................................................... 345
26.0 Constant-Current Source ......................................................................................................................................................... 349
27.0 Special Features ...................................................................................................................................................................... 351
28.0 Instruction Set Summary.......................................................................................................................................................... 365
29.0 Development Support............................................................................................................................................................... 375
30.0 Electrical Characteristics.......................................................................................................................................................... 379
31.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 439
32.0 Packaging Information.............................................................................................................................................................. 443
Appendix A: Revision History............................................................................................................................................................. 469
Index ................................................................................................................................................................................................. 471
The Microchip Website ...................................................................................................................................................................... 479
Customer Change Notification Service .............................................................................................................................................. 479
Customer Support.............................................................................................................................................................................. 479
Product Identification System ............................................................................................................................................................ 481
2016-2018 Microchip Technology Inc.
DS70005258C-page 9
dsPIC33EPXXXGS70X/80X FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Most Current Data Sheet
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Website at:
http://www.microchip.com
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
•
•
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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
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DS70005258C-page 10
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Referenced Sources
This device data sheet is based on the following
individual chapters of the “dsPIC33/PIC24 Family
Reference Manual”. These documents should be
considered as the general reference for the operation
of a particular module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the dsPIC33EPXXXGS70X/80X prod-
uct page of the Microchip website
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features and
other documentation, the resulting page
provides links to the related family
reference manual sections.
• “dsPIC33E Enhanced CPU” (DS70005158)
• “dsPIC33E/PIC24E Program Memory” (DS70000613)
• “Data Memory” (DS70595)
• “Dual Partition Flash Program Memory” (DS70005156)
• “Flash Programming” (DS70609)
• “Reset” (DS70602)
• “Interrupts” (DS70000600)
• “Direct Memory Access (DMA)” (DS70348)
• “Oscillator Module” (DS70005131)
• “Watchdog Timer and Power-Saving Modes” (DS70615)
• “I/O Ports” (DS70000598)
• “Timers” (DS70362)
• “Input Capture with Dedicated Timer” (DS70000352)
• “Output Compare with Dedicated Timer” (DS70005159)
• “High-Speed PWM Module” (DS70000323)
• “Peripheral Trigger Generator (PTG)” (DS70000669)
• “Serial Peripheral Interface (SPI) with Audio Codec Support” (DS70005136)
• “Inter-Integrated Circuit (I2C)” (DS70000195)
• “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582)
• “Configurable Logic Cell (CLC)” (DS70005298)
• “12-Bit High-Speed, Multiple SARs A/D Converter (ADC)” (DS70005213)
• “Enhanced Controller Area Network (ECAN™)” (DS70353)
• “High-Speed Analog Comparator Module” (DS70005128)
• “Programmable Gain Amplifier (PGA)” (DS70005146)
• “Device Configuration” (DS70000618)
• “Watchdog Timer and Power-Saving Modes” (DS70615)
• “CodeGuard™ Intermediate Security” (DS70005182)
• “Programming and Diagnostics” (DS70608)
2016-2018 Microchip Technology Inc.
DS70005258C-page 11
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 12
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
This document contains device-specific information for
the dsPIC33EPXXXGS70X/80X Digital Signal Controller
(DSC) devices.
1.0
DEVICE OVERVIEW
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive resource. To comple-
ment the information in this data sheet,
refer to the related section of the
“dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
dsPIC33EPXXXGS70X/80X devices contain extensive
Digital Signal Processor (DSP) functionality with a
high-performance, 16-bit MCU architecture.
Figure 1-1 shows a general block diagram of the core
and peripheral modules. Table 1-1 lists the functions of
the various pins shown in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific
register and bit information.
FIGURE 1-1:
dsPIC33EPXXXGS70X/80X FAMILY BLOCK DIAGRAM
CPU
Refer to Figure 3-1 for CPU diagram details.
PORTA
16
PORTB
PORTC
PORTD
PORTE
Power-up
Timer
16
Oscillator
Timing
Start-up
Generation
Timer
OSC1/CLKI
POR/BOR
MCLR
Watchdog
Timer
VDD, VSS
AVDD, AVSS
Peripheral Modules
Input
Captures
1-4
Output
CAN
PGA1,
PGA2
I2C1,
I2C2
ADC
Modules
1-2
PTG
Compares
1-4
Remappable
Pins
Analog
Comparators
1-4
Ports
Constant
Current
Source
Timers
1-5
PWMs
8x2
UART1,
UART2
CLC
1-4
SPI1-3
2016-2018 Microchip Technology Inc.
DS70005258C-page 13
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 1-1:
Pin Name(1)
PINOUT I/O DESCRIPTIONS
Pin Buffer
PPS
Description
Type Type
AN0-AN21
AN0ALT-AN1ALT
I
I
Analog No Analog input channels.
Analog No Alternate analog input channels.
C1RXR
C2RXR
C1TX
I
I
O
O
ST
ST
ST
ST
Yes CAN1 receive.
Yes CAN2 receive.
Yes CAN1 transmit.
Yes CAN2 transmit.
C2TX
CLKI
I
ST/
CMOS
—
No External clock source input. Always associated with OSC1 pin
function.
No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
CLKO
O
OSC1
OSC2
I
ST/
CMOS
—
No Oscillator crystal input. ST buffer when configured in RC mode; CMOS
otherwise.
No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
I/O
CLC1OUT
CLC2OUT
CLC3OUT
CLC4OUT
O
O
O
O
DIG
DIG
DIG
DIG
Yes CLC1 output.
Yes CLC2 output.
No(4) CLC3 output.
No(4) CLC4 output.
REFCLKO
IC1-IC4
O
I
—
Yes Reference clock output.
ST
Yes Capture Inputs 1 through 4.
OCFA
OC1-OC4
I
O
ST
—
Yes Compare Fault A input (for compare channels).
Yes Compare Outputs 1 through 4.
INT0
INT1
INT2
INT4
I
I
I
I
ST
ST
ST
ST
No External Interrupt 0.
Yes External Interrupt 1.
Yes External Interrupt 2.
Yes External Interrupt 4.
RA0-RA4
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
No PORTA is a bidirectional I/O port.
No PORTB is a bidirectional I/O port.
No PORTC is a bidirectional I/O port.
No PORTD is a bidirectional I/O port.
No PORTE is a bidirectional I/O port.
RB0-RB15
RC0-RC15
RD0-RD15
RE0-RE15
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
Yes Timer1 external clock input.
Yes Timer2 external clock input.
Yes Timer3 external clock input.
No Timer4 external clock input.
No Timer5 external clock input.
U1CTS
U1RTS
U1RX
U1TX
BCLK1
I
O
I
O
O
ST
—
ST
—
Yes UART1 Clear-to-Send.
Yes UART1 Ready-to-Send.
Yes UART1 receive.
Yes UART1 transmit.
ST
Yes UART1 IrDA® baud clock output.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
P = Power
I = Input
1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.
2: PWM4H/L through PWM8H/L are fixed on dsPIC33EPXXXGS708/808 devices. PWM4H/L through
PWM6H/L are fixed on dsPIC33EPXXXGS706/806 devices.
3: The SCK3 pin is fixed on dsPIC33EPXXXGS706/806 and dsPIC33EPXXXGS708/808 devices.
4: PPS is available on dsPIC33EPXXXGS702 devices only.
DS70005258C-page 14
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 1-1:
Pin Name(1)
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
PPS
Description
Type Type
U2CTS
U2RTS
U2RX
U2TX
BCLK2
I
O
I
O
O
ST
—
ST
—
Yes UART2 Clear-to-Send.
Yes UART2 Ready-to-Send.
Yes UART2 receive.
Yes UART2 transmit.
Yes UART2 IrDA baud clock output.
ST
SCK1
SDI1
SDO1
SS1
I/O
I
O
ST
ST
—
Yes Synchronous serial clock input/output for SPI1.
Yes SPI1 data in.
Yes SPI1 data out.
I/O
ST
Yes SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
SS2
I/O
I
O
ST
ST
—
Yes Synchronous serial clock input/output for SPI2.
Yes SPI2 data in.
Yes SPI2 data out.
I/O
ST
Yes SPI2 slave synchronization or frame pulse I/O.
SCK3
SDI3
SDO3
SS3
I/O
I
O
ST
ST
—
Yes(3) Synchronous serial clock input/output for SPI3.
Yes SPI3 data in.
Yes SPI3 data out.
Yes SPI3 slave synchronization or frame pulse I/O.
I/O
ST
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No Synchronous serial clock input/output for I2C1.
No Synchronous serial data input/output for I2C1.
No Alternate synchronous serial clock input/output for I2C1.
No Alternate synchronous serial data input/output for I2C1.
SCL2
SDA2
ASCL2
ASDA2
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No Synchronous serial clock input/output for I2C2.
No Synchronous serial data input/output for I2C2.
No Alternate synchronous serial clock input/output for I2C2.
No Alternate synchronous serial data input/output for I2C2.
TMS
TCK
TDI
I
I
I
ST
ST
ST
—
No JTAG Test mode select pin.
No JTAG test clock input pin.
No JTAG test data input pin.
No JTAG test data output pin.
TDO
O
FLT1-FLT8
FLT9-FLT12
FLT17-FLT22
FLT31
PWM1L-PWM3L
PWM1H-PWM3H
PWM4L-PWM8L(2)
PWM4H-PWM8H(2)
SYNCI1, SYNCI2
SYNCO1, SYNCO2
I
I
I
ST
ST
ST
ST
—
—
—
—
ST
—
Yes PWM Fault Inputs 1 through 8.
No PWM Fault Inputs 9 through 12.
No PWM Fault Inputs 17 through 22.
No PWM Fault Input 31 (Class B Fault).
No PWM Low Outputs 1 through 3.
No PWM High Outputs 1 through 3.
Yes PWM Low Outputs 4 through 8.
Yes PWM High Outputs 4 through 8.
Yes PWM Synchronization Inputs 1 and 2.
Yes PWM Synchronization Outputs 1 and 2.
I
O
O
O
O
I
O
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
P = Power
I = Input
1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.
2: PWM4H/L through PWM8H/L are fixed on dsPIC33EPXXXGS708/808 devices. PWM4H/L through
PWM6H/L are fixed on dsPIC33EPXXXGS706/806 devices.
3: The SCK3 pin is fixed on dsPIC33EPXXXGS706/806 and dsPIC33EPXXXGS708/808 devices.
4: PPS is available on dsPIC33EPXXXGS702 devices only.
2016-2018 Microchip Technology Inc.
DS70005258C-page 15
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 1-1:
Pin Name(1)
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Buffer
PPS
Description
Type Type
CMP1A-CMP4A
CMP1B-CMP4B
CMP1C-CMP4C
CMP1D-CMP4D
I
I
I
I
Analog No Comparator Channels 1A through 4A inputs.
Analog No Comparator Channels 1B through 4B inputs.
Analog No Comparator Channels 1C through 4C inputs.
Analog No Comparator Channels 1D through 4D inputs.
ACMP1-ACMP4
O
O
—
—
Yes Analog Comparator Outputs 1-4.
No DAC Output Voltages 1 and 2.
DACOUT1,
DACOUT2
EXTREF1, EXTREF2
PGA1P1-PGA1P4
PGA1N1-PGA1N3
PGA2P1-PGA2P4
PGA2N1-PGA2N3
ADTRG31
I
I
I
I
I
I
Analog No External Voltage Reference Inputs 1 and 2 for the Reference DACs.
Analog No PGA1 Positive Inputs 1 through 4.
Analog No PGA1 Negative Inputs 1 through 3.
Analog No PGA2 Positive Inputs 1 through 4.
Analog No PGA2 Negative Inputs 1 through 3.
ST
No External ADC trigger source.
PGED1
PGEC1
PGED2
PGEC2
PGED3
PGEC3
I/O
ST
ST
ST
ST
ST
ST
No Data I/O pin for Programming/Debugging Communication Channel 1.
No Clock input pin for Programming/Debugging Communication Channel 1.
No Data I/O pin for Programming/Debugging Communication Channel 2.
No Clock input pin for Programming/Debugging Communication Channel 2.
No Data I/O pin for Programming/Debugging Communication Channel 3.
No Clock input pin for Programming/Debugging Communication Channel 3.
I
I/O
I
I/O
I
MCLR
AVDD
AVSS
I/P
ST
No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
P
P
No Positive supply for analog modules. This pin must be connected at all
times.
P
P
No Ground reference for analog modules. This pin must be connected at
all times.
VDD
VCAP
VSS
P
P
P
—
—
—
No Positive supply for peripheral logic and I/O pins.
No CPU logic filter capacitor connection.
No Ground reference for logic and I/O pins.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
PPS = Peripheral Pin Select
Analog = Analog input
O = Output
P = Power
I = Input
1: Not all pins are available in all package variants. See the “Pin Diagrams” section for pin availability.
2: PWM4H/L through PWM8H/L are fixed on dsPIC33EPXXXGS708/808 devices. PWM4H/L through
PWM6H/L are fixed on dsPIC33EPXXXGS706/806 devices.
3: The SCK3 pin is fixed on dsPIC33EPXXXGS706/806 and dsPIC33EPXXXGS708/808 devices.
4: PPS is available on dsPIC33EPXXXGS702 devices only.
DS70005258C-page 16
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT DIGITAL
SIGNAL CONTROLLERS
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
Consider the following criteria when using decoupling
capacitors:
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2.1
Basic Connection Requirements
• Handling high-frequency noise: If the board is
experiencing high-frequency noise, above tens
of MHz, add a second ceramic-type capacitor in
parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
Getting started with the dsPIC33EPXXXGS70X/80X
family requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names which must always be
connected:
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins
regardless if ADC module is not used (see
Section 2.2 “Decoupling Capacitors”)
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
• VCAP
(see Section 2.3 “CPU Logic Filter Capacitor
Connection (VCAP)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins
used for In-Circuit Serial Programming™ (ICSP™)
and debugging purposes (see Section 2.5 “ICSP
Pins”)
inductance.
• OSC1 and OSC2 pins
when external oscillator source is used (see
Section 2.6 “External Oscillator Pins”)
2016-2018 Microchip Technology Inc.
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The placement of this capacitor should be close to the
VCAP pin. It is recommended that the trace length not
exceed one-quarter inch (6 mm). See Section 27.4
“On-Chip Voltage Regulator” for details.
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
0.1 µF
Ceramic
10 µF
Tantalum
VDD
2.4
Master Clear (MCLR) Pin
R
The MCLR pin provides two specific device
functions:
R1
MCLR
• Device Reset
C
• Device Programming and Debugging.
dsPIC33EP
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
VDD
VSS
VDD
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
Ceramic
(1)
L1
For example, as shown in Figure 2-2, it is recom-
mended that the capacitor, C, be isolated from the
MCLR pin during programming and debugging
operations.
Note 1: As an option, instead of a hard-wired connection, an
inductor (L1) can be substituted between VDD and
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 1 and the inductor
capacity greater than 10 mA.
Place the components as shown in Figure 2-2, within
one-quarter inch (6 mm) from the MCLR pin.
Where:
FCNV
2
f = -------------
(i.e., ADC Conversion Rate/2)
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
1
f = -----------------------
2 LC
VDD
2
1
L = ---------------------
(1)
2f C
R
(2)
R1
MCLR
2.2.1
TANK CAPACITORS
JP
C
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits, including DSCs, to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
dsPIC33EP
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor, C, in the
event of MCLR pin breakdown due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
2.3
CPU Logic Filter Capacitor
Connection (VCAP)
A low-ESR (< 0.5Ω) capacitor is required on the VCAP
pin, which is used to stabilize the voltage regulator
output voltage. The VCAP pin must not be connected to
VDD and must have a capacitor greater than 4.7 µF
(10 µF is recommended), 16V connected to ground. The
type can be ceramic or tantalum. See Section 30.0
“Electrical Characteristics” for additional information.
DS70005258C-page 18
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dsPIC33EPXXXGS70X/80X FAMILY
2.5
ICSP Pins
2.6
External Oscillator Pins
The PGECx and PGEDx pins are used for ICSP and
debugging purposes. It is recommended to keep the
trace length between the ICSP connector and the ICSP
pins on the device as short as possible. If the ICSP con-
nector is expected to experience an ESD event, a
series resistor is recommended, with the value in the
range of a few tens of Ohms, not to exceed 100 Ohms.
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator. For details, see Section 9.0
“Oscillator Configuration” for details.
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
Pull-up resistors, series diodes and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin Voltage Input High
(VIH) and Voltage Input Low (VIL) requirements.
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP
to MPLAB® PICkit™ 3, MPLAB ICD 3, or MPLAB
REAL ICE™.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
For more information on MPLAB ICD 2, MPLAB ICD 3
and REAL ICE connection requirements, refer to the
following documents that are available on the
Microchip website.
Main Oscillator
Guard Ring
• “Using MPLAB® ICD 3 In-Circuit Debugger”
(poster) (DS51765)
Guard Trace
Oscillator Pins
• “Development Tools Design Advisory” (DS51764)
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide for MPLAB X IDE” (DS50002085)
• “Using MPLAB® REAL ICE™ In-Circuit Emulator”
(poster) (DS51749)
2016-2018 Microchip Technology Inc.
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2.7
Oscillator Value Conditions on
Device Start-up
2.9
Targeted Applications
• Power Factor Correction (PFC)
- Interleaved PFC
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 3 MHz < FIN < 5.5 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start up in the FRC mode first. The
default PLL settings, after a POR with an oscillator
frequency outside this range, will violate the device
operating speed.
- Critical Conduction PFC
- Bridgeless PFC
• DC/DC Converters
- Buck, Boost, Forward, Flyback, Push-Pull
- Half/Full-Bridge
- Phase-Shift Full-Bridge
- Resonant Converters
• DC/AC
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLFBD, to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration Word.
- Half/Full-Bridge Inverter
- Resonant Inverter
Examples of typical application connections are shown
in Figure 2-4 through Figure 2-6.
2.8
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic low state.
Alternatively, connect a 1k to 10k resistor between VSS
and unused pins, and drive the output to logic low.
FIGURE 2-4:
INTERLEAVED PFC
VOUT+
|VAC|
k
k
2
1
k
4
VAC
k
3
VOUT-
FET
Driver
FET
Driver
PGA/ADC Channel
ADC Channel
PWM PGA/ADC PWM PGA/ADC
ADC
Channel
Channel
Channel
dsPIC33EPXXXGS70X/80X
DS70005258C-page 20
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 2-5:
PHASE-SHIFTED FULL-BRIDGE CONVERTER
VIN+
Gate 6
Gate 3
VOUT+
S3
Gate 1
S1
VOUT-
Gate 2
Gate 4
Gate 5
VIN-
Gate 5
FET
Driver
k
2
k
1
Analog
Ground
Gate 1
S1
FET
Driver
PWM PGA/ADC PWM
Channel
ADC
Channel
Gate 3
S3
dsPIC33EPXXXGS70X/80X
PWM
FET
Driver
Gate 2
Gate 4
2016-2018 Microchip Technology Inc.
DS70005258C-page 21
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 2-6:
OFF-LINE UPS
VDC
Full-Bridge Inverter
Push-Pull Converter
V
OUT
+
-
VBAT
+
VOUT
GND
GND
FET
Driver
FET
FET
FET
FET
FET
Driver
k
k
k
k
5
2
1
4
Driver Driver Driver Driver
PWM
ADC
PWM PGA/ADC ADC
PWM
PWM
PWM
PWM
or
Analog Comp.
k
ADC
ADC
3
dsPIC33EPXXXGS70X/80X
PWM
ADC
FET
Driver
k
6
+
Battery Charger
DS70005258C-page 22
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dsPIC33EPXXXGS70X/80X FAMILY
3.2
Instruction Set
3.0
CPU
The instruction set for dsPIC33EPXXXGS70X/80X
devices has two classes of instructions: the MCU class
of instructions and the DSP class of instructions. These
two instruction classes are seamlessly integrated into the
architecture and execute from a single execution unit.
The instruction set includes many addressing modes and
was designed for optimum C compiler efficiency.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “dsPIC33E Enhanced
CPU” (DS70005158) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip website
(www.microchip.com).
3.3
Data Space Addressing
The base Data Space can be addressed as up to
4K words or 8 Kbytes, and is split into two blocks,
referred to as X and Y data memory. Each memory block
has its own independent Address Generation Unit
(AGU). The MCU class of instructions operates solely
through the X memory AGU, which accesses the entire
memory map as one linear Data Space. Certain DSP
instructions operate through the X and Y AGUs to sup-
port dual operand reads, which splits the data address
space into two parts. The X and Y Data Space boundary
is device-specific.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The dsPIC33EPXXXGS70X/80X family CPU has a 16-bit
(data) modified Harvard architecture with an enhanced
instruction set, including significant support for Digital
Signal Processing (DSP). The CPU has a 24-bit
instruction word with a variable length opcode field.
The Program Counter (PC) is 23 bits wide and
addresses up to 4M x 24 bits of user program memory
space.
The upper 32 Kbytes of the Data Space memory map
can optionally be mapped into Program Space (PS) at
any 16K program word boundary. The program-to-Data
Space mapping feature, known as Program Space
Visibility (PSV), lets any instruction access Program
Space as if it were Data Space. Refer to “Data
Memory” (DS70595) in the “dsPIC33/PIC24 Family
Reference Manual” for more details on PSV and table
accesses.
An instruction prefetch mechanism helps maintain
throughput and provides predictable execution. Most
instructions execute in a single-cycle effective execu-
tion rate, with the exception of instructions that change
the program flow, the double-word move (MOV.D)
instruction, PSV accesses and the table instructions.
Overhead-free program loop constructs are supported
using the DO and REPEAT instructions, both of which
are interruptible at any point.
On dsPIC33EPXXXGS70X/80X devices, overhead-free
circular buffers (Modulo Addressing) are supported in
both X and Y address spaces. The Modulo Addressing
removes the software boundary checking overhead for
DSP algorithms. The X AGU Circular Addressing can be
used with any of the MCU class of instructions. The
X AGU also supports Bit-Reversed Addressing to
greatly simplify input or output data re-ordering for
radix-2 FFT algorithms.
3.1
Registers
The dsPIC33EPXXXGS70X/80X devices have sixteen,
16-bit Working registers in the programmer’s model. Each
of the Working registers can act as a Data, Address or
Address Offset register. The 16th Working register (W15)
operates as a Software Stack Pointer for interrupts and
calls.
3.4
Addressing Modes
The CPU supports these addressing modes:
In addition, the dsPIC33EPXXXGS70X/80X devices
include four Alternate Working register sets which consist
of W0 through W14. The Alternate Working registers can
be made persistent to help reduce the saving and restor-
ing of register content during Interrupt Service Routines
(ISRs). The Alternate Working registers can be assigned
to a specific Interrupt Priority Level (IPL1 through IPL7) by
configuring the CTXTx<2:0> bits in the FALTREG Config-
uration register. The Alternate Working registers can also
be accessed manually by using the CTXTSWPinstruction.
The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT
register can be used to identify the current, and most
recent, manually selected Working register sets.
• Inherent (no operand)
• Relative
• Literal
• Memory Direct
• Register Direct
• Register Indirect
Each instruction is associated with a predefined
addressing mode group, depending upon its functional
requirements. As many as six addressing modes are
supported for each instruction.
2016-2018 Microchip Technology Inc.
DS70005258C-page 23
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 3-1:
dsPIC33EPXXXGS70X/80X FAMILY CPU BLOCK DIAGRAM
X Address Bus
Y Data Bus
X Data Bus
16
16
16
16
Data Latch
Data Latch
Interrupt
Controller
PSV and Table
Data Access
Control Block
Y Data
RAM
X Data
RAM
8
16
24
24
16
Address
Latch
Address
Latch
24
16
16
24
X RAGU
X WAGU
PCU PCH PCL
Program Counter
16
Loop
Control
Logic
Stack
Control
Logic
Address Latch
Program Memory
Data Latch
Y AGU
16
EA MUX
16
16
24
24
16
16-Bit
Working Register Arrays
16
16
16
Divide
Support
DSP
Engine
16-Bit ALU
16
Instruction
Decode and
Control
Control Signals
to Various Blocks
16
Power, Reset
and Oscillator
Modules
Ports
Peripheral
Modules
DS70005258C-page 24
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dsPIC33EPXXXGS70X/80X FAMILY
In addition to the registers contained in the programmer’s
3.5
Programmer’s Model
model, the dsPIC33EPXXXGS70X/80X devices contain
control registers for Modulo Addressing, Bit-Reversed
Addressing and interrupts. These registers are
described in subsequent sections of this document.
The programmer’s model for the dsPIC33EPXXXGS70X/
80X family is shown in Figure 3-2. All registers in the
programmer’s model are memory-mapped and can be
manipulated directly by instructions. Table 3-1 lists a
description of each register.
All registers associated with the programmer’s model
are memory-mapped, as shown in Table 3-1.
TABLE 3-1:
PROGRAMMER’S MODEL REGISTER DESCRIPTIONS
Register(s) Name
Description
W0 through W15(1)
W0 through W14(1)
W0 through W14(1)
W0 through W14(1)
W0 through W14(1)
ACCA, ACCB
PC
Working Register Array
Alternate 1 Working Register Array
Alternate 2 Working Register Array
Alternate 3 Working Register Array
Alternate 4 Working Register Array
40-Bit DSP Accumulators
23-Bit Program Counter
SR
ALU and DSP Engine STATUS Register
Stack Pointer Limit Value Register
SPLIM
TBLPAG
Table Memory Page Address Register
Extended Data Space (EDS) Read Page Register
REPEATLoop Counter Register
DSRPAG
RCOUNT
DCOUNT
DOLoop Counter Register
DOSTARTH(2), DOSTARTL(2)
DOENDH, DOENDL
CORCON
DOLoop Start Address Register (High and Low)
DOLoop End Address Register (High and Low)
Contains DSP Engine, DOLoop Control and Trap Status bits
Note 1: Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context.
2: The DOSTARTH and DOSTARTL registers are read-only.
2016-2018 Microchip Technology Inc.
DS70005258C-page 25
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 3-2:
PROGRAMMER’S MODEL
D15
D0
D15
D0
D15
D0
D15
D0
D15
D0
W0
W0
W0 (WREG) W0
W1 W1
W0
W1
W1
W1
W0-W3
W2
W3
W4
W2
W3
W4
W2
W3
W4
W5
W2
W3
W4
W2
W3
W4
Alternate
Working/Address
Registers
W5
W6
W7
W5
W6
W7
DSP Operand
W5
W5
W6
W7
Registers
W6 W6
Working/Address
Registers
W7
W8
W7
W8
W8
W9
W8
W9
W8
W9
W9 W9
DSP Address
Registers
W10 W10
W11 W11
W10 W10
W11 W11
W12 W12
W10
W11
W12
W12 W12
W13 W13
W14 W14
W13 W13 W13
Frame Pointer/W14 W14 W14
0
Stack Pointer/W15
PUSH.Sand POP.SShadows
Nested DOStack
Stack Pointer Limit
0
SPLIM
AD39
AD31
AD15
AD0
ACCA
DSP
Accumulators
ACCB
PC23
PC0
0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
9
0
DSRPAG
X Data Space Read Page Address
15
0
0
RCOUNT
DCOUNT
REPEATLoop Counter
15
DOLoop Counter and Stack
23
0
0
DOLoop Start Address and Stack
DOLoop End Address and Stack
0
DOSTART
23
0
0
DOEND
15
0
0
CORCON
CPU Core Control Register
SRL
OA OB SA SB OAB SAB DA DC IPL2 IPL1 IPL0 RA
N
OV
Z
C
STATUS Register
DS70005258C-page 26
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dsPIC33EPXXXGS70X/80X FAMILY
3.6.1
KEY RESOURCES
3.6
CPU Resources
• “dsPIC33E Enhanced CPU” (DS70005158) in the
“dsPIC33/PIC24 Family Reference Manual”
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2016-2018 Microchip Technology Inc.
DS70005258C-page 27
dsPIC33EPXXXGS70X/80X FAMILY
3.7
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R/W-0
OA
R/W-0
OB
R/W-0
SA(3)
R/W-0
SB(3)
R/C-0
OAB
R/C-0
SAB
R-0
DA
R/W-0
DC
bit 15
bit 8
R/W-0(2)
IPL2(1)
bit 7
R/W-0(2)
IPL1(1)
R/W-0(2)
IPL0(1)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’= Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
OA: Accumulator A Overflow Status bit
1= Accumulator A has overflowed
0= Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1= Accumulator B has overflowed
0= Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(3)
1= Accumulator A is saturated or has been saturated at some time
0= Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(3)
1= Accumulator B is saturated or has been saturated at some time
0= Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1= Accumulator A or B has overflowed
0= Neither Accumulator A or B has overflowed
SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit
1= Accumulator A or B is saturated or has been saturated at some time
0= Neither Accumulator A or B is saturated
DA: DOLoop Active bit
1= DOloop is in progress
0= DOloop is not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
DS70005258C-page 28
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(1,2)
111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEATLoop Active bit
1= REPEATloop is in progress
0= REPEATloop is not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of the magnitude that
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation that affects the Z bit has set it at some time in the past
0= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by
clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not
be modified using bit operations.
2016-2018 Microchip Technology Inc.
DS70005258C-page 29
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
R/W-0
VAR
U-0
—
R/W-0
US1
R/W-0
US0
R/W-0
EDT(1)
R-0
R-0
R-0
DL2
DL1
DL0
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R-0
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
SFA
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
VAR: Variable Exception Processing Latency Control bit
1= Variable exception processing latency is enabled
0= Fixed exception processing latency is enabled
bit 14
Unimplemented: Read as ‘0’
bit 13-12
US<1:0>: DSP Multiply Unsigned/Signed Control bits
11= Reserved
10= DSP engine multiplies are mixed-sign
01= DSP engine multiplies are unsigned
00= DSP engine multiplies are signed
bit 11
EDT: Early DOLoop Termination Control bit(1)
1= Terminates executing DOloop at the end of current loop iteration
0= No effect
bit 10-8
DL<2:0>: DOLoop Nesting Level Status bits
111= Seven DOloops are active
•
•
•
001= One DOloop is active
000= Zero DOloops are active
bit 7
bit 6
bit 5
bit 4
bit 3
SATA: ACCA Saturation Enable bit
1= Accumulator A saturation is enabled
0= Accumulator A saturation is disabled
SATB: ACCB Saturation Enable bit
1= Accumulator B saturation is enabled
0= Accumulator B saturation is disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1= Data Space write saturation is enabled
0= Data Space write saturation is disabled
ACCSAT: Accumulator Saturation Mode Select bit
1= 9.31 saturation (super saturation)
0= 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
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REGISTER 3-2:
CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 2
bit 1
bit 0
SFA: Stack Frame Active Status bit
1= Stack frame is active; W14 and W15 address 0x0000 to 0xFFFF, regardless of DSRPAG
0= Stack frame is not active; W14 and W15 address the base Data Space
RND: Rounding Mode Select bit
1= Biased (conventional) rounding is enabled
0= Unbiased (convergent) rounding is enabled
IF: Integer or Fractional Multiplier Mode Select bit
1= Integer mode is enabled for DSP multiply
0= Fractional mode is enabled for DSP multiply
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
REGISTER 3-3:
CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
CCTXI2
CCTXI1
CCTXI0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
MCTXI2
MCTXI1
MCTXI0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
CCTXI<2:0>: Current (W Register) Context Identifier bits
111= Reserved
•
•
•
101= Reserved
100= Alternate Working Register Set 4 is currently in use
011= Alternate Working Register Set 3 is currently in use
010= Alternate Working Register Set 2 is currently in use
001= Alternate Working Register Set 1 is currently in use
000= Default register set is currently in use
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
MCTXI<2:0>: Manual (W Register) Context Identifier bits
111= Reserved
•
•
•
101= Reserved
100= Alternate Working Register Set 4 was most recently manually selected
011= Alternate Working Register Set 3 was most recently manually selected
010= Alternate Working Register Set 2 was most recently manually selected
001= Alternate Working Register Set 1 was most recently manually selected
000= Default register set was most recently manually selected
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
3.8
Arithmetic Logic Unit (ALU)
3.9
DSP Engine
The dsPIC33EPXXXGS70X/80X family ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts and
logic operations. Unless otherwise mentioned, arithmetic
operations are two’s complement in nature. Depending
on the operation, the ALU can affect the values of the
Carry (C), Zero (Z), Negative (N), Overflow (OV) and
Digit Carry (DC) Status bits in the SR register. The C
and DC Status bits operate as Borrow and Digit Borrow
bits, respectively, for subtraction operations.
The DSP engine consists of a high-speed 17-bit x 17-bit
multiplier, a 40-bit barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine can also perform inherent accumulator-
to-accumulator operations that require no additional
data. These instructions are, ADD, SUBand NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
• Fractional or Integer DSP Multiply (IF)
• Signed, Unsigned or Mixed-Sign DSP Multiply
(USx)
• Conventional or Convergent Rounding (RND)
• Automatic Saturation On/Off for ACCA (SATA)
• Automatic Saturation On/Off for ACCB (SATB)
Refer to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70000157) for information on
the SR bits affected by each instruction.
• Automatic Saturation On/Off for Writes to Data
Memory (SATDW)
The core CPU incorporates hardware support for both
multiplication and division. This includes a dedicated
hardware multiplier and support hardware for 16-bit
divisor division.
• Accumulator Saturation mode Selection
(ACCSAT)
TABLE 3-2:
Instruction
DSP INSTRUCTIONS
SUMMARY
3.8.1
MULTIPLIER
Algebraic
ACC
Using the high-speed, 17-bit x 17-bit multiplier, the ALU
supports unsigned, signed or mixed-sign operation in
several MCU Multiplication modes:
Operation
Write-Back
CLR
A = 0
Yes
No
ED
A = (x – y)2
A = A + (x – y)2
A = A + (x • y)
A = A + x2
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
EDAC
MAC
No
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit signed x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
Yes
No
MAC
MOVSAC
MPY
No change in A
Yes
No
A = x • y
MPY
A = x2
No
3.8.2
DIVIDER
MPY.N
MSC
A = – x • y
No
A = A – x • y
Yes
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
• 32-bit signed/16-bit signed divide
• 32-bit unsigned/16-bit unsigned divide
• 16-bit signed/16-bit signed divide
• 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
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User application access to the program memory space
4.0
MEMORY ORGANIZATION
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD operations, which use TBLPAG<7> to permit
access to calibration data and Device ID sections of the
configuration memory space.
Note:
This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “dsPIC33E/PIC24E Program
Memory” (DS70000613) in the “dsPIC33/
PIC24 Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
The program memory maps for dsPIC33EPXXXGS70X/
80X devices not operating in Dual Partition mode are
shown in Figure 4-1 and Figure 4-2.
The dsPIC33EPXXXGS70X/80X devices can operate
in a Dual Partition Flash Program Memory mode,
where the user Program Flash Memory is arranged as
two separate address spaces, one for each of the
Flash partitions. The Active Partition always starts at
address, 0x000000, and contains half of the available
Flash memory (64k/128k, depends on device). The
Inactive Partition always starts at address, 0x400000,
and implements the remaining half of Flash memory.
As shown in Figure 4-3 and Figure 4-4, the Active and
Inactive Partitions are identical, and both contain
unique copies of the Reset vector, Interrupt Vector
Tables (IVT and AIVT if enabled) and the Flash
Configuration Words.
The dsPIC33EPXXXGS70X/80X family architecture
features separate program and data memory spaces,
and buses. This architecture also allows the direct
access of program memory from the Data Space (DS)
during code execution.
4.1
Program Address Space
The program address memory space of the
dsPIC33EPXXXGS70X/80X family devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit PC during program
execution, or from table operation or Data Space
remapping, as described in Section 4.9 “Interfacing
Program and Data Memory Spaces”.
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dsPIC33EPXXXGS70X/80X FAMILY
The UDID is stored in five read-only locations,
located between 800F00h and 800F08h in the
device configuration space. Table 4-1 lists the
addresses of the identifier words and shows their
contents.
4.2
Unique Device Identifier (UDID)
All dsPIC33EPXXXGS70X/80X family devices are
individually encoded during final manufacturing with
a Unique Device Identifier or UDID. This feature
allows for manufacturing traceability of Microchip
Technology devices in applications where this is a
requirement. It may also be used by the application
manufacturer for any number of things that may
require unique identification, such as:
TABLE 4-1:
UDID ADDRESSES
Name Address Bits 23:16 Bits 15:8 Bits 7:0
UDID1 800F00
UDID2 800F02
UDID3 800F04
UDID4 800F06
UDID5 800F08
UDID Word 1
UDID Word 2
UDID Word 3
UDID Word 4
UDID Word 5
• Tracking the device
• Unique serial number
• Unique security key
The UDID comprises five 24-bit program words.
When taken together, these fields form a unique
120-bit identifier.
FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP64GS70X/80X DEVICES
0x000000
GOTOInstruction
0x000002
Reset Address
0x000004
0x0001FE
0x000200
Interrupt Vector Table
User Program
Flash Memory
(22,016 instructions)
0x00AF7E
0x00AF80
Device Configuration
0x00AFFE
0x00B000
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
0x800EFE
0x800F00
Reserved
UDID
0x800F08
0x800F0A
0x800F7E
0x800F80
Reserved
User OTP Memory
Reserved
0x800FFC
0x801000
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
DEVID
Reserved
0xFFFFFE
Note: Memory areas are not shown to scale.
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dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EP128GS70X/80X DEVICES
0x000000
GOTOInstruction
0x000002
Reset Address
0x000004
0x0001FE
0x000200
Interrupt Vector Table
User Program
Flash Memory
(44,032 instructions)
0x01577E
0x015780
Device Configuration
0x0157FE
0x015800
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
Reserved
0x800E78
0x800E7A
0x800F7E
0x800F80
User OTP Memory
0x800FFC
0x801000
Reserved
0xF9FFFE
0xFA0000
Write Latches
0xFA0002
0xFA0004
Reserved
0xFEFFFE
0xFF0000
0xFF0002
0xFF0004
DEVID
Reserved
0xFFFFFE
Note: Memory areas are not shown to scale.
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dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 4-3: PROGRAM MEMORY MAP FOR dsPIC33EP64GS70X/80X DEVICES
(DUAL PARTITION)
0x000000
GOTOInstruction
0x000002
Reset Address
0x000004
0x0001FE
0x000200
Interrupt Vector Table
Active Program
Flash Memory
Active Partition
(11,008 instructions)
0x00577E
0x005780
Device Configuration
0x0057FE
0x005800
Unimplemented
(Read ‘0’s)
0x3FFFFE
0x400000
GOTOInstruction
Reset Address
0x400002
0x400004
Interrupt Vector Table
0x4001FE
0x400200
Inactive Partition
Inactive Program
Flash Memory
(11,008 instructions)
0x40577E
0x405780
Device Configuration
Unimplemented
0x4057FE
0x405800
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
User OTP Memory
Reserved
0x800F7E
0x800F80
0x800FFC
0x800100
0xF9FFFE
0xFA0000
Write Latches
Reserved
0xFA0002
0xFA0004
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE
Note: Memory areas are not shown to scale.
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dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 4-4: PROGRAM MEMORY MAP FOR dsPIC33EP128GS70X/80X DEVICES
(DUAL PARTITION)
0x000000
GOTOInstruction
0x000002
Reset Address
0x000004
0x0001FE
0x000200
Interrupt Vector Table
Active Program
Flash Memory
Active Partition
(22,016 instructions)
0x00AB7E
0x00AB80
Device Configuration
0x00ABFE
0x00AC00
Unimplemented
(Read ‘0’s)
0x3FFFFE
0x400000
GOTOInstruction
Reset Address
0x400002
0x400004
Interrupt Vector Table
0x4001FE
0x400200
Inactive Partition
Inactive Program
Flash Memory
(22,016 instructions)
0x40AB7E
0x40AB80
Device Configuration
Unimplemented
0x40ABFE
0x40AC00
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
0x800E46
0x800E48
Calibration Data
0x800E78
0x800E7A
Reserved
User OTP Memory
Reserved
0x800F7E
0x800F80
0x800FFC
0x800100
0xF9FFFE
0xFA0000
Write Latches
Reserved
0xFA0002
0xFA0004
0xFEFFFE
0xFF0000
DEVID
0xFF0002
0xFF0004
Reserved
0xFFFFFE
Note: Memory areas are not shown to scale.
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dsPIC33EPXXXGS70X/80X FAMILY
4.2.1
PROGRAM MEMORY
ORGANIZATION
4.2.2
INTERRUPT AND TRAP VECTORS
All dsPIC33EPXXXGS70X/80X family devices reserve
the addresses between 0x000000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTOinstruction is programmed
by the user application at address, 0x000000, of Flash
memory, with the actual address for the start of code at
address, 0x000002, of Flash memory.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-5).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two, during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
A more detailed discussion of the Interrupt Vector
Tables (IVTs) is provided in Section 7.1 “Interrupt
Vector Table”.
FIGURE 4-5:
PROGRAM MEMORY ORGANIZATION
least significant word
PC Address
most significant word
23
msw
Address
(lsw Address)
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
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dsPIC33EPXXXGS70X/80X FAMILY
All word accesses must be aligned to an even address.
4.3
Data Address Space
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
The dsPIC33EPXXXGS70X/80X family CPU has a
separate 16-bit wide data memory space. The Data
Space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory map is shown in Figure 4-6.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the Data
Space. This arrangement gives a base Data Space
address range of 64 Kbytes or 32K words.
The lower half of the data memory space (i.e., when
EA<15> = 0) is used for implemented memory
addresses, while the upper half (EA<15> = 1) is
reserved for the Program Space Visibility (PSV).
All byte loads into any W register are loaded into the
LSB; the MSB is not modified.
A Sign-Extend (SE) instruction is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a Zero-Extend (ZE) instruction on the
appropriate address.
dsPIC33EPXXXGS70X/80X family devices implement
up to 12 Kbytes of data memory. If an EA points to a
location outside of this area, an all-zero word or byte is
returned.
4.3.1
DATA SPACE WIDTH
4.3.3
SFR SPACE
The data memory space is organized in byte-
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all Data
Space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
The first 4 Kbytes of the Near Data Space, from
0x0000 to 0x0FFF, is primarily occupied by Special
Function Registers (SFRs). These are used by the
dsPIC33EPXXXGS70X/80X family core and peripheral
modules for controlling the operation of the device.
SFRs are distributed among the modules that they
control and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.3.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve Data Space memory usage
efficiency, the dsPIC33EPXXXGS70X/80X family
instruction set supports both word and byte operations.
As a consequence of byte accessibility, all Effective
Address calculations are internally scaled to step
through word-aligned memory. For example, the core
recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and
pinout diagrams for device-specific
information.
4.3.4
NEAR DATA SPACE
The 8-Kbyte area, between 0x0000 and 0x1FFF, is
referred to as the Near Data Space. Locations in this
space are directly addressable through a 13-bit absolute
address field within all memory direct instructions. Addi-
tionally, the whole Data Space is addressable using MOV
instructions, which support Memory Direct Addressing
mode with a 16-bit address field, or by using Indirect
Addressing mode using a Working register as an
Address Pointer.
A data byte read, reads the complete word that
contains the byte, using the LSb of any EA to determine
which byte to select. The selected byte is placed onto
the LSB of the data path. That is, data memory and
registers are organized as two parallel, byte-wide
entities with shared (word) address decode, but
separate write lines. Data byte writes only write to the
corresponding side of the array or register that matches
the byte address.
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dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 4-6: DATA MEMORY MAP FOR dsPIC33EP64GS70X/80X DEVICES
MSB
Address
LSB
Address
16 Bits
MSB
LSB
0x0000
0x0001
4-Kbyte
SFR Space
SFR Space
0x0FFE
0x1000
0x0FFF
0x1001
8-Kbyte
Near
Data Space
X Data RAM (X)
Y Data RAM (Y)
8-Kbyte
SRAM Space
0x1FFF
0x2001
0x1FFE
0x2000
0x2FFF
0x3001
0x2FFE
0x3000
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
Note:
Memory areas are not shown to scale.
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dsPIC33EPXXXGS70X/80X FAMILY
4.3.5
X AND Y DATA SPACES
4.4
Memory Resources
The dsPIC33EPXXXGS70X/80X core has two Data
Spaces, X and Y. These Data Spaces can be considered
either separate (for some DSP instructions) or as one
unified linear address range (for MCU instructions). The
Data Spaces are accessed using two Address Genera-
tion Units (AGUs) and separate data paths. This feature
allows certain instructions to concurrently fetch two
words from RAM, thereby enabling efficient execution of
DSP algorithms, such as Finite Impulse Response (FIR)
filtering and Fast Fourier Transform (FFT).
Many useful resources are provided on the main
product page of the Microchip website for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
4.4.1
KEY RESOURCES
• “dsPIC33E/PIC24E Program Memory”
(DS70000613) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
The X Data Space is used by all instructions and
supports all addressing modes. X Data Space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
Data Space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MACclass).
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
The Y Data Space is used in concert with the X Data
Space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.Nand MSC) to provide
two concurrent data read paths.
Both the X and Y Data Spaces support Modulo Address-
ing mode for all instructions, subject to addressing mode
restrictions. Bit-Reversed Addressing mode is only
supported for writes to X Data Space.
All data memory writes, including in DSP instructions,
view Data Space as combined X and Y address space.
The boundary between the X and Y Data Spaces is
device-dependent and is not user-programmable.
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dsPIC33EPXXXGS70X/80X FAMILY
4.5
Special Function Register Maps
TABLE 4-2:
SFR BLOCK 000h
Register
Core
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
WREG14
01C
01E
020
022
024
026
028
02A
02C
02E
030
032
034
036
038
0000000000000000 DOSTARTL
0000100000000000 DOSTARTH
xxxxxxxxxxxxxxx0 DOENDL
xxxxxxxxxxxxxxxx DOENDH
xxxxxxxxxxxxxxxx SR
03A
03C
03E
040
042
044
046
048
04A
04C
04E
050
052
054
05A
xxxxxxxxxxxxxxx0
0000000000xxxxxx
xxxxxxxxxxxxxxx0
0000000000xxxxxx
0000000000000000
0000000000100000
0000000000000000
xxxxxxxxxxxxxxx0
xxxxxxxxxxxxxxx1
xxxxxxxxxxxxxxx0
xxxxxxxxxxxxxxx1
xxxxxxxxxxxxxxxx
00xxxxxxxxxxxxxx
00000000xxxxxxxx
0000000000000000
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
000
002
004
006
008
00A
00C
00E
010
012
014
016
018
01A
0000000000000000 WREG15
0000000000000000 SPLIM
0000000000000000 ACCAL
0000000000000000 ACCAH
0000000000000000 ACCAU
0000000000000000 ACCBL
0000000000000000 ACCBH
0000000000000000 ACCBU
0000000000000000 PCL
00000000xxxxxxxx CORCON
xxxxxxxxxxxxxxxx MODCON
xxxxxxxxxxxxxxxx XMODSRT
00000000xxxxxxxx XMODEND
0000000000000000 YMODSRT
0000000000000000 YMODEND
0000000000000001 XBREV
0000000000000001 DISICNT
xxxxxxxxxxxxxxxx TBLPAG
xxxxxxxxxxxxxxxx CTXTSTAT
0000000000000000 PCH
0000000000000000 DSRPAG
0000000000000000 DSWPAG
0000000000000000 RCOUNT
0000000000000000 DCOUNT
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
TABLE 4-3:
SFR BLOCK 100h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
Timers
TMR5HLD
116
118
11A
11C
11E
120
xxxxxxxxxxxxxxxx IC2CON2
xxxxxxxxxxxxxxxx IC2BUF
1111111111111111 IC2TMR
1111111111111111 IC3CON1
0000000000000000 IC3CON2
0000000000000000 IC3BUF
IC3TMR
14A
14C
14E
150
152
154
156
158
15A
15C
15E
0000000000001101
xxxxxxxxxxxxxxxx
0000000000000000
0000000000000000
0000000000001101
xxxxxxxxxxxxxxxx
0000000000000000
0000000000000000
0000000000001101
xxxxxxxxxxxxxxxx
0000000000000000
TMR1
PR1
100
102
104
106
108
10A
10C
10E
110
112
114
xxxxxxxxxxxxxxxx TMR5
1111111111111111 PR4
T1CON
TMR2
TMR3HLD
TMR3
PR2
0000000000000000 PR5
xxxxxxxxxxxxxxxx T4CON
xxxxxxxxxxxxxxxx T5CON
xxxxxxxxxxxxxxxx Input Capture
1111111111111111 IC1CON1
1111111111111111 IC1CON2
0000000000000000 IC1BUF
0000000000000000 IC1TMR
xxxxxxxxxxxxxxxx IC2CON1
140
142
144
146
148
0000000000000000 IC4CON1
0000000000001101 IC4CON2
xxxxxxxxxxxxxxxx IC4BUF
0000000000000000 IC4TMR
0000000000000000
PR3
T2CON
T3CON
TMR4
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
DS70005258C-page 42
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-4:
SFR BLOCK 200h
Register
Address
All Resets
Register
U1STA
Address
All Resets
Register
Address
All Resets
I2C1 and I2C2
I2C1CONL
I2C1CONH
I2C1STAT
I2C1ADD
I2C1MSK
I2C1BRG
I2C1TRN
I2C1RCV
I2C2CON1
I2C2CON2
I2C2STAT
I2C2ADD
I2C2MSK
I2C2BRG
I2C2TRN
I2C2RCV
222
224
226
228
230
232
234
236
238
0000000010010000 SPI1BRGH
0000000xxxxxxxxx SPI1IMSKL
0000000000000000 SPI1IMSKH
0000000000000000 SPI1URDTL
0000000000000000 SPI1URDTH
0000000010010000 SPI2CON1L
0000000xxxxxxxxx SPI2CON1H
0000000000000000 SPI2CON2L
0000000000000000 SPI2CON2H
SPI2STATL
252
254
256
258
25A
260
262
264
266
268
26A
26C
26E
270
272
274
276
278
27A
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000101000
0000000000000000
0000000000000000
0000000000000000
000xxxxxxxxxxxxx
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
200
202
204
206
208
20A
20C
20E
210
212
214
216
218
21A
21C
21E
0001000000000000 U1TXREG
0000000000000000 U1RXREG
0000000000000000 U1BRG
0000000000000000 U2MODE
0000000000000000 U2STA
0000000000000000 U2TXREG
0000000011111111 U2RXREG
0000000000000000 U2BRG
0001000000000000 SPI
0000000000000000 SPI1CON1L
0000000000000000 SPI1CON1H
0000000000000000 SPI1CON2L
0000000000000000 SPI1CON2H
0000000000000000 SPI1STATL
0000000011111111 SPI1STATH
0000000000000000 SPI1BUFL
SPI1BUFH
240
242
244
246
248
24A
24C
24E
250
0000000000000000 SPI2STATH
0000000000000000 SPI2BUFL
0000000000000000 SPI2BUFH
0000000000000000 SPI3STAT
0000000000101000 SPI2BRGH
0000000000000000 SPI2IMSKL
0000000000000000 SPI2IMSKH
0000000000000000 SPI2URDTL
000xxxxxxxxxxxxx SPI2URDTH
UART1 and UART2
U1MODE 220
0000000000000000 SPI1BRGL
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
TABLE 4-5:
SFR BLOCK 300h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
ADC
ADCMP0ENH
33A
33C
33E
340
342
344
346
368
36A
36C
36E
380
382
384
386
388
38A
38C
38E
0000000000000000 ADTRIG4L
0000000000000000 ADTRIG4H
0000000000000000 ADCMP0CON
0000000000000000 ADCMP1CON
0000000000000000 ADBASE
0000000000000000 ADLVLTRGL
0000000000000000 ADLVLTRGH
0000000000000000 ADCORE0L
0000000000000000 ADCORE0H
0000000000000000 ADCORE1L
0000000000000000 ADCORE1H
0000000000000000 ADCORE2L
0000000000000000 ADCORE2H
0000000000000000 ADCORE3L
0000000000000000 ADCORE3H
0000000000000000 ADEIEL
390
392
3A0
3A4
3C0
3D0
3D2
3D4
3D6
3D8
3DA
3DC
3DE
3E0
3E2
3F0
3F2
3F8
3FA
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000001100000000
0000000000000000
0000001100000000
0000000000000000
0000001100000000
0000000000000000
0000001100000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
ADCON1L
ADCON1H
ADCON2L
ADCON2H
ADCON3L
ADCON3H
ADCON4L
ADCON4H
ADMOD0L
ADMOD0H
ADMOD1L
ADIEL
300
302
304
306
308
30A
30C
30E
310
312
314
320
322
328
32A
330
332
338
0000000000000000 ADCMP0LO
0000000001100000 ADCMP0HI
0000000000000000 ADCMP1ENL
0000000000000000 ADCMP1ENH
0000000000000000 ADCMP1LO
0000000000000000 ADCMP1HI
0000000000000000 ADFL0DAT
0000000000000000 ADFL0CON
0000000000000000 ADFL1DAT
0000000000000000 ADFL1CON
0000000000000000 ADTRIG0L
0000000000000000 ADTRIG0H
0000000000000000 ADTRIG1L
0000000000000000 ADTRIG1H
0000000000000000 ADTRIG2L
0000000000000000 ADTRIG2H
0000000000000000 ADTRIG3L
0000000000000000 ADTRIG3H
ADIEH
ADCSS1L
ADCSS1H
ADSTATL
ADSTATH
ADCMP0ENL
0000000000000000 ADEIEH
0000000000000000 ADEISTATL
0000000000000000 ADEISTATH
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
2016-2018 Microchip Technology Inc.
DS70005258C-page 43
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-6:
SFR BLOCK 400h
Register
Address
All Resets
Register
Address
All Resets
Address
All Resets
Register
ADC (Continued)
C1FCTRL
486
488
48A
48C
48E
490
492
494
498
49A
0000000000000000 C1RXM2EID
0000000000000000 C1RXF1SID
0000000000000000 C1RXF1EID
0000000000000000 C1RXF2SID
0000000000000000 C1RXF2EID
0000000000000000 C1RXF3SID
0x000xxxxxxxxxxx C1RXF3EID
1111111111111111 C1RXF4SID
0000000000000000 C1RXF4EID
0000000000000000 C1RXF5SID
C1RXF5EID
4BA
4C4
4C6
4C8
4CA
4CC
4CE
4D0
4D2
4D4
4D6
4D8
4DA
4DC
4DE
4E0
4E2
4E4
4E6
4E8
4EA
4EC
4EE
4F0
4F2
4F4
4F6
4F8
4FA
4FC
4FE
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
ADCON5L
ADCON5H
ADCAL0L
400
0000000000000000 C1FIFO
0000000000000000 C1INTF
0000000000000000 C1INTE
0000000000000000 C1EC
402
404
406
40A
40C
40E
410
412
414
416
418
41A
41C
41E
420
422
424
426
428
42A
42C
42E
430
432
434
436
ADCAL0H
ADCAL1H
ADCBUF0
ADCBUF1
ADCBUF2
ADCBUF3
ADCBUF4
ADCBUF5
ADCBUF6
ADCBUF7
ADCBUF8
ADCBUF9
ADCBUF10
ADCBUF11
ADCBUF12
ADCBUF13
ADCBUF14
ADCBUF15
ADCBUF16
ADCBUF17
ADCBUF18
ADCBUF19
ADCBUF20
ADCBUF21
0000000000000000 C1CFG1
0000000000000000 C1CFG2
0000000000000000 C1FEN1
0000000000000000 C1FMSKSEL1
0000000000000000 C1FMSKSEL2
0000000000000000 CAN (WIN (C1CTRL<0>) = 0)
0000000000000000 C1RXFUL1
0000000000000000 C1RXFUL2
0000000000000000 C1RXOVF1
0000000000000000 C1RXOVF2
0000000000000000 C1TR01CON
0000000000000000 C1TR23CON
0000000000000000 C1TR45CON
0000000000000000 C1TR67CON
0000000000000000 C1RXD
4A0
4A2
4A8
4AA
4B0
4B2
4B4
4B6
4C0
4C2
0000000000000000 C1RXF6SID
0000000000000000 C1RXF6EID
0000000000000000 C1RXF7SID
0000000000000000 C1RXF7EID
0000000000000000 C1RXF8SID
0000000000000000 C1RXF8EID
0000000000000000 C1RXF9SID
xxxxxxxxxxxxxxxx C1RXF9EID
xxxxxxxxxxxxxxxx C1RXF10SID
xxxxxxxxxxxxxxxx C1RXF10EID
C1RXF11SID
0000000000000000 C1TXD
0000000000000000 CAN (WIN (C1CTR1<0>) = 1)
0000000000000000 C1BUFPNT1
0000000000000000 C1BUFPNT2
0000000000000000 C1BUFPNT3
0000000000000000 C1BUFPNT4
0000000000000000 C1RXM0SID
0000000000000000 C1RXM0EID
4A0
4A2
4A4
4A6
4B0
4B2
4B4
4B6
0000000000000000 C1RXF11EID
0000000000000000 C1RXF12SID
0000000000000000 C1RXF12EID
0000000000000000 C1RXF13SID
xxxxxxxxxxxxxxxx C1RXF13EID
xxxxxxxxxxxxxxxx C1RXF14SID
xxxxxxxxxxxxxxxx C1RXF14EID
xxxxxxxxxxxxxxxx C1RXF15SID
C1RXF15EID
CAN (WIN (C1CTRL<0>) = 0 OR 1)
C1RXM1SID
C1CTRL1
C1CTRL2
C1VEC
480
482
484
000010010000000 C1RXM1EID
000000000000000 CAN
000000001000000 C1RXM2SID
4B8
xxxxxxxxxxxxxxxx
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
TABLE 4-7:
SFR BLOCK 500h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
PGA
PGA2CAL
50A
0000000000000000 CMP2DAC
CMP3CON
546
548
54A
54C
54E
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
ISRCCON
PGA1CON
PGA1CAL
PGA2CON
500
504
506
508
0000000000000000 Comparators
0000000000000000 CMP1CON
0000000000000000 CMP1DAC
0000000000000000 CMP2CON
540
542
544
0000000000000000 CMP3DAC
0000000000000000 CMP4CON
0000000000000000 CMP4DAC
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
DS70005258C-page 44
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-8:
SFR BLOCK 600h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
SPI
RPOR8
678
67A
67C
67E
680
682
684
686
68A
68C
68E
690
692
694
696
698
69A
69C
6A0
6A2
6A4
6A6
0000000000000000 RPINR7
0000000000000000 RPINR8
0000000000000000 RPINR11
0000000000000000 RPINR12
0000000000000000 RPINR13
0000000000000000 RPINR18
0000000000000000 RPINR19
0000000000000000 RPINR20
0000000000000000 RPINR21
0000000000000000 RPINR22
0000000000000000 RPINR23
0000000000000000 RPINR26
0000000000000000 RPINR29
0000000000000000 RPINR30
0000000000000000 RPINR37
0000000000000000 RPINR38
0000000000000000 RPINR42
0000000000000000 RPINR43
0000000000000000 RPINR45
0000000000000000 RPINR46
0000000000000000
6AE
6B0
6B6
6B8
6BA
6C4
6C6
6C8
6CA
6CC
6CE
6D4
6DA
6DC
6EA
6EC
6F4
6F6
6FA
6FC
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
SPI3CON1L
SPI3CON1H
SPI3CON2L
SPI3CON2H
SPI3STATL
SPI3STATH
SPI3BUFL
SPI3BUFH
SPI3BRGL
SPI3BRGH
SPI3IMSKL
SPI3IMSKH
SPI3URDTL
SPI3URDTH
RPOR0
600
602
604
606
608
60A
60C
60E
610
612
614
616
618
61A
668
66A
66C
66E
670
672
674
0000000000000000 RPOR9
0000000000000000 RPOR10
0000000000000000 RPOR11
0000000000000000 RPOR12
0000000000101000 RPOR13
0000000000000000 RPOR14
0000000000000000 RPOR15
0000000000000000 RPOR17
000xxxxxxxxxxxxx RPOR18
0000000000000000 RPOR19
0000000000000000 RPOR20
0000000000000000 RPOR21
0000000000000000 RPOR22
0000000000000000 RPOR23
0000000000000000 RPOR24
0000000000000000 RPOR25
0000000000000000 RPOR26
0000000000000000 RPINR0
0000000000000000 RPINR1
0000000000000000 RPINR2
0000000000000000 RPINR3
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
0000000000000000
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
2016-2018 Microchip Technology Inc.
DS70005258C-page 45
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-9:
SFR BLOCK 700h
Register
Address
All Resets
Register
C2INTF
Address
All Resets
Register
Address
All Resets
NVM
78A
78C
78E
790
792
794
798
79A
0000000000000000 C2RXF1SID
0000000000000000 C2RXF1EID
0000000000000000 C2RXF2SID
0000000000000000 C2RXF2EID
0x000xxxxxxxxxxx C2RXF3SID
1111111111111111 C2RXF3EID
0000000000000000 C2RXF4SID
0000000000000000 C2RXF4EID
7C4
7C6
7C8
7CA
7CC
7CE
7D0
7D2
7D4
7D6
7D8
7DA
7DC
7DE
7E0
7E2
7E4
7E6
7E8
7EA
7EC
7EE
7F0
7F2
7F4
7F6
7F8
7FA
7FC
7FE
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
NVMCON
NVMADR
NVMADRU
NVMKEY
NVMSRCADR
NVMSRCADRH
System Control
RCON
728
72A
72C
72E
730
732
0000000000000000 C2INTE
0000000000000000 C2EC
0000000000000000 C2CFG1
0000000000000000 C2CFG2
0000000000000000 C2FEN1
0000000000000000 C2FMSKSEL1
C2FMSKSEL2
740
742
744
746
748
74C
74E
750
0x00x0x01x0xxxxx CAN (WIN (C1CTR1<0>) = 0)
C2RXF5SID
OSCCON
CLKDIV
PLLFBD
OSCTUN
LFSR
0000000000000000 C2RXFUL1
0000000000000000 C2RXFUL2
0000000000000000 C2RXOVF1
0000000000000000 C2RXOVF2
0000000000000000 C2TR01CON
0000000000000000 C2TR23CON
0000000001000000 C2TR45CON
C2TR67CON
7A0
7A2
7A8
7AA
7B0
7B2
7B4
7B6
7C0
7C2
0000000000000000 C2RXF5EID
0000000000000000 C2RXF6SID
0000000000000000 C2RXF6EID
0000000000000000 C2RXF7SID
0000000000000000 C2RXF7EID
0000000000000000 C2RXF8SID
0000000000000000 C2RXF8EID
xxxxxxxxxxxxxxxx C2RXF9SID
xxxxxxxxxxxxxxxx C2RXF9EID
xxxxxxxxxxxxxxxx C2RXF10SID
REFOCON
ACLKCON
PMD
PMD1
760
762
764
766
76A
76C
76E
0000000000000000 C2RXD
0000000000000000 C2TXD
PMD2
PMD3
0000000000000000 CAN (WIN (C1CTR1<0>) = 1)
C2RXF10EID
PMD4
0000000000000000 C2BUFPNT1
0000000000000000 C2BUFPNT2
0000000000000000 C2BUFPNT3
0000000000000000 C2BUFPNT4
7A0
7A2
7A4
7A6
7B0
7B2
7B4
7B6
7B8
7BA
0000000000000000 C2RXF11SID
0000000000000000 C2RXF11EID
0000000000000000 C2RXF12SID
0000000000000000 C2RXF12EID
xxxxxxxxxxxxxxxx C2RXF13SID
xxxxxxxxxxxxxxxx C2RXF13EID
xxxxxxxxxxxxxxxx C2RXF14SID
xxxxxxxxxxxxxxxx C2RXF14EID
xxxxxxxxxxxxxxxx C2RXF15SID
xxxxxxxxxxxxxxxx C2RXF15EID
PMD6
PMD7
PMD8
CAN (WIN (C1CTR1<0>) = 0 or 1)
C2RXM0SID
C2CTRL1
C2CTRL2
C2VEC
780
782
784
786
788
0000010010000000 C2RXM0EID
0000000000000000 C2RXM1SID
0000000001000000 C2RXM1EID
0000000000000000 C2RXM2SID
0000000000000000 C2RXM2EID
C2FCTRL
C2FIFO
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
DS70005258C-page 46
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-10: SFR BLOCK 800h
Register
Address
All Resets
Register
IEC9
Address
All Resets
Register
Address
All Resets
Interrupt Controller
800
832
834
836
840
842
844
846
848
84A
84C
84E
850
852
856
858
85A
85C
860
864
86E
870
872
0000000000000000 IPC26
0000000000000000 IPC27
0000000000000000 IPC28
0100010001000100 IPC29
0100010001000000 IPC35
0100010001000100 IPC36
0100000001000100 IPC37
0100010001000100 IPC38
0000000000000100 IPC39
0100010001000000 IPC40
0100010001000100 IPC41
0000000001000100 IPC42
0000010001000000 IPC43
0000000000000000 IPC44
0000010001000000 IPC45
0000010000000000 IPC46
0000000001000000 IPC47
0000010001000000 INTCON1
0000000001000000 INTCON2
0100010000000000 INTCON3
0000010001000100 INTCON4
0100000000000000 INTTREG
874
876
878
87A
886
888
88A
88C
88E
890
892
894
896
898
89A
89C
89E
8C0
8C2
8C4
8C6
8C8
0000000001000100
0100010000000000
0100010001000100
0000000001000100
0100010000000000
0000000000000000
0100000000000000
0100010001000100
0100010001000100
0100010001000100
0100010001000100
0000000001000100
0000010001000000
0100010001000000
0000000000000100
0100010000000000
0000010001000100
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
IFS0
IFS1
IFS2
IFS3
IFS4
IFS5
IFS6
IFS7
IFS8
IFS9
IFS10
IFS11
IEC0
IEC1
IEC2
IEC3
IEC4
IEC5
IEC6
IEC7
IEC8
0000000000000000 IEC10
0000000000000000 IEC11
0000000000000000 IPC0
0000000000000000 IPC1
0000000000000000 IPC2
0000000000000000 IPC3
0000000000000000 IPC4
0000000000000000 IPC5
0000000000000000 IPC6
0000000000000000 IPC7
0000000000000000 IPC8
0000000000000000 IPC9
0000000000000000 IPC11
0000000000000000 IPC12
0000000000000000 IPC13
0000000000000000 IPC14
0000000000000000 IPC16
0000000000000000 IPC18
0000000000000000 IPC23
0000000000000000 IPC24
0000000000000000 IPC25
802
804
806
808
80A
80C
80E
810
812
814
816
820
822
824
826
828
82A
82C
82E
830
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
TABLE 4-11: SFR BLOCK 900h
Register
Address
All Resets
Register
OC3R
Address
All Resets
Register
Address
All Resets
Output Compare
OC1CON1
OC1CON2
OC1RS
91A
91C
91E
920
922
924
926
xxxxxxxxxxxxxxxx CLC2CONH
0000000000000000 CLC2SEL
0000000000000000 CLC2GLSL
0000000000001100 CLC2GLSH
xxxxxxxxxxxxxxxx CLC3CONL
xxxxxxxxxxxxxxxx CLC3CONH
0000000000000000 CLC3SEL
CLC3GLSL
9CE
9D0
9D4
9D6
9D8
9DA
9DC
9E0
9E2
9E4
9E6
9E8
9EC
9EE
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
900
902
904
906
908
90A
90C
90E
910
912
914
916
918
0000000000000000 OC3TMR
0000000000001100 OC4CON1
xxxxxxxxxxxxxxxx OC4CON2
xxxxxxxxxxxxxxxx OC4RS
0000000000000000 OC4R
OC1R
OC1TMR
OC2CON1
OC2CON2
OC2RS
0000000000000000 OC4TMR
0000000000001100 CLC
xxxxxxxxxxxxxxxx CLC1CONL
xxxxxxxxxxxxxxxx CLC1CONH
0000000000000000 CLC1SEL
0000000000000000 CLC1GLSL
0000000000001100 CLC1GLSH
xxxxxxxxxxxxxxxx CLC2CONL
9C0
9C2
9C4
9C8
9CA
9CC
0000000000000000 CLC3GLSH
0000000000000000 CLC4CONL
0000000000000000 CLC4CONH
0000000000000000 CLC4SEL
0000000000000000 CLC4GLSL
0000000000000000 CLC4GLSH
OC2R
OC2TMR
OC3CON1
OC3CON2
OC3RS
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
2016-2018 Microchip Technology Inc.
DS70005258C-page 47
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-12: SFR BLOCK A00h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
PTG
PTGADJ
AD2
AD4
AD6
AD8
ADA
ADC
ADE
AE0
AE2
AE4
0000000000000000 PTGQUE7
0000000000000000 PTGQUE8
0000000000000000 PTGQUE9
xxxxxxxxxxxxxxxx PTGQUE10
xxxxxxxxxxxxxxxx PTGQUE11
xxxxxxxxxxxxxxxx PTGQUE12
xxxxxxxxxxxxxxxx PTGQUE13
xxxxxxxxxxxxxxxx PTGQUE14
xxxxxxxxxxxxxxxx PTGQUE15
xxxxxxxxxxxxxxxx
AE6
AE8
AEA
AEC
AEE
AF0
AF2
AF4
AF6
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx
PTGCST
AC0
AC2
AC4
AC6
AC8
ACA
ACC
ACE
AD0
0000000000000000 PTGL0
PTGCON
PTGBTE
0000000000000000 PTGQPTR
0000000000000000 PTGQUE0
0000000000000000 PTGQUE1
0000000000000000 PTGQUE2
0000000000000000 PTGQUE3
0000000000000000 PTGQUE4
0000000000000000 PTGQUE5
0000000000000000 PTGQUE6
PTGHOLD
PTGT0LIM
PTGT1LIM
PTGSDLIM
PTGC0LIM
PTGC1LIM
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
TABLE 4-13: SFR BLOCK B00h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
DMA
DMA1STBL
B18
B1A
B1C
B1E
B20
B22
B24
B26
B28
B2A
B2C
B2E
B30
0000000000000000 DMA3REQ
0000000000000000 DMA3STAL
0000000000000000 DMA3STAH
0000000000000000 DMA3STBL
0000000000000000 DMA3STBH
0000000000000000 DMA3PAD
0000000000000000 DMA3CNT
0000000000000000 DMAPWC
0000000000000000 DMARQC
0000000000000000 DMAPPS
0000000000000000 DMALCA
0000000000000000 DSADRL
0000000000000000 DSADRH
B32
B34
B36
B38
B3A
B3C
B3E
BF0
BF2
BF4
BF6
BF8
BFA
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000001111
0000000000000000
0000000000000000
DMA0CON
DMA0REQ
DMA0STAL
DMA0STAH
DMA0STBL
DMA0STBH
DMA0PAD
DMA0CNT
DMA1CON
DMA1REQ
DMA1STAL
DMA1STAH
B00
B02
B04
B06
B08
B0A
B0C
B0E
B10
B12
B14
B16
0000000000000000 DMA1STBH
0000000000000000 DMA1PAD
0000000000000000 DMA1CNT
0000000000000000 DMA2CON
0000000000000000 DMA2REQ
0000000000000000 DMA2STAL
0000000000000000 DMA2STAH
0000000000000000 DMA2STBL
0000000000000000 DMA2STBH
0000000000000000 DMA2PAD
0000000000000000 DMA2CNT
0000000000000000 DMA3CON
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
DS70005258C-page 48
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 4-14: SFR BLOCK C00h-D00h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
PWM
FCLCON3
C64
C66
C68
C6A
C6C
C6E
C70
C72
C74
C76
C78
C7A
C7C
C7E
C80
C82
C84
C86
C88
C8A
C8C
C8E
C90
C92
C94
C96
C98
C9A
C9C
C9E
CA0
CA2
CA4
CA6
CA8
CAA
CAC
CAE
CB0
CB2
CB4
CB6
CB8
CBA
CBC
CBE
CC0
0000000000000000 IOCON6
0000000000000000 FCLCON6
0000000000000000 PDC6
0000000000000000 PHASE6
0000000000000000 DTR6
0000000000000000 ALTDTR6
0000000000000000 SDC6
0000000000000000 SPHASE6
0000000000000000 TRIG6
0000000000000000 TRGCON6
0000000000000000 STRIG6
0000000000000000 PWMCAP6
0000000000000000 LEBCON6
0000000000000000 LEBDLY6
0000000000000000 AUXCON6
1100000000000000 PWMCON7
0000000000000000 IOCON7
0000000000000000 FCLCON7
0000000000000000 PDC7
0000000000000000 PHASE7
0000000000000000 DTR7
0000000000000000 ALTDTR7
0000000000000000 SDC7
0000000000000000 SPHASE7
0000000000000000 TRIG7
0000000000000000 TRGCON7
0000000000000000 STRIG7
0000000000000000 PWMCAP7
0000000000000000 LEBCON7
0000000000000000 LEBDLY7
0000000000000000 AUXCON7
1100000000000000 PWMCON8
0000000000000000 IOCON8
0000000000000000 FCLCON8
0000000000000000 PDC8
0000000000000000 PHASE8
0000000000000000 ALTDTR8
0000000000000000 SDC8
0000000000000000 SPHASE8
0000000000000000 TRIG8
0000000000000000 TRGCON8
0000000000000000 STRIG8
0000000000000000 PWMCAP8
0000000000000000 LEBCON8
0000000000000000 LEBDLY8
0000000000000000 AUXCON8
0000000000000000
CC2
CC4
CC6
CC8
CCA
CCC
CCE
CD0
CD2
CD4
CD6
CD8
CDA
CDC
CDE
CE0
CE2
CE4
CE6
CE8
CEA
CEC
CEE
CF0
CF2
CF4
CF6
CF8
CFA
CFC
CFE
D00
D02
D04
D06
D08
D0C
D0E
D10
D12
D14
D16
D18
D1A
D1C
D1E
1100000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
1100000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
1100000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
PTCON
C00
C02
C04
C06
C0A
C0E
C10
C12
C14
C1A
C1E
0000000000000000 PDC3
0000000000000000 PHASE3
1111111111111000 DTR3
0000000000000000 ALTDTR3
0000000000000000 SDC3
0000000000000000 SPHASE3
0000000000000000 TRIG3
1111111111111000 TRGCON3
0000000000000000 STRIG3
0000000000000000 PWMCAP3
xxxxxxxxxxxxxxxx LEBCON3
LEBDLY3
PTCON2
PTPER
SEVTCMP
MDC
STCON
STCON2
STPER
SSEVTCMP
CHOP
PWMKEY
PWM Generator
PWMCON1
IOCON1
FCLCON1
PDC1
C20
C22
C24
C26
C28
C2A
C2C
C2E
C30
C32
C34
C36
C38
C3A
C3C
C3E
C40
C42
C44
C46
C48
C4A
C4C
C4E
C50
C52
C54
C56
C58
C5A
C5C
C5E
C60
C62
0000000000000000 AUXCON3
1100000000000000 PWMCON4
0000000000000000 IOCON4
0000000000000000 FCLCON4
0000000000000000 PDC4
0000000000000000 PHASE4
0000000000000000 DTR4
0000000000000000 ALTDTR4
0000000000000000 SDC4
0000000000000000 SPHASE4
0000000000000000 TRIG4
0000000000000000 TRGCON4
0000000000000000 STRIG4
0000000000000000 PWMCAP4
0000000000000000 LEBCON4
0000000000000000 LEBDLY4
0000000000000000 AUXCON4
1100000000000000 PWMCON5
0000000000000000 IOCON5
0000000000000000 FCLCON5
0000000000000000 PDC5
0000000000000000 PHASE5
0000000000000000 DTR5
0000000000000000 ALTDTR5
0000000000000000 SDC5
0000000000000000 SPHASE5
0000000000000000 TRIG5
0000000000000000 TRGCON5
0000000000000000 STRIG5
0000000000000000 PWMCAP5
0000000000000000 LEBCON5
0000000000000000 LEBDLY5
0000000000000000 AUXCON5
1100000000000000 PWMCON6
PHASE1
DTR1
ALTDTR1
SDC1
SPHASE1
TRIG1
TRGCON1
STRIG1
PWMCAP1
LEBCON1
LEBDLY1
AUXCON1
PWMCON2
IOCON2
FCLCON2
PDC2
PHASE2
DTR2
ALTDTR2
SDC2
SPHASE2
TRIG2
TRGCON2
STRIG2
PWMCAP2
LEBCON2
LEBDLY2
AUXCON2
PWMCON3
IOCON3
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
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TABLE 4-15: SFR BLOCK E00h-F00h
Register
Address
All Resets
Register
Address
All Resets
Register
Address
All Resets
PORTA
ANSELB
E1E
0000001011101111 CNPDD
ANSELD
E3C
E3E
0000000000000000
0010000110100100
TRISA
PORTA
LATA
E00
E02
E04
E06
E08
E0A
E0C
E0E
0000000000011111 PORTC
0000000000000000 TRISC
0000000000000000 PORTC
0000000000000000 LATC
0000000000000000 ODCC
0000000000000000 CNENC
0000000000000000 CNPUC
0000000000000111 CNPDC
ANSELC
E20
E22
E24
E26
E28
E2A
E2C
E2E
1111011111111111 PORTE
0000000000000000 TRISE
0000000000000000 PORTE
0000000000000000 LATE
0000000000000000 ODCE
0000000000000000 CNENE
0000000000000000 CNPUE
0001011001110110 CNPDE
ANSELE
E40
E42
E44
E46
E48
E4A
E4C
E4E
1111111111111111
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
0000000000000000
ODCA
CNENA
CNPUA
CNPDA
ANSELA
PORTB
TRISB
E10
E12
E14
E16
E18
E1A
E1C
1111101111111111 PORTD
0000000000000000 TRISD
0000000000000000 PORTD
0000000000000000 LATD
0000000000000000 ODCD
0000000000000000 CNEND
0000000000000000 CNPUD
PORTB
LATB
E30
E32
E34
E36
E38
E3A
1111111111111111 CPU
0000000000000000 VISI
0000000000000000 JTAG
0000000000000000 JDATAH
0000000000000000 JDATAL
0000000000000000
F88
0000000000000000
ODCB
CNENB
CNPUB
CNPDB
FF0
FF2
0000000000000000
0000000000000000
Legend: x= unknown or indeterminate value. Address values are in hexadecimal. Reset values are in binary.
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dsPIC33EPXXXGS70X/80X FAMILY
The paged memory scheme provides access to
multiple 32-Kbyte windows in the PSV memory. The
Data Space Read Page (DSRPAG) register, in combi-
nation with the upper half of the Data Space address,
can provide up to 8 Mbytes of PSV address space. The
paged data memory space is shown in Figure 4-8.
4.5.1
PAGED MEMORY SCHEME
The dsPIC33EPXXXGS70X/80X family architecture
extends the available Data Space through a paging
scheme, which allows the available Data Space to be
accessed using MOV instructions in a linear fashion for
pre- and post-modified Effective Addresses (EAs).
The upper half of the base Data Space address is
used in conjunction with the Data Space Read Page
(DSRPAG) register to form the Program Space
Visibility (PSV) address.
The Program Space (PS) can be accessed with a
DSRPAG of 0x200 or greater. Only reads from PS are
supported using the DSRPAG register.
The Data Space Read Page (DSRPAG) register is
located in the SFR space. Construction of the PSV
address is shown in Figure 4-7. When DSRPAG<9> = 1
and the base address bit, EA<15>
= 1, the
DSRPAG<8:0> bits are concatenated onto EA<14:0>
to form the 24-bit PSV read address.
FIGURE 4-7:
PROGRAM SPACE VISIBILITY (PSV) READ ADDRESS GENERATION
Byte
Select
16-Bit DS EA
EA<15> = 0
(DSRPAG = don’t care)
0
EA
EA
No EDS Access
EA<15>
DSRPAG<9>
1
= 1
Select
DSRPAG
Generate
PSV Address
1
DSRPAG<8:0>
9 Bits
15 Bits
24-Bit PSV EA
Byte
Select
Note: DS read access when DSRPAG = 0x000 will force an address error trap.
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When a PSV page overflow or underflow occurs,
address within the PSV window. This creates a linear
PSV address space, but only when using Register
Indirect Addressing modes.
EA<15> is cleared as a result of the register indirect EA
calculation. An overflow or underflow of the EA in the
PSV pages can occur at the page boundaries when:
Exceptions to the operation described above arise
when entering and exiting the boundaries of Page 0
and PSV spaces. Table 4-16 lists the effects of overflow
and underflow scenarios at different boundaries.
• The initial address, prior to modification,
addresses the PSV page
• The EA calculation uses Pre- or Post-Modified
Register Indirect Addressing; however, this does
not include Register Offset Addressing
In the following cases, when overflow or underflow
occurs, the EA<15> bit is set and the DSRPAG is not
modified; therefore, the EA will wrap to the beginning of
the current page:
In general, when an overflow is detected, the DSRPAG
register is incremented and the EA<15> bit is set to keep
the base address within the PSV window. When an
underflow is detected, the DSRPAG register is decre-
mented and the EA<15> bit is set to keep the base
• Register Indirect with Register Offset Addressing
• Modulo Addressing
• Bit-Reversed Addressing
TABLE 4-16: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0 AND
PSV SPACE BOUNDARIES(2,3,4)
Before
After
O/U,
R/W
Operation
DS
EA<15>
Page
Description
DS
EA<15>
Page
Description
DSxPAG
DSxPAG
O,
Read
DSRPAG = 0x2FF
1
1
1
1
1
PSV: Last lsw
page
DSRPAG = 0x300
1
0
0
0
1
PSV: First MSB
page
[++Wn]
or
[Wn++]
O,
Read
DSRPAG = 0x3FF
DSRPAG = 0x001
DSRPAG = 0x200
DSRPAG = 0x300
PSV: Last MSB DSRPAG = 0x3FF
page
See Note 1
See Note 1
See Note 1
U,
Read
PSV page
DSRPAG = 0x001
[--Wn]
or
[Wn--]
U,
Read
PSV: First lsw
page
DSRPAG = 0x200
U,
Read
PSV: First MSB DSRPAG = 0x2FF
page
PSV: Last lsw
page
Legend: O = Overflow, U = Underflow, R = Read, W = Write
Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x7FFF).
2: An EDS access, with DSRPAG = 0x000, will generate an address error trap.
3: Only reads from PS are supported using DSRPAG.
4: Pseudolinear Addressing is not supported for large offsets.
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The Software Stack Pointer always points to the first
available free word and fills the software stack, work-
ing from lower toward higher addresses. Figure 4-9
illustrates how it pre-decrements for a stack pop
(read) and post-increments for a stack push (writes).
4.5.2
EXTENDED X DATA SPACE
The lower portion of the base address space range,
between 0x0000 and 0x7FFF, is always accessible,
regardless of the contents of the Data Space Read
Page register. It is indirectly addressable through the
register indirect instructions. It can be regarded as
being located in the default EDS Page 0 (i.e., EDS
address range of 0x000000 to 0x007FFF with the base
address bit, EA<15> = 0, for this address range). How-
ever, Page 0 cannot be accessed through the upper
32 Kbytes, 0x8000 to 0xFFFF, of base Data Space in
combination with DSRPAG = 0x000. Consequently,
DSRPAG is initialized to 0x001 at Reset.
When the PC is pushed onto the stack, PC<15:0> are
pushed onto the first available stack word, then
PC<22:16> are pushed into the second available stack
location. For a PC push during any CALL instruction,
the MSB of the PC is zero-extended before the push,
as shown in Figure 4-9. During exception processing,
the MSB of the PC is concatenated with the lower eight
bits of the CPU STATUS Register, SR. This allows the
contents of SRL to be preserved automatically during
interrupt processing.
Note 1: DSRPAG should not be used to access
Page 0. An EDS access with DSRPAG
set to 0x000 will generate an address
error trap.
Note 1: To maintain system Stack Pointer (W15)
coherency, W15 is never subject to
(EDS) paging, and is therefore, restricted
to an address range of 0x0000 to
0xFFFF. The same applies to W14 when
used as a Stack Frame Pointer (SFA = 1).
2: Clearing the DSRPAG in software has no
effect.
The remaining PSV pages are only accessible using
the DSRPAG register in combination with the upper
32 Kbytes, 0x8000 to 0xFFFF, of the base address,
where base address bit, EA<15> = 1.
2: As the stack can be placed in, and can
access X and Y spaces, care must be
taken regarding its use, particularly with
regard to local automatic variables in a C
development environment
4.5.3
SOFTWARE STACK
The W15 register serves as a dedicated Software
Stack Pointer (SSP), and is automatically modified by
exception processing, subroutine calls and returns;
however, W15 can be referenced by any instruction in
the same manner as all other W registers. This simpli-
fies reading, writing and manipulating the Stack Pointer
(for example, creating stack frames).
FIGURE 4-9:
CALL STACK FRAME
0x0000
15
0
CALL SUBR
Note: To protect against misaligned stack
accesses, W15<0> is fixed to ‘0’ by the
hardware.
PC<15:1>
W15 (before CALL)
W15 (after CALL)
b‘000000000’
PC<22:16>
<Free Word>
W15 is initialized to 0x1000 during all Resets. This
address ensures that the SSP points to valid RAM in all
dsPIC33EPXXXGS70X/80X devices and permits stack
availability for non-maskable trap exceptions. These can
occur before the SSP is initialized by the user software.
You can reprogram the SSP during initialization to any
location within Data Space.
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4.6.2
MCU INSTRUCTIONS
4.6
Instruction Addressing Modes
The three-operand MCU instructions are of the form:
The addressing modes shown in Table 4-17 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The address-
ing modes provided in the MACclass of instructions differ
from those in the other instruction types.
Operand 3 = Operand 1 <function> Operand 2
where Operand 1is always a Working register (that is,
the addressing mode can only be Register Direct),
which is referred to as Wb. Operand 2 can be a W
register fetched from data memory or a 5-bit literal. The
result location can either be a W register or a data
memory location. The following addressing modes are
supported by MCU instructions:
4.6.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field (f)
to directly address data present in the first 8192 bytes
of data memory (Near Data Space). Most file register
instructions employ a Working register, W0, which is
denoted as WREG in these instructions. The destina-
tion is typically either the same file register or WREG
(with the exception of the MULinstruction), which writes
the result to a register or register pair. The MOVinstruc-
tion allows additional flexibility and can access the
entire Data Space.
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-Bit or 10-Bit Literal
Note:
Not all instructions support all the
addressing modes given above. Individ-
ual instructions can support different
subsets of these addressing modes.
TABLE 4-17: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode Description
File Register Direct
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn form the Effective Address (EA).
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn form the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
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4.6.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
4.6.4
MACINSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also referred
to as MACinstructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the Data Pointers through register indirect
tables.
Move instructions, and the DSP accumulator class
of instructions, provide a greater degree of address-
ing flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The Effective Addresses generated (before and after
modification) must therefore, be valid addresses within
X Data Space for W8 and W9, and Y Data Space for
W10 and W11.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA. How-
ever, the 4-bit Wb (Register Offset) field is
shared by both source and destination (but
typically only used by one).
Note:
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by move and accumulator instructions:
In summary, the following addressing modes are
• Register Direct
supported by the MACclass of instructions:
• Register Indirect
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-Bit Literal
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
• 16-Bit Literal
4.6.5
OTHER INSTRUCTIONS
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions may support different subsets
of these addressing modes.
Besides the addressing modes outlined previously,
some instructions use literal constants of various sizes.
For example, BRA (branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the DISI instruction uses a 14-bit unsigned
literal field. In some instructions, such as ULNK, the
source of an operand or result is implied by the opcode
itself. Certain operations, such as a NOP, do not have
any operands.
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4.7.1
START AND END ADDRESS
4.7
Modulo Addressing
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-2).
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
Note:
Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
Modulo Addressing can operate in either Data or
Program Space (since the Data Pointer mechanism is
essentially the same for both). One circular buffer can be
supported in each of the X (which also provides the point-
ers into Program Space) and Y Data Spaces. Modulo
Addressing can operate on any W Register Pointer. How-
ever, it is not advisable to use W14 or W15 for Modulo
Addressing since these two registers are used as the
Stack Frame Pointer and Stack Pointer, respectively.
The length of a circular buffer is not directly specified. It is
determined by the difference between the corresponding
start and end addresses. The maximum possible length of
the circular buffer is 32K words (64 Kbytes).
4.7.2
W ADDRESS REGISTER SELECTION
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags, as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that
operate with Modulo Addressing:
In general, any particular circular buffer can be config-
ured to operate in only one direction, as there are certain
restrictions on the buffer start address (for incrementing
buffers) or end address (for decrementing buffers),
based upon the direction of the buffer.
• If XWM = 1111, X RAGU and X WAGU Modulo
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a Bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
Addressing is disabled
• If YWM = 1111, Y AGU Modulo Addressing is
disabled
The X Address Space Pointer W (XWM) register, to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-2). Modulo Addressing is
enabled for X Data Space when XWM is set to any
value other than ‘1111’ and the XMODEN bit is set
(MODCON<15>).
The Y Address Space Pointer W (YWM) register, to
which Modulo Addressing is to be applied, is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
Data Space when YWM is set to any value other than
‘1111’ and the YMODEN bit (MODCON<14>) is set.
FIGURE 4-10:
MODULO ADDRESSING OPERATION EXAMPLE
Byte
Address
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
0x1100
MOV
MOV
#0x0000, W0
#0x1110, W1
0x1163
DO
MOV
AGAIN, #0x31
W0, [W1++]
;fill the 50 buffer locations
;fill the next location
AGAIN: INC W0, W0
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
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4.7.3
MODULO ADDRESSING
APPLICABILITY
4.8.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
Bit-Reversed Addressing mode is enabled when all of
these situations are met:
• BWMx bits (W register selection) in the MODCON
register are any value other than ‘1111’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can therefore, jump beyond
boundaries and still be adjusted correctly.
XB<14:0> is the Bit-Reversed Addressing modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
Note:
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the Effective
Address. When an address offset (such as
[W7 + W2]) is used, Modulo Addressing
correction is performed, but the contents of
the register remain unchanged.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
does not function for any other addressing mode or for
byte-sized data and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB) and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
4.8
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
Note:
Modulo Addressing and Bit-Reversed
Addressing can be enabled simultaneously
using the same W register, but Bit-
Reversed Addressing operation will always
take precedence for data writes when
enabled.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the Bit-Reversed Pointer.
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FIGURE 4-11:
BIT-REVERSED ADDRESSING EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-18: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
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Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
4.9
Interfacing Program and Data
Memory Spaces
The dsPIC33EPXXXGS70X/80X family architecture
uses a 24-bit wide Program Space (PS) and a 16-bit
wide Data Space (DS). The architecture is also a
modified Harvard scheme, meaning that data can also
be present in the Program Space. To use this data
successfully, it must be accessed in a way that preserves
the alignment of information in both spaces.
Aside from normal execution, the architecture of the
dsPIC33EPXXXGS70X/80X family devices provides
two methods by which Program Space can be
accessed during operation:
• Using table instructions to access individual bytes
or words anywhere in the Program Space
• Remapping a portion of the Program Space into
the Data Space (Program Space Visibility)
TABLE 4-19: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xxx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
FIGURE 4-12:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter
23 Bits
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 Bits
16 Bits
24 Bits
User/Configuration
Space Select
Byte Select
Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain
word alignment of data in the Program and Data Spaces.
2: Table operations are not required to be word-aligned. Table Read operations are permitted in the
configuration memory space.
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• TBLRDH (Table Read High):
4.9.1
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
(D<15:8>) is always ‘0’.
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the Program Space without going
through Data Space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper eight bits of a Program Space word as data.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address in the TBLRDL instruc-
tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to Data Space addresses.
Program memory can thus be regarded as two 16-bit
wide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDHand TBLWTHaccess the space that
contains the upper data byte.
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a Program Space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user application
and configuration spaces. When TBLPAG<7> = 0, the
table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from Program Space.
Both function as either byte or word operations.
• TBLRDL(Table Read Low):
- In Word mode, this instruction maps the lower
word of the Program Space location (P<15:0>)
to a data address (D<15:0>)
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
FIGURE 4-13:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
00000000
0x020000
0x030000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
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NOTES:
DS70005258C-page 62
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manufacture boards with unprogrammed devices and
5.0
FLASH PROGRAM MEMORY
then program the device just before shipping the
product. This also allows the most recent firmware or a
custom firmware to be programmed.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Dual Partition Flash Program
Memory” (DS70005156) in the “dsPIC33/
PIC24 Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com)
Enhanced In-Circuit Serial Programming uses an
on-board bootloader, known as the Program Executive,
to manage the programming process. Using an SPI data
frame format, the Program Executive can erase,
program and verify program memory. For more informa-
tion on Enhanced ICSP, see the device programming
specification.
RTSP is accomplished using TBLRD(Table Read) and
TBLWT(Table Write) instructions. With RTSP, the user
application can write program memory data with a
single program memory word and erase program mem-
ory in blocks or ‘pages’ of 512 instructions (1536 bytes)
at a time.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
5.1
Table Instructions and Flash
Programming
The dsPIC33EPXXXGS70X/80X family devices contain
internal Program Flash Memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Regardless of the method used, all programming of
Flash memory is done with the Table Read and Table
Write instructions. These instructions allow direct read
and write access to the program memory space, from
the data memory, while the device is in normal operating
mode. The 24-bit target address in the program memory
is formed using bits<7:0> of the TBLPAG register and
the Effective Address (EA) from a W register, specified
in the table instruction, as shown in Figure 5-1. The
TBLRDLand the TBLWTLinstructions are used to read or
write to bits<15:0> of program memory. TBLRDL and
TBLWTLcan access program memory in both Word and
Byte modes. The TBLRDHand TBLWTHinstructions are
used to read or write to bits<23:16> of program memory.
TBLRDHand TBLWTHcan also access program memory
in Word or Byte mode.
Flash memory can be programmed in three ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
• Enhanced In-Circuit Serial Programming
(Enhanced ICSP)
• Run-Time Self-Programming (RTSP)
ICSP allows for a dsPIC33EPXXXGS70X/80X family
device to be serially programmed while in the end
application circuit. This is done with a programming
clock and programming data (PGECx/PGEDx) line,
and three other lines for power (VDD), ground (VSS) and
Master Clear (MCLR). This allows customers to
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 Bits
16 Bits
User/Configuration
Space Select
Byte
Select
24-Bit EA
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FIGURE 5-2:
UNCOMPRESSED/
COMPRESSED FORMAT
5.2
RTSP Operation
The dsPIC33EPXXXGS70X/80X family Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user application to erase
a single page (8 rows or 512 instructions) of memory at
a time and to program one row at a time. It is possible
to program two instructions at a time as well.
15
7
0
Even Byte
Address
LSW1
LSW2
0x00
MSB1
MSB2
The page erase and single row write blocks are
edge-aligned, from the beginning of program
memory, on boundaries of 1536 bytes and 192 bytes,
respectively. Figure 30-14 in Section 30.0 “Electrical
Characteristics” lists the typical erase and
programming times.
0x00
UNCOMPRESSED FORMAT (RPDF = 0)
Row programming is performed by loading 192 bytes
into data memory and then loading the address of the
first byte in that row into the NVMSRCADR register.
Once the write has been initiated, the device will
automatically load the write latches and increment the
NVMSRCADR and the NVMADR(U) registers until
all bytes have been programmed. The RPDF bit
(NVMCON<9>) selects the format of the stored data in
RAM to be either compressed or uncompressed. See
Figure 5-2 for data formatting. Compressed data helps
to reduce the amount of required RAM by using the
upper byte of the second word for the MSB of the
second instruction.
15
7
0
Even Byte
Address
LSW1
MSB2
MSB1
LSW2
COMPRESSED FORMAT (RPDF = 1)
5.3
Programming Operations
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the program-
ming operation is finished. Setting the WR bit
(NVMCON<15>) starts the operation and the WR bit is
automatically cleared when the operation is finished.
The basic sequence for RTSP word programming is to
use the TBLWTLand TBLWTHinstructions to load two of
the 24-bit instructions into the write latches found in
configuration memory space. Refer to Figure 4-1
through Figure 4-4 for write latch addresses. Program-
ming is performed by unlocking and setting the control
bits in the NVMCON register.
5.3.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
All erase and program operations may optionally use
the NVM interrupt to signal the successful completion
of the operation. For example, when performing Flash
write operations on the Inactive Partition in Dual
Partition mode, where the CPU remains running, it is
necessary to wait for the NVM interrupt before
programming the next block of Flash program memory.
Programmers can program two adjacent words
(24 bits x 2) of Program Flash Memory at a time on
every other word address boundary (0x000000,
0x000004, 0x000008, etc.). To do this, it is necessary to
erase the page that contains the desired address of the
location the user wants to change. For protection against
accidental operations, the write initiate sequence for
NVMKEY must be used to allow any erase or program
operation to proceed. After the programming command
has been executed, the user application must wait for
the programming time until programming is complete.
The two instructions following the start of the
programming sequence should be NOPs.
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For robustness of operation, in order to execute the
BOOTSWP instruction, it is necessary to execute the
5.4
Dual Partition Flash Configuration
For dsPIC33EPXXXGS70X/80X devices operating in
Dual Partition Flash Program Memory modes, the
Inactive Partition can be erased and programmed with-
out stalling the processor. The same programming
algorithms are used for programming and erasing the
Flash in the Inactive Partition, as described in
Section 5.2 “RTSP Operation”. On top of the page
erase option, the entire Flash memory of the Inactive
Partition can be erased by configuring the
NVMOP<3:0> bits in the NVMCON register.
NVM unlocking sequence as follows:
1. Write 0x55 to NVMKEY.
2. Write 0xAA to NVMKEY.
3. Execute the BOOTSWPinstruction.
If the unlocking sequence is not performed, the
BOOTSWPinstruction will be executed as a forced NOP
and a GOTOinstruction, following the BOOTSWPinstruc-
tion, will be executed, causing the PC to jump to that
location in the current operating partition.
Note 1: The application software to be loaded
into the Inactive Partition will have the
address of the Active Partition. The
bootloader firmware will need to offset
the address by 0x400000 in order to write
to the Inactive Partition.
The SFTSWP and P2ACTIV bits in the NVMCON
register are used to determine a successful swap of the
Active and Inactive Partitions, as well as which partition
is active. After the BOOTSWPand GOTO instructions, the
SFTSWP bit should be polled to verify the partition
swap has occurred and then cleared for the next panel
swap event.
5.4.1
FLASH PARTITION SWAPPING
5.4.2
DUAL PARTITION MODES
The Boot Sequence Number is used for determining
the Active Partition at start-up and is encoded within
the FBTSEQ Configuration register bits. Unlike most
Configuration registers, which only utilize the lower
16 bits of the program memory, FBTSEQ is a 24-bit
Configuration Word. The Boot Sequence Number
(BSEQ) is a 12-bit value and is stored in FBTSEQ
twice. The true value is stored in bits, FBTSEQ<11:0>,
and its complement is stored in bits, FBTSEQ<23:12>.
At device Reset, the sequence numbers are read and
the partition with the lowest sequence number
becomes the Active Partition. If one of the Boot
Sequence Numbers is invalid, the device will select the
partition with the valid Boot Sequence Number, or
default to Partition 1 if both sequence numbers are
invalid. See Section 27.0 “Special Features” for more
information.
While operating in Dual Partition mode, the
dsPIC33EPXXXGS70X/80X family devices have the
option for both partitions to have their own defined
security segments, as shown in Figure 27-4. Alterna-
tively, the device can operate in Protected Dual Partition
mode, where Partition 1 becomes permanently erase/
write-protected. Protected Dual Partition mode allows for
a “Factory Default” mode, which provides a fail-safe
backup image to be stored in Partition 1.
dsPIC33EPXXXGS70X/80X family devices can also
operate in Privileged Dual Partition mode, where addi-
tional security protections are implemented to allow for
protection of intellectual property when multiple parties
have software within the device. In Privileged Dual Par-
tition mode, both partitions place additional restrictions
on the FBSLIM register. These prevent changes to the
size of the Boot Segment and General Segment,
ensuring that neither segment will be altered.
The BOOTSWP instruction provides an alternative
means of swapping the Active and Inactive Partitions
(soft swap) without the need for a device Reset. The
BOOTSWPmust always be followed by a GOTOinstruc-
tion. The BOOTSWP instruction swaps the Active and
Inactive Partitions, and the PC vectors to the location
specified by the GOTO instruction in the newly Active
Partition.
5.5
Flash Memory Resources
Many useful resources are provided on the main
product page of the Microchip website for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
It is important to note that interrupts should temporarily
be disabled while performing the soft swap sequence
and that after the partition swap, all peripherals and
interrupts which were enabled remain enabled. Addi-
tionally, the RAM and stack will maintain state after the
switch. As a result, it is recommended that applications
using soft swaps jump to a routine that will reinitialize
the device in order to ensure the firmware runs as
expected. The Configuration registers will have no
effect during a soft swap.
5.5.1
KEY RESOURCES
• “Dual Partition Flash Program Memory”
(DS70005156) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
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There are two NVM Address registers: NVMADRU and
NVMADR. These two registers, when concatenated,
form the 24-bit Effective Address (EA) of the selected
word/row for programming operations, or the selected
page for erase operations. The NVMADRU register is
used to hold the upper eight bits of the EA, while the
NVMADR register is used to hold the lower 16 bits of
the EA.
5.6
Control Registers
Five SFRs are used to write and erase the Program
Flash Memory: NVMCON, NVMKEY, NVMADR,
NVMADRU and NVMSRCADR/H.
The NVMCON register (Register 5-1) selects the
operation to be performed (page erase, word/row
program, Inactive Partition erase), initiates the program
or erase cycle and is used to determine the Active
Partition in Dual Partition modes.
For row programming operation, data to be written to
Program Flash Memory is written into data memory
space (RAM) at an address defined by the
NVMSRCADR register (location of first element in row
programming data).
NVMKEY (Register 5-4) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must
consecutively write 0x55 and 0xAA to the NVMKEY
register.
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REGISTER 5-1:
NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER
R/SO-0(1)
WR
R/W-0(1)
WREN
R/W-0(1)
WRERR NVMSIDL(2) SFTSWP(6)
R/W-0
R/C-0
R-0
P2ACTIV(6)
R/W-0
RPDF
R/C-0
URERR
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP3(3,4) NVMOP2(3,4) NVMOP1(3,4) NVMOP0(3,4)
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
SO = Settable Only bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
WR: Write Control bit(1)
1= Initiates a Flash Memory Program or erase operation; the operation is self-timed and the bit is
cleared by hardware once the operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit(1)
1= Enables Flash program/erase operations
0= Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit(1)
1= An improper program or erase sequence attempt, or termination has occurred (bit is set automatically
on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12
bit 11
NVMSIDL: NVM Stop in Idle Control bit(2)
1= Flash voltage regulator goes into Standby mode during Idle mode
0= Flash voltage regulator is active during Idle mode
SFTSWP: Partition Soft Swap Status bit(6)
1= Partitions have been successfully swapped using the BOOTSWPinstruction (soft swap)
0= Awaiting successful partition swap using the BOOTSWPinstruction or a device Reset will determine
the Active Partition based on the FBTSEQ register
bit 10
bit 9
P2ACTIV: Partition 2 Active Status bit(6)
1= Partition 2 Flash is mapped into the active region
0= Partition 1 Flash is mapped into the active region
RPDF: Row Programming Data Format bit
1= Row data to be stored in RAM is in compressed format
0= Row data to be stored in RAM is in uncompressed format
Note 1: These bits can only be reset on a POR.
2: If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAVinstruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: Only applicable when operating in Dual Partition mode.
7: The specific Boot mode depends on bits<1:0> of the programmed data:
11= Single Partition Flash mode
10= Dual Partition Flash mode
01= Protected Dual Partition Flash mode
00= Reserved
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REGISTER 5-1:
NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)
bit 8
URERR: Row Programming Data Underrun Error bit
1= Indicates row programming operation has been terminated
0= No data underrun error is detected
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(1,3,4)
1111= Reserved
1110= User memory bulk erase operation
1011= Reserved
1010= Reserved
1001= Reserved
1000= Boot memory double-word program operation in a Dual Partition Flash mode(7)
0101= Reserved
0100= Inactive Partition memory erase operation
0011= Memory page erase operation
0010= Memory row program operation
0001= Memory double-word program operation(5)
0000= Reserved
Note 1: These bits can only be reset on a POR.
2: If this bit is set, power consumption will be further reduced (IIDLE) and upon exiting Idle mode, there is a
delay (TVREG) before Flash memory becomes operational.
3: All other combinations of NVMOP<3:0> are unimplemented.
4: Execution of the PWRSAVinstruction is ignored while any of the NVM operations are in progress.
5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.
6: Only applicable when operating in Dual Partition mode.
7: The specific Boot mode depends on bits<1:0> of the programmed data:
11= Single Partition Flash mode
10= Dual Partition Flash mode
01= Protected Dual Partition Flash mode
00= Reserved
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REGISTER 5-2:
NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
NVMADR<15:8>
bit 15
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
NVMADR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
NVMADR<15:0>: Nonvolatile Memory Lower Write Address bits
Selects the lower 16 bits of the location to program or erase in Program Flash Memory. This register
may be read or written to by the user application.
REGISTER 5-3:
NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
NVMADRU<23:16>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMADRU<23:16>: Nonvolatile Memory Upper Write Address bits
Selects the upper eight bits of the location to program or erase in Program Flash Memory. This register
may be read or written to by the user application.
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 5-4:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
W-0
bit 7
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMKEY<7:0>: NVM Key Register bits (write-only)
REGISTER 5-5:
NVMSRCADR: NVM SOURCE DATA ADDRESS REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
NVMSRCADR<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NVMSRCADR<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
NVMSRCADR<15:0>: NVM Source Data Address bits
The RAM address of the data to be programmed into Flash when the NVMOP<3:0> bits are set to row
programming.
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dsPIC33EPXXXGS70X/80X FAMILY
A simplified block diagram of the Reset module is
shown in Figure 6-1.
6.0
RESETS
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to “Reset” (DS70602) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com)
Any active source of Reset will make the SYSRST
signal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state, and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 4.0 “Memory Organization” of
this data sheet for register Reset states.
All types of device Reset set a corresponding status bit
in the RCON register to indicate the type of Reset (see
Register 6-1).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A POR clears all the bits, except for the BOR and POR
bits (RCON<1:0>) that are set. The user application
can set or clear any bit, at any time, during code
execution. The RCON bits only serve as status bits.
Setting a particular Reset status bit in software does
not cause a device Reset to occur.
The Reset module combines all Reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
• POR: Power-on Reset
• BOR: Brown-out Reset
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
• WDTO: Watchdog Timer Time-out Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
• IOPUWR: Illegal Condition Device Reset
- Illegal Opcode Reset
For all Resets, the default clock source is determined
by the FNOSC<2:0> bits in the FOSCSEL Configura-
tion register. The value of the FNOSCx bits is loaded
into the NOSC<2:0> (OSCCON<10:8>) bits on Reset,
which in turn, initializes the system clock.
- Uninitialized W Register Reset
- Security Reset
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESET Instruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Security Reset
Configuration Mismatch
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
6.1.1
KEY RESOURCES
6.1
Reset Resources
• “Reset” (DS70602) in the “dsPIC33/PIC24 Family
Reference Manual”
Many useful resources are provided on the main
product page of the Microchip website for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005258C-page 72
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1)
R/W-0
TRAPR
bit 15
R/W-0
U-0
—
U-0
—
R/W-0
U-0
—
R/W-0
CM
R/W-0
IOPUWR
VREGSF
VREGS
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or Uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or Uninitialized W register Reset has not occurred
bit 13-12
bit 11
Unimplemented: Read as ‘0’
VREGSF: Flash Voltage Regulator Standby During Sleep bit
1= Flash voltage regulator is active during Sleep
0= Flash voltage regulator goes into Standby mode during Sleep
bit 10
bit 9
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1= A Configuration Mismatch Reset has occurred
0= A Configuration Mismatch Reset has not occurred
bit 8
bit 7
bit 6
bit 5
bit 4
VREGS: Voltage Regulator Standby During Sleep bit
1= Voltage regulator is active during Sleep
0= Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software RESET(Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.
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REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 3
bit 2
bit 1
bit 0
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device has been in Idle mode
0= Device has not been in Idle mode
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
POR: Power-on Reset Flag bit
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless
of the SWDTEN bit setting.
DS70005258C-page 74
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
7.0
INTERRUPT CONTROLLER
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to “Interrupts” (DS70000600)
in the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
The Alternate Interrupt Vector Table (AIVT), shown in
Figure 7-2, is available only when the Boot Segment is
defined and the AIVT has been enabled. To enable the
Alternate Interrupt Vector Table, the Configuration bit,
AIVTDIS in the FSEC register, must be programmed
and the AIVTEN bit must be set (INTCON2<8> = 1).
When the AIVT is enabled, all interrupt and exception
processes use the alternate vectors instead of the
default vectors. The AIVT begins at the start of the last
page of the Boot Segment, defined by BSLIM<12:0>.
The second half of the page is no longer usable space.
The Boot Segment must be at least two pages to
enable the AIVT.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note: Although the Boot Segment must be
enabled in order to enable the AIVT,
application code does not need to be
present inside of the Boot Segment. The
AIVT (and IVT) will inherit the Boot
Segment code protection.
The dsPIC33EPXXXGS70X/80X family interrupt
controller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the dsPIC33EPXXXGS70X/80X family CPU.
The interrupt controller has the following features:
The AIVT supports debugging by providing a means to
switch between an application and a support environ-
ment without requiring the interrupt vectors to be
reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time.
• Six Processor Exceptions and Software Traps
• Seven User-Selectable Priority Levels
• Interrupt Vector Table (IVT) with a Unique Vector
for each Interrupt or Exception Source
• Fixed Priority within a Specified User Priority
Level
7.2
Reset Sequence
• Fixed Interrupt Entry and Return Latencies
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33EPXXXGS70X/80X family devices clear
their registers in response to a Reset, which forces the
PC to zero. The device then begins program execution
at location, 0x000000. A GOTOinstruction at the Reset
address can redirect program execution to the
appropriate start-up routine.
• Alternate Interrupt Vector Table (AIVT) for Debug
Support
7.1
Interrupt Vector Table
The dsPIC33EPXXXGS70X/80X family Interrupt Vector
Table (IVT), shown in Figure 7-1, resides in program
memory, starting at location, 000004h. The IVT con-
tains six non-maskable trap vectors and up to
246 sources of interrupts. In general, each interrupt
source has its own vector. Each interrupt vector
contains a 24-bit wide address. The value programmed
into each interrupt vector location is the starting
address of the associated Interrupt Service Routine
(ISR).
Note: Any unimplemented or unused vector
locations in the IVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with Vector 0 takes priority over interrupts at any other
vector address.
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 7-1:
dsPIC33EPXXXGS70X/80X FAMILY INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Oscillator Fail Trap Vector
Address Error Trap Vector
Generic Hard Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
0x000000
0x000002
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000014
0x000016
:
Generic Soft Trap Vector
Reserved
Interrupt Vector 0
Interrupt Vector 1
:
:
:
:
:
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
:
0x00007C
0x00007E
0x000080
:
See Table 7-1 for
Interrupt Vector Details
:
:
:
:
Interrupt Vector 116
Interrupt Vector 117
Interrupt Vector 118
Interrupt Vector 119
Interrupt Vector 120
:
0x0000FC
0x0000FE
0x000100
0x000102
0x000104
:
:
:
:
:
Interrupt Vector 244
Interrupt Vector 245
START OF CODE
0x0001FC
0x0001FE
0x000200
Note:
In Dual Partition Flash modes, each partition has a dedicated Interrupt Vector Table.
DS70005258C-page 76
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 7-2:
dsPIC33EPXXXGS70X/80X ALTERNATE INTERRUPT VECTOR TABLE(2)
Reserved
BSLIM<12:0>(1) + 0x000000
BSLIM<12:0>(1) + 0x000002
BSLIM<12:0>(1) + 0x000004
BSLIM<12:0>(1) + 0x000006
BSLIM<12:0>(1) + 0x000008
BSLIM<12:0>(1) + 0x00000A
BSLIM<12:0>(1) + 0x00000C
BSLIM<12:0>(1) + 0x00000E
BSLIM<12:0>(1) + 0x000010
BSLIM<12:0>(1) + 0x000012
BSLIM<12:0>(1) + 0x000014
BSLIM<12:0>(1) + 0x000016
:
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Generic Hard Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
Reserved
Generic Soft Trap Vector
Reserved
Interrupt Vector 0
Interrupt Vector 1
:
:
:
:
:
Interrupt Vector 52
BSLIM<12:0>(1) + 0x00007C
BSLIM<12:0>(1) + 0x00007E
BSLIM<12:0>(1) + 0x000080
:
Interrupt Vector 53
Interrupt Vector 54
See Table 7-1 for
Interrupt Vector Details
:
:
:
:
:
Interrupt Vector 116
Interrupt Vector 117
Interrupt Vector 118
Interrupt Vector 119
Interrupt Vector 120
:
BSLIM<12:0>(1) + 0x0000FC
BSLIM<12:0>(1) + 0x0000FE
BSLIM<12:0>(1) + 0x000100
BSLIM<12:0>(1) + 0x000102
BSLIM<12:0>(1) + 0x000104
:
:
:
:
:
Interrupt Vector 244
Interrupt Vector 245
BSLIM<12:0>(1) + 0x0001FC
BSLIM<12:0>(1) + 0x0001FE
Note 1: The address depends on the size of the Boot Segment defined by BSLIM<12:0>.
[(BSLIM<12:0> – 1) x 0x400] + Offset.
2: In Dual Partition Flash modes, each partition has a dedicated Alternate Interrupt Vector
Table (if enabled).
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS
Interrupt Bit Location
Vector
#
IRQ
#
Interrupt Source
IVT Address
Flag
Enable
Priority
Highest Natural Order Priority
INT0 – External Interrupt 0
IC1 – Input Capture 1
8
0
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
IFS0<0>
INT0IF
IEC0<0>
INT0IE
IPC0<2:0>
INT0IP<2:0>
9
1
IFS0<1>
IC1IF
IEC0<1>
IC1IE
IPC0<6:4>
IC1IP<2:0>
OC1 – Output Compare 1
T1 – Timer1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
IFS0<2>
OC1IF
IEC0<2>
OC1IE
IPC0<10:8>
OC1IP<2:0>
3
IFS0<3>
T1IF
IEC0<3>
T1IE
IPC0<14:12>
T1IP<2:0>
DMA0 – DMA Channel 0
IC2 – Input Capture 2
4
IFS0<4>
DMA0IF
IEC0<4>
DMA0IE
IPC1<2:0>
DMA0IP<2:0>
5
IFS0<5>
IC2IF
IEC0<5>
IC2IE
IPC1<6:4>
IC2IP<2:0>
OC2 – Output Compare 2
T2 – Timer2
6
IFS0<6>
OC2IF
IEC0<6>
OC2IE
IPC1<10:8>
OC2IP<2:0>
7
IFS0<7>
T2IF
IEC0<7>
T2IE
IPC1<14:12>
T2IP<2:0>
T3 – Timer3
8
IFS0<8>
T3IF
IEC0<8>
T3IE
IPC2<2:0>
T3IP<2:0>
SPI1TX – SPI1 Transfer Done
SPI1RX – SPI1 Receive Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Global Convert Done
DMA1 – DMA Channel 1
NVM – NVM Write Complete
SI2C1 – I2C1 Slave Event
MI2C1 – I2C1 Master Event
AC1 – Analog Comparator 1 Interrupt
CN – Input Change Interrupt
INT1 – External Interrupt 1
9
IFS0<9>
SPI1TXIF
IEC0<9>
SPI1TXIE
IPC2<6:4>
SPI1TXIP<2:0>
10
11
12
13
14
15
16
17
18
19
20
IFS0<10>
SPI1RXIF
IEC0<10>
SPI1RXIE SPI1RXIP<2:0>
IPC2<10:8>
IFS0<11>
U1RXIF
IEC0<11>
U1RXIE
IPC2<14:12>
U1RXIP<2:0>
IFS0<12>
U1TXIF
IEC0<12>
U1TXIE
IPC3<2:0>
U1TXIP<2:0>
IFS0<13>
ADCIF
IEC0<13>
ADCIE
IPC3<6:4>
ADCIP<2:0>
IFS0<14>
DMA1IF
IEC0<14>
DMA1IE
IPC3<10:8>
DMA1IP<2:0>
IFS0<15>
NVMIF
IEC0<15>
NVMIE
IPC3<14:12>
NVMIP<2:0>
IFS1<0>
SI2C1IF
IEC1<0>
SI2C1IE
IPC4<2:0>
SI2C1IP<2:0>
IFS1<1>
MI2C1IF
IEC1<1>
MI2C1IE
IPC4<6:4>
MI2C1IP<2:0>
IFS1<2>
AC1IF
IEC1<2>
AC1IE
IPC4<10:8>
AC1IP<2:0>
IFS1<3>
CNIF
IEC1<3>
CNIE
IPC4<14:12>
CNIP<2:0>
IFS1<4>
INT1IF
IEC1<4>
INT1IE
IPC5<2:0>
INT1IP<2:0>
Reserved
29-31
32
21-23 0x00003E-0x000043
—
—
—
DMA2 – DMA Channel 2
24
25
26
0x00044
0x000046
0x000048
IFS1<8>
DMA2IF
IEC1<8>
DMA2IE
IPC6<2:0>
DMA2IP<2:0>
OC3 – Output Compare 3
OC4 – Output Compare 4
33
34
IFS1<9>
OC3IF
IEC1<9>
OC3IE
IPC6<6:4>
OC3IP<2:0>
IFS1<10>
OC4IF
IEC1<10>
OC4IE
IPC6<10:8>
OC4IP<2:0>
DS70005258C-page 78
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Bit Location
Vector
#
IRQ
#
Interrupt Source
IVT Address
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x000059
0x00005A
0x00005E
0x000060
Flag
Enable
Priority
T4 – Timer4
35
36
37
38
39
40
41
42
43
44
45
46
27
28
29
30
31
32
33
34
35
36
37
38
IFS1<11>
T4IF
IEC1<11>
T4IE
IPC6<14:12>
T4IP<2:0>
T5 – Timer5
IFS1<12>
T5IF
IEC1<12>
T5IE
IPC7<2:0>
T5IP<2:0>
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
SPI2TX – SPI2 Transfer Done
SPI2RX – SPI2 Receive Done
C1RX – CAN1 RX Data Ready
C1 – CAN1 Combined Error
DMA3 – DMA Channel 3
IC3 – Input Capture 3
IFS1<13>
INT2IF
IEC1<13>
INT2IE
IPC7<6:4>
INT2IP<2:0>
IFS1<14>
U2RXIF
IEC1<14>
U2RXIE
IPC7<10:8>
U2RXIP<2:0>
IFS1<15>
U2TXIF
IEC1<15>
U2TXIE
IPC7<14:12>
U2TXIP<2:0>
IFS2<0>
IEC2<0>
IPC8<2:0>
SPI2TXIF
SPI2TXIE SPI2TXIP<2:0>
IEC2<1> IPC8<6:4>
SPI2RXIE SPI2RXIP<2:0>
IFS2<1>
SPI2RXIF
IFS2<2>
C1RXIF
IEC2<2>
C1RXIE
IPC8<10:8>
C1RXIP<2:0>
IFS2<3>
C1IF
IEC2<3>
C1IE
IPC8<14:12>
C1IP<2:0>
IFS2<4>
DMA3IF
IEC2<4>
DMA3IE
IPC9<2:0>
DMA3IP<2:0>
IFS2<5>
IC3IF
IEC2<5>
IC3IE
IPC9<6:4>
IC3IP<2:0>
IC4 – Input Capture 4
IFS2<6>
IC4IF
IEC2<6>
IC4IE
IPC9<10:8>
IC4IP<2:0>
Reserved
47-56
57
39-48 0x000062-0x000074
—
—
—
SI2C2 – I2C2 Slave Event
49
0x000076
IFS3<1>
SI2C2IF
IEC3<1>
SI2C2IE
IPC12<6:4>
SI2C2IP<2:0>
MI2C2 – I2C2 Master Event
58
50
0x000078
IFS3<2>
MI2C2IF
IEC3<2>
MI2C2IE
IPC12<10:8>
MI2C2IP<2:0>
Reserved
59-61
62
51-53 0x00007A-0x00007E
—
—
—
INT4 – External Interrupt 4
54
55
56
57
0x000080
0x000082
0x000083
0x000086
IFS3<6>
INT4IF
IEC3<6>
INT4IE
IPC13<10:8>
INT4IP<2:0>
C2RX – CAN2 RX Data Ready
C2 – CAN 2 Combined Error
63
64
65
IFS3<7>
C2RXIF
IEC3<7>
C2RXIE
IPC13<14:12>
C2RXIP<2:0>
IFS3<8>
C2IF
IEC3<8>
C2IE
IPC14<2:0>
C2IP<2:0>
PSEM – PWM Special Event Match
IFS3<9>
PSEMIF
IEC3<9>
PSEMIE
IPC14<6:4>
PSEMIP<2:0>
Reserved
66-72
73
58-64 0x000088-0x000094
—
—
—
U1E – UART1 Error Interrupt
65
0x000096
IFS4<1>
U1EIF
IEC4<1>
U1EIE
IPC16<6:4>
U1EIP<2:0>
U2E – UART2 Error Interrupt
74
66
0x000098
IFS4<2>
U2EIF
IEC4<2>
U2EIE
IPC16<10:8>
U2EIP<2:0>
Reserved
75-77
78
67-69 0x00009A-0x0000A2
—
—
—
C1TX – CAN1 TX Data Request
70
71
72
0x0000A0
0x0000A
0x0000A4
IFS4<6>
C1TXIF
IEC4<6>
C1TXIE
IPC17<10:8>
C1TXIP<2:0>
C2TX – CAN2 TX Data Request
Reserved
79
80
IFS4<7>
C2TXIF
IEC4<7>
C2TXIE
IPC17<14:12>
C2TXIP<2:0>
—
—
—
2016-2018 Microchip Technology Inc.
DS70005258C-page 79
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Bit Location
Vector
#
IRQ
#
Interrupt Source
IVT Address
Flag
Enable
Priority
PSES – PWM Secondary Special
Event Match
81
73
0x0000A6
IFS4<9>
PSESIF
IEC4<9>
PSESIE
IPC18<6:4>
PSESIP<2:0>
Reserved
82-97
98
74-89 0x0000A8-0x0000C6
—
—
—
SPI3TX – SPI3 Transfer Done
90
0x0000C8
IFS5<10>
SPI3TXIF
IEC5<10>
IPC22<10:8>
SPI3TXIE SPI3TXIP<2:0>
IEC5<11> IPC22<14:12>
SPI3RXIE SPI3RXIP<2:0>
SPI3RX – SPI3 Receive Done
99
91
0x0000CA
IFS5<10>
SPI3RXIF
Reserved
100-101 92-93 0x0000CC-0x0000CE
—
—
—
PWM1 – PWM1 Interrupt
102
103
104
105
106
107
108
109
94
0x0000D0
0x0000D2
0x0000D4
0x0000D6
0x0000D8
0x0000DA
0x0000DC
0x0000DE
IFS5<14>
PWM1IF
IEC5<14>
PWM1IE
IPC23<10:8>
PWM1IP<2:0>
PWM2 – PWM2 Interrupt
PWM3 – PWM3 Interrupt
PWM4 – PWM4 Interrupt
PWM5 – PWM5 Interrupt
PWM6 – PWM6 Interrupt
PWM7 – PWM7 Interrupt
PWM8 – PWM8 Interrupt
95
IFS5<15>
PWM2IF
IEC5<15>
PWM2IE
IPC23<14:12>
PWM2IP<2:0>
96
IFS6<0>
PWM3IF
IEC6<0>
PWM3IE
IPC24<2:0>
PWM3IP<2:0>
97
IFS6<1>
PWM4IF
IEC6<1>
PWM4IE
IPC24<6:4>
PWM4IP<2:0>
98
IFS6<2>
PWM5IF
IEC6<2>
PWM5IE
IPC24<10:8>
PWM5IP<2:0>
99
IFS6<3>
PWM6IF
IEC6<3>
PWM6IE
IPC24<14:12>
PWM6IP<2:0>
100
101
IFS6<4>
PWM7IF
IEC6<4>
PWM7IE
IPC25<2:0>
PWM7IP<2:0>
IFS6<5>
PWM8IF
IEC6<5>
PWM8IE
IPC25<6:4>
PWM8IP<2:0>
Reserved
110
111
102
103
0x0000E0
0x0000E2
—
—
—
AC2 – Analog Comparator 2 Interrupt
IFS6<7>
AC2IF
IEC6<7>
AC2IE
IPC25<14:12>
AC2IP<2:0>
AC3 – Analog Comparator 3 Interrupt
AC4 – Analog Comparator 4 Interrupt
112
113
104
105
0x0000E4
0x0000E6
IFS6<8>
AC3IF
IEC6<8>
AC3IE
IPC26<2:0>
AC3IP<2:0>
IFS6<9>
AC4IF
IEC6<9>
AC4IE
IPC26<6:4>
AC4IP<2:0>
Reserved
114-117 106-109 0x0000E8-0x0000EE
—
—
—
AN0 Conversion Done
118
119
120
121
122
123
124
125
110
111
112
113
114
115
116
117
0x0000F0
0x0000F2
0x0000F4
0x0000F6
0x0000F8
0x0000FA
0x0000FC
0x0000FE
IFS6<14>
AN0IF
IEC6<14>
AN0IE
IPC27<10:8>
AN0IP<2:0>
AN1 Conversion Done
AN2 Conversion Done
AN3 Conversion Done
AN4 Conversion Done
AN5 Conversion Done
AN6 Conversion Done
AN7 Conversion Done
Reserved
IFS6<15>
AN1IF
IEC6<15>
AN1IE
IPC27<14:12>
AN1IP<2:0>
IFS7<0>
AN2IF
IEC7<0>
AN2IE
IPC28<2:0>
AN2IP<2:0>
IFS7<1>
AN3IF
IEC7<1>
AN3IE
IPC28<6:4>
AN3IP<2:0>
IFS7<2>
AN4IF
IEC7<2>
AN4IE
IPC28<10:8>
AN4IP<2:0>
IFS7<3>
AN5IF
IEC7<3>
AN5IE
IPC28<14:12>
AN5IP<2:0>
IFS7<4>
AN6IF
IEC7<4>
AN6IE
IPC29<2:0>
AN6IP<2:0>
IFS7<5>
AN7IF
IEC7<5>
AN7IE
IPC29<6:4>
AN7IP<2:0>
126-131 118-123 0x000100-0x00010A
—
—
—
DS70005258C-page 80
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Bit Location
Vector
#
IRQ
#
Interrupt Source
IVT Address
0x00010C
0x00010E
0x000110
Flag
Enable
Priority
SPI1 Error Interrupt
SPI2 Error Interrupt
SPI3 Error Interrupt
132
133
134
124
125
126
IFS7<12>
SPI1IF
IEC7<12>
SPI1IE
IPC31<2:0>
SPI1IP<2:0>
IFS7<13>
SPI2IF
IEC7<13>
SPI2IE
IPC31<6:4>
SPI2IP<2:0>
IFS7<13>
SPI3IF
IEC7<13>
SPI3IE
IPC31<10:8>
SPI3IP<2:0>
Reserved
135-145 127-137 0x000112-0x000126
—
—
—
CLC1 Interrupt
146
147
148
149
150
151
138
139
140
141
142
143
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
IFS8<10>
CLC1IF
IEC8<10>
CLC1IE
IPC34<10:8>
CLC1IP<2:0>
CLC2 Interrupt
IFS8<11>
CLC2IF
IEC8<11>
CLC2IE
IPC34<14:12>
CLC2IP<2:0>
CLC3 Interrupt
IFS8<12>
CLC3IF
IEC8<12>
CLC3IE
IPC35<2:0>
CLC3IP<2:0>
CLC4 Interrupt
IFS8<13>
CLC4IF
IEC8<13>
CLC4IE
IPC35<6:4>
CLC4IP<2:0>
ICD – ICD Application
JTAG – JTAG Programming
IFS8<14>
ICDIF
IEC8<14>
ICDIE
IPC35<10:8>
ICDIP<2:0>
IFS8<15>
JTAGIF
IEC8<15>
JTAGIE
IPC35<14:12>
JTAGIP<2:0>
Reserved
152
153
144
145
0x000134
0x000136
—
—
—
PTGSTEP – PTG Step
IFS9<1>
IEC9<1>
IPC36<6:4>
PTGSTEPIF PTGSTEPIE PTGSTEP<2:0>
IFS9<2> IEC9<2> IPC36<10:8>
PTGWDTIF PTGWDTIE PTGWDT<2:0>
PTGWDT – PTG WDT Time-out
PTG0 – PTG Interrupt Trigger 0
PTG1 – PTG Interrupt Trigger 1
PTG2 – PTG Interrupt Trigger 2
PTG3 – PTG Interrupt Trigger 3
AN8 Conversion Done
154
155
156
157
158
159
160
161
162
163
164
165
166
167
146
147
148
149
150
151
152
153
154
155
156
157
158
159
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
IFS9<3>
PTG0IF
IEC9<3>
PTG0IE
IPC36<14:12>
PTG0IP<2:0>
IFS9<4>
PTG1IF
IEC9<4>
PTG1IE
IPC37<2:0>
PTG1IP<2:0>
IFS9<5>
PTG2IF
IEC9<5>
PTG2IE
IPC37<6:4>
PTG2IP<2:0>
IFS9<6>
PTG3IF
IEC9<6>
PTG3IE
IPC37<10:8>
PTG3IP<2:0>
IFS9<7>
AN8IF
IEC9<7>
AN8IE
IPC37<14:12>
AN8IP<2:0>
AN9 Conversion Done
IFS9<8>
AN9IF
IEC9<8>
AN9IE
IPC38<2:0>
AN9IP<2:0>
AN10 Conversion Done
IFS9<9>
AN10IF
IEC9<9>
AN10IE
IPC38<6:4>
AN10IP<2:0>
AN11 Conversion Done
IFS9<10>
AN11IF
IEC9<10>
AN11IE
IPC38<10:8>
AN11IP<2:0>
AN12 Conversion Done
IFS9<11>
AN12IF
IEC9<11>
AN12IE
IPC38<14:12>
AN12IP<2:0>
AN13 Conversion Done
IFS9<12>
AN13IF
IEC9<12>
AN13IE
IPC39<2:0>
AN13IP<2:0>
AN14 Conversion Done
IFS9<13>
AN14IF
IEC9<13>
AN14IE
IPC39<6:4>
AN14IP<2:0>
AN15 Conversion Done
IFS9<14>
AN15IF
IEC9<14>
AN15IE
IPC39<10:8>
AN15IP<2:0>
AN16 Conversion Done
IFS9<15>
AN16IF
IEC9<15>
AN16IE
IPC39<14:12>
AN16IP<2:0>
2016-2018 Microchip Technology Inc.
DS70005258C-page 81
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 7-1:
INTERRUPT VECTOR DETAILS (CONTINUED)
Interrupt Bit Location
Vector
#
IRQ
#
Interrupt Source
IVT Address
0x000154
0x000156
0x000158
0x00015A
0x00015C
Flag
Enable
Priority
AN17 Conversion Done
AN18 Conversion Done
AN19 Conversion Done
AN20 Conversion Done
AN21 Conversion Done
168
169
170
171
172
160
161
162
163
164
IFS10<0>
AN17IF
IEC10<0>
AN17IE
IPC40<2:0>
AN17IP<2:0>
IFS10<1>
AN18IF
IEC10<1>
AN18IE
IPC40<6:4>
AN18IP<2:0>
IFS10<2>
AN19IF
IEC10<2>
AN19IE
IPC40<10:8>
AN19IP<2:0>
IFS10<3>
AN20IF
IEC10<3>
AN20IE
IPC40<14:12>
AN20IP<2:0>
IFS10<4>
AN21IF
IEC10<4>
AN21IE
IPC41<2:0>
AN21IP<2:0>
Reserved
173-180 165-172 0x00015C-0x00016C
—
—
—
I2C1 – I2C1 Bus Collision
181
173
0x00016E
IFS10<13> IEC10<13>
I2C1IF I2C1IE
IFS10<14> IEC10<14>
IPC43<6:4>
I2C1IP<2:0>
I2C2 – I2C2 Bus Collision
182
174
0x000170
IPC43<10:8>
I2C2IP<2:0>
I2C2IF
I2C2IE
Reserved
183-184 175-176 0x000172-0x000174
—
—
—
ADCMP0 – ADC Digital Comparator 0
185
186
187
188
177
178
179
180
0x000176
0x000178
0x00017A
0x00017C
IFS11<1>
IEC11<1>
IPC44<6:4>
ADCMP0IF ADCMP0IE ADCMP0IP<2:0>
IFS11<2> IEC11<2> IPC44<10:8>
ADCMP1IF ADCMP1IE ADCMP1IP<2:0>
IFS11<3> IEC11<3> IPC44<14:12>
ADFLTR0IF ADFLTR0IE ADFLTR0IP<2:0>
IFS11<4> IEC11<4> IPC45<2:0>
ADFLTR1IF ADFLTR1IE ADFLTR1IP<2:0>
ADCMP1 – ADC Digital Comparator 1
ADFLTR0 – ADC Filter 0
ADFLTR1 – ADC Filter 1
Reserved
189-253 181-245 0x00017E-0x000192
—
—
—
DS70005258C-page 82
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
7.4.3
IECx
7.3
Interrupt Resources
The IECx registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
7.4.4
IPCx
7.3.1
KEY RESOURCES
The IPCx registers are used to set the Interrupt Priority
Level (IPL) for each source of interrupt. Each user
interrupt source can be assigned to one of seven
priority levels.
• “Interrupts” (DS70000600) in the
“dsPIC33/PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
7.4.5
INTTREG
The INTTREG register contains the associated
interrupt vector number and the new CPU Interrupt
Priority Level, which are latched into the Vector
Number of Pending Interrupt bits (VECNUM<7:0>) and
New CPU Interrupt Priority Level bits (ILR<3:0>) fields
in the INTTREG register. The new Interrupt Priority
Level is the priority of the pending interrupt.
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
7.4
Interrupt Control and Status
Registers
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence as they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having Vector Number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0> and the
INT0IP<2:0> bits in the first position of IPC0
(IPC0<2:0>).
dsPIC33EPXXXGS70X/80X family devices implement
the following registers for the interrupt controller:
• INTCON1
• INTCON2
• INTCON3
• INTCON4
• INTTREG
7.4.6
STATUS/CONTROL REGISTERS
Although these registers are not specifically part of the
interrupt control hardware, two of the CPU Control
registers contain bits that control interrupt functionality.
For more information on these registers, refer to
“dsPIC33E Enhanced CPU” (DS70005158) in the
“dsPIC33/PIC24 Family Reference Manual”.
7.4.1
INTCON1 THROUGH INTCON4
Global interrupt control functions are controlled from
INTCON1, INTCON2, INTCON3 and INTCON4.
INTCON1 contains the Interrupt Nesting Disable bit
(NSTDIS), as well as the control and status flags for the
processor trap sources.
• The CPU STATUS Register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU Interrupt Priority Level. The user
software can change the current CPU Interrupt
Priority Level by writing to the IPLx bits.
The INTCON2 register controls external interrupt
request signal behavior, contains the Global Interrupt
Enable bit (GIE) and the Alternate Interrupt Vector Table
Enable bit (AIVTEN).
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
INTCON3 contains the status flags for the Auxiliary
PLL and DOstack overflow status trap sources.
The INTCON4 register contains the Software
Generated Hard Trap Status bit (SGHT).
All Interrupt registers are described in Register 7-3
through Register 7-7 in the following pages.
7.4.2
IFSx
The IFSx registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
2016-2018 Microchip Technology Inc.
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REGISTER 7-1:
SR: CPU STATUS REGISTER(1)
R/W-0
OA
R/W-0
OB
R/W-0
SA
R/W-0
SB
R/C-0
OAB
R/C-0
SAB
R-0
DA
R/W-0
DC
bit 15
bit 8
R/W-0(3)
IPL2(2)
bit 7
R/W-0(3)
IPL1(2)
R/W-0(3)
IPL0(2)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’= Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2,3)
111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.
DS70005258C-page 84
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER(1)
R/W-0
VAR
U-0
—
R/W-0
US1
R/W-0
US0
R/W-0
EDT
R-0
R-0
R-0
DL2
DL1
DL0
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R-0
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
SFA
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’= Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 3
VAR: Variable Exception Processing Latency Control bit
1= Variable exception processing is enabled
0= Fixed exception processing is enabled
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU Interrupt Priority Level is greater than 7
0= CPU Interrupt Priority Level is 7 or less
Note 1: For complete register details, see Register 3-2.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
2016-2018 Microchip Technology Inc.
DS70005258C-page 85
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REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR
OVBERR
COVAERR
COVBERR
OVATE
OVBTE
COVTE
bit 8
R/W-0
SFTACERR
bit 7
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
MATHERR
ADDRERR
STKERR
OSCFAIL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator A
0= Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator B
0= Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator A
0= Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator B
0= Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap is disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap is disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B is enabled
0= Trap is disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1= Math error trap was caused by an invalid accumulator shift
0= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Divide-by-Zero Error Status bit
1= Math error trap was caused by a divide-by-zero
0= Math error trap was not caused by a divide-by-zero
bit 5
bit 4
Unimplemented: Read as ‘0’
MATHERR: Math Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
bit 3
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
DS70005258C-page 86
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
2016-2018 Microchip Technology Inc.
DS70005258C-page 87
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-1
GIE
R/W-0
DISI
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SWTRAP
AIVTEN
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
INT4EP
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
GIE: Global Interrupt Enable bit
1= Interrupts and associated IE bits are enabled
0= Interrupts are disabled, but traps are still enabled
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
SWTRAP: Software Trap Status bit
1= Software trap is enabled
0= Software trap is disabled
bit 12-9
bit 8
Unimplemented: Read as ‘0’
AIVTEN: Alternate Interrupt Vector Table Enable
1= Uses Alternate Interrupt Vector Table
0= Uses standard Interrupt Vector Table
bit 7-5
bit 4
Unimplemented: Read as ‘0’
INT4EP: External Interrupt 4 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
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REGISTER 7-5:
INTCON3: INTERRUPT CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
NAE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
APLL
DOOVR
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-9
bit 8
Unimplemented: Read as ‘0’
NAE: NVM Address Error Soft Trap Status bit
1= NVM address error soft trap has occurred
0= NVM address error soft trap has not occurred
bit 7-5
bit 4
Unimplemented: Read as ‘0’
DOOVR: DOStack Overflow Soft Trap Status bit
1= DOstack overflow soft trap has occurred
0= DOstack overflow soft trap has not occurred
bit 3-1
bit 0
Unimplemented: Read as ‘0’
APLL: Auxiliary PLL Loss of Lock Soft Trap Status bit
1= APLL lock soft trap has occurred
0= APLL lock soft trap has not occurred
REGISTER 7-6:
INTCON4: INTERRUPT CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SGHT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
Unimplemented: Read as ‘0’
SGHT: Software Generated Hard Trap Status bit
1= Software generated hard trap has occurred
0= Software generated hard trap has not occurred
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REGISTER 7-7:
INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
VECNUM<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7-0
VECNUM<7:0>: Vector Number of Pending Interrupt bits
11111111= 255, Reserved; do not use
•
•
•
00001001= 9, IC1 – Input Capture 1
00001000= 8, INT0 – External Interrupt 0
00000111= 7, Reserved; do not use
00000110= 6, Generic soft error trap
00000101= 5, Reserved; do not use
00000100= 4, Math error trap
00000011= 3, Stack error trap
00000010= 2, Generic hard trap
00000001= 1, Address error trap
00000000= 0, Oscillator fail trap
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The DMA Controller transfers data between Peripheral
Data registers and Data Space SRAM.
8.0
DIRECT MEMORY ACCESS
(DMA)
In addition, DMA can access the entire data memory
space. The data memory bus arbiter is utilized when
either the CPU or DMA attempts to access SRAM,
resulting in potential DMA or CPU Stalls.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data
sheet, refer to “Direct Memory Access
(DMA)” (DS70348) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip website
(www.microchip.com).
The DMA Controller supports four independent
channels. Each channel can be configured for transfers
to or from selected peripherals. The peripherals
supported by the DMA Controller include:
• CAN
• UART
• Input Capture
• Output Compare
• Timers
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Refer to Table 8-1 for a complete list of supported
peripherals.
FIGURE 8-1:
PERIPHERAL TO DMA CONTROLLER
Data Memory
Arbiter
PERIPHERAL
DMA
(see Figure 4-10)
SRAM
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In addition, DMA transfers can be triggered by timers as
well as external interrupts. Each DMA channel is uni-
directional. Two DMA channels must be allocated to read
and write to a peripheral. If more than one channel
receives a request to transfer data, a simple fixed priority
scheme, based on channel number, dictates which
channel completes the transfer and which channel, or
channels, are left pending. Each DMA channel moves a
block of data, after which, it generates an interrupt to the
CPU to indicate that the block is available for processing.
• Peripheral Indirect Addressing mode (peripheral
generates destination address)
• CPU Interrupt after Half or Full Block Transfer
Complete
• Byte or Word Transfers
• Fixed Priority Channel Arbitration
• Manual (software) or Automatic (peripheral DMA
requests) Transfer Initiation
• One-Shot or Auto-Repeat Block Transfer modes
• Ping-Pong mode (automatic switch between two
SRAM Start addresses after each block transfer
complete)
The DMA Controller provides these functional
capabilities:
• Four DMA Channels
• DMA Request for each Channel can be Selected
from any Supported Interrupt Source
• Register Indirect with Post-Increment Addressing
mode
• Debug Support Features
• Register Indirect without Post-Increment
Addressing mode
The peripherals that can utilize DMA are listed in
Table 8-1.
TABLE 8-1:
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
DMAxPAD Register
(Values to Read from
Peripheral)
DMAxPAD Register
(Values to Write to
Peripheral)
Peripheral to DMA
DMAxREQ Register
IRQSEL<7:0> Bits
Association
INT0 – External Interrupt 0
IC1 – Input Capture 1
IC2 – Input Capture 2
IC3 – Input Capture 3
IC4 – Input Capture 4
OC1 – Output Compare 1
00000000
00000001
00000101
00100101
00100110
00000010
—
—
—
—
—
—
0x0144 (IC1BUF)
0x014C (IC2BUF)
0x0154 (IC3BUF)
0x015C (IC4BUF)
—
0x0906 (OC1R)
0x0904 (OC1RS)
OC2 – Output Compare 2
OC3 – Output Compare 3
OC4 – Output Compare 4
00000110
00011001
00011010
—
—
—
0x0910 (OC2R)
0x090E (OC2RS)
0x091A (OC3R)
0x0918 (OC3RS)
0x0924 (OC4R)
0x0922 (OC4RS)
TMR2 – Timer2
00000111
00001000
00011011
00011100
00001011
00001100
00011110
00011111
00100010
01000110
00110111
01000111
—
—
TMR3 – Timer3
—
—
TMR4 – Timer4
—
—
TMR5 – Timer5
—
—
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
CAN1 – RX Data Ready
CAN1 – TX Data Request
CAN2 – RX Data Ready
CAN2 – TX Data Request
0x0226 (U1RXREG)
—
—
0x0224 (U1TXREG)
0x0236 (U2RXREG)
—
0x0234 (U2TXREG)
—
—
0x04C0 (C1RXD)
—
0x07C0(C2RXD)
—
0x04C2 (C1TXD)
—
0x07C2 (C2TXD)
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FIGURE 8-2:
DMA CONTROLLER BLOCK DIAGRAM
SRAM
Peripheral Indirect Address
DMA Controller
DMA
Ready
Peripheral 1
IRQ to DMA
and Interrupt
Controller
DMA
Channels
Arbiter
Modules
0
1
2
3
CPU DMA
DMA X-Bus
CPU Peripheral X-Bus
CPU DMA
CPU DMA
DMA
Ready
Peripheral 2
DMA
Ready
Peripheral 3
Non-DMA
Peripheral
CPU
IRQ to DMA and
Interrupt Controller
Modules
IRQ to DMA and
Interrupt Controller
Modules
Note: CPU and DMA address buses are not shown for clarity.
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Additional status registers (DMAPWC, DMARQC,
DMAPPS, DMALCA and DSADRL/H) are common to all
DMA Controller channels. These status registers pro-
vide information on write and request collisions, as well
as on last address and channel access information.
8.1
DMA Controller Registers
Each DMA Controller Channel x (where x = 0 through 3)
contains the following registers:
• 16-Bit DMA Channel x Control Register (DMAxCON)
• 16-Bit DMA Channel x IRQ Select Register
(DMAxREQ)
• 32-Bit DMA Channel x Start Address Register A
(DMAxSTAL/H)
• 32-Bit DMA Channel x Start Address Register B
(DMAxSTBL/H)
• 16-Bit DMA Channel x Peripheral Address Register
(DMAxPAD)
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in an
IECx register in the interrupt controller and the
corresponding interrupt priority control bits (DMAxIP)
are located in an IPCx register in the interrupt controller.
• 14-Bit DMA Channel x Transfer Count Register
(DMAxCNT)
REGISTER 8-1:
DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0
CHEN
R/W-0
SIZE
R/W-0
DIR
R/W-0
HALF
R/W-0
U-0
—
U-0
—
U-0
—
NULLW
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
AMODE1
AMODE0
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
CHEN: DMA Channel Enable bit
1= Channel is enabled
0= Channel is disabled
SIZE: DMA Data Transfer Size bit
1= Byte
0= Word
DIR: Transfer Direction bit (source/destination bus select)
1= Reads from RAM address, writes to peripheral address
0= Reads from peripheral address, writes to RAM address
HALF: Block Transfer Interrupt Select bit
1= Initiates interrupt when half of the data has been moved
0= Initiates interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1= Null data write to peripheral in addition to RAM write (DIR bit must also be clear)
0= Normal operation
bit 10-6
bit 5-4
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Addressing Mode Select bits
11= Reserved
10= Peripheral Indirect mode
01= Register Indirect without Post-Increment mode
00= Register Indirect with Post-Increment mode
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11= One-Shot, Ping-Pong modes are enabled (one block transfer from/to each DMA buffer)
10= Continuous, Ping-Pong modes are enabled
01= One-Shot, Ping-Pong modes are disabled
00= Continuous, Ping-Pong modes are disabled
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REGISTER 8-2:
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/S-0
FORCE(1)
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IRQSEL<7:0>
bit 0
Legend:
S = Settable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FORCE: Force DMA Transfer bit(1)
1= Forces a single DMA transfer (Manual mode)
0= Automatic DMA transfer initiation by DMA request
bit 14-8
bit 7-0
Unimplemented: Read as ‘0’
IRQSEL<7:0>: DMA Peripheral IRQ Number Select bits
01000111= CAN2 – TX data request
01000110= CAN1 – TX data request
00110111= CAN2 – RX data ready
00100110= IC4 – Input Capture 4
00100101= IC3 – Input Capture 3
00100010= CAN1 – RX data ready
00011111= UART2TX – UART2 transmitter
00011110= UART2RX – UART2 receiver
00011100= TMR5 – Timer5
00011011= TMR4 – Timer4
00011010= OC4 – Output Compare 4
00011001= OC3 – Output Compare 3
00001100= UART1TX – UART1 transmitter
00001011= UART1RX – UART1 receiver
00001000= TMR3 – Timer3
00000111= TMR2 – Timer2
00000110= OC2 – Output Compare 2
00000101= IC2 – Input Capture 2
00000010= OC1 – Output Compare 1
00000001= IC1 – Input Capture 1
00000000= INT0 – External Interrupt 0
Note 1: The FORCE bit cannot be cleared by user software. The FORCE bit is cleared by hardware when the
forced DMA transfer is complete or the channel is disabled (CHEN = 0).
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REGISTER 8-3:
DMAxSTAH: DMA CHANNEL x START ADDRESS REGISTER A (HIGH)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STA<23:16>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
STA<23:16>: DMA Primary Start Address bits (source or destination)
REGISTER 8-4:
DMAxSTAL: DMA CHANNEL x START ADDRESS REGISTER A (LOW)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
STA<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STA<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STA<15:0>: DMA Primary Start Address bits (source or destination)
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REGISTER 8-5:
DMAxSTBH: DMA CHANNEL x START ADDRESS REGISTER B (HIGH)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STB<23:16>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
STB<23:16>: DMA Secondary Start Address bits (source or destination)
REGISTER 8-6:
DMAxSTBL: DMA CHANNEL x START ADDRESS REGISTER B (LOW)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
STB<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STB<7:0>
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STB<15:0>: DMA Secondary Start Address bits (source or destination)
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REGISTER 8-7:
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PAD<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
PAD<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PAD<15:0>: DMA Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
REGISTER 8-8:
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
CNT<13:8>(2)
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNT<7:0>(2)
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-0
Unimplemented: Read as ‘0’
CNT<13:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: The number of DMA transfers = CNT<13:0> + 1.
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REGISTER 8-9:
DSADRH: DMA MOST RECENT RAM HIGH ADDRESS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<23:16>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
DSADR<23:16>: Most Recent DMA Address Accessed by DMA bits
REGISTER 8-10: DSADRL: DMA MOST RECENT RAM LOW ADDRESS REGISTER
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<15:8>
bit 15
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DSADR<15:0>: Most Recent DMA Address Accessed by DMA bits
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REGISTER 8-11: DMAPWC: DMA PERIPHERAL WRITE COLLISION STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
PWCOL3
PWCOL2
PWCOL1
PWCOL0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1= Write collision is detected
0= No write collision is detected
bit 2
bit 1
bit 0
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1= Write collision is detected
0= No write collision is detected
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1= Write collision is detected
0= No write collision is detected
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1= Write collision is detected
0= No write collision is detected
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REGISTER 8-12: DMARQC: DMA REQUEST COLLISION STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
RQCOL3
RQCOL2
RQCOL1
RQCOL0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
RQCOL3: Channel 3 Transfer Request Collision Flag bit
1= User FORCE and interrupt-based request collision are detected
0= No request collision is detected
bit 2
bit 1
bit 0
RQCOL2: Channel 2 Transfer Request Collision Flag bit
1= User FORCE and interrupt-based request collision are detected
0= No request collision is detected
RQCOL1: Channel 1 Transfer Request Collision Flag bit
1= User FORCE and interrupt-based request collision are detected
0= No request collision is detected
RQCOL0: Channel 0 Transfer Request Collision Flag bit
1= User FORCE and interrupt-based request collision are detected
0= No request collision is detected
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REGISTER 8-13: DMALCA: DMA LAST CHANNEL ACTIVE STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R-1
R-1
R-1
R-1
LSTCH<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3-0
Unimplemented: Read as ‘0’
LSTCH<3:0>: Last DMA Controller Channel Active Status bits
1111= No DMA transfer has occurred since system Reset
1110= Reserved
•
•
•
0100= Reserved
0011= Last data transfer was handled by Channel 3
0010= Last data transfer was handled by Channel 2
0001= Last data transfer was handled by Channel 1
0000= Last data transfer was handled by Channel 0
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REGISTER 8-14: DMAPPS: DMA PING-PONG STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
PPST3
PPST2
PPST1
PPST0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1= DMA3STB register is selected
0= DMA3STA register is selected
bit 2
bit 1
bit 0
PPST2: Channel 2 Ping-Pong Mode Status Flag bit
1= DMA2STB register is selected
0= DMA2STA register is selected
PPST1: Channel 1 Ping-Pong Mode Status Flag bit
1= DMA1STB register is selected
0= DMA1STA register is selected
PPST0: Channel 0 Ping-Pong Mode Status Flag bit
1= DMA0STB register is selected
0= DMA0STA register is selected
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NOTES:
DS70005258C-page 104
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dsPIC33EPXXXGS70X/80X FAMILY
The dsPIC33EPXXXGS70X/80X family oscillator
system provides:
9.0
OSCILLATOR CONFIGURATION
Note 1: This data sheet summarizes the features
• On-Chip Phase-Locked Loop (PLL) to Boost
Internal Operating Frequency on Select Internal
and External Oscillator Sources
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Oscillator Module”
(DS70005131) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
• On-the-Fly Clock Switching between Various
Clock Sources
• Doze mode for System Power Savings
• Fail-Safe Clock Monitor (FSCM) that Detects
Clock Failure and Permits Safe Application
Recovery or Shutdown
• Configuration Bits for Clock Source Selection
• Auxiliary PLL for ADC and PWM
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
A simplified diagram of the oscillator system is shown
in Figure 9-1.
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FIGURE 9-1:
OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator (POSC)
DOZE<2:0>
OSC1
POSCCLK
XT, HS, EC
S2
XTPLL, HSPLL,
ECPLL, FRCPLL
FPLLO
(1)
S3
S1
(2)
S1/S3
FCY
PLL
FVCO
OSC2
POSCMD<1:0>
(2)
FP
÷ 2
FRCCLK
FRCDIVN
FRC
Oscillator
FOSC
S7
REFERENCE CLOCK OUTPUT
TUN<5:0>
FRCDIV<2:0>
FRCDIV16
FRC
POSCCLK
FOSC
REFCLKO
÷ 16
S6
S0
S5
÷ N
RPn
RODIV<3:0>
LPRC
ROSEL
LPRC
Oscillator
Clock Fail Clock Switch
Reset
S0
NOSC<2:0>
FNOSC<2:0>
WDT, PWRT,
FSCM
AUXILIARY CLOCK GENERATOR CIRCUIT BLOCK DIAGRAM
(1)
FRCCLK
FVCO
0
1
1
ACLK
÷ N
PWM/ADC
to LFSR
1
0
1
0
APLL x 16
POSCCLK
GND
0
SELACLK APSTSCLR<2:0>(4)
ENAPLL
ASRCSEL
FRCSEL
Note 1: See Figure 9-2 for the source of the FVCO signal.
2: FP refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source for the CPU.
Throughout this document, FCY and FP are used interchangeably, except in the case of Doze mode. FP and FCY
will be different when Doze mode is used in any ratio other than 1:1.
3: The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper operation
of the PWM and ADC modules.
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Instruction execution speed or device operating
frequency, FCY, is given by Equation 9-1.
9.1
CPU Clocking System
The dsPIC33EPXXXGS70X/80X family of devices
provides six system clock options:
EQUATION 9-1:
DEVICE OPERATING
FREQUENCY
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase-Locked Loop
(FRCPLL)
FCY = FOSC/2
• FRC Oscillator with Postscaler
• Primary (XT, HS or EC) Oscillator
Figure 9-2 is a block diagram of the PLL module.
Equation 9-2 provides the relationship between Input
Frequency (FIN) and Output Frequency (FPLLO).
Equation 9-3 provides the relationship between Input
Frequency (FIN) and VCO Frequency (FVCO).
• Primary Oscillator with PLL (XTPLL, HSPLL,
ECPLL)
• Low-Power RC (LPRC) Oscillator
FIGURE 9-2:
PLL BLOCK DIAGRAM
(1)
(1)
FPLLO 120 MHz @ +125ºC
0.8 MHz < FPLLI < 8.0 MHz
(1)
(1)
120 MHZ < FVCO < 340 MHZ
FPLLO 140 MHz @ +85ºC
FPLLI
FIN
÷ N1
FVCO
FOSC
PFD
VCO
÷ N2
PLLPRE<4:0>
PLLPOST<1:0>
÷ M
PLLDIV<8:0>
Note 1: This frequency range must be met at all times.
EQUATION 9-2:
FPLLO CALCULATION
PLLDIV<8:0> + 2
M
FPLLO = FIN
= FIN
( ) ((PLLPRE<4:0> + 2) 2(PLLPOST<1:0> + 1)
)
N1
Where:
N1 = PLLPRE<4:0> + 2
N2 = 2 x (PLLPOST<1:0> + 1)
M = PLLDIV<8:0> + 2
EQUATION 9-3:
FVCO CALCULATION
PLLDIV<8:0> + 2
M
N1
FVCO = FIN
= FIN
(PLLPRE<4:0> + 2)
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TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0>
See
Notes
Fast RC Oscillator with Divide-by-n (FRCDIVN)
Fast RC Oscillator with Divide-by-16
Low-Power RC Oscillator (LPRC)
Primary Oscillator (HS) with PLL (HSPLL)
Primary Oscillator (XT) with PLL (XTPLL)
Primary Oscillator (EC) with PLL (ECPLL)
Primary Oscillator (HS)
Internal
Internal
Internal
Primary
Primary
Primary
Primary
Primary
Primary
Internal
xx
xx
xx
10
01
00
10
01
00
xx
111
110
101
011
011
011
010
010
010
001
1, 2
1
1
1
Primary Oscillator (XT)
Primary Oscillator (EC)
1
1
Fast RC Oscillator (FRC) with Divide-by-N and
PLL (FRCPLL)
Fast RC Oscillator (FRC)
Internal
xx
000
1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default Oscillator mode for an unprogrammed (erased) device.
9.2
Auxiliary Clock Generation
9.3
Reference Clock Generation
The auxiliary clock generation is used for peripherals
that need to operate at a frequency unrelated to the
system clock, such as PWM or ADC.
The reference clock output logic provides the user with
the ability to output a clock signal based on the system
clock or the crystal oscillator on a device pin. The user
application can specify a wide range of clock scaling
prior to outputting the reference clock.
The primary oscillator and internal FRC oscillator
sources can be used with an Auxiliary PLL (APLL) to
obtain the auxiliary clock. The Auxiliary PLL has a fixed
16x multiplication factor.
9.4
Oscillator Resources
The auxiliary clock has the following configuration
restrictions:
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
• For proper PWM operation, auxiliary clock
generation must be configured for 120 MHz (see
Parameter OS56 in Section 30.0 “Electrical Char-
acteristics”). If a slower frequency is desired, the
PWM Input Clock Prescaler (Divider) Select bits
(PCLKDIV<2:0>) should be used.
9.4.1
KEY RESOURCES
• “Oscillator Module” (DS70005131) in the
“dsPIC33/PIC24 Family Reference Manual”
• To achieve 1.04 ns PWM resolution, the auxiliary
clock must use the 16x Auxiliary PLL (APLL). All
other clock sources will have a minimum PWM
resolution of 8 ns.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• If the primary PLL is used as a source for the
auxiliary clock, the primary PLL should be config-
ured up to a maximum operation of 30 MIPS or
less.
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
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9.5
Oscillator Control Registers
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
NOSC2(2)
R/W-y
NOSC1(2)
R/W-y
NOSC0(2)
COSC2
COSC1
COSC0
bit 15
bit 8
R/W-0
CLKLOCK
bit 7
R/W-0
R-0
U-0
—
R/W-0
CF(3)
U-0
—
U-0
—
R/W-0
IOLOCK
LOCK
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
111= Fast RC Oscillator (FRC) with Divide-by-n
110= Fast RC Oscillator (FRC) with Divide-by-16
101= Low-Power RC Oscillator (LPRC)
100= Reserved
011= Primary Oscillator (XT, HS, EC) with PLL
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)
111= Fast RC Oscillator (FRC) with Divide-by-n
110= Fast RC Oscillator (FRC) with Divide-by-16
101= Low-Power RC Oscillator (LPRC)
100= Reserved
011= Primary Oscillator (XT, HS, EC) with PLL
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)
000= Fast RC Oscillator (FRC)
bit 7
CLKLOCK: Clock Lock Enable bit
1= If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and
PLL configurations may be modified
0= Clock and PLL selections are not locked, configurations may be modified
bit 6
bit 5
IOLOCK: I/O Lock Enable bit
1= I/O lock is active
0= I/O lock is not active
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
Note 1: Writes to this register require an unlock sequence.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not
permitted. This applies to clock switches in either direction. In these instances, the application must switch
to FRC mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.
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REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit(3)
1= FSCM has detected a clock failure
0= FSCM has not detected a clock failure
bit 2-1
bit 0
Unimplemented: Read as ‘0’
OSWEN: Oscillator Switch Enable bit
1= Requests oscillator switch to the selection specified by the NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence.
2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not
permitted. This applies to clock switches in either direction. In these instances, the application must switch
to FRC mode as a transitional clock source between the two PLL modes.
3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an
actual oscillator failure and will trigger an oscillator failure trap.
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REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
ROI
bit 15
DOZE2(1)
DOZE1(1)
DOZE0(1)
DOZEN(2,3)
FRCDIV2
FRCDIV1
FRCDIV0
bit 8
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST1 PLLPOST0
bit 7
PLLPRE4
PLLPRE3
PLLPRE2
PLLPRE1
PLLPRE0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits(1)
111= FCY divided by 128
110= FCY divided by 64
101= FCY divided by 32
100= FCY divided by 16
011= FCY divided by 8 (default)
010= FCY divided by 4
001= FCY divided by 2
000= FCY divided by 1
bit 11
DOZEN: Doze Mode Enable bit(2,3)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock and peripheral clock ratio is forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
111= FRC divided by 256
110= FRC divided by 64
101= FRC divided by 32
100= FRC divided by 16
011= FRC divided by 8
010= FRC divided by 4
001= FRC divided by 2
000= FRC divided by 1 (default)
bit 7-6
bit 5
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
11= Output divided by 8
10= Reserved
01= Output divided by 4 (default)
00= Output divided by 2
Unimplemented: Read as ‘0’
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
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REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)
11111= Input divided by 33
•
•
•
00001= Input divided by 3
00000= Input divided by 2 (default)
Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to
DOZE<2:0> are ignored.
2: This bit is cleared when the ROI bit is set and an interrupt occurs.
3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to
set the DOZEN bit is ignored.
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PLLDIV8
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PLLDIV<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
111111111= 513
•
•
•
000110000= 50 (default)
•
•
•
000000010= 4
000000001= 3
000000000= 2
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REGISTER 9-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits
011111= Maximum frequency deviation of 1.457% (7.477 MHz)
011110= Center frequency + 1.41% (7.474 MHz)
•
•
•
000001= Center frequency + 0.047% (7.373 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency – 0.047% (7.367 MHz)
•
•
•
100001= Center frequency – 1.457% (7.263 MHz)
100000= Minimum frequency deviation of -1.5% (7.259 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither
characterized nor tested.
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REGISTER 9-5:
ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER
R/W-0
ENAPLL
bit 15
R-0
R/W-1
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
APLLCK
SELACLK
APSTSCLR2 APSTSCLR1 APSTSCLR0
bit 8
R/W-0
ASRCSEL
bit 7
R/W-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRCSEL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
ENAPLL: Auxiliary PLL Enable bit
1= APLL is enabled
0= APLL is disabled
APLLCK: APLL Locked Status bit (read-only)
1= Indicates that Auxiliary PLL is in lock
0= Indicates that Auxiliary PLL is not in lock
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit
1= Auxiliary oscillators provide the source clock for the auxiliary clock divider
0= Primary PLL (FVCO) provides the source clock for the auxiliary clock divider
bit 12-11
bit 10-8
Unimplemented: Read as ‘0’
APSTSCLR<2:0>: Auxiliary Clock Output Divider bits
111= Divided by 1
110= Divided by 2
101= Divided by 4
100= Divided by 8
011= Divided by 16
010= Divided by 32
001= Divided by 64
000= Divided by 256
bit 7
ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit
1= Primary oscillator is the clock source
0= No clock input is selected
bit 6
FRCSEL: Select Reference Clock Source for Auxiliary PLL bit
1= Selects the FRC clock for Auxiliary PLL
0= Input clock source is determined by the ASRCSEL bit setting
bit 5-0
Unimplemented: Read as ‘0’
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REGISTER 9-6:
REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER
R/W-0
ROON
bit 15
U-0
—
R/W-0
R/W-0
R/W-0
RODIV3(1)
R/W-0
RODIV2(1)
R/W-0
RODIV1(1)
R/W-0
RODIV0(1)
ROSSLP
ROSEL
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROON: Reference Oscillator Output Enable bit
1= Reference oscillator output is enabled on the RPn pin(2)
0= Reference oscillator output is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
ROSSLP: Reference Oscillator Run in Sleep bit
1= Reference oscillator output continues to run in Sleep
0= Reference oscillator output is disabled in Sleep
bit 12
ROSEL: Reference Oscillator Source Select bit
1= Oscillator crystal is used as the reference clock
0= System clock is used as the reference clock
bit 11-8
RODIV<3:0>: Reference Oscillator Divider bits(1)
1111= Reference clock divided by 32,768
1110= Reference clock divided by 16,384
1101= Reference clock divided by 8,192
1100= Reference clock divided by 4,096
1011= Reference clock divided by 2,048
1010= Reference clock divided by 1,024
1001= Reference clock divided by 512
1000= Reference clock divided by 256
0111= Reference clock divided by 128
0110= Reference clock divided by 64
0101= Reference clock divided by 32
0100= Reference clock divided by 16
0011= Reference clock divided by 8
0010= Reference clock divided by 4
0001= Reference clock divided by 2
0000= Reference clock
bit 7-0
Unimplemented: Read as ‘0’
Note 1: The reference oscillator output must be disabled (ROON = 0) before writing to these bits.
2: This pin is remappable. See Section 11.6 “Peripheral Pin Select (PPS)” for more information.
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REGISTER 9-7:
LFSR: LINEAR FEEDBACK SHIFT REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
LFSR<14:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LFSR<7:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
LFSR<14:0>: Pseudorandom Data bits
bit 14-0
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dsPIC33EPXXXGS70X/80X FAMILY
10.1 Clock Frequency and Clock
Switching
10.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to “Watchdog Timer and
Power-Saving Modes” (DS70615) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
The dsPIC33EPXXXGS70X/80X family devices allow a
wide range of clock frequencies to be selected under
application control. If the system clock configuration is not
locked, users can choose low-power or high-precision
oscillators by simply changing the NOSCx bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
10.2 Instruction-Based Power-Saving
Modes
The dsPIC33EPXXXGS70X/80X family devices have
two special power-saving modes that are entered
through the execution of a special PWRSAV instruc-
tion. Sleep mode stops clock operation and halts all
code execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 10-1.
The dsPIC33EPXXXGS70X/80X family devices
provide the ability to manage power consumption by
selectively managing clocking to the CPU and the
peripherals. In general, a lower clock frequency and
a reduction in the number of peripherals being
clocked constitutes lower consumed power.
Note: SLEEP_MODE and IDLE_MODE are con-
stants defined in the assembler include
file for the selected device.
dsPIC33EPXXXGS70X/80X family devices can
manage power consumption in four ways:
• Clock Frequency
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to “wake-up”.
• Instruction-Based Sleep and Idle modes
• Software-Controlled Doze mode
• Selective Peripheral Control in Software
Combinations of these methods can be used to
selectively tailor an application’s power consumption
while still maintaining critical application features, such
as timing-sensitive communications.
EXAMPLE 10-1:
PWRSAV INSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into Sleep mode
; Put the device into Idle mode
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10.2.1
SLEEP MODE
10.2.2
IDLE MODE
The following occurs in Sleep mode:
The following occurs in Idle mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
The device wakes from Idle mode on any of these
events:
• Some device features or peripherals can continue
to operate. This includes items such as the Input
Change Notification on the I/O ports or peripherals
that use an external clock input.
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (two to
four clock cycles later), starting with the instruction
following the PWRSAVinstruction or the first instruction
in the ISR.
• Any peripheral that requires the system clock
source for its operation is disabled.
The device wakes up from Sleep mode on any of the
these events:
• Any interrupt source that is individually enabled
• Any form of device Reset
All peripherals also have the option to discontinue
operation when Idle mode is entered to allow for
increased power savings. This option is selectable in
the control register of each peripheral (for example, the
TSIDL bit in the Timer1 Control register (T1CON<13>).
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
For optimal power savings, the internal regulator and
the Flash regulator can be configured to go into stand-
by when Sleep mode is entered by clearing the VREGS
(RCON<8>) and VREGSF (RCON<11>) bits (default
configuration).
Any interrupt that coincides with the execution of a
PWRSAVinstruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
If the application requires a faster wake-up time, and
can accept higher current requirements, the VREGS
(RCON<8>) and VREGSF (RCON<11>) bits can be set
to keep the internal regulator and the Flash regulator
active during Sleep mode.
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10.3 Doze Mode
10.4 Peripheral Module Disable
The preferred strategies for reducing power consump-
tion are changing clock speed and invoking one of the
power-saving modes. In some circumstances, this
cannot be practical. For example, it may be necessary
for an application to maintain uninterrupted synchro-
nous communication, even while it is doing nothing
else. Reducing system clock speed can introduce
communication errors, while using a power-saving
mode can stop communications completely.
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have any effect and
read values are invalid.
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
A peripheral module is enabled only if both the associ-
ated bit in the PMD register is cleared and the peripheral
is supported by the specific dsPIC® DSC variant. If the
peripheral is present in the device, it is enabled in the
PMD register by default.
Note:
If a PMD bit is set, the corresponding
module is disabled after a delay of one
instruction cycle. Similarly, if a PMD bit is
cleared, the corresponding module is
enabled after a delay of one instruction
cycle (assuming the module control regis-
ters are already configured to enable
module operation).
Doze mode is enabled by setting the DOZEN bit
(CLKDIV<11>). The ratio between peripheral and core
clock speed is determined by the DOZE<2:0> bits
(CLKDIV<14:12>). There are eight possible configu-
rations, from 1:1 to 1:128, with 1:1 being the default
setting.
10.5 Power-Saving Resources
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU Idles, waiting for something to invoke an inter-
rupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
10.5.1
KEY RESOURCES
• “Watchdog Timer and Power-Saving Modes”
(DS70615) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2016-2018 Microchip Technology Inc.
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REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0
T5MD
R/W-0
T4MD
R/W-0
T3MD
R/W-0
T2MD
R/W-0
T1MD
U-0
—
R/W-0
U-0
—
PWMMD
bit 15
bit 8
R/W-0
R/W-0
U2MD
R/W-0
U1MD
R/W-0
R/W-0
R/W-0
C2MD
R/W-0
C1MD
R/W-0
I2C1MD
SPI2MD
SPI1MD
ADCMD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
T5MD: Timer5 Module Disable bit
1= Timer5 module is disabled
0= Timer5 module is enabled
T4MD: Timer4 Module Disable bit
1= Timer4 module is disabled
0= Timer4 module is enabled
T3MD: Timer3 Module Disable bit
1= Timer3 module is disabled
0= Timer3 module is enabled
T2MD: Timer2 Module Disable bit
1= Timer2 module is disabled
0= Timer2 module is enabled
T1MD: Timer1 Module Disable bit
1= Timer1 module is disabled
0= Timer1 module is enabled
bit 10
bit 9
Unimplemented: Read as ‘0’
PWMMD: PWM Module Disable bit
1= PWM module is disabled
0= PWM module is enabled
bit 8
bit 7
Unimplemented: Read as ‘0’
I2C1MD: I2C1 Module Disable bit
1= I2C1 module is disabled
0= I2C1 module is enabled
bit 6
bit 5
bit 4
bit 3
bit 2
U2MD: UART2 Module Disable bit
1= UART2 module is disabled
0= UART2 module is enabled
U1MD: UART1 Module Disable bit
1= UART1 module is disabled
0= UART1 module is enabled
SPI2MD: SPI2 Module Disable bit
1= SPI2 module is disabled
0= SPI2 module is enabled
SPI1MD: SPI1 Module Disable bit
1= SPI1 module is disabled
0= SPI1 module is enabled
C2MD: CAN2 Module Disable bit
1= CAN2 module is disabled
0= CAN2 module is enabled
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2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1 (CONTINUED)
bit 1
C1MD: CAN1 Module Disable bit
1= CAN1 module is disabled
0= CAN1 module is enabled
bit 0
ADCMD: ADC Module Disable bit
1= ADC module is disabled
0= ADC module is enabled
2016-2018 Microchip Technology Inc.
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REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IC4MD
IC3MD
IC2MD
IC1MD
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11
Unimplemented: Read as ‘0’
IC4MD: Input Capture 4 Module Disable bit
1= Input Capture 4 module is disabled
0= Input Capture 4 module is enabled
bit 10
bit 9
bit 8
IC3MD: Input Capture 3 Module Disable bit
1= Input Capture 3 module is disabled
0= Input Capture 3 module is enabled
IC2MD: Input Capture 2 Module Disable bit
1= Input Capture 2 module is disabled
0= Input Capture 2 module is enabled
IC1MD: Input Capture 1 Module Disable bit
1= Input Capture 1 module is disabled
0= Input Capture 1 module is enabled
bit 7-4
bit 3
Unimplemented: Read as ‘0’
OC4MD: Output Compare 4 Module Disable bit
1= Output Compare 4 module is disabled
0= Output Compare 4 module is enabled
bit 2
bit 1
bit 0
OC3MD: Output Compare 3 Module Disable bit
1= Output Compare 3 module is disabled
0= Output Compare 3 module is enabled
OC2MD: Output Compare 2 Module Disable bit
1= Output Compare 2 module is disabled
0= Output Compare 2 module is enabled
OC1MD: Output Compare 1 Module Disable bit
1= Output Compare 1 module is disabled
0= Output Compare 1 module is enabled
DS70005258C-page 122
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dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
CMPMD
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
I2C2MD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10
Unimplemented: Read as ‘0’
CMPMD: Comparator Module Disable bit
1= Comparator module is disabled
0= Comparator module is enabled
bit 9-2
bit 1
Unimplemented: Read as ‘0’
I2C2MD: I2C2 Module Disable bit
1= I2C2 module is disabled
0= I2C2 module is enabled
bit 0
Unimplemented: Read as ‘0’
REGISTER 10-4: PMD4: PERIPHERAL MODULE DISABLE CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
REFOMD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
REFOMD: Reference Clock Module Disable bit
1= Reference clock module is disabled
0= Reference clock module is enabled
bit 2-0
Unimplemented: Read as ‘0’
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dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 10-5: PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWM8MD
PWM7MD
PWM6MD
PWM5MD
PWM4MD
PWM3MD
PWM2MD
PWM1MD
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
SPI3MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
PWM8MD: PWM8 Module Disable bit
1= PWM8 module is disabled
0= PWM8 module is enabled
PWM7MD: PWM7 Module Disable bit
1= PWM7 module is disabled
0= PWM7 module is enabled
PWM6MD: PWM6 Module Disable bit
1= PWM6 module is disabled
0= PWM6 module is enabled
PWM5MD: PWM5 Module Disable bit
1= PWM5 module is disabled
0= PWM5 module is enabled
PWM4MD: PWM4 Module Disable bit
1= PWM4 module is disabled
0= PWM4 module is enabled
PWM3MD: PWM3 Module Disable bit
1= PWM3 module is disabled
0= PWM3 module is enabled
PWM2MD: PWM2 Module Disable bit
1= PWM2 module is disabled
0= PWM2 module is enabled
bit 8
PWM1MD: PWM1 Module Disable bit
1= PWM1 module is disabled
0= PWM1 module is enabled
bit 7-1
bit 0
Unimplemented: Read as ‘0’
SPI3MD: SPI3 Module Disable bit
1= SPI3 module is disabled
0= SPI3 module is enabled
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dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 10-6: PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
CMP4MD
CMP3MD
CMP2MD
CMP1MD
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
U-0
—
DMAMD
PTGMD
PGA1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11
Unimplemented: Read as ‘0’
CMP4MD: CMP4 Module Disable bit
1= CMP4 module is disabled
0= CMP4 module is enabled
bit 10
bit 9
bit 8
CMP3MD: CMP3 Module Disable bit
1= CMP3 module is disabled
0= CMP3 module is enabled
CMP2MD: CMP2 Module Disable bit
1= CMP2 module is disabled
0= CMP2 module is enabled
CMP1MD: CMP1 Module Disable bit
1= CMP1 module is disabled
0= CMP1 module is enabled
bit 7-5
bit 4
Unimplemented: Read as ‘0’
DMAMD: DMA Module Disable bit
1= DMA module is disabled
0= DMA module is enabled
bit 3
PTGMD: PTG Module Disable bit
1= PTG module is disabled
0= PTG module is enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
PGA1MD: PGA1 Module Disable bit
1= PGA1 module is disabled
0= PGA1 module is enabled
bit 0
Unimplemented: Read as ‘0’
2016-2018 Microchip Technology Inc.
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REGISTER 10-7: PMD8: PERIPHERAL MODULE DISABLE CONTROL REGISTER 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
PGA2MD
bit 15
bit 8
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
CLC4MD
CLC3MD
CLC2MD
CLC1MD
CCSMD
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10
Unimplemented: Read as ‘0’
PGA2MD: PGA2 Module Disable bit
1= PGA2 module is disabled
0= PGA2 module is enabled
bit 9-6
bit 5
Unimplemented: Read as ‘0’
CLC4MD: CLC4 Module Disable bit
1= CLC4 module is disabled
0= CLC4 module is enabled
bit 4
bit 3
bit 2
bit 1
bit 0
CLC3MD: CLC3 Module Disable bit
1= CLC3 module is disabled
0= CLC3 module is enabled
CLC2MD: CLC2 Module Disable bit
1= CLC2 module is disabled
0= CLC2 module is enabled
CLC1MD: CLC1 Module Disable bit
1= CLC1 module is disabled
0= CLC1 module is enabled
CCSMD: Constant-Current Source Module Disable bit
1= Constant-current source module is disabled
0= Constant-current source module is enabled
Unimplemented: Read as ‘0’
DS70005258C-page 126
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dsPIC33EPXXXGS70X/80X FAMILY
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 illus-
11.0 I/O PORTS
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “I/O Ports” (DS70000598) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
trates how ports are shared with other peripherals and
the associated I/O pin to which they are connected.
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as a
general purpose output pin is disabled. The I/O pin can
be read, but the output driver for the parallel port bit is
disabled. If a peripheral is enabled, but the peripheral is
not actively driving a pin, that pin can be driven by a port.
All port pins have eight registers directly associated with
their operation as digital I/Os. The Data Direction register
(TRISx) determines whether the pin is an input or an out-
put. If the data direction bit is a ‘1’, then the pin is an input.
All port pins are defined as inputs after a Reset. Reads
from the latch (LATx), read the latch. Writes to the latch,
write the latch. Reads from the port (PORTx), read the
port pins, while writes to the port pins, write the latch.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Many of the device pins are shared among the periph-
erals and the Parallel I/O ports. All I/O input ports feature
Schmitt Trigger inputs for improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device are disabled.
This means the corresponding LATx and TRISx
registers, and the port pin are read as zeros. Table 11-1
through Table 11-5 show ANSELx bits’ availability for
device variants.
11.1 Parallel I/O (PIO) Ports
Generally, a Parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through”, in
When a pin is shared with another peripheral or func-
tion that is defined as an input only, it is nevertheless
regarded as a dedicated port because there is no
other competing source of outputs.
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Peripheral Module
Output Multiplexers
Peripheral Input Data
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
I/O
1
0
Output Enable
Output Data
1
0
PIO Module
Read TRISx
Data Bus
D
Q
I/O Pin
WR TRISx
CK
TRISx Latch
D
Q
WR LATx +
WR PORTx
CK
Data Latch
Read LATx
Input Data
Read PORTx
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TABLE 11-1: PORTA PIN AND ANSELA AVAILABILITY
PORTA I/O Pins
RA15 RA14 RA13 RA12 RA11 RA10 RA9 RA8 RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0
Device
dsPIC33EPXXXGSX08
dsPIC33EPXXXGSX06
dsPIC33EPXXXGSX05
dsPIC33EPXXXGSX04
dsPIC33EPXXXGS702
ANSELA Bit Present
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
TABLE 11-2: PORTB PIN AND ANSELB AVAILABILITY
PORTB I/O Pins
RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
Device
dsPIC33EPXXXGSX08
dsPIC33EPXXXGSX06
dsPIC33EPXXXGSX05
dsPIC33EPXXXGSX04
dsPIC33EPXXXGS702
ANSELB Bit Present
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
TABLE 11-3: PORTC PIN AND ANSELC AVAILABILITY
PORTC I/O Pins
RC15 RC14 RC13 RC12 RC11 RC10 RC9 RC8 RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0
Device
dsPIC33EPXXXGSX08
dsPIC33EPXXXGSX06
dsPIC33EPXXXGSX05
dsPIC33EPXXXGSX04
dsPIC33EPXXXGS702
ANSELC Bit Present
X
X
X
X
X
X
X
X
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
—
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
X
—
X
—
X
—
—
—
—
—
X
—
X
—
X
—
—
—
X
—
X
—
—
TABLE 11-4: PORTD PIN AND ANSELD AVAILABILITY
PORTD I/O Pins
RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0
Device
dsPIC33EPXXXGSX08
dsPIC33EPXXXGSX06
dsPIC33EPXXXGSX05
dsPIC33EPXXXGSX04
dsPIC33EPXXXGS702
ANSELD Bit Present
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
—
X
—
—
—
X
—
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
X
—
—
—
X
—
—
—
—
—
—
—
X
X
—
—
—
—
—
—
—
X
—
—
—
—
—
—
—
—
X
X
X
—
—
—
—
—
—
TABLE 11-5: PORTE PIN AND ANSELE AVAILABILITY
PORTE I/O Pins
RE15 RE14 RE13 RE12 RE11 RE10 RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0
Device
dsPIC33EPXXXGSX08
dsPIC33EPXXXGSX06
dsPIC33EPXXXGSX05
dsPIC33EPXXXGSX04
dsPIC33EPXXXGS702
ANSELE Bit Present
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DS70005258C-page 128
2016-2018 Microchip Technology Inc.
11.2 I/O Port Control Register Maps
TABLE 11-6: PORTA REGISTER MAP(1)
File
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA<4:0>
RA<4:0>
PORTA
LATA
LATA<4:0>
ODCA<4:0>
CNIEA<4:0>
CNPUA<4:0>
CNPDA<4:0>
ODCA
CNENA
CNPUA
CNPDA
ANSELA
—
—
ANSA<2:0>
Legend: — = unimplemented, read as ‘0’.
Note 1: Refer to Table 11-1 for bit availability on each pin count variant.
TABLE 11-7: PORTB REGISTER MAP(1)
File
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
TRISB<15:11>
RB<15:11>
—
—
—
—
—
—
—
—
TRISB<9:0>
RB<9:0>
PORTB
LATB
LATB<15:11>
ODCB<15:11>
CNIEB<15:11>
CNPUB<15:11>
CNPDB<15:11>
—
LATB<9:0>
ODCB<9:0>
CNIEB<9:0>
ODCB
CNENB
CNPUB
CNPDB
ANSELB
CNPUB<9:0>
CNPDB<9:0>
—
—
—
—
ANSB9
—
ANSB<7:5>
—
ANSB<3:0>
Legend: — = unimplemented, read as ‘0’.
Note 1: Refer to Table 11-2 for bit availability on each pin count variant.
TABLE 11-8: PORTC REGISTER MAP(1)
File
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISC
TRISC<15:12>
RC<15:12>
—
—
—
—
—
—
—
—
TRISC<10:0>
RC<10:0>
PORTC
LATC
LATC<15:12>
ODCC<15:12>
CNIEC<15:12>
CNPUC<15:12>
CNPDC<15:12>
LATC<10:0>
ODCC<10:0>
CNIEC<10:0>
CNPUC<10:0>
CNPDC<10:0>
ANSC<6:4>
ODCC
CNENC
CNPUC
CNPDC
ANSELC
—
—
—
ANSC12
ANSC<10:9>
—
—
—
ANSC<2:1>
—
Legend: — = unimplemented, read as ‘0’.
Note 1: Refer to Table 11-3 for bit availability on each pin count variant.
TABLE 11-9: PORTD REGISTER MAP(1)
File
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISD
TRISD<15:0>
RD<15:0>
PORTD
LATD
LATD<15:0>
ODCD<15:0>
CNIED<15:0>
CNPUD<15:0>
CNPDD<15:0>
ANSD<8:7>
ODCD
CNEND
CNPUD
CNPDD
ANSELD
—
—
ANSD13
—
—
—
—
—
ANSD5
—
—
ANSD2
—
—
Legend: — = unimplemented, read as ‘0’.
Note 1: Refer to Table 11-4 for bit availability on each pin count variant.
TABLE 11-10: PORTE REGISTER MAP(1)
File
Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISE
TRISE<15:0>
RE<15:0>
PORTE
LATE
LATE<15:0>
ODCE<15:0>
CNIEE<15:0>
CNPUE<15:0>
CNPDE<15:0>
ODCE
CNENE
CNPUE
CNPDE
ANSELE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Legend: — = unimplemented, read as ‘0’.
Note 1: Refer to Table 11-5 for bit availability on each pin count variant.
dsPIC33EPXXXGS70X/80X FAMILY
11.2.1
OPEN-DRAIN CONFIGURATION
11.3.1
I/O PORT WRITE/READ TIMING
In addition to the PORTx, LATx and TRISx registers
for data control, port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control x register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically, this instruction
would be a NOP, as shown in Example 11-1.
11.4 Input Change Notification (ICN)
The Input Change Notification function of the I/O ports
allows devices to generate interrupt requests to the
processor in response to a Change-of-State (COS) on
selected input pins. This feature can detect input
Change-of-States, even in Sleep mode, when the
clocks are disabled. Every I/O port pin can be selected
(enabled) for generating an interrupt request on a
Change-of-State.
The open-drain feature allows the generation of out-
puts other than VDD by using external pull-up resistors.
The maximum open-drain voltage allowed on any pin
is the same as the maximum VIH specification for that
particular pin. See the “Pin Diagrams” section for the
available 5V tolerant pins and Table 30-11 for the
maximum VIH specification for each pin.
Three control registers are associated with the ICN
functionality of each I/O port. The CNENx registers
contain the ICN interrupt enable control bits for each of
the input pins. Setting any of these bits enables an ICN
interrupt for the corresponding pins.
11.3 Configuring Analog and Digital
Port Pins
The ANSELx register controls the operation of the
analog port pins. The port pins that are to function as
analog inputs or outputs must have their corresponding
ANSELx and TRISx bits set. In order to use port pins for
I/O functionality with digital modules, such as timers,
UARTs, etc., the corresponding ANSELx bit must be
cleared.
Each I/O pin also has a weak pull-up and a weak
pull-down connected to it. The pull-ups and pull-
downs act as a current source, or sink source,
connected to the pin, and eliminate the need for
external resistors when push button or keypad
devices are connected. The pull-ups and pull-downs
are enabled separately, using the CNPUx and the
CNPDx registers, which contain the control bits for
each of the pins. Setting any of the control bits
enables the weak pull-ups and/or pull-downs for the
corresponding pins.
The ANSELx register has a default value of 0xFFFF;
therefore, all pins that share analog functions are
analog (not digital) by default.
Pins with analog functions affected by the ANSELx
registers are listed with a buffer type of analog in the
Pinout I/O Descriptions (see Table 1-1). Table 11-1
through Table 11-5 show ANSELx bits’ availability for
device variants.
Note:
Pull-ups and pull-downs on Input Change
Notification pins should always be
disabled when the port pin is configured
as a digital output.
If the TRISx bit is cleared (output) while the ANSELx bit
is set, the digital output level (VOH or VOL) is converted
by an analog peripheral, such as the ADC module or
comparator module.
EXAMPLE 11-1:
PORT WRITE/READ
EXAMPLE
When the PORTx register is read, all pins configured as
analog input channels are read as cleared (a low level).
MOV
MOV
NOP
0xFF00, W0
W0, TRISB
; Configure PORTB<15:8>
; as inputs
; and PORTB<7:0>
; as outputs
; Delay 1 cycle
; Next Instruction
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin, defined as a
digital input (including the ANx pins), can cause the
input buffer to consume current that exceeds the
device specifications.
BTSS PORTB, #13
DS70005258C-page 132
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
11.5 I/O Port Control Registers
REGISTER 11-1: TRISx: PORTx DATA DIRECTION CONTROL REGISTER(1)
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
TRISx<15:8>
bit 15
R/W-1
bit 7
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
TRISx<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
TRISx<15:0>: PORTx Data Direction Control bits
1= The pin is an input
0= The pin is an output
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-2: PORTx: I/O PORTx REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PORTx<15:8>
R/W-0
R/W-0
R/W-0
PORTx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
PORTx<15:0>: I/O PORTx bits
1= The pin data is ‘1’
0= The pin data is ‘0’
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
2016-2018 Microchip Technology Inc.
DS70005258C-page 133
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 11-3: LATx: PORTx DATA LATCH REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
LATx<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
LATx<7:0>
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
LATx<15:0>: PORTx Data Latch bits
1= The latch content is ‘1’
0= The latch content is ‘0’
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-4: ODCx: PORTx OPEN-DRAIN CONTROL REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
ODCx<15:8>
R/W-0
R/W-0
R/W-0
ODCx<7:0>
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
PORTx<15:0>: PORTx Open-Drain Control bits
1= The pin acts as an open-drain output pin if TRISx is ‘0’
0= The pin acts as a normal pin
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
DS70005258C-page 134
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 11-5: CNENx: INPUT CHANGE NOTIFICATION INTERRUPT ENABLE x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNIEx<15:8>
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
CNIEx<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
CNIEx<15:0>: Input Change Notification Interrupt Enable x bits
1= Enables interrupt on input change
0= Disables interrupt on input change
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-6: CNPUx: INPUT CHANGE NOTIFICATION PULL-UP ENABLE x REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
CNPUx<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNPUx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
CNPUx<15:0>: Input Change Notification Pull-up Enable bits
1= Enables pull-up on PORTx pin
0= Disables pull-up on PORTx pin
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
2016-2018 Microchip Technology Inc.
DS70005258C-page 135
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 11-7: CNPDx: INPUT CHANGE NOTIFICATION PULL-DOWN ENABLE x REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CNPDx<15:8>
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
CNPDx<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
CNPDx<15:0>: Input Change Notification Pull-Down Enable x bits
1= Enables pull-down on PORTx pin
0= Disables pull-down on PORTx pin
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
REGISTER 11-8: ANSELx: ANALOG SELECT CONTROL x REGISTER(1)
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
ANSx<15:8>
R/W-1
R/W-1
R/W-1
ANSx<7:0>
R/W-1
R/W-1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
ANSx<15:0>: Analog PORTx Enable bits
1= Enables analog PORTx pin
0= Enables digital PORTx pin
Note 1: See Table 11-1, Table 11-2, Table 11-3, Table 11-4 and Table 11-5 for individual bit availability in this register.
DS70005258C-page 136
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
In comparison, some digital only peripheral modules
11.6 Peripheral Pin Select (PPS)
are never included in the Peripheral Pin Select feature.
This is because the peripheral’s function requires
special I/O circuitry on a specific port and cannot be
easily connected to multiple pins. One example
includes I2C modules. A similar requirement excludes
all modules with analog inputs, such as the ADC
Converter.
A major challenge in general purpose devices is
providing the largest possible set of peripheral features,
while minimizing the conflict of features on I/O pins.
The challenge is even greater on low pin count devices.
In an application where more than one peripheral
needs to be assigned to a single pin, inconvenient
work arounds in application code, or a complete
redesign, may be the only option.
A key difference between remappable and non-
remappable peripherals is that remappable peripherals
are not associated with a default I/O pin. The peripheral
must always be assigned to a specific I/O pin before it
can be used. In contrast, non-remappable peripherals
are always available on a default pin, assuming that the
peripheral is active and not conflicting with another
peripheral.
Peripheral Pin Select configuration provides an alter-
native to these choices by enabling peripheral set
selection and placement on a wide range of I/O pins.
By increasing the pinout options available on a particu-
lar device, users can better tailor the device to their
entire application, rather than trimming the application
to fit the device.
When a remappable peripheral is active on a given I/O
pin, it takes priority over all other digital I/Os and digital
communication peripherals associated with the pin.
Priority is given regardless of the type of peripheral that
is mapped. Remappable peripherals never take priority
over any analog functions associated with the pin.
The Peripheral Pin Select configuration feature
operates over a fixed subset of digital I/O pins. Users
may independently map the input and/or output of most
digital peripherals to any one of these I/O pins. Hard-
ware safeguards are included that prevent accidental
or spurious changes to the peripheral mapping once it
has been established.
11.6.3
CONTROLLING PERIPHERAL PIN
SELECT
11.6.1
AVAILABLE PINS
Peripheral Pin Select features are controlled through
two sets of SFRs: one to map peripheral inputs and one
to map outputs. Because they are separately con-
trolled, a particular peripheral’s input and output (if the
peripheral has both) can be placed on any selectable
function pin without constraint.
The number of available pins is dependent on the par-
ticular device and its pin count. Pins that support the
Peripheral Pin Select feature include the label, “RPn”,
in their full pin designation, where “n” is the remappable
pin number. “RP” is used to designate pins that support
both remappable input and output functions.
The association of a peripheral to a peripheral-
selectable pin is handled in two different ways,
depending on whether an input or output is being
mapped.
11.6.2
AVAILABLE PERIPHERALS
The peripherals managed by the Peripheral Pin Select
are all digital only peripherals. These include general
serial communications (UART and SPI), general pur-
pose timer clock inputs, timer-related peripherals (input
capture and output compare) and interrupt-on-change
inputs.
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11.6.4
INPUT MAPPING
11.6.4.1
Virtual Connections
The inputs of the Peripheral Pin Select options are
mapped on the basis of the peripheral. That is, a control
register associated with a peripheral dictates the pin it
will be mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-9
through Register 11-32). Each register contains sets of
8-bit fields, with each set associated with one of the
remappable peripherals. Programming a given periph-
eral’s bit field with an appropriate 8-bit index value maps
the RPn pin with the corresponding value, or internal
signal, to that peripheral. See Table 11-11 for a list of
available inputs.
The dsPIC33EPXXXGS70X/80X devices support six
virtual RPn pins (RP176-RP181), which are identical in
functionality to all other RPn pins, with the exception of
pinouts. These six pins are internal to the devices and
are not connected to a physical device pin.
These pins provide a simple way for inter-peripheral
connection without utilizing a physical pin. For
example, the output of the analog comparator can be
connected to RP176 and the PWM Fault input can be
configured for RP176 as well. This configuration allows
the analog comparator to trigger PWM Faults without
the use of an actual physical pin on the device.
For example, Figure 11-2 illustrates remappable pin
selection for the U1RX input.
TABLE 11-11: REMAPPABLE SOURCES
Remap Index
Output Function
FIGURE 11-2:
REMAPPABLE INPUT FOR
U1RX
0
1
VSS
CMP1
U1RXR<7:0>
0
2
CMP2
VSS
3
CMP3
4
CMP4
5
PWM4H
PWM4L
15
6
PTGO30
PTGO31
Reserved
REFO
U1RX Input
to Peripheral
7
8-11
12
16
RP16
13
SYNCO1
SYNCO2
PWM4L
14
181
15
RP181
16-20
21-31
32-41
42
RP16-RP20
Reserved
RP32-RP41
Reserved
RP43-RP58
Reserved
RP60-RP76
Reserved
RP176-RP181
Note:
For input only, Peripheral Pin Select func-
tionality does not have priority over TRISx
settings. Therefore, when configuring an
RPn pin for input, the corresponding bit in
the TRISx register must also be configured
for input (set to ‘1’).
43-58
59
60-76
77-175
176-181
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 11-12: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)
Input Name(1)
Function Name
Register
Configuration Bits
External Interrupt 1
INT1
INT2
RPINR0
RPINR1
INT1R<7:0>
INT2R<7:0>
T1CKR<7:0>
T2CKR<7:0>
T3CKR<7:0>
IC1R<7:0>
External Interrupt 2
Timer1 External Clock
Timer2 External Clock
Timer3 External Clock
Input Capture 1
Input Capture 2
Input Capture 3
Input Capture 4
Output Compare Fault A
PWM Fault 1
T1CK
T2CK
T3CK
IC1
RPINR2
RPINR3
RPINR3
RPINR7
IC2
RPINR7
IC2R<7:0>
IC3
RPINR8
IC3R<7:0>
IC4
RPINR8
IC4R<7:0>
OCFA
FLT1
FLT2
FLT3
FLT4
U1RX
U1CTS
U2RX
U2CTS
SDI1
RPINR11
RPINR12
RPINR12
RPINR13
RPINR13
RPINR18
RPINR18
RPINR19
RPINR19
RPINR20
RPINR20
RPINR21
PRINR26
PRINR26
RPINR29
RPINR29
RPINR30
RPINR22
RPINR22
RPINR23
RPINR37
RPINR38
RPINR42
RPINR42
RPINR43
RPINR43
RPINR45
RPINR46
OCFAR<7:0>
FLT1R<7:0>
FLT2R<7:0>
FLT3R<7:0>
FLT4R<7:0>
U1RXR<7:0>
U1CTSR<7:0>
U2RXR<7:0>
U2CTSR<7:0>
SDI1R<7:0>
SCK1R<7:0>
SS1R<7:0>
PWM Fault 2
PWM Fault 3
PWM Fault 4
UART1 Receive
UART1 Clear-to-Send
UART2 Receive
UART2 Clear-to-Send
SPI1 Data Input
SPI1 Clock Input
SPI1 Slave Select
CAN1 Receive
SCK1
SS1
C1RX
C2RX
SDI3
C1RXR<7:0>
C2RXR<7:0>
SDI3R<7:0>
SCK3R<7:0>
SS3R<7:0>
CAN2 Receive
SPI3 Data Input
SPI3 Clock Input
SPI3 Slave Select
SPI2 Data Input
SPI2 Clock Input
SPI2 Slave Select
PWM Synchronous Input 1
PWM Synchronous Input 2
PWM Fault 5
SCK3
SS3
SDI2
SDI2R<7:0>
SCK2R<7:0>
SS2R<7:0>
SCK2
SS2
SYNCI1
SYNCI2
FLT5
FLT6
FLT7
FLT8
CLCINA
CLCINB
SYNCI1R<7:0>
SYNCI2R<7:0>
FLT5R<7:0>
FLT6R<7:0>
FLT7R<7:0>
FLT8R<7:0>
CLCINA<7:0>
CLCINB<7:0>
PWM Fault 6
PWM Fault 7
PWM Fault 8
CLC Input A
CLC Input B
Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.
2016-2018 Microchip Technology Inc.
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11.6.5
OUTPUT MAPPING
11.6.5.1
Mapping Limitations
In contrast to inputs, the outputs of the Peripheral Pin
Select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Each register contains sets of 6-bit fields, with each set
associated with one RPn pin (see Register 11-33
through Register 11-56). The value of the bit field cor-
responds to one of the peripherals and that peripheral’s
output is mapped to the pin (see Table 11-13 and
Figure 11-3).
The control schema of the peripheral select pins is not
limited to a small range of fixed peripheral configura-
tions. There are no mutual or hardware-enforced
lockouts between any of the peripheral mapping SFRs.
Literally any combination of peripheral mappings,
across any or all of the RPn pins, is possible. This
includes both many-to-one and one-to-many mappings
of peripheral inputs, and outputs to pins. While such
mappings may be technically possible from a configu-
ration point of view, they may not be supportable from
an electrical point of view.
A null output is associated with the output register
Reset value of ‘0’. This is done to ensure that remap-
pable outputs remain disconnected from all output pins
by default.
FIGURE 11-3: MULTIPLEXING REMAPPABLE
OUTPUTS FOR RPn
RPnR<6:0>
Default
0
U1TX Output
1
SDO2 Output
2
RPn
Output Data
CLC3OUT Output
65
CLC4OUT Output
66
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TABLE 11-13: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)
Function
Default PORT
RPnR<6:0>
Output Name
0000000
0000001
0000010
0000011
0000100
0000101
0000110
0000111
0001000
0001001
0001010
0001110
0001111
0010000
0010001
0010010
0010011
0011000
0011001
0011010
0011111
0100000
0100001
0101101
0101110
0110001
0110010
0110011
0110100
0110101
0110110
0111001
0111010
0111011
0111100
0111101
0111110
0111111
1000000
1000001
1000010
RPn tied to Default Pin
U1TX
RPn tied to UART1 Transmit
U1RTS
U2TX
RPn tied to UART1 Request-to-Send
RPn tied to UART2 Transmit
U2RTS
SDO1
RPn tied to UART2 Request-to-Send
RPn tied to SPI1 Data Output
SCK1
RPn tied to SPI1 Clock Output
SS1
RPn tied to SPI1 Slave Select
SDO2
RPn tied to SPI2 Data Output
SCK2
RPn tied to SPI2 Clock Output
SS2
RPn tied to SPI2 Slave Select
C1TX
RPn tied to CAN1 Transmit
C2TX
RPn tied to CAN2 Transmit
OC1
RPn tied to Output Compare 1 Output
OC2
RPn tied to Output Compare 2 Output
OC3
RPn tied to Output Compare 3 Output
OC4
RPn tied to Output Compare 4 Output
ACMP1
ACMP2
ACMP3
SDO3
RPn tied to Analog Comparator 1 Output
RPn tied to Analog Comparator 2 Output
RPn tied to Analog Comparator 3 Output
RPn tied to SPI3 Data Output
SCK3
RPn tied to SPI3 Clock Output
SS3
RPn tied to SPI3 Slave Select
SYNCO1
SYNCO2
REFCLKO
ACMP4
PWM4H
PWM4L
PWM5H
PWM5L
PWM6H
PWM6L
PWM7H
PWM7L
PWM8H
PWM8L
CLC1OUT
CLC2OUT
CLC3OUT(1)
CLC4OUT(1)
RPn tied to PWM Primary Master Time Base Sync Output
RPn tied to PWM Secondary Master Time Base Sync Output
RPn tied to Reference Clock Output
RPn tied to Analog Comparator 4 Output
RPn tied to PWM Output Pins Associated with PWM Generator 4
RPn tied to PWM Output Pins Associated with PWM Generator 4
RPn tied to PWM Output Pins Associated with PWM Generator 5
RPn tied to PWM Output Pins Associated with PWM Generator 5
RPn tied to PWM Output Pins Associated with PWM Generator 6
RPn tied to PWM Output Pins Associated with PWM Generator 6
RPn tied to PWM Output Pins Associated with PWM Generator 7
RPn tied to PWM Output Pins Associated with PWM Generator 7
RPn tied to PWM Output Pins Associated with PWM Generator 8
RPn tied to PWM Output Pins Associated with PWM Generator 8
RPn tied to CLC1 Output
RPn tied to CLC2 Output
RPn tied to CLC3 Output
RPn tied to CLC4 Output
Note 1: PPS outputs are only available on dsPIC33EPXXXGS702 (28-pin) devices.
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3. Most I/O pins have multiple functions. Referring to
11.7 I/O Helpful Tips
the device pin diagrams in this data sheet, the prior-
ities of the functions allocated to any pins are
indicated by reading the pin name from left-to-right.
The left most function name takes precedence over
any function to its right in the naming convention.
For example: AN16/T2CK/T7CK/RC1; this indi-
cates that AN16 is the highest priority in this
example and will supersede all other functions to its
right in the list. Those other functions to its right,
even if enabled, would not work as long as any
other function to its left was enabled. This rule
applies to all of the functions listed for a given pin.
1. In some cases, certain pins, as defined in
Table 30-11 under “Injection Current”, have internal
protection diodes to VDD and VSS. The term,
“Injection Current”, is also referred to as “Clamp
Current”. On designated pins, with sufficient external
current-limiting precautions by the user, I/O pin
input voltages are allowed to be greater or less
than the data sheet absolute maximum ratings,
with respect to the VSS and VDD supplies. Note
that when the user application forward biases
either of the high or low-side internal input clamp
diodes, that the resulting current being injected
into the device, that is clamped internally by the
VDD and VSS power rails, may affect the ADC
accuracy by four to six counts.
4. Each pin has an internal weak pull-up resistor and
pull-down resistor that can be configured using the
CNPUx and CNPDx registers, respectively. These
resistors eliminate the need for external resistors
in certain applications. The internal pull-up is up to
~(VDD – 0.8), not VDD. This value is still above the
minimum VIH of CMOS and TTL devices.
2. I/O pins that are shared with any analog input pin
(i.e., ANx) are always analog pins, by default, after
any Reset. Consequently, configuring a pin as an
analog input pin automatically disables the digital
input pin buffer and any attempt to read the digital
input level by reading PORTx or LATx will always
return a ‘0’, regardless of the digital logic level on
the pin. To use a pin as a digital I/O pin on a shared
ANx pin, the user application needs to configure the
Analog Pin Configuration registers (i.e., ANSELx) in
the I/O ports module by setting the appropriate bit
that corresponds to that I/O port pin to a ‘0’.
5. When driving LEDs directly, the I/O pin can source
or sink more current than what is specified in the
VOH/IOH and VOL/IOL DC characteristics specifica-
tion. The respective IOH and IOL current rating only
applies to maintaining the corresponding output at
or above the VOH, and at or below the VOL levels.
However, for LEDs, unlike digital inputs of an exter-
nally connected device, they are not governed by
the same minimum VIH/VIL levels. An I/O pin output
can safely sink or source any current less than that
listed in the Absolute Maximum Ratings in
Section 30.0 “Electrical Characteristics”of this
data sheet. For example:
Note:
Although it is not possible to use a digital
input pin when its analog function is
enabled, it is possible to use the digital I/O
output function, TRISx = 0x0, while the
analog function is also enabled. However,
this is not recommended, particularly if the
analog input is connected to an external
analog voltage source, which would
create signal contention between the
analog signal and the output pin driver.
VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V
The maximum output current sourced by any 8 mA
I/O pin = 12 mA.
LED source current < 12 mA is technically permitted.
Refer to the VOH/IOH graphs in Section 31.0 “DC
and AC Device Characteristics Graphs” for
additional information.
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6. The Peripheral Pin Select (PPS) pin mapping rules
11.8 I/O Ports Resources
are as follows:
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
a) Only one “output” function can be active on a
given pin at any time, regardless if it is a
dedicated or remappable function (one pin,
one output).
b) It is possible to assign a “remappable output”
function to multiple pins and externally short or
tie them together for increased current drive.
11.8.1
KEY RESOURCES
• “I/O Ports” (DS70000598) in the “dsPIC33/PIC24
Family Reference Manual”
c) If any “dedicated output” function is enabled
on a pin, it will take precedence over any
remappable “output” function.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
d) If any “dedicated digital” (input or output) func-
tion is enabled on a pin, any number of “input”
remappable functions can be mapped to the
same pin.
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
e) If any “dedicated analog” function(s) are
enabled on a given pin, “digital input(s)” of any
kind will all be disabled, although a single “dig-
ital output”, at the user’s cautionary discretion,
can be enabled and active as long as there is
no signal contention with an external analog
input signal. For example, it is possible for the
ADC to convert the digital output logic level, or
to toggle a digital output on a comparator or
ADC input, provided there is no external
analog input, such as for a built-in self-test.
• Development Tools
f) Any number of “input” remappable functions
can be mapped to the same pin(s) at the same
time, including to any pin with a single output
from either a dedicated or remappable “output”.
g) The TRISx registers control only the digital I/O
output buffer. Any other dedicated or remap-
pable active “output” will automatically override
the TRISx setting. The TRISx register does not
control the digital logic “input” buffer. Remap-
pable digital “inputs” do not automatically
override TRISx settings, which means that the
TRISx bit must be set to input for pins with only
remappable input function(s) assigned.
h) All analog pins are enabled by default after any
Reset and the corresponding digital input buffer
on the pin has been disabled. Only the Analog
Pin Select (ANSELx) registers control the digi-
tal input buffer, not the TRISx register. The user
must disable the analog function on a pin using
the Analog Pin Select registers in order to use
any “digital input(s)” on a corresponding pin, no
exceptions.
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11.9 Peripheral Pin Select Registers
REGISTER 11-9: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT1R7
INT1R6
INT1R5
INT1R4
INT1R3
INT1R2
INT1R1
INT1R0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
INT1R<7:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
Unimplemented: Read as ‘0’
REGISTER 11-10: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
INT2R7
INT2R6
INT2R5
INT2R4
INT2R3
INT2R2
INT2R1
INT2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
INT2R<7:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-11: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T1CKR7
T1CKR6
T1CKR5
T1CKR4
T1CKR3
T1CKR2
T1CKR1
T1CKR0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
T1CKR<7:0>: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
Unimplemented: Read as ‘0’
REGISTER 11-12: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3CKR7
T3CKR6
T3CKR5
T3CKR4
T3CKR3
T3CKR2
T3CKR1
T3CKR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T2CKR7
T2CKR6
T2CKR5
T2CKR4
T2CKR3
T2CKR2
T2CKR1
T2CKR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
T3CKR<7:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
T2CKR<7:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-13: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
R/W-0
IC2R7
R/W-0
IC2R6
R/W-0
IC2R5
R/W-0
IC2R4
R/W-0
IC2R3
R/W-0
IC2R2
R/W-0
IC2R1
R/W-0
IC2R0
bit 15
bit 8
R/W-0
IC1R7
R/W-0
IC1R6
R/W-0
IC1R5
R/W-0
IC1R4
R/W-0
IC1R3
R/W-0
IC1R2
R/W-0
IC1R1
R/W-0
IC1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
IC2R<7:0>: Assign Input Capture 2 (IC2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
IC1R<7:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-14: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8
R/W-0
IC4R7
R/W-0
IC4R6
R/W-0
IC4R5
R/W-0
IC4R4
R/W-0
IC4R3
R/W-0
IC4R2
R/W-0
IC4R1
R/W-0
IC4R0
bit 15
bit 8
R/W-0
IC3R7
R/W-0
IC3R6
R/W-0
IC3R5
R/W-0
IC3R4
R/W-0
IC3R3
R/W-0
IC3R2
R/W-0
IC3R1
R/W-0
IC3R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
IC4R<7:0>: Assign Input Capture 4 (IC4) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
IC3R<7:0>: Assign Input Capture 3 (IC3) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-15: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OCFAR7
OCFAR6
OCFAR5
OCFAR4
OCFAR3
OCFAR2
OCFAR1
OCFAR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
OCFAR<7:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-16: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT2R0
bit 8
FLT2R7
FLT2R6
FLT2R5
FLT2R4
FLT2R3
FLT2R2
FLT2R1
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT1R7
FLT1R6
FLT1R5
FLT1R4
FLT1R3
FLT1R2
FLT1R1
FLT1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
FLT2R<7:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
FLT1R<7:0>: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-17: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT4R7
FLT4R6
FLT4R5
FLT4R4
FLT4R3
FLT4R2
FLT4R1
FLT4R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT3R7
FLT3R6
FLT3R5
FLT3R4
FLT3R3
FLT3R2
FLT3R1
FLT3R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
FLT4R<7:0>: Assign PWM Fault 4 (FLT4) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
FLT3R<7:0>: Assign PWM Fault 3 (FLT3) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-18: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U1CTSR7
U1CTSR6
U1CTSR5
U1CTSR4
U1CTSR3
U1CTSR2
U1CTSR1
U1CTSR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U1RXR7
U1RXR6
U1RXR5
U1RXR4
U1RXR3
U1RXR2
U1RXR1
U1RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
U1CTSR<7:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
U1RXR<7:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-19: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2CTSR7
U2CTSR6
U2CTSR5
U2CTSR4
U2CTSR3
U2CTSR2
U2CTSR1
U2CTSR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U2RXR7
U2RXR6
U2RXR5
U2RXR4
U2RXR3
U2RXR2
U2RXR1
U2RXR0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
U2CTSR<7:0>: Assign UART2 Clear-to-Send (U2CTS) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
U2RXR<7:0>: Assign UART2 Receive (U2RX) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-20: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCK1INR7
SCK1INR6
SCK1INR5 SCK1INR4 SCK1INR3
SCK1INR2
SCK1INR1
SCK1INR0
bit 8
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI1R0
bit 0
SDI1R7
SDI1R6
SDI1R5
SDI1R4
SDI1R3
SDI1R2
SDI1R1
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
SCK1INR<7:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
SDI1R<7:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-21: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS1R7
SS1R6
SS1R5
SS1R4
SS1R3
SS1R2
SS1R1
SS1R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
SS1R<7:0>: Assign SPI1 Slave Select (SS1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-22: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCK2INR0
bit 8
SCK2INR7
SCK2INR6
SCK2INR5 SCK2INR4 SCK2INR3
SCK2INR2
SCK2INR1
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI2R0
bit 0
SDI2R7
SDI2R6
SDI2R5
SDI2R4
SDI2R3
SDI2R2
SDI2R1
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
SCK2INR<7:0>: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
SDI2R<7:0>: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-23: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS2R7
SS2R6
SS2R5
SS2R4
SS2R3
SS2R2
SS2R1
SS2R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
SS2R<7:0>: Assign SPI2 Slave Select (SS2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-24: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C2RXR7
C2RXR6
C2RXR5
C2RXR4
C2RXR3
C2RXR2
C2RXR1
C2RXR0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C1RXR7
C1RXR6
C1RXR5
C1RXR4
C1RXR3
C1RXR2
C1RXR1
C1RXR0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
C2RXR<7:0>: Assign CAN2 Receive (C2RX) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
C1RXR<7:0>: Assign CAN1 Receive (C1RX) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-25: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SCK3R7
SCK3R6
SCK3R5
SCK3R4
SCK3R3
SCK3R2
SCK3R1
SCK3R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDI3R7
SDI3R6
SDI3R5
SDI3R4
SDI3R3
SDI3R2
SDI3R1
SDI3R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
SCK3R<7:0>: Assign SPI3 Clock Input (SCK3) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
SDI3R<7:0>: Assign SPI3 Data Input (SDI3) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-26: RPINR30: PERIPHERAL PIN SELECT INPUT REGISTER 30
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SS3R7
SS3R6
SS3R5
SS3R4
SS3R3
SS3R2
SS3R1
SS3R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
SS3R<7:0>: Assign SPI3 Slave Select (SS3) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-27: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCI1R0
bit 8
SYNCI1R7
SYNCI1R6
SYNCI1R5 SYNCI1R4 SYNCI1R3
SYNCI1R2
SYNCI1R1
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
SYNCI1R<7:0>: Assign PWM Synchronization Input 1 (SYNCI1) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
Unimplemented: Read as ‘0’
REGISTER 11-28: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCI2R0
bit 0
SYNCI2R7
SYNCI2R6
SYNCI2R5 SYNCI2R4 SYNCI2R3
SYNCI2R2
SYNCI2R1
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
SYNCI2R<7:0>: Assign PWM Synchronization Input 2 (SYNCI2) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-29: RPINR42: PERIPHERAL PIN SELECT INPUT REGISTER 42
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT6R7
FLT6R6
FLT6R5
FLT6R4
FLT6R3
FLT6R2
FLT6R1
FLT6R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT5R7
FLT5R6
FLT5R5
FLT5R4
FLT5R3
FLT5R2
FLT5R1
FLT5R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
FLT6R<7:0>: Assign PWM Fault 6 (FLT6) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
FLT5R<7:0>: Assign PWM Fault 5 (FLT5) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
REGISTER 11-30: RPINR43: PERIPHERAL PIN SELECT INPUT REGISTER 43
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT8R7
FLT8R6
FLT8R5
FLT8R4
FLT8R3
FLT8R2
FLT8R1
FLT8R0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLT7R7
FLT7R6
FLT7R5
FLT7R4
FLT7R3
FLT7R2
FLT7R1
FLT7R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
FLT8R<7:0>: Assign PWM Fault 8 (FLT8) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
FLT7R<7:0>: Assign PWM Fault 7 (FLT7) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-31: RPINR45: PERIPHERAL PIN SELECT INPUT REGISTER 45
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLCINAR7
CLCINAR6
CLCINAR5 CLCINAR4 CLCINAR3
CLCINAR2
CLCINAR1 CLCINAR0
bit 8
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
CLCINAR<7:0>: Assign CLC Input A (CLCINA) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
Unimplemented: Read as ‘0’
REGISTER 11-32: RPINR46: PERIPHERAL PIN SELECT INPUT REGISTER 46
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLCINBR7
CLCINBR6
CLCINBR5 CLCINBR4 CLCINBR3
CLCINBR2
CLCINBR1 CLCINBR0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
CLCINBR<7:0>: Assign CLC Input B (CLCINB) to the Corresponding RPn Pin bits
See Table 11-11 which contains a list of remappable inputs for the index value.
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REGISTER 11-33: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP17R6
RP17R5
RP17R4
RP17R3
RP17R2
RP17R1
RP17R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP16R6
RP16R5
RP16R4
RP16R3
RP16R2
RP16R1
RP16R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP17R<6:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP16R<6:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-34: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP19R6
RP19R5
RP19R4
RP19R3
RP19R2
RP19R1
RP19R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP18R6
RP18R5
RP18R4
RP18R3
RP18R2
RP18R1
RP18R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP19R<6:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP18R<6:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-35: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP32R6
RP32R5
RP32R4
RP32R3
RP32R2
RP32R1
RP32R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP20R6
RP20R5
RP20R4
RP20R3
RP20R2
RP20R1
RP20R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP32R<6:0>: Peripheral Output Function is Assigned to RP32 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP20R<6:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-36: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP34R6
RP34R5
RP34R4
RP34R3
RP34R2
RP34R1
RP34R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP33R6
RP33R5
RP33R4
RP33R3
RP33R2
RP33R1
RP33R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP34R<6:0>: Peripheral Output Function is Assigned to RP34 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP33R<6:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-37: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP36R6
RP36R5
RP36R4
RP36R3
RP36R2
RP36R1
RP36R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP35R6
RP35R5
RP35R4
RP35R3
RP35R2
RP35R1
RP35R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP36R<6:0>: Peripheral Output Function is Assigned to RP36 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP35R<6:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-38: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP38R6
RP38R5
RP38R4
RP38R3
RP38R2
RP38R1
RP38R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP37R6
RP37R5
RP37R4
RP37R3
RP37R2
RP37R1
RP37R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP38R<6:0>: Peripheral Output Function is Assigned to RP38 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP37R<6:0>: Peripheral Output Function is Assigned to RP37 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-39: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP40R6
RP40R5
RP40R4
RP40R3
RP40R2
RP40R1
RP40R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP39R6
RP39R5
RP39R4
RP39R3
RP39R2
RP39R1
RP39R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP40R<6:0>: Peripheral Output Function is Assigned to RP40 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP39R<6:0>: Peripheral Output Function is Assigned to RP39 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-40: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP43R6
RP43R5
RP43R4
RP43R3
RP43R2
RP43R1
RP43R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP41R6
RP41R5
RP41R4
RP41R3
RP41R2
RP41R1
RP41R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP43R<6:0>: Peripheral Output Function is Assigned to RP43 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP41R<6:0>: Peripheral Output Function is Assigned to RP41 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-41: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP45R6
RP45R5
RP45R4
RP45R3
RP45R2
RP45R1
RP45R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP44R6
RP44R5
RP44R4
RP44R3
RP44R2
RP44R1
RP44R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP45R<6:0>: Peripheral Output Function is Assigned to RP45 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP44R<6:0>: Peripheral Output Function is Assigned to RP44 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-42: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP47R6
RP47R5
RP47R4
RP47R3
RP47R2
RP47R1
RP47R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP46R6
RP46R5
RP46R4
RP46R3
RP46R2
RP46R1
RP46R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP47R<6:0>: Peripheral Output Function is Assigned to RP47 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP46R<6:0>: Peripheral Output Function is Assigned to RP46 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-43: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP49R6
RP49R5
RP49R4
RP49R3
RP49R2
RP49R1
RP49R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP48R6
RP48R5
RP48R4
RP48R3
RP48R2
RP48R1
RP48R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP49R<6:0>: Peripheral Output Function is Assigned to RP49 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP48R<6:0>: Peripheral Output Function is Assigned to RP48 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-44: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP51R6
RP51R5
RP51R4
RP51R3
RP51R2
RP51R1
RP51R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP50R6
RP50R5
RP50R4
RP50R3
RP50R2
RP50R1
RP50R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP51R<6:0>: Peripheral Output Function is Assigned to RP51 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP50R<6:0>: Peripheral Output Function is Assigned to RP50 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-45: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP53R6
RP53R5
RP53R4
RP53R3
RP53R2
RP53R1
RP53R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP52R6
RP52R5
RP52R4
RP52R3
RP52R2
RP52R1
RP52R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP53R<6:0>: Peripheral Output Function is Assigned to RP53 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP52R<6:0>: Peripheral Output Function is Assigned to RP52 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-46: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP55R6
RP55R5
RP55R4
RP55R3
RP55R2
RP55R1
RP55R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP54R6
RP54R5
RP54R4
RP54R3
RP54R2
RP54R1
RP54R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP55R<6:0>: Peripheral Output Function is Assigned to RP55 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP54R<6:0>: Peripheral Output Function is Assigned to RP54 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-47: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP57R6
RP57R5
RP57R4
RP57R3
RP57R2
RP57R1
RP57R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP56R6
RP56R5
RP56R4
RP56R3
RP56R2
RP56R1
RP56R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP57R<6:0>: Peripheral Output Function is Assigned to RP57 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP56R<6:0>: Peripheral Output Function is Assigned to RP56 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-48: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP60R6
RP60R5
RP60R4
RP60R3
RP60R2
RP60R1
RP60R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP58R6
RP58R5
RP58R4
RP58R3
RP58R2
RP58R1
RP58R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP60R<6:0>: Peripheral Output Function is Assigned to RP60 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP58R<6:0>: Peripheral Output Function is Assigned to RP58 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-49: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP62R6
RP62R5
RP62R4
RP62R3
RP62R2
RP62R1
RP62R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP61R6
RP61R5
RP61R4
RP61R3
RP61R2
RP61R1
RP61R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP62R<6:0>: Peripheral Output Function is Assigned to RP62 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP61R<6:0>: Peripheral Output Function is Assigned to RP61 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-50: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP64R6
RP64R5
RP64R4
RP64R3
RP64R2
RP64R1
RP64R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP63R6
RP63R5
RP63R4
RP63R3
RP63R2
RP63R1
RP63R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP64R<6:0>: Peripheral Output Function is Assigned to RP64 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP63R<6:0>: Peripheral Output Function is Assigned to RP63 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-51: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP66R6
RP66R5
RP66R4
RP66R3
RP66R2
RP66R1
RP66R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP65R6
RP65R5
RP65R4
RP65R3
RP65R2
RP65R1
RP65R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP66R<6:0>: Peripheral Output Function is Assigned to RP66 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP65R<6:0>: Peripheral Output Function is Assigned to RP65 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-52: RPOR19: PERIPHERAL PIN SELECT OUTPUT REGISTER 19
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP68R6
RP68R5
RP68R4
RP68R3
RP68R2
RP68R1
RP68R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP67R6
RP67R5
RP67R4
RP67R3
RP67R2
RP67R1
RP67R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP68R<6:0>: Peripheral Output Function is Assigned to RP68 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP67R<6:0>: Peripheral Output Function is Assigned to RP67 Output Pin bits
(see Table 11-13 for peripheral function numbers)
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REGISTER 11-53: RPOR20: PERIPHERAL PIN SELECT OUTPUT REGISTER 20
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP70R6
RP70R5
RP70R4
RP70R3
RP70R2
RP70R1
RP70R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP69R6
RP69R5
RP69R4
RP69R3
RP69R2
RP69R1
RP69R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP70R<6:0>: Peripheral Output Function is Assigned to RP70 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP69R<6:0>: Peripheral Output Function is Assigned to RP69 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-54: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP72R6
RP72R5
RP72R4
RP72R3
RP72R2
RP72R1
RP72R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP71R6
RP71R5
RP71R4
RP71R3
RP71R2
RP71R1
RP71R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP72R<6:0>: Peripheral Output Function is Assigned to RP72 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP71R<6:0>: Peripheral Output Function is Assigned to RP71 Output Pin bits
(see Table 11-13 for peripheral function numbers)
DS70005258C-page 166
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 11-55: RPOR22: PERIPHERAL PIN SELECT OUTPUT REGISTER 22
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP74R6
RP74R5
RP74R4
RP74R3
RP74R2
RP74R1
RP74R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP73R6
RP73R5
RP73R4
RP73R3
RP73R2
RP73R1
RP73R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP74R<6:0>: Peripheral Output Function is Assigned to RP74 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP73R<6:0>: Peripheral Output Function is Assigned to RP73 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-56: RPOR23: PERIPHERAL PIN SELECT OUTPUT REGISTER 23
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP76R6
RP76R5
RP76R4
RP76R3
RP76R2
RP76R1
RP76R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP75R6
RP75R5
RP75R4
RP75R3
RP75R2
RP75R1
RP75R0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP76R<6:0>: Peripheral Output Function is Assigned to RP76 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP75R<6:0>: Peripheral Output Function is Assigned to RP75 Output Pin bits
(see Table 11-13 for peripheral function numbers)
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 11-57: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP177R6
RP177R5
RP177R4
RP177R3
RP177R2
RP177R1
RP177R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP176R6
RP176R5
RP176R4
RP176R3
RP176R2
RP176R1
RP176R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP177R<6:0>: Peripheral Output Function is Assigned to RP177 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP176R<6:0>: Peripheral Output Function is Assigned to RP176 Output Pin bits
(see Table 11-13 for peripheral function numbers)
REGISTER 11-58: RPOR25: PERIPHERAL PIN SELECT OUTPUT REGISTER 25
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP179R6
RP179R5
RP179R4
RP179R3
RP179R2
RP179R1
RP179R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP178R6
RP178R5
RP178R4
RP178R3
RP178R2
RP178R1
RP178R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP179R<6:0>: Peripheral Output Function is Assigned to RP179 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP178R<6:0>: Peripheral Output Function is Assigned to RP178 Output Pin bits
(see Table 11-13 for peripheral function numbers)
DS70005258C-page 168
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 11-59: RPOR26: PERIPHERAL PIN SELECT OUTPUT REGISTER 26
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP181R6
RP181R5
RP181R4
RP181R3
RP181R2
RP181R1
RP181R0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP180R6
RP180R5
RP180R4
RP180R3
RP180R2
RP180R1
RP180R0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
Unimplemented: Read as ‘0’
bit 14-8
RP181R<6:0>: Peripheral Output Function is Assigned to RP181 Output Pin bits
(see Table 11-13 for peripheral function numbers)
bit 7
Unimplemented: Read as ‘0’
bit 6-0
RP180R<6:0>: Peripheral Output Function is Assigned to RP180 Output Pin bits
(see Table 11-13 for peripheral function numbers)
2016-2018 Microchip Technology Inc.
DS70005258C-page 169
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 170
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
The Timer1 module can operate in one of the following
modes:
12.0 TIMER1
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to “Timers” (DS70362) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The Timer modes are determined by the following bits:
• Timer1 Clock Source Select bit (TCS): T1CON<1>
• Timer1 External Clock Input Synchronization Select
bit (TSYNC): T1CON<2>
• Timer1 Gated Time Accumulation Enable bit
(TGATE): T1CON<6>
The Timer1 module is a 16-bit timer that can operate as
a free-running interval timer/counter.
Timer control bit settings for different operating modes
are provided in Table 12-1.
The Timer1 module has the following unique features
over other timers:
TABLE 12-1: TIMER1 MODE SETTINGS
• Can be Operated in Asynchronous Counter mode
from an External Clock Source
Mode
Timer
TCS
TGATE
TSYNC
• The External Clock Input (T1CK) can Optionally be
Synchronized to the Internal Device Clock and the
Clock Synchronization is Performed after the
prescaler
0
0
1
0
1
x
x
x
1
Gated Timer
Synchronous
Counter
A block diagram of Timer1 is shown in Figure 12-1.
Asynchronous
Counter
1
x
0
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Falling Edge
Detect
Gate
Sync
1
0
Set T1IF Flag
(1)
FP
10
00
x1
Prescaler
(/n)
T1CLK
TGATE
Latch
CLK
Data
Reset
TMR1
TCKPS<1:0>
ADC Trigger
0
T1CK
Equal
Prescaler
(/n)
Comparator
1
Sync
TGATE
TSYNC
TCS
TCKPS<1:0>
PR1
Note 1: FP is the peripheral clock.
2016-2018 Microchip Technology Inc.
DS70005258C-page 171
dsPIC33EPXXXGS70X/80X FAMILY
12.1.1
KEY RESOURCES
12.1 Timer1 Resources
• “Timers” (DS70362) in the “dsPIC33/PIC24
Family Reference Manual”
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005258C-page 172
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
12.2 Timer1 Control Register
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
TSYNC(1)
R/W-0
TCS(1)
U-0
—
TGATE
TCKPS1
TCKPS0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit(1)
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timer1 Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit(1)
When TCS = 1:
1= Synchronizes external clock input
0= Does not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit(1)
1= External clock is from pin, T1CK (on the rising edge)
0= Internal clock (FP)
Unimplemented: Read as ‘0’
Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any
attempts by user software to write to the TMR1 register are ignored.
2016-2018 Microchip Technology Inc.
DS70005258C-page 173
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 174
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Individually, all four of the 16-bit timers can function as
13.0 TIMER2/3 AND TIMER4/5
synchronous timers or counters. They also offer the
features listed previously, except for the event trigger;
this is implemented only with Timer2/3. The operating
modes and enabled features are determined by setting
the appropriate bit(s) in the T2CON, T3CON, T4CON
and T5CON registers. T2CON and T4CON are shown
in generic form in Register 13-1. T3CON and T5CON
are shown in Register 13-2.
Note 1: This data sheet summarizes the features of
the dsPIC33EPXXXGS70X/80X family of
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Timers” (DS70362) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
For 32-bit timer/counter operation, Timer2 and Timer4
are the least significant word (lsw); Timer3 and Timer5
are the most significant word (msw) of the 32-bit timers.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Note:
For 32-bit operation, T3CON and T5CON
control bits are ignored. Only T2CON and
T4CON control bits are used for setup and
control. Timer2 and Timer4 clock and gate
inputs are utilized for the 32-bit timer
modules, but an interrupt is generated
with the Timer3 and Timer5 interrupt flags.
The Timer2/3 and Timer4/5 modules are 32-bit timers,
which can also be configured as four independent
16-bit timers with selectable operating modes.
A block diagram for an example 32-bit timer pair
(Timer2/3 and Timer4/5) is shown in Figure 13-2.
As 32-bit timers, Timer2/3 and Timer4/5 operate in
three modes:
13.1 Timer Resources
• Two Independent 16-Bit Timers (e.g., Timer2 and
Timer3) with all 16-Bit Operating modes (except
Asynchronous Counter mode)
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
• Single 32-Bit Timer
• Single 32-Bit Synchronous Counter
They also support these features:
13.1.1
KEY RESOURCES
• Timer Gate Operation
• “Timers” (DS70362) in the “dsPIC33/PIC24
Family Reference Manual”
• Selectable Prescaler Settings
• Timer Operation during Idle and Sleep modes
• Interrupt on a 32-Bit Period Register Match
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• Time Base for Input Capture and Output Compare
modules (Timer2 and Timer3 only)
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
2016-2018 Microchip Technology Inc.
DS70005258C-page 175
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 13-1:
TIMERx BLOCK DIAGRAM (x = 2 THROUGH 5)
Falling Edge
Detect
Gate
Sync
1
0
Set TxIF Flag
(1)
10
00
x1
FP
Prescaler
(/n)
TxCLK
Reset
TGATE
Latch
CLK
Data
TMRx
TCKPS<1:0>
TxCK
ADC
Prescaler
(/n)
Trigger(2)
Sync
Equal
Comparator
TGATE
TCS
TCKPS<1:0>
PRx
Note 1: FP is the peripheral clock.
2: The ADC trigger is only available on TMR2.
FIGURE 13-2:
TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)
Falling Edge
Detect
Gate
Sync
1
0
Set TyIF Flag
PRx
PRy
TGATE
Data
Equal
Reset
Comparator
(1)
FP
10
00
x1
Prescaler
(/n)
CLK
lsw
TMRx
msw
TMRy
Latch
TCKPS<1:0>
TxCK
Prescaler
(/n)
Sync
TMRyHLD
TGATE
TCS
TCKPS<1:0>
Data Bus<15:0>
Note 1: Timerx is a Type B timer (x = 2 and 4).
2: Timery is a Type C timer (y = 3 and 5).
DS70005258C-page 176
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
13.2 Timer2/3 and Timer4/5 Control Registers
REGISTER 13-1: TxCON: (TIMER2 AND TIMER4) CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32
U-0
—
R/W-0
TCS(1)
U-0
—
TGATE
TCKPS1
TCKPS0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timerx On bit
When T32 = 1:
1= Starts 32-bit Timerx/y
0= Stops 32-bit Timerx/y
When T32 = 0:
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timerx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
bit 3
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256
10= 1:64
01= 1:8
00= 1:1
T32: 32-Bit Timer Mode Select bit
1= Timerx and Timery form a single 32-bit timer
0= Timerx and Timery act as two 16-bit timers
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(1)
1= External clock is from pin, TxCK (on the rising edge)
0= Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1: The TxCK pin is not available on all devices. Refer to the “Pin Diagrams” section for the available pins.
2016-2018 Microchip Technology Inc.
DS70005258C-page 177
dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 13-2: TyCON: (TIMER3 AND TIMER5) CONTROL REGISTER
R/W-0
TON(1)
U-0
—
R/W-0
TSIDL(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(1)
R/W-0
TCKPS1(1) TCKPS0(1)
R/W-0
U-0
—
U-0
—
R/W-0
TCS(1,3)
U-0
—
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
TON: Timery On bit(1)
1= Starts 16-bit Timery
0= Stops 16-bit Timery
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Timery Stop in Idle Mode bit(2)
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timery Gated Time Accumulation Enable bit(1)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation is enabled
0= Gated time accumulation is disabled
bit 5-4
TCKPS<1:0>: Timery Input Clock Prescale Select bits(1)
11= 1:256
10= 1:64
01= 1:8
00= 1:1
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timery Clock Source Select bit(1,3)
1= External clock is from pin, TyCK (on the rising edge)
0= Internal clock (FP)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit operation is enabled (TxCON<3> = 1), these bits have no effect on Timery operation; all timer
functions are set through TxCON.
2: When 32-bit timer operation is enabled (T32 = 1) in the Timerx Control register (TxCON<3>), the TSIDL
bit must be cleared to operate the 32-bit timer in Idle mode.
3: The TyCK pin is not available on all devices. See the “Pin Diagrams” section for the available pins.
DS70005258C-page 178
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Key features of the input capture module include:
14.0 INPUT CAPTURE
• Hardware-Configurable for 32-Bit Operation in All
modes by Cascading Two Adjacent modules
• Synchronous and Trigger modes of Output
Compare Operation, with up to 21 User-Selectable
Trigger/Sync Sources available
• A 4-Level FIFO Buffer for Capturing and Holding
Timer Values for Several Events
• Configurable Interrupt Generation
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
to be
a
comprehensive reference
source. To complement the information
in this data sheet, refer to “Input
Capture with Dedicated Timer”
(DS70000352) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
• Up to Six Clock Sources available for each module,
Driving a Separate Internal 16-Bit Counter
14.1 Input Capture Resources
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
14.1.1
KEY RESOURCES
The input capture module is useful in applications
requiring frequency (period) and pulse measurements.
The dsPIC33EPXXXGS70X/80X devices support four
input capture channels.
• “Input Capture with Dedicated Timer”
(DS70000352) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
FIGURE 14-1:
INPUT CAPTURE x MODULE BLOCK DIAGRAM
ICM<2:0>
ICI<1:0>
Event and
Set ICxIF
Edge Detect Logic
Prescaler
Counter
1:1/4/16
and
Interrupt
Logic
Clock Synchronizer
ICx Pin
ICTSEL<2:0>
Increment
16
Clock
Select
ICx Clock
Sources
4-Level FIFO Buffer
ICxTMR
16
Reset
16
Trigger and
Sync Logic
Trigger and
Sync Sources
ICxBUF
System Bus
ICOV, ICBNE
SYNCSEL<4:0>(1)
Note 1: The trigger/sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for
proper ICx module operation or the trigger/sync source must be changed to another source option.
2016-2018 Microchip Technology Inc.
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14.2 Input Capture Registers
REGISTER 14-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
ICSIDL
ICTSEL2
ICTSEL1
ICTSEL0
bit 15
bit 8
U-0
—
R/W-0
ICI1
R/W-0
ICI0
HC/HS/R-0
ICOV
HC/HS/R-0
ICBNE
R/W-0
ICM2
R/W-0
ICM1
R/W-0
ICM0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
HS = Hardware Settable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture x Stop in Idle Control bit
1= Input capture will halt in CPU Idle mode
0= Input capture will continue to operate in CPU Idle mode
bit 12-10
ICTSEL<2:0>: Input Capture x Timer Select bits
111= Peripheral clock (FP) is the clock source of the ICx
110= Reserved
101= Reserved
100= T1CLK is the clock source of the ICx (only the synchronous clock is supported)
011= T5CLK is the clock source of the ICx
010= T4CLK is the clock source of the ICx
001= T2CLK is the clock source of the ICx
000= T3CLK is the clock source of the ICx
bit 9-7
bit 6-5
Unimplemented: Read as ‘0’
ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0> = 001or 111)
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture x Overflow Status Flag bit (read-only)
1= Input capture buffer overflow has occurred
0= No input capture buffer overflow has occurred
bit 3
ICBNE: Input Capture x Buffer Not Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture x Mode Select bits
111= Input Capture x functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge
detect only, all other control bits are not applicable)
110= Unused (module is disabled)
101= Capture mode, every 16th rising edge (Prescaler Capture mode)
100= Capture mode, every 4th rising edge (Prescaler Capture mode)
011= Capture mode, every rising edge (Simple Capture mode)
010= Capture mode, every falling edge (Simple Capture mode)
001= Capture mode, every rising and falling edge (Edge Detect mode, ICI<1:0> is not used in this mode)
000= Input Capture x is turned off
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
IC32
bit 15
bit 8
R/W-0
ICTRIG(2) TRIGSTAT(3)
HS/R/W-0
U-0
—
R/W-0
R/W-1
R/W-1
R/W-0
R/W-1
SYNCSEL4(4) SYNCSEL3(4) SYNCSEL2(4) SYNCSEL1(4) SYNCSEL0(4)
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15-9
bit 8
Unimplemented: Read as ‘0’
IC32: Input Capture x 32-Bit Timer Mode Select bit (Cascade mode)
1= Odd ICx and even ICx form a single 32-bit input capture module(1)
0= Cascade module operation is disabled
bit 7
ICTRIG: Input Capture x Trigger Operation Select bit(2)
1= Input source is used to trigger the input capture timer (Trigger mode)
0= Input source is used to synchronize the input capture timer to a timer of another module
(Synchronization mode)
bit 6
bit 5
TRIGSTAT: Timer Trigger Status bit(3)
1= ICxTMR has been triggered and is running
0= ICxTMR has not been triggered and is being held clear
Unimplemented: Read as ‘0’
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
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REGISTER 14-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits(4)
11111= No sync or trigger source for ICx
11110= Reserved
11101= Reserved
11100= Reserved
11011= CMP4 module synchronizes or triggers ICx(5)
11010= CMP3 module synchronizes or triggers ICx(5)
11001= CMP2 module synchronizes or triggers ICx(5)
11000= CMP1 module synchronizes or triggers ICx(5)
10111= Reserved
10110= Reserved
10101= Reserved
10100= Reserved
10011= IC4 module interrupt synchronizes or triggers ICx
10010= IC3 module interrupt synchronizes or triggers ICx
10001= IC2 module interrupt synchronizes or triggers ICx
10000= IC1 module interrupt synchronizes or triggers ICx
01111= Timer5 synchronizes or triggers ICx
01110= Timer4 synchronizes or triggers ICx
01101= Timer3 synchronizes or triggers ICx (default)
01100= Timer2 synchronizes or triggers ICx
01011= Timer1 synchronizes or triggers ICx
01010= Reserved
01001= Reserved
01000= IC4 module synchronizes or triggers ICx
00111= IC3 module synchronizes or triggers ICx
00110= IC2 module synchronizes or triggers ICx
00101= IC1 module synchronizes or triggers ICx
00100= OC4 module synchronizes or triggers ICx
00011= OC3 module synchronizes or triggers ICx
00010= OC2 module synchronizes or triggers ICx
00001= OC1 module synchronizes or triggers ICx
00000= No sync or trigger source for ICx
Note 1: The IC32 bit in both the odd and even ICx must be set to enable Cascade mode.
2: The input source is selected by the SYNCSEL<4:0> bits of the ICxCON2 register.
3: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and
cleared in software.
4: Do not use the ICx module as its own sync or trigger source.
5: This option should only be selected as a trigger source and not as a synchronization source.
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single output pulse, or a sequence of output pulses, by
15.0 OUTPUT COMPARE
changing the state of the output pin on the compare
match events. The output compare module can also
generate interrupts on compare match events.
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Output Compare with
Dedicated Timer” (DS70005159) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
15.1 Output Compare Resources
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
15.1.1
KEY RESOURCES
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• “Output Compare with Dedicated Timer”
(DS70005159) in the “dsPIC33/PIC24 Family
Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
The output compare module can select one of six
available clock sources for its time base. The module
compares the value of the timer with the value of one or
two Compare registers, depending on the operating
mode selected. The state of the output pin changes
when the timer value matches the Compare register
value. The output compare module generates either a
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
FIGURE 15-1:
OUTPUT COMPARE x MODULE BLOCK DIAGRAM
OCxCON1
OCxCON2
OCxR
Rollover/Reset
OCxR Buffer
Comparator
OCx Pin
Match
Event
Increment
Clock
Select
OCx Clock
Sources
OCx Output and
Fault Logic
OCxTMR
Comparator
OCxRS Buffer
Rollover
Reset
OCFA
Match
Event
Match Event
Trigger and
Sync Logic
Trigger and
Sync Sources
SYNCSEL<4:0>
Trigger(1)
Rollover/Reset
OCx Synchronization/Trigger Event
OCx Interrupt
OCxRS
Reset
Note 1: The trigger/sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for
proper OCx module operation or the trigger/sync source must be changed to another source option.
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15.2 Output Compare Control Registers
REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
OCSIDL
OCTSEL2
OCTSEL1
OCTSEL0
bit 15
bit 8
R/W-0
U-0
—
U-0
—
HSC/R/W-0
OCFLTA
R/W-0
R/W-0
OCM2
R/W-0
OCM1
R/W-0
OCM0
ENFLTA
TRIGMODE
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Output Compare x Stop in Idle Mode Control bit
1= Output Compare x halts in CPU Idle mode
0= Output Compare x continues to operate in CPU Idle mode
bit 12-10
OCTSEL<2:0>: Output Compare x Clock Select bits
111= Peripheral clock (FP)
110= Reserved
101= Reserved
100= T1CLK is the clock source of the OCx (only the synchronous clock is supported)
011= T5CLK is the clock source of the OCx
010= T4CLK is the clock source of the OCx
001= T3CLK is the clock source of the OCx
000= T2CLK is the clock source of the OCx
bit 9-8
bit 7
Unimplemented: Read as ‘0’
ENFLTA: Fault A Input Enable bit
1= Output Compare Fault A input (OCFA) is enabled
0= Output Compare Fault A input (OCFA) is disabled
bit 6-5
bit 4
Unimplemented: Read as ‘0’
OCFLTA: PWM Fault A Condition Status bit
1= PWM Fault A condition on the OCFA pin has occurred
0= No PWM Fault A condition on the OCFA pin has occurred
bit 3
TRIGMODE: Trigger Status Mode Select bit
1= TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software
0= TRIGSTAT is cleared only by software
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.
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REGISTER 15-1: OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 (CONTINUED)
bit 2-0
OCM<2:0>: Output Compare x Mode Select bits
111= Center-Aligned PWM mode: Output is set high when OCxTMR = OCxR and set low when
OCxTMR = OCxRS(1)
110= Edge-Aligned PWM mode: Output is set high when OCxTMR = 0and set low when OCxTMR = OCxR(1)
101= Double Compare Continuous Pulse mode: Initializes OCx pin low, toggles OCx state continuously
on alternate matches of OCxR and OCxRS
100= Double Compare Single-Shot mode: Initializes OCx pin low, toggles OCx state on matches of
OCxR and OCxRS for one cycle
011= Single Compare mode: Compare event with OCxR, continuously toggles OCx pin
010= Single Compare Single-Shot mode: Initializes OCx pin high, compare event with OCxR, forces OCx
pin low
001= Single Compare Single-Shot mode: Initializes OCx pin low, compare event with OCxR, forces OCx
pin high
000= Output compare channel is disabled
Note 1: OCxR and OCxRS are double-buffered in PWM mode only.
2016-2018 Microchip Technology Inc.
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
OC32
FLTMD
FLTOUT
FLTTRIEN
OCINV
bit 15
bit 8
R/W-0
HS/R/W-0
TRIGSTAT
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
OCTRIG
OCTRIS
SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0
bit 0
bit 7
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
FLTMD: Fault Mode Select bit
1= Fault mode is maintained until the Fault source is removed; the corresponding OCFLTA bit is
cleared in software and a new PWMx period starts
0= Fault mode is maintained until the Fault source is removed and a new PWMx period starts
bit 14
bit 13
bit 12
FLTOUT: Fault Out bit
1= PWMx output is driven high on a Fault
0= PWMx output is driven low on a Fault
FLTTRIEN: Fault Output State Select bit
1= OCx pin is tri-stated on a Fault condition
0= OCx pin I/O state is defined by the FLTOUT bit on a Fault condition
OCINV: Output Compare x Invert bit
1= OCx output is inverted
0= OCx output is not inverted
bit 11-9
bit 8
Unimplemented: Read as ‘0’
OC32: Cascade Two OCx Modules Enable bit (32-bit operation)
1= Cascade module operation is enabled
0= Cascade module operation is disabled
bit 7
bit 6
bit 5
OCTRIG: Output Compare x Trigger/Sync Select bit
1= Triggers OCx from the source designated by the SYNCSELx bits
0= Synchronizes OCx with the source designated by the SYNCSELx bits
TRIGSTAT: Timer Trigger Status bit
1= Timer source has been triggered and is running
0= Timer source has not been triggered and is being held clear
OCTRIS: Output Compare x Output Pin Direction Select bit
1= OCx is tri-stated
0= OCx module drives the OCx pin
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
3: For each OCMPx instance, a different PTG trigger out is used:
OCMP1 – PTG trigger out [0]
OCMP2 – PTG trigger out [1]
OCMP3 – PTG trigger out [2]
OCMP4 – PTG trigger out [3]
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REGISTER 15-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 (CONTINUED)
bit 4-0
SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits
11111= OCxRS compare event is used for synchronization
11110= INT2 pin synchronizes or triggers OCx
11101= INT1 pin synchronizes or triggers OCx
11100= Reserved
11011= CMP4 module synchronizes or triggers OCx
11010= CMP3 module synchronizes or triggers OCx
11001= CMP2 module synchronizes or triggers OCx
11000= CMP1 module synchronizes or triggers OCx
10111= Reserved
10110= Reserved
10101= Reserved
10100= Reserved
10011= IC4 input capture interrupt event synchronizes or triggers OCx
10010= IC3 input capture interrupt event synchronizes or triggers OCx
10001= IC2 input capture interrupt event synchronizes or triggers OCx
10000= IC1 input capture interrupt event synchronizes or triggers OCx
01111= Timer5 synchronizes or triggers OCx
01110= Timer4 synchronizes or triggers OCx
01101= Timer3 synchronizes or triggers OCx
01100= Timer2 synchronizes or triggers OCx (default)
01011= Timer1 synchronizes or triggers OCx
01010= PTG Trigger Output x(3)
01001= Reserved
01000= IC4 input capture event synchronizes or triggers OCx
00111= IC3 input capture event synchronizes or triggers OCx
00110= IC2 input capture event synchronizes or triggers OCx
00101= IC1 input capture event synchronizes or triggers OCx
00100= OC4 module synchronizes or triggers OCx(1,2)
00011= OC3 module synchronizes or triggers OCx(1,2)
00010= OC2 module synchronizes or triggers OCx(1,2)
00001= OC1 module synchronizes or triggers OCx(1,2)
00000= No sync or trigger source for OCx
Note 1: Do not use the OCx module as its own synchronization or trigger source.
2: When the OCy module is turned off, it sends a trigger out signal. If the OCx module uses the OCy module
as a trigger source, the OCy module must be unselected as a trigger source prior to disabling it.
3: For each OCMPx instance, a different PTG trigger out is used:
OCMP1 – PTG trigger out [0]
OCMP2 – PTG trigger out [1]
OCMP3 – PTG trigger out [2]
OCMP4 – PTG trigger out [3]
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NOTES:
DS70005258C-page 188
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Figure 16-1 conceptualizes the PWM module in a
16.0 HIGH-SPEED PWM
simplified block diagram. Figure 16-2 illustrates how
the module hardware is partitioned for each PWMx
output pair for the Complementary PWM mode.
Note:
This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “High-Speed PWM
Module” (DS70000323) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip website
(www.microchip.com).
The PWM module contains eight PWM generators. The
module has up to 16 PWMx output pins: PWM1H/
PWM1L through PWM8H/PWM8L. For complementary
outputs, these 16 I/O pins are grouped into high/low
pairs. PWM1 through PWM6 can be used to trigger an
ADC conversion.
16.2 Feature Description
The high-speed PWM on dsPIC33EPXXXGS70X/80X
devices supports a wide variety of PWM modes and
output formats. This PWM module is ideal for power
conversion applications, such as:
The PWM module is designed for applications that
require:
• High resolution at high PWM frequencies
• The ability to drive Standard Edge-Aligned,
Center-Aligned, Complementary mode and
Push-Pull mode outputs
• AC/DC Converters
• DC/DC Converters
• Power Factor Correction
• Uninterruptible Power Supply (UPS)
• Inverters
• The ability to create multiphase PWM outputs
Two common, medium power converter topologies are
push-pull and half-bridge. These designs require the
PWM output signal to be switched between alternate
pins, as provided by the Push-Pull PWM mode.
• Battery Chargers
• Digital Lighting
Phase-shifted PWM describes the situation where
each PWM generator provides outputs, but the phase
relationship between the generator outputs is
specifiable and changeable.
16.1 Features Overview
The high-speed PWM module incorporates the
following features:
Multiphase PWM is often used to improve DC/DC
Converter load transient response, and reduce the size
of output filter capacitors and inductors. Multiple DC/DC
Converters are often operated in parallel, but phase
shifted in time. A single PWM output, operating at
250 kHz, has a period of 4 s but an array of four PWM
channels, staggered by 1 s each, yields an effective
switching frequency of 1 MHz. Multiphase PWM
applications typically use a fixed-phase relationship.
• Eight PWMx Generators with Two Outputs per
Generator
• Two Master Time Base modules
• Individual Time Base and Duty Cycle for each
PWM Output
• Duty Cycle, Dead Time, Phase Shift and a
Frequency Resolution of 1.04 ns
• Independent Fault and Current-Limit Inputs
• Redundant Output
Variable phase PWM is useful in Zero Voltage
Transition (ZVT) power converters. Here, the PWM
duty cycle is always 50% and the power flow is
controlled by varying the relative phase shift between
the two PWM generators.
• True Independent Output
• Center-Aligned PWM mode
• Output Override Control
• Chop mode (also known as Gated mode)
• Special Event Trigger
• Dual Trigger from PWMx to Analog-to-Digital
Converter (ADC)
• PWMxL and PWMxH Output Pin Swapping
• Independent PWMx Frequency, Duty Cycle and
Phase-Shift Changes
• Enhanced Leading-Edge Blanking (LEB) Functionality
• PWM Capture Functionality
Note:
Duty cycle, dead time, phase shift and
frequency resolution is 8.32 ns in
Center-Aligned PWM mode.
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To gain write access to these locked registers, the user
application must write two consecutive values (0xABCD
and 0x4321) to the PWMKEY register to perform the
unlock operation. The write access to the IOCONx or
FCLCONx registers must be the next SFR access
following the unlock process. There can be no other SFR
accesses during the unlock process and subsequent
write access. To write to both the IOCONx and
FCLCONx registers requires two unlock operations.
16.2.1
WRITE-PROTECTED REGISTERS
On dsPIC33EPXXXGS70X/80X family devices, write
protection is implemented for the IOCONx and FCLCONx
registers. The write protection feature prevents any inad-
vertent writes to these registers. This protection feature
can be controlled by the PWMLOCK Configuration bit
(FDEVOPT<0>). The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protection
feature can be disabled by configuring PWMLOCK = 0.
The correct unlocking sequence is described in
Example 16-1.
EXAMPLE 16-1:
PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE
; Writing to FCLCON1 register requires unlock sequence
mov #0xabcd, w10
mov #0x4321, w11
mov #0x0000, w0
mov w10, PWMKEY
mov w11, PWMKEY
mov w0, FCLCON1
; Load first unlock key to w10 register
; Load second unlock key to w11 register
; Load desired value of FCLCON1 register in w0
; Write first unlock key to PWMKEY register
; Write second unlock key to PWMKEY register
; Write desired value to FCLCON1 register
; Set PWM ownership and polarity using the IOCON1 register
; Writing to IOCON1 register requires unlock sequence
mov #0xabcd, w10
mov #0x4321, w11
mov #0xF000, w0
mov w10, PWMKEY
mov w11, PWMKEY
mov w0, IOCON1
; Load first unlock key to w10 register
; Load second unlock key to w11 register
; Load desired value of IOCON1 register in w0
; Write first unlock key to PWMKEY register
; Write second unlock key to PWMKEY register
; Write desired value to IOCON1 register
16.3.1
KEY RESOURCES
16.3 PWM Resources
• “High-Speed PWM Module” (DS70000323) in
the “dsPIC33/PIC24 Family Reference Manual”
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
DS70005258C-page 190
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 16-1:
HIGH-SPEED PWM MODULE ARCHITECTURAL DIAGRAM
SYNCI1/SYNCI2
Data Bus
Primary and Secondary
Master Time Base
SYNCO1/SYNCO2
Synchronization Signal
PWM1 Interrupt
PWM1H
PWM
Generator 1
PWM1L
Fault, Current Limit
Synchronization Signal
PWM2 Interrupt
PWM2H
PWM
Generator 2
PWM2L
CPU
Fault, Current Limit
PWM3 through PWM7
Synchronization Signal
PWM8 Interrupt
PWM8H
PWM
Generator 8
PWM8L
Primary Trigger
Secondary Trigger
Fault and
Current Limit
ADC Module
Special Event Trigger
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FIGURE 16-2:
SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWM
PTCON, PTCON2
STCON, STCON2
Module Control and Timing
SYNCI1
SYNCI2
PWMKEY
SYNCO1
PTPER
SEVTCMP
Comparator
Special Event Compare Trigger
Special Event
Comparator
Postscaler
Special Event Trigger
Master Time Base Counter
Clock
Prescaler
PMTMR
STPER
Primary Master Time Base
SYNCO2
SEVTCMP
Special Event Compare Trigger
Special Event
Postscaler
Comparator
Comparator
Special Event Trigger
Master Time Base Counter
Clock
SMTMR
MDC
Prescaler
Secondary Master Time Base
Master Duty Cycle Register
PDCx
PWM Generator 1
MUX
PWMx Output Mode
Comparator
Control Logic
PWMCAPx
ADC Trigger
User Override Logic
Pin
Control
Logic
Dead-Time
Logic
PTMRx
PWM1H
PWM1L
Current-Limit
Override Logic
Comparator
PHASEx
SDCx
TRIGx
Fault Override Logic
Secondary PWMx
MUX
Fault and
Current-Limit
Logic
Interrupt
Logic
Comparator
FLTx
ADC Trigger
Comparator
STMRx
SPHASEx
STRIGx
FCLCONx
LEBCONx
IOCONx
ALTDTRx
DTRx
PWMCONx
AUXCONx
TRGCONx
PWMxH
PWMxL
FLTx
PWM Generator 1 – PWM Generator 8
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REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER
R/W-0
PTEN
U-0
—
R/W-0
HSC/R-0
SESTAT
R/W-0
SEIEN
R/W-0
EIPU(1)
R/W-0
R/W-0
PTSIDL
SYNCPOL(1) SYNCOEN(1)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SYNCEN(1) SYNCSRC2(1) SYNCSRC1(1) SYNCSRC0(1) SEVTPS3(1) SEVTPS2(1) SEVTPS1(1) SEVTPS0(1)
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PTEN: PWM Module Enable bit
1= PWM module is enabled
0= PWM module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
PTSIDL: PWM Time Base Stop in Idle Mode bit
1= PWM time base halts in CPU Idle mode
0= PWM time base runs in CPU Idle mode
bit 12
bit 11
bit 10
bit 9
SESTAT: Special Event Interrupt Status bit
1= Special event interrupt is pending
0= Special event interrupt is not pending
SEIEN: Special Event Interrupt Enable bit
1= Special event interrupt is enabled
0= Special event interrupt is disabled
EIPU: Enable Immediate Period Updates bit(1)
1= Active Period register is updated immediately
0= Active Period register updates occur on PWM cycle boundaries
SYNCPOL: Synchronize Input and Output Polarity bit(1)
1= SYNCIx/SYNCO1 polarity is inverted (active-low)
0= SYNCIx/SYNCO1 is active-high
bit 8
SYNCOEN: Primary Time Base Synchronization Enable bit(1)
1= SYNCO1 output is enabled
0= SYNCO1 output is disabled
bit 7
SYNCEN: External Time Base Synchronization Enable bit(1)
1= External synchronization of primary time base is enabled
0= External synchronization of primary time base is disabled
bit 6-4
SYNCSRC<2:0>: Synchronous Source Selection bits(1)
111= Reserved
101= Reserved
100= Reserved
011= PTG Trigger Output 17
010= PTG Trigger Output 16
001= SYNCI2
000= SYNCI1
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
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REGISTER 16-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)
bit 3-0
SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits(1)
1111= 1:16 postscaler generates a Special Event Trigger on every sixteenth compare match event
•
•
•
0001= 1:2 postscaler generates a Special Event Trigger on every second compare match event
0000= 1:1 postscaler generates a Special Event Trigger on every compare match event
Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user
application must program the Period register with a value that is slightly larger than the expected period of
the external synchronization input signal.
REGISTER 16-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
PCLKDIV<2:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
PCLKDIV<2:0>: PWMx Input Clock Prescaler (Divider) Select bits(1)
111= Reserved
110= Divide-by-64, maximum PWM timing resolution
101= Divide-by-32, maximum PWM timing resolution
100= Divide-by-16, maximum PWM timing resolution
011= Divide-by-8, maximum PWM timing resolution
010= Divide-by-4, maximum PWM timing resolution
001= Divide-by-2, maximum PWM timing resolution
000= Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
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REGISTER 16-3: PTPER: PWM PRIMARY MASTER TIME BASE PERIOD REGISTER(1,2)
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
PTPER<15:8>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PTPER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits
Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant three bits set to ‘0’, thus yielding
a period resolution at 8.32 ns (at fastest auxiliary clock rate).
REGISTER 16-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTCMP<12:5>
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
SEVTCMP<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
SEVTCMP<12:0>: Special Event Compare Count Value bits
Unimplemented: Read as ‘0’
Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.
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REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
HSC/R-0
SESTAT
R/W-0
SEIEN
R/W-0
EIPU(1)
R/W-0
R/W-0
SYNCOEN
bit 8
SYNCPOL
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SEVTPS0
bit 0
SYNCEN
SYNCSRC2 SYNCSRC1 SYNCSRC0
SEVTPS3
SEVTPS2
SEVTPS1
bit 7
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
SESTAT: Special Event Interrupt Status bit
1= Secondary special event interrupt is pending
0= Secondary special event interrupt is not pending
bit 11
bit 10
bit 9
SEIEN: Special Event Interrupt Enable bit
1= Secondary special event interrupt is enabled
0= Secondary special event interrupt is disabled
EIPU: Enable Immediate Period Updates bit(1)
1= Active Secondary Period register is updated immediately
0= Active Secondary Period register updates occur on PWMx cycle boundaries
SYNCPOL: Synchronize Input and Output Polarity bit
1= SYNCIx/SYNCO2 polarity is inverted (active-low)
0= SYNCIx/SYNCO2 polarity is active-high
bit 8
SYNCOEN: Secondary Master Time Base Synchronization Enable bit
1= SYNCO2 output is enabled
0= SYNCO2 output is disabled
bit 7
SYNCEN: External Secondary Master Time Base Synchronization Enable bit
1= External synchronization of secondary time base is enabled
0= External synchronization of secondary time base is disabled
bit 6-4
SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits
111= Reserved
101= Reserved
100= Reserved
011= PTG Trigger Output 17
010= PTG Trigger Output 16
001= SYNCI2
000= SYNCI1
bit 3-0
SEVTPS<3:0>: PWMx Secondary Special Event Trigger Output Postscaler Select bits
1111= 1:16 postcaler
0001= 1:2 postcaler
•
•
•
0000= 1:1 postscaler
Note 1: This bit only applies to the secondary master time base period.
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REGISTER 16-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
PCLKDIV<2:0>(1)
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)
111= Reserved
110= Divide-by-64, maximum PWM timing resolution
101= Divide-by-32, maximum PWM timing resolution
100= Divide-by-16, maximum PWM timing resolution
011= Divide-by-8, maximum PWM timing resolution
010= Divide-by-4, maximum PWM timing resolution
001= Divide-by-2, maximum PWM timing resolution
000= Divide-by-1, maximum PWM timing resolution (power-on default)
Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will
yield unpredictable results.
REGISTER 16-7: STPER: PWM SECONDARY MASTER TIME BASE PERIOD REGISTER(1,2)
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
STPER<15:8>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
STPER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits
Note 1: The PWMx time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.
2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a
period resolution at 8.32 ns (at fastest auxiliary clock rate).
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REGISTER 16-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SSEVTCMP<12:5>
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
SSEVTCMP<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
SSEVTCMP<12:0>: Special Event Compare Count Value bits
Unimplemented: Read as ‘0’
Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SSEVTCMP resolution is 8.32 ns.
REGISTER 16-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER(1)
R/W-0
CHPCLKEN
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CHOPCLK6 CHOPCLK5
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CHPCLKEN: Enable Chop Clock Generator bit
1= Chop clock generator is enabled
0= Chop clock generator is disabled
bit 14-10
bit 9-3
Unimplemented: Read as ‘0’
CHOPCLK<6:0>: Chop Clock Divider bits
Value is in 8.32 ns increments. The frequency of the chop clock signal is given by:
Chop Frequency = 1/(16.64 * (CHOP<7:3> + 1) * Primary Master PWM Input Clock Period).
bit 2-0
Unimplemented: Read as ‘0’
Note 1: The chop clock generator operates with the primary PWM clock prescaler (PCLKDIV<2:0>) in the
PTCON2 register (Register 16-2).
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REGISTER 16-10: MDC: PWM MASTER DUTY CYCLE REGISTER(1,2)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
MDC<15:8>
R/W-0
R/W-0
R/W-0
MDC<7:0>
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
MDC<15:0>: PWM Master Duty Cycle Value bits
Note 1: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), PWM duty cycle resolution will increase from one to three LSBs.
REGISTER 16-11: PWMKEY: PWM PROTECTION LOCK/UNLOCK KEY REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWMKEY<15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PWMKEY<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PWMKEY<15:0>: PWM Protection Lock/Unlock Key Value bits
2016-2018 Microchip Technology Inc.
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REGISTER 16-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 8)
HSC/R-0
FLTSTAT(1)
bit 15
HSC/R-0
CLSTAT(1)
HSC/R-0
R/W-0
R/W-0
CLIEN
R/W-0
R/W-0
ITB(3)
R/W-0
MDCS(3)
TRGSTAT
FLTIEN
TRGIEN
bit 8
R/W-0
DTC1
R/W-0
DTC0
U-0
—
U-0
—
R/W-0
MTBS
R/W-0
CAM(2,3,4)
R/W-0
XPRES(5)
R/W-0
IUE
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FLTSTAT: Fault Interrupt Status bit(1)
1= Fault interrupt is pending
0= No Fault interrupt is pending
This bit is cleared by setting FLTIEN = 0.
CLSTAT: Current-Limit Interrupt Status bit(1)
1= Current-limit interrupt is pending
0= No current-limit interrupt is pending
This bit is cleared by setting CLIEN = 0.
TRGSTAT: Trigger Interrupt Status bit
1= Trigger interrupt is pending
0= No trigger interrupt is pending
This bit is cleared by setting TRGIEN = 0.
bit 12
bit 11
bit 10
bit 9
FLTIEN: Fault Interrupt Enable bit
1= Fault interrupt is enabled
0= Fault interrupt is disabled and the FLTSTAT bit is cleared
CLIEN: Current-Limit Interrupt Enable bit
1= Current-limit interrupt is enabled
0= Current-limit interrupt is disabled and the CLSTAT bit is cleared
TRGIEN: Trigger Interrupt Enable bit
1= A trigger event generates an interrupt request
0= Trigger event interrupts are disabled and the TRGSTAT bit is cleared
ITB: Independent Time Base Mode bit(3)
1= PHASEx/SPHASEx registers provide the time base period for this PWMx generator
0= PTPER register provides timing for this PWMx generator
bit 8
MDCS: Master Duty Cycle Register Select bit(3)
1= MDC register provides duty cycle information for this PWMx generator
0= PDCx and SDCx registers provide duty cycle information for this PWMx generator
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWMx is enabled by setting PTEN (PTCON<15>) = 1.
4: Center-Aligned mode ignores the Least Significant three bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
5: Configure CLMOD (FCLCONx<8>) = 0and ITB (PWMCONx<9>) = 1to operate in External Period Reset mode.
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REGISTER 16-12: PWMCONx: PWMx CONTROL REGISTER (x = 1 to 8) (CONTINUED)
bit 7-6
DTC<1:0>: Dead-Time Control bits
11= Reserved
10= Dead-time function is disabled
01= Negative dead time is actively applied for Complementary Output mode
00= Positive dead time is actively applied for all Output modes
bit 5-4
bit 3
Unimplemented: Read as ‘0’
MTBS: Master Time Base Select bit
1= PWMx generator uses the secondary master time base for synchronization and the clock source for
the PWMx generation logic (if secondary time base is available)
0= PWMx generator uses the primary master time base for synchronization and the clock source for the
PWMx generation logic
bit 2
bit 1
bit 0
CAM: Center-Aligned Mode Enable bit(2,3,4)
1= Center-Aligned mode is enabled
0= Edge-Aligned mode is enabled
XPRES: External PWMx Reset Control bit(5)
1= Current-limit source resets the time base for this PWMx generator if it is in Independent Time Base mode
0= External pins do not affect the PWMx time base
IUE: Immediate Update Enable bit
1= Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers are
immediate
0= Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers are
synchronized to the local PWMx time base
Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.
2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the
CAM bit is ignored.
3: These bits should not be changed after the PWMx is enabled by setting PTEN (PTCON<15>) = 1.
4: Center-Aligned mode ignores the Least Significant three bits of the Duty Cycle, Phase and Dead-Time
registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to
the fastest clock.
5: Configure CLMOD (FCLCONx<8>) = 0and ITB (PWMCONx<9>) = 1to operate in External Period Reset mode.
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REGISTER 16-13: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER (x = 1 to 8)(1,2,3)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PDCx<15:8>
R/W-0
R/W-0
R/W-0
PDCx<7:0>
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PDCx<15:0>: PWMx Generator Duty Cycle Value bits
Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the
Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both
the PWMxH and PWMxL.
2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), PWMx duty cycle resolution will increase from one to three LSBs.
REGISTER 16-14: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER (x = 1 to 8)(1,2,3)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SDCx<15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0 R/W-0
SDCx<7:0>
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
SDCx<15:0>: PWMx Secondary Duty Cycle for PWMxL Output Pin bits
Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the
SDCx register controls the PWMxL duty cycle.
2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,
while the maximum pulse width generated corresponds to a value of Period – 0x0008.
3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of
operation), PWMx duty cycle resolution will increase from one to three LSBs.
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REGISTER 16-15: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER (x = 1 to 8)(1,2)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PHASEx<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASEx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits
Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);
PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Phase-shift value for
PWMxH only
• When the PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;
therefore, the valid range is 0x0000 through period
2: If PWMCONx<9> = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);
PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL
• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent time base
period value for PWMxH only
• When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000-0xFFF8
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REGISTER 16-16: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER (x = 1 to 8)(1,2)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
SPHASEx<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SPHASEx<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits
(used in Independent PWM mode only)
Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);
SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<11:10> = 11), SPHASEx<15:0> = Phase-shift value for
PWMxL only
2: If PWMCONx<9> = 1, the following applies based on the mode of operation:
• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);
SPHASEx<15:0> = Not used
• True Independent Output mode (IOCONx<11:10> = 11); SPHASEx<15:0> = Independent time base
period value for PWMxL only
• When the PHASEx/SPHASEx registers provide the local period, the valid range of values is
0x0010-0xFFF8
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REGISTER 16-17: DTRx: PWMx DEAD-TIME REGISTER (x = 1 to 8)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
DTRx<13:8>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0
DTRx<7:0>
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-0
Unimplemented: Read as ‘0’
DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits
REGISTER 16-18: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER (x = 1 to 8)
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx<13:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALTDTRx<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-0
Unimplemented: Read as ‘0’
ALTDTRx<13:0>: Unsigned 14-Bit Alternate Dead-Time Value for PWMx Dead-Time Unit bits
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REGISTER 16-19: TRGCONx: PWMx TRIGGER CONTROL REGISTER (x = 1 to 8)
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
TRGDIV3
TRGDIV2
TRGDIV1
TRGDIV0
bit 15
bit 8
R/W-0
DTM(1)
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0
bit 0
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-12
TRGDIV<3:0>: Trigger # Output Divider bits
1111= Trigger output for every 16th trigger event
1110= Trigger output for every 15th trigger event
1101= Trigger output for every 14th trigger event
1100= Trigger output for every 13th trigger event
1011= Trigger output for every 12th trigger event
1010= Trigger output for every 11th trigger event
1001= Trigger output for every 10th trigger event
1000= Trigger output for every 9th trigger event
0111= Trigger output for every 8th trigger event
0110= Trigger output for every 7th trigger event
0101= Trigger output for every 6th trigger event
0100= Trigger output for every 5th trigger event
0011= Trigger output for every 4th trigger event
0010= Trigger output for every 3rd trigger event
0001= Trigger output for every 2nd trigger event
0000= Trigger output for every trigger event
bit 11-8
bit 7
Unimplemented: Read as ‘0’
DTM: Dual Trigger Mode bit(1)
1= Secondary trigger event is combined with the primary trigger event to create a PWM trigger
0= Secondary trigger event is not combined with the primary trigger event to create a PWM trigger;
two separate PWM triggers are generated
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits
111111= Wait 63 PWM cycles before generating the first trigger event after the module is enabled
•
•
•
000010= Wait 2 PWM cycles before generating the first trigger event after the module is enabled
000001= Wait 1 PWM cycle before generating the first trigger event after the module is enabled
000000= Wait 0 PWM cycles before generating the first trigger event after the module is enabled
Note 1: The secondary PWMx generator cannot generate PWM trigger interrupts.
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REGISTER 16-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 8)
R/W-1
PENH
R/W-1
PENL
R/W-0
POLH
R/W-0
POLL
R/W-0
PMOD1(1)
R/W-0
PMOD0(1)
R/W-0
R/W-0
OVRENH
OVRENL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLDAT1(2)
R/W-0
CLDAT0(2)
R/W-0
SWAP
R/W-0
OVRDAT1
OVRDAT0
FLTDAT1(2) FLTDAT0(2)
OSYNC
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PENH: PWMxH Output Pin Ownership bit
1= PWMx module controls the PWMxH pin
0= GPIO module controls the PWMxH pin
bit 14
PENL: PWMxL Output Pin Ownership bit
1= PWMx module controls the PWMxL pin
0= GPIO module controls the PWMxL pin
bit 13
POLH: PWMxH Output Pin Polarity bit
1= PWMxH pin is active-low
0= PWMxH pin is active-high
bit 12
POLL: PWMxL Output Pin Polarity bit
1= PWMxL pin is active-low
0= PWMxL pin is active-high
bit 11-10
PMOD<1:0>: PWMx I/O Pin Mode bits(1)
11= PWMx I/O pin pair is in the True Independent Output mode
10= PWMx I/O pin pair is in the Push-Pull Output mode
01= PWMx I/O pin pair is in the Redundant Output mode
00= PWMx I/O pin pair is in the Complementary Output mode
bit 9
OVRENH: Override Enable for PWMxH Pin bit
1= OVRDAT1 provides data for output on the PWMxH pin
0= PWMx generator provides data for the PWMxH pin
bit 8
OVRENL: Override Enable for PWMxL Pin bit
1= OVRDAT0 provides data for output on the PWMxL pin
0= PWMx generator provides data for the PWMxL pin
bit 7-6
bit 5-4
OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits
If OVRENH = 1, OVRDAT1 provides data for the PWMxH pin.
If OVRENL = 1, OVRDAT0 provides data for the PWMxL pin.
FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD<1:0> are Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If Fault is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
If current limit is active, then FLTDAT1 provides the state for the PWMxH pin.
If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.
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REGISTER 16-20: IOCONx: PWMx I/O CONTROL REGISTER (x = 1 to 8) (CONTINUED)
bit 3-2
CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits(2)
IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:
If current limit is active, then CLDAT1 provides the state for the PWMxH pin.
If current limit is active, then CLDAT0 provides the state for the PWMxL pin.
IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:
CLDAT<1:0> bits are ignored.
bit 1
bit 0
SWAP: SWAP PWMxH and PWMxL Pins bit
1= PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the
PWMxH pins
0= PWMxH and PWMxL pins are mapped to their respective pins
OSYNC: Output Override Synchronization bit
1= Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base
0= Output overrides via the OVRDAT<1:0> bits occur on the next CPU clock boundary
Note 1: These bits should not be changed after the PWMx module is enabled (PTEN = 1).
2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.
REGISTER 16-21: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 8)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRGCMP<12:5>
bit 15
R/W-0
bit 7
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
TRGCMP<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
TRGCMP<12:0>: Trigger Compare Value bits
When the primary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.
Unimplemented: Read as ‘0’
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REGISTER 16-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 8)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IFLTMOD
CLSRC4
CLSRC3
CLSRC2
CLSRC1
CLSRC0
CLPOL(1)
CLMOD
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
FLTSRC4
FLTSRC3
FLTSRC2
FLTSRC1
FLTSRC0
FLTPOL(1)
FLTMOD1
FLTMOD0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
IFLTMOD: Independent Fault Mode Enable bit
1= Independent Fault mode: Current-limit input maps FLTDAT1 to the PWMxH output and the Fault
input maps FLTDAT0 to the PWMxL output; the CLDAT<1:0> bits are not used for override functions
0= Normal Fault mode: Current-Limit mode maps CLDAT<1:0> bits to the PWMxH and PWMxL
outputs; the PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs
bit 14-10
CLSRC<4:0>: Current-Limit Control Signal Source Select for PWMx Generator bits
11111= FLT31
10001= Reserved
10000= Analog Comparator 4
01111= Analog Comparator 3
01110= Analog Comparator 2
01101= Analog Comparator 1
01100= Fault 12
01011= Fault 11
01010= Fault 10
01001= Fault 9
01000= Fault 8
00111= Fault 7
00110= Fault 6
00101= Fault 5
00100= Fault 4
00011= Fault 3
00010= Fault 2
00001= Fault 1
00000= Reserved
bit 9
bit 8
CLPOL: Current-Limit Polarity for PWMx Generator bit(1)
1= The selected current-limit source is active-low
0= The selected current-limit source is active-high
CLMOD: Current-Limit Mode Enable for PWMx Generator bit
1= Current-Limit mode is enabled
0= Current-Limit mode is disabled
Note 1: These bits should be changed only when PTEN = 0(PTCON<15>).
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REGISTER 16-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER
(x = 1 to 8) (CONTINUED)
bit 7-3
FLTSRC<4:0>: Fault Control Signal Source Select for PWMx Generator bits
11111= Fault 31 (Default)
11110-10111= Reserved
10110= Fault 22
10101= Fault 21
10100= Fault 20
10011= Fault 19
10010= Fault 18
10001= Fault 17
10000= Analog Comparator 4
01111= Analog Comparator 3
01110= Analog Comparator 2
01101= Analog Comparator 1
01100= Fault 12
01011= Fault 11
01010= Fault 10
01001= Fault 9
01000= Fault 8
00111= Fault 7
00110= Fault 6
00101= Fault 5
00100= Fault 4
00011= Fault 3
00010= Fault 2
00001= Fault 1
00000= Reserved
bit 2
FLTPOL: Fault Polarity for PWMx Generator bit(1)
1= The selected Fault source is active-low
0= The selected Fault source is active-high
bit 1-0
FLTMOD<1:0>: Fault Mode for PWMx Generator bits
11= Fault input is disabled
10= Reserved
01= The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (cycle)
00= The selected Fault source forces the PWMxH, PWMxL pins to FLTDATx values (latched condition)
Note 1: These bits should be changed only when PTEN = 0(PTCON<15>).
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REGISTER 16-23: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER (x = 1 to 8)(1)
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STRGCMP<12:5>
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
STRGCMP<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
STRGCMP<12:0>: Secondary Trigger Compare Value bits
When the secondary PWMx functions in the local time base, this register contains the compare values
that can trigger the ADC module.
bit 2-0
Unimplemented: Read as ‘0’
Note 1: STRIGx cannot generate the PWM trigger interrupts.
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REGISTER 16-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
(x = 1 to 8)
R/W-0
PHR
R/W-0
PHF
R/W-0
PLR
R/W-0
PLF
R/W-0
R/W-0
U-0
—
U-0
—
FLTLEBEN
CLLEBEN
bit 15
bit 8
U-0
—
U-0
—
R/W-0
BCH(1)
R/W-0
BCL(1)
R/W-0
BPHH
R/W-0
BPHL
R/W-0
BPLH
R/W-0
BPLL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
PHR: PWMxH Rising Edge Trigger Enable bit
1= Rising edge of PWMxH will trigger the Leading-Edge Blanking counter
0= Leading-Edge Blanking ignores the rising edge of PWMxH
PHF: PWMxH Falling Edge Trigger Enable bit
1= Falling edge of PWMxH will trigger the Leading-Edge Blanking counter
0= Leading-Edge Blanking ignores the falling edge of PWMxH
PLR: PWMxL Rising Edge Trigger Enable bit
1= Rising edge of PWMxL will trigger the Leading-Edge Blanking counter
0= Leading-Edge Blanking ignores the rising edge of PWMxL
PLF: PWMxL Falling Edge Trigger Enable bit
1= Falling edge of PWMxL will trigger the Leading-Edge Blanking counter
0= Leading-Edge Blanking ignores the falling edge of PWMxL
FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit
1= Leading-Edge Blanking is applied to the selected Fault input
0= Leading-Edge Blanking is not applied to the selected Fault input
CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit
1= Leading-Edge Blanking is applied to the selected current-limit input
0= Leading-Edge Blanking is not applied to the selected current-limit input
bit 9-6
bit 5
Unimplemented: Read as ‘0’
BCH: Blanking in Selected Blanking Signal High Enable bit(1)
1= State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is high
0= No blanking when the selected blanking signal is high
bit 4
bit 3
bit 2
BCL: Blanking in Selected Blanking Signal Low Enable bit(1)
1= State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is low
0= No blanking when the selected blanking signal is low
BPHH: Blanking in PWMxH High Enable bit
1= State blanking (of current-limit and/or Fault input signals) when the PWMxH output is high
0= No blanking when the PWMxH output is high
BPHL: Blanking in PWMxH Low Enable bit
1= State blanking (of current-limit and/or Fault input signals) when the PWMxH output is low
0= No blanking when the PWMxH output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.
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REGISTER 16-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL REGISTER
(x = 1 to 8) (CONTINUED)
bit 1
BPLH: Blanking in PWMxL High Enable bit
1= State blanking (of current-limit and/or Fault input signals) when the PWMxL output is high
0= No blanking when the PWMxL output is high
bit 0
BPLL: Blanking in PWMxL Low Enable bit
1= State blanking (of current-limit and/or Fault input signals) when the PWMxL output is low
0= No blanking when the PWMxL output is low
Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.
REGISTER 16-25: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER (x = 1 to 8)
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
LEB<8:5>
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
LEB<4:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-3
Unimplemented: Read as ‘0’
LEB<8:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits
The value is in 8.32 ns increments.
bit 2-0
Unimplemented: Read as ‘0’
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REGISTER 16-26: AUXCONx: PWMx AUXILIARY CONTROL REGISTER (x = 1 to 8)
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
HRPDIS
HRDDIS
BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0
bit 8
bit 15
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0 CHOPHEN
CHOPLEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
HRPDIS: High-Resolution PWMx Period Disable bit
1= High-resolution PWMx period is disabled to reduce power consumption
0= High-resolution PWMx period is enabled
HRDDIS: High-Resolution PWMx Duty Cycle Disable bit
1= High-resolution PWMx duty cycle is disabled to reduce power consumption
0= High-resolution PWMx duty cycle is enabled
bit 13-12
bit 11-8
Unimplemented: Read as ‘0’
BLANKSEL<3:0>: PWMx State Blank Source Select bits
The selected state blank signal will block the current-limit and/or Fault input signals
(if enabled via the BCH and BCL bits in the LEBCONx register).
1001= Reserved
1000= PWM8H is selected as the state blank source
0111= PWM7H is selected as the state blank source
0110= PWM6H is selected as the state blank source
0101= PWM5H is selected as the state blank source
0100= PWM4H is selected as the state blank source
0011= PWM3H is selected as the state blank source
0010= PWM2H is selected as the state blank source
0001= PWM1H is selected as the state blank source
0000= No state blanking
bit 7-6
bit 5-2
Unimplemented: Read as ‘0’
CHOPSEL<3:0>: PWMx Chop Clock Source Select bits
The selected signal will enable and disable (chop) the selected PWMx outputs.
1001= Reserved
1000= PWM8H is selected as the chop clock source
0111= PWM7H is selected as the chop clock source
0110= PWM6H is selected as the chop clock source
0101= PWM5H is selected as the chop clock source
0100= PWM4H is selected as the chop clock source
0011= PWM3H is selected as the chop clock source
0010= PWM2H is selected as the chop clock source
0001= PWM1H is selected as the chop clock source
0000= Chop clock generator is selected as the chop clock source
bit 1
bit 0
CHOPHEN: PWMxH Output Chopping Enable bit
1= PWMxH chopping function is enabled
0= PWMxH chopping function is disabled
CHOPLEN: PWMxL Output Chopping Enable bit
1= PWMxL chopping function is enabled
0= PWMxL chopping function is disabled
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REGISTER 16-27: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER (x = 1 to 8)
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PWMCAP<12:5>(1,2,3,4)
bit 8
bit 0
R-0
R-0
R-0
R-0
U-0
—
U-0
—
U-0
—
PWMCAP<4:0>(1,2,3,4)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
PWMCAP<12:0>: PWMx Primary Time Base Capture Value bits(1,2,3,4)
The value in this register represents the captured PWMx time base value when a leading edge is
detected on the current-limit input.
bit 2-0
Unimplemented: Read as ‘0’
Note 1: The capture feature is only available on a primary output (PWMxH).
2: This feature is active only after LEB processing on the current-limit input signal is complete.
3: The minimum capture resolution is 8.32 ns.
4: This feature can be used when the XPRES bit (PWMCONx<1>) is set to ‘0’.
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NOTES:
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The PTG module has the following major features:
17.0 PERIPHERAL TRIGGER
• Multiple Clock Sources
GENERATOR (PTG) MODULE
• Two 16-Bit General Purpose Timers
• Two 16-Bit General Limit Counters
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Peripheral Trigger
Generator (PTG)” (DS70000669) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
• Configurable for Rising or Falling Edge Triggering
• Generates Processor Interrupts to include:
- Four configurable processor interrupts
- Interrupt on a Step event in Single-Step mode
- Interrupt on a PTG Watchdog Timer time-out
• Able to Receive Trigger Signals from these
Peripherals:
- ADC
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- PWM
- Output Compare
- Input Capture
- Comparator
- INT2
• Able to Trigger or Synchronize to these
Peripherals:
17.1 Module Introduction
- Watchdog Timer
- Output Compare
- Input Capture
- ADC
The Peripheral Trigger Generator (PTG) provides a
means to schedule complex, high-speed peripheral
operations that would be difficult to achieve using soft-
ware. The PTG module uses 8-bit commands, called
“Steps”, that the user writes to the PTG Queue register
(PTGQUE0-PTQUE15) which performs operations,
such as wait for input signal, generate output trigger
and wait for timer.
- PWM
- Comparator
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FIGURE 17-1:
PTG BLOCK DIAGRAM
PTGHOLD
PTGL0<15:0>
PTGTxLIM<15:0>
PTGCxLIM<15:0>
PTGSDLIM<15:0>
PTGADJ
PTG General
Purpose
PTG Step
Delay Timer
PTG Loop
Counter x
Timerx
Step Command
PTGBTE<15:0>
PTGCST<15:0>
PTGCON<15:0>
PTGDIV<4:0>
PTGCLK<2:0>
Step Command
PTGO0
•
•
•
PTGO31
FP
TAD
T1CLK
T2CLK
T3CLK
FOSC
PTG Control Logic
Step Command
Step Command
PTG0IF
•
•
•
PWM
OC1
OC2
IC1
PTG3IF
CMPx
ADC
INT2
CNVCHSEL<5:0>
PTGQPTR<4:0>
PTG Watchdog
Timer(1)
PTGWDTIF
PTGQUE0
PTGQUE1
Command
Decoder
PTGQUE14
PTGQUE15
PTGSTEPIF
Note 1: This is a dedicated Watchdog Timer for the PTG module and is independent of the device Watchdog Timer.
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17.2 PTG Control Registers
REGISTER 17-1: PTGCST: PTG CONTROL/STATUS REGISTER
R/W-0
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
PTGEN
PTGSIDL
PTGTOGL
PTGSWT(2) PTGSSEN
PTGIVIS
bit 15
bit 8
R/W-0
HS-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
PTGSTRT
PTGWDTO
PTGITM1(1) PTGITM0(1)
bit 7
bit 0
Legend:
HS = Hardware Settable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
PTGEN: PTG Module Enable bit
1= PTG module is enabled
0= PTG module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
PTGSIDL: PTG Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
PTGTOGL: PTG TRIG Output Toggle Mode bit
1= Toggles the state of the PTGOx for each execution of the PTGTRIGcommand
0= Each execution of the PTGTRIGcommand will generate a single PTGOx pulse determined by the
value in the PTGPWDx bits
bit 11
bit 10
Unimplemented: Read as ‘0’
PTGSWT: PTG Software Trigger bit(2)
1= Triggers the PTG module
0= No action (clearing this bit will have no effect)
bit 9
bit 8
PTGSSEN: PTG Enable Single-Step bit
1= Enables Single-Step mode
0= Disables Single-Step mode
PTGIVIS: PTG Counter/Timer Visibility Control bit
1= Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the current values of their
corresponding Counter/Timer registers (PTGSD, PTGCx, PTGTx)
0= Reads of the PTGSDLIM, PTGCxLIM or PTGTxLIM registers return the value previously written to
those PTG Limit registers
bit 7
PTGSTRT: Start PTG Sequencer bit
1= Starts to sequentially execute commands (Continuous mode)
0= Stops executing commands
bit 6
PTGWDTO: PTG Watchdog Timer Time-out Status bit
1= PTG Watchdog Timer has timed out
0= PTG Watchdog Timer has not timed out.
bit 5-2
Unimplemented: Read as ‘0’
Note 1: These bits apply to the PTGWHIand PTGWLOcommands only.
2: This bit is only used with the PTGCTRLStep command software trigger option.
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REGISTER 17-1: PTGCST: PTG CONTROL/STATUS REGISTER (CONTINUED)
bit 1-0
PTGITM<1:0>: PTG Input Trigger Command Operating Mode bits(1)
11= Single level detect with Step delay is not executed on exit of command (regardless of PTGCTRL
command)
10= Single level detect with Step delay is executed on exit of command
01= Continuous edge detect with Step delay is not executed on exit of command (regardless of
PTGCTRL command)
00= Continuous edge detect with Step delay is executed on exit of command
Note 1: These bits apply to the PTGWHIand PTGWLOcommands only.
2: This bit is only used with the PTGCTRLStep command software trigger option.
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REGISTER 17-2: PTGCON: PTG CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGCLK2
PTGCLK1
PTGCLK0
PTGDIV4
PTGDIV3
PTGDIV2
PTGDIV1
PTGDIV0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
PTGWDT0
bit 0
PTGPWD3
PTGPWD2
PTGPWD1 PTGPWD0
PTGWDT2
PTGWDT1
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-13
PTGCLK<2:0>: Select PTG Module Clock Source bits
111= CLC2
110= CLC1
101= PTG module clock source will be T3CLK
100= PTG module clock source will be T2CLK
011= PTG module clock source will be T1CLK
010= PTG module clock source will be TAD
001= PTG module clock source will be FOSC
000= PTG module clock source will be FP
bit 12-8
PTGDIV<4:0>: PTG Module Clock Prescaler (divider) bits
11111= Divide-by-32
11110= Divide-by-31
•
•
•
00001= Divide-by-2
00000= Divide-by-1
bit 7-4
PTGPWD<3:0>: PTG Trigger Output Pulse-Width bits
1111= All trigger outputs are 16 PTG clock cycles wide
1110= All trigger outputs are 15 PTG clock cycles wide
•
•
•
0001= All trigger outputs are 2 PTG clock cycles wide
0000= All trigger outputs are 1 PTG clock cycle wide
bit 3
Unimplemented: Read as ‘0’
bit 2-0
PTGWDT<2:0>: Select PTG Watchdog Timer Time-out Count Value bits
111= Watchdog Timer will time-out after 512 PTG clocks
110= Watchdog Timer will time-out after 256 PTG clocks
101= Watchdog Timer will time-out after 128 PTG clocks
100= Watchdog Timer will time-out after 64 PTG clocks
011= Watchdog Timer will time-out after 32 PTG clocks
010= Watchdog Timer will time-out after 16 PTG clocks
001= Watchdog Timer will time-out after 8 PTG clocks
000= Watchdog Timer is disabled
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REGISTER 17-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCTS1
IC4TSS
IC3TSS
IC2TSS
IC1TSS
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OC4CS
OC3CS
OC2CS
OC1CS
OC4TSS
OC3TSS
OC2TSS
OC1TSS
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
ADCTS1: Sample Trigger PTGO12 for ADCx bit
1= Generates trigger when the broadcast command is executed
0= Does not generate trigger when the broadcast command is executed
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
IC4TSS: Trigger/Synchronization Source for IC4 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
IC3TSS: Trigger/Synchronization Source for IC3 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
IC2TSS: Trigger/Synchronization Source for IC2 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
IC1TSS: Trigger/Synchronization Source for IC1 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
OC4CS: Clock Source for OC4 bit
1= Generates clock pulse when the broadcast command is executed
0= Does not generate clock pulse when the broadcast command is executed
OC3CS: Clock Source for OC3 bit
1= Generates clock pulse when the broadcast command is executed
0= Does not generate clock pulse when the broadcast command is executed
OC2CS: Clock Source for OC2 bit
1= Generates clock pulse when the broadcast command is executed
0= Does not generate clock pulse when the broadcast command is executed
OC1CS: Clock Source for OC1 bit
1= Generates clock pulse when the broadcast command is executed
0= Does not generate clock pulse when the broadcast command is executed
OC4TSS: Trigger/Synchronization Source for OC4 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
OC3TSS: Trigger/Synchronization Source for OC3 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION= 1111Step command.
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REGISTER 17-3: PTGBTE: PTG BROADCAST TRIGGER ENABLE REGISTER(1,2) (CONTINUED)
bit 1
OC2TSS: Trigger/Synchronization Source for OC2 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
bit 0
OC1TSS: Trigger/Synchronization Source for OC1 bit
1= Generates trigger/synchronization when the broadcast command is executed
0= Does not generate trigger/synchronization when the broadcast command is executed
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
2: This register is only used with the PTGCTRL OPTION= 1111Step command.
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REGISTER 17-4: PTGT0LIM: PTG TIMER0 LIMIT REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PTGT0LIM<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT0LIM<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGT0LIM<15:0>: PTG Timer0 Limit Register bits
General purpose Timer0 Limit register (effective only with a PTGT0Step command).
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
REGISTER 17-5: PTGT1LIM: PTG TIMER1 LIMIT REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT1LIM<15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
PTGT1LIM<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGT1LIM<15:0>: PTG Timer1 Limit Register bits
General purpose Timer1 Limit register (effective only with a PTGT1Step command).
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
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REGISTER 17-6: PTGSDLIM: PTG STEP DELAY LIMIT REGISTER(1,2)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PTGSDLIM<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGSDLIM<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGSDLIM<15:0>: PTG Step Delay Limit Register bits
Holds a PTG Step delay value, representing the number of additional PTG clocks, between the start
of a Step command and the completion of a Step command.
Note 1: A base Step delay of one PTG clock is added to any value written to the PTGSDLIM register
(Step Delay = (PTGSDLIM) + 1).
2: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
REGISTER 17-7: PTGC0LIM: PTG COUNTER 0 LIMIT REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC0LIM<15:8>
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC0LIM<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGC0LIM<15:0>: PTG Counter 0 Limit Register bits
May be used to specify the loop count for the PTGJMPC0Step command or as a limit register for the
General Purpose Counter 0.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
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REGISTER 17-8: PTGC1LIM: PTG COUNTER 1 LIMIT REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PTGC1LIM<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGC1LIM<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGC1LIM<15:0>: PTG Counter 1 Limit Register bits
May be used to specify the loop count for the PTGJMPC1Step command or as a limit register for the
General Purpose Counter 1.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
REGISTER 17-9: PTGHOLD: PTG HOLD REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGHOLD<15:8>
bit 15
R/W-0
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGHOLD<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGHOLD<15:0>: PTG General Purpose Hold Register bits
Holds user-supplied data to be copied to the PTGTxLIM, PTGCxLIM, PTGSDLIM or PTGL0 register
with the PTGCOPYcommand.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
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REGISTER 17-10: PTGADJ: PTG ADJUST REGISTER(1)
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PTGADJ<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGADJ<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGADJ<15:0>: PTG Adjust Register bits
This register holds user-supplied data to be added to the PTGTxLIM, PTGCxLIM, PTGSDLIM or
PTGL0 register with the PTGADDcommand.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
REGISTER 17-11: PTGL0: PTG LITERAL 0 REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
PTGL0<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PTGL0<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PTGL0<15:0>: PTG Literal 0 Register bits
This register holds the 6-bit value to be written to the CNVCHSEL<5:0> bits (ADCON3L<5:0>) with
the PTGCTRLStep command.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
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REGISTER 17-12: PTGQPTR: PTG STEP QUEUE POINTER REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTGQPTR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
PTGQPTR<4:0>: PTG Step Queue Pointer Register bits
This register points to the currently active Step command in the Step queue.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
REGISTER 17-13: PTGQUEx: PTG STEP QUEUE REGISTER x (x = 0-15)(1,3)
R/W-0
R/W-0
R/W-0
R/W-0
STEP(2x + 1)<7:0>(2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
STEP(2x)<7:0>(2)
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
STEP(2x + 1)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x +1) command byte.
STEP(2x)<7:0>: PTG Step Queue Pointer Register bits(2)
A queue location for storage of the STEP(2x) command byte.
Note 1: This register is read-only when the PTG module is executing Step commands (PTGEN = 1and
PTGSTRT = 1).
2: Refer to Table 17-1 for the Step command encoding.
3: The Step registers maintain their values on any type of Reset.
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17.3 Step Commands and Format
TABLE 17-1: PTG STEP COMMAND FORMAT
Step Command Byte:
STEPx<7:0>
CMD<3:0>
OPTION<3:0>
bit 7
bit 4 bit 3
bit 0
bit 7-4
Step
Command
CMD<3:0>
Command Description
0000
0001
PTGCTRL
PTGADD
Execute control command as described by OPTION<3:0>
Add contents of PTGADJ register to target register as described by
OPTION<3:0>
PTGCOPY
PTGSTRB
PTGWHI
PTGWLO
Copy contents of PTGHOLD register to target register as described by
OPTION<3:0>
001x
0100
0101
Copy the value contained in CMD0:OPTION<3:0> to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
Wait for a low-to-high edge input from selected PTG trigger input as described
by OPTION<3:0>
Wait for a high-to-low edge input from selected PTG trigger input as described
by OPTION<3:0>
0110
0111
100x
101x
Reserved
PTGIRQ
Reserved
Generate individual interrupt request as described by OPTION<3:0>
Generate individual trigger output as described by <<CMD0>:OPTION<3:0>>
PTGTRIG
PTGJMP
Copy the value indicated in <<CMD0>:OPTION<3:0>> to the PTG Queue
Pointer (PTGQPTR) and jump to that Step queue
110x
PTGJMPC0
PTGC0 = PTGC0LIM: Increment the PTG Queue Pointer (PTGQPTR)
PTGC0 PTGC0LIM: Increment PTG Counter 0 (PTGC0) and copy the value
indicated in <<CMD0>:OPTION<3:0>> to the PTG Queue Pointer (PTGQPTR)
and jump to that Step queue
111x
PTGJMPC1
PTGC1 = PTGC1LIM: Increment the PTG Queue Pointer (PTGQPTR)
PTGC1 PTGC1LIM: Increment PTG Counter 1 (PTGC1) and copy the value
indicated in <<CMD0>:OPTION<3:0>> to the PTG Queue Pointer (PTGQPTR)
and jump to that Step queue
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOPinstruction).
2: Refer to Table 17-2 for the trigger output descriptions.
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TABLE 17-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0
Step
Command
OPTION<3:0>
Option Description
PTGCTRL(1)
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
Reserved
Reserved
Disable PTG Step Delay Timer (PTGSD)
Reserved
Reserved
Reserved
Enable PTG Step Delay Timer (PTGSD)
Reserved
Start and wait for the PTG Timer0 to match the PTG Timer0 Limit register
Start and wait for the PTG Timer1 to match the PTG Timer1 Limit register
Reserved
Wait for software trigger bit transition from low-to-high before continuing
(PTGSWT = 0to 1)
1100
1101
1110
1111
Copy contents of the PTG Counter 0 register to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
Copy contents of the PTG Counter 1 register to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
Copy contents of the PTG Literal 0 register to the CNVCHSEL<5:0> bits
(ADCON3L<5:0>)
Generate the triggers indicated in the PTG Broadcast Trigger Enable register
(PTGBTE)
PTGADD(1)
0000
0001
0010
0011
0100
Add contents of PTGADJ register to the PTG Counter 0 Limit register (PTGC0LIM)
Add contents of PTGADJ register to the PTG Counter 1 Limit register (PTGC1LIM)
Add contents of PTGADJ register to the PTG Timer0 Limit register (PTGT0LIM)
Add contents of PTGADJ register to the PTG Timer1 Limit register (PTGT1LIM)
Add contents of PTGADJ register to the PTG Step Delay Limit register
(PTGSDLIM)
0101
0110
0111
1000
Add contents of PTGADJ register to the PTG Literal 0 register (PTGL0)
Reserved
Reserved
PTGCOPY(1)
Copy contents of PTGHOLD register to the PTG Counter 0 Limit register
(PTGC0LIM)
1001
Copy contents of PTGHOLD register to the PTG Counter 1 Limit register
(PTGC1LIM)
1010
1011
1100
Copy contents of PTGHOLD register to the PTG Timer0 Limit register (PTGT0LIM)
Copy contents of PTGHOLD register to the PTG Timer1 Limit register (PTGT1LIM)
Copy contents of PTGHOLD register to the PTG Step Delay Limit register
(PTGSDLIM)
1101
1110
1111
Copy contents of PTGHOLD register to the PTG Literal 0 register (PTGL0)
Reserved
Reserved
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOPinstruction).
2: Refer to Table 17-2 for the trigger output descriptions.
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TABLE 17-1: PTG STEP COMMAND FORMAT (CONTINUED)
bit 3-0
Step
Command
OPTION<3:0>
Option Description
PTGWHI(1) or
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
0001
0010
0011
0100
PWM Special Event Trigger
PTGWLO(1)
PWM master time base synchronization output
PWM1 interrupt
PWM2 interrupt
PWM3 interrupt
PWM4 interrupt
PWM5 interrupt
OC1 trigger event
OC2 trigger event
IC1 trigger event
CMP1 trigger event
CMP2 trigger event
CMP3 trigger event
CMP4 trigger event
ADC conversion done interrupt
INT2 external interrupt
Generate PTG Interrupt 0
Generate PTG Interrupt 1
Generate PTG Interrupt 2
Generate PTG Interrupt 3
Reserved
PTGIRQ(1)
•
•
•
•
•
•
1111
00000
00001
Reserved
PTGO0
PTGO1
PTGTRIG(2)
•
•
•
•
•
•
11110
11111
PTGO30
PTGO31
Note 1: All reserved commands or options will execute but have no effect (i.e., execute as a NOPinstruction).
2: Refer to Table 17-2 for the trigger output descriptions.
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TABLE 17-2: PTG OUTPUT DESCRIPTIONS
PTG Output
PTG Output Description
Number
PTGO0
Trigger/synchronization source for OC1
Trigger/synchronization source for OC2
Trigger/synchronization source for OC3
Trigger/synchronization source for OC4
Clock source for OC1
Clock source for OC2
Clock source for OC3
Clock source for OC4
Trigger/synchronization source for IC1
Trigger/synchronization source for IC2
Trigger/synchronization source for IC3
Trigger/synchronization source for IC4
Sample trigger for ADC
Reserved
PTGO1
PTGO2
PTGO3
PTGO4
PTGO5
PTGO6
PTGO7
PTGO8
PTGO9
PTGO10
PTGO11
PTGO12
PTGO13
PTGO14
PTGO15
PTGO16
PTGO17
PTGO18
PTGO19
PTGO20
PTGO21
PTGO22
PTGO23
PTGO24
PTGO25
PTGO26
PTGO27
PTGO28
PTGO29
PTGO30
PTGO31
Reserved
Reserved
PWM time base synchronous source for PWM3
PWM time base synchronous source for PWM4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
CLC1 input
CLC2 input
CLC3 input
CLC4 input
PTG output to PPS input selection, RPI6
PTG output to PPS input selection, RPI7
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The SPI serial interface consists of four pins:
18.0 SERIAL PERIPHERAL
• SDIx: Serial Data Input
INTERFACE (SPI)
• SDOx: Serial Data Output
• SCKx: Shift Clock Input or Output
Note:
This data sheet summarizes the features of
the dsPIC33EPXXXGS70X/80X family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Serial Peripheral Interface (SPI) with
Audio Codec Support” (DS70005136) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
• SSx: Active-Low Slave Select or Frame
Synchronization I/O Pulse
The SPI module can be configured to operate using
two, three or four pins. In the 3-pin mode, SSx is not
used. In the 2-pin mode, both SDOx and SSx are not
used.
The SPI module has the ability to generate three inter-
rupts, reflecting the events that occur during the data
communication. The following types of interrupts can
be generated:
The Serial Peripheral Interface (SPI) module is a
synchronous serial interface useful for communicating
with other peripheral or microcontroller devices. These
peripheral devices may be serial EEPROMs, shift
registers, display drivers, A/D Converters, etc. The SPI
module is compatible with the Motorola® SPI and SIOP
interfaces. All devices in the dsPIC33EPXXXGS70X/80X
family include three SPI modules.
1. Receive interrupts are signalled by SPIxRXIF.
This event occurs when:
- RX watermark interrupt
- SPIROV = 1
- SPIRBF = 1
- SPIRBE = 1
The module supports operation in two buffer modes. In
Standard mode, data is shifted through a single serial
buffer. In Enhanced Buffer mode, data is shifted
through a FIFO buffer. The FIFO level depends on the
configured mode.
provided the respective mask bits are enabled in
SPIxIMSKL/H.
2. Transmit interrupts are signalled by SPIxTXIF.
This event occurs when:
- TX watermark interrupt
- SPITUR = 1
Variable length data can be transmitted and received,
from 2 to 32 bits.
- SPITBF = 1
Note:
Do not perform Read-Modify-Write opera-
tions (such as bit-oriented instructions) on
the SPIxBUF register in either Standard or
Enhanced Buffer mode.
- SPITBE = 1
provided the respective mask bits are enabled in
SPIxIMSKL/H.
3. General interrupts are signalled by SPIxIF. This
event occurs when
The module also supports a basic framed SPI protocol
while operating in either Master or Slave mode. A total
of four framed SPI configurations are supported.
- FRMERR = 1
- SPIBUSY = 1
- SRMT = 1
SPI3 also supports Audio modes. Four different Audio
modes are available.
• I2S
provided the respective mask bits are enabled in
SPIxIMSKL/H.
• Left Justified
• Right Justified
• PCM/DSP
Block diagrams of the module in Standard and Enhanced
modes are shown in Figure 18-1 and Figure 18-2.
In each of these modes, the serial clock is free-running
and audio data is always transferred.
Note:
In this section, the SPI modules are
referred to together as SPIx, or separately
as SPI1, SPI2 or SPI3. Special Function
Registers will follow a similar notation. For
example, SPIxCON1 and SPIxCON2
refer to the control registers for any of the
three SPI modules.
If an audio protocol data transfer takes place between
two devices, then usually one device is the master and
the other is the slave. However, audio data can be
transferred between two slaves. Because the audio
protocols require free-running clocks, the master can
be a third party controller. In either case, the master
generates two free-running clocks: SCKx and LRC
(Left, Right Channel Clock/SSx/FSYNC).
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To set up the SPIx module for the Standard Master
mode of operation:
To set up the SPIx module for the Standard Slave mode
of operation:
1. If using interrupts:
1. Clear the SPIxBUF registers.
2. If using interrupts:
a) Clear the interrupt flag bits in the respective
IFSx register.
a) Clear the SPIxBUFL and SPIxBUFH
registers.
b) Set the interrupt enable bits in the
respective IECx register.
b) Set the interrupt enable bits in the
respective IECx register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1L
and SPIxCON1H registers with the MSTEN bit
(SPIxCON1L<5>) = 1.
3. Write the desired settings to the SPIxCON1L,
SPIxCON1H and SPIxCON2L registers with
the MSTEN bit (SPIxCON1L<5>) = 0.
3. Clear the SPIROV bit (SPIxSTATL<6>).
4. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
4. Clear the SMP bit.
5. If the CKE bit (SPIxCON1L<8>) is set, then the
SSEN bit (SPIxCON1L<7>) must be set to
enable the SSx pin.
5. Write the data to be transmitted to the SPIxBUFL
and SPIxBUFH registers. Transmission (and
reception) will start as soon as data is written to
the SPIxBUFL and SPIxBUFH registers.
6. Clear the SPIROV bit (SPIxSTATL<6>).
7. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
FIGURE 18-1:
SPIx MODULE BLOCK DIAGRAM (STANDARD MODE)
Internal
Data Bus
Write
Read
SPIxRXB
SPIxTXB
SPIxURDT
MSb
Receive
Transmit
SPIxRXSR
SPIxTXSR
MSb
SDIx
0
1
Shift
Control
SDOx
TXELM<5:0> = 6’b0
URDTEN
SSx & FSYNC
Control
Clock
Control
Edge
Select
MCLKEN
REFO
SSx/FSYNC
SCKx
Baud Rate
Generator
Peripheral Clock
Edge
Select
Clock
Control
Enable Master Clock
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To set up the SPIx module for the Enhanced Buffer
Master mode of operation:
To set up the SPIx module for the Enhanced Buffer
Slave mode of operation:
1. If using interrupts:
1. Clear the SPIxBUFL and SPIxBUFH registers.
2. If using interrupts:
a) Clear the interrupt flag bits in the respective
IFSx register.
a) Clear the interrupt flag bits in the respective
IFSx register.
b) Set the interrupt enable bits in the
respective IECx register.
b) Set the interrupt enable bits in the
respective IECx register.
c) Write the SPIxIP bits in the respective IPCx
register.
c) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
2. Write the desired settings to the SPIxCON1L,
SPIxCON1H and SPIxCON2L registers with
MSTEN (SPIxCON1L<5>) = 1.
3. Write the desired settings to the SPIxCON1L,
SPIxCON1H and SPIxCON2L registers with the
MSTEN bit (SPIxCON1L<5>) = 0.
3. Clear the SPIROV bit (SPIxSTATL<6>).
4. Select Enhanced Buffer mode by setting the
ENHBUF bit (SPIxCON1L<0>).
4. Clear the SMP bit.
5. If the CKE bit is set, then the SSEN bit must be
set, thus enabling the SSx pin.
5. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
6. Clear the SPIROV bit (SPIxSTATL<6>).
6. Write the data to be transmitted to the
SPIxBUFL and SPIxBUFH registers. Transmis-
sion (and reception) will start as soon as data is
written to the SPIxBUFL and SPIxBUFH
registers.
7. Select Enhanced Buffer mode by setting the
ENHBUF bit (SPIxCON1L<0>).
8. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
FIGURE 18-2:
SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE)
Internal
Data Bus
Write
Read
SPIxRXB
SPIxTXB
SPIxURDT
MSb
Transmit
Receive
SPIxRXSR
SPIxTXSR
MSb
SDIx
0
1
Shift
Control
SDOx
TXELM<5:0> = 6’b0
URDTEN
SSx & FSYNC
Control
Clock
Control
Edge
Select
MCLKEN
SSx/FSYNC
SCKx
REFO
Baud Rate
Generator
Peripheral Clock
Edge
Select
Clock
Control
Enable Master Clock
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To set up the SPIx module for Audio mode:
3. Write the desired settings to the SPIxCON1L,
SPIxCON1H and SPIxCON2L registers with
AUDEN (SPIxCON1H<15>) = 1.
1. Clear the SPIxBUFL and SPIxBUFH registers.
2. If using interrupts:
4. Clear the SPIROV bit (SPIxSTATL<6>).
a) Clear the interrupt flag bits in the respective
IFSx register.
5. Enable SPIx operation by setting the SPIEN bit
(SPIxCON1L<15>).
b) Set the interrupt enable bits in the
respective IECx register.
6. Write the data to be transmitted to the SPIxBUFL
and SPIxBUFH registers. Transmission (and
reception) will start as soon as data is written to
the SPIxBUFL and SPIxBUFH registers.
a) Write the SPIxIP bits in the respective IPCx
register to set the interrupt priority.
REGISTER 18-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW
R/W-0
SPIEN
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
SPISIDL
DISSDO
MODE32(1,4) MODE16(1,4)
bit 15
bit 8
R/W-0
SSEN(2)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
R/W-0
MCLKEN(3)
R/W-0
SPIFE
R/W-0
MSTEN
DISSDI
DISSCK
ENHBUF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx On bit
1= Enables module
0= Turns off and resets module, disables clocks, disables interrupt event generation, allows SFR
modifications
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: SPIx Stop in Idle Mode bit
1= Halts in CPU Idle mode
0= Continues to operate in CPU Idle mode
bit 12
DISSDO: Disable SDOx Output Port bit
1= SDOx pin is not used by the module; pin is controlled by port function
0= SDOx pin is controlled by the module
bit 11-10
MODE32 and MODE16: Serial Word Length Select bits(1,4)
MODE32 MODE16
AUDEN
Communication
1
0
0
1
1
0
0
x
1
0
1
0
1
0
32-Bit
0
16-Bit
8-Bit
24-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
32-Bit Data, 32-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit Data, 16-Bit FIFO, 32-Bit Channel/64-Bit Frame
16-Bit FIFO, 16-Bit Channel/32-Bit Frame
1
Note 1: When AUDEN (SPIxCON1H<15>) = 1, this module functions as if CKE = 0, regardless of its actual value.
2: When FRMEN = 1, SSEN is not used.
3: MCLKEN can only be written when the SPIEN bit = 0.
4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.
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REGISTER 18-1: SPIxCON1L: SPIx CONTROL REGISTER 1 LOW (CONTINUED)
bit 9
SMP: SPIx Data Input Sample Phase bit
Master Mode:
1= Input data is sampled at the end of data output time
0= Input data is sampled at the middle of data output time
Slave Mode:
Input data is always sampled at the middle of data output time, regardless of the SMP setting.
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
CKE: SPIx Clock Edge Select bit(1)
1= Transmit happens on transition from active clock state to Idle clock state
0= Transmit happens on transition from Idle clock state to active clock state
SSEN: Slave Select Enable bit (Slave mode)(2)
1= SSx pin is used by the macro in Slave mode; SSx pin is used as the slave select input
0= SSx pin is not used by the macro (SSx pin will be controlled by the port I/O)
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
DISSDI: Disable SDIx Input Port bit
1= SDIx pin is not used by the module; pin is controlled by port function
0= SDIx pin is controlled by the module
DISSCK: Disable SCKx Output Port bit
1= SCKx pin is not used by the module; pin is controlled by port function
0= SCKx pin is controlled by the module
MCLKEN: Master Clock Enable bit(3)
1= REFO is used by the Baud Rate Generator (BRG)
0= Peripheral clock is used by the BRG
SPIFE: Frame Sync Pulse Edge Select bit
1= Frame Sync pulse (Idle-to-active edge) coincides with the first bit clock
0= Frame Sync pulse (Idle-to-active edge) precedes the first bit clock
ENHBUF: Enhanced Buffer Enable bit
1= Enhanced Buffer mode is enabled
0= Enhanced Buffer mode is disabled
Note 1: When AUDEN (SPIxCON1H<15>) = 1, this module functions as if CKE = 0, regardless of its actual value.
2: When FRMEN = 1, SSEN is not used.
3: MCLKEN can only be written when the SPIEN bit = 0.
4: This channel is not meaningful for DSP/PCM mode as LRC follows FRMSYPW.
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REGISTER 18-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AUDEN(1) SPISGNEXT
IGNROV
IGNTUR
AUDMONO(2) URDTEN(3) AUDMOD1(4) AUDMOD0(4)
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FRMEN
FRMSYNC
FRMPOL
MSSEN
FRMSYPW
FRMCNT2
FRMCNT1
FRMCNT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
AUDEN: Audio Codec Support Enable bit(1)
1= Audio protocol is enabled; MSTEN controls the direction of both SCKx and frame (a.k.a. LRC), and
this module functions as if FRMEN = 1, FRMSYNC = MSTEN, FRMCNT<2:0> = 001and SMP = 0,
regardless of their actual values
0= Audio protocol is disabled
bit 14
bit 13
SPISGNEXT: SPIx Sign-Extend RX FIFO Read Data Enable bit
1= Data from RX FIFO is sign-extended
0= Data from RX FIFO is not sign-extended
IGNROV: Ignore Receive Overflow bit
1= A Receive Overflow (ROV) is NOT a critical error; during ROV, data in the FIFO is not overwritten
by the receive data
0= A ROV is a critical error that stops SPI operation
bit 12
IGNTUR: Ignore Transmit Underrun bit
1= A Transmit Underrun (TUR) is NOT a critical error and data indicated by URDTEN is transmitted
until the SPIxTXB is not empty
0= A TUR is a critical error that stops SPI operation
bit 11
bit 10
bit 9-8
AUDMONO: Audio Data Format Transmit bit(2)
1= Audio data is mono (i.e., each data word is transmitted on both left and right channels)
0= Audio data is stereo
URDTEN: Transmit Underrun Data Enable bit(3)
1= Transmits data out of SPIxURDT register during Transmit Underrun conditions
0= Transmits the last received data during Transmit Underrun conditions
AUDMOD<1:0>: Audio Protocol Mode Selection bits(4)
11= PCM/DSP mode
10= Right Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
01= Left Justified mode: This module functions as if SPIFE = 1, regardless of its actual value
00= I2S mode: This module functions as if SPIFE = 0, regardless of its actual value
bit 7
FRMEN: Framed SPIx Support bit
1= Framed SPIx support is enabled (SSx pin is used as the FSYNC input/output)
0= Framed SPIx support is disabled
Note 1: AUDEN can only be written when the SPIEN bit = 0.
2: AUDMONO can only be written when the SPIEN bit = 0and is only valid for AUDEN = 1.
3: URDTEN is only valid when IGNTUR = 1.
4: The AUDMOD<1:0> bits can only be written when the SPIEN bit = 0and are only valid when AUDEN = 1.
When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
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REGISTER 18-2: SPIxCON1H: SPIx CONTROL REGISTER 1 HIGH (CONTINUED)
bit 6
bit 5
bit 4
FRMSYNC: Frame Sync Pulse Direction Control bit
1= Frame Sync pulse input (slave)
0= Frame Sync pulse output (master)
FRMPOL: Frame Sync/Slave Select Polarity bit
1= Frame Sync pulse/slave select is active-high
0= Frame Sync pulse/slave select is active-low
MSSEN: Master Mode Slave Select Enable bit
1= SPIx slave select support is enabled with polarity determined by FRMPOL (SSx pin is automatically
driven during transmission in Master mode)
0= Slave select SPIx support is disabled (SSx pin will be controlled by port I/O)
bit 3
FRMSYPW: Frame Sync Pulse-Width bit
1= Frame Sync pulse is one serial word length wide (as defined by MODE<32,16>/WLENGTH<4:0>)
0= Frame Sync pulse is one clock (SCK) wide
bit 2-0
FRMCNT<2:0>: Frame Sync Pulse Counter bits
Controls the number of serial words transmitted per Sync pulse.
111= Reserved
110= Reserved
101= Generates a Frame Sync pulse on every 32 serial words
100= Generates a Frame Sync pulse on every 16 serial words
011= Generates a Frame Sync pulse on every 8 serial words
010= Generates a Frame Sync pulse on every 4 serial words
001= Generates a Frame Sync pulse on every 2 serial words (value used by audio protocols)
000= Generates a Frame Sync pulse on each serial word
Note 1: AUDEN can only be written when the SPIEN bit = 0.
2: AUDMONO can only be written when the SPIEN bit = 0and is only valid for AUDEN = 1.
3: URDTEN is only valid when IGNTUR = 1.
4: The AUDMOD<1:0> bits can only be written when the SPIEN bit = 0and are only valid when AUDEN = 1.
When NOT in PCM/DSP mode, this module functions as if FRMSYPW = 1, regardless of its actual value.
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REGISTER 18-3: SPIxCON2L: SPIx CONTROL REGISTER 2 LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
WLENGTH<4:0>(1,2)
R/W-0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
WLENGTH<4:0>: Variable Word Length bits(1,2)
11111= 32-bit data
11110= 31-bit data
11101= 30-bit data
11100= 29-bit data
11011= 28-bit data
11010= 27-bit data
11001= 26-bit data
11000= 25-bit data
10111= 24-bit data
10110= 23-bit data
10101= 22-bit data
10100= 21-bit data
10011= 20-bit data
10010= 19-bit data
10001= 18-bit data
10000= 17-bit data
01111= 16-bit data
01110= 15-bit data
01101= 14-bit data
01100= 13-bit data
01011= 12-bit data
01010= 11-bit data
01001= 10-bit data
01000= 9-bit data
00111= 8-bit data
00110= 7-bit data
00101= 6-bit data
00100= 5-bit data
00011= 4-bit data
00010= 3-bit data
00001= 2-bit data
00000= See MODE<32,16> bits in SPIxCON1L<11:10>
Note 1: These bits are effective when AUDEN = 0only.
2: Varying the length by changing these bits does not affect the depth of the TX/RX FIFO.
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REGISTER 18-4: SPIxSTATL: SPIx STATUS REGISTER LOW
U-0
—
U-0
—
U-0
—
HS/R/C-0
FRMERR
HSC/R-0
SPIBUSY
U-0
—
U-0
—
HSC/R-0
SPITUR(1)
bit 15
bit 8
HSC/R-0
SRMT
HS/R/C-0
SPIROV
HSC/R-1
SPIRBE
U-0
—
HSC/R-1
SPITBE
U-0
—
HSC/R-0
SPITBF
HSC/R-0
SPIRBF
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented, read as ‘0’
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
bit 15-13
bit 12
Unimplemented: Read as ‘0’
FRMERR: SPIx Frame Error Status bit
1= Frame error is detected
0= No frame error is detected
bit 11
SPIBUSY: SPIx Activity Status bit
1= Module is currently busy with some transactions
0= No ongoing transactions (at time of read)
bit 10-9
bit 8
Unimplemented: Read as ‘0’
SPITUR: SPIx Transmit Underrun Status bit(1)
1= Transmit buffer has encountered a Transmit Underrun condition
0= Transmit buffer does not have a Transmit Underrun condition
bit 7
bit 6
bit 5
SRMT: Shift Register Empty Status bit
1= No current or pending transactions (i.e., neither SPIxTXB or SPIxTXSR contains data to transmit)
0= Current or pending transactions
SPIROV: SPIx Receive Overflow Status bit
1= A new byte/half-word/word has been completely received when the SPIxRXB was full
0= No overflow
SPIRBE: SPIx RX Buffer Empty Status bit
1= RX buffer is empty
0= RX buffer is not empty
Standard Buffer mode:
Automatically set in hardware when SPIxBUF is read from, reading SPIxRXB. Automatically cleared in
hardware when SPIx transfers data from SPIxRXSR to SPIxRXB.
Enhanced Buffer mode:
Indicates RXELM<5:0> = 000000.
bit 4
Unimplemented: Read as ‘0’
Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the
Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by
software.
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REGISTER 18-4: SPIxSTATL: SPIx STATUS REGISTER LOW (CONTINUED)
bit 3
SPITBE: SPIx Transmit Buffer Empty Status bit
1= SPIxTXB is empty
0= SPIxTXB is not empty
Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxTXB to SPIxTXSR. Automatically
cleared in hardware when SPIxBUF is written, loading SPIxTXB.
Enhanced Buffer mode:
Indicates TXELM<5:0> = 000000.
bit 2
Unimplemented: Read as ‘0’
bit 1
SPITBF: SPIx Transmit Buffer Full Status bit
1= SPIxTXB is full
0= SPIxTXB not full
Standard Buffer mode:
Automatically set in hardware when SPIxBUF is written, loading SPIxTXB. Automatically cleared in
hardware when SPIx transfers data from SPIxTXB to SPIxTXSR.
Enhanced Buffer mode:
Indicates TXELM<5:0> = 111111.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= SPIxRXB is full
0= SPIxRXB is not full
Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxRXSR to SPIxRXB. Automatically
cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer mode:
Indicates RXELM<5:0> = 111111.
Note 1: SPITUR is cleared when SPIEN = 0. When IGNTUR = 1, SPITUR provides dynamic status of the
Transmit Underrun condition, but does not stop RX/TX operation and does not need to be cleared by
software.
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REGISTER 18-5: SPIxSTATH: SPIx STATUS REGISTER HIGH
U-0
—
U-0
—
HSC/R-0
RXELM5(3)
HSC/R-0
RXELM4(2)
HSC/R-0
RXELM3(1)
HSC/R-0
RXELM2
HSC/R-0
RXELM1
HSC/R-0
RXELM0
bit 15
bit 8
U-0
—
U-0
—
HSC/R-0
TXELM5(3)
HSC/R-0
TXELM4(2)
HSC/R-0
TXELM3(1)
HSC/R-0
TXELM2
HSC/R-0
TXELM1
HSC/R-0
TXELM0
bit 7
bit 0
Legend:
HSC = Hardware Settable/Clearable bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
bit 7-6
Unimplemented: Read as ‘0’
RXELM<5:0>: Receive Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
Unimplemented: Read as ‘0’
bit 5-0
TXELM<5:0>: Transmit Buffer Element Count bits (valid in Enhanced Buffer mode)(1,2,3)
Note 1: RXELM3 and TXELM3 bits are only present when FIFODEPTH = 8 or higher.
2: RXELM4 and TXELM4 bits are only present when FIFODEPTH = 16 or higher.
3: RXELM5 and TXELM5 bits are only present when FIFODEPTH = 32.
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REGISTER 18-6: SPIxIMSKL: SPIx INTERRUPT MASK REGISTER LOW
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
SPITUREN
bit 8
FRMERREN
BUSYEN
bit 15
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
SPIRBFEN
bit 0
SRMTEN
SPIROVEN
SPIRBEN
SPITBEN
SPITBFEN
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
FRMERREN: Enable Interrupt Events via FRMERR bit
1= Frame error generates an interrupt event
0= Frame error does not generate an interrupt event
bit 11
BUSYEN: Enable Interrupt Events via SPIBUSY bit
1= SPIBUSY generates an interrupt event
0= SPIBUSY does not generate an interrupt event
bit 10-9
bit 8
Unimplemented: Read as ‘0’
SPITUREN: Enable Interrupt Events via SPITUR bit
1= Transmit Underrun (TUR) generates an interrupt event
0= Transmit Underrun does not generate an interrupt event
bit 7
bit 6
bit 5
SRMTEN: Enable Interrupt Events via SRMT bit
1= Shift Register Empty (SRMT) generates interrupt events
0= Shift Register Empty does not generate interrupt events
SPIROVEN: Enable Interrupt Events via SPIROV bit
1= SPIx Receive Overflow (ROV) generates an interrupt event
0= SPIx Receive Overflow does not generate an interrupt event
SPIRBEN: Enable Interrupt Events via SPIRBE bit
1= SPIx RX buffer empty generates an interrupt event
0= SPIx RX buffer empty does not generate an interrupt event
bit 4
bit 3
Unimplemented: Read as ‘0’
SPITBEN: Enable Interrupt Events via SPITBE bit
1= SPIx transmit buffer empty generates an interrupt event
0= SPIx transmit buffer empty does not generate an interrupt event
bit 2
bit 1
Unimplemented: Read as ‘0’
SPITBFEN: Enable Interrupt Events via SPITBF bit
1= SPIx transmit buffer full generates an interrupt event
0= SPIx transmit buffer full does not generate an interrupt event
bit 0
SPIRBFEN: Enable Interrupt Events via SPIRBF bit
1= SPIx receive buffer full generates an interrupt event
0= SPIx receive buffer full does not generate an interrupt event
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REGISTER 18-7: SPIxIMSKH: SPIx INTERRUPT MASK REGISTER HIGH
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1,4)
(1,3)
(1,2)
(1)
(1)
RXWIEN
RXMSK5
RXMSK4
RXMSK3
RXMSK2
RXMSK1
RXMSK0
bit 15
bit 8
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
(1)
(1,4)
(1,3)
(1,2)
(1)
(1)
TXWIEN
TXMSK5
TXMSK4
TXMSK3
TXMSK2
TXMSK1
TXMSK0
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
RXWIEN: Receive Watermark Interrupt Enable bit
1= Triggers receive buffer element watermark interrupt when RXMSK<5:0> RXELM<5:0>
0= Disables receive buffer element watermark interrupt
bit 14
Unimplemented: Read as ‘0’
bit 13-8
RXMSK<5:0>: RX Buffer Mask bits(1,2,3,4)
RX mask bits; used in conjunction with the RXWIEN bit.
TXWIEN: Transmit Watermark Interrupt Enable bit
bit 7
1= Triggers transmit buffer element watermark interrupt when TXMSK<5:0> = TXELM<5:0>
0= Disables transmit buffer element watermark interrupt
bit 6
Unimplemented: Read as ‘0’
bit 5-0
TXMSK<5:0>: TX Buffer Mask bits(1,2,3,4)
TX mask bits; used in conjunction with the TXWIEN bit.
Note 1: Mask values higher than FIFODEPTH are not valid. The module will not trigger a match for any value in
this case.
2: RXMSK2 and TXMSK2 bits are only present when FIFODEPTH = 8 or higher.
3: RXMSK3 and TXMSK3 bits are only present when FIFODEPTH = 16 or higher.
4: RXMSK4 and TXMSK4 bits are only present when FIFODEPTH = 32.
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FIGURE 18-3:
SPIx MASTER/SLAVE CONNECTION (STANDARD MODE)
Processor 1 (SPIx Master)
Processor 2 (SPIx Slave)
SDOx
SDIx
Serial Receive Buffer
Serial Transmit Buffer
(2)
(2)
(SPIxRXB)
(SPIxTXB)
SDIx
SDOx
SDIx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
LSb
LSb
MSb
MSb
MSb
MSb
LSb
LSb
SDOx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
Serial Clock
Serial Transmit Buffer
SCKx
SCKx
Serial Receive Buffer
(2)
(2)
(SPIxTXB)
(SPIxRXB)
(1)
SSx
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
(2)
(2)
MSTEN (SPIxCON1L<5>) = 1)
MSSEN (SPIxCON1H<4>) =
1and MSTEN (SPIxCON1L<5>) = 0
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
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FIGURE 18-4:
SPIx MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES)
Processor 1 (SPIx Master)
Processor 2 (SPIx Slave)
SDOx
SDIx
Serial Transmit FIFO
Serial Receive FIFO
(2)
(2)
(SPIxRXB)
(SPIxTXB)
SDIx
SDOx
SDIx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
LSb
LSb
MSb
MSb
MSb
MSb
LSb
LSb
SDOx
Shift Register
(SPIxRXSR)
Shift Register
(SPIxTXSR)
Serial Clock
SCKx
Serial Transmit FIFO
SCKx
Serial Receive FIFO
(2)
(2)
(SPIxTXB)
(SPIxRXB)
(1)
SSx
SPIx Buffer
(SPIxBUF)
SPIx Buffer
(SPIxBUF)
(2)
(2)
MSTEN (SPIxCON1L<5>) = 1)
MSSEN (SPIxCON1H<4>) =
1
and MSTEN (SPIxCON1L<5>) =
0
Note 1: Using the SSx pin in Slave mode of operation is optional.
2: User must write transmit data to read the received data from SPIxBUF. The SPIxTXB and SPIxRXB registers
are memory-mapped to SPIxBUF.
FIGURE 18-5:
SPIx MASTER, FRAME MASTER CONNECTION DIAGRAM
PIC24F
Processor 2
(SPIx Master, Frame Master)
SDOx
SDIx
SDOx
SDIx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
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FIGURE 18-6:
FIGURE 18-7:
FIGURE 18-8:
SPIx MASTER, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
Processor 2
SPIx Master, Frame Slave)
SDOx
SDIx
SDOx
SDIx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
SPIx SLAVE, FRAME MASTER CONNECTION DIAGRAM
PIC24F
(SPIx Slave, Frame Master)
Processor 2
SDOx
SDIx
SDOx
SDIx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
SPIx SLAVE, FRAME SLAVE CONNECTION DIAGRAM
PIC24F
(SPIx Slave, Frame Slave)
Processor 2
SDOx
SDIx
SDIx
SDOx
Serial Clock
SCKx
SSx
SCKx
SSx
Frame Sync
Pulse
EQUATION 18-1: RELATIONSHIP BETWEEN DEVICE AND SPIx CLOCK SPEED
FPB
Baud Rate =
(2 * (SPIxBRG + 1))
Where:
FPB is the Peripheral Bus Clock Frequency.
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The I2C module offers the following key features:
• I2C Interface supporting both Master and Slave
modes of Operation
19.0 INTER-INTEGRATED CIRCUIT
2
(I C)
• I2C Slave mode Supports 7 and 10-Bit Addressing
• I2C Master mode Supports 7 and 10-Bit Addressing
• I2C Port allows Bidirectional Transfers between
Master and Slaves
• Serial Clock Synchronization for I2C Port can be
used as a Handshake Mechanism to Suspend
and Resume Serial Transfer (SCLREL control)
• I2C Supports Multi-Master Operation, Detects Bus
Collision and Arbitrates Accordingly
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this
data sheet, refer to “Inter-Integrated
Circuit (I2C)” (DS70000195) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
• System Management Bus (SMBus) Support
• Alternate I2C Pin Mapping (ASCLx/ASDAx)
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
2
19.1 I C Resources
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
The dsPIC33EPXXXGS70X/80X family of devices
contains two Inter-Integrated Circuit (I2C) modules:
I2C1 and I2C2.
19.1.1
KEY RESOURCES
The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
communication standard, with a 16-bit interface.
• “Inter-Integrated Circuit (I2C)” (DS70000195) in
the “dsPIC33/PIC24 Family Reference Manual”
The I2C module has a 2-pin interface:
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• The SCLx/ASCLx pin is clock
• The SDAx/ASDAx pin is data
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
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FIGURE 19-1:
I2Cx BLOCK DIAGRAM (x = 1 OR 2)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx/ASCLx
SDAx/ASDAx
I2CxRSR
LSb
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
Read
Write
Collision
Detect
I2CxCONH
I2CxCONL
Acknowledge
Generation
Read
Write
Clock
Stretching
Read
Write
Read
I2CxTRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
FP/2
I2CxBRG
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2
19.2 I C Control Registers
REGISTER 19-1: I2CxCONL: I2Cx CONTROL REGISTER LOW
R/W-0
I2CEN
U-0
—
R/W-0
HC/R/W-1
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
STRICT
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
HC/R/W-0
ACKEN
HC/R/W-0
RCEN
HC/R/W-0
PEN
HC/R/W-0
RSEN
HC/R/W-0
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
‘1’ = Bit is set
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module; all I2C pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: I2Cx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Releases SCLx clock
0= Holds SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). It is cleared by hard-
ware at the beginning of every slave data byte transmission. It is cleared by hardware at the end of every
slave address byte reception. It is cleared by hardware at the end of every slave data byte reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). It is cleared by hardware at the beginning
of every slave data byte transmission. It is cleared by hardware at the end of every slave address byte
reception.
bit 11
STRICT: Strict I2Cx Reserved Address Enable bit
1= Strict Reserved Addressing is Enabled:
In Slave mode, the device will NACK any reserved address. In Master mode, the device is allowed
to generate addresses within the reserved address space.
0= Reserved Addressing is Acknowledged:
In Slave mode, the device will ACK any reserved address. In Master mode, the device should not
address a slave device with a reserved address.
bit 10
bit 9
bit 8
A10M: 10-Bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control is disabled
0= Slew rate control is enabled
SMEN: SMBus Input Levels bit
1= Enables I/O pin thresholds compliant with SMBus specification
0= Disables SMBus input thresholds
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REGISTER 19-1: I2CxCONL: I2Cx CONTROL REGISTER LOW (CONTINUED)
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enables interrupt when a general call address is received in I2CxRSR (module is enabled for reception)
0= General call address is disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with the SCLREL bit.
1= Enables software controlled clock stretching
0= Disables software controlled clock stretching
bit 5
bit 4
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1= Sends NACK during Acknowledge
0= Sends ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit; it is
cleared by hardware at the end of the master Acknowledge sequence
0= Acknowledge sequence is not in progress
bit 3
bit 2
bit 1
bit 0
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C; it is cleared by hardware at the end of the eighth bit of the master
receive data byte
0= Receive sequence is not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiates Stop condition on SDAx and SCLx pins; it is cleared by hardware at the end of the master
Stop sequence
0= Stop condition is not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiates Repeated Start condition on SDAx and SCLx pins; it is cleared by hardware at the end of
the master Repeated Start sequence
0= Repeated Start condition is not in progress
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiates Start condition on SDAx and SCLx pins; it is cleared by hardware at the end of the master
Start sequence
0= Start condition is not in progress
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REGISTER 19-2: I2CxCONH: I2Cx CONTROL REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-0
PCIE
R/W-0
SCIE
R/W-0
BOEN
R/W-0
R/W-0
R/W-0
AHEN
R/W-0
DHEN
SDAHT
SBCDE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-7
bit 6
Unimplemented: Read as ‘0’
PCIE: Stop Condition Interrupt Enable bit (I2C Slave mode only)
1= Enables interrupt on detection of Stop condition
0= Stop detection interrupts are disabled
bit 5
bit 4
SCIE: Start Condition Interrupt Enable bit (I2C Slave mode only)
1= Enables interrupt on detection of Start or Restart conditions
0= Start detection interrupts are disabled
BOEN: Buffer Overwrite Enable bit (I2C Slave mode only)
1= I2CxRCV is updated and ACK is generated for a received address/data byte, ignoring the state of
the I2COV only if the RBF bit = 0
0= I2CxRCV is only updated when I2COV is clear
bit 3
bit 2
SDAHT: SDAx Hold Time Selection bit
1= Minimum of 300 ns hold time on SDAx after the falling edge of SCLx
0= Minimum of 100 ns hold time on SDAx after the falling edge of SCLx
SBCDE: Slave Mode Bus Collision Detect Enable bit (I2C Slave mode only)
1= Enables slave bus collision interrupts
0= Slave bus collision interrupts are disabled
If the rising edge of SCLx and SDAx is sampled low when the module is in a high state, the BCL bit is
set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.
bit 1
bit 0
AHEN: Address Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCLx for a matching received address byte, the SCLREL
(I2CxCONL<12>) bit will be cleared and SCLx will be held low
0= Address holding is disabled
DHEN: Data Hold Enable bit (I2C Slave mode only)
1= Following the 8th falling edge of SCLx for a received data byte, the slave hardware clears the
SCLREL (I2CxCONL<12>) bit and SCLx is held low
0= Data holding is disabled
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REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER
HSC/R-0
HSC/R-0
TRSTAT
HSC/R-0
ACKTIM
U-0
—
U-0
—
HS/R/C-0
BCL
HSC/R-0
GCSTAT
HSC/R-0
ADD10
ACKSTAT
bit 15
bit 8
HS/R/C-0
IWCOL
HS/R/C-0
I2COV
HSC/R-0
D_A
HSC/R/C-0 HSC/R/C-0
HSC/R-0
R_W
HSC/R-0
RBF
HSC/R-0
TBF
P
S
bit 7
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
‘0’ = Bit is cleared
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
bit 15
ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
1= NACK was received from slave
0= ACK was received from slave
It is set or cleared by hardware at the end of a slave Acknowledge.
bit 14
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
It is set by hardware at the beginning of master transmission. It is cleared by hardware at the end of slave
Acknowledge.
bit 13
ACKTIM: Acknowledge Time Status bit (I2C Slave mode only)
1= I2C bus is an Acknowledge sequence, set on the 8th falling edge of SCLx
0= Not an Acknowledge sequence, cleared on the 9th rising edge of SCLx
bit 12-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No bus collision detected
It is set by hardware at detection of a bus collision.
bit 9
bit 8
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
It is set by hardware when address matches the general call address. It is cleared by hardware at Stop
detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
It is set by hardware at the match of the 2nd byte of the matched 10-bit address. It is cleared by hardware
at Stop detection.
bit 7
bit 6
IWCOL: I2Cx Write Collision Detect bit
1= An attempt to write to the I2CxTRN register failed because the I2C module is busy
0= No collision
It is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software).
I2COV: I2Cx Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register was still holding the previous byte
0= No overflow
It is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
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REGISTER 19-3: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
D_A: Data/Address bit (I2C Slave mode only)
bit 5
bit 4
bit 3
bit 2
bit 1
1= Indicates that the last byte received was data
0= Indicates that the last byte received was a device address
It is cleared by hardware at a device address match. It is set by hardware by reception of a slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
It is set or cleared by hardware when a Start, Repeated Start or Stop is detected.
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
It is set or cleared by hardware when a Start, Repeated Start or Stop is detected.
R_W: Read/Write Information bit (I2C Slave mode only)
1= Read – Indicates data transfer is output from the slave
0= Write – Indicates data transfer is input to the slave
It is set or cleared by hardware after reception of an I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive is complete, I2CxRCV is full
0= Receive is not complete, I2CxRCV is empty
It is set by hardware when I2CxRCV is written with a received byte. It is cleared by hardware when
software reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit is in progress, I2CxTRN is full
0= Transmit is complete, I2CxTRN is empty
It is set by hardware when software writes to I2CxTRN. It is cleared by hardware at completion of a data
transmission.
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REGISTER 19-4: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSK<9:0>: Address Mask Select bits
For 10-Bit Address:
1= Enables masking for bit Ax of incoming message address; bit match is not required in this position
0= Disables masking for bit Ax; bit match is required in this position
For 7-Bit Address (I2CxMSK<6:0> only):
1= Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position
0= Disables masking for bit Ax + 1; bit match is required in this position
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The primary features of the UARTx module are:
20.0 UNIVERSAL ASYNCHRONOUS
• Full-Duplex, 8 or 9-Bit Data Transmission through
the UxTX and UxRX Pins
RECEIVER TRANSMITTER
(UART)
• Even, Odd or No Parity Options (for 8-bit data)
• One or Two Stop bits
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
• Hardware Flow Control Option with UxCTS and
UxRTS Pins
to be
a
comprehensive reference
• Fully Integrated Baud Rate Generator with
16-Bit Prescaler
source. To complement the information
in this data sheet, refer to “Universal
Asynchronous Receiver Transmitter
(UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual”, which
is available from the Microchip website
(www.microchip.com).
• Baud Rates Ranging from 4.375 Mbps to 67 bps in
16x mode at 70 MIPS
• Baud Rates Ranging from 17.5 Mbps to 267 bps in
4x mode at 70 MIPS
• 4-Deep First-In First-Out (FIFO) Transmit Data
Buffer
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• 4-Deep FIFO Receive Data Buffer
• Parity, Framing and Buffer Overrun Error Detection
• Support for 9-Bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive Interrupts
• A Separate Interrupt for all UARTx Error Conditions
• Loopback mode for Diagnostic Support
• Support for Sync and Break Characters
• Support for Automatic Baud Rate Detection
• IrDA® Encoder and Decoder Logic
The dsPIC33EPXXXGS70X/80X family of devices
contains two UART modules.
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules avail-
able in the dsPIC33EPXXXGS70X/80X device family.
The UART is a full-duplex, asynchronous system that
can communicate with peripheral devices, such as
personal computers, LIN/J2602, RS-232 and RS-485
interfaces. The module also supports a hardware flow
control option with the UxCTS and UxRTS pins, and
also includes an IrDA® encoder and decoder.
• 16x Baud Clock Output for IrDA Support
A simplified block diagram of the UARTx module is
shown in Figure 20-1. The UARTx module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 20-1:
UARTx SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
®
IrDA
Hardware Flow Control
UARTx Receiver
UxRTS/BCLKx
UxCTS
UxRX
UARTx Transmitter
UxTX
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20.1 UART Helpful Tips
20.2 UART Resources
1. In multi-node, direct connect UART networks,
UART receive inputs react to the complemen-
tary logic level defined by the URXINV bit
(UxMODE<4>), which defines the Idle state, the
default of which is logic high (i.e., URXINV = 0).
Because remote devices do not initialize at the
same time, it is likely that one of the devices,
because the RX line is floating, will trigger a Start
bit detection and will cause the first byte received,
after the device has been initialized, to be invalid.
To avoid this situation, the user should use a pull-
up or pull-down resistor on the RX pin depending
on the value of the URXINV bit.
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
20.2.1
KEY RESOURCES
• “Universal Asynchronous Receiver
Transmitter (UART)” (DS70000582) in the
“dsPIC33/PIC24 Family Reference Manual”
• Code Samples
• Application Notes
• Software Libraries
• Webinars
a) If URXINV = 0, use a pull-up resistor on the
UxRX pin.
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
b) If URXINV = 1, use a pull-down resistor on
the UxRX pin.
• Development Tools
2. The first character received on a wake-up from
Sleep mode, caused by activity on the UxRX pin
of the UARTx module, will be invalid. In Sleep
mode, peripheral clocks are disabled. By the
time the oscillator system has restarted and
stabilized from Sleep mode, the baud rate bit
sampling clock, relative to the incoming UxRX
bit timing, is no longer synchronized, resulting in
the first character being invalid; this is to be
expected.
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20.3 UART Control Registers
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
bit 15
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
UEN1
R/W-0
UEN0
RTSMD
bit 8
HC/R/W-0
WAKE
R/W-0
HC/R/W-0
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL1
PDSEL0
STSEL
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption is
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: UARTx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA encoder and decoder are enabled
0= IrDA encoder and decoder are disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin is in Simplex mode
0= UxRTS pin is in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
bit 9-8
UEN<1:0>: UARTx Pin Enable bits
11= UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin is controlled by PORT latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by PORT latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins are controlled by
PORT latches
bit 7
bit 6
WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit
1= UARTx continues to sample the UxRX pin, interrupt is generated on the falling edge; bit is cleared
in hardware on the following rising edge
0= No wake-up is enabled
LPBACK: UARTx Loopback Mode Select bit
1= Enables Loopback mode
0= Loopback mode is disabled
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the
“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5
ABAUD: Auto-Baud Enable bit
1= Enables baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0= Baud rate measurement is disabled or completed
bit 4
URXINV: UARTx Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the
“dsPIC33/PIC24 Family Reference Manual” for information on enabling the UARTx module for receive or
transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
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REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
UTXISEL1
bit 15
R/W-0
R/W-0
U-0
—
HC/R/W-0
UTXBRK
R/W-0
UTXEN(1)
R-0
R-1
UTXINV
UTXISEL0
UTXBF
TRMT
bit 8
R/W-0
URXISEL1
bit 7
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL0
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 0
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
HC = Hardware Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
bit 15,13
UTXISEL<1:0>: UARTx Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register (TSR), and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations
are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least
one character open in the transmit buffer)
bit 14
UTXINV: UARTx Transmit Polarity Inversion bit
If IREN = 0:
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
If IREN = 1:
1= IrDA® encoded, UxTX Idle state is ‘1’
0= IrDA encoded, UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: UARTx Transmit Break bit
1= Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission is disabled or completed
bit 10
UTXEN: UARTx Transmit Enable bit(1)
1= Transmit is enabled, UxTX pin is controlled by UARTx
0= Transmit is disabled, any pending transmission is aborted and buffer is reset; UxTX pin is controlled
by the PORT
bit 9
UTXBF: UARTx Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: UARTx Receive Interrupt Mode Selection bits
11= Interrupt is set on UxRSR transfer, making the receive buffer full (i.e., has four data characters)
10= Interrupt is set on UxRSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)
0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer; receive buffer has one or more characters
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.
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REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect
0= Address Detect mode is disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive FIFO)
0= Framing error has not been detected
OERR: Receive Buffer Overrun Error Status bit (clear/read-only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed; clearing a previously set OERR bit (1 0transition) resets the
receiver buffer and the UxRSR to the empty state
bit 0
URXDA: UARTx Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/
PIC24 Family Reference Manual” for information on enabling the UARTx module for transmit operation.
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The Configurable Logic Cell (CLC) module allows the
21.0 CONFIGURABLE LOGIC CELL
(CLC)
user to specify combinations of signals as inputs to a
logic function and to use the logic output to control
other peripherals or I/O pins. This provides greater flex-
ibility and potential in embedded designs, since the
CLC module can operate outside the limitations of
software execution and supports a vast amount of
output designs.
Note:
This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Configurable Logic Cell (CLC)”
(DS70005298) in the “dsPIC33/PIC24
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
There are four input gates to the selected logic func-
tion. These four input gates select from a pool of up to
32 signals that are selected using four data source
selection multiplexers. Figure 21-1 shows an overview
of the module. Figure 21-3 shows the details of the data
source multiplexers and logic input gate connections.
FIGURE 21-1:
CLCx MODULE
DS1<2:0>
DS2<2:0>
DS3<2:0>
G1POL
G2POL
G3POL
DS4<2:0> G4POL
D
Q
LCOUT
FCY
CLK
MODE<2:0>
LCOE
LCEN
CLC
Inputs
(32)
Gate 1
TRISx Control
CLCx
Input
Data
Selection
Gates
CLCx
Output
Gate 2
Gate 3
Gate 4
Logic
Logic
Output
Function
LCPOL
Interrupt
det
See Figure 21-2
Set
CLCxIF
See Figure 21-3
INTP
INTN
Interrupt
det
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FIGURE 21-2:
CLCx LOGIC FUNCTION COMBINATORIAL OPTIONS
AND – OR
OR – XOR
Gate 1
Gate 2
Gate 3
Gate 4
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
Logic Output
MODE<2:0> = 000
MODE<2:0> = 001
4-Input AND
S-R Latch
Gate 1
Gate 1
Gate 2
Gate 3
Gate 4
Logic Output
S
R
Q
Gate 2
Gate 3
Gate 4
Logic Output
MODE<2:0> = 011
MODE<2:0> = 010
1-Input D Flip-Flop with S and R
2-Input D Flip-Flop with R
Gate 4
Gate 4
Gate 2
D
Q
Logic Output
S
R
Logic Output
Gate 2
Gate 1
Gate 3
D
Q
Gate 1
Gate 3
R
MODE<2:0> = 101
MODE<2:0> = 100
J-K Flip-Flop with R
1-Input Transparent Latch with S and R
Gate 4
Gate 2
Gate 1
Gate 4
Gate 3
J
Q
Logic Output
S
Gate 2
Gate 1
Gate 3
D
Q
Logic Output
K
R
LE
R
MODE<2:0> = 110
MODE<2:0> = 111
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FIGURE 21-3:
CLCx INPUT SOURCE SELECTION DIAGRAM
Data Selection
000
Input 0
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
Data Gate 1
Data 1 Non-Inverted
G1D1T
G1D1N
G1D2T
Data 1
Inverted
111
000
DS1x (CLCxSEL<2:0>)
G1D2N
G1D3T
G1D3N
G1D4T
Gate 1
Input 8
Input 9
G1POL
(CLCxCONH<0>)
Input 10
Input 11
Input 12
Input 13
Input 14
Input 15
Data 2 Non-Inverted
Data 2
Inverted
111
000
G1D4N
DS2x (CLCxSEL<6:4>)
Input 16
Input 17
Input 18
Input 19
Input 20
Input 21
Input 22
Input 23
Data Gate 2
Gate 2
Data 3 Non-Inverted
(Same as Data Gate 1)
Data Gate 3
Data 3
Inverted
111
000
Gate 3
Gate 4
DS3x (CLCxSEL<10:8>)
(Same as Data Gate 1)
Data Gate 4
Input 24
Input 25
Input 26
Input 27
Input 28
Input 29
Input 30
Input 31
(Same as Data Gate 1)
Data 4 Non-Inverted
Data 4
Inverted
111
DS4x (CLCxSEL<14:12>)
Note: All controls are undefined at power-up.
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
The CLCx Input MUX Select register (CLCxSEL)
21.1 Control Registers
allows the user to select up to four data input sources
using the four data input selection multiplexers. Each
multiplexer has a list of eight data sources available.
The CLCx module is controlled by the following registers:
• CLCxCONL
• CLCxCONH
• CLCxSEL
The CLCx Gate Logic Input Select registers
(CLCxGLSL and CLCxGLSH) allow the user to select
which outputs from each of the selection MUXes are
used as inputs to the input gates of the logic cell. Each
data source MUX outputs both a true and a negated
version of its output. All of these eight signals are
enabled, ORed together by the logic cell input gates.
• CLCxGLSL
• CLCxGLSH
The CLCx Control registers (CLCxCONL and
CLCxCONH) are used to enable the module and inter-
rupts, control the output enable bit, select output polarity
and select the logic function. The CLCx Control registers
also allow the user to control the logic polarity of not only
the cell output, but also some intermediate variables.
REGISTER 21-1: CLCxCONL: CLCx CONTROL REGISTER (LOW)
R/W-0
LCEN
U-0
—
U-0
—
U-0
—
R/W-0
INTP
R/W-0
INTN
U-0
—
U-0
—
bit 15
bit 8
R-0
R-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
LCOE
LCOUT
LCPOL
MODE2
MODE1
MODE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
LCEN: CLCx Enable bit
1= CLCx is enabled and mixing input signals
0= CLCx is disabled and has logic zero outputs
bit 14-12
bit 11
Unimplemented: Read as ‘0’
INTP: CLCx Positive Edge Interrupt Enable bit
1= Interrupt will be generated when a rising edge occurs on LCOUT
0= Interrupt will not be generated
bit 10
INTN: CLCx Negative Edge Interrupt Enable bit
1= Interrupt will be generated when a falling edge occurs on LCOUT
0= Interrupt will not be generated
bit 9-8
bit 7
Unimplemented: Read as ‘0’
LCOE: CLCx Port Enable bit
1= CLCx port pin output is enabled
0= CLCx port pin output is disabled
bit 6
LCOUT: CLCx Data Output Status bit
1= CLCx output high
0= CLCx output low
bit 5
LCPOL: CLCx Output Polarity Control bit
1= The output of the module is inverted
0= The output of the module is not inverted
bit 4-3
Unimplemented: Read as ‘0’
DS70005258C-page 266
2016-2018 Microchip Technology Inc.
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REGISTER 21-1: CLCxCONL: CLCx CONTROL REGISTER (LOW) (CONTINUED)
bit 2-0
MODE<2:0>: CLCx Mode bits
111= Single Input Transparent Latch with S and R
110= JK Flip-Flop with R
101= Two-Input D Flip-Flop with R
100= Single Input D Flip-Flop with S and R
011= SR Latch
010= Four-Input AND
001= Four-Input OR-XOR
000= Four-Input AND-OR
REGISTER 21-2: CLCxCONH: CLCx CONTROL REGISTER (HIGH)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
G4POL
G3POL
G2POL
G1POL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
G4POL: Gate 4 Polarity Control bit
1= Channel 4 logic output is inverted when applied to the logic cell
0= Channel 4 logic output is not inverted
bit 2
bit 1
bit 0
G3POL: Gate 3 Polarity Control bit
1= Channel 3 logic output is inverted when applied to the logic cell
0= Channel 3 logic output is not inverted
G2POL: Gate 2 Polarity Control bit
1= Channel 2 logic output is inverted when applied to the logic cell
0= Channel 2 logic output is not inverted
G1POL: Gate 1 Polarity Control bit
1= Channel 1 logic output is inverted when applied to the logic cell
0= Channel 1 logic output is not inverted
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REGISTER 21-3: CLCxSEL: CLCx INPUT MUX SELECT REGISTER
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
DS4<2:0>
DS3<2:0>
bit 15
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
DS2<2:0>
DS1<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
DS4<2:0>: Data Selection MUX 4 Signal Selection bits
See Table 21-1 for input selections.
bit 11
Unimplemented: Read as ‘0’
bit 10-8
DS3<2:0>: Data Selection MUX 3 Signal Selection bits
See Table 21-1 for input selections.
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DS2<2:0>: Data Selection MUX 2 Signal Selection bits
See Table 21-1 for input selections.
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DS1<2:0>: Data Selection MUX 1 Signal Selection bits
See Table 21-1 for input selections.
DS70005258C-page 268
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 21-1: CLC1 MULTIPLEXER INPUT SOURCES
DSx<2:0>
Signal Source
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
CLCINA
System Clock
Timer1 Match
PWM1H
PWM5L
High-Speed PWM Clock
Timer2 Match
Timer3 Match
CLCINB
CLC2 Out
CMP1 Out
UART1 TX Out
ADC End-of-Conversion
DMA Channel 0 Interrupt
PWM1L
PWM5H
CLCINA
CLC1 Out
CMP2 Out
SPI1 SDO Out
UART1 RX
PWM2H
PWM6L
OCMP2 Sync Output
CLCINB
CLC2 Out
CMP3 Out
SDI1
PTGO26
ECAN1
PWM2L
PWM6H
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TABLE 21-2: CLC2 MULTIPLEXER INPUT SOURCES
DSx<2:0>
000
Signal Source
CLCINA
System Clock
Timer1 Match
PWM3H
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
PWM7L
High-Speed PWM Clock
Timer2 Match
Timer3 Match
CLCINB
CLC1 Out
CMP1 Out
UART2 TX Out
ADC End-of-Conversion
DMA Channel 0 Interrupt
PWM3L
PWM7H
CLCINA
CLC2 Out
CMP2 Out
SPI2 SDO Out
UART2 RX
PWM4H
PWM8L
OCMP2 Sync Output
CLCINB
CLC1 Out
CMP3 Out
SDI2
PTGO27
ECAN1
PWM4L
PWM8H
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 21-3: CLC3 MULTIPLEXER INPUT SOURCES
DSx<2:0>
Signal Source
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
CLCINA
System Clock
Timer1 Match
PWM5H
REFO1 Clock Output
High-Speed PWM Clock
Timer2 Match
PWM3L
CLCINB
CLC4 Out
CMP1 Out
PWM5L
ADC End-of-Conversion
PWM3H
ICAP1 Sync Output
ICAP2 Sync Output
CLCINA
CLC3 Out
CMP2 Out
PWM6H
UART1 RX
DMA Channel 1 Interrupt
OCMP1 Sync Output
PWM4L
CLCINB
CLC4 Out
CMP3 Out
PWM6L
PTGO28
PWM4H
PC_PWM
OCMP3 Sync Output
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TABLE 21-4: CLC4 MULTIPLEXER INPUT SOURCES
DSx<2:0>
000
Signal Source
CLCINA
PWM7H
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
Timer1 Match
INTOSC/LPRC Clock
REFO1 Clock Output
High-Speed PWM Clock
Timer2 Match
PWM1L
CLCINB
CLC3 Out
CMP1 Out
PWM7L
ADC End-of-Conversion
PWM1H
ICAP1 Sync Output
ICAP2 Sync Output
CLCINA
CLC4 Out
CMP2 Out
PWM8H
UART2 RX
DMA Channel 1 Interrupt
OCMP1 Sync Output
PWM2L
CLCINB
CLC3 Out
CMP3 Out
PWM8L
PTGO29
PWM2H
PWM Sync Output
OCMP3 Sync Output
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dsPIC33EPXXXGS70X/80X FAMILY
REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G2D4T
G2D4N
G2D3T
G2D3N
G2D2T
G2D2N
G2D1T
G2D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G1D4T
G1D4N
G1D3T
G1D3N
G1D2T
G1D2N
G1D1T
G1D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
G2D4T: Gate 2 Data Source 4 True Enable bit
1= Data Source 4 non-inverted signal is enabled for Gate 2
0= Data Source 4 non-inverted signal is disabled for Gate 2
G2D4N: Gate 2 Data Source 4 Negated Enable bit
1= Data Source 4 inverted signal is enabled for Gate 2
0= Data Source 4 inverted signal is disabled for Gate 2
G2D3T: Gate 2 Data Source 3 True Enable bit
1= Data Source 3 non-inverted signal is enabled for Gate 2
0= Data Source 3 non-inverted signal is disabled for Gate 2
G2D3N: Gate 2 Data Source 3 Negated Enable bit
1= Data Source 3 inverted signal is enabled for Gate 2
0= Data Source 3 inverted signal is disabled for Gate 2
G2D2T: Gate 2 Data Source 2 True Enable bit
1= Data Source 2 non-inverted signal is enabled for Gate 2
0= Data Source 2 non-inverted signal is disabled for Gate 2
G2D2N: Gate 2 Data Source 2 Negated Enable bit
1= Data Source 2 inverted signal is enabled for Gate 2
0= Data Source 2 inverted signal is disabled for Gate 2
G2D1T: Gate 2 Data Source 1 True Enable bit
1= Data Source 1 non-inverted signal is enabled for Gate 2
0= Data Source 1 non-inverted signal is disabled for Gate 2
bit 8
G2D1N: Gate 2 Data Source 1 Negated Enable bit
1= Data Source 1 inverted signal is enabled for Gate 2
0= Data Source 1 inverted signal is disabled for Gate 2
bit 7
G1D4T: Gate 1 Data Source 4 True Enable bit
1= Data Source 4 non-inverted signal is enabled for Gate 1
0= Data Source 4 non-inverted signal is disabled for Gate 1
bit 6
G1D4N: Gate 1 Data Source 4 Negated Enable bit
1= Data Source 4 inverted signal is enabled for Gate 1
0= Data Source 4 inverted signal is disabled for Gate 1
bit 5
G1D3T: Gate 1 Data Source 3 True Enable bit
1= Data Source 3 non-inverted signal is enabled for Gate 1
0= Data Source 3 non-inverted signal is disabled for Gate 1
bit 4
G1D3N: Gate 1 Data Source 3 Negated Enable bit
1= Data Source 3 inverted signal is enabled for Gate 1
0= Data Source 3 inverted signal is disabled for Gate 1
2016-2018 Microchip Technology Inc.
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REGISTER 21-4: CLCxGLSL: CLCx GATE LOGIC INPUT SELECT LOW REGISTER (CONTINUED)
bit 3
bit 2
bit 1
bit 0
G1D2T: Gate 1 Data Source 2 True Enable bit
1= Data Source 2 non-inverted signal is enabled for Gate 1
0= Data Source 2 non-inverted signal is disabled for Gate 1
G1D2N: Gate 1 Data Source 2 Negated Enable bit
1= Data Source 2 inverted signal is enabled for Gate 1
0= Data Source 2 inverted signal is disabled for Gate 1
G1D1T: Gate 1 Data Source 1 True Enable bit
1= Data Source 1 non-inverted signal is enabled for Gate 1
0= Data Source 1 non-inverted signal is disabled for Gate 1
G1D1N: Gate 1 Data Source 1 Negated Enable bit
1= Data Source 1 inverted signal is enabled for Gate 1
0= Data Source 1 inverted signal is disabled for Gate 1
DS70005258C-page 274
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REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G4D4T
G4D4N
G4D3T
G4D3N
G4D2T
G4D2N
G4D1T
G4D1N
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
G3D4T
G3D4N
G3D3T
G3D3N
G3D2T
G3D2N
G3D1T
G3D1N
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
G4D4T: Gate 4 Data Source 4 True Enable bit
1= Data Source 4 non-inverted signal is enabled for Gate 4
0= Data Source 4 non-inverted signal is disabled for Gate 4
G4D4N: Gate 4 Data Source 4 Negated Enable bit
1= Data Source 4 inverted signal is enabled for Gate 4
0= Data Source 4 inverted signal is disabled for Gate 4
G4D3T: Gate 4 Data Source 3 True Enable bit
1= Data Source 3 non-inverted signal is enabled for Gate 4
0= Data Source 3 non-inverted signal is disabled for Gate 4
G4D3N: Gate 4 Data Source 3 Negated Enable bit
1= Data Source 3 inverted signal is enabled for Gate 4
0= Data Source 3 inverted signal is disabled for Gate 4
G4D2T: Gate 4 Data Source 2 True Enable bit
1= Data Source 2 non-inverted signal is enabled for Gate 4
0= Data Source 2 non-inverted signal is disabled for Gate 4
G4D2N: Gate 4 Data Source 2 Negated Enable bit
1= Data Source 2 inverted signal is enabled for Gate 4
0= Data Source 2 inverted signal is disabled for Gate 4
G4D1T: Gate 4 Data Source 1 True Enable bit
1= Data Source 1 non-inverted signal is enabled for Gate 4
0= Data Source 1 non-inverted signal is disabled for Gate 4
bit 8
G4D1N: Gate 4 Data Source 1 Negated Enable bit
1= Data Source 1 inverted signal is enabled for Gate 4
0= Data Source 1 inverted signal is disabled for Gate 4
bit 7
G3D4T: Gate 3 Data Source 4 True Enable bit
1= Data Source 4 non-inverted signal is enabled for Gate 3
0= Data Source 4 non-inverted signal is disabled for Gate 3
bit 6
G3D4N: Gate 3 Data Source 4 Negated Enable bit
1= Data Source 4 inverted signal is enabled for Gate 3
0= Data Source 4 inverted signal is disabled for Gate 3
bit 5
G3D3T: Gate 3 Data Source 3 True Enable bit
1= Data Source 3 non-inverted signal is enabled for Gate 3
0= Data Source 3 non-inverted signal is disabled for Gate 3
bit 4
G3D3N: Gate 3 Data Source 3 Negated Enable bit
1= Data Source 3 inverted signal is enabled for Gate 3
0= Data Source 3 inverted signal is disabled for Gate 3
2016-2018 Microchip Technology Inc.
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REGISTER 21-5: CLCxGLSH: CLCx GATE LOGIC INPUT SELECT HIGH REGISTER (CONTINUED)
bit 3
bit 2
bit 1
bit 0
G3D2T: Gate 3 Data Source 2 True Enable bit
1= Data Source 2 non-inverted signal is enabled for Gate 3
0= Data Source 2 non-inverted signal is disabled for Gate 3
G3D2N: Gate 3 Data Source 2 Negated Enable bit
1= Data Source 2 inverted signal is enabled for Gate 3
0= Data Source 2 inverted signal is disabled for Gate 3
G3D1T: Gate 3 Data Source 1 True Enable bit
1= Data Source 1 non-inverted signal is enabled for Gate 3
0= Data Source 1 non-inverted signal is disabled for Gate 3
G3D1N: Gate 3 Data Source 1 Negated Enable bit
1= Data Source 1 inverted signal is enabled for Gate 3
0= Data Source 1 inverted signal is disabled for Gate 3
DS70005258C-page 276
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
• Simultaneous Sampling of up to Five Analog Inputs
22.0 HIGH-SPEED, 12-BIT
• Channel Scan Capability
ANALOG-TO-DIGITAL
CONVERTER (ADC)
• Multiple Conversion Trigger Options for each
Core, including:
Note 1: This data sheet summarizes the features of
the dsPIC33EPXXXGS70X/80X family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“12-Bit High-Speed, Multiple SARs A/D
Converter (ADC)” (DS70005213) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
- PWM1 through PWM6 (primary and
secondary triggers, and current-limit event
trigger)
- PWM Special Event Trigger
- Timer1/Timer2 period match
- Output Compare 1 and event trigger
- External pin trigger event (ADTRG31)
- Software trigger
• Two Integrated Digital Comparators with
Dedicated Interrupts:
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
- Multiple comparison options
- Assignable to specific analog inputs
• Two Oversampling Filters with Dedicated
Interrupts:
- Provide increased resolution
- Assignable to a specific analog input
dsPIC33EPXXXGS70X/80X devices have a high-speed,
12-bit Analog-to-Digital Converter (ADC) that features
a low conversion latency, high resolution and over-
sampling capabilities to improve performance in
AC/DC, DC/DC power converters.
The module consists of five independent SAR ADC
cores. Simplified block diagrams of the multiple SARs
12-bit ADC are shown in Figure 22-1, Figure 22-2 and
Figure 22-3.
The analog inputs (channels) are connected through
multiplexers and switches to the Sample-and-Hold
(S&H) circuit of each ADC core. The core uses the
channel information (the output format, the Measure-
ment mode and the input number) to process the analog
sample. When conversion is complete, the result is
stored in the result buffer for the specific analog input,
and passed to the digital filter and digital comparator if
they were configured to use data from this particular
channel.
22.1 Features Overview
The high-speed, 12-bit multiple SARs Analog-to-Digital
Converter (ADC) includes the following features:
• Five ADC Cores: Four Dedicated Cores and
One Shared (common) Core
• User-Configurable Resolution of up to 12 Bits for
each Core
• Up to 3.25 Msps Conversion Rate per Channel at
12-Bit Resolution
The ADC module can sample up to five inputs at a time
(four inputs from the dedicated SAR cores and one
from the shared SAR core). If multiple ADC inputs
request conversion on the shared core, the module will
convert them in a sequential manner, starting with the
lowest order input.
• Low Latency Conversion
• Up to 22 Analog Input Channels, with a Separate
16-Bit Conversion Result Register for each Input
• Conversion Result can be Formatted as Unsigned
or Signed Data, on a per Channel Basis, for All
Channels
The ADC provides each analog input the ability to
specify its own trigger source. This capability allows the
ADC to sample and convert analog inputs that are
associated with PWM generators operating on
independent time bases.
• Single-Ended and Pseudodifferential
Conversions are available on All ADC Cores
2016-2018 Microchip Technology Inc.
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FIGURE 22-1:
ADC MODULE BLOCK DIAGRAM
AVDD AVSS
Voltage Reference
(REFSEL<2:0>)
AN0
AN7
Reference
Output Data
Clock
Dedicated
ADC Core 0
(2)
(1)
Digital Comparator 0
Digital Comparator 1
PGA1
AN0ALT
ADCMP0 Interrupt
ADCMP1 Interrupt
AN1
Reference
Output Data
Clock
AN18
Dedicated
ADC Core 1
(2)
(1)
PGA2
AN1ALT
Digital Filter 0
Digital Filter 1
ADFL0DAT
ADFLTR0 Interrupt
ADFLTR1 Interrupt
Reference
Output Data
Clock
ADFL1DAT
AN2
Dedicated
ADC Core 2
(2)
V
BG Reference(1)
AN11
Reference
Output Data
Clock
ADCBUF0
ADCBUF1
AN3
ADCAN0 Interrupt
ADCAN1 Interrupt
Dedicated
ADC Core 3
(2)
AN15
ADCBUF21
ADCAN21 Interrupt
Reference
Output Data
Clock
AN4
Shared
ADC Core
AN21
Divider
(CLKDIV<5:0>)
Clock Selection
(CLKSEL<1:0>)
Instruction FRC
Clock
AUX
Clock
Note 1: PGA1, PGA2 and the Band Gap Reference (VBG) are internal analog inputs and are not available on device pins.
2: If the dedicated core uses an alternate channel, then shared core function cannot be used.
DS70005258C-page 278
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 22-2:
DEDICATED ADC CORES 0 TO 3 BLOCK DIAGRAM
Positive Input
Positive Input
Selection
+
–
PGAx
Reference
(CxCHS<1:0>)
Alternate
Positive Input
12-Bit SAR
ADC
Sample-
and-Hold
Output Data
Negative Input
Selection
Negative Input
(1)
(DIFFx)
ADC Core
Clock Divider
(ADCS<6:0> bits)
Clock
Trigger Stops
Sampling
AVSS
Note 1: The DIFFx bit for the corresponding positive input channel must be set in order to use the negative differential input.
FIGURE 22-3:
SHARED ADC CORE BLOCK DIAGRAM
AN4
+
Reference
12-Bit
SAR
ADC
AN21
Output Data
Shared
Sample-
Analog Channel Number
from Current Trigger
and-Hold
ADC Core
Clock Divider
(SHRADC<6:0> bits)
Clock
(1)
Negative Input
–
AN9
Selection
(1)
(DIFFx)
SHRSAMC<9:0>
Sampling Time
AVSS
Note 1: Differential-mode conversion is not available for the shared ADC core in dsPIC33EPXXGS70X/80X
devices. For all other devices, the DIFFx bit for the corresponding positive input channel must be set to use
AN9 as the negative differential input.
2016-2018 Microchip Technology Inc.
DS70005258C-page 279
dsPIC33EPXXXGS70X/80X FAMILY
22.2.1
KEY RESOURCES
22.2 Analog-to-Digital Converter
Resources
• “12-Bit High-Speed, Multiple SARs A/D
Converter (ADC)” (DS70005213) in the
“dsPIC33/PIC24 Family Reference Manual”
Many useful resources are provided on the main
product page of the Microchip website for the devices
listed in this data sheet. This product page contains the
latest updates and additional information.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
REGISTER 22-1: ADCON1L: ADC CONTROL REGISTER 1 LOW
R/W-0
ADON(1)
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ADSIDL
bit 15
bit 8
bit 0
R/W-0
NRE(2)
r-0
—
r-0
—
r-0
—
r-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADON: ADC Enable bit(1)
1= ADC module is enabled
0= ADC module is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: ADC Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
NRE: Noise Reduction Enable bit(2)
1= Holds conversion process for one TADCORE when another core completes conversion to reduce
noise between cores
0= Noise reduction feature is disabled
bit 6-3
bit 2-0
Reserved: Maintain as ‘0’
Unimplemented: Read as ‘0’
Note 1: Set the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when
ADON = 1will result in unpredictable behavior.
2: If the NRE bit in the ADCON1L register is set, the end of conversion time is adjusted to reduce the noise
between ADC cores. Depending on the number of cores converting and the priority of the input, a few
additional TADs may be inserted, making the conversion time slightly less deterministic.
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REGISTER 22-2: ADCON1H: ADC CONTROL REGISTER 1 HIGH
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
bit 15
bit 8
bit 0
R/W-0
FORM
R/W-1
R/W-1
r-0
—
r-0
—
r-0
—
r-0
—
r-0
—
SHRRES1
SHRRES0
bit 7
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Reserved: Maintain as ‘0’
FORM: Fractional Data Output Format bit
1= Fractional
0= Integer
bit 6-5
bit 4-0
SHRRES<1:0>: Shared ADC Core Resolution Selection bits
11= 12-bit resolution
10= 10-bit resolution
01= 8-bit resolution
00= 6-bit resolution
Reserved: Maintain as ‘0’
2016-2018 Microchip Technology Inc.
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REGISTER 22-3: ADCON2L: ADC CONTROL REGISTER 2 LOW
R/W-0
R/W-0
r-0
—
R/W-0
EIEN
r-0
—
R/W-0
R/W-0
R/W-0
REFCIE
REFERCIE
SHREISEL2(1) SHREISEL1(1) SHREISEL0(1)
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SHRADCS<6:0>
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
REFCIE: Band Gap and Reference Voltage Ready Common Interrupt Enable bit
1= Common interrupt will be generated when the band gap will become ready
0= Common interrupt is disabled for the band gap ready event
REFERCIE: Band Gap or Reference Voltage Error Common Interrupt Enable bit
1= Common interrupt will be generated when a band gap or reference voltage error is detected
0= Common interrupt is disabled for the band gap and reference voltage error event
bit 13
bit 12
Reserved: Maintain as ‘0’
EIEN: Early Interrupts Enable bit
1= The early interrupt feature is enabled for the input channel interrupts (when the EISTATx flag is set)
0= The individual interrupts are generated when conversion is done (when the ANxRDY flag is set)
bit 11
Reserved: Maintain as ‘0’
bit 10-8
SHREISEL<2:0>: Shared Core Early Interrupt Time Selection bits(1)
111= Early interrupt is set and interrupt is generated eight TADCORE clocks prior to when the data is ready
110= Early interrupt is set and interrupt is generated seven TADCORE clocks prior to when the data is ready
101= Early interrupt is set and interrupt is generated six TADCORE clocks prior to when the data is ready
100= Early interrupt is set and interrupt is generated five TADCORE clocks prior to when the data is ready
011= Early interrupt is set and interrupt is generated four TADCORE clocks prior to when the data is ready
010= Early interrupt is set and interrupt is generated three TADCORE clocks prior to when the data is ready
001= Early interrupt is set and interrupt is generated two TADCORE clocks prior to when the data is ready
000= Early interrupt is set and interrupt is generated one TADCORE clock prior to when the data is ready
bit 7
Unimplemented: Read as ‘0’
bit 6-0
SHRADCS<6:0>: Shared ADC Core Input Clock Divider bits
These bits determine the number of TCORESRC (Source Clock Periods) for one shared TADCORE (Core
Clock Period).
1111111= 254 Source Clock Periods
•
•
•
0000011= 6 Source Clock Periods
0000010= 4 Source Clock Periods
0000001= 2 Source Clock Periods
0000000= 2 Source Clock Periods
Note 1: For the 6-bit shared ADC core resolution (SHRRES<1:0> = 00), the SHREISEL<2:0> settings,
from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution
(SHRRES<1:0> = 01), the SHREISEL<2:0> settings, ‘110’ and ‘111’, are not valid and should not be used.
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REGISTER 22-4: ADCON2H: ADC CONTROL REGISTER 2 HIGH
HSC/R-0
REFRDY
HSC/R-0
REFERR
r-0
—
r-0
—
r-0
—
r-0
—
R/W-0
R/W-0
SHRSAMC<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SHRSAMC<7:0>
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
HSC = Hardware Settable/Clearable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
bit 14
REFRDY: Band Gap and Reference Voltage Ready Flag bit
1= Band gap is ready
0= Band gap is not ready
REFERR: Band Gap or Reference Voltage Error Flag bit
1= Band gap was removed after the ADC module was enabled (ADON = 1)
0= No band gap error was detected
bit 13-10
bit 9-0
Reserved: Maintain as ‘0’
SHRSAMC<9:0>: Shared ADC Core Sample Time Selection bits
These bits specify the number of shared ADC Core Clock Periods (TADCORE) for the shared ADC core
sample time.
1111111111= 1025 TADCORE
•
•
•
0000000001= 3 TADCORE
0000000000= 2 TADCORE
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REGISTER 22-5: ADCON3L: ADC CONTROL REGISTER 3 LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
HSC/R-0
R/W-0
HSC/R-0
REFSEL2
REFSEL1
REFSEL0
SUSPEND
SUSPCIE
SUSPRDY
SHRSAMP
CNVRTCH
bit 15
bit 8
R/W-0
HSC/R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SWLCTRG
SWCTRG CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0
bit 0
bit 7
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
REFSEL<2:0>: ADC Reference Voltage Selection bits
Value
VREFH
VREFL
000
AVDD
AVSS
001-111= Unimplemented: Do not use
bit 12
bit 11
SUSPEND: All ADC Cores Triggers Disable bit
1= All new trigger events for all ADC cores are disabled
0= All ADC cores can be triggered
SUSPCIE: Suspend All ADC Cores Common Interrupt Enable bit
1= Common interrupt will be generated when ADC core triggers are suspended (SUSPEND bit = 1)
and all previous conversions are finished (SUSPRDY bit becomes set)
0= Common interrupt is not generated for suspend ADC cores event
bit 10
bit 9
SUSPRDY: All ADC Cores Suspended Flag bit
1= All ADC cores are suspended (SUSPEND bit = 1) and have no conversions in progress
0= ADC cores have previous conversions in progress
SHRSAMP: Shared ADC Core Sampling Direct Control bit
This bit should be used with the individual channel conversion trigger controlled by the CNVRTCH bit.
It connects an analog input, specified by the CNVCHSEL<5:0> bits, to the shared ADC core and allows
extending the sampling time. This bit is not controlled by hardware and must be cleared before the
conversion starts (setting CNVRTCH to ‘1’).
1= Shared ADC core samples an analog input specified by the CNVCHSEL<5:0> bits
0= Sampling is controlled by the shared ADC core hardware
bit 8
bit 7
bit 6
CNVRTCH: Software Individual Channel Conversion Trigger bit
1= Single trigger is generated for an analog input specified by the CNVCHSEL<5:0> bits; when the bit
is set, it is automatically cleared by hardware on the next instruction cycle
0= Next individual channel conversion trigger can be generated
SWLCTRG: Software Level-Sensitive Common Trigger bit
1= Triggers are continuously generated for all channels with the software, level-sensitive common
trigger selected as a source in the ADTRIGxL and ADTRIGxH registers
0= No software, level-sensitive common triggers are generated
SWCTRG: Software Common Trigger bit
1= Single trigger is generated for all channels with the software, common trigger selected as a source
in the ADTRIGxL and ADTRIGxH registers; when the bit is set, it is automatically cleared by
hardware on the next instruction cycle
0= Ready to generate the next software common trigger
bit 5-0
CNVCHSEL <5:0>: Channel Number Selection for Software Individual Channel Conversion Trigger bits
These bits define a channel to be converted when the CNVRTCH bit is set.
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REGISTER 22-6: ADCON3H: ADC CONTROL REGISTER 3 HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CLKSEL1
CLKSEL0
CLKDIV5
CLKDIV4
CLKDIV3
CLKDIV2
CLKDIV1
CLKDIV0
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
C3EN
R/W-0
C2EN
R/W-0
C1EN
R/W-0
C0EN
SHREN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
CLKSEL<1:0>: ADC Module Clock Source Selection bits
11= APLL
10= FRC
01= FOSC (System Clock x 2)
00= FSYS (System Clock)
bit 13-8
CLKDIV<5:0>: ADC Module Clock Source Divider bits
The divider forms a TCORESRC clock used by all ADC cores (shared and dedicated) from the TSRC ADC
module clock source selected by the CLKSEL<1:0> bits. Then, each ADC core individually divides the
TCORESRC clock to get a core-specific TADCORE clock using the ADCS<6:0> bits in the ADCORExH
register or the SHRADCS<6:0> bits in the ADCON2L register.
111111= 64 Source Clock Periods
•
•
•
000011= 4 Source Clock Periods
000010= 3 Source Clock Periods
000001= 2 Source Clock Periods
000000= 1 Source Clock Period
bit 7
SHREN: Shared ADC Core Enable bit
1= Shared ADC core is enabled
0= Shared ADC core is disabled
bit 6-4
bit 3
Unimplemented: Read as ‘0’
C3EN: Dedicated ADC Core 3 Enable bits
1= Dedicated ADC Core 3 is enabled
0= Dedicated ADC Core 3 is disabled
bit 2
bit 1
bit 0
C2EN: Dedicated ADC Core 2 Enable bits
1= Dedicated ADC Core 2 is enabled
0= Dedicated ADC Core 2 is disabled
C1EN: Dedicated ADC Core 1 Enable bits
1= Dedicated ADC Core 1 is enabled
0= Dedicated ADC Core 1 is disabled
C0EN: Dedicated ADC Core 0 Enable bits
1= Dedicated ADC Core 0 is enabled
0= Dedicated ADC Core 0 is disabled
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REGISTER 22-7: ADCON4L: ADC CONTROL REGISTER 4 LOW
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SAMC3EN
SAMC2EN
SAMC1EN
SAMC0EN
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-4
bit 3
Unimplemented: Read as ‘0’
SAMC3EN: Dedicated ADC Core 3 Conversion Delay Enable bit
1= After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC<9:0> bits in the ADCORE3L register
0= After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
bit 2
bit 1
bit 0
SAMC2EN: Dedicated ADC Core 2 Conversion Delay Enable bit
1= After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC<9:0> bits in the ADCORE2L register
0= After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
SAMC1EN: Dedicated ADC Core 1 Conversion Delay Enable bit
1= After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC<9:0> bits in the ADCORE1L register
0= After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
SAMC0EN: Dedicated ADC Core 0 Conversion Delay Enable bit
1= After trigger, the conversion will be delayed and the ADC core will continue sampling during the
time specified by the SAMC<9:0> bits in the ADCORE0L register
0= After trigger, the sampling will be stopped immediately and the conversion will be started on the
next core clock cycle
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REGISTER 22-8: ADCON4H: ADC CONTROL REGISTER 4 HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
C3CHS1
C3CHS0
C2CHS1
C2CHS0
C1CHS1
C1CHS0
C0CHS1
C0CHS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
C3CHS<1:0>: Dedicated ADC Core 3 Input Channel Selection bits
1x= Reserved
01= AN15 (differential negative input when DIFF3 (ADMOD0L<7>) = 1)
00= AN3
bit 5-4
bit 3-2
bit 1-0
C2CHS<1:0>: Dedicated ADC Core 2 Input Channel Selection bits
11= Reserved
10= VREF band gap
01= AN11 (differential negative input when DIFF2 (ADMOD0L<5>) = 1)
00= AN2
C1CHS<1:0>: Dedicated ADC Core 1 Input Channel Selection bits
11= AN1ALT
10= PGA2
01= AN18 (differential negative input when DIFF1 (ADMOD0L<3>) = 1)
00= AN1
C0CHS<1:0>: Dedicated ADC Core 0 Input Channel Selection bits
11= AN0ALT
10= PGA1
01= AN7 (differential negative input when DIFF0 (ADMOD0L<1>) = 1)
00= AN0
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REGISTER 22-9: ADCON5L: ADC CONTROL REGISTER 5 LOW
HSC/R-0
SHRRDY
U-0
—
U-0
—
U-0
—
HSC/R-0
C3RDY
HSC/R-0
C2RDY
HSC/R-0
C1RDY
HSC/R-0
C0RDY
bit 15
bit 8
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SHRPWR
C3PWR
C2PWR
C1PWR
C0PWR
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SHRRDY: Shared ADC Core Ready Flag bit
1= ADC core is powered and ready for operation
0= ADC core is not ready for operation
bit 14-12
bit 11
Unimplemented: Read as ‘0’
C3RDY: Dedicated ADC Core 3 Ready Flag bit
1= ADC core is powered and ready for operation
0= ADC core is not ready for operation
bit 10
bit 9
bit 8
bit 7
C2RDY: Dedicated ADC Core 2 Ready Flag bit
1= ADC core is powered and ready for operation
0= ADC core is not ready for operation
C1RDY: Dedicated ADC Core 1 Ready Flag bit
1= ADC core is powered and ready for operation
0= ADC core is not ready for operation
C0RDY: Dedicated ADC Core 0 Ready Flag bit
1= ADC core is powered and ready for operation
0= ADC core is not ready for operation
SHRPWR: Shared ADC Core x Power Enable bit
1= ADC Core x is powered
0= ADC Core x is off
bit 6-4
bit 3
Unimplemented: Read as ‘0’
C3PWR: Dedicated ADC Core 3 Power Enable bit
1= ADC core is powered
0= ADC core is off
bit 2
bit 1
bit 0
C2PWR: Dedicated ADC Core 2 Power Enable bit
1= ADC core is powered
0= ADC core is off
C1PWR: Dedicated ADC Core 1 Power Enable bit
1= ADC core is powered
0= ADC core is off
C0PWR: Dedicated ADC Core 0 Power Enable bit
1= ADC core is powered
0= ADC core is off
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REGISTER 22-10: ADCON5H: ADC CONTROL REGISTER 5 HIGH
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
WARMTIME<3:0>
bit 15
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
C3CIE
R/W-0
C2CIE
R/W-0
C1CIE
R/W-0
C0CIE
SHRCIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
WARMTIME<3:0>: ADC Dedicated Core x Power-up Delay bits
These bits determine the power-up delay in the number of the Core Source Clock Periods (TCORESRC)
for all ADC cores.
1111= 32768 Source Clock Periods
1110= 16384 Source Clock Periods
1101= 8192 Source Clock Periods
1100= 4096 Source Clock Periods
1011= 2048 Source Clock Periods
1010= 1024 Source Clock Periods
1001= 512 Source Clock Periods
1000= 256 Source Clock Periods
0111= 128 Source Clock Periods
0110= 64 Source Clock Periods
0101= 32 Source Clock Periods
0100= 16 Source Clock Periods
00xx= 16 Source Clock Periods
bit 7
SHRCIE: Shared ADC Core Ready Common Interrupt Enable bit
1= Common interrupt will be generated when ADC core is powered and ready for operation
0= Common interrupt is disabled for an ADC core ready event
bit 6-4
bit 3
Unimplemented: Read as ‘0’
C3CIE: Dedicated ADC Core 3 Ready Common Interrupt Enable bit
1= Common interrupt will be generated when ADC Core 3 is powered and ready for operation
0= Common interrupt is disabled for an ADC Core 3 ready event
bit 2
bit 1
bit 0
C2CIE: Dedicated ADC Core 2 Ready Common Interrupt Enable bit
1= Common interrupt will be generated when ADC Core 2 is powered and ready for operation
0= Common interrupt is disabled for an ADC Core 2 ready event
C1CIE: Dedicated ADC Core 1 Ready Common Interrupt Enable bit
1= Common interrupt will be generated when ADC Core 1 is powered and ready for operation
0= Common interrupt is disabled for an ADC Core 1 ready event
C0CIE: Dedicated ADC Core 0 Ready Common Interrupt Enable bit
1= Common interrupt will be generated when ADC Core 0 is powered and ready for operation
0= Common interrupt is disabled for an ADC Core 0 ready event
2016-2018 Microchip Technology Inc.
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REGISTER 22-11: ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW (x = 0 to 3)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
SAMC<9:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
SAMC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
SAMC<9:0>: Dedicated ADC Core x Conversion Delay Selection bits
These bits determine the time between the trigger event and the start of conversion in the number of
the Core Clock Periods (TADCORE). During this time, the ADC Core x still continues sampling. This
feature is enabled by the SAMCxEN bits in the ADCON4L register.
1111111111= 1025 TADCORE
•
•
•
0000000001= 3 TADCORE
0000000000= 2 TADCORE
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REGISTER 22-12: ADCORExH: DEDICATED ADC CORE x CONTROL REGISTER HIGH (x = 0 to 3)(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-1
RES1
R/W-1
RES0
EISEL2
EISEL1
EISEL0
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADCS<6:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-10
Unimplemented: Read as ‘0’
EISEL<2:0>: ADC Core x Early Interrupt Time Selection bits
111= Early interrupt is set and an interrupt is generated eight TADCORE clocks prior to when the data is ready
110= Early interrupt is set and an interrupt is generated seven TADCORE clocks prior to when the data is ready
101= Early interrupt is set and an interrupt is generated six TADCORE clocks prior to when the data is ready
100= Early interrupt is set and an interrupt is generated five TADCORE clocks prior to when the data is ready
011= Early interrupt is set and an interrupt is generated four TADCORE clocks prior to when the data is ready
010= Early interrupt is set and an interrupt is generated three TADCORE clocks prior to when the data is ready
001= Early interrupt is set and an interrupt is generated two TADCORE clocks prior to when the data is ready
000= Early interrupt is set and an interrupt is generated one TADCORE clock prior to when the data is ready
bit 9-8
RES<1:0>: ADC Core x Resolution Selection bits
11= 12-bit resolution
10= 10-bit resolution
01= 8-bit resolution
00= 6-bit resolution
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ADCS<6:0>: ADC Core x Input Clock Divider bits
These bits determine the number of Source Clock Periods (TCORESRC) for one Core Clock Period
(TADCORE).
1111111= 254 Source Clock Periods
•
•
•
0000011= 6 Source Clock Periods
0000010= 4 Source Clock Periods
0000001= 2 Source Clock Periods
0000000= 2 Source Clock Periods
Note 1: For the 6-bit ADC core resolution (RES<1:0> = 00), the EISEL<2:0> bits settings, from ‘100’ to ‘111’, are
not valid and should not be used. For the 8-bit ADC core resolution (RES<1:0> = 01), the EISEL<2:0> bits
settings, ‘110’ and ‘111’, are not valid and should not be used.
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REGISTER 22-13: ADLVLTRGL: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER LOW
R/W-0
bit 15
R/W-0
R/W-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
LVLEN<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LVLEN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
LVLEN<15:0>: Level Trigger for Corresponding Analog Input Enable bits
1= Input trigger is level-sensitive
0= Input trigger is edge-sensitive
REGISTER 22-14: ADLVLTRGH: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
LVLEN<21:16>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
LVLEN<21:16>: Level Trigger for Corresponding Analog Input Enable bits
1= Input trigger is level-sensitive
0= Input trigger is edge-sensitive
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REGISTER 22-15: ADEIEL: ADC EARLY INTERRUPT ENABLE REGISTER LOW
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
EIEN<15:8>
R/W-0
R/W-0
R/W-0
EIEN<7:0>
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EIEN<15:0>: Early Interrupt Enable for Corresponding Analog Inputs bits
1= Early interrupt is enabled for the channel
0= Early interrupt is disabled for the channel
REGISTER 22-16: ADEIEH: ADC EARLY INTERRUPT ENABLE REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EIEN<21:16>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
EIEN<21:16>: Early Interrupt Enable for Corresponding Analog Inputs bits
1= Early interrupt is enabled for the channel
0= Early interrupt is disabled for the channel
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REGISTER 22-17: ADEISTATL: ADC EARLY INTERRUPT STATUS REGISTER LOW
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
EISTAT<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
EISTAT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EISTAT<15:0>: Early Interrupt Status for Corresponding Analog Inputs bits
1= Early interrupt was generated
0= Early interrupt was not generated since the last ADCBUFx read
REGISTER 22-18: ADEISTATH: ADC EARLY INTERRUPT STATUS REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
EISTAT<21:16>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
EISTAT<21:16>: Early Interrupt Status for Corresponding Analog Inputs bits
1= Early interrupt was generated
0= Early interrupt was not generated since the last ADCBUFx read
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REGISTER 22-19: ADMOD0L: ADC INPUT MODE CONTROL REGISTER 0 LOW
R/W-0
DIFF7
R/W-0
SIGN7
R/W-0
DIFF6
R/W-0
SIGN6
R/W-0
DIFF5
R/W-0
SIGN5
R/W-0
DIFF4
R/W-0
SIGN4
bit 15
bit 8
R/W-0
DIFF3
R/W-0
SIGN3
R/W-0
DIFF2
R/W-0
SIGN2
R/W-0
DIFF1
R/W-0
SIGN1
R/W-0
DIFF0
R/W-0
SIGN0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1(odd) DIFF<7:0>: Differential-Mode for Corresponding Analog Inputs bits
1= Channel is differential
0= Channel is single-ended
bit 14-0 (even) SIGN<7:0>: Output Data Sign for Corresponding Analog Inputs bits
1= Channel output data is signed
0= Channel output data is unsigned
REGISTER 22-20: ADMOD0H: ADC INPUT MODE CONTROL REGISTER 0 HIGH
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF15
SIGN15
DIFF14
SIGN14
DIFF13
SIGN13
DIFF12
SIGN12
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF9
R/W-0
SIGN9
R/W-0
DIFF8
R/W-0
SIGN8
DIFF11
SIGN11
DIFF10
SIGN10
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1(odd) DIFF<15:8>: Differential-Mode for Corresponding Analog Inputs bits
1= Channel is differential
0= Channel is single-ended
bit 14-0 (even) SIGN<15:8>: Output Data Sign for Corresponding Analog Inputs bits
1= Channel output data is signed
0= Channel output data is unsigned
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REGISTER 22-21: ADMOD1L: ADC INPUT MODE CONTROL REGISTER 1 LOW
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
DIFF21
SIGN21
DIFF20
SIGN20
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIFF19
SIGN19
DIFF18
SIGN18
DIFF17
SIGN17
DIFF16
SIGN16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
Unimplemented: Read as ‘0’
bit 11-1(odd) DIFF<21:16>: Differential-Mode for Corresponding Analog Inputs bits
1= Channel is differential
0= Channel is single-ended
bit 10-0 (even) SIGN<21:16>: Output Data Sign for Corresponding Analog Inputs bits
1= Channel output data is signed
0= Channel output data is unsigned
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REGISTER 22-22: ADIEL: ADC INTERRUPT ENABLE REGISTER LOW
R/W-0
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
IE<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
IE<15:0>: Common Interrupt Enable bits
1= Common and individual interrupts are enabled for the corresponding channel
0= Common and individual interrupts are disabled for the corresponding channel
REGISTER 22-23: ADIEH: ADC INTERRUPT ENABLE REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IE<21:16>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
IE<21:16>: Common Interrupt Enable bits
1= Common and individual interrupts are enabled for the corresponding channel
0= Common and individual interrupts are disabled for the corresponding channel
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REGISTER 22-24: ADSTATL: ADC DATA READY STATUS REGISTER LOW
HSC/R-0
bit 15
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
bit 8
HSC/R-0
AN<15:8>RDY
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
AN<7:0>RDY
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
AN<15:0>RDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1= Channel conversion result is ready in the corresponding ADCBUFx register
0= Channel conversion result is not ready
REGISTER 22-25: ADSTATH: ADC DATA READY STATUS REGISTER HIGH
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
bit 0
AN<21:16>RDY
bit 7
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
AN<21:16>RDY: Common Interrupt Enable for Corresponding Analog Inputs bits
1= Channel conversion result is ready in the corresponding ADCBUFx register
0= Channel conversion result is not ready
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REGISTER 22-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
(x = 0 to 5)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
TRGSRC(4x+1)<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC(4x)<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
TRGSRC(4x+1)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111= ADTRG31
11110= PTG Trigger Output 12
11101= PWM Generator 6 current-limit trigger
11100= PWM Generator 5 current-limit trigger
11011= PWM Generator 4 current-limit trigger
11010= PWM Generator 3 current-limit trigger
11001= PWM Generator 2 current-limit trigger
11000= PWM Generator 1 current-limit trigger
10111= Output Compare 2 trigger
10110= Output Compare 1 trigger
10101= CLC2 output
10100= PWM Generator 6 secondary trigger
10011= PWM Generator 5 secondary trigger
10010= PWM Generator 4 secondary trigger
10001= PWM Generator 3 secondary trigger
10000= PWM Generator 2 secondary trigger
01111= PWM Generator 1 secondary trigger
01110= PWM secondary Special Event Trigger
01101= Timer2 period match
01100= Timer1 period match
01011= CLC1 output
01010= PWM Generator 6 primary trigger
01001= PWM Generator 5 primary trigger
01000= PWM Generator 4 primary trigger
00111= PWM Generator 3 primary trigger
00110= PWM Generator 2 primary trigger
00101= PWM Generator 1 primary trigger
00100= PWM Special Event Trigger
00011= Reserved
00010= Level software trigger
00001= Common software trigger
00000= No trigger is enabled
bit 7-5
Unimplemented: Read as ‘0’
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REGISTER 22-26: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW
(x = 0 to 5) (CONTINUED)
bit 4-0
TRGSRC(4x)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111= ADTRG31
11110= PTG Trigger Output 30
11101= PWM Generator 6 current-limit trigger
11100= PWM Generator 5 current-limit trigger
11011= PWM Generator 4 current-limit trigger
11010= PWM Generator 3 current-limit trigger
11001= PWM Generator 2 current-limit trigger
11000= PWM Generator 1 current-limit trigger
10111= Output Compare 2 trigger
10110= Output Compare 1 trigger
10101= CLC2 output
10100= PWM Generator 6 secondary trigger
10011= PWM Generator 5 secondary trigger
10010= PWM Generator 4 secondary trigger
10001= PWM Generator 3 secondary trigger
10000= PWM Generator 2 secondary trigger
01111= PWM Generator 1 secondary trigger
01110= PWM secondary Special Event Trigger
01101= Timer2 period match
01100= Timer1 period match
01011= CLC1 output
01010= PWM Generator 6 primary trigger
01001= PWM Generator 5 primary trigger
01000= PWM Generator 4 primary trigger
00111= PWM Generator 3 primary trigger
00110= PWM Generator 2 primary trigger
00101= PWM Generator 1 primary trigger
00100= PWM Special Event Trigger
00011= Reserved
00010= Level software trigger
00001= Common software trigger
00000= No trigger is enabled
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REGISTER 22-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
(x = 0 to 5)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
TRGSRC(4x+3)<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
TRGSRC(4x+2)<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
TRGSRC(4x+3)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111= ADTRG31
11110= PTG Trigger Output 30
11101= PWM Generator 6 current-limit trigger
11100= PWM Generator 5 current-limit trigger
11011= PWM Generator 4 current-limit trigger
11010= PWM Generator 3 current-limit trigger
11001= PWM Generator 2 current-limit trigger
11000= PWM Generator 1 current-limit trigger
10111= Output Compare 2 trigger
10110= Output Compare 1 trigger
10101= CLC2 output
10100= PWM Generator 6 secondary trigger
10011= PWM Generator 5 secondary trigger
10010= PWM Generator 4 secondary trigger
10001= PWM Generator 3 secondary trigger
10000= PWM Generator 2 secondary trigger
01111= PWM Generator 1 secondary trigger
01110= PWM secondary Special Event Trigger
01101= Timer2 period match
01100= Timer1 period match
01011= CLC1 output
01010= PWM Generator 6 primary trigger
01001= PWM Generator 5 primary trigger
01000= PWM Generator 4 primary trigger
00111= PWM Generator 3 primary trigger
00110= PWM Generator 2 primary trigger
00101= PWM Generator 1 primary trigger
00100= PWM Special Event Trigger
00011= Reserved
00010= Level software trigger
00001= Common software trigger
00000= No trigger is enabled
bit 7-5
Unimplemented: Read as ‘0’
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REGISTER 22-27: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH
(x = 0 to 5) (CONTINUED)
bit 4-0
TRGSRC(4x+2)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits
11111= ADTRG31
11110= PTG Trigger Output 30
11101= PWM Generator 6 current-limit trigger
11100= PWM Generator 5 current-limit trigger
11011= PWM Generator 4 current-limit trigger
11010= PWM Generator 3 current-limit trigger
11001= PWM Generator 2 current-limit trigger
11000= PWM Generator 1 current-limit trigger
10111= Output Compare 2 trigger
10110= Output Compare 1 trigger
10101= CLC2 output
10100= PWM Generator 6 secondary trigger
10011= PWM Generator 5 secondary trigger
10010= PWM Generator 4 secondary trigger
10001= PWM Generator 3 secondary trigger
10000= PWM Generator 2 secondary trigger
01111= PWM Generator 1 secondary trigger
01110= PWM secondary Special Event Trigger
01101= Timer2 period match
01100= Timer1 period match
01011= CLC1 output
01010= PWM Generator 6 primary trigger
01001= PWM Generator 5 primary trigger
01000= PWM Generator 4 primary trigger
00111= PWM Generator 3 primary trigger
00110= PWM Generator 2 primary trigger
00101= PWM Generator 1 primary trigger
00100= PWM Special Event Trigger
00011= Reserved
00010= Level software trigger
00001= Common software trigger
00000= No trigger is enabled
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REGISTER 22-28: ADCAL0L: ADC CALIBRATION REGISTER 0 LOW
HSC/R-0
U-0
—
U-0
—
U-0
—
r-0
—
R/W-0
R/W-0
R/W-0
CAL1RDY
CAL1DIFF
CAL1EN
CAL1RUN
bit 15
bit 8
HSC/R-0
U-0
—
U-0
—
U-0
—
r-0
—
R/W-0
R/W-0
R/W-0
CAL0RDY
CAL0DIFF
CAL0EN
CAL0RUN
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CAL1RDY: Dedicated ADC Core 1 Calibration Status Flag bit
1= Dedicated ADC Core 1 calibration is finished
0= Dedicated ADC Core 1 calibration is in progress
bit 14-12
bit 11
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 10
CAL1DIFF: Dedicated ADC Core 1 Differential-Mode Calibration bit
1= Dedicated ADC Core 1 will be calibrated in Differential Input mode
0= Dedicated ADC Core 1 will be calibrated in Single-Ended Input mode
bit 9
bit 8
bit 7
CAL1EN: Dedicated ADC Core 1 Calibration Enable bit
1= Dedicated ADC Core 1 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0= Dedicated ADC Core 1 calibration bits are disabled
CAL1RUN: Dedicated ADC Core 1 Calibration Start bit
1= If this bit is set by software, the dedicated ADC Core 1 calibration cycle is started; this bit is
automatically cleared by hardware
0= Software can start the next calibration cycle
CAL0RDY: Dedicated ADC Core 0 Calibration Status Flag bit
1= Dedicated ADC Core 0 calibration is finished
0= Dedicated ADC Core 0 calibration is in progress
bit 6-4
bit 3
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 2
CAL0DIFF: Dedicated ADC Core 0 Differential-Mode Calibration bit
1= Dedicated ADC Core 0 will be calibrated in Differential Input mode
0= Dedicated ADC Core 0 will be calibrated in Single-Ended Input mode
bit 1
bit 0
CAL0EN: Dedicated ADC Core 0 Calibration Enable bit
1= Dedicated ADC Core 0 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0= Dedicated ADC Core 0 calibration bits are disabled
CAL0RUN: Dedicated ADC Core 0 Calibration Start bit
1= If this bit is set by software, the dedicated ADC Core 0 calibration cycle is started; this bit is
automatically cleared by hardware
0= Software can start the next calibration cycle
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REGISTER 22-29: ADCAL0H: ADC CALIBRATION REGISTER 0 HIGH
HSC/R-0
U-0
—
U-0
—
U-0
—
r-0
—
R/W-0
R/W-0
R/W-0
CAL3RDY
CAL3DIFF
CAL3EN
CAL3RUN
bit 15
bit 8
HSC/R-0
U-0
—
U-0
—
U-0
—
r-0
—
R/W-0
R/W-0
R/W-0
CAL2RDY
CAL2DIFF
CAL2EN
CAL2RUN
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CAL3RDY: Dedicated ADC Core 3 Calibration Status Flag bit
1= Dedicated ADC Core 3 calibration is finished
0= Dedicated ADC Core 3 calibration is in progress
bit 14-12
bit 11
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 10
CAL3DIFF: Dedicated ADC Core 3 Differential-Mode Calibration bit
1= Dedicated ADC Core 3 will be calibrated in Differential Input mode
0= Dedicated ADC Core 3 will be calibrated in Single-Ended Input mode
bit 9
bit 8
bit 7
CAL3EN: Dedicated ADC Core 3 Calibration Enable bit
1= Dedicated ADC Core 3 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0= Dedicated ADC Core 3 calibration bits are disabled
CAL3RUN: Dedicated ADC Core 3 Calibration Start bit
1= If this bit is set by software, the dedicated ADC Core 3 calibration cycle is started; this bit is
automatically cleared by hardware
0= Software can start the next calibration cycle
CAL2RDY: Dedicated ADC Core 2 Calibration Status Flag bit
1= Dedicated ADC Core 2 calibration is finished
0= Dedicated ADC Core 2 calibration is in progress
bit 6-4
bit 3
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 2
CAL2DIFF: Dedicated ADC Core 2 Differential-Mode Calibration bit
1= Dedicated ADC Core 2 will be calibrated in Differential Input mode
0= Dedicated ADC Core 2 will be calibrated in Single-Ended Input mode
bit 1
bit 0
CAL2EN: Dedicated ADC Core 2 Calibration Enable bit
1= Dedicated ADC Core 2 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by
software
0= Dedicated ADC Core 2 calibration bits are disabled
CAL2RUN: Dedicated ADC Core 2 Calibration Start bit
1= If this bit is set by software, the dedicated ADC Core 2 calibration cycle is started; this bit is
automatically cleared by hardware
0= Software can start the next calibration cycle
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REGISTER 22-30: ADCAL1H: ADC CALIBRATION REGISTER 1 HIGH
HS/R/W-0
CSHRRDY
bit 15
U-0
—
U-0
—
U-0
—
r-0
—
R/W-0
R/W-0
R/W-0
CSHRRUN
bit 8
CSHRDIFF
CSHREN
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
r = Reserved bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
HS = Hardware Settable bit
R = Readable bit
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
bit 15
CSHRRDY: Shared ADC Core Calibration Status Flag bit
1= Shared ADC core calibration is finished
0= Shared ADC core calibration is in progress
bit 14-12
bit 11
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
bit 10
CSHRDIFF: Shared ADC Core Differential-Mode Calibration bit
1= Shared ADC core will be calibrated in Differential Input mode
0= Shared ADC core will be calibrated in Single-Ended Input mode
bit 9
CSHREN: Shared ADC Core Calibration Enable bit
1= Shared ADC core calibration bits (CSHRRDY, CSHRDIFF and CSHRRUN) can be accessed by
software
0= Shared ADC core calibration bits are disabled
bit 8
CSHRRUN: Shared ADC Core Calibration Start bit
1= If this bit is set by software, the shared ADC core calibration cycle is started; this bit is cleared
automatically by hardware
0= Software can start the next calibration cycle
bit 7-0
Unimplemented: Read as ‘0’
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REGISTER 22-31: ADCMPxCON: ADC DIGITAL COMPARATOR x CONTROL REGISTER (x = 0 or 1)
U-0
—
U-0
—
U-0
—
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
HSC/R-0
CHNL<4:0>
bit 15
bit 8
R/W-0
R/W-0
IE
HC/HS/R-0
STAT
R/W-0
BTWN
R/W-0
HIHI
R/W-0
HILO
R/W-0
LOHI
R/W-0
LOLO
CMPEN
bit 7
bit 0
Legend:
HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared HS = Hardware Settable bit
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
CHNL<4:0>: Input Channel Number bits
If the comparator has detected an event for a channel, this channel number is written to these bits.
11111= Reserved
•
•
10110= Reserved
10101= AN21
10100= AN20
•
•
00001= AN1
00000= AN0
bit 7
bit 6
bit 5
CMPEN: Comparator Enable bit
1= Comparator is enabled
0= Comparator is disabled and the STAT status bit is cleared
IE: Comparator Common ADC Interrupt Enable bit
1= Common ADC interrupt will be generated if the comparator detects a comparison event
0= Common ADC interrupt will not be generated for the comparator
STAT: Comparator Event Status bit
This bit is cleared by hardware when the channel number is read from the CHNL<4:0> bits.
1= A comparison event has been detected since the last read of the CHNL<4:0> bits
0= A comparison event has not been detected since the last read of the CHNL<4:0> bits
bit 4
bit 3
bit 2
bit 1
bit 0
BTWN: Between Low/High Comparator Event bit
1= Generates a comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
0= Does not generate a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI
HIHI: High/High Comparator Event bit
1= Generates a digital comparator event when ADCBUFx ≥ ADCMPxHI
0= Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxHI
HILO: High/Low Comparator Event bit
1= Generates a digital comparator event when ADCBUFx < ADCMPxHI
0= Does not generate a digital comparator event when ADCBUFx < ADCMPxHI
LOHI: Low/High Comparator Event bit
1= Generates a digital comparator event when ADCBUFx ≥ ADCMPxLO
0= Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxLO
LOLO: Low/Low Comparator Event bit
1= Generates a digital comparator event when ADCBUFx < ADCMPxLO
0= Does not generate a digital comparator event when ADCBUFx < ADCMPxLO
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REGISTER 22-32: ADCMPxENL: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER
LOW (x = 0 or 1)
R/W-0
bit 15
R/W/0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
CMPEN<15:8>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
CMPEN<15:0>: Comparator Enable for Corresponding Input Channels bits
1= Conversion result for corresponding channel is used by the comparator
0= Conversion result for corresponding channel is not used by the comparator
REGISTER 22-33: ADCMPxENH: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER
HIGH (x = 0 or 1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
—
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPEN<21:16>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
CMPEN<21:16>: Comparator Enable for Corresponding Input Channels bits
1= Conversion result for corresponding channel is used by the comparator
0= Conversion result for corresponding channel is not used by the comparator
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REGISTER 22-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1)
R/W-0
FLEN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
IE
HSC/R-0
RDY
MODE1
MODE0
OVRSAM2
OVRSAM1
OVRSAM0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FLCHSEL<4:0>
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HSC = Hardware Settable/Clearable bit
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
FLEN: Filter Enable bit
1= Filter is enabled
0= Filter is disabled and the RDY bit is cleared
bit 14-13
MODE<1:0>: Filter Mode bits
11= Averaging mode
10= Reserved
01= Reserved
00= Oversampling mode
bit 12-10
OVRSAM<2:0>: Filter Averaging/Oversampling Ratio bits
If MODE<1:0> = 00:
111= 128x (16-bit result in the ADFLxDAT register is in 12.4 format)
110= 32x (15-bit result in the ADFLxDAT register is in 12.3 format)
101= 8x (14-bit result in the ADFLxDAT register is in 12.2 format)
100= 2x (13-bit result in the ADFLxDAT register is in 12.1 format)
011= 256x (16-bit result in the ADFLxDAT register is in 12.4 format)
010= 64x (15-bit result in the ADFLxDAT register is in 12.3 format)
001= 16x (14-bit result in the ADFLxDAT register is in 12.2 format)
000= 4x (13-bit result in the ADFLxDAT register is in 12.1 format)
If MODE<1:0> = 11(12-bit result in the ADFLxDAT register in all instances):
111= 256x
110= 128x
101= 64x
100= 32x
011= 16x
010= 8x
001= 4x
000= 2x
bit 9
bit 8
IE: Filter Common ADC Interrupt Enable bit
1= Common ADC interrupt will be generated when the filter result will be ready
0= Common ADC interrupt will not be generated for the filter
RDY: Oversampling Filter Data Ready Flag bit
This bit is cleared by hardware when the result is read from the ADFLxDAT register.
1= Data in the ADFLxDAT register is ready
0= The ADFLxDAT register has been read and new data in the ADFLxDAT register is not ready
bit 7-5
Unimplemented: Read as ‘0’
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REGISTER 22-34: ADFLxCON: ADC DIGITAL FILTER x CONTROL REGISTER
(x = 0 or 1) (CONTINUED)
bit 4-0
FLCHSEL<4:0>: Oversampling Filter Input Channel Selection bits
11111= Reserved
•
•
•
10110= Reserved
10101= AN21
10100= AN20
•
•
•
00001= AN1
00000= AN0
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NOTES:
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The CAN module features are as follows:
23.0 CONTROLLER AREA
• Implementation of the CAN Protocol, CAN 1.2,
CAN 2.0A and CAN 2.0B
NETWORK (CAN) MODULE
(dsPIC33EPXXXGS80X
DEVICES ONLY)
• Standard and Extended Data Frames
• 0-8 Bytes of Data Length
Note 1: This data sheet summarizes the features
of the dsPIC33EPXXXGS70X/80X family
of devices. It is not intended to be a
comprehensive reference source. To com-
plement the information in this data sheet,
refer to “Enhanced Controller Area
Network (ECAN™)” (DS70353) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
• Programmable Bit Rate, up to 1 Mbit/sec
• Automatic Response to Remote Transmission
Requests
• Up to Eight Transmit Buffers with Application
Specified Prioritization and Abort Capability (each
buffer can contain up to 8 bytes of data)
• Up to 32 Receive Buffers (each buffer can contain
up to 8 bytes of data)
• Up to 16 Full (Standard/Extended Identifier)
Acceptance Filters
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Three Full Acceptance Filter Masks
• DeviceNet™ Addressing Support
• Programmable Wake-up Functionality with
Integrated Low-Pass Filter
• Programmable Loopback mode supports
Self-Test Operation
• Signaling via Interrupt Capabilities for All CAN
Receiver and Transmitter Error States
23.1 Overview
The Controller Area Network (CAN) module is a serial
interface, useful for communicating with other CAN
modules or microcontroller devices. This interface/
protocol was designed to allow communications within
noisy environments. The dsPIC33EPXXXGS80X
devices contain two CAN modules.
• Programmable Clock Source
• Programmable Link to Input Capture 2 (IC2)
module for Timestamping and Network
Synchronization
• Low-Power Sleep and Idle modes
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
The CAN module is a communication controller, imple-
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH CAN specification. The module supports
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implemen-
tation is a full CAN system. The CAN specification is
not covered within this data sheet. The reader can refer
to the BOSCH CAN specification for further details.
2016-2018 Microchip Technology Inc.
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FIGURE 23-1:
CANx MODULE BLOCK DIAGRAM
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
RxF11 Filter
RxF10 Filter
RxF9 Filter
RxF8 Filter
RxF7 Filter
RxF6 Filter
RxF5 Filter
RxF4 Filter
RxF3 Filter
RxF2 Filter
RxF1 Filter
RxF0 Filter
DMA Controller
TRB7 TX/RX Buffer Control Register
TRB6 TX/RX Buffer Control Register
TRB5 TX/RX Buffer Control Register
TRB4 TX/RX Buffer Control Register
TRB3 TX/RX Buffer Control Register
TRB2 TX/RX Buffer Control Register
TRB1 TX/RX Buffer Control Register
TRB0 TX/RX Buffer Control Register
RxM2 Mask
RxM1 Mask
RxM0 Mask
Transmit Byte
Sequencer
Message Assembly
Buffer
Control
Configuration
Logic
CPU
Bus
CAN Protocol
Engine
Interrupts
CxTX
CxRX
Modes are requested by setting the REQOP<2:0> bits
(CxCTRL1<10:8>). Entry into a mode is Acknowledged
by monitoring the OPMODE<2:0> bits (CxCTRL1<7:5>).
The module does not change the mode and the
OPMODEx bits until a change in mode is acceptable,
generally during bus Idle time, which is defined as at least
eleven consecutive recessive bits.
23.2 Modes of Operation
The CANx module can operate in one of several
operation modes selected by the user. These modes
include:
• Initialization mode
• Disable mode
• Normal Operation mode
• Listen Only mode
• Listen All Messages mode
• Loopback mode
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23.3 CAN Control Registers
REGISTER 23-1: CxCTRL1: CANx CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
CSIDL
R/W-0
ABAT
R/W-0
R/W-1
R/W-0
R/W-0
CANCKS
REQOP2
REQOP1
REQOP0
bit 15
bit 8
R-1
R-0
R-0
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
WIN
OPMODE2
OPMODE1 OPMODE0
CANCAP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CSIDL: CANx Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode
0= Continues module operation in Idle mode
bit 12
ABAT: Abort All Pending Transmissions bit
1= Signals all transmit buffers to abort transmission
0= Module will clear this bit when all transmissions are aborted
bit 11
CANCKS: CANx Module Clock (FCAN) Source Select bit
1= FCAN is equal to 2 * FP
0= FCAN is equal to FP
bit 10-8
REQOP<2:0>: Request Operation Mode bits
111= Set Listen All Messages mode
110= Reserved
101= Reserved
100= Set Configuration mode
011= Set Listen Only mode
010= Set Loopback mode
001= Set Disable mode
000= Set Normal Operation mode
bit 7-5
OPMODE<2:0>: Operation Mode bits
111= Module is in Listen All Messages mode
110= Reserved
101= Reserved
100= Module is in Configuration mode
011= Module is in Listen Only mode
010= Module is in Loopback mode
001= Module is in Disable mode
000= Module is in Normal Operation mode
bit 4
bit 3
Unimplemented: Read as ‘0’
CANCAP: CANx Message Receive Timer Capture Event Enable bit
1= Enables input capture based on CAN message receive
0= Disables CAN capture
bit 2-1
bit 0
Unimplemented: Read as ‘0’
WIN: SFR Map Window Select bit
1= Uses filter window
0= Uses buffer window
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REGISTER 23-2: CxCTRL2: CANx CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
DNCNT<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111= Invalid selection
10001= Compare up to Data Byte 3, bit 6 with EID<17>
•
•
•
00001= Compare up to Data Byte 1, bit 7 with EID<0>
00000= Do not compare data bytes
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REGISTER 23-3: CxVEC: CANx INTERRUPT CODE REGISTER
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
FILHIT4
FILHIT3
FILHIT2
FILHIT1
FILHIT0
bit 15
bit 8
U-0
—
R-1
R-0
R-0
R-0
R-0
R-0
R-0
ICODE6
ICODE5
ICODE4
ICODE3
ICODE2
ICODE1
ICODE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Number bits
10000-11111= Reserved
01111= Filter 15
•
•
•
00001= Filter 1
00000= Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111= Reserved
1000100= FIFO almost full interrupt
1000011= Receiver overflow interrupt
1000010= Wake-up interrupt
1000001= Error interrupt
1000000= No interrupt
•
•
•
0010000-0111111= Reserved
0001111= RB15 buffer interrupt
•
•
•
0001001= RB9 buffer interrupt
0001000= RB8 buffer interrupt
0000111= TRB7 buffer interrupt
0000110= TRB6 buffer interrupt
0000101= TRB5 buffer interrupt
0000100= TRB4 buffer interrupt
0000011= TRB3 buffer interrupt
0000010= TRB2 buffer interrupt
0000001= TRB1 buffer interrupt
0000000= TRB0 buffer interrupt
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REGISTER 23-4: CxFCTRL: CANx FIFO CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMABS2
DMABS1
DMABS0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
FSA4
R/W-0
FSA3
R/W-0
FSA2
R/W-0
FSA1
R/W-0
FSA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-13
DMABS<2:0>: DMA Buffer Size bits
111= Reserved
110= 32 buffers in RAM
101= 24 buffers in RAM
100= 16 buffers in RAM
011= 12 buffers in RAM
010= 8 buffers in RAM
001= 6 buffers in RAM
000= 4 buffers in RAM
bit 12-5
bit 4-0
Unimplemented: Read as ‘0’
FSA<4:0>: FIFO Area Starts with Buffer bits
11111= Receive Buffer RB31
11110= Receive Buffer RB30
•
•
•
00001= Transmit/Receive Buffer TRB1
00000= Transmit/Receive Buffer TRB0
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REGISTER 23-5: CxFIFO: CANx FIFO STATUS REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
FBP5
FBP4
FBP3
FBP2
FBP1
FBP0
bit 15
bit 8
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
FNRB5
FNRB4
FNRB3
FNRB2
FNRB1
FNRB0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FBP<5:0>: FIFO Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
•
•
•
000001= TRB1 buffer
000000= TRB0 buffer
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FNRB<5:0>: FIFO Next Read Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
•
•
•
000001= TRB1 buffer
000000= TRB0 buffer
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REGISTER 23-6: CxINTF: CANx INTERRUPT FLAG REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
bit 15
bit 8
R/C-0
IVRIF
R/C-0
R/C-0
U-0
—
R/C-0
R/C-0
R/C-0
RBIF
R/C-0
TBIF
WAKIF
ERRIF
FIFOIF
RBOVIF
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be Written to Clear bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
TXBO: Transmitter in Error State Bus Off bit
1= Transmitter is in Bus Off state
0= Transmitter is not in Bus Off state
bit 12
bit 11
bit 10
bit 9
TXBP: Transmitter in Error State Bus Passive bit
1= Transmitter is in Bus Passive state
0= Transmitter is not in Bus Passive state
RXBP: Receiver in Error State Bus Passive bit
1= Receiver is in Bus Passive state
0= Receiver is not in Bus Passive state
TXWAR: Transmitter in Error State Warning bit
1= Transmitter is in Error Warning state
0= Transmitter is not in Error Warning state
RXWAR: Receiver in Error State Warning bit
1= Receiver is in Error Warning state
0= Receiver is not in Error Warning state
bit 8
EWARN: Transmitter or Receiver in Error State Warning bit
1= Transmitter or receiver is in Error Warning state
0= Transmitter or receiver is not in Error Warning state
bit 7
IVRIF: Invalid Message Interrupt Flag bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
WAKIF: Bus Wake-up Activity Interrupt Flag bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
ERRIF: Error Interrupt Flag bit (multiple sources in CxINTF<13:8> register)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
bit 3
Unimplemented: Read as ‘0’
FIFOIF: FIFO Almost Full Interrupt Flag bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 2
RBOVIF: RX Buffer Overflow Interrupt Flag bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
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REGISTER 23-6: CxINTF: CANx INTERRUPT FLAG REGISTER (CONTINUED)
bit 1
RBIF: RX Buffer Interrupt Flag bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 0
TBIF: TX Buffer Interrupt Flag bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
REGISTER 23-7: CxINTE: CANx INTERRUPT ENABLE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
IVRIE
R/W-0
R/W-0
ERRIE
U-0
—
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
TBIE
WAKIE
FIFOIE
RBOVIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
IVRIE: Invalid Message Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 6
bit 5
WAKIE: Bus Wake-up Activity Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
ERRIE: Error Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
FIFOIE: FIFO Almost Full Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
bit 2
bit 1
bit 0
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
RBIE: RX Buffer Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
TBIE: TX Buffer Interrupt Enable bit
1= Interrupt request is enabled
0= Interrupt request is not enabled
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REGISTER 23-8: CxEC: CANx TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
TERRCNT7 TERRCNT6 TERRCNT5 TERRCNT4 TERRCNT3 TERRCNT2 TERRCNT1 TERRCNT0
bit 15 bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
RERRCNT7 RERRCNT6 RERRCNT5 RERRCNT4 RERRCNT3 RERRCNT2 RERRCNT1 RERRCNT0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
TERRCNT<7:0>: Transmit Error Count bits
RERRCNT<7:0>: Receive Error Count bits
REGISTER 23-9: CxCFG1: CANx BAUD RATE CONFIGURATION REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
SJW1
R/W-0
SJW0
R/W-0
BRP5
R/W-0
BRP4
R/W-0
BRP3
R/W-0
BRP2
R/W-0
BRP1
R/W-0
BRP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
SJW<1:0>: Synchronization Jump Width bits
11= Length is 4 x TQ
10= Length is 3 x TQ
01= Length is 2 x TQ
00= Length is 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
11 1111= TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010= TQ = 2 x 3 x 1/FCAN
00 0001= TQ = 2 x 2 x 1/FCAN
00 0000= TQ = 2 x 1 x 1/FCAN
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REGISTER 23-10: CxCFG2: CANx BAUD RATE CONFIGURATION REGISTER 2
U-0
—
R/W-x
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WAKFIL
SEG2PH2
SEG2PH1
SEG2PH0
bit 15
bit 8
R/W-x
R/W-x
SAM
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEG2PHTS
SEG1PH2
SEG1PH1
SEG1PH0
PRSEG2
PRSEG1
PRSEG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
WAKFIL: Select CAN Bus Line Filter for Wake-up bit
1= Uses CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 13-11
bit 10-8
Unimplemented: Read as ‘0’
SEG2PH<2:0>: Phase Segment 2 bits
111= Length is 8 x TQ
•
•
•
000= Length is 1 x TQ
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of SEG1PHx bits or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN Bus Line bit
1= Bus line is sampled three times at the sample point
0= Bus line is sampled once at the sample point
bit 5-3
SEG1PH<2:0>: Phase Segment 1 bits
111= Length is 8 x TQ
•
•
•
000= Length is 1 x TQ
bit 2-0
PRSEG<2:0>: Propagation Time Segment bits
111= Length is 8 x TQ
•
•
•
000= Length is 1 x TQ
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REGISTER 23-11: CxFEN1: CANx ACCEPTANCE FILTER ENABLE REGISTER 1
R/W-1
bit 15
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
FLTEN<15:8>
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
FLTEN<15:0>: Enable Filter n to Accept Messages bits
1= Enables Filter n
0= Disables Filter n
REGISTER 23-12: CxBUFPNT1: CANx FILTERS 0-3 BUFFER POINTER REGISTER 1
R/W-0
F3BP3
R/W-0
F3BP2
R/W-0
F3BP1
R/W-0
F3BP0
R/W-0
F2BP3
R/W-0
F2BP2
R/W-0
F2BP1
R/W-0
F2BP0
bit 15
bit 8
R/W-0
F1BP3
R/W-0
F1BP2
R/W-0
F1BP1
R/W-0
F1BP0
R/W-0
F0BP3
R/W-0
F0BP2
R/W-0
F0BP1
R/W-0
F0BP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F3BP<3:0>: RX Buffer Mask for Filter 3 bits
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F2BP<3:0>: RX Buffer Mask for Filter 2 bits (same values as bits 15-12)
F1BP<3:0>: RX Buffer Mask for Filter 1 bits (same values as bits 15-12)
F0BP<3:0>: RX Buffer Mask for Filter 0 bits (same values as bits 15-12)
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REGISTER 23-13: CxBUFPNT2: CANx FILTERS 4-7 BUFFER POINTER REGISTER 2
R/W-0
F7BP3
R/W-0
F7BP2
R/W-0
F7BP1
R/W-0
F7BP0
R/W-0
F6BP3
R/W-0
F6BP2
R/W-0
F6BP1
R/W-0
F6BP0
bit 15
bit 8
R/W-0
F5BP3
R/W-0
F5BP2
R/W-0
F5BP1
R/W-0
F5BP0
R/W-0
F4BP3
R/W-0
F4BP2
R/W-0
F4BP1
R/W-0
F4BP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F7BP<3:0>: RX Buffer Mask for Filter 7 bits
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F6BP<3:0>: RX Buffer Mask for Filter 6 bits (same values as bits 15-12)
F5BP<3:0>: RX Buffer Mask for Filter 5 bits (same values as bits 15-12)
F4BP<3:0>: RX Buffer Mask for Filter 4 bits (same values as bits 15-12)
REGISTER 23-14: CxBUFPNT3: CANx FILTERS 8-11 BUFFER POINTER REGISTER 3
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11BP3
F11BP2
F11BP1
F11BP0
F10BP3
F10BP2
F10BP1
F10BP0
bit 15
bit 8
R/W-0
F9BP3
R/W-0
F9BP2
R/W-0
F9BP1
R/W-0
F9BP0
R/W-0
F8BP3
R/W-0
F8BP2
R/W-0
F8BP1
R/W-0
F8BP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F11BP<3:0>: RX Buffer Mask for Filter 11 bits
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F10BP<3:0>: RX Buffer Mask for Filter 10 bits (same values as bits 15-12)
F9BP<3:0>: RX Buffer Mask for Filter 9 bits (same values as bits 15-12)
F8BP<3:0>: RX Buffer Mask for Filter 8 bits (same values as bits 15-12)
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REGISTER 23-15: CxBUFPNT4: CANx FILTERS 12-15 BUFFER POINTER REGISTER 4
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15BP3
F15BP2
F15BP1
F15BP0
F14BP3
F14BP2
F14BP1
F14BP0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F13BP3
F13BP2
F13BP1
F13BP0
F12BP3
F12BP2
F12BP1
F12BP0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F15BP<3:0>: RX Buffer Mask for Filter 15 bits
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F14BP<3:0>: RX Buffer Mask for Filter 14 bits (same values as bits 15-12)
F13BP<3:0>: RX Buffer Mask for Filter 13 bits (same values as bits 15-12)
F12BP<3:0>: RX Buffer Mask for Filter 12 bits (same values as bits 15-12)
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REGISTER 23-16: CxRXFnSID: CANx ACCEPTANCE FILTER n STANDARD IDENTIFIER
REGISTER (n = 0-15)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Message address bit, SIDx, must be ‘1’ to match filter
0= Message address bit, SIDx, must be ‘0’ to match filter
bit 4
bit 3
Unimplemented: Read as ‘0’
EXIDE: Extended Identifier Enable bit
If MIDE = 1:
1= Matches only messages with Extended Identifier addresses
0= Matches only messages with Standard Identifier addresses
If MIDE = 0:
Ignores EXIDE bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Message address bit, EIDx, must be ‘1’ to match filter
0= Message address bit, EIDx, must be ‘0’ to match filter
REGISTER 23-17: CxRXFnEID: CANx ACCEPTANCE FILTER n EXTENDED IDENTIFIER
REGISTER (n = 0-15)
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
EID<15:8>
bit 15
R/W-x
bit 7
R/W-x
R/W-x
R/W-x R/W-x
EID<7:0>
R/W-x
R/W-x
R/W-x
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Message address bit, EIDx, must be ‘1’ to match filter
0= Message address bit, EIDx, must be ‘0’ to match filter
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REGISTER 23-18: CxFMSKSEL1: CANx FILTERS 7-0 MASK SELECTION REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7MSK1
F7MSK0
F6MSK1
F6MSK0
F5MSK1
F5MSK0
F4MSK1
F4MSK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F3MSK1
F3MSK0
F2MSK1
F2MSK0
F1MSK1
F1MSK0
F0MSK1
F0MSK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
F7MSK<1:0>: Mask Source for Filter 7 bits
11= Reserved
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
bit 13-12
bit 11-10
bit 9-8
F6MSK<1:0>: Mask Source for Filter 6 bits (same values as bits 15-14)
F5MSK<1:0>: Mask Source for Filter 5 bits (same values as bits 15-14)
F4MSK<1:0>: Mask Source for Filter 4 bits (same values as bits 15-14)
F3MSK<1:0>: Mask Source for Filter 3 bits (same values as bits 15-14)
F2MSK<1:0>: Mask Source for Filter 2 bits (same values as bits 15-14)
F1MSK<1:0>: Mask Source for Filter 1 bits (same values as bits 15-14)
F0MSK<1:0>: Mask Source for Filter 0 bits (same values as bits 15-14)
bit 7-6
bit 5-4
bit 3-2
bit 1-0
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REGISTER 23-19: CxFMSKSEL2: CANx FILTERS 15-8 MASK SELECTION REGISTER 2
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15MSK1
F15MSK0
F14MSK1
F14MSK0
F13MSK1
F13MSK0
F12MSK1
F12MSK0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11MSK1
F11MSK0
F10MSK1
F10MSK0
F9MSK1
F9MSK0
F8MSK1
F8MSK0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
F15MSK<1:0>: Mask Source for Filter 15 bits
11= Reserved
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
bit 13-12
bit 11-10
bit 9-8
F14MSK<1:0>: Mask Source for Filter 14 bits (same values as bits 15-14)
F13MSK<1:0>: Mask Source for Filter 13 bits (same values as bits 15-14)
F12MSK<1:0>: Mask Source for Filter 12 bits (same values as bits 15-14)
F11MSK<1:0>: Mask Source for Filter 11 bits (same values as bits 15-14)
F10MSK<1:0>: Mask Source for Filter 10 bits (same values as bits 15-14)
F9MSK<1:0>: Mask Source for Filter 9 bits (same values as bits 15-14)
F8MSK<1:0>: Mask Source for Filter 8 bits (same values as bits 15-14)
bit 7-6
bit 5-4
bit 3-2
bit 1-0
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REGISTER 23-20: CxRXMnSID: CANx ACCEPTANCE FILTER MASK n STANDARD IDENTIFIER
REGISTER (n = 0-2)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
MIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Includes bit, SIDx, in filter comparison
0= Bit, SIDx, is a don’t care in filter comparison
bit 4
bit 3
Unimplemented: Read as ‘0’
MIDE: Identifier Receive Mode bit
1= Matches only message types (standard or extended address) that correspond to the EXIDE bit in
the filter
0= Matches either standard or extended address message if filters match
(i.e., if (Filter SIDx) = (Message SIDx) or if (Filter SIDx/EIDx) = (Message SIDx/EIDx))
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Includes bit, EIDx, in filter comparison
0= Bit, EIDx, is a don’t care in filter comparison
REGISTER 23-21: CxRXMnEID: CANx ACCEPTANCE FILTER MASK n EXTENDED IDENTIFIER
REGISTER (n = 0-2)
R/W-x
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
EID<15:8>
R/W-x
R/W-x
R/W-x
EID<7:0>
R/W-x
R/W-x
R/W-x
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Includes bit, EIDx, in filter comparison
0= Bit, EIDx, is a don’t care in filter comparison
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REGISTER 23-22: CxRXFUL1: CANx RECEIVE BUFFER FULL REGISTER 1
R/C-0
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
bit 8
R/C-0
RXFUL<15:8>
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL<7:0>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be Written to Clear bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
RXFUL<15:0>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty (cleared by user software)
REGISTER 23-23: CxRXFUL2: CANx RECEIVE BUFFER FULL REGISTER 2
R/C-0
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
bit 8
R/C-0
RXFUL<31:24>
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL<23:16>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be Written to Clear bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
RXFUL<31:16>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty (cleared by user software)
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REGISTER 23-24: CxRXOVF1: CANx RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
bit 8
R/C-0
RXOVF<15:8>
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF<7:0>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be Written to Clear bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
RXOVF<15:0>: Receive Buffer n Overflow bits
1= Module attempted to write to a full buffer (set by module)
0= No overflow condition (cleared by user software)
REGISTER 23-25: CxRXOVF2: CANx RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
bit 8
R/C-0
RXOVF<31:24>
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF<23:16>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be Written to Clear bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-0
RXOVF<31:16>: Receive Buffer n Overflow bits
1= Module attempted to write to a full buffer (set by module)
0= No overflow condition (cleared by user software)
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REGISTER 23-26: CxTRmnCON: CANx TX/RX BUFFER mn CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI1
TXnPRI0
bit 15
bit 8
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENm
TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm
RTRENm
TXmPRI1
TXmPRI0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
See Definition for bits 7-0, controls Buffer n.
TXENm: TX/RX Buffer m Selection bit
1= Buffer, TRBm, is a transmit buffer
0= Buffer, TRBm, is a receive buffer
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
TXABTm: Message Aborted bit(1)
1= Message was aborted
0= Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit(1)
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit(1)
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
1= Requests that a message be sent; the bit automatically clears when the message is successfully sent
0= Clearing the bit to ‘0’ while set requests a message abort
RTRENm: Auto-Remote Transmit Enable bit
1= When a remote transmit is received, TXREQx will be set
0= When a remote transmit is received, TXREQx will be unaffected
TXmPRI<1:0>: Message Transmission Priority bits
11= Highest message priority
10= High intermediate message priority
01= Low intermediate message priority
00= Lowest message priority
Note 1: This bit is cleared when TXREQmn is set.
Note:
The buffers, SIDx, EIDx, DLCx, Data Field and Receive Status registers, are located in DMA RAM.
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23.4 CAN Message Buffers
CAN Message Buffers are part of RAM memory. They
are not CAN Special Function Registers. The user
application must directly write into the RAM area that is
configured for CAN Message Buffers. The location and
size of the buffer area is defined by the user
application.
BUFFER 21-1:
CANx MESSAGE BUFFER WORD 0
U-0
—
U-0
—
U-0
—
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
bit 15
bit 8
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
SRR
R/W-x
IDE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-2
bit 1
Unimplemented: Read as ‘0’
SID<10:0>: Standard Identifier bits
SRR: Substitute Remote Request bit
When IDE = 0:
1= Message will request remote transmission
0= Normal message
When IDE = 1:
The SRR bit must be set to ‘1’.
bit 0
IDE: Extended Identifier bit
1= Message will transmit an Extended Identifier
0= Message will transmit a Standard Identifier
BUFFER 21-2:
CANx MESSAGE BUFFER WORD 1
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<17:14>
bit 15
bit 8
R/W-x
bit 0
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
EID<13:6>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
EID<17:6>: Extended Identifier bits
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(
BUFFER 21-3:
CANx MESSAGE BUFFER WORD 2
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
R/W-x
RTR
R/W-x
RB1
bit 15
bit 8
U-x
—
U-x
—
U-x
—
R/W-x
RB0
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
EID<5:0>: Extended Identifier bits
RTR: Remote Transmission Request bit
When IDE = 1:
1= Message will request remote transmission
0= Normal message
When IDE = 0:
The RTR bit is ignored.
bit 8
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
Unimplemented: Read as ‘0’
RB0: Reserved Bit 0
bit 7-5
bit 4
User must set this bit to ‘0’ per CAN protocol.
DLC<3:0>: Data Length Code bits
bit 3-0
BUFFER 21-4:
CAN
R/W-x
x MESSAGE BUFFER WORD 3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 1<15:8>
bit 15
R/W-x
bit 7
bit 8
R/W-x
bit 0
R/W-x
R/W-x
R/W-x
R/W-x
Byte 0<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 1<15:8>: CANx Message Byte 1 bits
Byte 0<7:0>: CANx Message Byte 0 bits
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BUFFER 21-5:
CAN
R/W-x
x MESSAGE BUFFER WORD 4
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
Byte 3<15:8>
bit 15
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 2<7:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 3<15:8>: CANx Message Byte 3 bits
Byte 2<7:0>: CANx Message Byte 2 bits
BUFFER 21-6:
CAN
R/W-x
x MESSAGE BUFFER WORD 5
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 5<15:8>
bit 15
R/W-x
bit 7
bit 8
R/W-x
bit 0
R/W-x
R/W-x
R/W-x
R/W-x
Byte 4<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 5<15:8>: CANx Message Byte 5 bits
Byte 4<7:0>: CANx Message Byte 4 bits
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BUFFER 21-7:
CAN
R/W-x
x MESSAGE BUFFER WORD 6
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
Byte 7<15:8>
bit 15
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 6<7:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 7<15:8>: CANx Message Byte 7 bits
Byte 6<7:0>: CANx Message Byte 6 bits
BUFFER 21-8:
CANx MESSAGE BUFFER WORD 7
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
FILHIT<4:0>(1)
R/W-x
R/W-x
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
bit 7-0
Unimplemented: Read as ‘0’
Note 1: Only written by module for receive buffers, unused for transmit buffers.
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NOTES:
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24.1 Features Overview
24.0 HIGH-SPEED ANALOG
COMPARATOR
The Switch Mode Power Supply (SMPS) comparator
module offers the following major features:
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to “High-Speed Analog
Comparator Module” (DS70005128) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
• Four Rail-to-Rail Analog Comparators
• Dedicated 12-Bit DAC for each Analog
Comparator
• Up to Six Selectable Input Sources per
Comparator:
- Four external inputs
- Two internal inputs from the PGAx module
• Programmable Comparator Hysteresis
• Programmable Output Polarity
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Up to Two DAC Outputs to Device Pins
• Multiple Voltage References for the DAC:
- External References (EXTREF1 or
EXTREF2)
- AVDD
• Interrupt Generation Capability
• Functional Support for PWMx:
- PWM duty cycle control
- PWM period control
The high-speed analog comparator module monitors
current and/or voltage transients that may be too fast
for the CPU and ADC to capture.
- PWM Fault detected
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The analog comparator input pins are typically shared
24.2 Module Description
with pins used by the Analog-to-Digital Converter (ADC)
module. Both the comparator and the ADC can use the
same pins at the same time. This capability enables a
user to measure an input voltage with the ADC and
detect voltage transients with the comparator.
Figure 24-1 shows a functional block diagram of one
analog comparator from the high-speed analog
comparator module. The analog comparator provides
high-speed operation with a typical delay of 15 ns. The
negative input of the comparator is always connected
to the DACx circuit. The positive input of the compara-
tor is connected to an analog multiplexer that selects
the desired source pin.
FIGURE 24-1:
HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM
INSELx
ALTINP
PWM Trigger
(remappable I/O)
PGA1OUT
PGA2OUT
(1)
CMPxA
(1)
Status
CMPxB
CMPxC
(1)
0
1
Pulse Stretcher
and
Digital Filter
CMPx
(1)
(1)
CMPxD
Interrupt
Request
EXTREF
RANGE
CMPPOL
AVDD
(1)
(2)
DACOE
DACx
EXTREF1
(2,3)
EXTREF2
DAC1/
DAC3
12
CMREFx
Output
Buffer
DACOUT1
PGA1OUT
PGAOEN
DBCC bit
FDEVOPT<6>
DACOE
DAC2/
DAC4
Output
Buffer
(3)
DACOUT2
PGA2OUT
PGAOEN
Note 1: x = 1-4
2: EXTREF1 is connected to DAC1/DAC3. EXTREF2 is connected to DAC2/DAC4.
3: Not available on all devices.
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Each DACx has an output enable bit, DACOE, in the
24.3 Module Applications
CMPxCON register that enables the DACx reference
voltage to be routed to an external output pin
(DACOUTx). Refer to Figure 24-1 for connecting the
DACx output voltage to the DACOUTx pins.
This module provides a means for the SMPS dsPIC®
DSC devices to monitor voltage and currents in a
power conversion application. The ability to detect
transient conditions and stimulate the dsPIC DSC
processor and/or peripherals, without requiring the
processor and ADC to constantly monitor voltages or
currents, frees the dsPIC DSC to perform other tasks.
Note 1: Ensure that multiple DACOE bits are not
set in software. The output on the
DACOUTx pin will be indeterminate if
multiple comparators enable the DACx
output.
The comparator module has a high-speed comparator
and an associated 12-bit DAC that provides a
programmable reference voltage to the inverting input
of the comparator. The polarity of the comparator out-
put is user-programmable. The output of the module
can be used in the following modes:
2: DACOUT2 is not available on all devices.
24.5 Pulse Stretcher and Digital Logic
The analog comparator can respond to very fast tran-
sient signals. After the comparator output is given the
desired polarity, the signal is passed to a pulse
stretching circuit. The pulse stretching circuit has an
asynchronous set function and a delay circuit that
ensures the minimum pulse width is three system clock
cycles wide to allow the attached circuitry to properly
respond to a narrow pulse event.
• Generate an Interrupt
• Trigger an ADC Sample and Convert Process
• Truncate the PWM Signal (current limit)
• Truncate the PWM Period (current minimum)
• Disable the PWM Outputs (Fault latch)
The output of the comparator module may be used in
multiple modes at the same time, such as: 1) generate
an interrupt, 2) have the ADC take a sample and con-
vert it, and 3) truncate the PWM output in response to
a voltage being detected beyond its expected value.
The pulse stretcher circuit is followed by a digital filter.
The digital filter is enabled via the FLTREN bit in the
CMPxCON register. The digital filter operates with the
clock specified via the FCLKSEL bit in the CMPxCON
register. The comparator signal must be stable in a high
or low state, for at least three of the selected clock
cycles, for it to pass through the digital filter.
The comparator module can also be used to wake-up the
system from Sleep or Idle mode when the analog input
voltage exceeds the programmed threshold voltage.
24.4 Digital-to-Analog Comparator (DAC)
Each analog comparator has a dedicated 12-bit DAC
that is used to program the comparator threshold voltage
via the CMPxDAC register. The DAC voltage reference
source is selected using the EXTREF and RANGE bits
in the CMPxCON register.
The EXTREF bit selects either the external voltage ref-
erence, EXTREFx, or an internal source as the voltage
reference source. The EXTREFx input enables users to
connect to a voltage reference that better suits their
application. The RANGE bit enables AVDD as the
voltage reference source for the DAC when an internal
voltage reference is selected.
Note:
EXTREF2 is not available on all devices.
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24.6 Hysteresis
24.7 Analog Comparator Resources
An additional feature of the module is hysteresis con-
trol. Hysteresis can be enabled or disabled and its
amplitude can be controlled by the HYSSEL<1:0> bits
in the CMPxCON register. Three different values are
available: 15 mV, 30 mV and 45 mV. It is also possible
to select the edge (rising or falling) to which hysteresis
is to be applied.
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
24.7.1
KEY RESOURCES
• “High-Speed Analog Comparator Module”
(DS70005128) in the “dsPIC33/PIC24 Family
Reference Manual”
Hysteresis control prevents the comparator output from
continuously changing state because of small
perturbations (noise) at the input (see Figure 24-2).
• Code Samples
• Application Notes
• Software Libraries
• Webinars
FIGURE 24-2:
HYSTERESIS CONTROL
Output
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
Hysteresis Range
(15 mV/30 mV/45 mV)
Input
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REGISTER 24-1: CMPxCON: COMPARATOR x CONTROL REGISTER
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMPON
CMPSIDL
HYSSEL1
HYSSEL0
FLTREN
FCLKSEL
DACOE
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
HS/HC-0
R/W-0
R/W-0
R/W-0
INSEL1
INSEL0
EXTREF
HYSPOL
CMPSTAT
ALTINP
CMPPOL
RANGE
bit 7
bit 0
Legend:
HC = Hardware Clearable bit HS = Hardware Settable bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
CMPON: Comparator Operating Mode bit
1= Comparator module is enabled
0= Comparator module is disabled (reduces power consumption)
bit 14
bit 13
Unimplemented: Read as ‘0’
CMPSIDL: Comparator Stop in Idle Mode bit
1= Discontinues module operation when device enters Idle mode.
0= Continues module operation in Idle mode
If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables all comparators while in Idle mode.
bit 12-11
HYSSEL<1:0>: Comparator Hysteresis Select bits
11= 45 mV hysteresis
10= 30 mV hysteresis
01= 15 mV hysteresis
00= No hysteresis is selected
bit 10
bit 9
FLTREN: Digital Filter Enable bit
1= Digital filter is enabled
0= Digital filter is disabled
FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit
1= Digital filter and pulse stretcher operate with the PWM clock
0= Digital filter and pulse stretcher operate with the system clock
bit 8
DACOE: DACx Output Enable bit
1= DACx analog voltage is connected to the DACOUTx pin(1)
0= DACx analog voltage is not connected to the DACOUTx pin
bit 7-6
INSEL<1:0>: Input Source Select for Comparator bits
If ALTINP = 0, Select from Comparator Inputs:
11= Selects CMPxD input pin
10= Selects CMPxC input pin
01= Selects CMPxB input pin
00= Selects CMPxA input pin
If ALTINP = 1, Select from Alternate Inputs:
11= Reserved
10= Reserved
01= Selects PGA2 output
00= Selects PGA1 output
Note 1: DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.
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REGISTER 24-1: CMPxCON: COMPARATOR x CONTROL REGISTER (CONTINUED)
bit 5
EXTREF: Enable External Reference bit
1= External source provides reference to DACx (maximum DAC voltage is determined by the external
voltage source)
0= AVDD provides reference to DACx (maximum DAC voltage is AVDD)
bit 4
HYSPOL: Comparator Hysteresis Polarity Select bit
1= Hysteresis is applied to the falling edge of the comparator output
0= Hysteresis is applied to the rising edge of the comparator output
bit 3
bit 2
CMPSTAT: Comparator Current State bit
Reflects the current output state of Comparator x, including the setting of the CMPPOL bit.
ALTINP: Alternate Input Select bit
1= INSEL<1:0> bits select alternate inputs
0= INSEL<1:0> bits select comparator inputs
bit 1
bit 0
CMPPOL: Comparator Output Polarity Control bit
1= Output is inverted
0= Output is non-inverted
RANGE: DACx Output Voltage Range Select bit
1= AVDD is the maximum DACx output voltage
0= Unimplemented, do not use
Note 1: DACOUTx can be associated only with a single comparator at any given time. The software must ensure
that multiple comparators do not enable the DACx output by setting their respective DACOE bit.
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REGISTER 24-2: CMPxDAC: COMPARATOR x DAC CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
CMREF<11:8>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CMREF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
CMREF<11:0>: Comparator Reference Voltage Select bits
111111111111
•
•
•
•
= ([CMREF<11:0>] * (AVDD)/4096) volts (EXTREF = 0)
or ([CMREF<11:0>] * (EXTREF)/4096) volts (EXTREF = 1)
•
•
000000000000
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 344
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dsPIC33EPXXXGS70X/80X FAMILY
The dsPIC33EPXXXGS70X/80X family devices have
25.0 PROGRAMMABLE GAIN
two Programmable Gain Amplifiers (PGA1, PGA2).
The PGA is an op amp-based, non-inverting amplifier
with user-programmable gains. The output of the PGA
can be connected to a number of dedicated Sample-
and-Hold inputs of the Analog-to-Digital Converter and/
or to the high-speed analog comparator module. The
PGA has five selectable gains and may be used as a
ground referenced amplifier (single-ended) or used
with an independent ground reference point.
AMPLIFIER (PGA)
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to “Programmable Gain
Amplifier (PGA)” (DS70005146) in the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
Key features of the PGA module include:
• Single-Ended or Independent Ground Reference
• Selectable Gains: 4x, 8x, 16x, 32x and 64x
• High Gain Bandwidth
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
• Rail-to-Rail Output Voltage
• Wide Input Voltage Range
FIGURE 25-1:
PGAx MODULE BLOCK DIAGRAM
GAIN<2:0> = 6
Gain of 64x
Gain of 32x
GAIN<2:0> = 5
GAIN<2:0> = 4
GAIN<2:0> = 3
Gain of 16x
Gain of 8x
GAIN<2:0> = 2
Gain of 4x
–
PGAx Negative Input
PGAxOUT
AMPx
PGAx Positive Input
+
PGACAL<5:0>
Note 1: x = 1 and 2.
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
input source. To provide an independent ground
reference, the PGAxN2 and PGAxN3 pins are available
as the negative input source to the PGAx module.
25.1 Module Description
The Programmable Gain Amplifiers are used to amplify
small voltages (i.e., voltages across burden/shunt
resistors) to improve the signal-to-noise ratio of the
measured signal. The PGAx output voltage can be
read by any of the four dedicated Sample-and-Hold
circuits on the ADC module. The output voltage can
also be fed to the comparator module for overcurrent/
voltage protection. Figure 25-2 shows a functional
block diagram of the PGAx module. Refer to
Section 22.0 “High-Speed, 12-Bit Analog-to-Digital
Converter (ADC)” and Section 24.0 “High-Speed
Analog Comparator” for more interconnection details.
Note 1: Not all PGA positive/negative inputs are
available on all devices. Refer to the
specific device pinout for available input
source pins.
The output voltage of the PGAx module can be
connected to the DACOUTx pin by setting the
PGAOEN bit in the PGAxCON register. When the
PGAOEN bit is enabled, the output voltage of PGA1 is
connected to DACOUT1 and PGA2 is connected to
DACOUT2. For devices with a single DACOUTx pin,
the output voltage of PGA2 can be connected to
DACOUT1 by configuring the DBCC Configuration bit
in the FDEVOPT register (FDEVOPT<6>).
The gain of the PGAx module is selectable via the
GAIN<2:0> bits in the PGAxCON register. There are
five selectable gains, ranging from 4x to 64x. The
SELPI<2:0> and SELNI<2:0> bits in the PGAxCON
register select one of four positive/negative inputs to
the PGAx module. For single-ended applications, the
SELNI<2:0> bits will select the ground as the negative
If both the DACx output voltage and PGAx output volt-
age are connected to the DACOUTx pin, the resulting
output voltage would be a combination of signals.
There is no assigned priority between the PGAx
module and the DACx module.
FIGURE 25-2:
PGAx FUNCTIONAL BLOCK DIAGRAM
INSEL<1:0>
(CMPCONx)
SELPI<2:0>
(1)
(1)
PGAxCON
PGAxCAL
+
–
PGAEN GAIN<2:0>
(1)
PGAxP1
DACx
(1)
PGAxP2
PGACAL<5:0>
(1)
PGAxP3
CxCHS<1:0>
(ADCON4H)
(1)
PGAxP4
ADC
S&H
+
(1)
PGAx
GND
–
(1)
PGAxN2
(1,3)
PGAxN3
GND
PGAOEN
(2)
SELNI<2:0>
To DACOUTx Pin
Note 1: x = 1 and 2.
2: The DACOUT2 device pin is only available on 64-pin devices.
3: The PGAxN3 input is not available on 28-pin devices.
DS70005258C-page 346
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dsPIC33EPXXXGS70X/80X FAMILY
25.2.1
KEY RESOURCES
25.2 PGA Resources
• “Programmable Gain Amplifier (PGA)”
(DS70005146) in the “dsPIC33/PIC24 Family
Reference Manual”
Many useful resources are provided on the main prod-
uct page of the Microchip website for the devices listed
in this data sheet. This product page contains the latest
updates and additional information.
• Code Samples
• Application Notes
• Software Libraries
• Webinars
• All Related “dsPIC33/PIC24 Family Reference
Manual” Sections
• Development Tools
REGISTER 25-1: PGAxCON: PGAx CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PGAEN
PGAOEN
SELPI2
SELPI1
SELPI0
SELNI2
SELNI1
SELNI0
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
GAIN2
R/W-0
GAIN1
R/W-0
GAIN0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
PGAEN: PGAx Enable bit
1= PGAx module is enabled
0= PGAx module is disabled (reduces power consumption)
bit 14
PGAOEN: PGAx Output Enable bit
1= PGAx output is connected to the DACOUTx pin
0= PGAx output is not connected to the DACOUTx pin
bit 13-11
SELPI<2:0>: PGAx Positive Input Selection bits
111= Reserved
110= Reserved
101= Reserved
100= Reserved
011= PGAxP4
010= PGAxP3
001= PGAxP2
000= PGAxP1
bit 10-8
SELNI<2:0>: PGAx Negative Input Selection bits
111= Reserved
110= Reserved
101= Reserved
100= Reserved
011= Ground (Single-Ended mode)
010= PGAxN3
001= PGAxN2
000= Ground (Single-Ended mode)
bit 7-3
Unimplemented: Read as ‘0’
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REGISTER 25-1: PGAxCON: PGAx CONTROL REGISTER (CONTINUED)
bit 2-0
GAIN<2:0>: PGAx Gain Selection bits
111= Reserved
110= Gain of 64x
101= Gain of 32x
100= Gain of 16x
011= Gain of 8x
010= Gain of 4x
001= Reserved
000= Reserved
REGISTER 25-2: PGAxCAL: PGAx CALIBRATION REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PGACAL<5:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
PGACAL<5:0>: PGAx Offset Calibration bits
The calibration values for PGA1 and PGA2 must be copied from Flash addresses, 0x800E48 and
0x800E4C, respectively, into these bits before the module is enabled. Refer to the calibration data
address table (Table 27-3) in Section 27.0 “Special Features” for more information.
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dsPIC33EPXXXGS70X/80X FAMILY
26.1 Features Overview
26.0 CONSTANT-CURRENT
SOURCE
The constant-current source module offers the following
major features:
Note 1: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended
to be a comprehensive reference source.
To complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Man-
ual”, which is available from the Microchip
website (www.microchip.com).
• Constant-Current Generator (10 µA nominal)
• Internal Selectable Connection to One of Four Pins
• Enable/Disable bit
26.2 Module Description
Figure 26-1 shows a functional block diagram of the
constant-current source module. It consists of a
precision current generator with a nominal value of
10 µA. The module can be enabled and disabled using
the ISRCEN bit in the ISRCCON register. The output
of the current generator is internally connected to a
device pin. The dsPIC33EPXXXGS70X/80X family
can have up to four selectable current source pins.
The OUTSEL<2:0> bits in the ISRCCON register allow
selection of the target pin.
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
Section 4.0 “Memory Organization” in
this data sheet for device-specific register
and bit information.
The constant-current source module is a precision
current generator and is used in conjunction with the
ADC module to measure the resistance of external
resistors connected to device pins.
The current source is calibrated during testing.
FIGURE 26-1:
CONSTANT-CURRENT SOURCE MODULE BLOCK DIAGRAM
Constant-Current Source
ISRC1
ISRC2
M
U
X
ISRC3
ISRC4
ISRCEN
OUTSEL<2:0>
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dsPIC33EPXXXGS70X/80X FAMILY
26.3 Current Source Control Register
REGISTER 26-1: ISRCCON: CONSTANT-CURRENT SOURCE CONTROL REGISTER
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
ISRCEN
OUTSEL2(1) OUTSEL1(1) OUTSEL0(1)
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ISRCCAL0
bit 0
ISRCCAL5 ISRCCAL4 ISRCCAL3
ISRCCAL2
ISRCCAL1
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ISRCEN: Constant-Current Source Enable bit
1= Current source is enabled
0= Current source is disabled
bit 14-11
bit 10-8
Unimplemented: Read as ‘0’
OUTSEL<2:0>: Output Constant-Current Select bits(1)
111= Reserved
110= Reserved
101= Reserved
100= Reserved
011= Input pin, ISRC4 (AN4)
010= Input pin, ISRC3 (AN5)
001= Input pin, ISRC2 (AN6)
000= Input pin, ISRC1 (AN12)
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
ISRCCAL<5:0>: Constant-Current Source Calibration bits
The calibration value must be copied from Flash address, 0x800E78, into these bits before the
module is enabled. Refer to the calibration data address table (Table 27-3) in Section 27.0 “Special
Features” for more information.
Note 1: ISRC1 and ISCR3 are not available on 28, 44 and 48-pin packages. Refer to the “Pin Diagrams” section
for availability.
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dsPIC33EPXXXGS70X/80X FAMILY
27.1 Configuration Bits
27.0 SPECIAL FEATURES
In dsPIC33EPXXXGS70X/80X family devices, the
Configuration Words are implemented as volatile
memory. This means that configuration data must be
programmed each time the device is powered up.
Configuration data is stored at the end of the on-chip
program memory space, known as the Flash Configura-
tion Words. Their specific locations are shown in
Table 27-1 with detailed descriptions in Table 27-2. The
configuration data is automatically loaded from the Flash
Configuration Words to the proper Configuration
Shadow registers during device Resets.
Note: This data sheet summarizes the features of
the dsPIC33EPXXXGS70X/80X family of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Device Configuration” (DS70000618),
“Watchdog Timer and Power-Saving
Modes” (DS70615) and “CodeGuard™
Intermediate Security” (DS70005182) in
the “dsPIC33/PIC24 Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
For devices operating in Dual Partition Flash modes, the
BSEQx bits (FBTSEQ<11:0>) determine which panel is
the Active Partition at start-up and the Configuration
Words from that panel are loaded into the Configuration
Shadow registers.
The dsPIC33EPXXXGS70X/80X family devices
include several features intended to maximize
application flexibility and reliability, and minimize cost
through elimination of external components. These are:
Note:
Configuration data is reloaded on all types
of device Resets.
• Flexible Configuration
• Watchdog Timer (WDT)
When creating applications for these devices, users
should always specifically allocate the location of the
Flash Configuration Words for configuration data in
their code for the compiler. This is to make certain that
program code is not stored in this address when the
code is compiled. Program code executing out of
configuration space will cause a device Reset.
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit Emulation
• Brown-out Reset (BOR)
Note:
Performing a page erase operation on the
last page of program memory clears the
Flash Configuration Words.
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DS70005258C-page 351
TABLE 27-1: CONFIGURATION REGISTER MAP(3)
Device
Memory
Size
Name
Address
Bits 23-16
Bit 15
Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Kbytes)
00AF80
015780
00AF90
015790
00AF90
015794
00AF98
015798
00AF9C
01579C
00AFA0
0157A0
00AFA4
0157A4
00AFA8
0157A8
64
128
64
FSEC
—
—
—
—
—
—
—
—
AIVTDIS
—
—
—
—
—
—
—
—
—
—
—
CSS<2:0>
CWRP
GSS<1:0>
GWRP
—
BSEN
BSS<1:0>
BWRP
FBSLIM
FSIGN
FOSCSEL
FOSC
—
—
BSLIM<12:0>
128
64
Reserved(2)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
128
64
—
—
—
IESO
—
FNOSC<2:0>
128
64
—
PLLKEN
FCKSM<1:0>
IOL1WAY
—
WDTPRE
—
OSCIOFNC
POSCMD<1:0>
128
64
FWDT
FPOR
—
—
WDTWIN<1:0>
WINDIS
WDTEN<1:0>
WDTPOST<3:0>
128
64
—
—
—
—
—
—
—
—
—
—
—
—
JTAGEN
—
—
—
—
—
—
Reserved(1)
128
64
FICD
BTSWP
—
—
Reserved(1)
—
ICS<1:0>
128
64
FDEVOPT 00AFAC
0157AC
—
—
—
—
—
—
DBCC
ALTI2C2 ALTI2C1 Reserved(1)
—
PWMLOCK
128
64
FALTREG 00AFB0
0157B0
CTXT4<2:0>
CTXT3<3:0>
CTXT2 <2:0>
—
CTXT1 <2:0>
128
64
FBTSEQ 00AFFC
IBSEQ<11:0>
—
BSEQ<11:0>
—
0157FC
FBOOT(4) 801000
128
—
—
—
—
—
—
—
—
—
—
—
—
—
—
BTMODE<1:0>
Note 1: These bits are reserved and must be programmed as ‘1’.
2: This bit is reserved and must be programmed as ‘0’.
3: When operating in Dual Partition Flash mode, each partition will have dedicated Configuration registers. On a device Reset, the configuration values of the Active Partition are read at start-up, but during a soft
swap condition, the configuration settings of the newly Active Partition are ignored.
4: FBOOT resides in configuration memory space.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 27-2: CONFIGURATION BITS DESCRIPTION
Bit Field
BSS<1:0>
Description
Boot Segment Code-Protect Level bits
11= Boot Segment is not code-protected other than BWRP
10= Standard security
0x= High security
BSEN
Boot Segment Control bit
1= No Boot Segment is enabled
0= Boot Segment size is determined by the BSLIM<12:0> bits
BWRP
Boot Segment Write-Protect bit
1= Boot Segment can be written
0= Boot Segment is write-protected
BSLIM<12:0>
Boot Segment Flash Page Address Limit bits
Contains the last active Boot Segment page. The value to be programmed is the inverted
page address, such that programming additional ‘0’s can only increase the Boot Segment
size (i.e., 0x1FFD = 2 Pages or 1024 IW).
GSS<1:0>
General Segment Code-Protect Level bits
11= User program memory is not code-protected
10= Standard security
0x= High security
GWRP
General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
CWRP
Configuration Segment Write-Protect bit
1= Configuration data is not write-protected
0= Configuration data is write-protected
CSS<2:0>
Configuration Segment Code-Protect Level bits
111= Configuration data is not code-protected
110= Standard security
10x= Enhanced security
0xx= High security
BTSWP
BOOTSWPInstruction Enable/Disable bit
1= BOOTSWPinstruction is disabled
0= BOOTSWPinstruction is enabled
BSEQ<11:0>
IBSEQ<11:0>
Boot Sequence Number bits (Dual Partition modes only)
Relative value defining which partition will be active after device Reset; the partition
containing a lower boot number will be active.
Inverse Boot Sequence Number bits (Dual Partition modes only)
The one’s complement of BSEQ<11:0>; must be calculated by the user and written for
device programming. If BSEQx and IBSEQx are not complements of each other, the Boot
Sequence Number is considered to be invalid.
AIVTDIS(1)
IESO
Alternate Interrupt Vector Table bit
1= Alternate Interrupt Vector Table is disabled
0= Alternate Interrupt Vector Table is enabled if INTCON2<8> = 1
Two-Speed Oscillator Start-up Enable bit
1= Starts up device with FRC, then automatically switches to the user-selected oscillator
source when ready
0= Starts up device with the user-selected oscillator source
PWMLOCK
PWMx Lock Enable bit
1= Certain PWMx registers may only be written after a key sequence
0= PWMx registers may be written without a key sequence
Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
FNOSC<2:0>
Description
Oscillator Selection bits
111= Fast RC Oscillator with Divide-by-N (FRCDIVN)
110= Fast RC Oscillator with Divide-by-16
101= Low-Power RC Oscillator (LPRC)
100= Reserved; do not use
011= Primary Oscillator with PLL module (XT+PLL, HS+PLL, EC+PLL)
010= Primary Oscillator (XT, HS, EC)
001= Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)
000= Fast RC Oscillator (FRC)
FCKSM<1:0>
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
Peripheral Pin Select Configuration bit
1= Allows only one reconfiguration
0= Allows multiple reconfigurations
OSCIOFNC
POSCMD<1:0>
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is the clock output
0= OSC2 is a general purpose digital I/O pin
Primary Oscillator Mode Select bits
11= Primary Oscillator is disabled
10= HS Crystal Oscillator mode
01= XT Crystal Oscillator mode
00= EC (External Clock) mode
WDTEN<1:0>
Watchdog Timer Enable bits
11= Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the
SWDTEN bit in the RCON register will have no effect)
10= Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by
clearing the SWDTEN bit in the RCON register)
01= Watchdog Timer is enabled only while device is active and is disabled while in Sleep
mode; software control is disabled in this mode
00= Watchdog Timer and SWDTEN bit are disabled
WINDIS
Watchdog Timer Window Enable bit
1= Watchdog Timer is in Non-Window mode
0= Watchdog Timer is in Window mode
PLLKEN
PLL Lock Enable bit
1= PLL lock is enabled
0= PLL lock is disabled
WDTPRE
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
WDTPOST<3:0>
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
•
•
•
0001= 1:2
0000= 1:1
Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.
DS70005258C-page 354
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Description
WDTWIN<1:0>
Watchdog Timer Window Select bits
11= WDT window is 25% of the WDT period
10= WDT window is 37.5% of the WDT period
01= WDT window is 50% of the WDT period
00= WDT window is 75% of the WDT period
ALTI2C1
ALTI2C2
JTAGEN
ICS<1:0>
Alternate I2C1 Pin bit
1= I2C1 is mapped to the SDA1/SCL1 pins
0= I2C1 is mapped to the ASDA1/ASCL1 pins
Alternate I2C2 Pin bit
1= I2C2 is mapped to the SDA2/SCL2 pins
0= I2C2 is mapped to the ASDA2/ASCL2 pins
JTAG Enable bit
1= JTAG is enabled
0= JTAG is disabled
ICD Communication Channel Select bits
11= Communicates on PGEC1 and PGED1
10= Communicates on PGEC2 and PGED2
01= Communicates on PGEC3 and PGED3
00= Reserved, do not use
DBCC
DACx Output Cross Connection Select bit
1= No cross connection between DAC outputs
0= Interconnects DACOUT1 and DACOUT2
CTXT1<2:0>
Alternate Working Register Set 1 Interrupt Priority Level (IPL) Select bits
111= Reserved
110= Assigned to IPL of 7
101= Assigned to IPL of 6
100= Assigned to IPL of 5
011= Assigned to IPL of 4
010= Assigned to IPL of 3
001= Assigned to IPL of 2
000= Assigned to IPL of 1
CTXT2<2:0>
Alternate Working Register Set 2 Interrupt Priority Level (IPL) Select bits
111= Reserved
110= Assigned to IPL of 7
101= Assigned to IPL of 6
100= Assigned to IPL of 5
011= Assigned to IPL of 4
010= Assigned to IPL of 3
001= Assigned to IPL of 2
000= Assigned to IPL of 1
CTXT3<2:0>
Alternate Working Register Set 3 Interrupt Priority Level (IPL) Select bits
111= Reserved
110= Assigned to IPL of 7
101= Assigned to IPL of 6
100= Assigned to IPL of 5
011= Assigned to IPL of 4
010= Assigned to IPL of 3
001= Assigned to IPL of 2
000= Assigned to IPL of 1
Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.
2016-2018 Microchip Technology Inc.
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TABLE 27-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
CTXT4<2:0>
Description
Alternate Working Register Set 4 Interrupt Priority Level (IPL) Select bits
111= Reserved
110= Assigned to IPL of 7
101= Assigned to IPL of 6
100= Assigned to IPL of 5
011= Assigned to IPL of 4
010= Assigned to IPL of 3
001= Assigned to IPL of 2
000= Assigned to IPL of 1
BTMODE<1:0>
Boot Mode Configuration bits
11= Single Partition mode
10= Dual Partition mode
01= Protected Dual Partition mode
00= Privileged Dual Partition mode
Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.
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The dsPIC33EPXXXGS70X/80X devices have two
27.2 Device Calibration and
Identification registers near the end of configuration
memory space that store the Device ID (DEVID) and
Device Revision (DEVREV). These registers are used
to determine the mask, variant and manufacturing
information about the device. These registers are
read-only and are shown in Register 27-1 and
Register 27-2.
Identification
The PGAx and current source modules on the
dsPIC33EPXXXGS70X/80X family devices require
Calibration Data registers to improve performance of
the module over a wide operating range. These
Calibration registers are read-only and are stored in
configuration memory space. Prior to enabling the
module, the calibration data must be read (TBLPAG
and Table Read instruction) and loaded into its respec-
tive SFR registers. The device calibration addresses
are shown in Table 27-3.
TABLE 27-3: DEVICE CALIBRATION ADDRESSES(1)
Calibration
Name
Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PGA1CAL
800E48
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PGA1 Calibration Data
PGA2 Calibration Data
PGA2CAL 800E4C
ISRCCAL 800E78
Current Source Calibration Data
Note 1: The calibration data must be copied into its respective SFR registers prior to enabling the module.
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REGISTER 27-1: DEVID: DEVICE ID REGISTER
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEVID<23:16>
bit 23
bit 15
bit 7
bit 16
bit 8
bit 0
R
R
DEVID<15:8>
R
R
DEVID<7:0>
Legend: R = Read-Only bit
bit 23-0 DEVID<23:0>: Device Identifier bits
U = Unimplemented bit
REGISTER 27-2: DEVREV: DEVICE REVISION REGISTER
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
DEVREV<23:16>
bit 23
bit 15
bit 7
bit 16
bit 8
bit 0
R
R
DEVREV<15:8>
R
R
DEVREV<7:0>
Legend: R = Read-only bit
bit 23-0 DEVREV<23:0>: Device Revision bits
U = Unimplemented bit
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27.3 User OTP Memory
27.5 Brown-out Reset (BOR)
The dsPIC33EPXXXGS70X/80X family devices contain
64 words of user One-Time-Programmable (OTP) mem-
ory, located at addresses, 0x800F80 through 0x800FFC.
The user OTP Words can be used for storing checksum,
code revisions, product information, such as serial
numbers, system manufacturing dates, manufacturing lot
numbers and other application-specific information.
These words can only be written once at program time
and not at run time; they can be read at run time.
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage, VCAP. The main purpose of the
BOR module is to generate a device Reset when a
brown-out condition occurs. Brown-out conditions are
generally caused by glitches on the AC mains (for
example, missing portions of the AC cycle waveform
due to bad power transmission lines or voltage sags
due to excessive current draw when a large inductive
load is turned on).
27.4 On-Chip Voltage Regulator
A BOR generates a Reset pulse which resets the
device. The BOR selects the clock source based on the
device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
All the dsPIC33EPXXXGS70X/80X family devices power
their core digital logic at a nominal 1.8V. This can create
a conflict for designs that are required to operate at a
higher typical voltage, such as 3.3V. To simplify system
design, all devices in the dsPIC33EPXXXGS70X/80X
family incorporate an on-chip regulator that allows the
device to run its core logic from VDD.
If an Oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the Power-up Timer (PWRT) Time-out
(TPWRT) is applied before the internal Reset is released.
If TPWRT = 0and a crystal oscillator is being used, then a
nominal delay of TFSCM is applied. The total delay in this
case is TFSCM. Refer to Parameter SY35 in Table 30-23
of Section 30.0 “Electrical Characteristics” for specific
TFSCM values.
The regulator provides power to the core from the other
VDD pins. A low-ESR (less than 1 Ohm) capacitor (such
as tantalum or ceramic) must be connected to the VCAP
pin (Figure 27-1). This helps to maintain the stability of
the regulator. The recommended value for the filter
capacitor is provided in Table 30-5, located in
Section 30.0 “Electrical Characteristics”.
The BOR status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the VCAP
pin.
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1,2,3)
3.3V
dsPIC33EP
VDD
VCAP
VSS
CEFC
Note 1: These are typical operating voltages. Refer
to Table 30-5 located in Section 30.0
“Electrical Characteristics” for the full
operating ranges of VDD and VCAP.
2: It is important for the low-ESR capacitor
to be placed as close as possible to the
VCAP pin.
3: Typical VCAP pin voltage = 1.8V when
VDD ≥ VDDMIN.
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27.6.2
SLEEP AND IDLE MODES
27.6 Watchdog Timer (WDT)
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes and code execution continues from where the
PWRSAV instruction was executed. The corresponding
SLEEP or IDLE bit (RCON<3:2>) needs to be cleared in
software after the device wakes up.
For dsPIC33EPXXXGS70X/80X family devices, the
WDT is driven by the LPRC oscillator. When the WDT
is enabled, the clock source is also enabled.
27.6.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler that can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration
bit. With a 32 kHz input, the prescaler yields a WDT
Time-out Period (TWDT), as shown in Parameter SY12
in Table 30-23.
27.6.3
ENABLING WDT
The WDT is enabled or disabled by the WDTEN<1:0>
Configuration bits in the FWDT Configuration register.
When the WDTEN<1:0> Configuration bits have been
programmed to ‘0b11’, the WDT is always enabled.
The WDT can be optionally controlled in software
when the WDTEN<1:0> Configuration bits have been
programmed to ‘0b10’. The WDT is enabled in soft-
ware by setting the SWDTEN control bit (RCON<5>).
The SWDTEN control bit is cleared on any device
Reset. The software WDT option allows the user appli-
cation to enable the WDT for critical code segments
and disables the WDT during non-critical segments for
maximum power savings.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the
selection of 16 settings, from 1:1 to 1:32,768. Using the
prescaler and postscaler time-out periods, ranges from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
The WDT Time-out flag bit, WDTO (RCON<4>), is not
automatically cleared following a WDT time-out. To
detect subsequent WDT events, the flag must be
cleared in software.
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSCx bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
27.6.4
WDT WINDOW
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
The Watchdog Timer has an optional Windowed mode,
enabled by programming the WINDIS bit in the WDT
Configuration register (FWDT<7>). In the Windowed
mode (WINDIS = 0), the WDT should be cleared based
on the settings in the programmable Watchdog Timer
Window select bits (WDTWIN<1:0>).
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 27-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPOST<3:0>
WDTPRE
SWDTEN
WDT
Wake-up
WDTEN<1:0>
1
RS
RS
Prescaler
Postscaler
(Divide-by-N1)
(Divide-by-N2)
LPRC Clock
WDT
Reset
0
WINDIS
WDT Window Select
WDTWIN<1:0>
CLRWDTInstruction
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27.7 JTAG Interface
27.10 Code Protection and
CodeGuard™ Security
The dsPIC33EPXXXGS70X/80X family devices imple-
ment a JTAG interface, which supports boundary scan
device testing. Detailed information on this interface is
provided in future revisions of the document.
dsPIC33EPXXXGS70X/80X devices offer multiple levels
of security for protecting individual intellectual property.
The program Flash protection can be broken up into
three segments: Boot Segment (BS), General Segment
(GS) and Configuration Segment (CS). Boot Segment
has the highest security privilege and can be thought to
have limited restrictions when accessing other segments.
General Segment has the least security and is intended
for the end user system code. Configuration Segment
contains only the device user configuration data which is
located at the end of the program memory space.
Note: Refer to “Programming and Diagnostics”
(DS70608) in the “dsPIC33/PIC24 Family
Reference Manual” for further information on
usage, configuration and operation of the
JTAG interface.
27.8
In-Circuit Serial Programming™
(ICSP™)
The code protection features are controlled by the
Configuration registers, FSEC and FBSLIM. The FSEC
register controls the code-protect level for each
segment and if that segment is write-protected. The
size of BS and GS will depend on the BSLIM<12:0> bits
setting and if the Alternate Interrupt Vector Table (AIVT)
is enabled. The BSLIM<12:0> bits define the number of
pages for BS with each page containing 512 IW. The
smallest BS size is one page, which will consist of the
Interrupt Vector Table (IVT) and 256 IW of code
protection.
The dsPIC33EPXXXGS70X/80X family devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data, and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the device just before shipping the
product. Serial programming also allows the most recent
firmware or a custom firmware to be programmed.
Refer to the “dsPIC33E/PIC24E Flash Programming
Specification for Devices with Volatile Configuration
Bits” (DS70663) for details about In-Circuit Serial
Programming™ (ICSP™).
If the AIVT is enabled, the last page of BS will contain
the AIVT and will not contain any BS code. With AIVT
enabled, the smallest BS size is now two pages
(1024 IW), with one page for the IVT and BS code, and
the other page for the AIVT. Write protection of the BS
does not cover the AIVT. The last page of BS can
always be programmed or erased by BS code. The
General Segment will start at the next page and will
consume the rest of program Flash except for the Flash
Configuration Words. The IVT will assume GS security
only if BS is not enabled. The IVT is protected from
being programmed or page erased when either
security segment has enabled write protection.
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
27.9 In-Circuit Debugger
When MPLAB® ICD 3 or REAL ICE™ emulator is
selected as a debugger, the in-circuit debugging function-
ality is enabled. This function allows simple debugging
functions when used with MPLAB IDE. Debugging func-
tionality is controlled through the PGECx (Emulation/
Debug Clock) and PGEDx (Emulation/Debug Data) pin
functions.
Note:
Refer to “CodeGuard™ Intermediate
Security” (DS70005182) in the “dsPIC33/
PIC24 Family Reference Manual” for further
information on usage, configuration and
operation of CodeGuard Security.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In
addition, when the feature is enabled, some of the
resources are not available for general use. These
resources include the first 80 bytes of data RAM and
two I/O pins (PGECx and PGEDx).
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The different device security segments are shown in
Figure 27-3. Here, all three segments are shown but
are not required. If only basic code protection is
required, then GS can be enabled independently or
combined with CS, if desired.
Privileged Dual Partition mode performs the same
function as Protected Dual Partition mode, except
additional constraints are applied in an effort to prevent
code in the Boot Segment and General Segment from
being used against each other.
FIGURE 27-3:
SECURITY SEGMENTS
EXAMPLE FOR
FIGURE 27-4:
SECURITY SEGMENTS
EXAMPLE FOR
dsPIC33EPXXXGS70X/80X
DEVICES
dsPIC33EP64GS70X/80X
DEVICES (DUAL
PARTITION MODES)
0x000000
IVT
0x000000
0x000200
IVT
0x000200
IVT and AIVT
Assume
BS Protection
BS
IVT and AIVT
Assume
BS Protection
BS
(2)
AIVT + 256 IW
(2)
AIVT + 256IW
BSLIM<12:0>
BSLIM<12:0>
GS
GS
(1)
CS
0x0XXX00
(1)
CS
0x005800
Unimplemented
Note 1: If CS is write-protected, the last page
(GS + CS) of program memory will be
protected from an erase condition.
(read ‘0’s)
0x400000
IVT
2: The last half (256 IW) of the last page of
BS is unusable program memory.
0x400200
IVT and AIVT
Assume
BS
BS Protection
dsPIC33EPXXXGS70X/80X family devices can be
operated in Dual Partition mode, where security is
required for each partition. When operating in Dual Par-
tition mode, the Active and Inactive Partitions both
contain unique copies of the Reset vector, Interrupt
Vector Tables (IVT and AIVT, if enabled) and the Flash
Configuration Words. Both partitions have the three
security segments described previously. Code may not
be executed from the Inactive Partition, but it may be
programmed by, and read from, the Active Partition,
subject to defined code protection. Figure 27-4 and
Figure 27-5 show the different security segments for
devices operating in Dual Partition mode.
(2)
AIVT + 256 IW
BSLIM<12:0>
GS
(1)
CS
0x405800
Note 1: If CS is write-protected, the last page
(GS + CS) of program memory will be
protected from an erase condition.
The device may also operate in a Protected Dual
Partition mode or in Privileged Dual Partition mode. In
Protected Dual Partition mode, Partition 1 is perma-
nently erase/write-protected. This implementation
allows for a “Factory Default” mode, which provides a
fail-safe backup image to be stored in Partition 1. For
example, a fail-safe bootloader can be placed in
Partition 1, along with a fail-safe backup code image,
which can be used or rewritten into Partition 2 in the
event of a failed Flash update to Partition 2.
2: The last half (256 IW) of the last page of
BS is unusable program memory.
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FIGURE 27-5:
SECURITY SEGMENTS
EXAMPLE FOR
dsPIC33EP128GS70X/80X
DEVICES (DUAL
PARTITION MODES)
0x000000
IVT
0x000200
IVT and AIVT
Assume
BS Protection
BS
(2)
AIVT + 256IW
BSLIM<12:0>
GS
(1)
CS
0x00AC00
Unimplemented
(read ‘0’s)
0x400000
IVT
0x400200
IVT and AIVT
Assume
BS Protection
BS
(2)
AIVT + 256 IW
BSLIM<12:0>
GS
(1)
CS
0x40AC00
Note 1: If CS is write-protected, the last page
(GS + CS) of program memory will be
protected from an erase condition.
2: The last half (256 IW) of the last page of
BS is unusable program memory.
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NOTES:
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dsPIC33EPXXXGS70X/80X FAMILY
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
28.0 INSTRUCTION SET SUMMARY
Note: This data sheet summarizes the
features of the dsPIC33EPXXXGS70X/
80X family of devices. It is not intended to
be a comprehensive reference source. To
complement the information in this data
sheet, refer to the related section of the
“dsPIC33/PIC24 Family Reference Manual”,
which is available from the Microchip
web site (www.microchip.com).
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
The dsPIC33EP instruction set is almost identical to
that of the dsPIC30F and dsPIC33F.
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The first source operand, which is a register ‘Wb’
without any address modifier
• The second source operand, which is a literal
value
The instruction set is highly orthogonal and is grouped
into five basic categories:
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
The MACclass of DSP instructions can use some of the
following operands:
• DSP operations
• The accumulator (A or B) to be used (required
operand)
• Control operations
Table 28-1 lists the general symbols used in describing
the instructions.
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
The dsPIC33E instruction set summary in Table 28-2
lists all the instructions, along with the status flags
affected by each instruction.
The other DSP instructions do not involve any
multiplication and can include:
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The accumulator to be used (required)
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
The control instructions can use some of the following
operands:
However, word or byte-oriented file register instructions
have two operands:
• A program memory address
• The mode of the Table Read and Table Write
instructions
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
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Most instructions are a single word. Certain double-word
instructions are designed to provide all the required
information in these 48 bits. In the second word, the
eight MSbs are ‘0’s. If this second word is executed as
an instruction (by itself), it executes as a NOP.
these cases, the execution takes multiple instruction
cycles, with the additional instruction cycle(s) executed
as a NOP. Certain instructions that involve skipping over
the subsequent instruction require either two or three
cycles if the skip is performed, depending on whether
the instruction being skipped is a single-word or two-
word instruction. Moreover, double-word moves require
two cycles.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true or the
Program Counter is changed as a result of the
instruction, or a PSV or Table Read is performed. In
Note:
For more details on the instruction set, refer
to the “16-Bit MCU and DSC Programmer’s
Reference Manual” (DS70000157).
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
a {b, c, d}
<n:m>
.b
a is selected from the set of values b, c, d
Register bit field
Byte mode selection
.d
Double-Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator Write-Back Destination Address register {W13, [W13]+ = 2}
4-bit bit selection field (used in word addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0x0000...0x1FFF}
C, DC, N, OV, Z
Expr
f
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal {0...16384}
lit14
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
Field does not require an entry, can be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
Wb
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0...W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor Working register pair (Direct Addressing)
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TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wm
Wm*Wn
Multiplicand and Multiplier Working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
Multiplicand and Multiplier Working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 Working registers {W0...W15}
Wnd
Wns
WREG
Ws
One of 16 Destination Working registers {W0...W15}
One of 16 Source Working registers {W0...W15}
W0 (Working register used in file register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X Data Space Prefetch Address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
Wy
X Data Space Prefetch Destination register for DSP instructions {W4...W7}
Y Data Space Prefetch Address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y Data Space Prefetch Destination register for DSP instructions {W4...W7}
2016-2018 Microchip Technology Inc.
DS70005258C-page 367
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles(1)
1
ADD
ADD
Acc
Add Accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
ADD
f
f = f + WREG
ADD
f,WREG
WREG = f + WREG
ADD
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
ADD
Wd = Wb + Ws
ADD
Wd = Wb + lit5
ADD
16-bit Signed Add to Accumulator
f = f + WREG + (C)
2
3
4
5
ADDC
AND
ADDC
ADDC
ADDC
ADDC
ADDC
AND
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
f = f .AND. WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
AND
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
N,Z
AND
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
N,Z
AND
N,Z
AND
Wd = Wb .AND. lit5
N,Z
ASR
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
ASR
f,WREG
ASR
Ws,Wd
ASR
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
ASR
N,Z
BCLR
BCLR
BCLR
BOOTSWP
None
Bit Clear Ws
None
6
7
BOOTSWP
BRA
Swap the Active and Inactive Program
Flash Space
None
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
C,Expr
Branch if Carry
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
1 (4)
4
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if Greater Than or Equal
Branch if Unsigned Greater Than or Equal
Branch if Greater Than
Branch if Unsigned Greater Than
Branch if Less Than or Equal
Branch if Unsigned Less Than or Equal
Branch if Less Than
Branch if Unsigned Less Than
Branch if Negative
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
Branch if Accumulator A Overflow
Branch if Accumulator B Overflow
Branch if Overflow
Branch if Accumulator A Saturated
Branch if Accumulator B Saturated
Branch Unconditionally
Branch if Zero
Z,Expr
1 (4)
4
Wn
Computed Branch
8
BSET
f,#bit4
Ws,#bit4
Bit Set f
1
Bit Set Ws
1
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005258C-page 368
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles(1)
9
BSW
BSW.C
BSW.Z
BTG
Ws,Wb
Write C bit to Ws<Wb>
1
1
1
1
1
1
1
1
1
None
None
None
None
None
Ws,Wb
Write Z bit to Ws<Wb>
Bit Toggle f
10
11
BTG
f,#bit4
Ws,#bit4
f,#bit4
BTG
Bit Toggle Ws
BTSC
BTSC
Bit Test f, Skip if Clear
1
(2 or 3)
BTSC
BTSS
BTSS
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
1
1
1
None
None
None
(2 or 3)
12
13
BTSS
BTST
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
C
Bit Test Ws to Z
Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
C
Ws,Wb
Z
14
15
16
BTSTS
CALL
CLR
f,#bit4
Z
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call Subroutine
C
Z
CALL
CALL
CALL.L
CLR
lit23
SFA
Wn
Call Indirect Subroutine
Call Indirect Subroutine (long address)
f = 0x0000
SFA
Wn
SFA
f
None
CLR
WREG
WREG = 0x0000
None
CLR
Ws
Ws = 0x0000
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
OA,OB,SA,SB
WDTO,Sleep
17
18
CLRWDT
COM
CLRWDT
COM
COM
f
f = f
1
1
1
1
N,Z
N,Z
f,WREG
WREG = f
COM
CP
Ws,Wd
Wd = Ws
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,Z
19
CP
f
Compare f with WREG
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit8
Compare Wb with lit8
CP
Wb,Ws
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
20
21
CP0
CPB
CP0
CP0
CPB
CPB
CPB
f
Ws
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit8, with Borrow
f
Wb,#lit8
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
22
23
24
25
CPSEQ
CPSEQ
Wb,Wn
Compare Wb with Wn, Skip if =
1
1
None
(2 or 3)
CPBEQ
CPSGT
CPBEQ
CPSGT
Wb,Wn,Expr
Wb,Wn
Compare Wb with Wn, Branch if =
Compare Wb with Wn, Skip if >
1
1
1 (5)
None
None
1
(2 or 3)
CPBGT
CPSLT
CPBGT
CPSLT
Wb,Wn,Expr
Wb,Wn
Compare Wb with Wn, Branch if >
Compare Wb with Wn, Skip if <
1
1
1 (5)
None
None
1
(2 or 3)
CPBLT
CPSNE
CPBLT
CPSNE
Wb,Wn,Expr
Wb,Wn
Compare Wb with Wn, Branch if <
1
1
1 (5)
None
None
Compare Wb with Wn, Skip if
1
(2 or 3)
CPBNE
CPBNE
Wb,Wn,Expr
Compare Wb with Wn, Branch if
1
1 (5)
None
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2016-2018 Microchip Technology Inc.
DS70005258C-page 369
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles(1)
26
CTXTSWP
CTXTSWP #1it3
CTXTSWP Wn
Switch CPU Register Context to Context
Defined by lit3
1
1
2
2
None
None
Switch CPU Register Context to Context
Defined by Wn
27
28
DAW
DEC
DAW
Wn
Wn = Decimal Adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
WREG = f – 1
1
DEC
Wd = Ws – 1
1
29
DEC2
DEC2
DEC2
DEC2
DISI
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
f
f = f – 2
1
f,WREG
Ws,Wd
WREG = f – 2
1
Wd = Ws – 2
1
30
31
DISI
DIV
#lit14
Wm,Wn
Disable Interrupts for k Instruction Cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do Code to PC + Expr, lit15 + 1 Times
Do Code to PC + Expr, (Wn) + 1 Times
Euclidean Distance (no accumulate)
1
18
18
18
18
18
2
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
Wm,Wn
Wm,Wn
Wm,Wn
32
33
DIVF
DO
Wm,Wn
#lit15,Expr
Wn,Expr
Wm*Wm,Acc,Wx,Wy,Wxd
DO
2
None
34
35
ED
ED
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
36
37
38
39
40
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
GOTO.L
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to Address
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
None
C
C
C
None
Wn
Go to Indirect
None
Wn
Go to Indirect (long address)
f = f + 1
None
41
42
43
INC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
44
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
45
46
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link Frame Pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SFA
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f
f = Logical Right Shift f
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Multiply and Accumulate
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
47
MAC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DS70005258C-page 370
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles(1)
48
MOV
MOV
f,Wn
Move f to Wn
Move f to f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
MOV
f
MOV
f,WREG
Move f to WREG
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit Literal to Wn
Move 8-bit Literal to Wn
MOV.b
MOV
Move Wn to f
MOV
Wso,Wdo
WREG,f
Move Ws to Wd
MOV
Move WREG to f
MOV.D
MOV.D
MOVPAG
MOVPAG
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
Move 10-bit Literal to DSRPAG
Move 8-bit Literal to TBLPAG
Move Ws<9:0> to DSRPAG
Move Ws<7:0> to TBLPAG
Prefetch and Store Accumulator
Multiply Wm by Wn to Accumulator
Ws,Wnd
49
MOVPAG
#lit10,DSRPAG
#lit8,TBLPAG
MOVPAGW Ws, DSRPAG
MOVPAGW Ws, TBLPAG
50
51
MOVSAC
MPY
MOVSAC
MPY
Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
OA,OB,OAB,
SA,SB,SAB
MPY
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Square Wm to Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
52
53
MPY.N
MSC
MPY.N
MSC
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
-(Multiply Wm by Wn) to Accumulator
Multiply and Subtract from Accumulator
1
1
1
1
None
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB
OA,OB,OAB,
SA,SB,SAB
54
MUL
MUL.SS
Wb,Ws,Wnd
{Wnd + 1, Wnd} = Signed(Wb) *
Signed(Ws)
1
1
None
MUL.SS
MUL.SU
Wb,Ws,Acc
Wb,Ws,Wnd
Accumulator = Signed(Wb) * Signed(Ws)
1
1
1
1
None
None
{Wnd + 1, Wnd} = Signed(Wb) *
Unsigned(Ws)
MUL.SU
Wb,Ws,Acc
Accumulator = Signed(Wb) *
Unsigned(Ws)
1
1
None
MUL.SU
MUL.US
Wb,#lit5,Acc
Wb,Ws,Wnd
Accumulator = Signed(Wb) * Unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = Unsigned(Wb) *
Signed(Ws)
MUL.US
MUL.UU
MUL.UU
MUL.UU
Wb,Ws,Acc
Wb,Ws,Wnd
Wb,#lit5,Acc
Wb,Ws,Acc
Accumulator = Unsigned(Wb) *
Signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd + 1, Wnd} = Unsigned(Wb) *
Unsigned(Ws)
Accumulator = Unsigned(Wb) *
Unsigned(lit5)
Accumulator = Unsigned(Wb) *
Unsigned(Ws)
MULW.SS Wb,Ws,Wnd
MULW.SU Wb,Ws,Wnd
MULW.US Wb,Ws,Wnd
MULW.UU Wb,Ws,Wnd
Wnd = Signed(Wb) * Signed(Ws)
Wnd = Signed(Wb) * Unsigned(Ws)
Wnd = Unsigned(Wb) * Signed(Ws)
Wnd = Unsigned(Wb) * Unsigned(Ws)
1
1
1
1
1
1
1
1
1
1
None
None
None
None
None
MUL.SU
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = Signed(Wb) *
Unsigned(lit5)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
Wnd = Signed(Wb) * Unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = Unsigned(Wb) *
Unsigned(lit5)
MUL.UU
MUL
Wb,#lit5,Wnd
f
Wnd = Unsigned(Wb) * Unsigned(lit5)
W3:W2 = f * WREG
1
1
1
1
None
None
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2016-2018 Microchip Technology Inc.
DS70005258C-page 371
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles(1)
55
NEG
NEG
Acc
Negate Accumulator
1
1
OA,OB,OAB,
SA,SB,SAB
NEG
NEG
f
f = f + 1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
None
56
57
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
2
All
58
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
None
None
None
PUSH
Wso
Wns
PUSH.D
Push W(ns):W(ns + 1) to Top-of-Stack
(TOS)
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
Push Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
WDTO,Sleep
SFA
59
60
PWRSAV
RCALL
#lit1
Expr
Wn
Go into Sleep or Idle mode
Relative Call
4
Computed Call
4
SFA
61
REPEAT
#lit15
Wn
Repeat Next Instruction lit15 + 1 Times
Repeat Next Instruction (Wn) + 1 Times
Software Device Reset
1
None
None
None
SFA
1
62
63
64
65
66
RESET
RETFIE
RETLW
RETURN
RLC
1
Return from Interrupt
6 (5)
6 (5)
6 (5)
1
#lit10,Wn
Return with Literal in Wn
SFA
Return from Subroutine
SFA
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
Store Accumulator
C,N,Z
C,N,Z
C,N,Z
N,Z
RLC
f,WREG
1
RLC
Ws,Wd
1
67
68
69
70
RLNC
RRC
RLNC
RLNC
RLNC
RRC
f
1
f,WREG
1
N,Z
Ws,Wd
1
N,Z
f
1
C,N,Z
C,N,Z
C,N,Z
N,Z
RRC
f,WREG
1
RRC
Ws,Wd
1
RRNC
SAC
RRNC
RRNC
RRNC
SAC
f
1
f,WREG
1
N,Z
Ws,Wd
1
N,Z
Acc,#Slit4,Wdo
1
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = Sign-Extended Ws
f = 0xFFFF
1
71
72
SE
Ws,Wnd
f
1
SETM
SETM
SETM
SETM
SFTAC
1
WREG
Ws
WREG = 0xFFFF
1
Ws = 0xFFFF
1
73
SFTAC
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
1
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles(1)
74
SL
SL
SL
SL
SL
SL
SUB
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
WREG = Left Shift f
Ws,Wd
Wd = Left Shift Ws
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
N,Z
75
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
f
f = f – WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
SUB
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
Wn = Wn – lit10
SUB
SUB
Wd = Wb – Ws
SUB
Wd = Wb – lit5
76
SUBB
SUBB
SUBB
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
SUBBR
SUBBR
SUBBR
f = f – WREG – (C)
WREG = f – WREG – (C)
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
77
78
SUBR
f,WREG
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = WREG – f
Wd = Ws – Wb
Wd = lit5 – Wb
SUBBR
f = WREG – f – (C)
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
f,WREG
Wb,Ws,Wd
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Wb,#lit5,Wd
Wn
Wd = lit5 – Wb – (C)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
5
5
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
None
None
None
None
None
None
SFA
79
SWAP
Wn = Nibble Swap Wn
Wn = Byte Swap Wn
Wn
80
81
82
83
84
85
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
XOR
f
N,Z
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
Wd = Wb .XOR. Ws
N,Z
XOR
Wd = Wb .XOR. lit5
N,Z
86
ZE
ZE
Wnd = Zero-Extend Ws
C,Z,N
Note 1: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
2016-2018 Microchip Technology Inc.
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NOTES:
DS70005258C-page 374
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
29.1 MPLAB X Integrated Development
Environment Software
29.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers (MCU) and dsPIC® digital
signal controllers (DSC) are supported with a full range
of software and hardware development tools:
The MPLAB X IDE is a single, unified graphical user
interface for Microchip and third-party software, and
hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
MPLAB X IDE is an entirely new IDE with a host of free
software components and plug-ins for high-
performance application development and debugging.
Moving between tools and upgrading from software
simulators to hardware debugging and programming
tools is simple with the seamless user interface.
• Integrated Development Environment
- MPLAB® X IDE Software
• Compilers/Assemblers/Linkers
- MPLAB XC Compiler
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
With complete project management, visual call graphs,
a configurable watch window and a feature-rich editor
that includes code completion and context menus,
MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
multiple projects with simultaneous debugging, MPLAB
X IDE is also suitable for the needs of experienced
users.
• Simulators
- MPLAB X SIM Software Simulator
• Emulators
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers/Programmers
- MPLAB ICD 3
Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
- MPLAB PM3 Device Programmer
• Smart code completion makes suggestions and
provides hints as you type
• Low-Cost Demonstration/Development Boards,
Evaluation Kits and Starter Kits
• Automatic code formatting based on user-defined
rules
• Third-party development tools
• Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker
2016-2018 Microchip Technology Inc.
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29.2 MPLAB XC Compilers
29.4 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB XC Compilers are complete ANSI C
compilers for all of Microchip’s 8, 16 and 32-bit MCU
and DSC devices. These compilers provide powerful
integration capabilities, superior code optimization and
ease of use. MPLAB XC Compilers run on Windows,
Linux or MAC OS X.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler. It can link
relocatable objects from precompiled libraries, using
directives from a linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
debug information that is optimized to the MPLAB X
IDE.
The free MPLAB XC Compiler editions support all
devices and commands, with no time or memory
restrictions, and offer sufficient code optimization for
most applications.
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
MPLAB XC Compilers include an assembler, linker and
utilities. The assembler generates relocatable object
files that can then be archived or linked with other relo-
catable object files and archives to create an execut-
able file. MPLAB XC Compiler uses the assembler to
produce its object file. Notable features of the assem-
bler include:
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
29.5 MPLAB Assembler, Linker and
Librarian for Various Device
Families
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
then be archived or linked with other relocatable object
files and archives to create an executable file. Notable
features of the assembler include:
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
29.3 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command-line interface
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code, and COFF files for
debugging.
• Rich directive set
• Flexible macro language
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process
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29.6 MPLAB X SIM Software Simulator
29.8 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB X SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
The MPLAB ICD 3 In-Circuit Debugger System is
Microchip’s most cost-effective, high-speed hardware
debugger/programmer for Microchip Flash DSC and
MCU devices. It debugs and programs PIC Flash
microcontrollers and dsPIC DSCs with the powerful,
yet easy-to-use graphical user interface of the
MPLAB IDE.
The MPLAB ICD 3 In-Circuit Debugger probe is
connected to the design engineer’s PC using a high-
speed USB 2.0 interface and is connected to the target
with a connector compatible with the MPLAB ICD 2 or
MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
supports all MPLAB ICD 2 headers.
The MPLAB X SIM Software Simulator fully supports
symbolic debugging using the MPLAB XC Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
29.9 PICkit 3 In-Circuit Debugger/
Programmer
The MPLAB PICkit 3 allows debugging and program-
ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineer’s PC using a full-
speed USB interface and can be connected to the
target via a Microchip debug (RJ-11) connector (com-
patible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming™ (ICSP™).
29.7 MPLAB REAL ICE In-Circuit
Emulator System
The MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs all 8, 16 and 32-bit MCU, and DSC devices
with the easy-to-use, powerful graphical user interface of
the MPLAB X IDE.
The emulator is connected to the design engineer’s
PC using a high-speed USB 2.0 interface and is
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11)
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection
(CAT5).
29.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages, and a mod-
ular, detachable socket assembly to support various
package types. The ICSP cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.
The emulator is field upgradable through future firmware
downloads in MPLAB X IDE. MPLAB REAL ICE offers
significant advantages over competitive emulators
including full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, logic
probes, a ruggedized probe interface and long (up to
three meters) interconnection cables.
2016-2018 Microchip Technology Inc.
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29.11 Demonstration/Development
Boards, Evaluation Kits and
Starter Kits
29.12 Third-Party Development Tools
Microchip also offers a great collection of tools from
third-party vendors. These tools are carefully selected
to offer good value and unique functionality.
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide applica-
tion firmware and source code for examination and
modification.
• Device Programmers and Gang Programmers
from companies, such as SoftLog and CCS
• Software Tools from companies, such as Gimpel
and Trace Systems
• Protocol Analyzers from companies, such as
Saleae and Total Phase
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
• Demonstration Boards from companies, such as
MikroElektronika, Digilent® and Olimex
• Embedded Ethernet Solutions from companies,
such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
®
tion software for analog filter design, KEELOQ security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
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dsPIC33EPXXXGS70X/80X FAMILY
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the dsPIC33EPXXXGS70X/80X family electrical characteristics. Additional
information will be provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the dsPIC33EPXXXGS70X/80X family are listed below. Exposure to these maximum
rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any
other conditions above the parameters indicated in the operation listings of this specification, is not implied.
(1)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(3)..................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(3)................................................... -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(3)................................................... -0.3V to +3.6V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................300 mA
Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA
Maximum current sunk/sourced by any 8x I/O pin..................................................................................................25 mA
Maximum current sunk by all ports(2)....................................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those, or any other conditions
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: See the “Pin Diagrams” section for the 5V tolerant pins.
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30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS vs. VOLTAGE
Maximum MIPS
VDD Range
(in Volts)
Temperature Range
(in °C)
Characteristic
dsPIC33EPXXXGS70X/80X Family
—
—
3.0V to 3.6V(1)
3.0V to 3.6V(1)
-40°C to +85°C
-40°C to +125°C
70
60
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators)
may have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
TABLE 30-2: THERMAL OPERATING CONDITIONS
Rating
Industrial Temperature Devices
Symbol
Min.
Typ.
Max.
Unit
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Extended Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ.
Max.
Unit
Notes
Package Thermal Resistance, 80-Pin TQFP 12x12x1 mm
Package Thermal Resistance, 64-Pin TQFP 10x10x1 mm
Package Thermal Resistance, 48-Pin TQFP 7x7x1 mm
Package Thermal Resistance, 44-Pin QFN 8x8 mm
Package Thermal Resistance, 44-Pin TQFP 10x10x1 mm
Package Thermal Resistance, 28-Pin QFN-S 6x6x0.9 mm
Package Thermal Resistance, 28-Pin UQFN 6x6x0.55 mm
Package Thermal Resistance, 28-Pin SOIC 7.50 mm
JA
JA
JA
JA
JA
JA
JA
JA
53.0
49.0
63.0
29.0
50.0
30.0
26.0
70.0
—
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
Operating Voltage
DC10
DC12
VDD
VDR
Supply Voltage
RAM Retention Voltage(2)
3.0
—
—
—
—
—
—
—
3.6
1.95
2.0
V
V
V
V
+25°C, +85°C, +125°C
-40°C
DC16
DC17
VPOR
SVDD
VDD Start Voltage
to Ensure Internal
Power-on Reset Signal
VSS
VDD Rise Rate
1.0
—
—
V/ms 0V-3V in 3 ms
to Ensure Internal
Power-on Reset Signal
Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators) may
have degraded performance. Device functionality is tested but not characterized. Refer to
Parameter BO10 in Table 30-13 for the minimum and maximum BOR values.
2: This is the limit to which VDD may be lowered and the RAM contents will always be retained.
TABLE 30-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristics
Min.
Typ.
Max.
Units
Comments
CEFC
External Filter Capacitor
Value(1)
4.7
—
10
F
Capacitor must have a low
series resistance (<1 Ohm)
Note 1: Typical VCAP Voltage = 1.8 volts when VDD VDDMIN.
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TABLE 30-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Parameter
Typ.
Max.
Units
Conditions
No.
Operating Current (IDD)(1)
DC20d
DC20a
DC20b
DC20c
DC22d
DC22a
DC22b
DC22c
DC24d
DC24a
DC24b
DC24c
DC25d
DC25a
DC25b
DC25c
DC26d
DC26a
DC26b
DC27d
DC27a
DC27b
8
13
13
13
13
20
20
20
20
30
30
30
30
42
42
42
42
46
46
46
75
75
75
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
8
3.3V
3.3V
3.3V
3.3V
10 MIPS
20 MIPS
40 MIPS
8
8
12
12
12
12
19
19
19
19
27
27
27
27
30
30
30
57
57
57
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
60 MIPS
70 MIPS
+25°C
+85°C
-40°C
3.3V
3.3V
70 MIPS
(Note 2)
+25°C
+85°C
Note 1: IDD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDD measurements are as follows:
• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from
rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
• CLKO is configured as an I/O input pin in the Configuration Word
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD, WDT and FSCM are disabled
• CPU, SRAM, program memory and data memory are operational
• No peripheral modules are operating or being clocked (all defined PMDx bits are set)
• CPU is executing while(1)statement
• JTAG is disabled
2: For this specification, the following test conditions apply:
• APLL clock is enabled
• All 8 PWMs enabled and operating at maximum speed (PTCON2<2:0> = 000), PTPER = 1000h,
50% duty cycle
• All other peripherals are disabled (corresponding PMDx bits are set)
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TABLE 30-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Parameter
Typ.
Max.
Units
Conditions
No.
Idle Current (IIDLE)(1)
DC40d
DC40a
DC40b
DC40c
DC42d
DC42a
DC42b
DC42c
DC44d
DC44a
DC44b
DC44c
DC45d
DC45a
DC45b
DC45c
DC46d
DC46a
DC46b
2
2
4
4
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
10 MIPS
20 MIPS
40 MIPS
2
4
2
4
3
6
3
6
+25°C
+85°C
+125°C
-40°C
4
7
4
7
6
12
12
12
12
17
17
17
17
20
20
20
6
+25°C
+85°C
+125°C
-40°C
6
6
9
9
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
60 MIPS
70 MIPS
9
9
10
10
10
+25°C
+85°C
Note 1: Base Idle current (IIDLE) is measured as follows:
•
CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
•
•
•
•
•
CLKO is configured as an I/O input pin in the Configuration Word
All I/O pins are configured as inputs and pulled to VSS
MCLR = VDD, WDT and FSCM are disabled
No peripheral modules are operating or being clocked (all defined PMDx bits are set)
The NVMSIDL bit (NVMCON<12>) = 1(i.e., Flash regulator is set to standby while the device is in Idle
mode)
•
•
The VREGSF bit (RCON<11>) = 0(i.e., Flash regulator is set to standby while the device is in Sleep mode)
JTAG is disabled
2016-2018 Microchip Technology Inc.
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TABLE 30-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Parameter
Typ.
Max.
Units
Conditions
No.
Power-Down Current (IPD)(1)
DC60d
DC60a
DC60b
DC60c
15
20
110
150
A
A
A
A
-40°C
+25°C
+85°C
+125°C
3.3V
150
500
500
1200
Note 1: IPD (Sleep) current is measured as follows:
•
CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with
external square wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
CLKO is configured as an I/O input pin in the Configuration Word
All I/O pins are configured as inputs and pulled to VSS
MCLR = VDD, WDT and FSCM are disabled
All peripheral modules are disabled (PMDx bits are all set)
The VREGS bit (RCON<8>) = 0(i.e., core regulator is set to standby while the device is in Sleep mode)
The VREGSF bit (RCON<11>) = 0(i.e., Flash regulator is set to standby while the device is in Sleep mode)
JTAG is disabled
•
•
•
•
•
•
•
TABLE 30-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT)(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Parameter No.
Typ.
Max.
Units
Conditions
DC61d
DC61a
DC61b
DC61c
1
1
2
2
10
10
17
20
A
A
A
A
-40°C
+25°C
+85°C
+125°C
3.3V
Note 1: The IWDT current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current. All parameters are characterized but not tested during manufacturing.
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TABLE 30-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Doze
Ratio
Parameter No.
Typ.
Max.
Units
Conditions
Doze Current (IDOZE)(1)
DC73a(2)
DC73g
20
10
20
10
20
10
20
10
40
22
40
22
40
22
40
22
1:2
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
3.3V
FOSC = 140 MHz
FOSC = 140 MHz
FOSC = 140 MHz
FOSC = 120 MHz
DC70a(2)
3.3V
3.3V
3.3V
DC70g
1:128
1:2
DC71a(2)
DC71g
DC72a(2)
1:128
1:2
DC72g
1:128
Note 1: IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading
and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact
on the current consumption. The test conditions for all IDOZE measurements are as follows:
•
Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square
wave from rail-to-rail (EC clock overshoot/undershoot < 250 mV required)
•
•
•
•
•
•
•
CLKO is configured as an I/O input pin in the Configuration Word
All I/O pins are configured as inputs and pulled to VSS
MCLR = VDD, WDT and FSCM are disabled
CPU, SRAM, program memory and data memory are operational
No peripheral modules are operating or being clocked (all defined PMDx bits are set)
CPU is executing while(1)statement
JTAG is disabled
2: These parameter are characterized but not tested in manufacturing.
2016-2018 Microchip Technology Inc.
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TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Input Low Voltage
Min.
Typ.(1) Max.
Units
Conditions
VIL
DI10
DI18
DI19
Any I/O Pin and MCLR
I/O Pins with SDAx, SCLx
I/O Pins with SDAx, SCLx
Input High Voltage
VSS
VSS
VSS
—
—
—
0.2 VDD
0.3 VDD
0.8
V
V
V
SMBus disabled
SMBus enabled
VIH
DI20
I/O Pins Not 5V Tolerant(4)
0.8 VDD
0.8 VDD
—
—
VDD
5.5
V
V
I/O Pins 5V Tolerant and
MCLR(4)
5V Tolerant I/O Pins with
SDAx, SCLx(4)
0.8 VDD
2.1
—
—
5.5
5.5
V
V
SMBus disabled
5V Tolerant I/O Pins with
SDAx, SCLx(4)
SMBus enabled
I/O Pins with SDAx, SCLx Not 0.8 VDD
5V Tolerant(4)
—
VDD
VDD
550
400
V
SMBus disabled
I/O Pins with SDAx, SCLx Not
5V Tolerant(4)
2.1
100
100
—
V
SMBus enabled
DI30
DI31
ICNPU
ICNPD
Input Change Notification
Pull-up Current
230
230
A
A
VDD = 3.3V, VPIN = VSS
VDD = 3.3V, VPIN = VDD
Input Change Notification
Pull-Down Current(5)
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
5: VIL Source < (VSS – 0.3). Characterized but not tested.
6: VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
7: Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
8: | Injection Currents | > 0 can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
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TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ.(1) Max.
Units
Conditions
IIL
Input Leakage Current(2,3)
DI50
DI51
I/O Pins 5V Tolerant(4)
-1
-1
—
—
+1
+1
A
A
VSS VPIN VDD,
pin at high-impedance
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
VSS VPIN VDD,
pin at high-impedance,
-40°C TA +85°C
DI51a
DI51b
DI51c
-1
-1
-1
—
—
—
+1
+1
+1
A
A
A
Analog pins shared with
external reference pins,
-40°C TA +85°C
VSS VPIN VDD,
pin at high-impedance,
-40°C TA +125°C
Analog pins shared with
external reference pins,
-40°C TA +125°C
DI55
DI56
MCLR
OSC1
-5
-5
—
—
+5
+5
A
A
VSS VPIN VDD
VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
5: VIL Source < (VSS – 0.3). Characterized but not tested.
6: VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
7: Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
8: | Injection Currents | > 0 can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
2016-2018 Microchip Technology Inc.
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TABLE 30-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ.(1) Max.
Units
Conditions
DI60a IICL
Input Low Injection Current
0
—
-5(5,8)
mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP
and RB7
DI60b IICH
Input High Injection Current
0
—
+5(6,7,8)
mA All pins except VDD, VSS,
AVDD, AVSS, MCLR, VCAP,
RB7 and all 5V tolerant
pins(7)
DI60c IICT
Total Input Injection Current
(sum of all I/O and control
pins)
-20(9)
—
+20(9)
mA Absolute instantaneous
sum of all ± input injection
currents from all I/O pins
( | IICL | + | IICH | ) IICT
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.
5: VIL Source < (VSS – 0.3). Characterized but not tested.
6: VIH Source > (VDD + 0.3) for pins that are not 5V tolerant only.
7: Digital 5V tolerant pins do not have internal high-side diodes to VDD and cannot tolerate any “positive”
input injection current.
8: | Injection Currents | > 0 can affect the ADC results by approximately 4-6 counts.
9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted
provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not
exceed the specified limit. Characterized but not tested.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param. Symbol
Characteristic
Min.
Typ.
Max. Units
Conditions
DO10 VOL
Output Low Voltage
—
—
0.4
0.4
V
V
VDD = 3.3V,
IOL 6 mA, -40°C TA +85°C,
IOL 5 mA, +85°C TA +125°C
4x Sink Driver Pins(2)
Output Low Voltage
—
—
VDD = 3.3V,
IOL 12 mA, -40°C TA +85°C,
IOL 8 mA, +85°C TA +125°C
8x Sink Driver Pins(3)
DO20 VOH
DO20A VOH1
Output High Voltage
2.4
2.4
—
—
—
—
V
V
V
IOH -10 mA, VDD = 3.3V
4x Source Driver Pins(2)
Output High Voltage
IOH -15 mA, VDD = 3.3V
8x Source Driver Pins(3)
Output High Voltage
1.5(1)
2.0(1)
3.0(1)
1.5(1)
2.0(1)
3.0(1)
—
—
—
—
—
—
—
—
—
—
—
—
IOH -14 mA, VDD = 3.3V
IOH -12 mA, VDD = 3.3V
IOH -7 mA, VDD = 3.3V
IOH -22 mA, VDD = 3.3V
IOH -18 mA, VDD = 3.3V
IOH -10 mA, VDD = 3.3V
4x Source Driver Pins(2)
Output High Voltage
V
8x Source Driver Pins(3)
Note 1: Parameters are characterized but not tested.
2: Includes RA0-RA2, RB0-RB1, RB9, RC1-RC2, RC9-RC10, RC12, RD7, RD8, RE4-RE5, RE8-RE9 and
RE12-RE13 pins.
3: Includes all I/O pins that are not 4x driver pins (see Note 2).
TABLE 30-13: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.(2)
Typ.
Max.
Units
Conditions
BO10
VBOR
BOR Event on VDD Transition
High-to-Low
2.65
—
2.95
V
VDD (Notes 2 and 3)
Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality
is tested, but not characterized. Analog modules (ADC, PGAs and comparators) may have degraded
performance.
2: Parameters are for design guidance only and are not tested in manufacturing.
3: The VBOR specification is relative to VDD.
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TABLE 30-14: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min. Typ.(1) Max. Units
Conditions
Program Flash Memory
Cell Endurance
D130
D131
EP
10,000
3.0
—
—
—
—
—
3.6
3.6
—
E/W -40C to +125C
VPR
VDD for Read
V
V
D132b VPEW
VDD for Self-Timed Write
Characteristic Retention
3.0
D134
D135
D136
TRETD
20
Year Provided no other specifications
are violated, -40C to +125C
IDDP
Supply Current during
Programming(2)
—
10
—
—
—
—
—
—
—
—
mA
mA
IPEAK
Instantaneous Peak Current
During Start-up
—
150
20.1
20.3
47.3
47.9
679
687
D137a TPE
D137b TPE
D138a TWW
D138b TWW
D139a TRW
D139b TRW
Page Erase Time
Page Erase Time
Word Write Cycle Time
Word Write Cycle Time
Row Write Time
19.7
19.5
46.5
46.0
667
660
ms TPE = 146893 FRC cycles,
TA = +85°C (Note 3)
ms TPE = 146893 FRC cycles,
TA = +125°C (Note 3)
µs TWW = 346 FRC cycles,
TA = +85°C (Note 3)
µs TWW = 346 FRC cycles,
TA = +125°C (Note 3)
µs TRW = 4965 FRC cycles,
TA = +85°C (Note 3)
Row Write Time
µs TRW = 4965 FRC cycles,
TA = +125°C (Note 3)
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: Parameter characterized but not tested in manufacturing.
3: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 011111(for Minimum), TUN<5:0> = 100000(for
Maximum). This parameter depends on the FRC accuracy (see Table 30-20) and the value of the FRC
Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and
Maximum time, see Section 5.3 “Programming Operations”.
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dsPIC33EPXXXGS70X/80X FAMILY
30.2 AC Characteristics and Timing
Parameters
This section defines the dsPIC33EPXXXGS70X/80X
family AC characteristics and timing parameters.
TABLE 30-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 30.1 “DC Characteristics”.
FIGURE 30-1:
Load Condition 1 – for all pins except OSC2
VDD/2
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 30-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min.
Typ. Max. Units
Conditions
No.
DO50 COSCO
OSC2 Pin
—
—
15
pF In XT and HS modes, when
external clock is used to drive
OSC1
DO56 CIO
DO58 CB
All I/O Pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C mode
400
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FIGURE 30-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
OS20
OS30 OS30
OS31 OS31
OS25
CLKO
OS41
OS40
TABLE 30-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Sym
No.
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
60
MHz EC
Oscillator Crystal Frequency
3.5
10
—
—
10
40
MHz XT
MHz HS
OS20
OS25
TOSC
TCY
TOSC = 1/FOSC
8.33
7.14
—
—
—
—
—
DC
DC
ns
ns
ns
ns
ns
+125°C
TOSC = 1/FOSC
+85°C
+125°C
+85°C
EC
Instruction Cycle Time(2)
Instruction Cycle Time(2)
16.67
DC
14.28
DC
OS30
OS31
TosL, External Clock in (OSC1)
TosH High or Low Time
0.45 x TOSC
0.55 x TOSC
TosR, External Clock in (OSC1)
TosF Rise or Fall Time
—
—
20
ns
EC
OS40
OS41
OS42
TckR CLKO Rise Time(3,4)
—
—
—
5.2
5.2
12
—
—
—
ns
ns
TckF
GM
CLKO Fall Time(3,4)
External Oscillator
mA/V HS, VDD = 3.3V,
TA = +25°C
Transconductance(4)
—
6
—
mA/V XT, VDD = 3.3V,
TA = +25°C
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values
are based on characterization data for that particular oscillator type, under standard operating conditions,
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at
“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,
the “Maximum” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: This parameter is characterized but not tested in manufacturing.
DS70005258C-page 392
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-18: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled Oscillator
(VCO) Input Frequency Range
0.8
—
8.0
MHz ECPLL, XTPLL modes
OS51
OS52
OS53
FVCO
TLOCK
DCLK
On-Chip VCO System Frequency 120
—
340
3.1
3
MHz
ms
%
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)(2)
0.9
-3
1.5
0.5
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for
individual time bases, or communication clocks used by the application, use the following formula:
DCLK
Effective Jitter = -------------------------------------------------------------------------------------------
FOSC
--------------------------------------------------------------------------------------
Time Base or Communication Clock
For example, if FOSC = 120 MHz and the SPIx bit rate = 10 MHz, the effective jitter is as follows:
DCLK
DCLK
DCLK
3.464
Effective Jitter = ------------- = ------------- = -------------
120
--------
10
12
TABLE 30-19: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS56
OS57
OS58
FHPOUT On-Chip 16x PLL CCO
Frequency
112
118
120
MHz
FHPIN
On-Chip 16x PLL Phase
Detector Input Frequency
7.0
—
7.37
—
7.5
10
MHz
µs
TSU
Frequency Generator Lock
Time
Note 1: Data in “Typ” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested in manufacturing.
2016-2018 Microchip Technology Inc.
DS70005258C-page 393
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TABLE 30-20: INTERNAL FRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Characteristic
Min.
Typ.
Max.
Units
Conditions
No.
Internal FRC Accuracy @ FRC Frequency = 7.37 MHz(1)
F20a
FRC
-2
-0.9
-2
0.5
0.5
1
+2
+0.9
+2
%
%
%
-40°C TA -10°C
-10°C TA +85°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
F20b
FRC
+85°C TA +125°C VDD = 3.0-3.6V
Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.
TABLE 30-21: INTERNAL LPRC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Characteristic
Min.
Typ.
Max.
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a LPRC
-30
-20
-30
—
—
—
+30
+20
+30
%
%
%
-40°C TA -10°C
-10°C TA +85°C
VDD = 3.0-3.6V
VDD = 3.0-3.6V
F21b LPRC
+85°C TA +125°C VDD = 3.0-3.6V
Note 1: This is the change of the LPRC frequency as VDD changes.
DS70005258C-page 394
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-3:
I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
Old Value
New Value
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-22: I/O TIMING REQUIREMENTS
AC CHARACTERISTICS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
DO31
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
20
2
5
5
10
10
—
—
ns
ns
DO32
DI35
DI40
Port Output Fall Time
INTx Pin High or Low Time (input)
CNx High or Low Time (input)
—
—
ns
TCY
Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
FIGURE 30-4:
BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS
MCLR
TMCLR
(SY20)
BOR
TBOR
Various Delays (depending on configuration)
(SY30)
Reset Sequence
CPU Starts Fetching Code
2016-2018 Microchip Technology Inc.
DS70005258C-page 395
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TABLE 30-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Power-up Period
Min.
Typ.(2)
Max. Units
Conditions
SY00 TPU
SY10 TOST
SY12 TWDT
—
—
400
1024 TOSC
—
600
—
µs
—
Oscillator Start-up Time
TOSC = OSC1 period
Watchdog Timer
Time-out Period
0.81
1.22 ms WDTPRE = 0,
WDTPOST<3:0> = 0000,
using LPRC tolerances indicated in
F21 (see Table 30-21) at +85°C
3.25
0.68
—
4.88 ms WDTPRE = 1,
WDTPOST<3:0> = 0000,
using LPRC tolerances indicated in
F21 (see Table 30-21) at +85°C
SY13 TIOZ
I/O High-Impedance from
MCLR Low or Watchdog
Timer Reset
0.72
1.2
µs
SY20 TMCLR
SY30 TBOR
SY35 TFSCM
MCLR Pulse Width (low)
BOR Pulse Width (low)
2
1
—
—
—
—
µs
µs
Fail-Safe Clock Monitor
Delay
—
500
900
µs -40°C to +85°C
SY36 TVREG
Voltage Regulator
Standby-to-Active mode
Transition Time
—
—
30
µs
SY37 TOSCDFRC FRC Oscillator Start-up
Delay
—
—
48
—
—
µs
µs
SY38 TOSCDLPRC LPRC Oscillator Start-up
Delay
70
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.
DS70005258C-page 396
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-5:
TIMER1-TIMER5 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx10
Tx11
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(2)
Min.
Typ.
Max.
Units
Conditions
TA10 TTXH
TA11 TTXL
T1CK High Synchronous mode
Time
Greater of:
20 or
(TCY + 20)/N
—
—
ns Must also meet
Parameter TA15,
N = Prescale Value
(1, 8, 64, 256)
Asynchronous mode
35
—
—
—
—
ns
T1CK Low Synchronous mode
Time
Greater of:
20 or
(TCY + 20)/N
ns Must also meet
Parameter TA15,
N = Prescale Value
(1, 8, 64, 256)
Asynchronous mode
10
—
—
—
—
ns
TA15 TTXP
OS60 Ft1
T1CK Input Synchronous mode
Period
Greater of:
40 or
ns N = Prescale Value
(1, 8, 64, 256)
(2 TCY + 40)/N
T1CK Oscillator Input Frequency
Range (oscillator enabled by
setting bit, TCS (T1CON<1>))
DC
—
—
50
kHz
TA20 TCKEXTMRL Delay from External T1CK Clock 0.75 TCY + 40
Edge to Timer Increment
1.75 TCY + 40 ns
Note 1: Timer1 is a Type A timer.
2: These parameters are characterized but not tested in manufacturing.
2016-2018 Microchip Technology Inc.
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TABLE 30-25: TIMER2 AND TIMER4 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TB10 TtxH
TB11 TtxL
TB15 TtxP
TxCK High Synchronous mode Greater of:
—
—
ns Must also meet
Parameter TB15,
N = Prescale Value
(1, 8, 64, 256)
Time
20 or
(TCY + 20)/N
TxCK Low Synchronous mode Greater of:
—
—
ns Must also meet
Parameter TB15,
N = Prescale Value
(1, 8, 64, 256)
Time
20 or
(TCY + 20)/N
TxCK Input Synchronous mode Greater of:
—
—
—
ns N = Prescale Value
(1, 8, 64, 256)
Period
40 or
(2 TCY + 40)/N
TB20 TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
0.75 TCY + 40
1.75 TCY + 40
ns
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 30-26: TIMER3 AND TIMER5 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TtxH
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
TC10
TxCK High
Synchronous
Synchronous
TCY + 20
—
—
ns
Must also meet
Parameter TC15
Time
TC11
TC15
TC20
TtxL
TtxP
TxCK Low
Time
TCY + 20
2 TCY + 40
0.75 TCY + 40
—
—
—
—
—
ns
ns
ns
Must also meet
Parameter TC15
TxCK Input
Period
Synchronous
with Prescaler
N = Prescale Value
(1, 8, 64, 256)
TCKEXTMRL Delay from External TxCK
Clock Edge to Timer Increment
1.75 TCY + 40
Note 1: These parameters are characterized but not tested in manufacturing.
DS70005258C-page 398
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-6:
INPUT CAPTURE x (ICx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-27: INPUT CAPTURE x MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param.
No.
Symbol Characteristics(1)
Min.
Max.
Units
Conditions
IC10
TCCL
TCCH
TCCP
ICx Input Low Time
ICx Input High Time
ICx Input Period
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
ns
Must also meet
Parameter IC15
IC11
IC15
Greater of:
12.5 + 25 or
(0.5 TCY/N) + 25
—
—
ns
ns
Must also meet
Parameter IC15
N = Prescale Value
(1, 4, 16)
Greater of:
25 + 50 or
(1 TCY/N) + 50
Note 1: These parameters are characterized but not tested in manufacturing.
2016-2018 Microchip Technology Inc.
DS70005258C-page 399
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-7:
OUTPUT COMPARE x MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC11
Note: Refer to Figure 30-1 for load conditions.
OC10
TABLE 30-28: OUTPUT COMPARE x MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See Parameter DO32
See Parameter DO31
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 30-8:
OCx/PWMx MODULE TIMING CHARACTERISTICS
OC20
OCFA
OCx
OC15
TABLE 30-29: OCx/PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
OC15
OC20
TFD
Fault Input to PWMx I/O Change
Fault Input Pulse Width
—
—
—
TCY + 20
—
ns
ns
TFLT
TCY + 20
Note 1: These parameters are characterized but not tested in manufacturing.
DS70005258C-page 400
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-9:
HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS
MP30
Fault Input
(active-low)
MP20
PWMx
FIGURE 30-10:
HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS
MP11 MP10
PWMx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.
Max.
Units
Conditions
MP10
MP11
MP20
TFPWM
TRPWM
TFD
PWMx Output Fall Time
PWMx Output Rise Time
—
—
—
—
—
—
—
—
15
ns
ns
ns
See Parameter DO32
See Parameter DO31
Fault Input to PWMx
I/O Change
MP30
TFH
Fault Input Pulse Width
15
—
—
ns
Note 1: These parameters are characterized but not tested in manufacturing.
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-31: SPI1, SPI2 AND SPI3 MAXIMUM DATA/CLOCK RATE SUMMARY(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Master
Transmit Only
(Half-Duplex)
Master
Slave
Maximum
Data Rate
Transmit/Receive Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
(Full-Duplex)
15 MHz
9 MHz
Table 30-32
—
—
0,1
1
0,1
0,1
0,1
0
0,1
1
—
—
—
—
—
—
Table 30-33
—
9 MHz
Table 30-34
—
0
1
15 MHz
11 MHz
15 MHz
11 MHz
—
—
—
—
Table 30-35
Table 30-36
Table 30-37
Table 30-38
1
0
1
1
0
0
1
0
0
0
0
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
FIGURE 30-11:
SPI1, SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY,
CKE = 0) TIMING CHARACTERISTICS(1,2)
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
Bit 14 - - - - - -1
LSb
SDOx
SP30, SP31
SP30, SP31
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices with
a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 402
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-12:
SPI1, SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY,
CKE = 1) TIMING CHARACTERISTICS(1,2)
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35
MSb
Bit 14 - - - - - -1
LSb
SDOx
SP30, SP31
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
TABLE 30-32: SPI1, SPI2 AND SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max.
Units
Conditions
SP10
SP20
FscP
TscF
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
15
—
MHz (Note 3)
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP21
SP30
SP31
SP35
SP36
TscR
TdoF
TdoR
SCKx Output Rise Time
—
—
—
—
30
—
—
—
6
—
—
—
20
—
See Parameter DO31
(Note 4)
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See Parameter DO32
(Note 4)
See Parameter DO31
(Note 4)
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
TdiV2scH, SDOx Data Output Setup to
—
TdiV2scL
First SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 403
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-13:
SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x,
SMP = 1) TIMING CHARACTERISTICS(1,2)
SP36
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP21
MSb
Bit 14 - - - - - -1
SP30, SP31
LSb
SDOx
SDIx
SP40
MSb In
SP41
Bit 14 - - - -1
LSb In
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05
devices with a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
TABLE 30-33: SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param.
Symbol
FscP
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10
SP20
SP21
SP30
SP31
SP35
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
—
—
—
—
—
—
—
6
9
MHz (Note 3)
TscF
TscR
TdoF
TdoR
—
—
—
—
20
ns
ns
ns
ns
ns
See Parameter DO32 (Note 4)
See Parameter DO31 (Note 4)
See Parameter DO32 (Note 4)
See Parameter DO31 (Note 4)
SCKx Output Rise Time
SDOx Data Output Fall Time
SDOx Data Output Rise Time
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP36
SP40
SP41
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
30
30
—
—
—
—
—
—
ns
ns
ns
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
DS70005258C-page 404
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-14:
SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x,
SMP = 1) TIMING CHARACTERISTICS(1,2)
SCKx
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCKx
(CKP = 1)
SP35 SP36
MSb
Bit 14 - - - - - -1
LSb
SDOx
SDIx
SP30, SP31
SP30, SP31
LSb In
MSb In
SP40 SP41
Bit 14 - - - -1
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices with
a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
TABLE 30-34: SPI1, SPI2 AND SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param.
Symbol
FscP
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
MHz -40ºC to +125ºC (Note 3)
SP10
SP20
SP21
SP30
SP31
SP35
Maximum SCKx Frequency
SCKx Output Fall Time
—
—
—
—
—
—
—
—
—
—
—
6
9
TscF
TscR
TdoF
TdoR
—
—
—
—
20
ns
ns
ns
ns
ns
See Parameter DO32 (Note 4)
See Parameter DO31 (Note 4)
See Parameter DO32 (Note 4)
See Parameter DO31 (Note 4)
SCKx Output Rise Time
SDOx Data Output Fall Time
SDOx Data Output Rise Time
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
SP36
SP40
SP41
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
30
30
—
—
—
—
—
—
ns
ns
ns
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 405
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-15:
SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SCKx
(CKP = 1)
SP36
SP72
SP73
SP35
SDOx
SDIx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices with
a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 406
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-35: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SP60
TscR
TdoF
TdoR
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
50
See Parameter DO31
(Note 4)
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
TssL2scH, SSx to SCKx or SCKx
TssL2scL Input
to SCKx Edge
30
120
TssH2doZ SSx to SDOx Output
10
1.5 TCY + 40
—
(Note 4)
(Note 4)
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 407
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-16:
SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP73
SP72
SP70
SCKx
(CKP = 1)
SP36
SP35
SP72
SP73
SDOx
SDIx
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices with
a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 408
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-36: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
11
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SP60
TscR
TdoF
TdoR
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
50
See Parameter DO31
(Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
TssL2scH, SSx to SCKx or SCKx
TssL2scL Input
to SCKx Edge
30
120
TssH2doZ SSx to SDOx Output
10
1.5 TCY + 40
—
(Note 4)
(Note 4)
High-Impedance
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 409
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-17:
SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35 SP36
SDOx
SDIx
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 410
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-37: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
TscR
TdoF
TdoR
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
See Parameter DO31
(Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
TssL2scH, SSx to SCKx or SCKx
TssL2scL Input
to SCKx Edge
30
120
TssH2doZ SSx to SDOx Output
10
(Note 4)
(Note 4)
High-Impedance
TscH2ssH SSx after SCKx Edge
1.5 TCY + 40
TscL2ssH
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 66.7 ns. Therefore, the SCKx clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 411
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-18:
SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SSx
SP52
SP50
SCKx
(CKP = 0)
SP70
SP73
SP72
SP72
SP73
SCKx
(CKP = 1)
SP35 SP36
MSb
Bit 14 - - - - - -1
LSb
SDOx
SDIx
SP30, SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note 1: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 412
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-38: SPI1, SPI2 AND SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCKx Input Frequency
SCKx Input Fall Time
—
—
—
—
11
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
TscR
TdoF
TdoR
SCKx Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
See Parameter DO31
(Note 4)
SDOx Data Output Fall Time
SDOx Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
TdoV2scH, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
30
—
—
—
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
30
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
TssL2scH, SSx to SCKx or SCKx
TssL2scL Input
to SCKx Edge
30
120
TssH2doZ SSx to SDOx Output
10
(Note 4)
(Note 4)
High-Impedance
TscH2ssH SSx after SCKx Edge
1.5 TCY + 40
TscL2ssH
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCKx is 91 ns. Therefore, the SCKx clock generated by the master must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
5: Pertaining to SPI3: dsPIC33EPXXXGS702, dsPIC33EPXXXGSX04 and dsPIC33EPXXXGSX05 devices
with a remappable SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 413
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-39: SPI3 MAXIMUM DATA/CLOCK RATE SUMMARY(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Master
Transmit Only
(Half-Duplex)
Master
Slave
Maximum
Data Rate
Transmit/Receive Transmit/Receive
(Full-Duplex)
CKE
CKP
SMP
(Full-Duplex)
25 MHz
25 MHz
25 MHz
25 MHz
25 MHz
25 MHz
25 MHz
Table 30-40
—
—
0,1
1
0,1
0,1
0,1
0
0,1
1
—
—
—
—
—
—
Table 30-41
—
Table 30-42
—
0
1
—
—
—
—
Table 30-43
Table 30-44
Table 30-45
Table 30-46
1
0
1
1
0
0
1
0
0
0
0
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
FIGURE 30-19:
SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)
TIMING CHARACTERISTICS(1,2)
SCK3
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK3
(CKP = 1)
SP35
MSb
Bit 14 - - - - - -1
LSb
SDO3
SP30, SP31
SP30, SP31
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 414
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-20:
SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)
TIMING CHARACTERISTICS(1,2)
SP36
SCK3
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK3
(CKP = 1)
SP35
MSb
Bit 14 - - - - - -1
LSb
SDO3
SP30, SP31
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
TABLE 30-40: SPI3 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max.
Units
Conditions
SP10
SP20
FscP
TscF
Maximum SCK3 Frequency
SCK3 Output Fall Time
—
—
—
—
25
—
MHz (Note 3)
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP21
SP30
SP31
SP35
SP36
TscR
TdoF
TdoR
SCK3 Output Rise Time
—
—
—
—
20
—
—
—
6
—
—
—
20
—
See Parameter DO31
(Note 4)
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
See Parameter DO32
(Note 4)
See Parameter DO31
(Note 4)
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
TdiV2scH, SDO3 Data Output Setup to
—
TdiV2scL
First SCK3 Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 66.7 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 415
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-21:
SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING CHARACTERISTICS(1,2)
SP36
SCK3
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK3
(CKP = 1)
SP35
MSb
Bit 14 - - - - - -1
SP30, SP31
LSb
SDO3
SDI3
SP40
MSb In
SP41
Bit 14 - - - -1
LSb In
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
TABLE 30-41: SPI3 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param.
Symbol
FscP
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
SP10
SP20
SP21
SP30
SP31
SP35
Maximum SCK3 Frequency
SCK3 Output Fall Time
—
—
—
—
—
—
—
—
—
—
—
6
25
—
—
—
—
20
MHz (Note 3)
TscF
TscR
TdoF
TdoR
ns See Parameter DO32 (Note 4)
ns See Parameter DO31 (Note 4)
ns See Parameter DO32 (Note 4)
SCK3 Output Rise Time
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
ns
ns
See Parameter DO31 (Note 4)
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
SP36
SP40
SP41
TdoV2sc, SDO3 Data Output Setup to
TdoV2scL First SCK3 Edge
20
20
15
—
—
—
—
—
—
ns
ns
ns
TdiV2scH, Setup Time of SDI3 Data
TdiV2scL Input to SCK3 Edge
TscH2diL, Hold Time of SDI3 Data Input
TscL2diL
to SCK3 Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
DS70005258C-page 416
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-22:
SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING CHARACTERISTICS(1,2)
SCK3
(CKP = 0)
SP10
SP21
SP20
SP20
SP21
SCK3
(CKP = 1)
SP35SP36
MSb
Bit 14 - - - - - -1
LSb
SDO3
SD3
SP30, SP31
SP30, SP31
LSb In
MSb In
SP40 SP41
Bit 14 - - - -1
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
TABLE 30-42: SPI3 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param. Symbol
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
MHz -40ºC to +125ºC (Note 3)
SP10
SP20
SP21
SP30
SP31
SP35
FscP
TscF
TscR
TdoF
TdoR
Maximum SCK3 Frequency
SCK3 Output Fall Time
—
—
—
—
—
—
—
—
—
—
—
6
25
—
—
—
—
20
ns
ns
ns
ns
ns
See Parameter DO32 (Note 4)
See Parameter DO31 (Note 4)
See Parameter DO32 (Note 4)
See Parameter DO31 (Note 4)
SCK3 Output Rise Time
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
SP36
SP40
SP41
TdoV2scH, SDO3 Data Output Setup to
TdoV2scL First SCK3 Edge
20
20
20
—
—
—
—
—
—
ns
ns
ns
TdiV2scH, Setup Time of SDI3 Data
TdiV2scL Input to SCK3 Edge
TscH2diL, Hold Time of SDI3 Data Input
TscL2diL to SCK3Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 417
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-23:
SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SP60
SS3
SP52
SP50
SCK3
(CKP = 0)
SP70
SP73
SP72
SCK3
(CKP = 1)
SP36
SP35
SP72
SP73
SDO3
SDI3
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 418
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-43: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCK3 Input Frequency
SCK3 Input Fall Time
—
—
—
—
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SP60
TscR
TdoF
TdoR
SCK3 Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
50
See Parameter DO31
(Note 4)
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
—
TdoV2scH, SDO3 Data Output Setup to
TdoV2scL First SCK3 Edge
20
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDI3 Data Input
20
TdiV2scL
TscH2diL, Hold Time of SDI3 Data Input
TscL2diL to SCK3 Edge
TssL2scH, SS3 to SCK3 or SCK3
TssL2scL Input
to SCK3 Edge
15
120
TssH2doZ SS3 to SDO3 Output
10
1.5 TCY + 40
—
(Note 4)
(Note 4)
High-Impedance
TscH2ssH SS3 after SCK3 Edge
TscL2ssH
TssL2doV SDO3 Data Output Valid after
SS3 Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 66.7 ns. Therefore, the SCK3 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 419
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-24:
SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SP60
SS3
SP52
SP50
SCK3
(CKP = 0)
SP70
SP73
SP72
SCK3
(CKP = 1)
SP36
SP35
SP72
SP73
SDO3
SDI3
MSb
Bit 14 - - - - - -1
LSb
SP30, SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 420
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-44: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCK3 Input Frequency
SCK3 Input Fall Time
—
—
—
—
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
SP60
TscR
TdoF
TdoR
SCK3 Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
50
See Parameter DO31
(Note 4)
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
—
TdoV2scH, SDO3 Data Output Setup to
TdoV2scL First SCK3 Edge
20
—
—
—
—
—
—
—
TdiV2scH, Setup Time of SDI3 Data Input
20
TdiV2scL
TscH2diL, Hold Time of SDI3 Data Input
TscL2diL to SCK3 Edge
TssL2scH, SS3 to SCK3 or SCK3
TssL2scL Input
to SCK3 Edge
15
120
TssH2doZ SS3 to SDO3 Output
10
1.5 TCY + 40
—
(Note 4)
(Note 4)
High-Impedance
TscH2ssH, SS3 after SCK3 Edge
TscL2ssH
TssL2doV SDO3 Data Output Valid after
SS3 Edge
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 91 ns. Therefore, the SCK3 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 421
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-25:
SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SS3
SP52
SP50
SCK3
(CKP = 0)
SP70
SP73
SP72
SP72
SCK3
(CKP = 1)
SP73
SP35 SP36
MSb
Bit 14 - - - - - -1
LSb
SDO3
SDI3
SP51
SP30, SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 422
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-45: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCK3 Input Frequency
SCK3 Input Fall Time
—
—
—
—
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
TscR
TdoF
TdoR
SCK3 Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
See Parameter DO31
(Note 4)
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
—
TdoV2scH, SDO3 Data Output Setup to
TdoV2scL First SCK3 Edge
20
—
—
—
—
—
—
TdiV2scH, Setup Time of SDI3 Data Input
20
TdiV2scL
TscH2diL, Hold Time of SDI3 Data Input
TscL2diL to SCK3 Edge
TssL2scH, SS3 to SCK3 or SCK3
TssL2scL Input
to SCK3 Edge
15
120
TssH2doZ SS3 to SDO3 Output
10
(Note 4)
(Note 4)
High-Impedance
TscH2ssH, SS3 after SCK3 Edge
1.5 TCY + 40
TscL2ssH
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 66.7 ns. Therefore, the SCK3 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 423
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-26:
SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING CHARACTERISTICS(1,2)
SS3
SP52
SP50
SCK3
(CKP = 0)
SP70
SP73
SP72
SP72
SCK3
(CKP = 1)
SP73
SP35 SP36
SDO3
SDI3
MSb
Bit 14 - - - - - -1
LSb
SP51
SP30, SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note 1: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2: Refer to Figure 30-1 for load conditions.
DS70005258C-page 424
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-46: SPI3 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)
TIMING REQUIREMENTS(5)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param. Symbol
Characteristic(1)
Min.
Typ.(2) Max. Units
Conditions
MHz (Note 3)
SP70
SP72
FscP
TscF
Maximum SCK3 Input Frequency
SCK3 Input Fall Time
—
—
—
—
25
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
See Parameter DO32
(Note 4)
SP73
SP30
SP31
SP35
SP36
SP40
SP41
SP50
SP51
SP52
TscR
TdoF
TdoR
SCK3 Input Rise Time
—
—
—
—
6
—
—
—
20
—
—
—
—
50
—
See Parameter DO31
(Note 4)
SDO3 Data Output Fall Time
SDO3 Data Output Rise Time
—
See Parameter DO32
(Note 4)
—
See Parameter DO31
(Note 4)
TscH2doV, SDO3 Data Output Valid after
TscL2doV SCK3 Edge
—
TdoV2scH, SDO3 Data Output Setup to
TdoV2scL First SCK3 Edge
20
—
—
—
—
—
—
TdiV2scH, Setup Time of SDI3 Data Input
20
TdiV2scL
TscH2diL, Hold Time of SDI3 Data Input
TscL2diL to SCK3 Edge
TssL2scH, SS3 to SCK3 or SCK3
TssL2scL Input
to SCK3 Edge
15
120
TssH2doZ SS3 to SDO3 Output
10
(Note 4)
(Note 4)
High-Impedance
TscH2ssH, SS3 after SCK1 Edge
1.5 TCY + 40
TscL2ssH
Note 1: These parameters are characterized, but are not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated.
3: The minimum clock period for SCK3 is 91 ns. Therefore, the SCK3 clock generated by the master must
not violate this specification.
4: Assumes 50 pF load on all SPI3 pins.
5: For dsPIC33EPXXXGSX06 and dsPIC33EPXXXGSX08 devices with a fixed SCK3 pin.
2016-2018 Microchip Technology Inc.
DS70005258C-page 425
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-27:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-28:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM26
IM11
IM25
IM33
IM10
SDAx
In
IM40
IM40
IM45
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
DS70005258C-page 426
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-47: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(4)
Min.(1)
Max.
Units
Conditions
IM10
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 2)
400 kHz mode TCY/2 (BRG + 2)
—
—
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
pF
ns
1 MHz mode(2) TCY/2 (BRG + 2)
—
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 2)
400 kHz mode TCY/2 (BRG + 2)
—
—
1 MHz mode(2) TCY/2 (BRG + 2)
—
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
20 + 0.1 CB
—
250
100
40
0
TSU:DAT Data Input
Setup Time
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 2)
1 MHz mode(2) TCY/2 (BRG + 2)
—
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 2)
Hold Time
—
After this period, the
first clock pulse is
generated
400 kHz mode
1 MHz mode(2) TCY/2 (BRG + 2)
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 2)
TCY/2 (BRG +2)
—
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 2)
1 MHz mode(2) TCY/2 (BRG + 2)
100 kHz mode TCY/2 (BRG + 2)
400 kHz mode TCY/2 (BRG + 2)
1 MHz mode(2) TCY/2 (BRG + 2)
—
—
THD:STO Stop Condition
Hold Time
—
—
—
TAA:SCL Output Valid
from Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
IM50
IM51
CB
Bus Capacitive Loading
Pulse Gobbler Delay
400
390
TPGD
65
(Note 3)
Note 1: BRG is the value of the I2C Baud Rate Generator.
2: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
4: These parameters are characterized but not tested in manufacturing.
2016-2018 Microchip Technology Inc.
DS70005258C-page 427
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-29:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS31
IS34
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 30-30:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS11
IS21
IS10
IS26
SCLx
IS30
IS33
IS25
IS31
SDAx
In
IS45
IS40
IS40
SDAx
Out
DS70005258C-page 428
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-48: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic(3)
Min.
Max. Units
Conditions
IS10
TLO:SCL Clock Low Time 100 kHz mode
400 kHz mode
4.7
1.3
0.5
4.0
—
—
—
—
µs
µs
µs
1 MHz mode(1)
IS11
THI:SCL Clock High Time 100 kHz mode
µs
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1 MHz mode(1)
0.6
—
µs
Device must operate at a
minimum of 10 MHz
0.5
—
300
300
100
1000
300
300
—
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
µs
pF
ns
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
—
SDAx and SCLx 100 kHz mode
Rise Time
CB is specified to be from
10 to 400 pF
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
250
100
100
0
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
THD:STO Stop Condition
Hold Time
—
0.6
0.25
0
—
TAA:SCL Output Valid from 100 kHz mode
3500
1000
350
—
Clock
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
IS50
IS51
CB
Bus Capacitive Loading
Pulse Gobbler Delay
400
390
TPGD
65
(Note 2)
Note 1: Maximum Pin Capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
2: Typical value for this parameter is 130 ns.
3: These parameters are characterized but not tested in manufacturing.
2016-2018 Microchip Technology Inc.
DS70005258C-page 429
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-31:
CANx MODULE I/O TIMING CHARACTERISTICS
CxTX Pin
(output)
Old Value
New Value
CA10 CA11
CA20
CxRX Pin
(input)
TABLE 30-49: CANx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min.
Typ.(2) Max.
Units
Conditions
CA10
CA11
CA20
TIOF
TIOR
TCWF
Port Output Fall Time
Port Output Rise Time
—
—
—
—
—
—
—
—
ns
ns
ns
See Parameter DO32
See Parameter DO31
Pulse Width to Trigger
CAN Wake-up Filter
120
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
DS70005258C-page 430
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
FIGURE 30-32:
UARTx MODULE I/O TIMING CHARACTERISTICS
UA20
UxRX
UXTX
MSb In
UA10
Bits 6-1
LSb In
TABLE 30-50: UARTx MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +125°C
Param
Symbol
No.
Characteristic(1)
UARTx Baud Time
Min. Typ.(2) Max. Units
Conditions
UA10
UA11
UA20
TUABAUD
FBAUD
TCWF
66.67
—
—
—
—
—
15
—
ns
Mbps
ns
UARTx Baud Frequency
Start Bit Pulse Width to Trigger
UARTx Wake-up
500
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 30-51: ANALOG CURRENT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
AC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +125°C
Param
Symbol
No.
Characteristic(1)
Min. Typ.(2) Max. Units
Conditions
AVD01 IDD
Analog Modules Current
Consumption
—
9
—
mA Characterized data with the
following modules enabled:
APLL, 5 ADC Cores, 2 PGAs
and 4 Analog Comparators
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2016-2018 Microchip Technology Inc.
DS70005258C-page 431
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-52: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(5)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
AVDD
Characteristics
Min.
Typical
Max.
Units
Conditions
Device Supply
AD01
Module VDD Supply
Greater of:
VDD – 0.3
or 3.0
—
—
Lesser of:
VDD + 0.3
or 3.6
V
V
Within 300 mV of VDD at
all times, including device
power-up
AD02
AVSS
Module VSS Supply
VSS
VSS + 0.3
Reference Inputs
AD06
AD07
VREFL
VREF
Reference Voltage Low
—
AVSS
—
—
V
V
(Note 1)
(Note 3)
Absolute Reference
2.7
AVDD
Voltage (VREFH – VREFL)
AD08
IREF
Reference Input Current
—
5
10
µA ADC operating or in standby
Analog Input
AD12 VINH-VINL Full-Scale Input Span
AVSS
AVSS – 0.3
—
—
—
AVDD
AVDD + 0.3
—
V
V
AD14
AD17
VIN
RIN
Absolute Input Voltage
Recommended
100
For minimum sampling
Impedance of Analog
Voltage Source
time (Note 1)
AD66
VBG
Internal Voltage
—
1.2
—
V
Reference Source
ADC Accuracy: Pseudodifferential Input
AD20a Nr
AD21a INL
AD22a DNL
Resolution
12
bits
Integral Nonlinearity
> -3
> -1
—
—
< 3
< 1
LSb AVSS = 0V, AVDD = 3.3V
Differential Nonlinearity
LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23a GERR
Gain Error
(Dedicated Core)
> 0
> 5
> 0
> 2
—
8
15
5
< 15
< 22
< 10
< 13
—
LSb AVSS = 0V, AVDD = 3.3V
Gain Error
(Shared Core)
LSb
AD24a EOFF
Offset Error
(Dedicated Core)
LSb AVSS = 0V, AVDD = 3.3V
LSb
Offset Error
(Shared Core)
8
AD25a
—
Monotonicity
—
—
Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: No missing codes, limits based on characterization results.
3: These parameters are characterized but not tested in manufacturing.
4: Characterized with a 15 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.
DS70005258C-page 432
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-52: ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(5)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
Characteristics
Min.
Typical
Max.
Units
Conditions
ADC Accuracy: Single-Ended Input
AD20b Nr
AD21b INL
AD22b DNL
Resolution
12
bits
Integral Nonlinearity
Differential Nonlinearity
> 5
—
—
< 5
< 1
LSb AVSS = 0V, AVDD = 3.3V
> -1
LSb AVSS = 0V, AVDD = 3.3V
(Note 2)
AD23b GERR
Gain Error
(Dedicated Core)
> 0
> 5
> 2
> 5
—
8
< 15
< 22
< 15
< 22
—
LSb AVSS = 0V, AVDD = 3.3V
Gain Error
(Shared Core)
15
9
LSb
AD24b EOFF
Offset Error
(Dedicated Core)
LSb AVSS = 0V, AVDD = 3.3V
LSb
Offset Error
(Shared Core)
17
AD25b
—
Monotonicity
—
—
Guaranteed
Dynamic Performance
AD31b SINAD
AD34b ENOB
Signal-to-Noise and
Distortion
63
—
> 65
—
dB (Notes 3, 4)
bits (Notes 3, 4)
Effective Number of Bits
10.3
—
Note 1: These parameters are not characterized or tested in manufacturing.
2: No missing codes, limits based on characterization results.
3: These parameters are characterized but not tested in manufacturing.
4: Characterized with a 15 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.
2016-2018 Microchip Technology Inc.
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dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-53: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(2)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol Characteristics
Min. Typ.(1) Max. Units
Conditions
Clock Parameters
AD50 TAD
AD51 FTP
ADC Clock Period 14.28
—
—
ns
Throughput Rate
SH0-SH3
SH4
—
—
—
—
3.25 Msps 70 MHz ADC clock, 12 bits, no pending
conversion at time of trigger
3.25 Msps
Note 1: These parameters are characterized but not tested in manufacturing.
2: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is ensured, but not characterized.
TABLE 30-54: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(2)
AC/DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Comments
CM10
CM11
VIOFF
VICM
Input Offset Voltage
-35
0
±5
—
35
mV
V
Input Common-Mode
Voltage Range(1)
AVDD
CM13 CMRR Common-Mode
Rejection Ratio
60
—
—
—
—
dB
CM14
TRESP
Large Signal Response
15
ns V+ input step of 100 mV while
V- input is held at AVDD/2. Delay
measured from analog input pin to
PWMx output pin.
CM15
CM16
VHYST
TON
Input Hysteresis
5
10
—
20
1
mV Depends on HYSSEL<1:0>
µs
Comparator Enabled to
Valid Output
—
Note 1: These parameters are for design guidance only and are not tested in manufacturing.
2: The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
DS70005258C-page 434
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-55: DACx MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(2)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC/DC CHARACTERISTICS
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Comments
DA01
DA02
DA03
DA04
DA05
DA06
DA07
EXTREF External Voltage Reference(1)
1
—
12
AVDD
V
CVRES
INL
Resolution
bits
LSB
LSB
LSB
%
Integral Nonlinearity Error
Differential Nonlinearity Error
Offset Error
-16
-1.8
-8
-12
±1
0
1.8
15
0
DNL
EOFF
EG
3
Gain Error
-1.2
—
-0.5
700
TSET
Settling Time(1)
—
ns
Output with 2% of desired
output voltage with a
10-90% or 90-10% step
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
TABLE 30-56: DACx OUTPUT (DACOUTx PIN) SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Comments
DA11 RLOAD
DA11a CLOAD
DA12 IOUT
Resistive Output Load
Impedance
10k
—
—
Ohm
Output Load
Capacitance
—
—
—
300
—
35
—
pF Including output pin
capacitance
Output Current Drive
Strength
µA Sink and source
DA13 VRANGE Output Drive Voltage AVSS + 250 mV
AVDD – 900 mV
V
Range at Current
Drive of 300 µA
DA14 VLRANGE Output Drive Voltage
Range at Reduced
AVSS + 50 mV
—
—
—
AVDD – 500 mV
1.3 x IOUT
V
Current Drive of 50 µA
DA15 IDD
Current Consumed
when Module is
Enabled
µA Module will always
consume this current,
even if no load is
connected to the output
DA30 VOFFSET Input Offset Voltage
—
5
—
mV
Note 1: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
2016-2018 Microchip Technology Inc.
DS70005258C-page 435
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TABLE 30-57: PGAx MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
AC/DC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ.
Max.
Units
Comments
PA01
PA02
VIN
Input Voltage Range
AVSS – 0.3
AVSS
—
—
AVDD + 0.3
AVDD – 1.6
V
V
VCM
Common-Mode Input
Voltage Range
PA03
PA04
VOS
VOS
Input Offset Voltage
-10
—
—
10
—
mV
Input Offset Voltage Drift
with Temperature
15
µV/C
PA05
PA06
PA07
RIN+
RIN-
Input Impedance of
Positive Input
—
—
>1M || 7 pF
10k || 7 pF
—
—
|| pF
|| pF
Input Impedance of
Negative Input
GERR
Gain Error
-2
-3
-4
—
—
—
—
—
2
3
%
%
%
%
Gain = 4x, 8x
Gain = 16x
4
Gain = 32x, 64x
PA08
PA09
LERR
IDD
Gain Nonlinearity Error
Current Consumption
0.5
% of full scale,
Gain = 16x
—
2.0
—
mA
Module is enabled with
a 2-volt P-P output
voltage swing
PA10a BW
PA10b
Small Signal
Bandwidth (-3 dB)
G = 4x
—
—
—
—
—
—
10
5
—
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
µs
G = 8x
PA10c
G = 16x
G = 32x
G = 64x
2.5
PA10d
1.25
0.625
0.4
PA10e
PA11
OST
Output Settling Time to 1%
of Final Value
Gain = 16x, 100 mV
input step change
PA12 SR
Output Slew Rate
—
—
—
40
1
—
—
10
V/µs Gain = 16x
PA13
PA14
TGSEL
TON
Gain Selection Time
Module Turn On/Setting Time
µs
µs
—
Note 1: The PGAx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.
DS70005258C-page 436
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
TABLE 30-58: CONSTANT-CURRENT SOURCE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)(1)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ.
Max. Units
Conditions
CC01 IDD
Current Consumption
—
—
30
±3
—
—
µA
%
CC02 IREG
Regulation of Current with
Voltage On
CC03 IOUT
Current Output at Terminal
—
10
—
µA
Note 1: The constant-current source module is functional at VBORMIN < VDD < VDDMIN, but with degraded
performance. Unless otherwise stated, module functionality is tested, but not characterized.
TABLE 30-59: DMA MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Characteristic
Min.
Typ.(1)
Max.
Units
Conditions
(2)
1 TCY
DM1
DMA Byte/Word Transfer Latency
—
—
ns
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because DMA transfers use the CPU data bus, this time is dependent on other functions on the bus.
2016-2018 Microchip Technology Inc.
DS70005258C-page 437
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NOTES:
DS70005258C-page 438
2016-2018 Microchip Technology Inc.
31.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 31-1:
VOH – 4x DRIVER PINS
FIGURE 31-3:
VOL – 4x DRIVER PINS
3.6V
3.6V
3.3V
3.3V
3V
3V
Absolute Maximum
Absolute Maximum
FIGURE 31-2:
VOH – 8x DRIVER PINS
FIGURE 31-4:
VOL – 8x DRIVER PINS
3.6V
3.6V
3.3V
3.3V
3V
3V
Absolute Maximum
Absolute Maximum
FIGURE 31-5:
TYPICAL IPD CURRENT @ VDD = 3.3V
FIGURE 31-7:
TYPICAL IDOZE CURRENT @ VDD = 3.3V, +25°C
300
30.0
25.0
20.0
250
200
150
100
50
15.0
10.0
5.0
0
0.0
-40 -30 -20 -10
0
10 20
30 40
50 60
70 80
90 100 110 120
1:1
1:2
1:64
1:128
Temperature (°C)
Doze Ratio
FIGURE 31-6:
TYPICAL IDD CURRENT @ VDD = 3.3V, +25°C
FIGURE 31-8:
TYPICAL IIDLE CURRENT @ VDD = 3.3V, +25°C
12.0
30
10.0
8.0
6.0
4.0
2.0
25
20
15
10
0.0
10
5
20
30
40
50
60
70
10
20
30
40
50
60
70
MIPS
MIPS
FIGURE 31-9:
TYPICAL FRC FREQUENCY @ VDD = 3.3V
FIGURE 31-10:
TYPICAL LPRC FREQUENCY @ VDD = 3.3V
7400
34.4
34.2
34
7350
7300
7250
7200
33.8
33.6
33.4
33.2
33
7150
-40
-40
-20
0
20
40
60
80
100
120
-20
0
20
40
60
80
100
120
Temperature (°C)
Temperature (°C)
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 442
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
32.0 PACKAGING INFORMATION
32.1 Package Marking Information
28-Lead SOIC (7.50 mm)
Example
dsPIC33EP128GS702
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
1810017
YYWWNNN
28-Lead UQFN (6x6x0.55 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
33EP128
GS702
1810017
28-Lead QFN-S (6x6x0.9 mm)
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
33EP128
GS702
1810017
44-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33EP
64GS804
1810017
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2016-2018 Microchip Technology Inc.
DS70005258C-page 443
dsPIC33EPXXXGS70X/80X FAMILY
32.1 Package Marking Information (Continued)
44-Lead QFN (8x8 mm)
Example
XXXXXXXXXXX
XXXXXXXXXXX
XXXXXXXXXXX
YYWWNNN
dsPIC33EP
64GS804
1810017
48-Lead TQFP (7x7x1.0 mm)
Example
1
E1P64GS
8051810
XXXXXXX
XXXYYWW
NNN
017
64-Lead TQFP (10x10x1 mm)
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC33EP
64GS806
1810017
80-Lead TQFP (12x12x1 mm)
Example
XXXXXXXXXXXX
XXXXXXXXXXXX
YYWWNNN
dsPIC33EP64
GS808
1810017
DS70005258C-page 444
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
32.2 Package Details
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS70005258C-page 445
dsPIC33EPXXXGS70X/80X FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70005258C-page 446
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS70005258C-page 447
dsPIC33EPXXXGS70X/80X FAMILY
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.10 C
2X
0.10 C
TOP VIEW
A
A1
C
0.10 C
28X
SEATING
PLANE
(A3)
SIDE VIEW
0.08 C
8X b1
8X b2
0.10
C A B
D2
0.10
C A B
E2
2
1
28X K
2X P
N
NOTE 1
e
L
28X b
0.10
0.05
C A B
C
BOTTOM VIEW
Microchip Technology Drawing C04-385 Rev C Sheet 1 of 2
DS70005258C-page 448
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Exposed Pad Corner Chamfer
Terminal Width
Corner Anchor Pad
Corner Pad, Metal Free Zone
Terminal Length
Terminal-to-Exposed-Pad
N
28
0.65 BSC
0.50
e
A
A1
A3
E
E2
D
D2
P
b
0.45
0.00
0.55
0.05
0.02
0.127 REF
6.00 BSC
4.65
6.00 BSC
4.65
4.55
4.75
4.55
-
4.75
-
0.35
0.30
0.40
0.20
0.40
-
0.25
0.35
0.15
0.30
0.20
0.35
0.43
0.25
0.50
-
b1
b2
L
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-385 Rev C Sheet 2 of 2
2016-2018 Microchip Technology Inc.
DS70005258C-page 449
dsPIC33EPXXXGS70X/80X FAMILY
28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (2N) - 6x6x0.55 mm Body [UQFN]
With 4.65x4.65 mm Exposed Pad and Corner Anchors
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C2
Y2
EV
28
Y3
1
X1
ØV
2
Y4
G1
C1
EV
G2
Y1
X4
X3
E
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.65 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
X3
Y3
X4
Y4
G1
G2
V
4.75
4.75
6.00
6.00
Contact Pad Spacing
Contact Pad Width (X28)
Contact Pad Length (X28)
Corner Anchor (X4)
0.35
0.80
1.00
1.00
0.35
0.35
Corner Anchor (X4)
Corner Anchor Chamfer (X4)
Corner Anchor Chamfer (X4)
Contact Pad to Pad (X28)
Contact Pad to Center Pad (X28)
Thermal Via Diameter
0.20
0.20
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2385B
Note:
Corner anchor pads are not connected internally and are designed as mechanical features when the
package is soldered to the PCB.
DS70005258C-page 450
2016-2018 Microchip Technology Inc.
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2016-2018 Microchip Technology Inc.
DS70005258C-page 451
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DS70005258C-page 452
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
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ꢄ ꢈ*++&&&ꢏ!ꢋꢆꢂꢁꢆꢄꢋꢈꢏꢆꢁ!+ꢈꢉꢆ$ꢉꢊꢋꢇꢊ
2016-2018 Microchip Technology Inc.
DS70005258C-page 453
dsPIC33EPXXXGS70X/80X FAMILY
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
D1
B
E
NOTE 2
(DATUM A)
(DATUM B)
E1
A
A
NOTE 1
2X
N
0.20 H A B
2X
1 2 3
0.20 H A B
4X 11 TIPS
TOP VIEW
0.20 C A B
A
A2
C
SEATING PLANE
0.10 C
A1
SIDE VIEW
1 2 3
N
NOTE 1
44 X b
0.20
C A B
e
BOTTOM VIEW
Microchip Technology Drawing C04-076C Sheet 1 of 2
DS70005258C-page 454
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
44-Lead Plastic Thin Quad Flatpack (PT) - 10x10x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
θ
L
(L1)
SECTION A-A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
0.80 BSC
-
MAX
Number of Leads
Lead Pitch
Overall Height
Standoff
N
e
A
A1
-
1.20
0.15
1.05
0.05
0.95
-
Molded Package Thickness
Overall Width
A2
E
1.00
12.00 BSC
10.00 BSC
12.00 BSC
10.00 BSC
0.37
Molded Package Width
Overall Length
E1
D
Molded Package Length
Lead Width
D1
b
c
0.30
0.09
0.45
0.45
0.20
0.75
Lead Thickness
Lead Length
Footprint
-
L
L1
θ
0.60
1.00 REF
3.5°
Foot Angle
0°
7°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Exact shape of each corner is optional.
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-076C Sheet 2 of 2
2016-2018 Microchip Technology Inc.
DS70005258C-page 455
dsPIC33EPXXXGS70X/80X FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS70005258C-page 456
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.20 C
2X
TOP VIEW
0.20 C
A1
0.10 C
0.08 C
C
A
SEATING
PLANE
44X
0.10
A3
SIDE VIEW
L
C A B
D2
0.10
C A B
E2
K
2
1
NOTE 1
N
44X b
0.07
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-103D Sheet 1 of 2
2016-2018 Microchip Technology Inc.
DS70005258C-page 457
dsPIC33EPXXXGS70X/80X FAMILY
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Terminal Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Terminal Width
Terminal Length
N
44
0.65 BSC
0.90
e
A
A1
A3
E
E2
D
D2
b
L
0.80
0.00
1.00
0.05
0.02
0.20 REF
8.00 BSC
6.45
8.00 BSC
6.45
0.30
0.40
-
6.25
6.60
6.25
0.20
0.30
0.20
6.60
0.35
0.50
-
Terminal-to-Exposed-Pad
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103D Sheet 2 of 2
DS70005258C-page 458
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
44-Lead Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN or VQFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
X2
EV
44
G2
1
2
ØV
EV
C2
Y2
G1
Y1
SILK SCREEN
E
X1
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
MILLIMETERS
NOM
0.65 BSC
MIN
MAX
Contact Pitch
Optional Center Pad Width
Optional Center Pad Length
Contact Pad Spacing
X2
Y2
C1
C2
X1
Y1
G1
G2
V
6.60
6.60
8.00
8.00
Contact Pad Spacing
Contact Pad Width (X44)
Contact Pad Length (X44)
Contact Pad to Contact Pad (X40)
Contact Pad to Center Pad (X44)
Thermal Via Diameter
0.35
0.85
0.30
0.28
0.33
1.20
Thermal Via Pitch
EV
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing No. C04-2103C
2016-2018 Microchip Technology Inc.
DS70005258C-page 459
dsPIC33EPXXXGS70X/80X FAMILY
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
48X TIPS
0.20 C A-B D
D
D1
D1
2
D
A
B
E1 E
E1
2
A
A
E1
4
N
1
2
NOTE 1
4X
D1
0.20 H A-B D
4
48x b
0.08
C A-B D
e
TOP VIEW
0.10 C
H
C
A2
A1
A
SEATING
PLANE
0.08 C
SIDE VIEW
Microchip Technology Drawing C04-300-PT Rev A Sheet 1 of 2
DS70005258C-page 460
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
H
c
E
T
L
(L1)
SECTION A-A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
48
0.50 BSC
-
MAX
Number of Leads
Lead Pitch
Overall Height
Standoff
N
e
A
A1
-
1.20
0.15
1.05
0.75
0.05
0.95
0.45
-
Molded Package Thickness
A2
L
1.00
0.60
1.00 REF
3.5°
Foot Length
Footprint
Foot Angle
L1
I
0°
7°
Overall Width
Overall Length
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
E
D
E1
D1
c
b
D
E
9.00 BSC
9.00 BSC
7.00 BSC
7.00 BSC
-
0.22
12°
12°
0.09
0.17
11°
0.16
0.27
13°
Mold Draft Angle Top
Mold Draft Angle Bottom
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
5. Datums A-B and D to be determined at center line between leads where leads exit
plastic body at datum plane H
Microchip Technology Drawing C04-300-PT Rev A Sheet 2 of 2
2016-2018 Microchip Technology Inc.
DS70005258C-page 461
dsPIC33EPXXXGS70X/80X FAMILY
48-Lead Thin Quad Flatpack (PT) - 7x7x1.0 mm Body [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
G
C2
SILK SCREEN
48
Y1
1 2
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
E
0.50 BSC
8.40
8.40
Contact Pad Spacing
Contact Pad Spacing
Contact Pad Width (X48)
C1
C2
X1
0.30
1.50
Contact Pad Length (X48)
Distance Between Pads
Y1
G
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during
reflow process
Microchip Technology Drawing C04-2300-PT Rev A
DS70005258C-page 462
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
D1
D1/2
D
NOTE 2
E1/2
A
B
E1
E
A
A
SEE DETAIL 1
4X N/4 TIPS
N
1
3
0.20 C A-B D
2
4X
NOTE 1
0.20 H A-B D
TOP VIEW
A2
A
0.05
C
SEATING
PLANE
A1
C A-B D
64 X b
0.08
0.08 C
e
SIDE VIEW
Microchip Technology Drawing C04-085C Sheet 1 of 2
2016-2018 Microchip Technology Inc.
DS70005258C-page 463
dsPIC33EPXXXGS70X/80X FAMILY
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
H
c
E
T
L
(L1)
X=A—B OR D
X
SECTION A-A
e/2
DETAIL 1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
64
0.50 BSC
-
1.00
-
MAX
Number of Leads
Lead Pitch
Overall Height
N
e
A
-
1.20
1.05
0.15
0.75
Molded Package Thickness
Standoff
A2
A1
L
0.95
0.05
0.45
Foot Length
0.60
Footprint
Foot Angle
L1
I
1.00 REF
3.5°
0°
7°
Overall Width
Overall Length
E
D
E1
D1
c
b
D
E
12.00 BSC
12.00 BSC
10.00 BSC
10.00 BSC
-
Molded Package Width
Molded Package Length
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0.09
0.17
11°
0.20
0.27
13°
0.22
12°
12°
11°
13°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2
DS70005258C-page 464
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS70005258C-page 465
dsPIC33EPXXXGS70X/80X FAMILY
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DS70005258C-page 466
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2016-2018 Microchip Technology Inc.
DS70005258C-page 467
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
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Revision C (October 2018)
APPENDIX A: REVISION HISTORY
• Sections:
Revision A (May 2016)
- Adds Note 1 to all “Pin Diagrams”.
This is the initial version of the document.
- Updates Section 2.5 “ICSP Pins”,
Section 4.5.2 “Extended X Data Space”,
Section 8.0 “Direct Memory Access
(DMA)”, Section 11.7 “I/O Helpful Tips”,
Section 16.2 “Feature Description”,
Section 24.1 “Features Overview” and
Section 24.3 “Module Applications”.
Revision B (January 2017)
• Sections:
- Updates Note 1 in Section 5.0 “Flash
Program Memory”.
• Tables:
• Tables:
- Updates the device description table on
page 2.
- Updates Table 1-1, Table 4-9, Table 4-15,
Table 8-1, Table 21-1, Table 21-2, Table 21-3,
Table 21-4, Table 30-11, Table 30-56 and
Table 30-57.
- Updates Table 1-1, Table 4-2, Table 4-11,
Table 7-1, Table 8-1, Table 11-11,
Table 11-13, Table 17-1, Table 30-3,
Table 30-4, Table 30-6, Table 30-7,
Table 30-8, Table 30-9, Table 30-10,
Table 30-11, Table 30-52, Table 30-54 and
Table 30-55.
• Registers:
- Updates Register 3-2, Register 5-1,
Register 9-4, Register 9-5, Register 10-1,
Register 11-8, Register 14-1, Register 16-1,
Register 16-2, Register 16-3, Register 16-4,
Register 16-5, Register 16-6, Register 16-7,
Register 16-8, Register 16-9, Register 16-10,
Register 16-11, Register 16-13,
- Adds Table 11-6, Table 11-7, Table 11-8,
Table 11-9 and Table 11-10.
• Figures:
Register 16-14, Register 16-16,
- Updates the Pin Function tables in the Pin
Diagram figures on pages 5 through 8.
Register 16-22, Register 19-1, Register 19-3,
Register 21-3, Register 22-1, Register 22-28,
Register 22-29, Register 22-30 and
Register 26-1.
- Updates Figure 4-1, Figure 17-1, Figure 18-1
and Figure 18-2.
• Registers:
• Figures:
- Updates Register 3-3, Register 16-5,
Register 17-11, Register 18-1 and
Register 19-2.
- Updates Figure 16-2, Figure 18-1,
Figure 18-2 and Figure 30-30.
- Adds Register 11-1, Register 11-2,
Register 11-3, Register 11-4, Register 11-5,
Register 11-6, Register 11-7 and
Register 11-8.
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INDEX
Assembler
A
MPASM Assembler .................................................. 376
MPLAB Assembler, Linker, Librarian........................ 376
Absolute Maximum Ratings .............................................. 379
AC Characteristics ............................................................ 391
ADC Specifications ................................................... 432
Analog Current Specifications................................... 431
Analog-to-Digital Conversion Requirements............. 434
Auxiliary PLL Clock................................................... 393
CANx I/O Requirements ........................................... 430
Capacitive Loading Requirements on
B
Bit-Reversed Addressing.................................................... 58
Example...................................................................... 59
Implementation........................................................... 58
Sequence Table (16-Entry) ........................................ 59
Block Diagrams
Output Pins....................................................... 391
DMA Module Requirements...................................... 437
External Clock Requirements ................................... 392
High-Speed PWMx Requirements............................ 401
I/O Requirements...................................................... 395
I2Cx Bus Data Requirements (Master Mode)........... 427
I2Cx Bus Data Requirements (Slave Mode)............. 429
Input Capture x Requirements.................................. 399
Internal FRC Accuracy.............................................. 394
Internal LPRC Accuracy............................................ 394
Load Conditions........................................................ 391
OCx/PWMx Module Requirements........................... 400
Output Compare x Requirements ............................. 400
PLL Clock.................................................................. 393
Reset, WDT, OST, PWRT Requirements................. 396
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
CKE = 0, CKP = x, SMP = 1) Requirements ........ 405
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
CKE = 1, CKP = x, SMP = 1) Requirements ........ 404
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex,
Transmit Only) Requirements ............................... 403
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 0, CKP = 0, SMP = 0) Requirements........ 413
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 0, CKP = 1, SMP = 0) Requirements........ 411
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 1, CKP = 0, SMP = 0) Requirements........ 407
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 1, CKP = 1, SMP = 0) Requirements........ 409
SPI3 Master Mode (Full-Duplex, CKE = 0,
CKP = x, SMP = 1) Requirements.................... 417
SPI3 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) Requirements.................... 416
SPI3 Master Mode (Half-Duplex, Transmit Only)
Requirements ................................................... 415
SPI3 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) Requirements.................... 425
SPI3 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) Requirements.................... 423
SPI3 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) Requirements.................... 419
SPI3 Slave Mode (Full-Duplex, CKE = 1,
16-Bit Timer1 Module ............................................... 171
ADC Module ............................................................. 278
Addressing for Table Registers .................................. 63
CALL Stack Frame ..................................................... 54
CANx Module ........................................................... 312
CLCx Input Source Selection ................................... 265
CLCx Logic Function Combinatorial Options............ 264
CLCx Module............................................................ 263
Connections for On-Chip Voltage Regulator ............ 359
Constant-Current Source.......................................... 349
CPU Core ................................................................... 24
Data Access from Program Space
Address Generation............................................ 60
Dedicated ADC Cores 0-3........................................ 279
DMA Controller........................................................... 93
dsPIC33EPXXGS70X/80X Family.............................. 13
High-Speed Analog Comparator x............................ 338
High-Speed PWM Architecture................................. 191
Hysteresis Control .................................................... 340
I2Cx Module ............................................................. 250
Input Capture x......................................................... 179
Interleaved PFC.......................................................... 20
MCLR Pin Connections .............................................. 18
Multiplexing Remappable Outputs for RPn .............. 140
Off-Line UPS .............................................................. 22
Oscillator System...................................................... 106
Output Compare x Module ....................................... 183
Peripheral to DMA Controller...................................... 91
PGAx Functions........................................................ 346
PGAx Module ........................................................... 345
Phase-Shifted Full-Bridge Converter.......................... 21
PLL Module .............................................................. 107
Programmer’s Model .................................................. 26
PSV Read Address Generation.................................. 51
PTG Module ............................................................. 218
Recommended Minimum Connection ........................ 18
Remappable Input for U1RX .................................... 138
Reset System ............................................................. 71
Security Segments for dsPIC33EP128GS70X/80X
(Dual Partition Modes)...................................... 363
Security Segments for dsPIC33EP64GS70X/80X
(Dual Partition Modes)...................................... 362
Security Segments for
CKP = 1, SMP = 0) Requirements.................... 421
Temperature and Voltage Specifications.................. 391
Timer1 External Clock Requirements ....................... 397
Timer2/Timer4 External Clock Requirements........... 398
Timer3/Timer5 External Clock Requirements........... 398
UARTx I/O Requirements ......................................... 431
AC/DC Characteristics
DACx Specifications ................................................. 435
High-Speed Analog Comparator Specifications........ 434
PGAx Specifications ................................................. 436
Analog-to-Digital Converter. See ADC.
dsPIC33EPXXXGS70X/80X............................. 362
Shared ADC Core..................................................... 279
Shared Port Structure............................................... 127
Simplified Conceptual of High-Speed PWM............. 192
SPIx Master, Frame Master Connection .................. 247
SPIx Master, Frame Slave Connection .................... 248
SPIx Master/Slave Connection
(Enhanced Buffer Modes)................................. 247
SPIx Master/Slave Connection (Standard Mode)..... 246
SPIx Module (Enhanced Mode)................................ 235
Arithmetic Logic Unit (ALU)................................................. 32
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SPIx Module (Standard Mode)..................................234
SPIx Slave, Frame Master Connection.....................248
D
Data Address Space........................................................... 39
SPIx Slave, Frame Slave Connection.......................248
Suggested Oscillator Circuit Placement......................19
Timerx (x = 2 through 5)............................................176
Type B/Type C Timer Pair (32-Bit Timer)..................176
UARTx Module..........................................................257
Watchdog Timer (WDT)............................................360
Brown-out Reset (BOR) ............................................ 351, 359
Memory Map for dsPIC33EP64GS70X/80X
Devices............................................................... 40
Near Data Space ........................................................ 39
Organization, Alignment ............................................. 39
SFR Space ................................................................. 39
Width .......................................................................... 39
Data Space
Extended X................................................................. 54
Paged Data Memory Space (figure)........................... 52
Paged Memory Scheme ............................................. 51
C
C Compilers
MPLAB XC................................................................376
CAN Module
DC Characteristics
Brown-out Reset (BOR)............................................ 389
Constant-Current Source Specifications................... 437
DACx Output (DACOUTx Pin) Specifications........... 435
Doze Current (IDOZE)................................................ 385
I/O Pin Input Specifications....................................... 386
I/O Pin Output Specifications.................................... 389
Idle Current (IIDLE) .................................................... 383
Operating Current (IDD) ............................................ 382
Operating MIPS vs. Voltage ..................................... 380
Power-Down Current (IPD)........................................ 384
Program Memory...................................................... 390
Temperature and Voltage Specifications.................. 381
Watchdog Timer Delta Current (IWDT).................... 384
DC/AC Characteristics
Control Registers ......................................................313
Message Buffers.......................................................332
Word 0 ..............................................................332
Word 1 ..............................................................332
Word 2 ..............................................................333
Word 3 ..............................................................333
Word 4 ..............................................................334
Word 5 ..............................................................334
Word 6 ..............................................................335
Word 7 ..............................................................335
Modes of Operation ..................................................312
Overview ...................................................................311
CAN Module (CAN)...........................................................311
CLC
Graphs and Tables ................................................... 439
Demo/Development Boards, Evaluation and
Control Registers ......................................................266
Code Examples
Starter Kits................................................................ 378
Development Support....................................................... 375
Device Calibration............................................................. 357
Addresses................................................................. 357
and Identification ...................................................... 357
Device Programmer
MPLAB PM3 ............................................................. 377
Direct Memory Access. See DMA.
DMA Controller
Port Write/Read ........................................................132
PWM Write-Protected Register
Unlock Sequence..............................................190
PWRSAVInstruction Syntax........................................117
Code Protection ........................................................ 351, 361
CodeGuard Security.................................................. 351, 361
Configurable Logic Cell (CLC) ..........................................263
Configurable Logic Cell. See CLC.
Configuration Bits..............................................................351
Description ................................................................353
Configuration Register Map ..............................................352
Constant-Current Source ..................................................349
Control Register........................................................350
Description ................................................................349
Features Overview....................................................349
Controller Area Network. See CAN.
Channel to Peripheral Associations............................ 92
Control Registers........................................................ 94
DMAxCNT .......................................................... 94
DMAxCON.......................................................... 94
DMAxPAD .......................................................... 94
DMAxREQ.......................................................... 94
DMAxSTAL/H ..................................................... 94
DMAxSTBL/H ..................................................... 94
Supported Peripherals................................................ 91
Doze Mode ....................................................................... 119
DSP Engine ........................................................................ 32
CPU
Addressing Modes ......................................................23
Clocking System Options..........................................107
Fast RC (FRC) Oscillator..................................107
FRC Oscillator with PLL (FRCPLL)...................107
FRC Oscillator with Postscaler .........................107
Low-Power RC (LPRC) Oscillator.....................107
Primary (XT, HS, EC) Oscillator........................107
Primary Oscillator with PLL
E
Electrical Characteristics .................................................. 379
AC............................................................................. 391
Equations
Device Operating Frequency.................................... 107
FPLLO Calculation ..................................................... 107
FVCO Calculation ...................................................... 107
Relationship Between Device and
(XTPLL, HSPLL, ECPLL)..........................107
Control Registers ........................................................28
Data Space Addressing ..............................................23
Instruction Set.............................................................23
Registers.....................................................................23
Resources...................................................................27
Customer Change Notification Service .............................478
Customer Notification Service...........................................478
Customer Support.............................................................478
SPIx Clock Speed............................................. 248
Errata.................................................................................. 10
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Input Change Notification (ICN)........................................ 132
Instruction Addressing Modes ............................................ 55
F
Filter Capacitor (CEFC) Specifications............................... 381
Flash Program Memory ...................................................... 63
and Table Instructions................................................. 63
Control Registers ........................................................ 66
Dual Partition Flash Configuration .............................. 65
Operations .................................................................. 64
Resources................................................................... 65
RTSP Operation.......................................................... 64
Flexible Configuration ....................................................... 351
File Register Instructions............................................ 55
Fundamental Modes Supported ................................. 55
MAC Instructions ........................................................ 56
MCU Instructions........................................................ 55
Move and Accumulator Instructions ........................... 56
Other Instructions ....................................................... 56
Instruction Set Summary .................................................. 365
Overview................................................................... 368
Symbols Used in Opcode Descriptions .................... 366
Instruction-Based Power-Saving Modes........................... 117
Idle............................................................................ 118
Sleep ........................................................................ 118
G
Getting Started Guidelines.................................................. 17
Connection Requirements .......................................... 17
CPU Logic Filter Capacitor Connection (VCAP) .......... 18
Decoupling Capacitors................................................ 17
External Oscillator Pins............................................... 19
ICSP Pins.................................................................... 19
Master Clear (MCLR) Pin............................................ 18
Oscillator Value Conditions on Start-up...................... 20
Targeted Applications ................................................. 20
Unused I/Os................................................................ 20
2
Inter-Integrated Circuit (I C) ............................................. 249
Control Registers...................................................... 251
Resources ................................................................ 249
2
Inter-Integrated Circuit. See I C.
Internet Address ............................................................... 478
Interrupt Controller
Alternate Interrupt Vector Table (AIVT)...................... 75
Control and Status Registers...................................... 83
INTCON1............................................................ 83
INTCON2............................................................ 83
INTCON3............................................................ 83
INTCON4............................................................ 83
INTTREG............................................................ 83
Interrupt Vector Details............................................... 78
Interrupt Vector Table (IVT)........................................ 75
Reset Sequence......................................................... 75
Resources .................................................................. 83
Interrupts Coincident with Power Save Instructions ......... 118
H
High-Speed Analog Comparator
Applications............................................................... 339
Description................................................................ 338
Digital-to-Analog Comparator (DAC) ........................ 339
Features Overview.................................................... 337
Hysteresis ................................................................. 340
Pulse Stretcher and Digital Logic.............................. 339
Resources................................................................. 340
High-Speed PWM
Features.................................................................... 189
Resources................................................................. 190
Write-Protected Registers......................................... 190
High-Speed, 12-Bit Analog-to-Digital
J
JTAG Boundary Scan Interface........................................ 351
JTAG Interface ................................................................. 361
L
Converter (ADC) ....................................................... 277
Control Registers ...................................................... 280
Features Overview.................................................... 277
Resources................................................................. 280
Leading-Edge Blanking (LEB) .......................................... 189
LPRC Oscillator
Use with WDT........................................................... 360
M
I
Memory Organization ......................................................... 33
Resources .................................................................. 41
Special Function Register Maps................................. 42
Microchip Internet Web Site.............................................. 478
Modulo Addressing............................................................. 57
Applicability................................................................. 58
Operation Example..................................................... 57
Start and End Address ............................................... 57
W Address Register Selection.................................... 57
MPLAB REAL ICE In-Circuit Emulator System ................ 377
MPLAB X Integrated Development
I/O Ports............................................................................ 127
Configuring Analog/Digital Port Pins......................... 132
Control Registers ...................................................... 133
Helpful Tips............................................................... 142
Open-Drain Configuration......................................... 132
Parallel I/O (PIO)....................................................... 127
Register Maps........................................................... 129
PORTA ............................................................. 129
PORTB ............................................................. 129
PORTC ............................................................. 130
PORTD ............................................................. 130
PORTE ............................................................. 131
Resources................................................................. 143
Write/Read Timing .................................................... 132
In-Circuit Debugger........................................................... 361
MPLAB ICD 3............................................................ 377
PICkit 3 Programmer ................................................ 377
In-Circuit Emulation........................................................... 351
In-Circuit Serial Programming (ICSP)....................... 351, 361
Input Capture .................................................................... 179
Control Registers ...................................................... 180
Resources................................................................. 179
Environment Software .............................................. 375
MPLINK Object Linker/MPLIB Object Librarian................ 376
Multiplexer Input Sources
CLC1 ........................................................................ 269
CLC2 ........................................................................ 270
CLC3 ........................................................................ 271
CLC4 ........................................................................ 272
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ADCAL0L (ADC Calibration 0 Low).......................... 303
ADCAL1H (ADC Calibration 1 High)......................... 305
ADCMPxCON (ADC Digital Comparator x
Control)............................................................. 306
ADCMPxENH (ADC Digital Comparator x
Channel Enable High) ...................................... 307
ADCMPxENL (ADC Digital Comparator x
Channel Enable Low) ....................................... 307
ADCON1H (ADC Control 1 High) ............................. 281
ADCON1L (ADC Control 1 Low)............................... 280
ADCON2H (ADC Control 2 High) ............................. 283
ADCON2L (ADC Control 2 Low)............................... 282
ADCON3H (ADC Control 3 High) ............................. 285
ADCON3L (ADC Control 3 Low)............................... 284
ADCON4H (ADC Control 4 High) ............................. 287
ADCON4L (ADC Control 4 Low)............................... 286
ADCON5H (ADC Control 5 High) ............................. 289
ADCON5L (ADC Control 5 Low)............................... 288
ADCORExH (Dedicated ADC Core x
O
Oscillator
Control Registers ......................................................109
Resources.................................................................108
Oscillator Configuration.....................................................105
Output Compare................................................................183
Control Registers ......................................................184
Resources.................................................................183
P
Packaging .........................................................................443
Details.......................................................................445
Marking .....................................................................443
Peripheral Module Disable (PMD).....................................119
Peripheral Pin Select (PPS)..............................................137
Available Peripherals ................................................137
Available Pins ...........................................................137
Control ......................................................................137
Control Registers ......................................................144
Input Mapping ...........................................................138
Output Mapping ........................................................140
Output Selection for Remappable Pins.....................141
Selectable Input Sources..........................................139
Peripheral Trigger Generator (PTG) Module.....................217
Peripheral Trigger Generator. See PTG.
Pinout I/O Descriptions (table) ............................................14
Power-Saving Features.....................................................117
Clock Frequency and Switching................................117
Resources.................................................................119
Program Address Space.....................................................33
Construction................................................................60
Data Access from Program Memory Using
Control High) .................................................... 291
ADCORExL (Dedicated ADC Core x
Control Low) ..................................................... 290
ADEIEH (ADC Early Interrupt Enable High) ............. 293
ADEIEL (ADC Early Interrupt Enable Low)............... 293
ADEISTATH (ADC Early Interrupt Status High) ....... 294
ADEISTATL (ADC Early Interrupt Status Low)......... 294
ADFLxCON (ADC Digital Filter x Control) ................ 308
ADIEH (ADC Interrupt Enable High)......................... 297
ADIEL (ADC Interrupt Enable Low) .......................... 297
ADLVLTRGH (ADC Level-Sensitive Trigger
Control High) .................................................... 292
ADLVLTRGL (ADC Level-Sensitive Trigger
Control Low) ..................................................... 292
ADMOD0H (ADC Input Mode Control 0 High).......... 295
ADMOD0L (ADC Input Mode Control 0 Low) ........... 295
ADMOD1L (ADC Input Mode Control 1 Low) ........... 296
ADSTATH (ADC Data Ready Status High) .............. 298
ADSTATL (ADC Data Ready Status Low)................ 298
ADTRIGxH (ADC Channel Trigger x
Table Instructions................................................61
Memory Map (dsPIC33EP128GS70X/80X Devices,
Dual Partition) .....................................................37
Memory Map (dsPIC33EP128GS70X/80X
Devices)..............................................................35
Memory Map (dsPIC33EP64GS70X/80X Devices,
Dual Partition) .....................................................36
Memory Map
Selection High) ................................................. 301
ADTRIGxL (ADC Channel Trigger x
(dsPIC33EP64GS70X/80X Devices) ..................34
Table Read High Instructions (TBLRDH) .....................61
Table Read Low Instructions (TBLRDL) ......................61
Program Memory
Interfacing with Data Memory Spaces ........................60
Organization................................................................38
Reset Vector ...............................................................38
Programmable Gain Amplifier (PGA)................................345
Description ................................................................346
Resources.................................................................347
Programmable Gain Amplifier. See PGA.
Programmer’s Model...........................................................25
Register Descriptions..................................................25
PTG
Control Registers ......................................................219
Introduction ...............................................................217
Output Descriptions ..................................................232
Step Commands and Format....................................229
Pulse-Width Modulator. See PWM.
Selection Low).................................................. 299
ALTDTRx (PWMx Alternate Dead-Time).................. 205
ANSELx (Analog Select Control x) ........................... 136
AUXCONx (PWMx Auxiliary Control) ....................... 214
CHOP (PWM Chop Clock Generator) ...................... 198
CLCxCONH (CLCx Control High)............................. 267
CLCxCONL (CLCx Control Low) .............................. 266
CLCxGLSH (CLCx Gate Logic
Input Select High)............................................. 275
CLCxGLSL (CLCx Gate Logic Input Select Low) ..... 273
CLCxSEL (CLCx Input MUX Select)......................... 268
CLKDIV (Clock Divisor) ............................................ 111
CMPxCON (Comparator x Control) .......................... 341
CMPxDAC (Comparator x DAC Control).................. 343
CNENx (Input Change Notification
Interrupt Enable x)............................................ 135
CNPDx (Input Change Notification
Pull-Down Enable x)......................................... 136
CNPUx (Input Change Notification
R
Pull-up Enable x) .............................................. 135
CORCON (Core Control)...................................... 30, 85
CTXTSTAT (CPU W Register Context Status)........... 31
CxBUFPNT1 (CANx Filters 0-3 Buffer Pointer 1) ..... 322
CxBUFPNT2 (CANx Filters 4-7 Buffer Pointer 2) ..... 323
Referenced Sources ...........................................................11
Registers
ACLKCON (Auxiliary Clock Divisor Control).............114
ADCAL0L (ADC Calibration 0 High) .........................304
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CxBUFPNT3 (CANx Filters 8-11
Buffer Pointer 3)................................................ 323
CxBUFPNT4 (CANx Filters 12-15
INTTREG (Interrupt Control and Status) .................... 90
IOCONx (PWMx I/O Control).................................... 207
ISRCCON (Constant-Current Source Control)......... 350
LATx (PORTx Data Latch)........................................ 134
LEBCONx (PWMx Leading-Edge
Buffer Pointer 4)................................................ 324
CxCFG1 (CANx Baud Rate Configuration 1)............ 320
CxCFG2 (CANx Baud Rate Configuration 2)............ 321
CxCTRL1 (CANx Control 1)...................................... 313
CxCTRL2 (CANx Control 2)...................................... 314
CxEC (CANx Transmit/Receive Error Count) ........... 320
CxFCTRL (CANx FIFO Control) ............................... 316
CxFEN1 (CANx Acceptance Filter Enable 1)............ 322
CxFIFO (CANx FIFO Status) .................................... 317
CxFMSKSEL1 (CANx Filters 7-0
Mask Selection 1) ............................................. 326
CxFMSKSEL2 (CANx Filters 15-8
Mask Selection 2) ............................................. 327
CxINTE (CANx Interrupt Enable).............................. 319
CxINTF (CANx Interrupt Flag) .................................. 318
CxRXFnEID (CANx Acceptance Filter n
Blanking Control).............................................. 212
LEBDLYx (PWMx Leading-Edge
Blanking Delay) ................................................ 213
LFSR (Linear Feedback Shift).................................. 116
MDC (PWM Master Duty Cycle)............................... 199
NVMADR (Nonvolatile Memory Lower Address)........ 69
NVMADRU (Nonvolatile Memory Upper Address) ..... 69
NVMCON (Nonvolatile Memory (NVM) Control) ........ 67
NVMKEY (Nonvolatile Memory Key).......................... 70
NVMSRCADR (NVM Source Data Address).............. 70
OCxCON1 (Output Compare x Control 1)................ 184
OCxCON2 (Output Compare x Control 2)................ 186
ODCx (PORTx Open-Drain Control) ........................ 134
OSCCON (Oscillator Control)................................... 109
OSCTUN (FRC Oscillator Tuning)............................ 113
PDCx (PWMx Generator Duty Cycle)....................... 202
PGAxCAL (PGAx Calibration) .................................. 348
PGAxCON (PGAx Control)....................................... 347
PHASEx (PWMx Primary Phase-Shift)..................... 203
PLLFBD (PLL Feedback Divisor) ............................. 112
PMD1 (Peripheral Module Disable Control 1) .......... 120
PMD2 (Peripheral Module Disable Control 2) .......... 122
PMD3 (Peripheral Module Disable Control 3) .......... 123
PMD4 (Peripheral Module Disable Control 4) .......... 123
PMD6 (Peripheral Module Disable Control 6) .......... 124
PMD7 (Peripheral Module Disable Control 7) .......... 125
PMD8 (Peripheral Module Disable Control 8) .......... 126
PORTx (I/O PORTx)................................................. 133
PTCON (PWM Time Base Control).......................... 193
PTCON2 (PWM Clock Divider Select)...................... 194
PTGADJ (PTG Adjust).............................................. 227
PTGBTE (PTG Broadcast Trigger Enable)............... 222
PTGC0LIM (PTG Counter 0 Limit) ........................... 225
PTGC1LIM (PTG Counter 1 Limit) ........................... 226
PTGCON (PTG Control)........................................... 221
PTGCST (PTG Control/Status) ................................ 219
PTGHOLD (PTG Hold)............................................. 226
PTGL0 (PTG Literal 0).............................................. 227
PTGQPTR (PTG Step Queue Pointer)..................... 228
PTGQUEx (PTG Step Queue x)............................... 228
PTGSDLIM (PTG Step Delay Limit) ......................... 225
PTGT0LIM (PTG Timer0 Limit) ................................ 224
PTGT1LIM (PTG Timer1 Limit) ................................ 224
PTPER (PWM Primary Master
Extended Identifier)........................................... 325
CxRXFnSID (CANx Acceptance Filter n
Standard Identifier) ........................................... 325
CxRXFUL1 (CANx Receive Buffer Full 1)................. 329
CxRXFUL2 (CANx Receive Buffer Full 2)................. 329
CxRXMnEID (CANx Acceptance Filter Mask n
Extended Identifier)........................................... 328
CxRXMnSID (CANx Acceptance Filter Mask n
Standard Identifier) ........................................... 328
CxRXOVF1 (CANx Receive Buffer Overflow 1)........ 330
CxRXOVF2 (CANx Receive Buffer Overflow 2)........ 330
CxTRmnCON (CANx TX/RX Buffer mn Control) ...... 331
CxVEC (CANx Interrupt Code) ................................. 315
DEVID (Device ID).................................................... 358
DEVREV (Device Revision)...................................... 358
DMALCA (DMA Last Channel Active Status) ........... 102
DMAPPS (DMA Ping-Pong Status) .......................... 103
DMAPWC (DMA Peripheral Write
Collision Status)................................................ 100
DMARQC (DMA Request Collision Status) .............. 101
DMAxCNT (DMA Channel x Transfer Count) ............. 98
DMAxCON (DMA Channel x Control)......................... 94
DMAxPAD (DMA Channel x Peripheral Address)....... 98
DMAxREQ (DMA Channel x IRQ Select) ................... 95
DMAxSTAH (DMA Channel x
Start Address A, High) ........................................ 96
DMAxSTAL (DMA Channel x
Start Address A, Low)......................................... 96
DMAxSTBH (DMA Channel x
Start Address B, High) ........................................ 97
DMAxSTBL (DMA Channel x
Time Base Period)............................................ 195
PWMCAPx (PWMx Primary
Start Address B, Low)......................................... 97
DSADRH (DMA Most Recent RAM High Address)..... 99
DSADRL (DMA Most Recent RAM Low Address)...... 99
DTRx (PWMx Dead-Time)........................................ 205
FCLCONx (PWMx Fault Current-Limit Control)........ 209
I2CxCONH (I2Cx Control High) ................................ 253
I2CxCONL (I2Cx Control Low).................................. 251
I2CxMSK (I2Cx Slave Mode Address Mask) ............ 256
I2CxSTAT (I2Cx Status) ........................................... 254
ICxCON1 (Input Capture x Control 1)....................... 180
ICxCON2 (Input Capture x Control 2)....................... 181
INTCON1 (Interrupt Control 1).................................... 86
INTCON2 (Interrupt Control 2).................................... 88
INTCON3 (Interrupt Control 3).................................... 89
INTCON4 (Interrupt Control 4).................................... 89
Time Base Capture) ......................................... 215
PWMCONx (PWMx Control) .................................... 200
PWMKEY (PWM Protection Lock/Unlock Key) ........ 199
RCON (Reset Control)................................................ 73
REFOCON (Reference Oscillator Control)............... 115
RPINR0 (Peripheral Pin Select Input 0) ................... 144
RPINR1 (Peripheral Pin Select Input 1) ................... 144
RPINR11 (Peripheral Pin Select Input 11) ............... 147
RPINR12 (Peripheral Pin Select Input 12) ............... 147
RPINR13 (Peripheral Pin Select Input 13) ............... 148
RPINR18 (Peripheral Pin Select Input 18) ............... 148
RPINR19 (Peripheral Pin Select Input 19) ............... 149
RPINR2 (Peripheral Pin Select Input 2) ................... 145
RPINR20 (Peripheral Pin Select Input 20) ............... 149
2016-2018 Microchip Technology Inc.
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RPINR21 (Peripheral Pin Select Input 21)................150
RPINR22 (Peripheral Pin Select Input 22)................150
RPINR23 (Peripheral Pin Select Input 23)................151
RPINR26 (Peripheral Pin Select Input 26)................151
RPINR29 (Peripheral Pin Select Input 29)................152
RPINR3 (Peripheral Pin Select Input 3)....................145
RPINR30 (Peripheral Pin Select Input 30)................152
RPINR37 (Peripheral Pin Select Input 37)................153
RPINR38 (Peripheral Pin Select Input 38)................153
RPINR42 (Peripheral Pin Select Input 42)................154
RPINR43 (Peripheral Pin Select Input 43)................154
RPINR45 (Peripheral Pin Select Input 45)................155
RPINR46 (Peripheral Pin Select Input 46)................155
RPINR7 (Peripheral Pin Select Input 7)....................146
RPINR8 (Peripheral Pin Select Input 8)....................146
RPOR0 (Peripheral Pin Select Output 0)..................156
RPOR1 (Peripheral Pin Select Output 1)..................156
RPOR10 (Peripheral Pin Select Output 10)..............161
RPOR11 (Peripheral Pin Select Output 11)..............161
RPOR12 (Peripheral Pin Select Output 12)..............162
RPOR13 (Peripheral Pin Select Output 13)..............162
RPOR14 (Peripheral Pin Select Output 14)..............163
RPOR15 (Peripheral Pin Select Output 15)..............163
RPOR16 (Peripheral Pin Select Output 16)..............164
RPOR17 (Peripheral Pin Select Output 17)..............164
RPOR18 (Peripheral Pin Select Output 18)..............165
RPOR19 (Peripheral Pin Select Output 19)..............165
RPOR2 (Peripheral Pin Select Output 2)..................157
RPOR20 (Peripheral Pin Select Output 20)..............166
RPOR21 (Peripheral Pin Select Output 21)..............166
RPOR22 (Peripheral Pin Select Output 22)..............167
RPOR23 (Peripheral Pin Select Output 23)..............167
RPOR24 (Peripheral Pin Select Output 24)..............168
RPOR25 (Peripheral Pin Select Output 25)..............168
RPOR26 (Peripheral Pin Select Output 26)..............169
RPOR3 (Peripheral Pin Select Output 3)..................157
RPOR4 (Peripheral Pin Select Output 4)..................158
RPOR5 (Peripheral Pin Select Output 5)..................158
RPOR6 (Peripheral Pin Select Output 6)..................159
RPOR7 (Peripheral Pin Select Output 7)..................159
RPOR8 (Peripheral Pin Select Output 8)..................160
RPOR9 (Peripheral Pin Select Output 9)..................160
SDCx (PWMx Secondary Duty Cycle) ......................202
SEVTCMP (PWM Special Event Compare)..............195
SPHASEx (PWMx Secondary Phase-Shift)..............204
SPIxCON1H (SPIx Control 1 High)...........................238
SPIxCON1L (SPIx Control 1 Low) ............................236
SPIxCON2L (SPIx Control 2 Low) ............................240
SPIxIMSKH (SPIx Interrupt Mask High)....................245
SPIxIMSKL (SPIx Interrupt Mask Low) .....................244
SPIxSTATH (SPIx Status High)................................243
SPIxSTATL (SPIx Status Low) .................................241
SR (CPU STATUS)...............................................28, 84
SSEVTCMP (PWM Secondary
STRIGx (PWMx Secondary Trigger
Compare Value) ............................................... 211
T1CON (Timer1 Control) .......................................... 173
TRGCONx (PWMx Trigger Control) ......................... 206
TRIGx (PWMx Primary Trigger Compare Value)...... 208
TRISx (PORTx Data Direction Control) .................... 133
TxCON (Timer2/4 Control)........................................ 177
TyCON (Timer3/5 Control)........................................ 178
UxMODE (UARTx Mode).......................................... 259
UxSTA (UARTx Status and Control)......................... 261
Resets................................................................................. 71
Brown-out Reset (BOR).............................................. 71
Configuration Mismatch Reset (CM)........................... 71
Illegal Condition Reset (IOPUWR).............................. 71
Illegal Opcode..................................................... 71
Security............................................................... 71
Uninitialized W Register ..................................... 71
Master Clear (MCLR) Pin Reset................................. 71
Power-on Reset (POR)............................................... 71
RESETInstruction (SWR)............................................ 71
Resources .................................................................. 72
Trap Conflict Reset (TRAPR) ..................................... 71
Watchdog Timer Time-out Reset (WDTO) ................. 71
Revision History................................................................ 469
S
Serial Peripheral Interface (SPI)....................................... 233
Serial Peripheral Interface. See SPI.
SFR Blocks
000h............................................................................ 42
100h............................................................................ 42
200h............................................................................ 43
300h............................................................................ 43
400h............................................................................ 44
500h............................................................................ 44
600h............................................................................ 45
700h............................................................................ 46
800h............................................................................ 47
900h............................................................................ 47
A00h ........................................................................... 48
B00h ........................................................................... 48
C00h-D00h ................................................................. 49
E00h-F00h.................................................................. 50
Software Simulator
MPLAB X SIM........................................................... 377
Special Features of the CPU ............................................ 351
T
Thermal Operating Conditions.......................................... 380
Thermal Packaging Characteristics.................................. 380
Third-Party Development Tools........................................ 378
Timer1............................................................................... 171
Control Register........................................................ 173
Mode Settings........................................................... 171
Resources ................................................................ 172
Timer2/3 and Timer4/5 ..................................................... 175
Control Registers...................................................... 177
Resources ................................................................ 175
Special Event Compare)...................................198
STCON (PWM Secondary Master
Time Base Control)...........................................196
STCON2 (PWM Secondary
Clock Divider Select).........................................197
STPER (PWM Secondary Master
Time Base Period) ............................................197
DS70005258C-page 476
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
Timing Diagrams
BOR and Master Clear Reset Characteristics .......... 395
CANx I/O................................................................... 430
U
UART
Unique Device Identifier (UDID) ......................................... 34
Universal Asynchronous Receiver
External Clock........................................................... 392
High-Speed PWMx Fault Characteristics.................. 401
High-Speed PWMx Module Characteristics.............. 401
I/O Characteristics .................................................... 395
I2Cx Bus Data (Master Mode) .................................. 426
I2Cx Bus Data (Slave Mode) .................................... 428
I2Cx Bus Start/Stop Bits (Master Mode)................... 426
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 428
Input Capture x (ICx) Characteristics........................ 399
OCx/PWMx Characteristics ...................................... 400
Output Compare x (OCx) Characteristics ................. 400
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
CKE = 0, CKP = x, SMP = 1)............................ 405
SPI1, SPI2 and SPI3 Master Mode (Full-Duplex,
CKE = 1, CKP = x, SMP = 1)............................ 404
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex,
Transmit Only, CKE = 0)................................... 402
SPI1, SPI2 and SPI3 Master Mode (Half-Duplex,
Transmit Only, CKE = 1)................................... 403
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 0, CKP = 0, SMP = 0)............................ 412
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 0, CKP = 1, SMP = 0)............................ 410
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 1, CKP = 0, SMP = 0)............................ 406
SPI1, SPI2 and SPI3 Slave Mode (Full-Duplex,
CKE = 1, CKP = 1, SMP = 0)............................ 408
SPI3 Master Mode (Full-Duplex, CKE = 0,
Transmitter (UART) .................................................. 257
Control Registers...................................................... 259
Helpful Tips............................................................... 258
Resources ................................................................ 258
Universal Asynchronous Receiver Transmitter. See UART.
User OTP Memory............................................................ 359
V
Voltage Regulator (On-Chip) ............................................ 359
W
Watchdog Timer (WDT)............................................ 351, 360
Programming Considerations................................... 360
WWW Address ................................................................. 478
WWW, On-Line Support ..................................................... 10
CKP = x, SMP = 1) ........................................... 417
SPI3 Master Mode (Full-Duplex, CKE = 1,
CKP = x, SMP = 1) ........................................... 416
SPI3 Master Mode (Half-Duplex,
Transmit Only, CKE = 0)................................... 414
SPI3 Master Mode (Half-Duplex,
Transmit Only, CKE = 1)................................... 415
SPI3 Slave Mode (Full-Duplex, CKE = 0,
CKP = 0, SMP = 0) ........................................... 424
SPI3 Slave Mode (Full-Duplex, CKE = 0,
CKP = 1, SMP = 0) ........................................... 422
SPI3 Slave Mode (Full-Duplex, CKE = 1,
CKP = 0, SMP = 0) ........................................... 418
SPI3 Slave Mode (Full-Duplex, CKE = 1,
CKP = 1, SMP = 0) ........................................... 420
Timer1-Timer5 External Clock Characteristics ......... 397
UARTx I/O Characteristics........................................ 431
2016-2018 Microchip Technology Inc.
DS70005258C-page 477
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 478
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
Technical support is available through the website
at: http://microchip.com/support
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2016-2018 Microchip Technology Inc.
DS70005258C-page 479
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 480
2016-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X FAMILY
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
dsPIC 33 EP 64 GS8 04 T - I / PT XXX
dsPIC33EP64GS804-I/PT:
dsPIC33, Enhanced Performance,
64-Kbyte Program Memory, SMPS,
44-Pin, Industrial Temperature,
TQFP Package.
Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (Kbyte)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
=
=
=
16-Bit Digital Signal Controller
Enhanced Performance
SMPS Family
Flash Memory Family:
Product Group:
Pin Count:
EP
GS
02
04
05
06
08
=
=
=
=
=
28-pin
44-pin
48-pin
64-pin
80-pin
Temperature Range:
Package:
I
=
=
-40C to +85C (Industrial)
-40C to +125C (Extended)
E
ML
MM
2N
PT
PT
PT
PT
SO
=
=
=
=
=
=
=
=
Plastic Quad, No Lead Package – (44-pin) 8x8 mm body (QFN)
Plastic Quad, No Lead Package – (28-pin) 6x6 mm body (QFN-S)
Plastic Quad Flat, No Lead Package – (28-pin) 6x6 mm body (UQFN)
Plastic Thin Quad Flatpack – (44-pin) 10x10 mm body (TQFP)
Plastic Thin Quad Flatpack – (48-pin) 7x7 mm body (TQFP)
Plastic Thin Quad Flatpack – (64-pin) 10x10 mm body (TQFP)
Plastic Thin Quad Flatpack – (80-pin) 12x12 mm body (TQFP)
Plastic Small Outline, Wide – (28-pin) 7.50 mm body (SOIC)
2016-2018 Microchip Technology Inc.
DS70005258C-page 481
dsPIC33EPXXXGS70X/80X FAMILY
NOTES:
DS70005258C-page 482
2016-2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3795-6
== ISO/TS 16949 ==
2016-2018 Microchip Technology Inc.
DS70005258C-page 483
Worldwide Sales and Service
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DS70005258C-page 484
2016-2018 Microchip Technology Inc.
08/15/18
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