DSPIC33EPGS02-TI/SS_技术文档

dsPIC33EPXXGS202 FAMILY

16-Bit Digital Signal Controllers for Digital Power Applications with

Interconnected High-Speed PWM, ADC, PGA and Comparators

Operating Conditions

Advanced Analog Features

• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS

• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS

• High-Speed ADC module:

- 12-bit with 2 dedicated SAR ADC cores and

one shared SAR ADC core

Flash Architecture

- Up to 3.25 Msps conversion rate per ADC core @

12-bit resolution

• 16 Kbytes-32 Kbytes of Program Flash

- Dedicated result buffer for each analog

channel

Core: 16-Bit dsPIC33E CPU

- Flexible and independent ADC trigger

sources

• Code-Efficient (C and Assembly) Architecture

• Two 40-Bit Wide Accumulators

- Two digital comparators

- One oversampling filter

• Single-Cycle (MAC/MPY) with Dual Data Fetch

• Single-Cycle Mixed-Sign MUL Plus

Hardware Divide

•

Two Rail-to-Rail Comparators with Hysteresis:

- Dedicated 12-bit Digital-to-Analog Converter

(DAC) for each analog comparator

• 32-Bit Multiply Support

• Two Additional Working Register Sets (reduces

context switching)

• Two Programmable Gain Amplifiers:

- Single-ended or independent ground

reference

Clock Management

- Five selectable gains (4x, 8x, 16x, 32x

and 64x)

• ±0.9% Internal Oscillator

• Programmable PLLs and Oscillator Clock Sources

• Fail-Safe Clock Monitor (FSCM)

• Independent Watchdog Timer (WDT)

• Fast Wake-up and Start-up

- 40 MHz gain bandwidth

Interconnected SMPS Peripherals

• Reduces CPU Interaction to Improve Performance

• Flexible PWM Trigger Options for

ADC Conversions

Power Management

• Low-Power Management modes (Sleep,

Idle, Doze)

• High-Speed Comparator Truncates PWM

(15 ns typical):

• Integrated Power-on Reset and Brown-out Reset

• 0.5 mA/MHz Dynamic Current (typical)

• 10 μA IPD Current (typical)

- Supports Cycle-by-Cycle Current mode control

- Current Reset mode (variable frequency)

Timers/Output Compare/Input Capture

High-Speed PWM

• Three 16-Bit and One 32-Bit Timers/Counters

• Three PWM Generators (two outputs per

generator)

• One Output Compare (OC) module, Configurable

as Timers/Counters

• Individual Time Base and Duty Cycle for each PWM

• One Input Capture (IC) module

• 1.04 ns PWM Resolution (frequency, duty cycle,

dead time and phase)

• Supports Center-Aligned, Redundant, Complementary

and True Independent Output modes

• Independent Fault and Current-Limit Inputs

• Output Override Control

• PWM Support for:

- AC/DC, DC/DC, inverters, PFC, lighting

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DS70005208E-page 1

dsPIC33EPXXGS202 FAMILY

Communication Interfaces

Qualification and Class B Support

• One UART module (15 Mbps):

- Supports LIN/J2602 protocols and IrDA^®

• AEC-Q100 REVG (Grade 1, -40°C to +125°C)

• Class B Safety Library, IEC 60730

• One 4-Wire SPI module (15 Mbps)

• 4x4x0.6 mm and 6x6x0.5 mm UQFN Packages

are Designed and Optimized to ease IPC9592B

2nd Level Temperature Cycle Qualification

2

• One I C module (up to 1 Mbaud) with SMBus

Support

Debugger Development Support

Input/Output

• In-Circuit and In-Application Programming

• Sink/Source up to 12mA/15mA, respectively;

Pin-Specific for Standard VOH/VOL

• Three Program and One Complex

Data Breakpoint

• 5V Tolerant Pins

• IEEE 1149.2 Compatible (JTAG) Boundary Scan

• Trace and Run-Time Watch

• Selectable Open-Drain, Pull-ups and Pull-Downs

• External Interrupts on All I/O Pins

• Peripheral Pin Select (PPS) to allow Function

Remap with Six Virtual I/Os

TABLE 1:

dsPIC33EPXXGS202 FAMILY DEVICES

Remappable Peripherals

Device

dsPIC33EP16GS202 28 16K 2K

dsPIC33EP32GS202 28 32K 2K

3

1

3

3x2 12

1

3

2

21 SSOP, SOIC, QFN-S,

UQFN (4x4 mm),

21

UQFN (6x6 mm)

Note 1: The external clock for Timer1, Timer2 and Timer3 is remappable.

2: INT0 is not remappable; INT1 and INT2 are remappable.

DS70005208E-page 2

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dsPIC33EPXXGS202 FAMILY

Pin Diagrams

= Pins are up to 5V tolerant

28-Pin SOIC,

28-Pin SSOP

1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

AVDD

AVSS

RA3

MCLR

RA0

2

RA1

3

RA2

4

RA4

RB0

5

RB14

RB13

RB12

RB11

RB9

6

RB10

7

V

SS

8

RB1

RB2⁽²⁾

RB3

9

V

CAP

SS

10

11

12

13

14

V

RB7

RB6

RB5

RB15

RB4

V

DD

RB8

PIN FUNCTION DESCRIPTIONS

Pin Function

1

2

MCLR

AN0/PGA1P1/CMP1A/RA0

AN1/PGA1P2/PGA2P1/CMP1B/RA1

15

16

17

18

19

20

21

22

23

24

25

26

27

28

PGEC3/RP47/RB15

TDO/AN9/PGA2N2/RP37/RB5

PGED1/TDI/AN10/SCL1/RP38/RB6

PGEC1/AN11/SDA1/RP39/RB7

3

4

AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2

AN3/PGA2P3/CMP1D/CMP2B/RP32/RB0

AN4/CMP2C/RP41/RB9

5

V

SS

6

CAP

7

AN5/CMP2D/RP42/RB10

TMS/PWM3H/RP43/RB11

TCK/PWM3L/RP44/RB12

PWM2H/RP45/RB13

PWM2L/RP46/RB14

PWM1H/RA4

8

VSS

9

OSC1/CLKI/AN6/RP33/RB1

10

11

12

13

14

OSC2/CLKO/AN7/PGA1N2/RP34/RB2⁽²⁾

PGED2/AN8/INT0/RP35/RB3

PGEC2/ADTRG31/RP36/RB4

PWM1L/RA3

V

DD

AVSS

PGED3/FLT31/RP40/RB8

AVDD

Legend: Shaded pins are up to 5 VDC tolerant.

Note 1: RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.

2: At device power-up, a pulse with an amplitude around 2V and a duration greater than 500 μs, may be observed on this device

pin, independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being driven

can endure this active duration.

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DS70005208E-page 3

dsPIC33EPXXGS202 FAMILY

Pin Diagrams (Continued)

28-Pin UQFN, 28-Pin UQFN,

28-Pin QFN-S

= Pins are up to 5V tolerant

28 27 26 25 24 23 22

RA2

RB0

1

2

3

4

5

6

7

21

20

19

18

17

16

15

RB14

RB13

RB12

RB11

RB9

dsPIC33EPXXGS202

RB10

V

SS

V

CAP

SS

RB1

RB2⁽²⁾

RB7

8

9

10 11 12 13 14

PIN FUNCTION DESCRIPTIONS

Pin Function

PGEC1/AN11/SDA1/RP39/RB7

1

2

AN2/PGA1P3/PGA2P2/CMP1C/CMP2A/RA2

AN3/PGA2P3/CMP1D/ CMP28/RP32/RB0

AN4/CMP2C/RP41/RB9

15

16

17

18

19

20

21

22

23

24

25

26

27

28

V

SS

3

CAP

4

AN5/CMP2D/RP42/RB10

TMS/PWM3H/RP43/RB11

TCK/PWM3L/RP44/RB12

PWM2H/RP45/RB13

PWM2L/RP46/RB14

PWM1H/RA4

5

VSS

6

OSC1/CLKI/AN6/RP33/RB1

7

OSC2/CLKO/AN7/PGA1N2/RP34/RB2⁽²⁾

PGED2/AN8/INT0/RP35/RB3

PGEC2/ADTRG31/RP36/RB4

8

9

PWM1L/RA3

10

11

12

13

14

V

DD

AVSS

PGED3/FLT31/RP40/RB8

PGEC3/RP47/RB15

AVDD

MCLR

TDO/AN9/PGA2N2/RP37/RB5

PGED1/TDI/AN10/SCL1/RP38/RB6

AN0/PGA1P1/CMP1A/RA0

AN1/PGA1P2/PGA2P1/CMP1B/RA1

Legend: Shaded pins are up to 5 VDC tolerant.

Note 1: RPn represents remappable peripheral functions. See Table 10-1 and Table 10-2 for the complete list of remappable sources.

2: At device power-up, a pulse with an amplitude around 2V and a duration greater than 500 μs, may be observed on this device

pin, independent of pull-down resistors. It is recommended not to use this pin as an output driver unless the circuit being driven

can endure this active duration.

DS70005208E-page 4

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dsPIC33EPXXGS202 FAMILY

Table of Contents

1.0 Device Overview .......................................................................................................................................................................... 7

2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 11

3.0 CPU............................................................................................................................................................................................ 17

4.0 Memory Organization................................................................................................................................................................. 27

5.0 Flash Program Memory.............................................................................................................................................................. 61

6.0 Resets ....................................................................................................................................................................................... 69

7.0 Interrupt Controller ..................................................................................................................................................................... 73

8.0 Oscillator Configuration.............................................................................................................................................................. 87

9.0 Power-Saving Features.............................................................................................................................................................. 97

10.0 I/O Ports ................................................................................................................................................................................... 105

11.0 Timer1 ...................................................................................................................................................................................... 131

12.0 Timer2/3 .................................................................................................................................................................................. 135

13.0 Input Capture............................................................................................................................................................................ 139

14.0 Output Compare....................................................................................................................................................................... 143

15.0 High-Speed PWM..................................................................................................................................................................... 149

16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 175

2

17.0 Inter-Integrated Circuit (I C)..................................................................................................................................................... 183

18.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 191

19.0 High-Speed, 12-Bit Analog-to-Digital Converter (ADC)............................................................................................................ 197

20.0 High-Speed Analog Comparator .............................................................................................................................................. 227

21.0 Programmable Gain Amplifier (PGA) ....................................................................................................................................... 233

22.0 Special Features ...................................................................................................................................................................... 239

23.0 Instruction Set Summary.......................................................................................................................................................... 251

24.0 Development Support............................................................................................................................................................... 261

25.0 Electrical Characteristics.......................................................................................................................................................... 265

26.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 311

27.0 Packaging Information.............................................................................................................................................................. 315

Appendix A: Revision History............................................................................................................................................................. 331

Index ................................................................................................................................................................................................. 333

The Microchip Web Site..................................................................................................................................................................... 339

Customer Change Notification Service .............................................................................................................................................. 339

Customer Support.............................................................................................................................................................................. 339

Product Identification System ............................................................................................................................................................ 341

 2015-2018 Microchip Technology Inc.

DS70005208E-page 5

dsPIC33EPXXGS202 FAMILY

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip

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If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

Errata

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DS70005208E-page 6

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dsPIC33EPXXGS202 FAMILY

This document contains device-specific information for

the dsPIC33EPXXGS202 Digital Signal Controller (DSC)

1.0

DEVICE OVERVIEW

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

devices. It is not intended to be a com-

prehensive resource. To complement the

information in this data sheet, refer to the

related section in the “dsPIC33/PIC24

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

devices.

The dsPIC33EPXXGS202 devices contain extensive

Digital Signal Processor (DSP) functionality with a

high-performance, 16-bit MCU architecture.

Figure 1-1 shows a general block diagram of the core

and peripheral modules. Table 1-1 lists the functions of

the various pins shown in the pinout diagrams.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific

register and bit information.

FIGURE 1-1:

dsPIC33EPXXGS202 FAMILY BLOCK DIAGRAM

CPU

Refer to Figure 3-1 for CPU diagram details.

PORTA

16

Power-up

Timer

PORTB

Oscillator

Timing

Start-up

Generation

Timer

16

OSC1/CLKI

POR/BOR

MCLR

Watchdog

Timer

V

DD, VSS

AVDD, AVSS

Peripheral Modules

Output

Compare 1

PGA1,

PGA2

Input

Capture 1

ADC

I2C1

Remappable

Pins

Analog

Comparator

1-2

Ports

PWM

3x2

Timers

1-3

UART1

SPI1

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DS70005208E-page 7

dsPIC33EPXXGS202 FAMILY

TABLE 1-1:

Pin Name

PINOUT I/O DESCRIPTIONS

Pin Buffer

PPS

Description

Type Type

AN0-AN11

CLKI

I

Analog No Analog input channels.

ST/

CMOS

—

No External clock source input. Always associated with OSC1 pin

function.

No Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes.

Always associated with OSC2 pin function.

CLKO

O

OSC1

OSC2

I

ST/

CMOS

—

No Oscillator crystal input. ST buffer when configured in RC mode; CMOS

otherwise.

No Oscillator crystal output. Connects to crystal or resonator in Crystal

Oscillator mode. Optionally functions as CLKO in RC and EC modes.

I/O

IC1

I

ST

Yes Capture Input 1.

OCFA

OC1

I

O

ST

—

Yes Compare Fault A input (for compare channels).

Yes Compare Output 1.

INT0

INT1

INT2

I

ST

No External Interrupt 0.

Yes External Interrupt 1.

Yes External Interrupt 2.

RA0-RA4

I/O

ST

No PORTA is a bidirectional I/O port.

No PORTB is a bidirectional I/O port.

RB0-RB15

T1CK

T2CK

T3CK

I

ST

Yes Timer1 external clock input.

Yes Timer2 external clock input.

Yes Timer3 external clock input.

U1CTS

U1RTS

U1RX

U1TX

BCLK1

I

O

I

O

ST

—

ST

—

Yes UART1 Clear-to-Send.

Yes UART1 Request-to-Send.

Yes UART1 receive.

Yes UART1 transmit.

®

ST

Yes UART1 IrDA baud clock output.

SCK1

SDI1

SDO1

SS1

I/O

I

O

ST

—

Yes Synchronous serial clock input/output for SPI1.

Yes SPI1 data in.

Yes SPI1 data out.

I/O

ST

Yes SPI1 slave synchronization or frame pulse I/O.

SCL1

SDA1

I/O

ST

No Synchronous serial clock input/output for I2C1.

No Synchronous serial data input/output for I2C1.

TMS

TCK

TDI

I

ST

—

No JTAG Test mode select pin.

No JTAG test clock input pin.

No JTAG test data input pin.

No JTAG test data output pin.

TDO

O

FLT1-FLT8

FLT31

PWM1L-PWM3L

PWM1H-PWM3H

SYNCI1, SYNCI2

SYNCO1, SYNCO2

I

O

I

ST

—

ST

—

Yes PWM Fault Inputs 1 through 8.

No PWM Fault Input 31.

No PWM Low Outputs 1 through 3.

No PWM High Outputs 1 through 3.

Yes PWM Synchronization Inputs 1 and 2.

Yes PWM Synchronization Outputs 1 and 2.

O

CMP1A-CMP2A

CMP1B-CMP2B

CMP1C-CMP2C

CMP1D-CMP2D

I

Analog No Comparator Channels 1A through 2A inputs.

Analog No Comparator Channels 1B through 2B inputs.

Analog No Comparator Channels 1C through 2C inputs.

Analog No Comparator Channels 1D through 2D inputs.

Legend: CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

PPS = Peripheral Pin Select

Analog = Analog input

O = Output

TTL = TTL input buffer

P = Power

I = Input

DS70005208E-page 8

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TABLE 1-1:

Pin Name

PINOUT I/O DESCRIPTIONS (CONTINUED)

Pin Buffer

Type Type

PPS

Description

PGA1P1-PGA1P3

PGA1N2

I

Analog No PGA1 Positive Inputs 1 through 3.

Analog No PGA1 Negative Input 2.

PGA2P1-PGA2P3

PGA2N2

Analog No PGA2 Positive Inputs 1 through 3.

Analog No PGA2 Negative Input 2.

ADTRG31

ST

No External ADC trigger source.

PGED1

PGEC1

PGED2

PGEC2

PGED3

PGEC3

I/O

ST

No Data I/O pin for Programming/Debugging Communication Channel 1.

No Clock input pin for Programming/Debugging Communication Channel 1.

No Data I/O pin for Programming/Debugging Communication Channel 2.

No Clock input pin for Programming/Debugging Communication Channel 2.

No Data I/O pin for Programming/Debugging Communication Channel 3.

No Clock input pin for Programming/Debugging Communication Channel 3.

I

I/O

I

I/O

I

MCLR

AVDD

I/P

P

ST

P

No Master Clear (Reset) input. This pin is an active-low Reset to the device.

No Positive supply for analog modules. This pin must be connected at all

times.

AVSS

P

No Ground reference for analog modules. This pin must be connected at

all times.

V

DD

P

—

No Positive supply for peripheral logic and I/O pins.

No CPU logic filter capacitor connection.

CAP

SS

No Ground reference for logic and I/O pins.

Legend: CMOS = CMOS compatible input or output

ST = Schmitt Trigger input with CMOS levels

PPS = Peripheral Pin Select

Analog = Analog input

O = Output

TTL = TTL input buffer

P = Power

I = Input

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DS70005208E-page 9

dsPIC33EPXXGS202 FAMILY

NOTES:

DS70005208E-page 10

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dsPIC33EPXXGS202 FAMILY

2.2

Decoupling Capacitors

2.0

GUIDELINES FOR GETTING

STARTED WITH 16-BIT DIGITAL

SIGNAL CONTROLLERS

The use of decoupling capacitors on every pair of

power supply pins, such as VDD, VSS, AVDD and

AVSS is required.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

Consider the following criteria when using decoupling

capacitors:

• Value and type of capacitor: Recommendation

of 0.1 µF (100 nF), 10-20V. This capacitor should

be a low-ESR and have resonance frequency in

the range of 20 MHz and higher. It is

recommended to use ceramic capacitors.

• Placement on the printed circuit board: The

decoupling capacitors should be placed as close

to the pins as possible. It is recommended to

place the capacitors on the same side of the

board as the device. If space is constricted, the

capacitor can be placed on another layer on the

PCB using a via; however, ensure that the trace

length from the pin to the capacitor is within

one-quarter inch (6 mm) in length.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

2.1

Basic Connection Requirements

• Handling high-frequency noise: If the board is

experiencing high-frequency noise, above tens of

MHz, add a second ceramic-type capacitor in

parallel to the above described decoupling

capacitor. The value of the second capacitor can

be in the range of 0.01 µF to 0.001 µF. Place this

second capacitor next to the primary decoupling

capacitor. In high-speed circuit designs, consider

implementing a decade pair of capacitances as

close to the power and ground pins as possible.

For example, 0.1 µF in parallel with 0.001 µF.

Getting started with the dsPIC33EPXXGS202 family

requires attention to a minimal set of device pin

connections before proceeding with development. The

following is a list of pin names which must always be

connected:

• All VDD and VSS pins

(see Section 2.2 “Decoupling Capacitors”)

• All AVDD and AVSS pins

regardless if ADC module is not used (see

Section 2.2 “Decoupling Capacitors”)

• Maximizing performance: On the board layout

from the power supply circuit, run the power and

return traces to the decoupling capacitors first,

and then to the device pins. This ensures that the

decoupling capacitors are first in the power chain.

Equally important is to keep the trace length

between the capacitor and the power pins to a

minimum, thereby reducing PCB track

• VCAP

(see Section 2.3 “CPU Logic Filter Capacitor

Connection (VCAP)”)

• MCLR pin

(see Section 2.4 “Master Clear (MCLR) Pin”)

• PGECx/PGEDx pins

used for In-Circuit Serial Programming™ (ICSP™)

and debugging purposes (see Section 2.5 “ICSP

Pins”)

inductance.

• OSC1 and OSC2 pins

when external oscillator source is used (see

Section 2.6 “External Oscillator Pins”)

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dsPIC33EPXXGS202 FAMILY

The placement of this capacitor should be close to the

CAP pin. It is recommended that the trace length not

exceeds one-quarter inch (6 mm). See Section 22.4

“On-Chip Voltage Regulator” for details.

FIGURE 2-1:

RECOMMENDED

MINIMUM CONNECTION

V

0.1 µF

Ceramic

10 µF

VDD

Tantalum

2.4

Master Clear (MCLR) Pin

R

The MCLR pin provides two specific device

functions:

R1

MCLR

• Device Reset

C

• Device Programming and Debugging.

dsPIC33EPXXGS202

During device programming and debugging, the

resistance and capacitance that can be added to the

pin must be considered. Device programmers and

debuggers drive the MCLR pin. Consequently,

specific voltage levels (VIH and VIL) and fast signal

transitions must not be adversely affected. Therefore,

specific values of R and C will need to be adjusted

based on the application and PCB requirements.

V

DD

V

SS

DD

V

SS

0.1 µF

Ceramic

0.1 µF

Ceramic

0.1 µF

Ceramic

(1)

L1

For example, as shown in Figure 2-2, it is

recommended that the capacitor, C, be isolated from

the MCLR pin during programming and debugging

operations.

Note 1: As an option, instead of a hard-wired connection, an

inductor (L1) can be substituted between VDD and

AVDD to improve ADC noise rejection. The inductor

impedance should be less than 1 and the inductor

capacity greater than 10 mA.

Place the components as shown in Figure 2-2 within

one-quarter inch (6 mm) from the MCLR pin.

Where:

F

CNV

f = -------------

(i.e., A/D Conversion Rate/2)

FIGURE 2-2:

EXAMPLE OF MCLR PIN

CONNECTIONS

2

1

f = -----------------------

2 LC

V

DD

²

1



L = ---------------------





(1)

2f C

R

(2)

R1

MCLR

2.2.1

TANK CAPACITORS

JP

C

On boards with power traces running longer than six

inches in length, it is suggested to use a tank capacitor

for integrated circuits including DSCs to supply a local

power source. The value of the tank capacitor should

be determined based on the trace resistance that con-

nects the power supply source to the device and the

maximum current drawn by the device in the applica-

tion. In other words, select the tank capacitor so that it

meets the acceptable voltage sag at the device. Typical

values range from 4.7 µF to 47 µF.

dsPIC33EPXXGS202

Note 1: R  10 k is recommended. A suggested

starting value is 10 k. Ensure that the

MCLR pin VIH and VIL specifications are met.

2: R1  470 will limit any current flowing into

MCLR from the external capacitor, C, in the

event of MCLR pin breakdown due to

Electrostatic Discharge (ESD) or Electrical

Overstress (EOS). Ensure that the MCLR pin

2.3

CPU Logic Filter Capacitor

Connection (VCAP

VIH and VIL specifications are met.

)

A low-ESR (<1 Ohms) capacitor is required on the

CAP pin, which is used to stabilize the voltage

V

regulator output voltage. The VCAP pin must not be

connected to VDD and must have a capacitor greater

than 4.7 µF (10 µF is recommended), 16V connected

to ground. The type can be ceramic or tantalum. See

Section 25.0 “Electrical Characteristics” for

additional information.

DS70005208E-page 12

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2.5

ICSP Pins

2.6

External Oscillator Pins

The PGECx and PGEDx pins are used for ICSP and

debugging purposes. It is recommended to keep the

trace length between the ICSP connector and the ICSP

pins on the device as short as possible. If the ICSP con-

nector is expected to experience an ESD event, a

series resistor is recommended, with the value in the

range of a few tens of Ohms, not to exceed 100 Ohms.

Many DSCs have options for at least two oscillators: a

high-frequency primary oscillator and a low-frequency

secondary oscillator. For details, see Section 8.0

“Oscillator Configuration” for details.

The oscillator circuit should be placed on the same

side of the board as the device. Also, place the oscil-

lator circuit close to the respective oscillator pins, not

exceeding one-half inch (12 mm) distance between

them. The load capacitors should be placed next to

the oscillator itself, on the same side of the board.

Use a grounded copper pour around the oscillator

circuit to isolate them from surrounding circuits. The

grounded copper pour should be routed directly to the

MCU ground. Do not run any signal traces or power

traces inside the ground pour. Also, if using a

two-sided board, avoid any traces on the other side of

the board where the crystal is placed. A suggested

layout is shown in Figure 2-3.

Pull-up resistors, series diodes and capacitors on the

PGECx and PGEDx pins are not recommended as they

will interfere with the programmer/debugger communi-

cations to the device. If such discrete components are

an application requirement, they should be removed

from the circuit during programming and debugging.

Alternatively, refer to the AC/DC characteristics and

timing requirements information in the respective

device Flash programming specification for information

on capacitive loading limits and pin Voltage Input High

(VIH) and Voltage Input Low (VIL) requirements.

Ensure that the “Communication Channel Select”

(i.e., PGECx/PGEDx pins) programmed into the

device matches the physical connections for the

FIGURE 2-3:

SUGGESTED PLACEMENT

OF THE OSCILLATOR

CIRCUIT

®

ICSP to MPLAB PICkit™ 3, MPLAB ICD 3 or MPLAB

REAL ICE™.

For more information on MPLAB ICD 2, MPLAB ICD 3

and REAL ICE connection requirements, refer to the

following documents that are available on the

Microchip web site.

Main Oscillator

Guard Ring

®

• “Using MPLAB ICD 3” (poster) DS51765

Guard Trace

Oscillator Pins

• “Multi-Tool Design Advisory” DS51764

®

• “MPLAB REAL ICE™ In-Circuit Emulator User’s

Guide” DS51616

®

• “Using MPLAB REAL ICE™ In-Circuit Emulator”

(poster) DS51749

 2015-2018 Microchip Technology Inc.

DS70005208E-page 13

dsPIC33EPXXGS202 FAMILY

2.7

Oscillator Value Conditions on

Device Start-up

2.9

Targeted Applications

• Power Factor Correction (PFC):

- Interleaved PFC

If the PLL of the target device is enabled and

configured for the device start-up oscillator, the

maximum oscillator source frequency must be limited

to 3 MHz < FIN < 5.5 MHz to comply with device PLL

start-up conditions. This means that if the external

oscillator frequency is outside this range, the

application must start-up in the FRC mode first. The

default PLL settings after a POR with an oscillator

frequency outside this range will violate the device

operating speed.

- Critical Conduction PFC

- Bridgeless PFC

• DC/DC Converters:

- Buck, Boost, Forward, Flyback, Push-Pull

- Half/Full-Bridge

- Phase-Shift Full-Bridge

- Resonant Converters

• DC/AC:

Once the device powers up, the application firmware

can initialize the PLL SFRs, CLKDIV and PLLDBF to a

suitable value, and then perform a clock switch to the

Oscillator + PLL clock source. Note that clock switching

must be enabled in the device Configuration Word.

- Half/Full-Bridge Inverter

- Resonant Inverter

Examples of typical application connections are shown

in Figure 2-4 through Figure 2-6.

2.8

Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor between VSS

and unused pins and drive the output to logic low.

FIGURE 2-4:

INTERLEAVED PFC

VOUT+

|VAC

|

k

2

1

k

4

VAC

k

3

k

5

VOUT-

FET

Driver

FET

Driver

PGA/ADC Channel

ADC Channel

PWM PGA/ADC PWM PGA/ADC

ADC

Channel

dsPIC33EPXXGS202

Note: k , k and k are gains.

1

2

3

DS70005208E-page 14

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FIGURE 2-5:

PHASE-SHIFTED FULL-BRIDGE CONVERTER

VIN+

Gate 6

Gate 3

Gate 1

VOUT+

S1

S3

G ate 4

VOUT

-

Gate 2

Gate 5

VIN-

Gate 5

FET

Driver

k

2

k

1

Analog

Ground

Gate 1

S1

FET

Driver

PGA/ADC PWM

Channel

ADC

Channel

PWM

Gate 3

dsPIC33EPXXGS202

FET

Driver

S3

PWM

Gate 2

Gate 4

Note: k , k and k are gains.

1

2

3

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dsPIC33EPXXGS202 FAMILY

FIGURE 2-6:

OFF-LINE UPS

V

DC

Full-Bridge Inverter

Push-Pull Converter

V

OUT

+

-

VBAT

+

VOUT

GND

FET

Driver

FET

Driver

k

5

2

1

4

Driver Driver Driver Driver

PWM

ADC

PWM PGA/ADC ADC

PWM

or

Analog Comp.

k

ADC

3

dsPIC33EPXXGS202

Note: k , k , k , k and k are gains.

1

2

3

4

5

DS70005208E-page 16

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3.2

Instruction Set

3.0

CPU

The instruction set for dsPIC33EPXXGS202 devices

has two classes of instructions: the MCU class of

instructions and the DSP class of instructions. These

two instruction classes are seamlessly integrated into the

architecture and execute from a single execution unit.

The instruction set includes many addressing modes and

was designed for optimum C compiler efficiency.

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

devices. It is not intended to be a compre-

hensive reference source. To complement

the information in this data sheet, refer

to “CPU” (DS70359) in the “dsPIC33/

PIC24 Family Reference Manual”, which

is available from the Microchip web site

(www.microchip.com).

3.3

Data Space Addressing

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The base Data Space (DS) can be addressed as 1K word

or 2 Kbytes and is split into two blocks, referred to as X

and Y data memory. Each memory block has its own inde-

pendent Address Generation Unit (AGU). The MCU class

of instructions operates solely through the X memory

AGU, which accesses the entire memory map as one

linear Data Space. Certain DSP instructions operate

through the X and Y AGUs to support dual operand reads,

which splits the data address space into two parts. The X

and Y Data Space boundary is device-specific.

The dsPIC33EPXXGS202 CPU has a 16-bit (data)

modified Harvard architecture with an enhanced

instruction set, including significant support for Digital

Signal Processing (DSP). The CPU has a 24-bit instruc-

tion word with a variable length opcode field. The

Program Counter (PC) is 23 bits wide and addresses up

to 4M x 24 bits of user program memory space.

The upper 32 Kbytes of the Data Space memory map

can optionally be mapped into Program Space (PS) at

any 16K program word boundary. The program-to-Data

Space mapping feature, known as Program Space

Visibility (PSV), lets any instruction access Program

Space as if it were Data Space. Refer to “Data

Memory” (DS70595) in the “dsPIC33/PIC24 Family

Reference Manual” for more details on PSV and table

accesses.

An instruction prefetch mechanism helps maintain

throughput and provides predictable execution. Most

instructions execute in a single-cycle effective execu-

tion rate, with the exception of instructions that change

the program flow, the double-word move (MOV.D)

instruction, PSV accesses and the table instructions.

Overhead-free program loop constructs are supported

using the DO and REPEAT instructions, both of which

are interruptible at any point.

On dsPIC33EPXXGS202 devices, overhead-free

circular buffers (Modulo Addressing) are supported in

both X and Y address spaces. The Modulo Addressing

removes the software boundary checking overhead for

DSP algorithms. The X AGU Circular Addressing can

be used with any of the MCU class of instructions. The

X AGU also supports Bit-Reversed Addressing to

greatly simplify input or output data re-ordering for

radix-2 FFT algorithms.

3.1

Registers

The dsPIC33EPXXGS202 devices have sixteen, 16-bit

Working registers in the programmer’s model. Each of the

Working registers can act as a data, address or address

offset register. The 16th Working register (W15) operates

as a Software Stack Pointer (SSP) for interrupts and calls.

3.4

Addressing Modes

In addition, the dsPIC33EPXXGS202 devices include two

Alternate Working register sets which consist of W0

through W14. The Alternate registers can be made per-

sistent to help reduce the saving and restoring of register

content during Interrupt Service Routines (ISRs). The

Alternate Working registers can be assigned to a specific

Interrupt Priority Level (IPL1 through IPL6) by configuring

the CTXTx<2:0> bits in the FALTREG Configuration

register. The Alternate Working registers can also be

accessed manually by using the CTXTSWP instruction.

The CCTXI<2:0> and MCTXI<2:0> bits in the CTXTSTAT

register can be used to identify the current and most

recent, manually selected Working register sets.

The CPU supports these addressing modes:

• Inherent (no operand)

• Relative

• Literal

• Memory Direct

• Register Direct

• Register Indirect

Each instruction is associated with a predefined

addressing mode group, depending upon its functional

requirements. As many as six addressing modes are

supported for each instruction.

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dsPIC33EPXXGS202 FAMILY

FIGURE 3-1:

dsPIC33EPXXGS202 CPU BLOCK DIAGRAM

X Address Bus

Y Data Bus

X Data Bus

16

Data Latch

Interrupt

Controller

PSV and Table

Data Access

Control Block

Y Data

RAM

X Data

RAM

8

16

24

16

Address

Latch

Address

Latch

24

16

24

X RAGU

X WAGU

PCU PCH

Program Counter

PCL

16

Loop

Control

Logic

Stack

Control

Logic

Address Latch

Program Memory

Data Latch

Y AGU

16

EA MUX

16

24

16

16-Bit

Working Register Arrays

16

Divide

Support

DSP

Engine

16-Bit ALU

16

Instruction

Decode and

Control

Control Signals

to Various Blocks

16

Power, Reset

and Oscillator

Modules

Ports

Peripheral

Modules

DS70005208E-page 18

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dsPIC33EPXXGS202 FAMILY

In addition to the registers contained in the

programmer’s model, the dsPIC33EPXXGS202 devices

contain control registers for Modulo Addressing, Bit-

Reversed Addressing and interrupts. These registers

are described in subsequent sections of this document.

3.5

Programmer’s Model

The programmer’s model for the dsPIC33EPXXGS202

family is shown in Figure 3-2. All registers in the

programmer’s model are memory-mapped and can be

manipulated directly by instructions. Table 3-1 lists a

description of each register.

All registers associated with the programmer’s model

are memory-mapped, as shown in Table 3-1.

TABLE 3-1:

PROGRAMMER’S MODEL REGISTER DESCRIPTIONS

Register(s) Name

Description

(1)

W0 through W15

W0 through W14

ACCA, ACCB

PC

Working Register Array

Alternate Working Register Array 1

Alternate Working Register Array 2

40-Bit DSP Accumulators

23-Bit Program Counter

SR

ALU and DSP Engine STATUS Register

Stack Pointer Limit Value Register

SPLIM

TBLPAG

Table Memory Page Address Register

Extended Data Space (EDS) Read Page Register

REPEATLoop Counter Register

DSRPAG

RCOUNT

DCOUNT

DOLoop Counter Register

(2)

DOSTARTH , DOSTARTL

DOENDH, DOENDL

CORCON

DOLoop Start Address Register (High and Low)

DOLoop End Address Register (High and Low)

Contains DSP Engine, DOLoop Control and Trap Status bits

Note 1: Memory-mapped W0 through W14 represent the value of the register in the currently active CPU context.

2: The DOSTARTH and DOSTARTL registers are read-only.

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dsPIC33EPXXGS202 FAMILY

FIGURE 3-2:

PROGRAMMER’S MODEL

D15

D0

D15

D0

W0 (WREG) W0

W1 W1

W0

W1

W0-W3

W2

W3

W4

W5

W6

W7

W2

W3

W4

W2

W3

W4

DSP Operand

Registers

W5

Alternate

Working/Address

Registers

W6

W7

W6

W7

Working/Address

Registers

W8

W9

W8

DSP Address

Registers

W9 W9

W10 W10

W11 W11

W10

W11

W12

W12 W12

W13 W13 W13

Frame Pointer/W14 W14 W14

0

Stack Pointer/W15

PUSH.Sand POP.SShadows

Stack Pointer Limit

AD15

0

SPLIM

Nested DOStack

AD39

AD31

AD0

ACCA

DSP

Accumulators

(1)

ACCB

PC23

0

PC0

Program Counter

0

7

TBLPAG

Data Table Page Address

9

0

DSRPAG

X Data Space Read Page Address

15

0

RCOUNT

REPEATLoop Counter

DCOUNT

DOLoop Counter and Stack

23

0

DOLoop Start Address and Stack

DOLoop End Address and Stack

0

DOSTART

23

0

DOEND

15

0

CORCON

CPU Core Control Register

SRL

OAB SAB DA DC IPL2 IPL1 IPL0 RA

OA OB SA SB

N

OV

Z

C

STATUS Register

DS70005208E-page 20

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3.6.1

KEY RESOURCES

3.6

CPU Resources

• “CPU” (DS70359) in the “dsPIC33/PIC24 Family

Reference Manual”

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

 2015-2018 Microchip Technology Inc.

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dsPIC33EPXXGS202 FAMILY

3.7

CPU Control Registers

REGISTER 3-1:

SR: CPU STATUS REGISTER

R/W-0

OA

R/W-0

OB

R/W-0

R/C-0

OAB

R/C-0

SAB

R-0

DA

R/W-0

DC

(3)

SA

SB

bit 15

bit 8

(2)

R/W-0

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

(1)

IPL2

IPL1

IPL0

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’= Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

OA: Accumulator A Overflow Status bit

1= Accumulator A has overflowed

0= Accumulator A has not overflowed

OB: Accumulator B Overflow Status bit

1= Accumulator B has overflowed

0= Accumulator B has not overflowed

(3)

SA: Accumulator A Saturation ‘Sticky’ Status bit

1= Accumulator A is saturated or has been saturated at some time

0= Accumulator A is not saturated

(3)

SB: Accumulator B Saturation ‘Sticky’ Status bit

1= Accumulator B is saturated or has been saturated at some time

0= Accumulator B is not saturated

OAB: OA || OB Combined Accumulator Overflow Status bit

1= Accumulators A or B have overflowed

0= Neither Accumulators A or B have overflowed

SAB: SA || SB Combined Accumulator ‘Sticky’ Status bit

1= Accumulators A or B are saturated, or have been saturated at some time

0= Neither Accumulator A or B are saturated

DA: DOLoop Active bit

1= DOloop in progress

0= DOloop not in progress

bit 8

DC: MCU ALU Half Carry/Borrow bit

1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)

of the result occurred

0= No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized

data) of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.

3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not

be modified using bit operations.

DS70005208E-page 22

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REGISTER 3-1:

SR: CPU STATUS REGISTER (CONTINUED)

(1,2)

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits

111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

bit 4

bit 3

bit 2

RA: REPEATLoop Active bit

1= REPEATloop is in progress

0= REPEATloop is not in progress

N: MCU ALU Negative bit

1= Result was negative

0= Result was non-negative (zero or positive)

OV: MCU ALU Overflow bit

This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude that

causes the sign bit to change state.

1= Overflow occurred for signed arithmetic (in this arithmetic operation)

0= No overflow occurred

bit 1

bit 0

Z: MCU ALU Zero bit

1= An operation that affects the Z bit has set it at some time in the past

0= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)

C: MCU ALU Carry/Borrow bit

1= A carry-out from the Most Significant bit of the result occurred

0= No carry-out from the Most Significant bit of the result occurred

Note 1: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

2: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.

3: A data write to the SR register can modify the SA and SB bits by either a data write to SA and SB or by

clearing the SAB bit. To avoid a possible SA or SB bit write race condition, the SA and SB bits should not

be modified using bit operations.

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REGISTER 3-2:

CORCON: CORE CONTROL REGISTER

R/W-0

VAR

U-0

—

R/W-0

US1

R/W-0

US0

R/W-0

R-0

(1)

EDT

DL2

DL1

DL0

bit 15

bit 8

R/W-0

SATA

R/W-0

SATB

R/W-1

R/W-0

R/C-0

R-0

R/W-0

RND

R/W-0

IF

(2)

SATDW

ACCSAT

IPL3

SFA

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

VAR: Variable Exception Processing Latency Control bit

1= Variable exception processing latency

0= Fixed exception processing latency

bit 14

Unimplemented: Read as ‘0’

bit 13-12

US<1:0>: DSP Multiply Unsigned/Signed Control bits

11= Reserved

10= DSP engine multiplies are mixed-sign

01= DSP engine multiplies are unsigned

00= DSP engine multiplies are signed

(1)

bit 11

EDT: Early DOLoop Termination Control bit

1= Terminates executing DOloop at the end of current loop iteration

0= No effect

bit 10-8

DL<2:0>: DOLoop Nesting Level Status bits

111= 7 DOloops are active

•

001= 1 DOloop is active

000= 0 DOloops are active

bit 7

bit 6

bit 5

bit 4

bit 3

SATA: ACCA Saturation Enable bit

1= Accumulator A saturation is enabled

0= Accumulator A saturation is disabled

SATB: ACCB Saturation Enable bit

1= Accumulator B saturation is enabled

0= Accumulator B saturation is disabled

SATDW: Data Space Write from DSP Engine Saturation Enable bit

1= Data Space write saturation is enabled

0= Data Space write saturation is disabled

ACCSAT: Accumulator Saturation Mode Select bit

1= 9.31 saturation (super saturation)

0= 1.31 saturation (normal saturation)

(2)

IPL3: CPU Interrupt Priority Level Status bit 3

1= CPU Interrupt Priority Level is greater than 7

0= CPU Interrupt Priority Level is 7 or less

Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

DS70005208E-page 24

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REGISTER 3-2:

CORCON: CORE CONTROL REGISTER (CONTINUED)

bit 2

bit 1

bit 0

SFA: Stack Frame Active Status bit

1= Stack frame is active; W14 and W15 address of 0x0000 to 0xFFFF, regardless of DSRPAG

0= Stack frame is not active; W14 and W15 address of Base Data Space

RND: Rounding Mode Select bit

1= Biased (conventional) rounding is enabled

0= Unbiased (convergent) rounding is enabled

IF: Integer or Fractional Multiplier Mode Select bit

1= Integer mode is enabled for DSP multiply

0= Fractional mode is enabled for DSP multiply

Note 1: This bit is always read as ‘0’.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

REGISTER 3-3:

CTXTSTAT: CPU W REGISTER CONTEXT STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

CCTXI2

CCTXI1

CCTXI0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0

MCTXI2

MCTXI1

MCTXI0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10-8

Unimplemented: Read as ‘0’

CCTXI<2:0>: Current (W Register) Context Identifier bits

111= Reserved

•

011= Reserved

010= Alternate Working Register Set 2 is currently in use

001= Alternate Working Register Set 1 is currently in use

000= Default register set is currently in use

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

MCTXI<2:0>: Manual (W Register) Context Identifier bits

111= Reserved

•

011= Reserved

010= Alternate Working Register Set 2 was most recently manually selected

001= Alternate Working Register Set 1 was most recently manually selected

000= Default register set was most recently manually selected

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3.8

Arithmetic Logic Unit (ALU)

3.9

DSP Engine

The dsPIC33EPXXGS202 family ALU is 16 bits wide and

is capable of addition, subtraction, bit shifts and logic

operations. Unless otherwise mentioned, arithmetic

operations are two’s complement in nature. Depending

on the operation, the ALU can affect the values of the

Carry (C), Zero (Z), Negative (N), Overflow (OV) and

Digit Carry (DC) Status bits in the SR register. The C and

DC Status bits operate as Borrow and Digit Borrow bits,

respectively, for subtraction operations.

The DSP engine consists of a high-speed 17-bit x 17-bit

multiplier, a 40-bit barrel shifter and a 40-bit adder/

subtracter (with two target accumulators, round and

saturation logic).

The DSP engine can also perform inherent accumulator-

to-accumulator operations that require no additional

data. These instructions are ADD, SUBand NEG.

The DSP engine has options selected through bits in

the CPU Core Control register (CORCON), as listed

below:

The ALU can perform 8-bit or 16-bit operations,

depending on the mode of the instruction that is used.

Data for the ALU operation can come from the W

register array or data memory, depending on the

addressing mode of the instruction. Likewise, output

data from the ALU can be written to the W register array

or a data memory location.

• Fractional or Integer DSP Multiply (IF)

• Signed, unsigned or mixed-sign DSP multiply

(USx)

• Conventional or Convergent Rounding (RND)

• Automatic Saturation On/Off for ACCA (SATA)

• Automatic Saturation On/Off for ACCB (SATB)

Refer to the “16-Bit MCU and DSC Programmer’s

Reference Manual” (DS70000157) for information on

the SR bits affected by each instruction.

• Automatic Saturation On/Off for Writes to Data

Memory (SATDW)

The core CPU incorporates hardware support for both

multiplication and division. This includes a dedicated

hardware multiplier and support hardware for 16-bit

divisor division.

• Accumulator Saturation mode Selection

(ACCSAT)

TABLE 3-2:

Instruction

DSP INSTRUCTIONS

SUMMARY

3.8.1

MULTIPLIER

Algebraic

Operation

ACC Write

Using the high-speed 17-bit x 17-bit multiplier, the ALU

supports unsigned, signed, or mixed-sign operation in

several MCU multiplication modes:

Back

CLR

A = 0

A = (x – y)

Yes

No

2

• 16-bit x 16-bit signed

ED

2

• 16-bit x 16-bit unsigned

EDAC

MAC

A = A + (x – y)

No

• 16-bit signed x 5-bit (literal) unsigned

• 16-bit signed x 16-bit unsigned

• 16-bit unsigned x 5-bit (literal) unsigned

• 16-bit unsigned x 16-bit signed

• 8-bit unsigned x 8-bit unsigned

A = A + (x • y)

Yes

No

2

MAC

A = A + x

MOVSAC

MPY

No change in A

Yes

No

A = x • y

2

MPY

A = x

No

3.8.2

DIVIDER

MPY.N

MSC

A = – x • y

No

A = A – x • y

Yes

The divide block supports 32-bit/16-bit and 16-bit/16-bit

signed and unsigned integer divide operations with the

following data sizes:

• 32-bit signed/16-bit signed divide

• 32-bit unsigned/16-bit unsigned divide

• 16-bit signed/16-bit signed divide

• 16-bit unsigned/16-bit unsigned divide

The quotient for all divide instructions ends up in W0

and the remainder in W1. Sixteen-bit signed and

unsigned DIV instructions can specify any W register

for both the 16-bit divisor (Wn) and any W register

(aligned) pair (W(m + 1):Wm) for the 32-bit dividend.

The divide algorithm takes one cycle per bit of divisor,

so both 32-bit/16-bit and 16-bit/16-bit instructions take

the same number of cycles to execute.

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4.2

Unique Device Identifier (UDID)

4.0

MEMORY ORGANIZATION

All dsPIC33EPXXGS202 family devices are individu-

ally encoded during final manufacturing with a Unique

Device Identifier or UDID. This feature allows for

manufacturing traceability of Microchip Technology

devices in applications where this is a requirement. It

may also be used by the application manufacturer

for any number of things that may require unique

identification, such as:

Note:

This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this

data sheet, refer to “dsPIC33E/PIC24E

Program Memory” (DS70000613) in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

• Tracking the device

• Unique serial number

• Unique security key

The dsPIC33EPXXGS202 family architecture features

separate program and data memory spaces, and

buses. This architecture also allows the direct access

of program memory from the Data Space (DS) during

code execution.

The UDID comprises five 24-bit program words.

When taken together, these fields form a unique

120-bit identifier.

The UDID is stored in five read-only locations,

located between 800F00h and 800F08h in the

device configuration space. Table 4-1 lists the

addresses of the Identifier Words and shows their

contents.

4.1

Program Address Space

The program address memory space of the

dsPIC33EPXXGS202 family devices is 4M instructions.

The space is addressable by a 24-bit value derived

either from the 23-bit PC during program execution, or

from table operation or Data Space remapping, as

described in Section 4.9 “Interfacing Program and

Data Memory Spaces”.

TABLE 4-1:

UDID ADDRESSES

Name Address Bits 23:16 Bits 15:8 Bits 7:0

UDID1 800F00

UDID2 800F02

UDID3 800F04

UDID4 800F06

UDID5 800F08

UDID Word 1

UDID Word 2

UDID Word 3

UDID Word 4

UDID Word 5

User application access to the program memory space

is restricted to the lower half of the address range

(0x000000 to 0x7FFFFF). The exception is the use of

TBLRD operations, which use TBLPAG to permit

access to calibration data and Device ID sections of the

configuration memory space.

The program memory maps for the dsPIC33EP16/

32GS202 devices are shown in Figure 4-1 and

Figure 4-2.

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FIGURE 4-1: PROGRAM MEMORY MAP FOR dsPIC33EP16GS202 DEVICES

0x000000

GOTOInstruction

0x000002

Reset Address

0x000004

Interrupt Vector Table

0x0001FE

0x000200

User Program

Flash Memory

(5312 instructions)

0x002B7E

0x002B80

Device Configuration

0x002BFE

0x002C00

Unimplemented

(Read ‘0’s)

0x7FFFFE

0x800000

Executive Code Memory

0x800BFE

0x800C00

Reserved

OTP Memory

Reserved

0x800F7E

0x800F80

0x800FFE

0x801000

0xF9FFFE

0xFA0000

Write Latches

0xFA0002

0xFA0004

Reserved

0xFEFFFE

0xFF0000

0xFF0002

0xFF0004

DEVID

Reserved

0xFFFFFE

Note: Memory areas are not shown to scale.

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FIGURE 4-2: PROGRAM MEMORY MAP FOR dsPIC33EP32GS202 DEVICES

0x000000

0x000002

GOTOInstruction

Reset Address

0x000004

0x0001FE

0x000200

Interrupt Vector Table

User Program

Flash Memory

(10,944 instructions)

0x00577E

0x005780

Device Configuration

0x0057FE

0x005800

Unimplemented

(Read ‘0’s)

0x7FFFFE

0x800000

Executive Code Memory

0x800BFE

0x800C00

Reserved

OTP Memory

Reserved

0x800F7E

0x800F80

0x800FFE

0x801000

0xF9FFFE

0xFA0000

Write Latches

0xFA0002

0xFA0004

Reserved

0xFEFFFE

0xFF0000

0xFF0002

0xFF0004

DEVID

Reserved

0xFFFFFE

Note: Memory areas are not shown to scale.

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4.2.1

PROGRAM MEMORY

ORGANIZATION

4.2.2

INTERRUPT AND TRAP VECTORS

All dsPIC33EPXXGS202 family devices reserve the

addresses between 0x000000 and 0x000200 for hard-

coded program execution vectors. A hardware Reset

vector is provided to redirect code execution from the

default value of the PC on device Reset to the actual

start of code. A GOTO instruction is programmed by

the user application at address, 0x000000, of Flash

memory, with the actual address for the start of code at

address, 0x000002, of Flash memory.

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 4-3).

Program memory addresses are always word-aligned

on the lower word, and addresses are incremented, or

decremented, by two during code execution. This

arrangement provides compatibility with data memory

space addressing and makes data in the program

memory space accessible.

A more detailed discussion of the Interrupt Vector

Tables (IVTs) is provided in Section 7.1 “Interrupt

Vector Table”.

FIGURE 4-3:

PROGRAM MEMORY ORGANIZATION

least significant word

PC Address

most significant word

23

msw

Address

(lsw Address)

16

8

0

0x000001

0x000003

0x000005

0x000007

0x000000

0x000002

0x000004

0x000006

00000000

Program Memory

‘Phantom’ Byte

(read as ‘0’)

Instruction Width

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All word accesses must be aligned to an even address.

Misaligned word data fetches are not supported, so

4.3

Data Address Space

The dsPIC33EPXXGS202 family CPU has a separate

16-bit wide data memory space. The Data Space is

accessed using separate Address Generation Units

(AGUs) for read and write operations. The data memory

map is shown in Figure 4-4.

care must be taken when mixing byte and word

operations, or translating from 8-bit MCU code. If a

misaligned read or write is attempted, an address error

trap is generated. If the error occurred on a read, the

instruction underway is completed. If the error occurred

on a write, the instruction is executed but the write does

not occur. In either case, a trap is then executed,

allowing the system and/or user application to examine

the machine state prior to execution of the address

Fault.

All Effective Addresses (EAs) in the data memory space

are 16 bits wide and point to bytes within the Data

Space. This arrangement gives a base Data Space

address range of 64 Kbytes or 32K words.

The lower half of the data memory space (i.e., when

EA<15> = 0) is used for implemented memory

addresses, while the upper half (EA<15> = 1) is reserved

for the Program Space Visibility (PSV).

All byte loads into any W register are loaded into the

LSB; the MSB is not modified.

A Sign-Extend (SE) instruction is provided to allow user

applications to translate 8-bit signed data to 16-bit

signed values. Alternatively, for 16-bit unsigned data,

user applications can clear the MSB of any W register

by executing a Zero-Extend (ZE) instruction on the

appropriate address.

dsPIC33EPXXGS202 family devices implement up to

12 Kbytes of data memory. If an EA points to a location

outside of this area, an all-zero word or byte is returned.

4.3.1

DATA SPACE WIDTH

The data memory space is organized in byte-

addressable, 16-bit wide blocks. Data is aligned in data

memory and registers as 16-bit words, but all Data

Space EAs resolve to bytes. The Least Significant

Bytes (LSBs) of each word have even addresses, while

the Most Significant Bytes (MSBs) have odd

addresses.

4.3.3

SFR SPACE

The first 4 Kbytes of the Near Data Space, from

0x0000 to 0x0FFF, are primarily occupied by Special

Function Registers (SFRs). These are used by the

dsPIC33EPXXGS202 family core and peripheral

modules for controlling the operation of the device.

SFRs are distributed among the modules that they

control, and are generally grouped together by module.

Much of the SFR space contains unused addresses;

these are read as ‘0’.

4.3.2

DATA MEMORY ORGANIZATION

AND ALIGNMENT

To maintain backward compatibility with PIC^®MCU

devices and improve Data Space memory usage

efficiency, the dsPIC33EPXXGS202 family instruc-

tion set supports both word and byte operations. As a

consequence of byte accessibility, all Effective Address

calculations are internally scaled to step through word-

aligned memory. For example, the core recognizes that

Post-Modified Register Indirect Addressing mode

[Ws++] results in a value of Ws + 1 for byte operations

and Ws + 2 for word operations.

Note:

The actual set of peripheral features and

interrupts varies by the device. Refer to

the corresponding device tables and

pinout diagrams for device-specific

information.

4.3.4

NEAR DATA SPACE

The 8-Kbyte area, between 0x0000 and 0x1FFF, is

referred to as the Near Data Space. Locations in this

space are directly addressable through a 13-bit absolute

address field within all memory direct instructions. Addi-

tionally, the whole Data Space is addressable using MOV

instructions, which support Memory Direct Addressing

mode with a 16-bit address field, or by using Indirect

Addressing mode using a Working register as an

Address Pointer.

A data byte read, reads the complete word that

contains the byte, using the LSb of any EA to determine

which byte to select. The selected byte is placed onto

the LSB of the data path. That is, data memory and reg-

isters are organized as two parallel, byte-wide entities

with shared (word) address decode, but separate write

lines. Data byte writes only write to the corresponding

side of the array or register that matches the byte

address.

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FIGURE 4-4: DATA MEMORY MAP FOR dsPIC33EP16/32GS202 DEVICES

MSB

Address

LSB

Address

16 Bits

MSB

LSB

0x0000

0x0001

4-Kbyte

SFR Space

0x0FFE

0x1000

0x0FFF

0x1001

X Data RAM (X)

Y Data RAM (Y)

8-Kbyte

Near

Data Space

0x13FF

0x1401

2-Kbyte

SRAM Space

0x13FE

0x1400

0x17FF

0x1801

0x17FE

0x1800

0x1FFF

0x2001

0x1FFE

0x2000

0x8001

0x8000

Program Visibility Space

Optionally

Mapped

into Program

Memory using

DSRPAG register

0xFFFF

0xFFFE

Note:

Memory areas are not shown to scale.

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Both the X and Y Data Spaces support Modulo Address-

ing mode for all instructions, subject to addressing mode

restrictions. Bit-Reversed Addressing mode is only

supported for writes to X Data Space.

4.3.5

X AND Y DATA SPACES

The dsPIC33EPXXGS202 core has two Data Spaces, X

and Y. These Data Spaces can be considered either

separate (for some DSP instructions) or as one unified

linear address range (for MCU instructions). The Data

Spaces are accessed using two Address Generation

Units (AGUs) and separate data paths. This feature

allows certain instructions to concurrently fetch two

words from RAM, thereby enabling efficient execution of

DSP algorithms, such as Finite Impulse Response (FIR)

filtering and Fast Fourier Transform (FFT).

All data memory writes, including in DSP instructions,

view Data Space as combined X and Y address space.

The boundary between the X and Y Data Spaces is

device-dependent and is not user-programmable.

4.4

Memory Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

The X Data Space is used by all instructions and

supports all addressing modes. X Data Space has

separate read and write data buses. The X read data

bus is the read data path for all instructions that view

Data Space as combined X and Y address space. It is

also the X data prefetch path for the dual operand DSP

instructions (MACclass).

4.4.1

KEY RESOURCES

• “dsPIC33E/PIC24E Program Memory”

(DS70000613) in the “dsPIC33/PIC24 Family

Reference Manual”

The Y Data Space is used in concert with the X Data

Space by the MAC class of instructions (CLR, ED,

EDAC, MAC, MOVSAC, MPY, MPY.Nand MSC) to provide

two concurrent data read paths.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

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The paged memory scheme provides access to multiple

32-Kbyte windows in the PSV memory. The Data Space

Read Page register (DSRPAG), in combination with the

upper half of the Data Space address, can provide up to

8 Mbytes of PSV address space. The paged data

memory space is shown in Figure 4-6.

4.5.1

PAGED MEMORY SCHEME

The dsPIC33EPXXGS202 architecture extends the

available Data Space through a paging scheme, which

allows the available Data Space to be accessed using

MOV instructions in a linear fashion for pre- and post-

modified Effective Addresses (EAs). The upper half of

the base Data Space address is used in conjunction

with the Data Space Read Page (DSRPAG) register to

form the Program Space Visibility (PSV) address.

The Program Space (PS) can be accessed with a

DSRPAG of 0x200 or greater. Only reads from PS are

supported using the DSRPAG.

The Data Space Read Page (DSRPAG) register is

located in the SFR space. Construction of the

PSV address is shown in Figure 4-5. When

DSRPAG<9>

= 1 and the base address bit,

EA<15> = 1, the DSRPAG<8:0> bits are concate-

nated onto EA<14:0> to form the 24-bit PSV read

address.

FIGURE 4-5:

PROGRAM SPACE VISIBILITY (PSV) READ ADDRESS GENERATION

Byte

Select

16-Bit DS EA

EA<15> = 0

(DSRPAG = don’t care)

0

EA

No EDS Access

EA<15>

DSRPAG<9>

1

= 1

Select

DSRPAG

Generate

PSV Address

1

DSRPAG<8:0>

9 Bits

15 Bits

24-Bit PSV EA

Byte

Select

Note: DS read access when DSRPAG = 0x000 will force an address error trap.

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When a PSV page overflow or underflow occurs,

base address within the PSV window. This creates a

linear PSV address space, but only when using

Register Indirect Addressing modes.

EA<15> is cleared as a result of the register indirect EA

calculation. An overflow or underflow of the EA in the

PSV pages can occur at the page boundaries when:

Exceptions to the operation described above arise

when entering and exiting the boundaries of Page 0

and PSV spaces. Table 4-24 lists the effects of overflow

and underflow scenarios at different boundaries.

• The initial address, prior to modification,

addresses the PSV page

• The EA calculation uses Pre- or Post-Modified

Register Indirect Addressing; however, this does

not include Register Offset Addressing

In the following cases, when overflow or underflow

occurs, the EA<15> bit is set and the DSRPAG is not

modified; therefore, the EA will wrap to the beginning of

the current page:

In general, when an overflow is detected, the DSRPAG

register is incremented and the EA<15> bit is set to

keep the base address within the PSV window. When

an underflow is detected, the DSRPAG register is

decremented and the EA<15> bit is set to keep the

• Register Indirect with Register Offset Addressing

• Modulo Addressing

• Bit-Reversed Addressing

TABLE 4-24: OVERFLOW AND UNDERFLOW SCENARIOS AT PAGE 0 AND

PSV SPACE BOUNDARIES^(2,3,4)

Before

After

O/U,

R/W

Operation

DS

EA<15>

Page

Description

DS

EA<15>

Page

Description

DSxPAG

O,

Read

DSRPAG = 0x2FF

1

PSV: Last lsw

page

DSRPAG = 0x300

1

0

1

PSV: First MSB

page

[++Wn]

or

[Wn++]

O,

Read

DSRPAG = 0x3FF

DSRPAG = 0x001

DSRPAG = 0x200

DSRPAG = 0x300

PSV: Last MSB DSRPAG = 0x3FF

page

See Note 1

U,

Read

PSV page

DSRPAG = 0x001

[--Wn]

or

[Wn--]

U,

Read

PSV: First lsw

page

DSRPAG = 0x200

U,

Read

PSV: First MSB DSRPAG = 0x2FF

page

PSV: Last lsw

page

Legend: O = Overflow, U = Underflow, R = Read, W = Write

Note 1: The Register Indirect Addressing now addresses a location in the base Data Space (0x0000-0x7FFF).

2: An EDS access, when DSRPAG = 0x000, will generate an address error trap.

3: Only reads from PS are supported using DSRPAG.

4: Pseudolinear Addressing is not supported for large offsets.

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When the PC is pushed onto the stack, PC<15:0> are

pushed onto the first available stack word, then

PC<22:16> are pushed into the second available stack

location. For a PC push during any CALL instruction,

the MSB of the PC is zero-extended before the push,

as shown in Figure 4-7. During exception processing,

the MSB of the PC is concatenated with the lower 8 bits

of the CPU STATUS Register, SR. This allows the

contents of SRL to be preserved automatically during

interrupt processing.

4.5.2

EXTENDED X DATA SPACE

The lower portion of the base address space range,

between 0x0000 and 0x7FFF, is always accessible

regardless of the contents of the Data Space Read

Page register. It is indirectly addressable through the

register indirect instructions. It can be regarded as

being located in the default EDS Page 0 (i.e., EDS

address range of 0x000000 to 0x007FFF with the base

address bit, EA<15> = 0, for this address range). How-

ever, Page 0 cannot be accessed through the upper

32 Kbytes, 0x8000 to 0xFFFF, of base Data Space in

combination with DSRPAG = 0x000. Consequently,

DSRPAG is initialized to 0x001 at Reset.

Note 1: To maintain the Software Stack Pointer

(W15) coherency, W15 is never subject

to (EDS) paging, and is therefore,

restricted to an address range of 0x0000

to 0xFFFF. The same applies to the W14

when used as a Stack Frame Pointer

(SFA = 1).

Note:

DSRPAG should not be used to access

Page 0. An EDS access with DSRPAG set

to 0x000 will generate an address error

trap.

2: As the stack can be placed in, and can

access X and Y spaces, care must be

taken regarding its use, particularly with

regard to local automatic variables in a C

development environment

The remaining PSV pages are only accessible using

the DSRPAG register in combination with the upper

32 Kbytes, 0x8000 to 0xFFFF, of the base address,

where base address bit, EA<15> = 1.

4.5.3

SOFTWARE STACK

FIGURE 4-7:

CALL STACK FRAME

The W15 register serves as a dedicated Software

Stack Pointer (SSP) and is automatically modified by

exception processing, subroutine calls and returns;

however, W15 can be referenced by any instruction in

the same manner as all other W registers. This simpli-

fies reading, writing and manipulating the Stack Pointer

(for example, creating stack frames).

0x0000

15

0

CALL SUBR

Note: To protect against misaligned stack

accesses, W15<0> is fixed to ‘0’ by the

hardware.

PC<15:1>

W15 (before CALL)

W15 (after CALL)

b‘000000000’

PC<22:16>

W15 is initialized to 0x1000 during all Resets. This

address ensures that the SSP points to valid RAM in all

dsPIC33EPXXGS202 devices and permits stack avail-

ability for non-maskable trap exceptions. These can

occur before the SSP is initialized by the user software.

You can reprogram the SSP during initialization to any

location within Data Space.

The Software Stack Pointer always points to the first

available free word and fills the software stack, work-

ing from lower toward higher addresses. Figure 4-7

illustrates how it pre-decrements for a stack pop (read)

and post-increments for a stack push (writes).

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4.6.2

MCU INSTRUCTIONS

4.6

Instruction Addressing Modes

The three-operand MCU instructions are of the form:

The addressing modes shown in Table 4-25 form the

basis of the addressing modes optimized to support the

specific features of individual instructions. The address-

ing modes provided in the MACclass of instructions differ

from those in the other instruction types.

Operand 3 = Operand 1 <function> Operand 2

where Operand 1 is always a Working register (that is,

the addressing mode can only be Register Direct),

which is referred to as Wb. Operand 2 can be a W

register fetched from data memory or a 5-bit literal. The

result location can either be a W register or a data

memory location. The following addressing modes are

supported by MCU instructions:

4.6.1

FILE REGISTER INSTRUCTIONS

Most file register instructions use a 13-bit address field (f)

to directly address data present in the first 8192 bytes

of data memory (Near Data Space). Most file register

instructions employ a Working register, W0, which is

denoted as WREG in these instructions. The destina-

tion is typically either the same file register or WREG

(with the exception of the MULinstruction), which writes

the result to a register or register pair. The MOVinstruc-

tion allows additional flexibility and can access the

entire Data Space.

• Register Direct

• Register Indirect

• Register Indirect Post-Modified

• Register Indirect Pre-Modified

• 5-Bit or 10-Bit Literal

Note:

Not all instructions support all the

addressing modes given above. Individ-

ual instructions can support different

subsets of these addressing modes.

TABLE 4-25: FUNDAMENTAL ADDRESSING MODES SUPPORTED

Addressing Mode Description

File Register Direct

The address of the file register is specified explicitly.

The contents of a register are accessed directly.

The contents of Wn form the Effective Address (EA).

Register Direct

Register Indirect

Register Indirect Post-Modified

The contents of Wn form the EA. Wn is post-modified (incremented

or decremented) by a constant value.

Register Indirect Pre-Modified

Wn is pre-modified (incremented or decremented) by a signed constant value

to form the EA.

Register Indirect with Register Offset The sum of Wn and Wb forms the EA.

(Register Indexed)

Register Indirect with Literal Offset

The sum of Wn and a literal forms the EA.

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4.6.3

MOVE AND ACCUMULATOR

INSTRUCTIONS

4.6.4

MACINSTRUCTIONS

The dual source operand DSP instructions (CLR, ED,

EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also referred

to as MACinstructions, use a simplified set of addressing

modes to allow the user application to effectively

manipulate the Data Pointers through register indirect

tables.

Move instructions, and the DSP accumulator class

of instructions, provide a greater degree of address-

ing flexibility than other instructions. In addition to the

addressing modes supported by most MCU instruc-

tions, move and accumulator instructions also support

Register Indirect with Register Offset Addressing

mode, also referred to as Register Indexed mode.

The two-source operand prefetch registers must be

members of the set {W8, W9, W10, W11}. For data

reads, W8 and W9 are always directed to the X RAGU,

and W10 and W11 are always directed to the Y AGU.

The Effective Addresses generated (before and after

modification) must therefore, be valid addresses within

X Data Space for W8 and W9, and Y Data Space for

W10 and W11.

Note:

For the MOV instructions, the addressing

mode specified in the instruction can differ

for the source and destination EA. How-

ever, the 4-bit Wb (Register Offset) field is

shared by both source and destination (but

typically, only used by one).

Note:

Register Indirect with Register Offset

Addressing mode is available only for W9

(in X space) and W11 (in Y space).

In summary, the following addressing modes are

supported by move and accumulator instructions:

• Register Direct

In summary, the following addressing modes are

supported by the MACclass of instructions:

• Register Indirect

• Register Indirect Post-modified

• Register Indirect Pre-modified

• Register Indirect with Register Offset (Indexed)

• Register Indirect with Literal Offset

• 8-Bit Literal

• Register Indirect

• Register Indirect Post-Modified by 2

• Register Indirect Post-Modified by 4

• Register Indirect Post-Modified by 6

• Register Indirect with Register Offset (Indexed)

• 16-Bit Literal

Note:

Not all instructions support all the

addressing modes given above. Individual

instructions may support different subsets

of these addressing modes.

4.6.5

OTHER INSTRUCTIONS

Besides the addressing modes outlined previously, some

instructions use literal constants of various sizes. For

example, BRA (branch) instructions use 16-bit signed

literals to specify the branch destination directly, whereas

the DISIinstruction uses a 14-bit unsigned literal field. In

some instructions, such as ULNK, the source of an

operand or result is implied by the opcode itself. Certain

operations, such as a NOP, do not have any operands.

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4.7.1

START AND END ADDRESS

4.7

Modulo Addressing

The Modulo Addressing scheme requires that a

starting and ending address be specified and loaded

into the 16-bit Modulo Buffer Address registers:

XMODSRT, XMODEND, YMODSRT and YMODEND

(see Table 4-2).

Modulo Addressing mode is a method of providing an

automated means to support circular data buffers using

hardware. The objective is to remove the need for

software to perform data address boundary checks

when executing tightly looped code, as is typical in

many DSP algorithms.

Note:

Y space Modulo Addressing EA calcula-

tions assume word-sized data (LSb of

every EA is always clear).

Modulo Addressing can operate in either Data or

Program Space (since the Data Pointer mechanism is

essentially the same for both). One circular buffer can

be supported in each of the X (which also provides the

pointers into Program Space) and Y Data Spaces.

Modulo Addressing can operate on any W Register

Pointer. However, it is not advisable to use W14 or W15

for Modulo Addressing since these two registers are

used as the Stack Frame Pointer and Stack Pointer,

respectively.

The length of a circular buffer is not directly specified. It

is determined by the difference between the corre-

sponding start and end addresses. The maximum

possible length of the circular buffer is 32K words

(64 Kbytes).

4.7.2

W ADDRESS REGISTER SELECTION

The Modulo and Bit-Reversed Addressing Control

register, MODCON<15:0>, contains enable flags, as well

as a W register field to specify the W Address registers.

The XWM and YWM fields select the registers that

operate with Modulo Addressing:

In general, any particular circular buffer can be config-

ured to operate in only one direction, as there are certain

restrictions on the buffer start address (for incrementing

buffers) or end address (for decrementing buffers),

based upon the direction of the buffer.

• If XWM = 1111, X RAGU and X WAGU Modulo

The only exception to the usage restrictions is for

buffers that have a power-of-two length. As these

buffers satisfy the start and end address criteria, they

can operate in a Bidirectional mode (that is, address

boundary checks are performed on both the lower and

upper address boundaries).

Addressing is disabled

• If YWM = 1111, Y AGU Modulo Addressing is

disabled

The X Address Space Pointer W register (XWM), to

which Modulo Addressing is to be applied, is stored in

MODCON<3:0> (see Table 4-2). Modulo Addressing is

enabled for X Data Space when XWM is set to any

value other than ‘1111’ and the XMODEN bit is set

(MODCON<15>).

The Y Address Space Pointer W register (YWM), to

which Modulo Addressing is to be applied, is stored in

MODCON<7:4>. Modulo Addressing is enabled for

Y Data Space when YWM is set to any value other than

‘1111’ and the YMODEN bit is set at MODCON<14>.

FIGURE 4-8:

MODULO ADDRESSING OPERATION EXAMPLE

Byte

Address

MOV

#0x1100, W0

W0, XMODSRT

#0x1163, W0

W0, MODEND

#0x8001, W0

W0, MODCON

;set modulo start address

;set modulo end address

;enable W1, X AGU for modulo

;W0 holds buffer fill value

;point W1 to buffer

0x1100

MOV

#0x0000, W0

#0x1110, W1

0x1163

DO

MOV

AGAIN, #0x31

W0, [W1++]

;fill the 50 buffer locations

;fill the next location

AGAIN: INC W0, W0

;increment the fill value

Start Addr = 0x1100

End Addr = 0x1163

Length = 0x0032 words

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4.7.3

MODULO ADDRESSING

APPLICABILITY

4.8.1

BIT-REVERSED ADDRESSING

IMPLEMENTATION

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W

register. Address boundaries check for addresses

equal to:

Bit-Reversed Addressing mode is enabled when all of

these conditions are met:

• BWMx bits (W register selection) in the MODCON

register are any value other than ‘1111’ (the stack

cannot be accessed using Bit-Reversed

Addressing)

• The upper boundary addresses for incrementing

buffers

• The lower boundary addresses for decrementing

buffers

• The BREN bit is set in the XBREV register

• The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment

It is important to realize that the address boundaries

check for addresses less than or greater than the upper

(for incrementing buffers) and lower (for decrementing

buffers) boundary addresses (not just equal to). Address

changes can, therefore, jump beyond boundaries and

still be adjusted correctly.

N

If the length of a bit-reversed buffer is M = 2 bytes,

the last ‘N’ bits of the data buffer start address must

be zeros.

XB<14:0> is the Bit-Reversed Addressing modifier, or

‘pivot point’, which is typically a constant. In the case of

an FFT computation, its value is equal to half of the FFT

data buffer size.

Note:

The modulo corrected Effective Address

is written back to the register only when

Pre-Modify or Post-Modify Addressing

mode is used to compute the Effective

Address. When an address offset (such as

[W7 + W2]) is used, Modulo Addressing

correction is performed, but the contents of

the register remain unchanged.

Note:

All bit-reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

When enabled, Bit-Reversed Addressing is executed

only for Register Indirect with Pre-Increment or Post-

Increment Addressing and word-sized data writes. It

does not function for any other addressing mode or for

byte-sized data and normal addresses are generated

instead. When Bit-Reversed Addressing is active, the

W Address Pointer is always added to the address

modifier (XB) and the offset associated with the Register

Indirect Addressing mode is ignored. In addition, as

word-sized data is a requirement, the LSb of the EA is

ignored (and always clear).

4.8

Bit-Reversed Addressing

Bit-Reversed Addressing mode is intended to simplify

data reordering for radix-2 FFT algorithms. It is

supported by the X AGU for data writes only.

The modifier, which can be a constant value or register

contents, is regarded as having its bit order reversed.

The address source and destination are kept in normal

order. Thus, the only operand requiring reversal is the

modifier.

Note:

Modulo Addressing and Bit-Reversed

Addressing can be enabled simultaneously

using the same W register, but Bit-

Reversed Addressing operation will always

take precedence for data writes when

enabled.

If Bit-Reversed Addressing has already been enabled

by setting the BREN (XBREV<15>) bit, a write to the

XBREV register should not be immediately followed by

an indirect read operation using the W register that has

been designated as the Bit-Reversed Pointer.

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FIGURE 4-9:

BIT-REVERSED ADDRESSING EXAMPLE

Sequential Address

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1

0

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4

0

Bit-Reversed Address

Pivot Point

XB = 0x0008 for a 16-Word Bit-Reversed Buffer

TABLE 4-26: BIT-REVERSED ADDRESSING SEQUENCE (16-ENTRY)

Normal Address Bit-Reversed Address

A3

A2

A1

A0

Decimal

A3

A2

A1

A0

Decimal

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

8

2

4

3

12

2

4

5

10

6

7

14

1

8

9

10

11

12

13

14

15

5

13

3

11

7

15

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Table instructions allow an application to read or write

to small areas of the program memory. This capability

makes the method ideal for accessing data tables that

need to be updated periodically. It also allows access

to all bytes of the program word. The remapping

method allows an application to access a large block of

data on a read-only basis, which is ideal for look-ups

from a large table of static data. The application can

only access the least significant word of the program

word.

4.9

Interfacing Program and Data

Memory Spaces

The dsPIC33EPXXGS202 family architecture uses a

24-bit wide Program Space (PS) and a 16-bit wide Data

Space (DS). The architecture is also a modified

Harvard scheme, meaning that data can also be

present in the Program Space. To use this data

successfully, it must be accessed in a way that

preserves the alignment of information in both spaces.

Aside from normal execution, the architecture of the

dsPIC33EPXXGS202 family devices provides two

methods by which Program Space can be accessed

during operation:

• Using table instructions to access individual bytes

or words anywhere in the Program Space

• Remapping a portion of the Program Space into

the Data Space (Program Space Visibility)

TABLE 4-27: PROGRAM SPACE ADDRESS CONSTRUCTION

Program Space Address

Access

Space

Access Type

<23>

<22:16>

<15>

<14:1>

<0>

Instruction Access

(Code Execution)

User

0

PC<22:1>

0

0xxx xxxx xxxx xxxx xxxx xxx0

TBLRD/TBLWT

(Byte/Word Read/Write)

TBLPAG<7:0>

0xxx xxxx

Data EA<15:0>

xxxx xxxx xxxx xxxx

Data EA<15:0>

Configuration

TBLPAG<7:0>

1xxx xxxx

xxxx xxxx xxxx xxxx

FIGURE 4-10:

DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION

(1)

Program Counter

0

Program Counter

23 Bits

0

1/0

EA

(2)

1/0

TBLPAG

8 Bits

Table Operations

16 Bits

24 Bits

User/Configuration

Space Select

Byte Select

Note 1: The Least Significant bit (LSb) of Program Space addresses is always fixed as ‘0’ to maintain

word alignment of data in the Program and Data Spaces.

2: Table operations are not required to be word-aligned. Table Read operations are permitted in the

configuration memory space.

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• TBLRDH (Table Read High):

4.9.1

DATA ACCESS FROM PROGRAM

MEMORY USING TABLE

INSTRUCTIONS

- In Word mode, this instruction maps the entire

upper word of a program address (P<23:16>)

to a data address. The ‘phantom’ byte

(D<15:8>) is always ‘0’.

The TBLRDL and TBLWTL instructions offer a direct

method of reading or writing the lower word of any

address within the Program Space without going

through Data Space. The TBLRDH and TBLWTH

instructions are the only method to read or write the

upper 8 bits of a Program Space word as data.

- In Byte mode, this instruction maps the upper

or lower byte of the program word to D<7:0>

of the data address in the TBLRDL instruc-

tion. The data is always ‘0’ when the upper

‘phantom’ byte is selected (Byte Select = 1).

The PC is incremented by two for each successive

24-bit program word. This allows program memory

addresses to directly map to Data Space

addresses. Program memory can thus be regarded

as two 16-bit wide word address spaces, residing side

by side, each with the same address range. TBLRDL

and TBLWTLaccess the space that contains the least

significant data word. TBLRDHand TBLWTHaccess the

space that contains the upper data byte.

In a similar fashion, two table instructions, TBLWTH

and TBLWTL, are used to write individual bytes or

words to a Program Space address. The details of

their operation are explained in Section 5.0 “Flash

Program Memory”.

For all table operations, the area of program memory

space to be accessed is determined by the Table Page

register (TBLPAG). TBLPAG covers the entire program

memory space of the device, including user application

and configuration spaces. When TBLPAG<7> = 0, the

table page is located in the user memory space. When

TBLPAG<7> = 1, the page is located in configuration

space.

Two table instructions are provided to move byte or

word-sized (16-bit) data to and from Program Space.

Both function as either byte or word operations.

• TBLRDL(Table Read Low):

- In Word mode, this instruction maps the lower

word of the Program Space location (P<15:0>)

to a data address (D<15:0>)

- In Byte mode, either the upper or lower byte

of the lower program word is mapped to the

lower byte of a data address. The upper byte

is selected when Byte Select is ‘1’; the lower

byte is selected when it is ‘0’.

FIGURE 4-11:

ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS

Program Space

TBLPAG

02

23

15

0

0x000000

23

16

8

0

00000000

0x020000

0x030000

‘Phantom’ Byte

TBLRDH.B (Wn<0> = 0)

TBLRDL.B (Wn<0> = 1)

TBLRDL.B (Wn<0> = 0)

TBLRDL.W

The address for the table operation is determined by the data EA

within the page defined by the TBLPAG register.

Only read operations are shown; write operations are also valid in

the user memory area.

0x800000

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NOTES:

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device just before shipping the product. This also

allows the most recent firmware or a custom firmware

to be programmed.

5.0

FLASH PROGRAM MEMORY

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to “Flash Programming” (DS70609)

in the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

Enhanced In-Circuit Serial Programming uses an on-

board bootloader, known as the Program Executive, to

manage the programming process. Using an SPI data

frame format, the Program Executive can erase,

program and verify program memory. For more informa-

tion on Enhanced ICSP, see the device programming

specification.

RTSP is accomplished using TBLRD(Table Read) and

TBLWT(Table Write) instructions. With RTSP, the user

application can write program memory data with a

single program memory word and erase program mem-

ory in blocks or ‘pages’ of 512 instructions (1536 bytes)

at a time.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

5.1

Table Instructions and Flash

Programming

The dsPIC33EPXXGS202 family devices contain inter-

nal Flash program memory for storing and executing

application code. The memory is readable, writable and

erasable during normal operation over the entire VDD

range.

Regardless of the method used, all programming of

Flash memory is done with the Table Read and Table

Write instructions. These allow direct read and write

access to the program memory space from the data

memory while the device is in normal operating mode.

The 24-bit target address in the program memory is

formed using bits<7:0> of the TBLPAG register and the

Effective Address (EA) from a W register, specified in

the table instruction, as shown in Figure 5-1. The

TBLRDLand the TBLWTLinstructions are used to read or

write to bits<15:0> of program memory. TBLRDL and

TBLWTLcan access program memory in both Word and

Byte modes. The TBLRDHand TBLWTHinstructions are

used to read or write to bits<23:16> of program memory.

TBLRDHand TBLWTHcan also access program memory

in Word or Byte mode.

Flash memory can be programmed in three ways:

• In-Circuit Serial Programming™ (ICSP™)

programming capability

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

• Run-Time Self-Programming (RTSP)

ICSP allows for a dsPIC33EPXXGS202 family device

to be serially programmed while in the end application

circuit. This is done with a programming clock and pro-

gramming data (PGECx/PGEDx) line, and three other

lines for power (VDD), ground (VSS) and Master Clear

(MCLR). This allows customers to manufacture boards

with unprogrammed devices and then program the

FIGURE 5-1:

ADDRESSING FOR TABLE REGISTERS

24 Bits

Program Counter

Using

Program Counter

0

Working Reg EA

Using

Table Instruction

1/0

TBLPAG Reg

8 Bits

16 Bits

User/Configuration

Space Select

Byte

Select

24-Bit EA

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FIGURE 5-2:

UNCOMPRESSED/

COMPRESSED FORMAT

5.2

RTSP Operation

The dsPIC33EPXXGS202 family Flash program

memory array is organized into rows of 64 instructions

or 192 bytes. RTSP allows the user application to erase

a single page (8 rows or 512 instructions) of memory at

a time and to program one row at a time. It is possible

to program two instructions at a time as well.

15

7

0

Even Byte

Address

LSW1

LSW2

0x00

MSB1

MSB2

The page erase and single row write blocks are

edge-aligned, from the beginning of program

memory on boundaries of 1536 bytes and 192 bytes,

respectively. Figure 25-14 in Section 25.0 “Electri-

cal Characteristics” lists the typical erase and

programming times.

0x00

UNCOMPRESSED FORMAT (RPDF = 0)

Row programming is performed by loading 192 bytes

into data memory and then loading the address of the

first byte in that row into the NVMSRCADR register.

Once the write has been initiated, the device will

automatically load the write latches and increment the

NVMSRCADR and the NVMADR(U) registers until all

bytes have been programmed. The RPDF bit

(NVMCON<9>) selects the format of the stored data in

RAM to be either compressed or uncompressed. See

Figure 5-2 for data formatting. Compressed data helps

to reduce the amount of required RAM by using the

upper byte of the second word for the MSB of the

second instruction.

15

7

0

Even Byte

Address

LSW1

MSB2

MSB1

LSW2

COMPRESSED FORMAT (RPDF = 1)

5.3

Programming Operations

A complete programming sequence is necessary for

programming or erasing the internal Flash in RTSP

mode. The processor stalls (waits) until the program-

ming operation is finished. Setting the WR bit

(NVMCON<15>) starts the operation and the WR bit is

automatically cleared when the operation is finished.

The basic sequence for RTSP word programming is to

use the TBLWTLand TBLWTHinstructions to load two of

the 24-bit instructions into the write latches found in

configuration memory space. Refer to Figure 4-1

through Figure 4-3 for write latch addresses. Program-

ming is performed by unlocking and setting the control

bits in the NVMCON register.

5.3.1

PROGRAMMING ALGORITHM FOR

FLASH PROGRAM MEMORY

All erase and program operations may optionally use

the NVM interrupt to signal the successful completion

of the operation.

Programmers can program two adjacent words

(24 bits x 2) of Program Flash Memory (PFM) at a time

on every other word address boundary (0x000000,

0x000004, 0x000008, etc.). To do this, it is necessary

to erase the page that contains the desired address of

the location the user wants to change. For protection

against accidental operations, the write initiate

sequence for NVMKEY must be used to allow any

erase or program operation to proceed. After the

programming command has been executed, the user

application must wait for the programming time until

programming is complete. The two instructions follow-

ing the start of the programming sequence should be

NOPs.

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5.4

Flash Memory Resources

5.5

Control Registers

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

Five SFRs are used to write and erase the Program

Flash Memory: NVMCON, NVMKEY, NVMADR,

NVMADRU and NVMSRCADR.

The NVMCON register (Register 5-1) selects the oper-

ation to be performed (page erase, word/row program)

and initiates the program/erase cycle.

5.4.1

KEY RESOURCES

• “Flash Programming” (DS70609) in the “dsPIC33/

PIC24 Family Reference Manual”,

NVMKEY (Register 5-4) is a write-only register that is

used for write protection. To start a programming or erase

sequence, the user application must consecutively write

0x55 and 0xAA to the NVMKEY register.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

There are two NVM Address registers: NVMADRU and

NVMADR. These two registers, when concatenated,

form the 24-bit Effective Address (EA) of the selected

word/row for programming operations, or the selected

page for erase operations. The NVMADRU register is

used to hold the upper 8 bits of the EA, while the

NVMADR register is used to hold the lower 16 bits of

the EA.

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

For row programming operation, data to be written to

Program Flash Memory is written into data memory

space (RAM) at an address defined by the

NVMSRCADR register (location of first element in row

programming data).

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REGISTER 5-1:

NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER

(1)

R/SO-0

R/W-0

U-0

—

U-0

—

R/W-0

RPDF

R/C-0

(2)

WR

WREN

WRERR NVMSIDL

URERR

bit 15

bit 8

(1)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(3,4)

NVMOP3

NVMOP2

NVMOP1

NVMOP0

bit 0

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

SO = Settable Only bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

(1)

bit 15

WR: Write Control bit

1= Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is

cleared by hardware once the operation is complete

0= Program or erase operation is complete and inactive

(1)

bit 14

bit 13

WREN: Write Enable bit

1= Enables Flash program/erase operations

0= Inhibits Flash program/erase operations

(1)

WRERR: Write Sequence Error Flag bit

1= An improper program or erase sequence attempt, or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

0= The program or erase operation completed normally

(2)

bit 12

NVMSIDL: NVM Stop in Idle Control bit

1= Flash voltage regulator goes into Standby mode during Idle mode

0= Flash voltage regulator is active during Idle mode

bit 11-10

bit 9

Unimplemented: Read as ‘0’

RPDF: Row Programming Data Format

1= Row data to be stored in RAM in compressed format

0= Row data to be stored in RAM in uncompressed format

bit 8

URERR: Row Programming Data Underrun Error bit

1= Indicates row programming operation has been terminated

0= No data underrun error is detected

bit 7-4

Unimplemented: Read as ‘0’

Note 1: These bits can only be reset on a POR.

2: If this bit is set, power consumption will be further reduced (IIDLE), and upon exiting Idle mode, there is a

delay (TVREG) before Flash memory becomes operational.

3: All other combinations of NVMOP<3:0> are unimplemented.

4: Execution of the PWRSAVinstruction is ignored while any of the NVM operations are in progress.

5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.

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REGISTER 5-1:

bit 3-0

NVMCON: NONVOLATILE MEMORY (NVM) CONTROL REGISTER (CONTINUED)

(1,3,4)

NVMOP<3:0>: NVM Operation Select bits

1111= Reserved

•

0101= Reserved

0100= Reserved

0011= Memory page erase operation

0010= Memory row program operation

0001= Memory double-word program operation

0000= Reserved

(5)

Note 1: These bits can only be reset on a POR.

2: If this bit is set, power consumption will be further reduced (IIDLE), and upon exiting Idle mode, there is a

delay (TVREG) before Flash memory becomes operational.

3: All other combinations of NVMOP<3:0> are unimplemented.

4: Execution of the PWRSAVinstruction is ignored while any of the NVM operations are in progress.

5: Two adjacent words on a 4-word boundary are programmed during execution of this operation.

REGISTER 5-2:

R/W-x

NVMADR: NONVOLATILE MEMORY LOWER ADDRESS REGISTER

R/W-x

bit 8

R/W-x

bit 0

NVMADR<15:8>

bit 15

R/W-x

bit 7

R/W-x

NVMADR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

NVMADR<15:0>: Nonvolatile Memory Lower Write Address bits

Selects the lower 16 bits of the location to program or erase in Program Flash Memory. This register

may be read or written to by the user application.

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REGISTER 5-3:

NVMADRU: NONVOLATILE MEMORY UPPER ADDRESS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-x

bit 0

R/W-x

bit 7

R/W-x

NVMADRU<23:16>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

NVMADRU<23:16>: Nonvolatile Memory Upper Write Address bits

Selects the upper 8 bits of the location to program or erase in Program Flash Memory. This register

may be read or written to by the user application.

REGISTER 5-4:

NVMKEY: NONVOLATILE MEMORY KEY REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

W-0

bit 7

W-0

NVMKEY<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

NVMKEY<7:0>: Key Register bits (write-only)

DS70005208E-page 66

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REGISTER 5-5:

NVMSRCADRL: NVM SOURCE DATA ADDRESS LOW REGISTER

R/W-0

bit 8

R/W-0

bit 0

NVMSRCADR<15:8>

bit 15

R/W-0

bit 7

R/W-0

NVMSRCADR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

NVMSRCADR<15:0>: Source Data Address bits

The RAM address of the data to be programmed into Flash when the NVMOP<3:0> bits are set to row

programming.

REGISTER 5-6:

NVMSRCADRH: NVM SOURCE DATA ADDRESS HIGH REGISTER

R/W-0

bit 8

R/W-0

bit 0

NVMSRCADR<31:24>

bit 15

R/W-0

bit 7

R/W-0

NVMSRCADR<23:16>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

NVMSRCADR<31:16>: Source Data Address bits

The RAM address of the data to be programmed into Flash when the NVMOP<3:0> bits are set to row

programming. These bits must be always programmed to zero.

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NOTES:

DS70005208E-page 68

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A simplified block diagram of the Reset module is

shown in Figure 6-1.

6.0

RESETS

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Reset” (DS70602) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

web site (www.microchip.com).

Any active source of Reset will make the SYSRST

signal active. On system Reset, some of the registers

associated with the CPU and peripherals are forced to

a known Reset state, and some are unaffected.

Note:

Refer to the specific peripheral section or

Section 4.0 “Memory Organization” of

this manual for register Reset states.

All types of device Reset set a corresponding status bit

in the RCON register to indicate the type of Reset (see

Register 6-1).

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

A POR clears all the bits, except for the BOR and POR

bits (RCON<1:0>) that are set. The user application

can set or clear any bit at any time during code execu-

tion. The RCON bits only serve as status bits. Setting a

particular Reset status bit in software does not cause a

device Reset to occur.

The Reset module combines all Reset sources and

controls the device Master Reset Signal, SYSRST. The

following is a list of device Reset sources:

The RCON register also has other bits associated with

the Watchdog Timer and device power-saving states.

The function of these bits is discussed in other sections

of this manual.

• POR: Power-on Reset

• BOR: Brown-out Reset

• MCLR: Master Clear Pin Reset

• SWR: RESETInstruction

• WDTO: Watchdog Timer Time-out Reset

• CM: Configuration Mismatch Reset

• TRAPR: Trap Conflict Reset

• IOPUWR: Illegal Condition Device Reset

- Illegal Opcode Reset

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset is meaningful.

For all Resets, the default clock source is determined

by the FNOSC<2:0> bits in the FOSCSEL Configura-

tion register. The value of the FNOSCx bits is loaded

into the NOSC<2:0> (OSCCON<10:8>) bits on Reset,

which in turn, initializes the system clock.

- Uninitialized W Register Reset

- Security Reset

FIGURE 6-1:

RESET SYSTEM BLOCK DIAGRAM

RESETInstruction

Glitch Filter

MCLR

WDT

Module

Sleep or Idle

BOR

Internal

Regulator

SYSRST

VDD

POR

V

DD Rise

Detect

Trap Conflict

Illegal Opcode

Uninitialized W Register

Security Reset

Configuration Mismatch

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6.1.1

KEY RESOURCES

6.1

Reset Resources

• “Reset” (DS70602) in the “dsPIC33/PIC24

Family Reference Manual”

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

DS70005208E-page 70

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dsPIC33EPXXGS202 FAMILY

REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾

R/W-0

TRAPR

bit 15

R/W-0

U-0

—

U-0

—

R/W-0

U-0

—

R/W-0

CM

R/W-0

IOPUWR

VREGSF

VREGS

bit 8

R/W-0

EXTR

R/W-0

SWR

R/W-0

WDTO

R/W-0

IDLE

R/W-1

BOR

R/W-1

POR

(2)

SWDTEN

SLEEP

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

TRAPR: Trap Reset Flag bit

1= A Trap Conflict Reset has occurred

0= A Trap Conflict Reset has not occurred

IOPUWR: Illegal Opcode or Uninitialized W Register Access Reset Flag bit

1= An illegal opcode detection, an illegal address mode or Uninitialized W register used as an

Address Pointer caused a Reset

0= An illegal opcode or Uninitialized W register Reset has not occurred

bit 13-12

bit 11

Unimplemented: Read as ‘0’

VREGSF: Flash Voltage Regulator Standby During Sleep bit

1= Flash voltage regulator is active during Sleep

0= Flash voltage regulator goes into Standby mode during Sleep

bit 10

bit 9

Unimplemented: Read as ‘0’

CM: Configuration Mismatch Flag bit

1= A Configuration Mismatch Reset has occurred.

0= A Configuration Mismatch Reset has not occurred

bit 8

bit 7

bit 6

bit 5

bit 4

VREGS: Voltage Regulator Standby During Sleep bit

1= Voltage regulator is active during Sleep

0= Voltage regulator goes into Standby mode during Sleep

EXTR: External Reset (MCLR) Pin bit

1= A Master Clear (pin) Reset has occurred

0= A Master Clear (pin) Reset has not occurred

SWR: Software RESET(Instruction) Flag bit

1= A RESETinstruction has been executed

0= A RESETinstruction has not been executed

(2)

SWDTEN: Software Enable/Disable of WDT bit

1= WDT is enabled

0= WDT is disabled

WDTO: Watchdog Timer Time-out Flag bit

1= WDT time-out has occurred

0= WDT time-out has not occurred

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless

of the SWDTEN bit setting.

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REGISTER 6-1:

RCON: RESET CONTROL REGISTER⁽¹⁾(CONTINUED)

bit 3

bit 2

bit 1

bit 0

SLEEP: Wake-up from Sleep Flag bit

1= Device has been in Sleep mode

0= Device has not been in Sleep mode

IDLE: Wake-up from Idle Flag bit

1= Device has been in Idle mode

0= Device has not been in Idle mode

BOR: Brown-out Reset Flag bit

1= A Brown-out Reset has occurred

0= A Brown-out Reset has not occurred

POR: Power-on Reset Flag bit

1= A Power-on Reset has occurred

0= A Power-on Reset has not occurred

Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not

cause a device Reset.

2: If the WDTEN<1:0> Configuration bits are ‘11’ (unprogrammed), the WDT is always enabled, regardless

of the SWDTEN bit setting.

DS70005208E-page 72

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7.1.1

ALTERNATE INTERRUPT VECTOR

TABLE

7.0

INTERRUPT CONTROLLER

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “Interrupts” (DS70000600)

in the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

The Alternate Interrupt Vector Table (AIVT), shown in

Figure 7-2, is available only when the Boot Segment

(BS) is defined and the AIVT has been enabled. To

enable the Alternate Interrupt Vector Table, the Config-

uration bit, AIVTDIS in the FSEC register, must be

programmed and the AIVTEN bit must be set

(INTCON2<8> = 1). When the AIVT is enabled, all

interrupt and exception processes use the alternate

vectors instead of the default vectors. The AIVT begins

at the start of the last page of the Boot Segment,

defined by BSLIM<12:0>. The second half of the page

is no longer usable space. The Boot Segment must be

at least 2 pages to enable the AIVT.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note: Although the Boot Segment must be

enabled in order to enable the AIVT,

application code does not need to be

present inside of the Boot Segment. The

AIVT (and IVT) will inherit the Boot

Segment code protection.

The dsPIC33EPXXGS202 family interrupt controller

reduces the numerous peripheral interrupt request

signals to a single interrupt request signal to the

dsPIC33EPXXGS202 family CPU.

The interrupt controller has the following features:

The AIVT supports debugging by providing a means to

switch between an application and a support environ-

ment without requiring the interrupt vectors to be

reprogrammed. This feature also enables switching

between applications for evaluation of different

software algorithms at run time.

• Six Processor Exceptions and Software Traps

• Seven User-Selectable Priority Levels

• Interrupt Vector Table (IVT) with a Unique Vector

for each Interrupt or Exception Source

• Fixed Priority within a Specified User Priority

Level

7.2

Reset Sequence

• Fixed Interrupt Entry and Return Latencies

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The dsPIC33EPXXGS202 family devices clear their

registers in response to a Reset, which forces the PC

to zero. The device then begins program execution at

location, 0x000000. A GOTO instruction at the Reset

address can redirect program execution to the

appropriate start-up routine.

• Alternate Interrupt Vector Table (AIVT) for Debug

Support

7.1

Interrupt Vector Table

The dsPIC33EPXXGS202 family Interrupt Vector Table

(IVT), shown in Figure 7-1, resides in program memory,

starting at location, 000004h. The IVT contains six non-

maskable trap vectors and up to fifty sources of

interrupts. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Note: Any unimplemented or unused vector

locations in the IVT should be pro-

grammed with the address of a default

interrupt handler routine that contains a

RESETinstruction.

Interrupt vectors are prioritized in terms of their natural

priority. This priority is linked to their position in the

vector table. Lower addresses generally have a higher

natural priority. For example, the interrupt associated

with Vector 0 takes priority over interrupts at any other

vector address.

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FIGURE 7-1:

dsPIC33EPXXGS202 FAMILY INTERRUPT VECTOR TABLE

Reset – GOTOInstruction

Reset – GOTOAddress

Oscillator Fail Trap Vector

Address Error Trap Vector

Generic Hard Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

0x000000

0x000002

0x000004

0x000006

0x000008

0x00000A

0x00000C

0x00000E

0x000010

0x000012

0x000014

0x000016

:

Generic Soft Trap Vector

Reserved

Interrupt Vector 0

Interrupt Vector 1

:

Interrupt Vector 52

Interrupt Vector 53

Interrupt Vector 54

:

0x00007C

0x00007E

0x000080

:

See Table 7-1 for

Interrupt Vector Details

:

Interrupt Vector 116

Interrupt Vector 117

Interrupt Vector 118

Interrupt Vector 119

Interrupt Vector 120

:

0x0000FC

0x0000FE

0x000100

0x000102

0x000104

:

Interrupt Vector 244

Interrupt Vector 245

START OF CODE

0x0001FC

0x0001FE

0x000200

DS70005208E-page 74

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FIGURE 7-2:

dsPIC33EPXXGS202 FAMILY ALTERNATE INTERRUPT VECTOR TABLE

(1)

Reserved

BSLIM<12:0> + 0x000000

(1)

Reserved

BSLIM<12:0> + 0x000002

(1)

Oscillator Fail Trap Vector

BSLIM<12:0> + 0x000004

(1)

Address Error Trap Vector

BSLIM<12:0> + 0x000006

(1)

Generic Hard Trap Vector

BSLIM<12:0> + 0x000008

(1)

Stack Error Trap Vector

BSLIM<12:0> + 0x00000A

(1)

Math Error Trap Vector

BSLIM<12:0> + 0x00000C

(1)

Reserved

BSLIM<12:0> + 0x00000E

(1)

Generic Soft Trap Vector

BSLIM<12:0> + 0x000010

(1)

Reserved

BSLIM<12:0> + 0x000012

(1)

Interrupt Vector 0

BSLIM<12:0> + 0x000014

(1)

Interrupt Vector 1

BSLIM<12:0> + 0x000016

:

(1)

Interrupt Vector 52

BSLIM<12:0> + 0x00007C

(1)

Interrupt Vector 53

BSLIM<12:0> + 0x00007E

(1)

Interrupt Vector 54

BSLIM<12:0> + 0x000080

See Table 7-1 for

:

Interrupt Vector Details

:

(1)

Interrupt Vector 116

Interrupt Vector 117

Interrupt Vector 118

Interrupt Vector 119

Interrupt Vector 120

:

BSLIM<12:0> + 0x0000FC

(1)

BSLIM<12:0> + 0x0000FE

(1)

BSLIM<12:0> + 0x000100

(1)

BSLIM<12:0> + 0x000102

(1)

BSLIM<12:0> + 0x000104

:

(1)

Interrupt Vector 244

Interrupt Vector 245

BSLIM<12:0> + 0x0001FC

(1)

BSLIM<12:0> + 0x0001FE

Note 1: The address depends on the size of the Boot Segment defined by BSLIM<12:0>.

[(BSLIM<12:0> – 1) x 0x400] + Offset.

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TABLE 7-1:

INTERRUPT VECTOR DETAILS

Interrupt Bit Location

Vector

#

IRQ

#

Interrupt Source

IVT Address

Flag

Enable

Priority

Highest Natural Order Priority

INT0 – External Interrupt 0

IC1 – Input Capture 1

OC1 – Output Compare 1

T1 – Timer1

8

9

0

1

0x000014

0x000016

0x000018

0x00001A

0x00001C-0x000020

0x000022

0x000024

0x000026

0x000028

0x00002A

0x00002C

0x00002E

0x000030

0x000032

0x000034

0x000036

0x000038

0x00003A

0x00003C

IFS0<0>

IFS0<1>

IFS0<2>

IFS0<3>

—

IEC0<0>

IEC0<1>

IEC0<2>

IPC0<2:0>

IPC0<6:4>

IPC0<10:8>

10

2

11

3

IEC0<3> IPC0<14:12>

Reserved

12–14

15

4–6

7

—

T2 – Timer2

IFS0<7>

IFS0<8>

IFS0<9>

IEC0<7> IPC1<14:12>

T3 – Timer3

16

8

IEC0<8>

IEC0<9>

IPC2<2:0>

IPC2<6:4>

SPI1E – SPI1 Error

17

9

SPI1 – SPI1 Transfer Done

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC – ADC Global Convert Done

Reserved

18

10

11

12

13

14

15

16

17

18

19

20

IFS0<10> IEC0<10> IPC2<10:8>

IFS0<11> IEC0<11> IPC2<14:12>

19

20

IFS0<12> IEC0<12>

IFS0<13> IEC0<13>

IPC3<2:0>

IPC3<6:4>

—

21

22

—

NVM – NVM Write Complete

SI2C1 – I2C1 Slave Event

MI2C1 – I2C1 Master Event

CMP1 – Analog Comparator 1 Interrupt

CN – Input Change Interrupt

INT1 – External Interrupt 1

Reserved

23

IFS0<15> IEC0<15> IPC3<14:12>

24

IFS1<0>

IFS1<1>

IFS1<2>

IFS1<3>

IFS1<4>

—

IEC1<0>

IEC1<1>

IEC1<2>

IPC4<2:0>

IPC4<6:4>

IPC4<10:8>

25

26

27

IEC1<3> IPC4<14:12>

28

IEC1<4>

—

IPC5<2:0>

29-36

37

21-28 0x00003E-0x00004C

29 0x00004E

30-56 0x000050-0x000084

57 0x000086

55-64 0x000088-0x000094

65 0x000096

66-72 0x000098-0x0000A4

73 0x0000A6

—

IPC7<6:4>

—

INT2 – External Interrupt 2

Reserved

IFS1<13> IEC1<13>

38-64

65

—

IFS3<9>

—

IEC3<9>

—

PSEM – PWM Special Event Match

Reserved

IPC14<6:4>

—

63-72

73

U1E – UART1 Error Interrupt

Reserved

IFS4<1>

—

IEC4<1>

—

IPC16<6:4>

—

74-80

81

PWM Secondary Special Event Match

Reserved

IFS4<9>

—

IEC4<9>

—

IPC18<6:4>

—

82-101 74-93 0x0000A8-0x0000CE

PWM1 – PWM1 Interrupt

PWM2 – PWM2 Interrupt

PWM3 – PWM3 Interrupt

Reserved

102

103

104

94

95

96

0x0000D0

0x0000D2

0x0000D4

IFS5<14> IEC5<14> IPC23<10:8>

IFS5<15> IEC5<15> IPC23<14:12>

IFS6<0>

—

IEC6<0>

—

IPC24<2:0>

—

105-110 97-102 0x0000D6-0x0000E0

111 103 0x0000E2

112-117 104-109 0x0000E4-0x0000EE

CMP2 – Analog Comparator 2 Interrupt

Reserved

IFS6<7>

—

IEC6<7> IPC25<14:12>

—

AN0 Conversion Done

AN1 Conversion Done

AN2 Conversion Done

AN3 Conversion Done

AN4 Conversion Done

AN5 Conversion Done

AN6 Conversion Done

AN7 Conversion Done

118

119

120

121

122

123

124

125

110

111

112

113

114

115

116

117

0x0000F0

0x0000F2

0x0000F4

0x0000F6

0x0000F8

0x0000FA

0x0000FC

0x0000FE

IFS6<14> IEC6<14> IPC27<10:8>

IFS6<15> IEC6<15> IPC27<14:12>

IFS7<0>

IFS7<1>

IFS7<2>

IFS7<3>

IFS7<4>

IFS7<5>

IEC7<0>

IEC7<1>

IPC28<2:0>

IPC28<6:4>

IEC7<2> IPC28<10:8>

IEC7<3> IPC28<14:12>

IEC7<4>

IEC7<5>

IPC29<2:0>

IPC29<6:4>

DS70005208E-page 76

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TABLE 7-1:

INTERRUPT VECTOR DETAILS (CONTINUED)

Interrupt Bit Location

Vector

#

IRQ

#

Interrupt Source

IVT Address

Flag

Enable

Priority

Reserved

126-158 118-150 0x000100-0x000140

—

AN8 Conversion Done

AN9 Conversion Done

AN10 Conversion Done

AN11 Conversion Done

AN12 Conversion Done

AN13 Conversion Done

AN14 Conversion Done

Reserved

159

160

161

162

163

164

165

151

152

153

154

155

156

157

0x000142

0x000144

0x000146

0x000148

0x00014A

0x00014C

0x00014E

IFS9<7>

IFS9<8>

IFS9<9>

IEC9<7> IPC37<14:12>

IEC9<8>

IEC9<9>

IPC38<2:0>

IPC38<6:4>

IFS9<10> IEC9<10> IPC38<10:8>

IFS9<11> IEC9<11> IPC38<14:12>

IFS9<12> IEC9<12> IPC39<2:0>

IFS9<13> IEC9<13> IPC39<6:4>

166-180 158-172 0x000150-0x00016C

181 173 0x00016E

182-184 174-176 0x000170-0x000174

—

I2C1 – I2C1 Bus Collision

Reserved

IFS10<13> IEC10<13> IPC43<6:4>

—

ADCMP0 – ADC Digital Comparator 0

ADCMP1 – ADC Digital Comparator 1

ADFL0 – ADC Filter 0

Reserved

185

186

187

177

178

179

0x000176

0x000178

0x00017A

IFS11<1> IEC11<1> IPC44<6:4>

IFS11<2> IEC11<2> IPC44<10:8>

IFS11<3> IEC11<3> IPC44<14:12>

188-253 180-245 0x00017C-0x0001FE

—

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7.4.3

IECx

7.3

Interrupt Resources

The IECx registers maintain all of the interrupt enable

bits. These control bits are used to individually enable

interrupts from the peripherals or external signals.

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

7.4.4

IPCx

7.3.1

KEY RESOURCES

The IPCx registers are used to set the Interrupt Priority

Level (IPL) for each source of interrupt. Each user

interrupt sources can be assigned to one of seven

priority levels.

• “Interrupts” (DS70000600) in the

“dsPIC33/PIC24 Family Reference Manual”

• Code Samples

• Application Notes

• Software Libraries

• Webinars

7.4.5

INTTREG

The INTTREG register contains the associated

interrupt vector number and the new CPU Interrupt

Priority Level, which are latched into the Vector

Number (VECNUM<7:0>) and Interrupt Level bits

(ILR<3:0>) fields in the INTTREG register. The new

Interrupt Priority Level is the priority of the pending

interrupt.

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

7.4

Interrupt Control and Status

Registers

The interrupt sources are assigned to the IFSx, IECx

and IPCx registers in the same sequence as they are

listed in Table 7-1. For example, the INT0 (External

Interrupt 0) is shown as having Vector Number 8 and a

natural order priority of 0. Thus, the INT0IF bit is found

in IFS0<0>, the INT0IE bit in IEC0<0> and the

INT0IP<2:0> bits in the first position of IPC0

(IPC0<2:0>).

dsPIC33EPXXGS202 family devices implement the

following registers for the interrupt controller:

• INTCON1

• INTCON2

• INTCON3

• INTCON4

• INTTREG

7.4.6

STATUS/CONTROL REGISTERS

Although these registers are not specifically part of the

interrupt control hardware, two of the CPU Control

registers contain bits that control interrupt functionality.

For more information on these registers refer to

“CPU” (DS70359) in the “dsPIC33/PIC24 Family

Reference Manual”.

7.4.1

INTCON1 THROUGH INTCON4

Global interrupt control functions are controlled from

INTCON1, INTCON2, INTCON3 and INTCON4.

INTCON1 contains the Interrupt Nesting Disable bit

(NSTDIS), as well as the control and status flags for the

processor trap sources.

• The CPU STATUS Register, SR, contains the

IPL<2:0> bits (SR<7:5>). These bits indicate the

current CPU Interrupt Priority Level. The user

software can change the current CPU Interrupt

Priority Level by writing to the IPLx bits.

The INTCON2 register controls external interrupt

request signal behavior, contains the Global Interrupt

Enable bit (GIE) and the Alternate Interrupt Vector Table

Enable bit (AIVTEN).

• The CORCON register contains the IPL3 bit

which, together with IPL<2:0>, also indicates the

current CPU priority level. IPL3 is a read-only bit

so that trap events cannot be masked by the user

software.

INTCON3 contains the status flags for the Auxiliary

PLL and DOstack overflow status trap sources.

The INTCON4 register contains the Software

Generated Hard Trap Status bit (SGHT).

All Interrupt registers are described in Register 7-3

through Register 7-7 in the following pages.

7.4.2

IFSx

The IFSx registers maintain all of the interrupt request

flags. Each source of interrupt has a status bit, which is

set by the respective peripherals or external signal and

is cleared via software.

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REGISTER 7-1:

SR: CPU STATUS REGISTER⁽¹⁾

R/W-0

OA

R/W-0

OB

R/W-0

SA

R/W-0

SB

R/C-0

OAB

R/C-0

SAB

R-0

DA

R/W-0

DC

bit 15

bit 8

(3)

R/W-0

R-0

RA

R/W-0

N

R/W-0

OV

R/W-0

Z

R/W-0

C

(2)

IPL2

IPL1

IPL0

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’= Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

(2,3)

bit 7-5

IPL<2:0>: CPU Interrupt Priority Level Status bits

111= CPU Interrupt Priority Level is 7 (15); user interrupts are disabled

110= CPU Interrupt Priority Level is 6 (14)

101= CPU Interrupt Priority Level is 5 (13)

100= CPU Interrupt Priority Level is 4 (12)

011= CPU Interrupt Priority Level is 3 (11)

010= CPU Interrupt Priority Level is 2 (10)

001= CPU Interrupt Priority Level is 1 (9)

000= CPU Interrupt Priority Level is 0 (8)

Note 1: For complete register details, see Register 3-1.

2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority

Level. The value in parentheses indicates the IPL, if IPL<3> = 1. User interrupts are disabled when

IPL<3> = 1.

3: The IPL<2:0> Status bits are read-only when the NSTDIS bit (INTCON1<15>) = 1.

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REGISTER 7-2:

CORCON: CORE CONTROL REGISTER⁽¹⁾

R/W-0

VAR

U-0

—

R/W-0

US1

R/W-0

US0

R/W-0

EDT

R-0

DL2

DL1

DL0

bit 15

bit 8

R/W-0

SATA

R/W-0

SATB

R/W-1

R/W-0

R/C-0

R-0

R/W-0

RND

R/W-0

IF

(2)

SATDW

ACCSAT

IPL3

SFA

bit 7

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’= Bit is set

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 3

VAR: Variable Exception Processing Latency Control bit

1= Variable exception processing latency

0= Fixed exception processing latency

(2)

IPL3: CPU Interrupt Priority Level Status bit 3

1= CPU Interrupt Priority Level is greater than 7

0= CPU Interrupt Priority Level is 7 or less

Note 1: For complete register details, see Register 3-2.

2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.

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REGISTER 7-3:

INTCON1: INTERRUPT CONTROL REGISTER 1

R/W-0

NSTDIS

bit 15

R/W-0

OVAERR

OVBERR

COVAERR

COVBERR

OVATE

OVBTE

COVTE

bit 8

R/W-0

SFTACERR

bit 7

R/W-0

U-0

—

R/W-0

U-0

—

DIV0ERR

MATHERR

ADDRERR

STKERR

OSCFAIL

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

bit 9

NSTDIS: Interrupt Nesting Disable bit

1= Interrupt nesting is disabled

0= Interrupt nesting is enabled

OVAERR: Accumulator A Overflow Trap Flag bit

1= Trap was caused by overflow of Accumulator A

0= Trap was not caused by overflow of Accumulator A

OVBERR: Accumulator B Overflow Trap Flag bit

1= Trap was caused by overflow of Accumulator B

0= Trap was not caused by overflow of Accumulator B

COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit

1= Trap was caused by catastrophic overflow of Accumulator A

0= Trap was not caused by catastrophic overflow of Accumulator A

COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit

1= Trap was caused by catastrophic overflow of Accumulator B

0= Trap was not caused by catastrophic overflow of Accumulator B

OVATE: Accumulator A Overflow Trap Enable bit

1= Trap overflow of Accumulator A

0= Trap is disabled

OVBTE: Accumulator B Overflow Trap Enable bit

1= Trap overflow of Accumulator B

0= Trap is disabled

bit 8

COVTE: Catastrophic Overflow Trap Enable bit

1= Trap on catastrophic overflow of Accumulator A or B is enabled

0= Trap is disabled

bit 7

SFTACERR: Shift Accumulator Error Status bit

1= Math error trap was caused by an invalid accumulator shift

0= Math error trap was not caused by an invalid accumulator shift

bit 6

DIV0ERR: Divide-by-Zero Error Status bit

1= Math error trap was caused by a divide-by-zero

0= Math error trap was not caused by a divide-by-zero

bit 5

bit 4

Unimplemented: Read as ‘0’

MATHERR: Math Error Status bit

1= Math error trap has occurred

0= Math error trap has not occurred

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REGISTER 7-3:

INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)

bit 3

bit 2

bit 1

bit 0

ADDRERR: Address Error Trap Status bit

1= Address error trap has occurred

0= Address error trap has not occurred

STKERR: Stack Error Trap Status bit

1= Stack error trap has occurred

0= Stack error trap has not occurred

OSCFAIL: Oscillator Failure Trap Status bit

1= Oscillator failure trap has occurred

0= Oscillator failure trap has not occurred

Unimplemented: Read as ‘0’

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REGISTER 7-4:

INTCON2: INTERRUPT CONTROL REGISTER 2

R/W-1

GIE

R/W-0

DISI

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SWTRAP

AIVTEN

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

INT2EP

INT1EP

INT0EP

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

GIE: Global Interrupt Enable bit

1= Interrupts and associated IE bits are enabled

0= Interrupts are disabled, but traps are still enabled

DISI: DISIInstruction Status bit

1= DISIinstruction is active

0= DISIinstruction is not active

SWTRAP: Software Trap Status bit

1= Software trap is enabled

0= Software trap is disabled

bit 12-9

bit 8

Unimplemented: Read as ‘0’

AIVTEN: Alternate Interrupt Vector Table Enable

1= Uses Alternate Interrupt Vector Table

0= Uses standard Interrupt Vector Table

bit 7-3

bit 2

Unimplemented: Read as ‘0’

INT2EP: External Interrupt 2 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

bit 1

bit 0

INT1EP: External Interrupt 1 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

INT0EP: External Interrupt 0 Edge Detect Polarity Select bit

1= Interrupt on negative edge

0= Interrupt on positive edge

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REGISTER 7-5:

INTCON3: INTERRUPT CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

NAE

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

APLL

DOOVR

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

NAE: NVM Address Error Soft Trap Status bit

1= NVM address error soft trap has occurred

0= NVM address error soft trap has not occurred

bit 7-5

bit 4

Unimplemented: Read as ‘0’

DOOVR: DOStack Overflow Soft Trap Status bit

1= DOstack overflow soft trap has occurred

0= DOstack overflow soft trap has not occurred

bit 3-1

bit 0

Unimplemented: Read as ‘0’

APLL: Auxiliary PLL Loss of Lock Soft Trap Status bit

1= APLL lock soft trap has occurred

0= APLL lock soft trap has not occurred

REGISTER 7-6:

INTCON4: INTERRUPT CONTROL REGISTER 4

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SGHT

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-1

bit 0

Unimplemented: Read as ‘0’

SGHT: Software Generated Hard Trap Status bit

1= Software generated hard trap has occurred

0= Software generated hard trap has not occurred

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REGISTER 7-7:

INTTREG: INTERRUPT CONTROL AND STATUS REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R-0

ILR3

ILR2

ILR1

ILR0

bit 15

bit 8

R-0

VECNUM7

bit 7

R-0

VECNUM6

VECNUM5 VECNUM4 VECNUM3

VECNUM2

VECNUM1

VECNUM0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-12

bit 11-8

Unimplemented: Read as ‘0’

ILR<3:0>: New CPU Interrupt Priority Level bits

1111= CPU Interrupt Priority Level is 15

•

0001= CPU Interrupt Priority Level is 1

0000= CPU Interrupt Priority Level is 0

bit 7-0

VECNUM<7:0>: Vector Number of Pending Interrupt bits

11111111= 255, Reserved; do not use

•

00001001= 9, IC1 – Input Capture 1

00001000= 8, INT0 – External Interrupt 0

00000111= 7, Reserved; do not use

00000110= 6, Generic soft error trap

00000101= 5, Reserved; do not use

00000100= 4, Math error trap

00000011= 3, Stack error trap

00000010= 2, Generic hard trap

00000001= 1, Address error trap

00000000= 0, Oscillator fail trap

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NOTES:

DS70005208E-page 86

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The dsPIC33EPXXGS202 family oscillator system

provides:

8.0

OSCILLATOR CONFIGURATION

Note 1: This data sheet summarizes the

• On-Chip Phase-Locked Loop (PLL) to Boost

Internal Operating Frequency on Select Internal

and External Oscillator Sources

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Oscillator Module”

(DS70005131) in the “dsPIC33/PIC24

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com)

• On-the-Fly Clock Switching between Various

Clock Sources

• Doze mode for System Power Savings

• Fail-Safe Clock Monitor (FSCM) that Detects

Clock Failure and Permits Safe Application

Recovery or Shutdown

• Configuration bits for Clock Source Selection

• Auxiliary PLL for ADC and PWM

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

A simplified diagram of the oscillator system is shown

in Figure 8-1.

FIGURE 8-1:

OSCILLATOR SYSTEM DIAGRAM

DOZE<2:0>

Primary Oscillator (POSC)

OSC1

XT, HS, EC

XTPLL, HSPLL,

POSCCLK

S2

(2)

CY

F

S3

S1

ECPLL, FRCPLL, (FPLLO

)

PLL

S1/S3

(1)

FVCO

OSC2

(2)

POSCMD<1:0>

FP

÷ 2

FRCCLK

FRCDIVN

FRC

Oscillator

FOSC

S7

FRCDIV<2:0>

TUN<5:0>

FRCDIV16

FRC

S6

S0

÷ 16

LPRC

Oscillator

S5

Clock Switch

NOSC<2:0>

Reset

Clock Fail

S0

FNOSC<2:0>

WDT, PWRT,

FSCM

AUXILIARY CLOCK GENERATOR CIRCUIT BLOCK DIAGRAM

(1)

FVCO

FRCCLK

0

1

ACLK

PWM/ADC

to LFSR

1

0

1

0

APLL x 16

÷ N

POSCCLK

GND

0

ASRCSEL

FRCSEL

ENAPLL

SELACLK APSTSCLR<2:0>⁽³⁾

Note 1: See Figure 8-2 for the source of the FVCO signal.

2: The term, F , refers to the clock source for all the peripherals, while FCY (or MIPS) refers to the clock source

for the CPU. Throughout this document, FCY and F are used interchangeably, except in the case of Doze

mode. F and FCY will be different when Doze mode is used in any ratio other than 1:1.

P

3: The auxiliary clock postscaler must be configured to divide-by-1 (APSTSCLR<2:0> = 111) for proper

operation of the PWM and ADC modules.

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Instruction execution speed or device operating

frequency, FCY, is given by Equation 8-1.

8.1

CPU Clocking System

The dsPIC33EPXXGS202 family of devices provides

six system clock options:

EQUATION 8-1:

DEVICE OPERATING

FREQUENCY

• Fast RC (FRC) Oscillator

• FRC Oscillator with Phase-Locked Loop (PLL)

• FRC Oscillator with Postscaler

• Primary (XT, HS or EC) Oscillator

• Primary Oscillator with PLL

F

CY = FOSC/2

Figure 8-2 is a block diagram of the PLL module.

Equation 8-2 provides the relationship between input

frequency (FIN) and output frequency (FPLLO).

• Low-Power RC (LPRC) Oscillator

Equation 8-3 provides the relationship between input

frequency (FIN) and VCO frequency (FVCO).

FIGURE 8-2:

PLL BLOCK DIAGRAM

(1)

F

PLLO  120 MHz @ +125ºC

0.8 MHz < FPLLI < 8.0 MHz

(1)

120 MH

Z

< FVCO < 340 MHZ

PLLO  140 MHz @ +85ºC

F

PLLI

F

VCO

FPLLO

FIN

÷ N1

PFD

VCO

÷ N2

PLLPRE<4:0>

PLLPOST<1:0>

÷ M

PLLDIV<8:0>

Note 1: This frequency range must be met at all times.

EQUATION 8-2:

FPLLO CALCULATION

(PLLDIV<8:0> + 2)

(PLLPRE<4:0> + 2)  2(PLLPOST<1:0> + 1)

M

F

PLLO = FIN



= FIN 

)

(

)

N1  N2

Where:

N1 = PLLPRE<4:0> + 2

N2 = 2 x (PLLPOST<1:0> + 1)

M = PLLDIV<8:0> + 2

EQUATION 8-3:

FVCO CALCULATION

(PLLDIV<8:0> + 2)

(PLLPRE<4:0> + 2)

M

N1

F

VCO = FIN



= FIN 

(

)

( )

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TABLE 8-1:

CONFIGURATION BIT VALUES FOR CLOCK SELECTION

Oscillator Mode Oscillator Source POSCMD<1:0> FNOSC<2:0>

See

Notes

Fast RC Oscillator with Divide-by-N (FRCDIVN)

Fast RC Oscillator with Divide-by-16

Low-Power RC Oscillator (LPRC)

Primary Oscillator (HS) with PLL (HSPLL)

Primary Oscillator (XT) with PLL (XTPLL)

Primary Oscillator (EC) with PLL (ECPLL)

Primary Oscillator (HS)

Internal

Primary

Internal

xx

10

01

00

10

01

00

xx

111

110

101

011

010

001

1, 2

1

Primary Oscillator (XT)

Primary Oscillator (EC)

1

Fast RC Oscillator (FRC) with Divide-by-N and

PLL (FRCPLL)

Fast RC Oscillator (FRC)

Internal

xx

000

1

Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.

2: This is the default oscillator mode for an unprogrammed (erased) device.

8.2

Auxiliary Clock Generation

8.3

Oscillator Resources

The auxiliary clock generation is used for peripherals

that need to operate at a frequency unrelated to the

system clock, such as PWM or ADC.

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

The primary oscillator and internal FRC oscillator

sources can be used with an Auxiliary PLL (APLL) to

obtain the auxiliary clock. The Auxiliary PLL has a fixed

16x multiplication factor.

8.3.1

KEY RESOURCES

• “Oscillator Module” (DS70005131) in the

“dsPIC33/PIC24 Family Reference Manual”

The auxiliary clock has the following configuration

restrictions:

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• For proper PWM operation, auxiliary clock

generation must be configured for 120 MHz (see

Parameter OS56 in Section 25.0 “Electrical Char-

acteristics”). If a slower frequency is desired, the

PWM Input Clock Prescaler (Divider) Select bits

(PCLKDIV<2:0>) should be used.

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

• To achieve 1.04 ns PWM resolution, the auxiliary

clock must use the 16x Auxiliary PLL (APLL). All

other clock sources will have a minimum PWM

resolution of 8 ns.

• If the primary PLL is used as a source for the

auxiliary clock, the primary PLL should be

configured up to a maximum operation of

30 MIPS or less.

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8.4

Oscillator Control Registers

REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER⁽¹⁾

U-0

—

R-0

U-0

—

R/W-y

(2)

COSC2

COSC1

COSC0

NOSC2

NOSC1

NOSC0

bit 8

bit 15

R/W-0

CLKLOCK

bit 7

R/W-0

R-0

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

(3)

IOLOCK

LOCK

CF

OSWEN

bit 0

Legend:

y = Value set from Configuration bits on POR

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-12

COSC<2:0>: Current Oscillator Selection bits (read-only)

111= Fast RC Oscillator (FRC) with Divide-by-n

110= Fast RC Oscillator (FRC) with Divide-by-16

101= Low-Power RC Oscillator (LPRC)

100= Reserved

011= Primary Oscillator (XT, HS, EC) with PLL

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 11

Unimplemented: Read as ‘0’

(2)

bit 10-8

NOSC<2:0>: New Oscillator Selection bits

111= Fast RC Oscillator (FRC) with Divide-by-n

110= Fast RC Oscillator (FRC) with Divide-by-16

101= Low-Power RC Oscillator (LPRC)

100= Reserved

011= Primary Oscillator (XT, HS, EC) with PLL

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator (FRC) with Divide-by-N and PLL (FRCPLL)

000= Fast RC Oscillator (FRC)

bit 7

CLKLOCK: Clock Lock Enable bit

1= If (FCKSM0 = 1), then clock and PLL configurations are locked; if (FCKSM0 = 0), then clock and

PLL configurations may be modified

0= Clock and PLL selections are not locked, configurations may be modified

bit 6

bit 5

IOLOCK: I/O Lock Enable bit

1= I/O lock is active

0= I/O lock is not active

LOCK: PLL Lock Status bit (read-only)

1= Indicates that PLL is in lock or PLL start-up timer is satisfied

0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled

Note 1: Writes to this register require an unlock sequence.

2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-

ted. This applies to clock switches in either direction. In these instances, the application must switch to

FRC mode as a transitional clock source between the two PLL modes.

3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an

actual oscillator failure and trigger an oscillator failure trap.

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REGISTER 8-1:

OSCCON: OSCILLATOR CONTROL REGISTER⁽¹⁾(CONTINUED)

bit 4

bit 3

Unimplemented: Read as ‘0’

(3)

CF: Clock Fail Detect bit

1= FSCM has detected a clock failure

0= FSCM has not detected a clock failure

bit 2-1

bit 0

Unimplemented: Read as ‘0’

OSWEN: Oscillator Switch Enable bit

1= Requests oscillator switch to selection specified by the NOSC<2:0> bits

0= Oscillator switch is complete

Note 1: Writes to this register require an unlock sequence.

2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permit-

ted. This applies to clock switches in either direction. In these instances, the application must switch to

FRC mode as a transitional clock source between the two PLL modes.

3: This bit should only be cleared in software. Setting the bit in software (= 1) will have the same effect as an

actual oscillator failure and trigger an oscillator failure trap.

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REGISTER 8-2:

CLKDIV: CLOCK DIVISOR REGISTER

R/W-0 R/W-1 R/W-1 R/W-0

R/W-0

ROI

R/W-0

(1)

(2,3)

DOZE2

DOZE1

DOZE0

DOZEN

FRCDIV2

FRCDIV1

FRCDIV0

bit 15

bit 8

R/W-0

R/W-1

U-0

—

R/W-0

PLLPOST1

bit 7

PLLPOST0

PLLPRE4

PLLPRE3

PLLPRE2

PLLPRE1

PLLPRE0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

ROI: Recover on Interrupt bit

1= Interrupts will clear the DOZEN bit and the processor clock, and the peripheral clock ratio is set

to 1:1

0= Interrupts have no effect on the DOZEN bit

(1)

bit 14-12

DOZE<2:0>: Processor Clock Reduction Select bits

111= FCY divided by 128

110= FCY divided by 64

101= FCY divided by 32

100= FCY divided by 16

011= FCY divided by 8 (default)

010= FCY divided by 4

001= FCY divided by 2

000= FCY divided by 1

(2,3)

bit 11

DOZEN: Doze Mode Enable bit

1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks

0= Processor clock and peripheral clock ratio is forced to 1:1

bit 10-8

FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits

111= FRC divided by 256

110= FRC divided by 64

101= FRC divided by 32

100= FRC divided by 16

011= FRC divided by 8

010= FRC divided by 4

001= FRC divided by 2

000= FRC divided by 1 (default)

bit 7-6

bit 5

PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)

11= Output divided by 8

10= Reserved

01= Output divided by 4 (default)

00= Output divided by 2

Unimplemented: Read as ‘0’

Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to

DOZE<2:0> are ignored.

2: This bit is cleared when the ROI bit is set and an interrupt occurs.

3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to

set the DOZEN bit is ignored.

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REGISTER 8-2:

bit 4-0

CLKDIV: CLOCK DIVISOR REGISTER (CONTINUED)

PLLPRE<4:0>: PLL Phase Detector Input Divider Select bits (also denoted as ‘N1’, PLL prescaler)

11111= Input divided by 33

•

00001= Input divided by 3

00000= Input divided by 2 (default)

Note 1: The DOZE<2:0> bits can only be written to when the DOZEN bit is clear. If DOZEN = 1, any writes to

DOZE<2:0> are ignored.

2: This bit is cleared when the ROI bit is set and an interrupt occurs.

3: The DOZEN bit cannot be set if DOZE<2:0> = 000. If DOZE<2:0> = 000, any attempt by user software to

set the DOZEN bit is ignored.

REGISTER 8-3:

PLLFBD: PLL FEEDBACK DIVISOR REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PLLDIV8

bit 15

bit 8

R/W-0

bit 0

R/W-0

bit 7

R/W-0

R/W-1

R/W-0

PLLDIV<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8-0

Unimplemented: Read as ‘0’

PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)

111111111= 513

•

000110000= 50 (default)

•

000000010= 4

000000001= 3

000000000= 2

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REGISTER 8-4:

OSCTUN: FRC OSCILLATOR TUNING REGISTER⁽¹⁾

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

R/W-0

TUN<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

TUN<5:0>: FRC Oscillator Tuning bits

011111= Maximum frequency deviation of 1.457% (7.477 MHz)

011110= Center frequency + 1.41% (7.474 MHz)

•

000001= Center frequency + 0.047% (7.373 MHz)

000000= Center frequency (7.37 MHz nominal)

111111= Center frequency – 0.047% (7.367 MHz)

•

100001= Center frequency – 1.457% (7.263 MHz)

100000= Minimum frequency deviation of -1.5% (7.259 MHz)

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the

FRC frequency over a wide range of temperatures. The tuning step-size is an approximation and is neither

characterized nor tested.

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REGISTER 8-5:

ACLKCON: AUXILIARY CLOCK DIVISOR CONTROL REGISTER

R/W-0

ENAPLL

bit 15

R-0

R/W-1

U-0

—

U-0

—

R/W-1

APLLCK

SELACLK

APSTSCLR2 APSTSCLR1 APSTSCLR0

bit 0

R/W-0

ASRCSEL

bit 7

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRCSEL

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

ENAPLL: Auxiliary PLL Enable bit

1= APLL is enabled

0= APLL is disabled

APLLCK: APLL Locked Status bit (read-only)

1= Indicates that the Auxiliary PLL is in lock

0= Indicates that the Auxiliary PLL is not in lock

SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider bit

1= Auxiliary oscillators provide the source clock for the auxiliary clock divider

0= Primary PLL (FVCO) provides the source clock for the auxiliary clock divider

bit 12-11

bit 10-8

Unimplemented: Read as ‘0’

APSTSCLR<2:0>: Auxiliary Clock Output Divider bits

111= Divided by 1

110= Divided by 2

101= Divided by 4

100= Divided by 8

011= Divided by 16

010= Divided by 32

001= Divided by 64

000= Divided by 256

bit 7

ASRCSEL: Select Reference Clock Source for Auxiliary Clock bit

1= Primary oscillator is the clock source

0= No clock input is selected

bit 6

FRCSEL: Select Reference Clock Source for Auxiliary PLL bit

1= Selects FRC clock for Auxiliary PLL

0= Input clock source is determined by the ASRCSEL bit setting

bit 5-0

Unimplemented: Read as ‘0’

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REGISTER 8-6:

LFSR: LINEAR FEEDBACK SHIFT REGISTER

U-0

—

R/W-0

bit 8

R/W-0

bit 0

LFSR<14:8>

bit 15

R/W-0

bit 7

R/W-0

LFSR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

LFSR<14:0>: Pseudorandom Data bits

bit 14-0

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9.1

Clock Frequency and Clock

Switching

9.0

POWER-SAVING FEATURES

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Watchdog Timer and

Power-Saving Modes” (DS70615) in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com)

The dsPIC33EPXXGS202 family devices allow a wide

range of clock frequencies to be selected under appli-

cation control. If the system clock configuration is not

locked, users can choose low-power or high-precision

oscillators by simply changing the NOSCx bits

(OSCCON<10:8>). The process of changing a system

clock during operation, as well as limitations to the

process, are discussed in more detail in Section 8.0

“Oscillator Configuration”.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

9.2

Instruction-Based Power-Saving

Modes

The dsPIC33EPXXGS202 family devices have two

special power-saving modes that are entered

through the execution of a special PWRSAV instruc-

tion. Sleep mode stops clock operation and halts all

code execution. Idle mode halts the CPU and code

execution, but allows peripheral modules to continue

operation. The assembler syntax of the PWRSAV

instruction is shown in Example 9-1.

The dsPIC33EPXXGS202 family devices provide the

ability to manage power consumption by selectively

managing clocking to the CPU and the peripherals. In

general, a lower clock frequency and a reduction in

the number of peripherals being clocked constitutes

lower consumed power.

Note: SLEEP_MODE and IDLE_MODE are con-

stants defined in the assembler include

file for the selected device.

dsPIC33EPXXGS202 family devices can manage

power consumption in four ways:

• Clock Frequency

Sleep and Idle modes can be exited as a result of an

enabled interrupt, WDT time-out or a device Reset. When

the device exits these modes, it is said to “wake-up”.

• Instruction-Based Sleep and Idle modes

• Software-Controlled Doze mode

• Selective Peripheral Control in Software

Combinations of these methods can be used to

selectively tailor an application’s power consumption

while still maintaining critical application features, such

as timing-sensitive communications.

EXAMPLE 9-1:

PWRSAV INSTRUCTION SYNTAX

PWRSAV #SLEEP_MODE

PWRSAV #IDLE_MODE

; Put the device into Sleep mode

; Put the device into Idle mode

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9.2.1

SLEEP MODE

9.2.2

IDLE MODE

The following occur in Sleep mode:

The following occur in Idle mode:

• The system clock source is shut down. If an

on-chip oscillator is used, it is turned off.

• The CPU stops executing instructions.

• The WDT is automatically cleared.

• The device current consumption is reduced to a

minimum, provided that no I/O pin is sourcing

current.

• The system clock source remains active. By

default, all peripheral modules continue to operate

normally from the system clock source, but can

also be selectively disabled (see Section 9.4

“Peripheral Module Disable”).

• The Fail-Safe Clock Monitor does not operate,

since the system clock source is disabled.

• If the WDT or FSCM is enabled, the LPRC also

remains active.

• The LPRC clock continues to run in Sleep mode if

the WDT is enabled.

• The WDT, if enabled, is automatically cleared

prior to entering Sleep mode.

The device wakes from Idle mode on any of these

events:

• Some device features or peripherals can continue

to operate. This includes items such as the Input

Change Notification on the I/O ports, or peripherals

that use an external clock input.

• Any interrupt that is individually enabled

• Any device Reset

• A WDT time-out

On wake-up from Idle mode, the clock is reapplied to

the CPU and instruction execution will begin (2-4 clock

cycles later), starting with the instruction following the

PWRSAVinstruction or the first instruction in the ISR.

• Any peripheral that requires the system clock

source for its operation is disabled.

The device wakes up from Sleep mode on any of the

these events:

All peripherals also have the option to discontinue

operation when Idle mode is entered to allow for

increased power savings. This option is selectable in

the control register of each peripheral (for example, the

TSIDL bit in the Timer1 Control register (T1CON<13>).

• Any interrupt source that is individually enabled

• Any form of device Reset

• A WDT time-out

On wake-up from Sleep mode, the processor restarts

with the same clock source that was active when Sleep

mode was entered.

9.2.3

INTERRUPTS COINCIDENT WITH

POWER SAVE INSTRUCTIONS

For optimal power savings, the internal regulator and

the Flash regulator can be configured to go into stand-

by when Sleep mode is entered by clearing the VREGS

(RCON<8>) and VREGSF (RCON<11>) bits (default

configuration).

Any interrupt that coincides with the execution of a

PWRSAVinstruction is held off until entry into Sleep or

Idle mode has completed. The device then wakes up

from Sleep or Idle mode.

If the application requires a faster wake-up time, and

can accept higher current requirements, the VREGS

(RCON<8>) and VREGSF (RCON<11>) bits can be set

to keep the internal regulator and the Flash regulator

active during Sleep mode.

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9.3

Doze Mode

9.4

Peripheral Module Disable

The preferred strategies for reducing power consump-

tion are changing clock speed and invoking one of the

power-saving modes. In some circumstances, this

cannot be practical. For example, it may be necessary

for an application to maintain uninterrupted synchronous

communication, even while it is doing nothing else.

Reducing system clock speed can introduce communi-

cation errors, while using a power-saving mode can stop

communications completely.

The Peripheral Module Disable (PMD) registers

provide a method to disable a peripheral module by

stopping all clock sources supplied to that module.

When a peripheral is disabled using the appropriate

PMDx control bit, the peripheral is in a minimum power

consumption state. The control and status registers

associated with the peripheral are also disabled, so

writes to those registers do not have any effect and

read values are invalid.

Doze mode is a simple and effective alternative method

to reduce power consumption while the device is still

executing code. In this mode, the system clock

continues to operate from the same source and at the

same speed. Peripheral modules continue to be

clocked at the same speed, while the CPU clock speed

is reduced. Synchronization between the two clock

domains is maintained, allowing the peripherals to

access the SFRs while the CPU executes code at a

slower rate.

A peripheral module is enabled only if both the associ-

ated bit in the PMDx register is cleared and the peripheral

is supported by the specific dsPIC^®DSC variant. If the

peripheral is present in the device, it is enabled in the

PMD register by default.

Note:

If a PMDx bit is set, the corresponding

module is disabled after a delay of one

instruction cycle. Similarly, if a PMDx bit is

cleared, the corresponding module is

enabled after a delay of one instruction

cycle (assuming the module control regis-

ters are already configured to enable

module operation).

Doze mode is enabled by setting the DOZEN bit

(CLKDIV<11>). The ratio between peripheral and core

clock speed is determined by the DOZE<2:0> bits

(CLKDIV<14:12>). There are eight possible configu-

rations, from 1:1 to 1:128, with 1:1 being the default

setting.

9.5

Power-Saving Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

Programs can use Doze mode to selectively reduce

power consumption in event-driven applications. This

allows clock-sensitive functions, such as synchronous

communications, to continue without interruption while

the CPU Idles, waiting for something to invoke an inter-

rupt routine. An automatic return to full-speed CPU

operation on interrupts can be enabled by setting the

ROI bit (CLKDIV<15>). By default, interrupt events

have no effect on Doze mode operation.

9.5.1

KEY RESOURCES

• “Watchdog Timer and Power-Saving Modes”

(DS70615) in the “dsPIC33/PIC24 Family

Reference Manual”

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

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REGISTER 9-1:

PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

T3MD

R/W-0

T2MD

R/W-0

T1MD

U-0

—

R/W-0

U-0

—

PWMMD

bit 15

bit 8

R/W-0

I2C1MD

bit 7

U-0

—

R/W-0

U1MD

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

SPI1MD

ADCMD

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13

Unimplemented: Read as ‘0’

T3MD: Timer3 Module Disable bit

1= Timer3 module is disabled

0= Timer3 module is enabled

bit 12

bit 11

T2MD: Timer2 Module Disable bit

1= Timer2 module is disabled

0= Timer2 module is enabled

T1MD: Timer1 Module Disable bit

1= Timer1 module is disabled

0= Timer1 module is enabled

bit 10

bit 9

Unimplemented: Read as ‘0’

PWMMD: PWM Module Disable bit

1= PWM module is disabled

0= PWM module is enabled

bit 8

bit 7

Unimplemented: Read as ‘0’

I2C1MD: I2C1 Module Disable bit

1= I2C1 module is disabled

0= I2C1 module is enabled

bit 6

bit 5

Unimplemented: Read as ‘0’

U1MD: UART1 Module Disable bit

1= UART1 module is disabled

0= UART1 module is enabled

bit 4

bit 3

Unimplemented: Read as ‘0’

SPI1MD: SPI1 Module Disable bit

1= SPI1 module is disabled

0= SPI1 module is enabled

bit 2-1

bit 0

Unimplemented: Read as ‘0’

ADCMD: ADC Module Disable bit

1= ADC module is disabled

0= ADC module is enabled

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REGISTER 9-2:

PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

IC1MD

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

OC1MD

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-9

bit 8

Unimplemented: Read as ‘0’

IC1MD: Input Capture 1 Module Disable bit

1= Input Capture 1 module is disabled

0= Input Capture 1 module is enabled

bit 7-1

bit 0

Unimplemented: Read as ‘0’

OC1MD: Output Compare 1 Module Disable bit

1= Output Compare 1 module is disabled

0= Output Compare 1 module is enabled

REGISTER 9-3:

PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

CMPMD

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10

Unimplemented: Read as ‘0’

CMPMD: Comparator Module Disable bit

1= Comparator module is disabled

0= Comparator module is enabled

bit 9-0

Unimplemented: Read as ‘0’

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REGISTER 9-4:

PMD6: PERIPHERAL MODULE DISABLE CONTROL REGISTER 6

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

PWM3MD

PWM2MD

PWM1MD

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10

Unimplemented: Read as ‘0’

PWM3MD: PWM3 Module Disable bit

1= PWM3 module is disabled

0= PWM3 module is enabled

bit 9

PWM2MD: PWM2 Module Disable bit

1= PWM2 module is disabled

0= PWM2 module is enabled

bit 8

PWM1MD: PWM1 Module Disable bit

1= PWM1 module is disabled

0= PWM1 module is enabled

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 9-5:

PMD7: PERIPHERAL MODULE DISABLE CONTROL REGISTER 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CMP2MD

CMP1MD

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

PGA1MD

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9

Unimplemented: Read as ‘0’

CMP2MD: Comparator Channel 2 (CMP2) Module Disable bit

1= CMP2 module is disabled

0= CMP2 module is enabled

bit 8

CMP1MD: Comparator Channel 1 (CMP1) Module Disable bit

1= CMP1 module is disabled

0= CMP1 module is enabled

bit 7-2

bit 1

Unimplemented: Read as ‘0’

PGA1MD: PGA1 Module Disable bit

1= PGA1 module is disabled

0= PGA1 module is enabled

bit 0

Unimplemented: Read as ‘0’

REGISTER 9-6:

PMD8: PERIPHERAL MODULE DISABLE CONTROL REGISTER 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

PGA2MD

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-11

bit 10

Unimplemented: Read as ‘0’

PGA2MD: PGA2 Module Disable bit

1= PGA2 module is disabled

0= PGA2 module is enabled

bit 9-0

Unimplemented: Read as ‘0’

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NOTES:

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has ownership of the output data and control signals of

the I/O pin. The logic also prevents “loop through”, in

10.0 I/O PORTS

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to

be a comprehensive reference source.

To complement the information in this data

sheet, refer to “I/O Ports” (DS70000598)

in the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

which a port’s digital output can drive the input of a

peripheral that shares the same pin. Figure 10-1 illus-

trates how ports are shared with other peripherals and

the associated I/O pin to which they are connected.

When a peripheral is enabled and the peripheral is

actively driving an associated pin, the use of the pin as a

general purpose output pin is disabled. The I/O pin can

be read, but the output driver for the parallel port bit is

disabled. If a peripheral is enabled, but the peripheral is

not actively driving a pin, that pin can be driven by a port.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

All port pins have eight registers directly associated with

their operation as digital I/Os. The Data Direction register

(TRISx) determines whether the pin is an input or an out-

put. If the data direction bit is a ‘1’, then the pin is an input.

All port pins are defined as inputs after a Reset. Reads

from the latch (LATx), read the latch. Writes to the latch,

write the latch. Reads from the port (PORTx) read the

port pins, while writes to the port pins write the latch.

Many of the device pins are shared among the

peripherals and the Parallel I/O ports. All I/O input ports

feature Schmitt Trigger inputs for improved noise

immunity.

Any bit and its associated data and control registers that

are not valid for a particular device are disabled. This

means the corresponding LATx and TRISx registers,

and the port pin are read as zeros.

10.1 Parallel I/O (PIO) Ports

Generally, a Parallel I/O port that shares a pin with a

peripheral is subservient to the peripheral. The

peripheral’s output buffer data and control signals are

provided to a pair of multiplexers. The multiplexers

select whether the peripheral or the associated port

When a pin is shared with another peripheral or func-

tion that is defined as an input only, it is nevertheless

regarded as a dedicated port because there is no

other competing source of outputs.

FIGURE 10-1:

BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE

Peripheral Module

Output Multiplexers

Peripheral Input Data

Peripheral Module Enable

Peripheral Output Enable

Peripheral Output Data

I/O

1

0

Output Enable

Output Data

1

0

PIO Module

Read TRISx

Data Bus

D

Q

I/O Pin

WR TRISx

CK

TRISx Latch

D

Q

WR LATx +

WR PORTx

CK

Data Latch

Read LATx

Input Data

Read PORTx

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10.1.1

OPEN-DRAIN CONFIGURATION

10.2.1

I/O PORT WRITE/READ TIMING

In addition to the PORTx, LATx and TRISx registers

for data control, port pins can also be individually

configured for either digital or open-drain output. This

is controlled by the Open-Drain Control register,

ODCx, associated with each port. Setting any of the

bits configures the corresponding pin to act as an

open-drain output.

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP, as shown in Example 10-1.

10.3 Input Change Notification (ICN)

The Input Change Notification function of the I/O ports

allows devices to generate interrupt requests to the

processor in response to a Change-of-State (COS) on

selected input pins. This feature can detect input

Change-of-States even in Sleep mode, when the clocks

are disabled. Every I/O port pin can be selected

(enabled) for generating an interrupt request on a

Change-of-State.

The open-drain feature allows the generation of out-

puts other than VDD by using external pull-up resistors.

The maximum open-drain voltage allowed on any pin

is the same as the maximum VIH specification for that

particular pin.

See the “Pin Diagrams” section for the available

5V tolerant pins and Table 25-11 for the maximum

V

IH specification for each pin.

Three control registers are associated with the ICN

functionality of each I/O port. The CNENx registers

contain the ICN interrupt enable control bits for each of

the input pins. Setting any of these bits enables an ICN

interrupt for the corresponding pins.

10.2 Configuring Analog and Digital

Port Pins

The ANSELx register controls the operation of the

analog port pins. The port pins that are to function as

analog inputs or outputs must have their corresponding

ANSELx and TRISx bits set. In order to use port pins for

I/O functionality with digital modules, such as timers,

UART, etc., the corresponding ANSELx bit must be

cleared.

Each I/O pin also has a weak pull-up and a weak

pull-down connected to it. The pull-ups and pull-

downs act as a current source, or sink source,

connected to the pin, and eliminate the need for

external resistors when push button or keypad

devices are connected. The pull-ups and pull-downs

are enabled separately, using the CNPUx and the

CNPDx registers, which contain the control bits for

each of the pins. Setting any of the control bits

enables the weak pull-ups and/or pull-downs for the

corresponding pins.

The ANSELx register has a default value of 0xFFFF;

therefore, all pins that share analog functions are

analog (not digital) by default.

Pins with analog functions affected by the ANSELx

registers are listed with a buffer type of analog in the

Pinout I/O Descriptions (see Table 1-1).

Note:

Pull-ups and pull-downs on Input Change

Notification pins should always be

disabled when the port pin is configured

as a digital output.

If the TRISx bit is cleared (output) while the ANSELx bit

is set, the digital output level (VOH or VOL) is converted

by an analog peripheral, such as the ADC module or

comparator module.

EXAMPLE 10-1:

PORT WRITE/READ

When the PORTx register is read, all pins configured as

analog input channels are read as cleared (a low level).

MOV

NOP

0xFF00, W0

; Configure PORTB<15:8>

; as inputs

; and PORTB<7:0>

; as outputs

; Delay 1 cycle

; Next Instruction

Pins configured as digital inputs do not convert an

analog input. Analog levels on any pin, defined as a

digital input (including the ANx pins), can cause the

input buffer to consume current that exceeds the

device specifications.

W0, TRISB

BTSS PORTB, #13

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In comparison, some digital only peripheral modules

are never included in the Peripheral Pin Select feature.

10.4 Peripheral Pin Select (PPS)

A major challenge in general purpose devices is

providing the largest possible set of peripheral features

while minimizing the conflict of features on I/O pins.

The challenge is even greater on low pin count devices.

In an application where more than one peripheral

needs to be assigned to a single pin, inconvenient

work arounds in application code, or a complete

redesign, may be the only option.

This is because the peripheral’s function requires

special I/O circuitry on a specific port and cannot be

easily connected to multiple pins. One example

2

includes I C modules. A similar requirement excludes

all modules with analog inputs, such as the ADC

Converter.

A key difference between remappable and non-

remappable peripherals is that remappable peripherals

are not associated with a default I/O pin. The peripheral

must always be assigned to a specific I/O pin before it

can be used. In contrast, non-remappable peripherals

are always available on a default pin, assuming that the

peripheral is active and not conflicting with another

peripheral.

Peripheral Pin Select configuration provides an alter-

native to these choices by enabling peripheral set

selection and their placement on a wide range of I/O

pins. By increasing the pinout options available on a

particular device, users can better tailor the device to

their entire application, rather than trimming the

application to fit the device.

When a remappable peripheral is active on a given I/O

pin, it takes priority over all other digital I/Os and digital

communication peripherals associated with the pin.

Priority is given regardless of the type of peripheral that

is mapped. Remappable peripherals never take priority

over any analog functions associated with the pin.

The Peripheral Pin Select configuration feature

operates over a fixed subset of digital I/O pins. Users

may independently map the input and/or output of most

digital peripherals to any one of these I/O pins. Hard-

ware safeguards are included that prevent accidental

or spurious changes to the peripheral mapping once it

has been established.

10.4.3

CONTROLLING PERIPHERAL PIN

SELECT

10.4.1

AVAILABLE PINS

Peripheral Pin Select features are controlled through

two sets of SFRs: one to map peripheral inputs and one

to map outputs. Because they are separately con-

trolled, a particular peripheral’s input and output (if the

peripheral has both) can be placed on any selectable

function pin without constraint.

The number of available pins is dependent on the

particular device and its pin count. Pins that support the

Peripheral Pin Select feature include the label, “RPn”,

in their full pin designation, where “n” is the remappable

pin number. “RPn” is used to designate pins that

support both remappable input and output functions.

The association of a peripheral to a peripheral-

selectable pin is handled in two different ways,

depending on whether an input or output is being

mapped.

10.4.2

AVAILABLE PERIPHERALS

The peripherals managed by the Peripheral Pin Select

are all digital only peripherals. These include general

serial communications (UART and SPI), general pur-

pose timer clock inputs, timer-related peripherals (input

capture and output compare) and interrupt-on-change

inputs.

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10.4.4

INPUT MAPPING

10.4.4.1

Virtual Connections

The inputs of the Peripheral Pin Select options are

mapped on the basis of the peripheral. That is, a control

register associated with a peripheral dictates the pin it

will be mapped to. The RPINRx registers are used to

configure peripheral input mapping (see Register 10-1

through Register 10-15). Each register contains sets of

8-bit fields, with each set associated with one of the

remappable peripherals. Programming a given periph-

eral’s bit field with an appropriate 8-bit value maps the

RPn pin with the corresponding value to that peripheral.

For any given device, the valid range of values for any

bit field corresponds to the maximum number of

Peripheral Pin Selections supported by the device.

The dsPIC33EPXXGS202 devices support six virtual

RPn pins (RP176-RP181), which are identical in

functionality to all other RPn pins, with the exception of

pinouts. These six pins are internal to the devices and

are not connected to a physical device pin.

These pins provide a simple way for inter-peripheral

connection without utilizing

a physical pin. For

example, the output of the analog comparator can be

connected to RP176 and the PWM Fault input can be

configured for RP176 as well. This configuration allows

the analog comparator to trigger PWM Faults without

the use of an actual physical pin on the device.

For example, Figure 10-2 illustrates remappable pin

selection for the U1RX input.

FIGURE 10-2:

REMAPPABLE INPUT FOR

U1RX

U1RXR<7:0>

0

RP0

RP1

RP2

1

U1RX Input

to Peripheral

2

n

RPn

Note:

For input only, Peripheral Pin Select functionality

does not have priority over TRISx settings.

Therefore, when configuring an RPn pin for

input, the corresponding bit in the TRISx register

must also be configured for input (set to ‘1’).

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TABLE 10-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)

(1)

Input Name

External Interrupt 1

Function Name

Register

Configuration Bits

INT1

INT2

RPINR0

RPINR1

INT1R<7:0>

INT2R<7:0>

T1CKR<7:0>

T2CKR<7:0>

T3CKR<7:0>

IC1R<7:0>

External Interrupt 2

Timer1 External Clock

Timer2 External Clock

Timer3 External Clock

Input Capture 1

T1CK

T2CK

T3CK

IC1

RPINR2

RPINR3

RPINR7

Output Compare Fault A

PWM Fault 1

OCFA

FLT1

RPINR11

RPINR12

RPINR13

RPINR18

RPINR20

RPINR21

RPINR37

RPINR38

RPINR42

RPINR43

OCFAR<7:0>

FLT1R<7:0>

FLT2R<7:0>

FLT3R<7:0>

FLT4R<7:0>

U1RXR<7:0>

U1CTSR<7:0>

SDI1R<7:0>

SCK1R<7:0>

SS1R<7:0>

PWM Fault 2

FLT2

PWM Fault 3

FLT3

PWM Fault 4

FLT4

UART1 Receive

UART1 Clear-to-Send

SPI1 Data Input

SPI1 Clock Input

SPI1 Slave Select

PWM Synchronous Input 1

PWM Synchronous Input 2

PWM Fault 5

U1RX

U1CTS

SDI1

SCK1

SS1

SYNCI1

SYNCI2

FLT5

SYNCI1R<7:0>

SYNCI2R<7:0>

FLT5R<7:0>

FLT6R<7:0>

FLT7R<7:0>

FLT8R<7:0>

PWM Fault 6

FLT6

PWM Fault 7

FLT7

PWM Fault 8

FLT8

Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.

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10.4.5

OUTPUT MAPPING

10.4.5.1

Mapping Limitations

In contrast to inputs, the outputs of the Peripheral Pin

Select options are mapped on the basis of the pin. In this

case, a control register associated with a particular pin

dictates the peripheral output to be mapped. The RPORx

registers are used to control output mapping. Each

register contains sets of 6-bit fields, with each set associ-

ated with one RPn pin (see Register 10-16 through

Register 10-26). The value of the bit field corresponds to

one of the peripherals and that peripheral’s output is

mapped to the pin (see Table 10-2 and Figure 10-3).

The control schema of the peripheral select pins is not

limited to a small range of fixed peripheral configura-

tions. There are no mutual or hardware-enforced

lockouts between any of the peripheral mapping SFRs.

Literally any combination of peripheral mappings

across any or all of the RPn pins is possible. This

includes both many-to-one and one-to-many mappings

of peripheral inputs, and outputs to pins. While such

mappings may be technically possible from a configu-

ration point of view, they may not be supportable from

an electrical point of view.

A null output is associated with the Output register

Reset value of ‘0’. This is done to ensure that remap-

pable outputs remain disconnected from all output pins

by default.

FIGURE 10-3: MULTIPLEXING REMAPPABLE

OUTPUTS FOR RPn

RPnR<5:0>

Default

0

U1TX Output

1

U1RTS Output

2

RPn

Output Data

SYNCO1 Output

45

SYNCO2 Output

46

TABLE 10-2: OUTPUT SELECTION FOR REMAPPABLE PINS (RPn)

Function

Default PORT

RPnR<5:0>

Output Name

000000

000001

000010

000101

000110

000111

010000

011000

011001

101101

101110

RPn tied to Default Pin

U1TX

RPn tied to UART1 Transmit

U1RTS/BCLK

SDO1

RPn tied to UART1 Request-to-Send

RPn tied to SPI1 Data Output

SCK1

RPn tied to SPI1 Clock Output

SS1

RPn tied to SPI1 Slave Select

OC1

RPn tied to Output Compare 1 Output

RPn tied to Analog Comparator 1 Output

RPn tied to Analog Comparator 2 Output

RPn tied to PWM Primary Master Time Base Sync Output

RPn tied to PWM Secondary Master Time Base Sync Output

ACMP1

ACMP2

SYNCO1

SYNCO2

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3. Most I/O pins have multiple functions. Referring to

the device pin diagrams in this data sheet, the prior-

10.5 I/O Helpful Tips

1. In some cases, certain pins, as defined in

Table 25-11 under “Injection Current”, have internal

protection diodes to VDD and VSS. The term,

“Injection Current”, is also referred to as “Clamp

Current”. On designated pins, with sufficient exter-

nal current-limiting precautions by the user, I/O pin

input voltages are allowed to be greater or less

than the data sheet absolute maximum ratings,

with respect to the VSS and VDD supplies. Note

that when the user application forward biases

either of the high or low side internal input clamp

diodes, that the resulting current being injected

into the device, that is clamped internally by the

ities of the functions allocated to any pins are

indicated by reading the pin name from left-to-right.

The left most function name takes precedence over

any function to its right in the naming convention.

For example: AN16/T2CK/T7CK/RC1. This indi-

cates that AN16 is the highest priority in this

example and will supersede all other functions to its

right in the list. Those other functions to its right,

even if enabled, would not work as long as any

other function to its left was enabled. This rule

applies to all of the functions listed for a given pin.

4. Each pin has an internal weak pull-up resistor and

pull-down resistor that can be configured using the

CNPUx and CNPDx registers, respectively. These

resistors eliminate the need for external resistors

in certain applications. The internal pull-up is up to

~(VDD – 0.8), not VDD. This value is still above the

minimum VIH of CMOS and TTL devices.

VDD and VSS power rails, may affect the ADC

accuracy by four to six counts.

2. I/O pins that are shared with any analog input pin

(i.e., ANx) are always analog pins by default after

any Reset. Consequently, configuring a pin as an

analog input pin automatically disables the digital

input pin buffer and any attempt to read the digital

input level by reading PORTx or LATx will always

return a ‘0’, regardless of the digital logic level on

the pin. To use a pin as a digital I/O pin on a shared

ANx pin, the user application needs to configure the

Analog Pin Configuration registers in the I/O ports

module (i.e., ANSELx) by setting the appropriate bit

that corresponds to that I/O port pin to a ‘0’.

5. When driving LEDs directly, the I/O pin can source

or sink more current than what is specified in the

VOH/IOH and VOL/IOL DC characteristics specifica-

tion. The respective IOH and IOL current rating only

applies to maintaining the corresponding output at

or above the VOH, and at or below the VOL levels.

However, for LEDs, unlike digital inputs of an exter-

nally connected device, they are not governed by

the same minimum VIH/VIL levels. An I/O pin output

can safely sink or source any current less than

that listed in the Absolute Maximum Ratings in

Section 25.0 “Electrical Characteristics”of this

data sheet. For example:

Note:

Although it is not possible to use a digital

input pin when its analog function is

enabled, it is possible to use the digital I/O

output function, TRISx = 0x0, while the

analog function is also enabled. However,

this is not recommended, particularly if the

analog input is connected to an external

analog voltage source, which would create

signal contention between the analog

signal and the output pin driver.

VOH = 2.4V @ IOH = -8 mA and VDD = 3.3V

The maximum output current sourced by any 8 mA

I/O pin = 12 mA.

LED source current < 12 mA is technically permitted.

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6. The Peripheral Pin Select (PPS) pin mapping rules

10.6 I/O Ports Resources

are as follows:

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

a) Only one “output” function can be active on

a given pin at any time, regardless if it is a

dedicated or remappable function (one pin,

one output).

b) It is possible to assign a “remappable output”

function to multiple pins and externally short

or tie them together for increased current

drive.

10.6.1

KEY RESOURCES

• “I/O Ports” (DS70000598) in the “dsPIC33/PIC24

Family Reference Manual”

• Code Samples

• Application Notes

• Software Libraries

• Webinars

c) If any “dedicated output” function is enabled

on a pin, it will take precedence over any

remappable “output” function.

d) If any “dedicated digital” (input or output)

function is enabled on a pin, any number of

“input” remappable functions can be

mapped to the same pin.

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

e) If any “dedicated analog” function(s) are

enabled on a given pin, “digital input(s)” of

any kind will all be disabled, although a

single “digital output”, at the user’s caution-

ary discretion, can be enabled and active as

long as there is no signal contention with an

external analog input signal. For example, it

is possible for the ADC to convert the digital

output logic level, or to toggle a digital out-

put on a comparator or ADC input, provided

there is no external analog input, such as

for a built-in self-test.

f) Any number of “input” remappable functions

can be mapped to the same pin(s) at the

same time, including to any pin with a single

output from either a dedicated or remappable

“output”.

g) The TRISx registers control only the digital

I/O output buffer. Any other dedicated or

remappable active “output” will automatically

override the TRISx setting. The TRISx reg-

ister does not control the digital logic

“input” buffer. Remappable digital “inputs”

do not automatically override TRISx set-

tings, which means that the TRISx bit must

be set to input for pins with only remappable

input function(s) assigned.

h) All analog pins are enabled by default after

any Reset and the corresponding digital input

buffer on the pin has been disabled. Only the

Analog Pin Select (ANSELx) registers control

the digital input buffer, not the TRISx register.

The user must disable the analog function on

a pin using the Analog Pin Select registers in

order to use any “digital input(s)” on a

corresponding pin, no exceptions.

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10.7 Peripheral Pin Select Registers

REGISTER 10-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0

R/W-0

bit 8

INT1R<7:0>

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

INT1R<7:0>: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

Unimplemented: Read as ‘0’

REGISTER 10-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

INT2R<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

INT2R<7:0>: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2

R/W-0

bit 8

T1CKR<7:0>

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

T1CKR<7:0>: Assign Timer1 External Clock (T1CK) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 10-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3

R/W-0

T3CKR7

T3CKR6

T3CKR5

T3CKR4

T3CKR3

T3CKR2

T3CKR1

T3CKR0

bit 15

bit 8

R/W-0

T2CKR7

T2CKR6

T2CKR5

T2CKR4

T2CKR3

T2CKR2

T2CKR1

T2CKR0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

T3CKR<7:0>: Assign Timer3 External Clock (T3CK) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

0000001= Input tied to RP1

0000000= Input tied to VSS

bit 7-0

T2CKR<7:0>: Assign Timer2 External Clock (T2CK) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

IC1R<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

IC1R<7:0>: Assign Input Capture 1 (IC1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

REGISTER 10-6: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

OCFAR<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

OCFAR<7:0>: Assign Output Compare Fault A (OCFA) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-7: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12

R/W-0

FLT2R7

FLT2R6

FLT2R5

FLT2R4

FLT2R3

FLT2R2

FLT2R1

FLT2R0

bit 15

bit 8

R/W-0

FLT1R7

FLT1R6

FLT1R5

FLT1R4

FLT1R3

FLT1R2

FLT1R1

FLT1R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

FLT2R<7:0>: Assign PWM Fault 2 (FLT2) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

FLT1R<7:0>: Assign PWM Fault 1 (FLT1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-8: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13

R/W-0

FLT4R7

FLT4R6

FLT4R5

FLT4R4

FLT4R3

FLT4R2

FLT4R1

FLT4R0

bit 15

bit 8

R/W-0

FLT3R7

FLT3R6

FLT3R5

FLT3R4

FLT3R3

FLT3R2

FLT3R1

FLT3R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

FLT4R<7:0>: Assign PWM Fault 4 (FLT4) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

FLT3R<7:0>: Assign PWM Fault 3 (FLT3) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-9: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18

R/W-0

U1CTSR7

U1CTSR6

U1CTSR5

U1CTSR4

U1CTSR3

U1CTSR2

U1CTSR1

U1CTSR0

bit 15

bit 8

R/W-0

U1RXR7

U1RXR6

U1RXR5

U1RXR4

U1RXR3

U1RXR2

U1RXR1

U1RXR0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

U1CTSR<7:0>: Assign UART1 Clear-to-Send (U1CTS) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

U1RXR<7:0>: Assign UART1 Receive (U1RX) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-10: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20

R/W-0

SCK1INR0

bit 8

SCK1INR7

SCK1INR6

SCK1INR5 SCK1INR4 SCK1INR3

SCK1INR2

SCK1INR1

bit 15

R/W-0

SDI1R0

bit 0

SDI1R7

SDI1R6

SDI1R5

SDI1R4

SDI1R3

SDI1R2

SDI1R1

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

SCK1INR<7:0>: Assign SPI1 Clock Input (SCK1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

SDI1R<7:0>: Assign SPI1 Data Input (SDI1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-11: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

SS1R<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

SS1R<7:0>: Assign SPI1 Slave Select (SS1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

REGISTER 10-12: RPINR37: PERIPHERAL PIN SELECT INPUT REGISTER 37

R/W-0

bit 8

SYNCI1R<7:0>

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

SYNCI1R<7:0>: Assign PWM Synchronization Input 1 (SYNCI1) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 10-13: RPINR38: PERIPHERAL PIN SELECT INPUT REGISTER 38

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

SYNCI2R<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

bit 7-0

Unimplemented: Read as ‘0’

SYNCI2R<7:0>: Assign PWM Synchronization Input 2 (SYNCI2) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-14: RPINR42: PERIPHERAL PIN SELECT INPUT REGISTER 42

R/W-0

FLT6R7

FLT6R6

FLT6R5

FLT6R4

FLT6R3

FLT6R2

FLT6R1

FLT6R0

bit 15

bit 8

R/W-0

FLT5R7

FLT5R6

FLT5R5

FLT5R4

FLT5R3

FLT5R2

FLT5R1

FLT5R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

FLT6R<7:0>: Assign PWM Fault 6 (FLT6) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

FLT5R<7:0>: Assign PWM Fault 5 (FLT5) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-15: RPINR43: PERIPHERAL PIN SELECT INPUT REGISTER 43

R/W-0

FLT8R7

FLT8R6

FLT8R5

FLT8R4

FLT8R3

FLT8R2

FLT8R1

FLT8R0

bit 15

bit 8

R/W-0

FLT7R7

FLT7R6

FLT7R5

FLT7R4

FLT7R3

FLT7R2

FLT7R1

FLT7R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-8

FLT8R<7:0>: Assign PWM Fault 8 (FLT8) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

bit 7-0

FLT7R<7:0>: Assign PWM Fault 7 (FLT7) to the Corresponding RPn Pin bits

10110101= Input tied to RP181

10110100= Input tied to RP180

•

00000001= Input tied to RP1

00000000= Input tied to VSS

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REGISTER 10-16: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0

U-0

—

U-0

—

R/W-0

RP33R5

RP33R4

RP33R3

RP33R2

RP33R1

RP33R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP32R5

RP32R4

RP32R3

RP32R2

RP32R1

RP32R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP33R<5:0>: Peripheral Output Function is Assigned to RP33 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP32R<5:0>: Peripheral Output Function is Assigned to RP32 Output Pin bits

(see Table 10-2 for peripheral function numbers)

REGISTER 10-17: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1

U-0

—

U-0

—

R/W-0

RP35R5

RP35R4

RP35R3

RP35R2

RP35R1

RP35R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP34R5

RP34R4

RP34R3

RP34R2

RP34R1

RP34R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP35R<5:0>: Peripheral Output Function is Assigned to RP35 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP34R<5:0>: Peripheral Output Function is Assigned to RP34 Output Pin bits

(see Table 10-2 for peripheral function numbers)

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REGISTER 10-18: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2

U-0

—

U-0

—

R/W-0

RP37R5

RP37R4

RP37R3

RP37R2

RP37R1

RP37R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP36R5

RP36R4

RP36R3

RP36R2

RP36R1

RP36R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP37R<5:0>: Peripheral Output Function is Assigned to RP37 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP36R<5:0>: Peripheral Output Function is Assigned to RP36 Output Pin bits

(see Table 10-2 for peripheral function numbers)

REGISTER 10-19: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3

U-0

—

U-0

—

R/W-0

RP39R5

RP39R4

RP39R3

RP39R2

RP39R1

RP39R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP38R5

RP38R4

RP38R3

RP38R2

RP38R1

RP38R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP39R<5:0>: Peripheral Output Function is Assigned to RP39 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP38R<5:0>: Peripheral Output Function is Assigned to RP38 Output Pin bits

(see Table 10-2 for peripheral function numbers)

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REGISTER 10-20: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4

U-0

—

U-0

—

R/W-0

RP41R5

RP41R4

RP41R3

RP41R2

RP41R1

RP41R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP40R5

RP40R4

RP40R3

RP40R2

RP40R1

RP40R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP41R<5:0>: Peripheral Output Function is Assigned to RP41 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP40R<5:0>: Peripheral Output Function is Assigned to RP40 Output Pin bits

(see Table 10-2 for peripheral function numbers)

REGISTER 10-21: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5

U-0

—

U-0

—

R/W-0

RP43R5

RP43R4

RP43R3

RP43R2

RP43R1

RP43R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP42R5

RP42R4

RP42R3

RP42R2

RP42R1

RP42R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP43R<5:0>: Peripheral Output Function is Assigned to RP43 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP42R<5:0>: Peripheral Output Function is Assigned to RP42 Output Pin bits

(see Table 10-2 for peripheral function numbers)

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REGISTER 10-22: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6

U-0

—

U-0

—

R/W-0

RP45R5

RP45R4

RP45R3

RP45R2

RP45R1

RP45R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP44R5

RP44R4

RP44R3

RP44R2

RP44R1

RP44R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP45R<5:0>: Peripheral Output Function is Assigned to RP45 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP44R<5:0>: Peripheral Output Function is Assigned to RP44 Output Pin bits

(see Table 10-2 for peripheral function numbers)

REGISTER 10-23: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7

U-0

—

U-0

—

R/W-0

RP47R5

RP47R4

RP47R3

RP47R2

RP47R1

RP47R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP46R5

RP46R4

RP46R3

RP46R2

RP46R1

RP46R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP47R<5:0>: Peripheral Output Function is Assigned to RP47 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP46R<5:0>: Peripheral Output Function is Assigned to RP46 Output Pin bits

(see Table 10-2 for peripheral function numbers)

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REGISTER 10-24: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8

U-0

—

U-0

—

R/W-0

RP177R5

RP177R4

RP177R3

RP177R2

RP177R1

RP177R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP176R5

RP176R4

RP176R3

RP176R2

RP176R1

RP176R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP177R<5:0>: Peripheral Output Function is Assigned to RP177 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP176R<5:0>: Peripheral Output Function is Assigned to RP176 Output Pin bits

(see Table 10-2 for peripheral function numbers)

REGISTER 10-25: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9

U-0

—

U-0

—

R/W-0

RP179R5

RP179R4

RP179R3

RP179R2

RP179R1

RP179R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP178R5

RP178R4

RP178R3

RP178R2

RP178R1

RP178R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP179R<5:0>: Peripheral Output Function is Assigned to RP179 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP178R<5:0>: Peripheral Output Function is Assigned to RP178 Output Pin bits

(see Table 10-2 for peripheral function numbers)

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REGISTER 10-26: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10

U-0

—

U-0

—

R/W-0

RP181R5

RP181R4

RP181R3

RP181R2

RP181R1

RP181R0

bit 15

bit 8

U-0

—

U-0

—

R/W-0

RP180R5

RP180R4

RP180R3

RP180R2

RP180R1

RP180R0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

Unimplemented: Read as ‘0’

RP181R<5:0>: Peripheral Output Function is Assigned to RP181 Output Pin bits

(see Table 10-2 for peripheral function numbers)

bit 7-6

bit 5-0

Unimplemented: Read as ‘0’

RP180R<5:0>: Peripheral Output Function is Assigned to RP180 Output Pin bits

(see Table 10-2 for peripheral function numbers)

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The Timer1 module can operate in one of the following

modes:

11.0 TIMER1

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Timers” (DS70362) in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

• Timer mode

• Gated Timer mode

• Synchronous Counter mode

• Asynchronous Counter mode

In Timer and Gated Timer modes, the input clock is

derived from the internal instruction cycle clock (FCY).

In Synchronous and Asynchronous Counter modes,

the input clock is derived from the external clock input

at the T1CK pin.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The Timer modes are determined by the following bits:

• Timer Clock Source Control bit (TCS): T1CON<1>

• Timer Synchronization Control bit (TSYNC):

T1CON<2>

• Timer Gate Control bit (TGATE): T1CON<6>

The Timer1 module is a 16-bit timer that can operate as

a free-running interval timer/counter.

Timer control bit settings for different operating modes

are provided in Table 11-1.

The Timer1 module has the following unique features

over other timers:

TABLE 11-1: TIMER MODE SETTINGS

• Can be Operated in Asynchronous Counter mode

from an External Clock Source

Mode

Timer

TCS

TGATE

TSYNC

0

1

0

1

x

1

• The External Clock Input (T1CK) can Optionally be

Synchronized to the Internal Device Clock and the

Clock Synchronization is Performed after the

Prescaler

Gated Timer

Synchronous

Counter

A block diagram of Timer1 is shown in Figure 11-1.

Asynchronous

Counter

1

x

0

FIGURE 11-1:

16-BIT TIMER1 MODULE BLOCK DIAGRAM

Gate

Sync

Falling Edge

Detect

1

0

Set T1IF Flag

(1)

F

P

10

00

x1

Prescaler

(/n)

T1CLK

TGATE

Latch

CLK

Data

Reset

TMR1

TCKPS<1:0>

ADC Trigger

0

T1CK

Equal

Prescaler

(/n)

Comparator

1

Sync

TGATE

TSYNC

TCS

TCKPS<1:0>

PR1

Note 1:

FP is the Peripheral Clock.

 2015-2018 Microchip Technology Inc.

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dsPIC33EPXXGS202 FAMILY

11.1.1

KEY RESOURCES

11.1 Timer1 Resources

•

“Timers” (DS70362) in the “dsPIC33/PIC24

Family Reference Manual”

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

DS70005208E-page 132

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11.2 Timer1 Control Register

REGISTER 11-1: T1CON: TIMER1 CONTROL REGISTER

R/W-0

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

(1)

TON

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

R/W-0

U-0

—

(1)

TGATE

TCKPS1

TCKPS0

TSYNC

TCS

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 15

TON: Timer1 On bit

1= Starts 16-bit Timer1

0= Stops 16-bit Timer1

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Timer1 Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer1 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

TCKPS<1:0>: Timer1 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3

bit 2

Unimplemented: Read as ‘0’

(1)

TSYNC: Timer1 External Clock Input Synchronization Select bit

When TCS = 1:

1= Synchronizes external clock input

0= Does not synchronize external clock input

When TCS = 0:

This bit is ignored.

(1)

bit 1

bit 0

TCS: Timer1 Clock Source Select bit

1= External clock is from pin, T1CK (on the rising edge)

0= Peripheral Clock (F

P)

Unimplemented: Read as ‘0’

Note 1: When Timer1 is enabled in External Synchronous Counter mode (TCS = 1, TSYNC = 1, TON = 1), any

attempts by user software to write to the TMR1 register are ignored.

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NOTES:

DS70005208E-page 134

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Individually, both of the 16-bit timers can function as

synchronous timers or counters. They also offer the

12.0 TIMER2/3

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Timers” (DS70362) in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

features listed previously, except for the event trigger;

this is implemented only with Timer2/3. The operating

modes and enabled features are determined by setting

the appropriate bit(s) in the T2CON and T3CON

registers. T2CON details are in Register 12-1. T3CON

details are in Register 12-2.

For 32-bit timer/counter operation, Timer2 is the least

significant word (lsw); Timer3 is the most significant

word (msw) of the 32-bit timers.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Note:

For 32-bit operation, T3CON control bits

are ignored. Only T2CON control bits are

used for setup and control. Timer2 clock

and gate inputs are utilized for the 32-bit

timer modules, but an interrupt is generated

with the Timer3 interrupt flag.

The Timer2/3 module is a 32-bit timer, which can also

be configured as two independent 16-bit timers with

selectable operating modes.

A block diagram for an example 32-bit timer pair

(Timer2/3) is shown in Figure 12-2.

As 32-bit timers, Timer2 and Timer3 operate in three

modes:

12.1 Timer Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Two Independent 16-Bit Timers (e.g., Timer2 and

Timer3) with all 16-Bit Operating modes (except

Asynchronous Counter mode)

• Single 32-Bit Timer

12.1.1

KEY RESOURCES

• Single 32-Bit Synchronous Counter

They also support these features:

•

“Timers” (DS70362) in the “dsPIC33/PIC24

Family Reference Manual”

• Timer Gate Operation

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• Selectable Prescaler Settings

• Timer Operation during Idle and Sleep modes

• Interrupt on a 32-Bit Period Register Match

• Time Base for Input Capture and Output Compare

modules (Timer2 and Timer3 only)

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

 2015-2018 Microchip Technology Inc.

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FIGURE 12-1:

TIMERx BLOCK DIAGRAM (x = 2,3)

Gate

Sync

Falling Edge

Detect

1

0

Set TxIF Flag

(1)

FP

10

00

x1

Prescaler

(/n)

TxCLK

Reset

TGATE

Latch

CLK

Data

TMRx

TCKPS<1:0>

TxCK

ADC

Prescaler

(/n)

Trigger⁽²⁾

Sync

Equal

Comparator

TGATE

TCS

TCKPS<1:0>

PRx

Note 1:

FP is the Peripheral Clock.

2: The ADC trigger is only available on TMR2.

FIGURE 12-2:

TYPE B/TYPE C TIMER PAIR BLOCK DIAGRAM (32-BIT TIMER)

Falling Edge

Detect

Gate

Sync

1

0

Set TyIF Flag

PRx

PRy

TGATE

Data

Equal

Reset

Comparator

(1)

FP

10

00

x1

Prescaler

(/n)

CLK

lsw

TMRx⁽²⁾

msw

Latch

TMRy⁽³⁾

TCKPS<1:0>

TxCK

Prescaler

(/n)

Sync

TMRyHLD

TGATE

TCS

TCKPS<1:0>

Data Bus<15:0>

Note 1:

FP is the Peripheral Clock.

2: Timerx is a Type B timer (x = 2).

3: Timery is a Type C timer (y = 3).

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12.2

Timer2/3 Control Registers

REGISTER 12-1: T2CON: TIMER2 CONTROL REGISTER

R/W-0

TON

U-0

—

R/W-0

TSIDL

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

U-0

—

R/W-0

T32

U-0

—

R/W-0

TCS

U-0

—

TGATE

TCKPS1

TCKPS0

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

TON: Timer2 On bit

When T32 = 1:

1= Starts 32-bit Timer2/3

0= Stops 32-bit Timer2/3

When T32 = 0:

1= Starts 16-bit Timer2

0= Stops 16-bit Timer2

bit 14

bit 13

Unimplemented: Read as ‘0’

TSIDL: Timer2 Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

TGATE: Timer2 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

bit 5-4

bit 3

TCKPS<1:0>: Timer2 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

T32: 32-Bit Timer Mode Select bit

1= Timer2 and Timer3 form a single 32-bit timer

0= Timer2 and Timer3 act as two 16-bit timers

bit 2

bit 1

Unimplemented: Read as ‘0’

TCS: Timer2 Clock Source Select bit

1= External clock is from pin, T2CK (on the rising edge)

0= Peripheral Clock (F

P)

bit 0

Unimplemented: Read as ‘0’

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REGISTER 12-2: T3CON: TIMER3 CONTROL REGISTER

R/W-0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

(1)

(2)

TON

TSIDL

bit 15

bit 8

bit 0

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

U-0

—

(1)

TGATE

TCKPS1

TCKPS0

TCS

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

(1)

bit 15

TON: Timer3 On bit

1= Starts 16-bit Timer3

0= Stops 16-bit Timer3

bit 14

bit 13

Unimplemented: Read as ‘0’

(2)

TSIDL: Timer3 Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-7

bit 6

Unimplemented: Read as ‘0’

(1)

TGATE: Timer3 Gated Time Accumulation Enable bit

When TCS = 1:

This bit is ignored.

When TCS = 0:

1= Gated time accumulation is enabled

0= Gated time accumulation is disabled

(1)

bit 5-4

TCKPS<1:0>: Timer3 Input Clock Prescale Select bits

11= 1:256

10= 1:64

01= 1:8

00= 1:1

bit 3-2

bit 1

Unimplemented: Read as ‘0’

(1)

TCS: Timer3 Clock Source Select bit

1= External clock is from pin, T3CK (on the rising edge)

0= Peripheral Clock (F

P)

bit 0

Unimplemented: Read as ‘0’

Note 1: When 32-bit operation is enabled (T2CON<3> = 1), these bits have no effect on Timer3 operation; all

timer functions are set through T2CON.

2: When 32-bit timer operation is enabled (T32 = 1) in the Timer2 Control register (T2CON<3>), the TSIDL

bit must be cleared to operate the 32-bit timer in Idle mode.

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dsPIC33EPXXGS202 FAMILY

• Synchronous and Trigger modes of Output

Compare Operation, with up to Six

13.0 INPUT CAPTURE

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to

be a comprehensive reference source.

To complement the information in this

data sheet, refer to “Input Capture

with Dedicated Timer” (DS70000352)

in the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

User-Selectable Trigger/Sync Sources Available

• A 4-Level FIFO Buffer for Capturing and Holding

Timer Values for Several Events

• Configurable Interrupt Generation

• Up to Four Clock Sources Available, Driving a

Separate Internal 16-Bit Counter

13.1 Input Capture Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

13.1.1

KEY RESOURCES

•

“Input Capture with Dedicated Timer”

(DS70000352) in the “dsPIC33/PIC24 Family

Reference Manual”

• Code Samples

• Application Notes

The input capture module is useful in applications

requiring frequency (period) and pulse measurements.

The dsPIC33EPXXGS202 family devices support one

input capture channel.

• Software Libraries

• Webinars

Key features of the input capture module include:

• Hardware-Configurable for 32-Bit Operation in all

modes by Cascading Two Adjacent Modules

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

FIGURE 13-1:

INPUT CAPTURE MODULE BLOCK DIAGRAM

ICM<2:0>

ICI<1:0>

Event and

Set IC1IF

Edge Detect Logic

Prescaler

Counter

1:1/4/16

Interrupt

Logic

and

Clock Synchronizer

IC1 Pin

ICTSEL<2:0>

Increment

16

Clock

Select

IC1 Clock

Sources

4-Level FIFO Buffer

IC1TMR

16

Reset

16

Trigger and

Sync Logic

Trigger and

Sync Sources

IC1BUF

System Bus

ICOV, ICBNE

SYNCSEL<4:0>⁽¹⁾

Note 1: The trigger/sync source is enabled by default and is set to Timer3 as a source. This timer must be enabled for

proper IC1 module operation or the trigger/sync source must be changed to another source option.

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13.2 Input Capture Control Registers

REGISTER 13-1: IC1CON1: INPUT CAPTURE CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

ICSIDL

ICTSEL2

ICTSEL1

ICTSEL0

bit 15

bit 8

U-0

—

R/W-0

ICI1

R/W-0

ICI0

R-0, HC, HS R-0, HC, HS

ICOV ICBNE

R/W-0

ICM2

R/W-0

ICM1

R/W-0

ICM0

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15-14

bit 13

Unimplemented: Read as ‘0’

ICSIDL: Input Capture Stop in Idle Control bit

1= Input capture will halt in CPU Idle mode

0= Input capture will continue to operate in CPU Idle mode

bit 12-10

ICTSEL<2:0>: Input Capture Timer Select bits

111= Peripheral Clock (F

110= Reserved

P) is the clock source of the IC1

101= Reserved

100= T1CLK is the clock source of the IC1 (only the synchronous clock is supported)

011= Reserved

010= Reserved

001= T2CLK is the clock source of the IC1

000= T3CLK is the clock source of the IC1

bit 9-7

bit 6-5

Unimplemented: Read as ‘0’

ICI<1:0>: Number of Captures per Interrupt Select bits (this field is not used if ICM<2:0> = 001or 111)

11= Interrupt on every fourth capture event

10= Interrupt on every third capture event

01= Interrupt on every second capture event

00= Interrupt on every capture event

bit 4

ICOV: Input Capture Overflow Status Flag bit (read-only)

1= Input capture buffer overflow has occurred

0= No input capture buffer overflow has occurred

bit 3

ICBNE: Input Capture Buffer Not Empty Status bit (read-only)

1= Input capture buffer is not empty, at least one more capture value can be read

0= Input capture buffer is empty

bit 2-0

ICM<2:0>: Input Capture Mode Select bits

111= Input capture functions as an interrupt pin only in CPU Sleep and Idle modes (rising edge detect

only, all other control bits are not applicable)

110= Unused (module is disabled)

101= Capture mode, every 16th rising edge (Prescaler Capture mode)

100= Capture mode, every 4th rising edge (Prescaler Capture mode)

011= Capture mode, every rising edge (Simple Capture mode)

010= Capture mode, every falling edge (Simple Capture mode)

001= Capture mode, every rising and falling edge (Edge Detect mode, (ICI<1:0>) is not used in this mode)

000= Input capture is turned off

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REGISTER 13-2: IC1CON2: INPUT CAPTURE CONTROL REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

R/W-0, HS

U-0

—

R/W-0

R/W-1

R/W-0

R/W-1

(1)

(2)

(3)

ICTRIG

bit 7

TRIGSTAT

SYNCSEL4

SYNCSEL3

SYNCSEL2

SYNCSEL1

SYNCSEL0

bit 0

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-8

bit 7

Unimplemented: Read as ‘0’

(1)

ICTRIG: Input Capture Trigger Operation Select bit

1= Input source used to trigger the input capture timer (Trigger mode)

0= Input source used to synchronize the input capture timer to a timer of another module

(Synchronization mode)

(2)

bit 6

bit 5

TRIGSTAT: Timer Trigger Status bit

1= IC1TMR has been triggered and is running

0= IC1TMR has not been triggered and is being held clear

Unimplemented: Read as ‘0’

Note 1: The input source is selected by the SYNCSEL<4:0> bits of the IC1CON2 register.

2: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and

cleared in software.

3: Do not use the IC1 module as its own sync or trigger source.

4: This option should only be selected as a trigger source and not as a synchronization source.

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REGISTER 13-2: IC1CON2: INPUT CAPTURE CONTROL REGISTER 2 (CONTINUED)

(3)

bit 4-0

SYNCSEL<4:0>: Input Source Select for Synchronization and Trigger Operation bits

11111 = No sync or trigger source for IC1

11110 = Reserved

11101 = Reserved

11100 = Reserved

11011 = Reserved

11010 = Reserved

11001 = CMP2 module synchronizes or triggers IC1

11000 = CMP1 module synchronizes or triggers IC1

(4)

10111 = Reserved

10110 = Reserved

10101 = Reserved

10100 = Reserved

10011 = Reserved

10010 = Reserved

10001 = Reserved

10000 = Reserved

01111 = Reserved

01110 = Reserved

01101 = Timer3 synchronizes or triggers IC1 (default)

01100 = Timer2 synchronizes or triggers IC1

01011 = Timer1 synchronizes or triggers IC1

01010 = Reserved

01001 = Reserved

01000 = Reserved

00111 = Reserved

00110 = Reserved

00101 = Reserved

00100 = Reserved

00011 = Reserved

00010 = Reserved

00001 = OC1 module synchronizes or triggers IC1

00000 = No sync or trigger source for IC1

Note 1: The input source is selected by the SYNCSEL<4:0> bits of the IC1CON2 register.

2: This bit is set by the selected input source (selected by SYNCSEL<4:0> bits); it can be read, set and

cleared in software.

3: Do not use the IC1 module as its own sync or trigger source.

4: This option should only be selected as a trigger source and not as a synchronization source.

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single output pulse, or a sequence of output pulses, by

changing the state of the output pin on the compare

match events. The output compare module can also

generate interrupts on compare match events.

14.0 OUTPUT COMPARE

Note 1: This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “Output Compare with

Dedicated Timer” (DS70005159) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

web site (www.microchip.com).

14.1 Output Compare Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

14.1.1

KEY RESOURCES

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

•

“Output Compare with Dedicated Timer”

(DS70005159) in the “dsPIC33/PIC24 Family

Reference Manual”

• Code Samples

• Application Notes

• Software Libraries

• Webinars

The output compare module can select one of four

available clock sources for its time base. The module

compares the value of the timer with the value of one or

two Compare registers, depending on the operating

mode selected. The state of the output pin changes

when the timer value matches the Compare register

value. The output compare module generates either a

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

FIGURE 14-1:

OUTPUT COMPARE MODULE BLOCK DIAGRAM

OC1CON1

OC1CON2

OC1R

Rollover/Reset

OC1R Buffer

Comparator

OC1 Pin

Match

Event

Increment

Clock

Select

OC1 Clock

Sources

OC1 Output and

Fault Logic

OC1TMR

Comparator

OC1RS Buffer

Rollover

Reset

OCFA

Match

Event

Match Event

Trigger and

Sync Logic

Trigger and

Sync Sources

SYNCSEL<4:0>

Trigger⁽¹⁾

Rollover/Reset

OC1 Synchronization/Trigger Event

OC1 Interrupt

OC1RS

Reset

Note 1: The trigger/sync source is enabled by default and is set to Timer2 as a source. This timer must be enabled for

OC1 module operation or the trigger/sync source must be changed to another source option.

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14.2 Output Compare Control Registers

REGISTER 14-1: OC1CON1: OUTPUT COMPARE CONTROL REGISTER 1

U-0

—

U-0

—

R/W-0

U-0

—

U-0

—

OCSIDL

OCTSEL2

OCTSEL1

OCTSEL0

bit 15

bit 8

R/W-0

U-0

—

U-0

—

R/W-0, HSC

OCFLTA

R/W-0

OCM2

R/W-0

OCM1

R/W-0

OCM0

ENFLTA

TRIGMODE

bit 7

bit 0

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-14

bit 13

Unimplemented: Read as ‘0’

OCSIDL: Output Compare Stop in Idle Mode Control bit

1= Output compare halts in CPU Idle mode

0= Output compare continues to operate in CPU Idle mode

bit 12-10

OCTSEL<2:0>: Output Compare Clock Select bits

111= Peripheral Clock (F

P)

110= Reserved

101= Reserved

100= T1CLK is the clock source of the OC1 (only the synchronous clock is supported)

011= Reserved

010= Reserved

001= T3CLK is the clock source of the OC1

000= T2CLK is the clock source of the OC1

bit 9-8

bit 7

Unimplemented: Read as ‘0’

ENFLTA: Fault A Input Enable bit

1= Output Compare Fault A input (OCFA) is enabled

0= Output Compare Fault A input (OCFA) is disabled

bit 6-5

bit 4

Unimplemented: Read as ‘0’

OCFLTA: PWM Fault A Condition Status bit

1= PWM Fault A condition on the OCFA pin has occurred

0= No PWM Fault A condition on the OCFA pin has occurred

bit 3

TRIGMODE: Trigger Status Mode Select bit

1= TRIGSTAT (OC1CON2<6>) is cleared when OC1RS = OC1TMR or in software

0= TRIGSTAT is cleared only by software

Note 1: OC1R and OC1RS are double-buffered in PWM mode only.

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REGISTER 14-1: OC1CON1: OUTPUT COMPARE CONTROL REGISTER 1 (CONTINUED)

bit 2-0

OCM<2:0>: Output Compare Mode Select bits

111= Center-Aligned PWM mode: Output is set high when OC1TMR = OC1R and set low when

(1)

OC1TMR = OC1RS

110= Edge-Aligned PWM mode: Output is set high when OC1TMR = 0 and set low when

(1)

OC1TMR = OC1R

101= Double Compare Continuous Pulse mode: Initializes OC1 pin low, toggles OC1 state continuously

on alternate matches of OC1R and OC1RS

100= Double Compare Single-Shot mode: Initializes OC1 pin low, toggles OC1 state on matches of

OC1R and OC1RS for one cycle

011= Single Compare mode: Compare event with OC1R, continuously toggles OC1 pin

010= Single Compare Single-Shot mode: Initializes OC1 pin high, compare event with OC1R, forces

OC1 pin low

001= Single Compare Single-Shot mode: Initializes OC1 pin low, compare event with OC1R, forces

OC1 pin high

000= Output compare channel is disabled

Note 1: OC1R and OC1RS are double-buffered in PWM mode only.

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REGISTER 14-2: OC1CON2: OUTPUT COMPARE CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

FLTMD

FLTOUT

FLTTRIEN

OCINV

bit 15

bit 8

R/W-0

R/W-0, HS

TRIGSTAT

R/W-0

R/W-1

R/W-0

OCTRIG

OCTRIS

SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0

bit 0

bit 7

Legend:

HS = Hardware Settable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

FLTMD: Fault Mode Select bit

1= Fault mode is maintained until the Fault source is removed; the corresponding OCFLTA bit is

cleared in software and a new PWM period starts

0= Fault mode is maintained until the Fault source is removed and a new PWM period starts

bit 14

bit 13

bit 12

FLTOUT: Fault Out bit

1= PWM output is driven high on a Fault

0= PWM output is driven low on a Fault

FLTTRIEN: Fault Output State Select bit

1= OC1 pin is tri-stated on a Fault condition

0= OC1 pin I/O state is defined by the FLTOUT bit on a Fault condition

OCINV: Output Compare Invert bit

1= OC1 output is inverted

0= OC1 output is not inverted

bit 11-8

bit 7

Unimplemented: Read as ‘0’

OCTRIG: Output Compare Trigger/Sync Select bit

1= Triggers OC1 from the source designated by the SYNCSEL<4:0> bits

0= Synchronizes OC1 with the source designated by the SYNCSEL<4:0> bits

bit 6

bit 5

TRIGSTAT: Timer Trigger Status bit

1= Timer source has been triggered and is running

0= Timer source has not been triggered and is being held clear

OCTRIS: Output Compare Output Pin Direction Select bit

1= Output compare is tri-stated

0= Output compare module drives the OCx pin

Note 1: This option should only be selected as a trigger source and not as a synchronization source.

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REGISTER 14-2: OC1CON2: OUTPUT COMPARE CONTROL REGISTER 2 (CONTINUED)

bit 4-0

SYNCSEL<4:0>: Trigger/Synchronization Source Selection bits

11111 = OC1RS compare event is used for synchronization

11110 = INT2 pin synchronizes or triggers OC1

11101 = INT1 pin synchronizes or triggers OC1

11100 = Reserved

11011 = Reserved

11010 = Reserved

11001 = CMP2 module triggers OC1

11000 = CMP1 module triggers OC1

(1)

10111 = Reserved

10110 = Reserved

10101 = Reserved

10100 = Reserved

10011 = Reserved

10010 = Reserved

10001 = Reserved

10000 = IC1 input capture interrupt event synchronizes or triggers OC1

01111 = Reserved

01110 = Reserved

01101 = Timer3 synchronizes or triggers OC1

01100 = Timer2 synchronizes or triggers OC1 (default)

01011 = Timer1 synchronizes or triggers OC1

01010 = Reserved

01001 = Reserved

01000 = Reserved

00111 = Reserved

00110 = Reserved

00101 = IC1 input capture event synchronizes or triggers OC1

00100 = Reserved

00011 = Reserved

00010 = Reserved

00001 = Reserved

00000 = No sync or trigger source for OC1

Note 1: This option should only be selected as a trigger source and not as a synchronization source.

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NOTES:

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Figure 15-1 conceptualizes the PWM module in a

simplified block diagram. Figure 15-2 illustrates how

15.0 HIGH-SPEED PWM

Note:

This data sheet summarizes the features

of the dsPIC33EPXXGS202 family of

the module hardware is partitioned for each PWM

output pair for the Complementary PWM mode.

devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to “High-Speed PWM

Module” (DS70000323) in the “dsPIC33/

PIC24 Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

The PWM module contains three PWM generators.

The module has up to six PWM output pins: PWM1H/

PWM1L through PWM3H/PWM3L. For complementary

outputs, these six I/O pins are grouped into high/low

pairs.

15.2 Feature Description

The PWM module is designed for applications that

require:

The high-speed PWM module on dsPIC33EPXXGS202

devices supports a wide variety of PWM modes and

output formats. This PWM module is ideal for power

conversion applications, such as:

• High resolution at high PWM frequencies

• The ability to drive Standard, Edge-Aligned,

Center-Aligned Complementary and

Push-Pull mode outputs

• AC/DC Converters

• DC/DC Converters

• Power Factor Correction

• Uninterruptible Power Supply (UPS)

• Inverters

• The ability to create multiphase PWM outputs

Two common, medium power converter topologies are

push-pull and half-bridge. These designs require the

PWM output signal to be switched between alternate

pins, as provided by the Push-Pull PWM mode.

• Battery Chargers

• Digital Lighting

Phase-shifted PWM describes the situation where

each PWM generator provides outputs, but the

phase relationship between the generator outputs is

specifiable and changeable.

15.1 Features Overview

The high-speed PWM module incorporates the

following features:

Multiphase PWM is often used to improve DC/DC

Converter load transient response, and reduce the size

of output filter capacitors and inductors. Multiple DC/DC

Converters are often operated in parallel, but phase

shifted in time. A single PWM output operating at

250 kHz has a period of 4 s, but an array of four PWM

channels, staggered by 1 s each, yields an effective

switching frequency of 1 MHz. Multiphase PWM

applications typically use a fixed-phase relationship.

• Three PWM Generators with Two Outputs per

Generator

• Two Master Time Base Modules

• Individual Time Base and Duty Cycle for each

PWM Output

• Duty Cycle, Dead Time, Phase Shift and a

Frequency Resolution of 1.04 ns

• Independent Fault and Current-Limit Inputs

• Redundant Output

Variable phase PWM is useful in Zero Voltage

Transition (ZVT) power converters. Here, the PWM

duty cycle is always 50% and the power flow is

controlled by varying the relative phase shift between

the two PWM generators.

• True Independent Output

• Center-Aligned PWM mode

• Output Override Control

• Chop mode (also known as Gated mode)

• Special Event Trigger

• Dual Trigger from PWM to Analog-to-Digital

Converter (ADC)

• PWMxL and PWMxH Output Pin Swapping

• Independent PWMx Frequency, Duty Cycle and

Phase-Shift Changes

• Enhanced Leading-Edge Blanking (LEB) Functionality

• PWMx Capture Functionality

Note:

Duty cycle, dead time, phase shift and

frequency resolution is 8.32 ns in

Center-Aligned PWM mode.

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To gain write access to these locked registers, the user

application must write two consecutive values (0xABCD

and 0x4321) to the PWMKEY register to perform the

unlock operation. The write access to the IOCONx or

FCLCONx registers must be the next SFR access

following the unlock process. There can be no other SFR

accesses during the unlock process and subsequent

write access. To write to both the IOCONx and

FCLCONx registers requires two unlock operations.

15.2.1

WRITE-PROTECTED REGISTERS

On the dsPIC33EPXXGS202 family devices, write

protection is implemented for the IOCONx and

FCLCONx registers. The write protection feature

prevents any inadvertent writes to these registers. This

protection feature can be controlled by the PWMLOCK

Configuration bit (FDEVOPT<0>). The default state of

the write protection feature is enabled (PWMLOCK = 1).

The write protection feature can be disabled by

configuring PWMLOCK = 0.

The correct unlocking sequence is described in

Example 15-1.

EXAMPLE 15-1:

PWM WRITE-PROTECTED REGISTER UNLOCK SEQUENCE

; Writing to FCLCON1 register requires unlock sequence

mov #0xabcd, w10

mov #0x4321, w11

mov #0x0000, w0

mov w10, PWMKEY

mov w11, PWMKEY

mov w0, FCLCON1

; Load first unlock key to w10 register

; Load second unlock key to w11 register

; Load desired value of FCLCON1 register in w0

; Write first unlock key to PWMKEY register

; Write second unlock key to PWMKEY register

; Write desired value to FCLCON1 register

; Set PWM ownership and polarity using the IOCON1 register

; Writing to IOCON1 register requires unlock sequence

mov #0xabcd, w10

mov #0x4321, w11

mov #0xF000, w0

mov w10, PWMKEY

mov w11, PWMKEY

mov w0, IOCON1

; Load first unlock key to w10 register

; Load second unlock key to w11 register

; Load desired value of IOCON1 register in w0

; Write first unlock key to PWMKEY register

; Write second unlock key to PWMKEY register

; Write desired value to IOCON1 register

15.3.1

KEY RESOURCES

15.3 PWM Resources

•

“High-Speed PWM Module” (DS70000323) in

the “dsPIC33/PIC24 Family Reference Manual”

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

DS70005208E-page 150

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FIGURE 15-1:

HIGH-SPEED PWM MODULE ARCHITECTURAL DIAGRAM

SYNCIx

Data Bus

Primary and Secondary

Master Time Base

SYNCOx

Synchronization Signal

PWM1 Interrupt

PWM1H

PWM1L

PWM

Generator 1

Fault, Current-Limit

Synchronization Signal

PWM2 Interrupt

PWM2H

PWM2L

PWM

Generator 2

CPU

Fault, Current-Limit

Synchronization Signal

PWM3H

PWM3L

PWM3 Interrupt

PWM

Generator 3

Primary Trigger

Secondary Trigger

Special Event Trigger

Fault and

Current-Limit

ADC Module

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FIGURE 15-2:

SIMPLIFIED CONCEPTUAL BLOCK DIAGRAM OF THE HIGH-SPEED PWM

PTCON, PTCON2

STCON, STCON2

Module Control and Timing

SYNCI1

SYNCI2

PWMKEY

SYNCO1

PTPER

SEVTCMP

Comparator

Special Event Compare Trigger

Special Event

Comparator

Postscaler

Special Event Trigger

Master Time Base Counter

Clock

Prescaler

PMTMR

STPER

Primary Master Time Base

SYNCO2

SEVTCMP

Special Event Compare Trigger

Special Event

Postscaler

Comparator

Special Event Trigger

Master Time Base Counter

Clock

SMTMR

MDC

Prescaler

Secondary Master Time Base

Master Duty Cycle Register

PWM Generator 1

PDCx

MUX

PWM Output Mode

Comparator

Control Logic

PWMCAPx

ADC Trigger

User Override Logic

Control

Logic

Dead-Time

Logic

PTMRx

PWM1H

PWM1L

Current-Limit

Override Logic

Comparator

PHASEx

SDCx

Fault Override Logic

TRIGx

Secondary PWMx

MUX

Fault and

Current-Limit

Logic

Interrupt

Logic

Comparator

FLTx

ADC Trigger

Comparator

STMRx

SPHASEx

STRIGx

FCLCONx

LEBCONx

IOCONx

ALTDTRx

DTRx

PWMCONx

AUXCONx

TRGCONx

PWMxH

PWMxL

FLTx

PWM Generator 2 – PWM Generator 3

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REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER

R/W-0

PTEN

U-0

—

R/W-0

HS/HC-0

SESTAT

R/W-0

SEIEN

R/W-0

(1)

PTSIDL

EIPU

SYNCPOL SYNCOEN

bit 8

bit 15

R/W-0

SYNCEN

bit 7

R/W-0

(1)

SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3

SEVTPS2

SEVTPS1

SEVTPS0

bit 0

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PTEN: PWM Module Enable bit

1= PWM module is enabled

0= PWM module is disabled

bit 14

bit 13

Unimplemented: Read as ‘0’

PTSIDL: PWM Time Base Stop in Idle Mode bit

1= PWM time base halts in CPU Idle mode

0= PWM time base runs in CPU Idle mode

bit 12

bit 11

bit 10

bit 9

SESTAT: Special Event Interrupt Status bit

1= Special event interrupt is pending

0= Special event interrupt is not pending

SEIEN: Special Event Interrupt Enable bit

1= Special event interrupt is enabled

0= Special event interrupt is disabled

(1)

EIPU: Enable Immediate Period Updates bit

1= Active Period register is updated immediately

0= Active Period register updates occur on PWM cycle boundaries

(1)

SYNCPOL: Synchronize Input and Output Polarity bit

1= SYNCIx/SYNCO1 polarity is inverted (active-low)

0= SYNCIx/SYNCO1 is active-high

(1)

bit 8

SYNCOEN: Primary Time Base Synchronization Enable bit

1= SYNCO1 output is enabled

0= SYNCO1 output is disabled

(1)

bit 7

SYNCEN: External Time Base Synchronization Enable bit

1= External synchronization of primary time base is enabled

0= External synchronization of primary time base is disabled

(1)

bit 6-4

SYNCSRC<2:0>: Synchronous Source Selection bits

111= Reserved

101= Reserved

100= Reserved

011= Reserved

010= Reserved

001= SYNCI2

000= SYNCI1

Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user

application must program the Period register with a value that is slightly larger than the expected period of

the external synchronization input signal.

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REGISTER 15-1: PTCON: PWM TIME BASE CONTROL REGISTER (CONTINUED)

(1)

bit 3-0

SEVTPS<3:0>: PWM Special Event Trigger Output Postscaler Select bits

1111= 1:16 Postscaler generates a Special Event Trigger on every sixteenth compare match event

•

0001= 1:2 Postscaler generates a Special Event Trigger on every second compare match event

0000= 1:1 Postscaler generates a Special Event Trigger on every compare match event

Note 1: These bits should be changed only when PTEN = 0. In addition, when using the SYNCIx feature, the user

application must program the Period register with a value that is slightly larger than the expected period of

the external synchronization input signal.

REGISTER 15-2: PTCON2: PWM CLOCK DIVIDER SELECT REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(1)

PCLKDIV<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

(1)

PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits

111= Reserved

110= Divide-by-64, maximum PWM timing resolution

101= Divide-by-32, maximum PWM timing resolution

100= Divide-by-16, maximum PWM timing resolution

011= Divide-by-8, maximum PWM timing resolution

010= Divide-by-4, maximum PWM timing resolution

001= Divide-by-2, maximum PWM timing resolution

000= Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

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REGISTER 15-3: PTPER: PWM PRIMARY MASTER TIME BASE PERIOD REGISTER^(1,2)

R/W-1

bit 15

R/W-1

bit 7

R/W-1

bit 8

R/W-0

bit 0

PTPER<15:8>

R/W-1

R/W-0

PTPER<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PTPER<15:0>: Primary Master Time Base (PMTMR) Period Value bits

Note 1: The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.

2: Any period value that is less than 0x0028 must have the Least Significant 3 bits set to ‘0’, thus yielding a

period resolution at 8.32 ns (at fastest auxiliary clock rate).

REGISTER 15-4: SEVTCMP: PWM SPECIAL EVENT COMPARE REGISTER⁽¹⁾

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

SEVTCMP<12:5>

R/W-0

U-0

—

U-0

—

U-0

—

SEVTCMP<4:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

SEVTCMP<12:0>: Special Event Compare Count Value bits

Unimplemented: Read as ‘0’

Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.

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REGISTER 15-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER

U-0

—

U-0

—

U-0

—

HS/HC-0

SESTAT

R/W-0

SEIEN

R/W-0

(1)

EIPU

SYNCPOL SYNCOEN

bit 8

bit 15

R/W-0

SYNCEN

SYNCSRC2 SYNCSRC1 SYNCSRC0 SEVTPS3

SEVTPS2

SEVTPS1

SEVTPS0

bit 7

bit 0

Legend:

HS = Hardware Settable bit HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

SESTAT: Special Event Interrupt Status bit

1= Secondary special event interrupt is pending

0= Secondary special event interrupt is not pending

bit 11

bit 10

bit 9

SEIEN: Special Event Interrupt Enable bit

1= Secondary special event interrupt is enabled

0= Secondary special event interrupt is disabled

(1)

EIPU: Enable Immediate Period Updates bit

1= Active Secondary Period register is updated immediately

0= Active Secondary Period register updates occur on PWM cycle boundaries

SYNCPOL: Synchronize Input and Output Polarity bit

1= SYNCIx/SYNCO2 polarity is inverted (active-low)

0= SYNCIx/SYNCO2 polarity is active-high

bit 8

SYNCOEN: Secondary Master Time Base Synchronization Enable bit

1= SYNCO2 output is enabled.

0= SYNCO2 output is disabled

bit 7

SYNCEN: External Secondary Master Time Base Synchronization Enable bit

1= External synchronization of secondary time base is enabled

0= External synchronization of secondary time base is disabled

bit 6-4

SYNCSRC<2:0>: Secondary Time Base Sync Source Selection bits

111= Reserved

101= Reserved

100= Reserved

011= Reserved

010= Reserved

001= SYNCI2

000= SYNCI1

bit 3-0

SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits

1111= 1:16 Postscale

0001= 1:2 Postscale

0000= 1:1 Postscale

Note 1: This bit only applies to the secondary master time base period.

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REGISTER 15-6: STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER 2

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

(1)

PCLKDIV<2:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

Unimplemented: Read as ‘0’

(1)

PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits

111= Reserved

110= Divide-by-64, maximum PWM timing resolution

101= Divide-by-32, maximum PWM timing resolution

100= Divide-by-16, maximum PWM timing resolution

011= Divide-by-8, maximum PWM timing resolution

010= Divide-by-4, maximum PWM timing resolution

001= Divide-by-2, maximum PWM timing resolution

000= Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

REGISTER 15-7: STPER: PWM SECONDARY MASTER TIME BASE PERIOD REGISTER^(1,2)

R/W-1

bit 15

R/W-1

bit 7

R/W-1

bit 8

R/W-1

bit 0

STPER<15:8>

R/W-1

STPER<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits

Note 1: The PWM time base has a minimum value of 0x0010 and a maximum value of 0xFFF8.

2: Any period value that is less than 0x0028 must have the Least Significant three bits set to ‘0’, thus yielding

a period resolution at 8.32 ns (at fastest auxiliary clock rate).

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REGISTER 15-8: SSEVTCMP: PWM SECONDARY SPECIAL EVENT COMPARE REGISTER⁽¹⁾

R/W-0

bit 15

R/W-0

bit 7

R/W-0

SSEVTCMP<12:5>

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

SSEVTCMP<4:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

SSEVTCMP<12:0>: Special Event Compare Count Value bits

Unimplemented: Read as ‘0’

Note 1: One LSB = 1.04 ns (at fastest auxiliary clock rate); therefore, the minimum SEVTCMP resolution is 8.32 ns.

REGISTER 15-9: CHOP: PWM CHOP CLOCK GENERATOR REGISTER⁽¹⁾

R/W-0

CHPCLKEN

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

CHOPCLK6 CHOPCLK5

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

CHOPCLK4 CHOPCLK3 CHOPCLK2 CHOPCLK1 CHOPCLK0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CHPCLKEN: Enable Chop Clock Generator bit

1= Chop clock generator is enabled

0= Chop clock generator is disabled

bit 14-10

bit 9-3

Unimplemented: Read as ‘0’

CHOPCLK<6:0>: Chop Clock Divider bits

Value is in 8.32 ns increments. The frequency of the chop clock signal is given by the following

expression:

Chop Frequency = 1/(16.64 * (CHOPCLK<6:0> + 1) * Primary Master PWM Input Clock Period)

bit 2-0

Unimplemented: Read as ‘0’

Note 1: The chop clock generator operates with the primary PWM clock prescaler (PCLKDIV<2:0>) in the

PTCON2 register (Register 15-2).

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REGISTER 15-10: MDC: PWM MASTER DUTY CYCLE REGISTER^(1,2)

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

MDC<15:8>

R/W-0

MDC<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

MDC<15:0>: Master PWM Duty Cycle Value bits

Note 1: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of Period – 0x0008.

2: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of

operation), PWM duty cycle resolution will increase from one to three LSBs.

REGISTER 15-11: PWMKEY: PWM PROTECTION LOCK/UNLOCK KEY REGISTER

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

PWMKEY<15:8>

R/W-0

PWMKEY<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PWMKEY<15:0>: PWM Protection Lock/Unlock Key Value bits

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REGISTER 15-12: PWMCONx: PWMx CONTROL REGISTER

HS/HC-0

R/W-0

CLIEN

R/W-0

(1)

(3)

FLTSTAT

bit 15

CLSTAT

TRGSTAT

FLTIEN

TRGIEN

ITB

MDCS

bit 8

R/W-0

DTC1

bit 7

R/W-0

DTC0

U-0

—

U-0

—

R/W-0

MTBS

R/W-0

IUE

(2,3,4)

(5)

CAM

XPRES

bit 0

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1)

bit 15

bit 14

bit 13

FLTSTAT: Fault Interrupt Status bit

1= Fault interrupt is pending

0= No Fault interrupt is pending

This bit is cleared by setting FLTIEN = 0.

(1)

CLSTAT: Current-Limit Interrupt Status bit

1= Current-limit interrupt is pending

0= No current-limit interrupt is pending

This bit is cleared by setting CLIEN = 0.

TRGSTAT: Trigger Interrupt Status bit

1= Trigger interrupt is pending

0= No trigger interrupt is pending

This bit is cleared by setting TRGIEN = 0.

bit 12

bit 11

bit 10

bit 9

FLTIEN: Fault Interrupt Enable bit

1= Fault interrupt is enabled

0= Fault interrupt is disabled and the FLTSTAT bit is cleared

CLIEN: Current-Limit Interrupt Enable bit

1= Current-limit interrupt is enabled

0= Current-limit interrupt is disabled and the CLSTAT bit is cleared

TRGIEN: Trigger Interrupt Enable bit

1= A trigger event generates an interrupt request

0= Trigger event interrupts are disabled and the TRGSTAT bit is cleared

(3)

ITB: Independent Time Base Mode bit

1= PHASEx/SPHASEx registers provide the time base period for this PWMx generator

0= PTPER register provides timing for this PWMx generator

(3)

bit 8

MDCS: Master Duty Cycle Register Select bit

1= MDC register provides duty cycle information for this PWMx generator

0= PDCx and SDCx registers provide duty cycle information for this PWMx generator

Note 1: Software must clear the interrupt status here and in the corresponding IFSx register in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.

4: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time

registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to

the fastest clock.

5: Configure CLMOD (FCLCONx<8>) = 0and ITB (PWMCONx<9>) = 1to operate in External Period Reset

mode.

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REGISTER 15-12: PWMCONx: PWMx CONTROL REGISTER (CONTINUED)

bit 7-6

DTC<1:0>: Dead-Time Control bits

11= Reserved

10= Dead-time function is disabled

01= Negative dead time is actively applied for Complementary Output mode

00= Positive dead time is actively applied for all Output modes

bit 5-4

bit 3

Unimplemented: Read as ‘0’

MTBS: Master Time Base Select bit

1= PWMx generator uses the secondary master time base for synchronization and the clock source for

the PWMx generation logic (if secondary time base is available)

0= PWMx generator uses the primary master time base for synchronization and the clock source for

the PWMx generation logic

(2,3,4)

bit 2

bit 1

bit 0

CAM: Center-Aligned Mode Enable bit

1= Center-Aligned mode is enabled

0= Edge-Aligned mode is enabled

(5)

XPRES: External PWMx Reset Control bit

1= Current-limit source resets the time base for this PWMx generator if it is in Independent Time Base mode

0= External pins do not affect the PWMx time base

IUE: Immediate Update Enable bit

1= Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers

are immediate

0= Updates to the active Duty Cycle, Phase Offset, Dead-Time and local Time Base Period registers

are synchronized to the local PWMx time base

Note 1: Software must clear the interrupt status here and in the corresponding IFSx register in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.

4: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time

registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to

the fastest clock.

5: Configure CLMOD (FCLCONx<8>) = 0and ITB (PWMCONx<9>) = 1to operate in External Period Reset

mode.

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REGISTER 15-13: PDCx: PWMx GENERATOR DUTY CYCLE REGISTER^(1,2,3)

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

PDCx<15:8>

R/W-0

PDCx<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PDCx<15:0>: PWMx Generator Duty Cycle Value bits

Note 1: In Independent PWM mode, the PDCx register controls the PWMxH duty cycle only. In the

Complementary, Redundant and Push-Pull PWM modes, the PDCx register controls the duty cycle of both

the PWMxH and PWMxL.

2: The smallest pulse width that can be generated on the PWMx output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of Period – 0x0008.

3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of

operation), PWM duty cycle resolution will increase from one to three LSBs.

REGISTER 15-14: SDCx: PWMx SECONDARY DUTY CYCLE REGISTER^(1,2,3)

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

SDCx<15:8>

R/W-0

SDCx<7:0>

R/W-0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

SDCx<15:0>: Secondary Duty Cycle for PWMxL Output Pin bits

Note 1: The SDCx register is used in Independent PWM mode only. When used in Independent PWM mode, the

SDCx register controls the PWMxL duty cycle.

2: The smallest pulse width that can be generated on the PWM output corresponds to a value of 0x0008,

while the maximum pulse width generated corresponds to a value of Period – 0x0008.

3: As the duty cycle gets closer to 0% or 100% of the PWM period (0 to 40 ns, depending on the mode of

operation), PWM duty cycle resolution will increase from one to three LSBs.

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REGISTER 15-15: PHASEx: PWMx PRIMARY PHASE-SHIFT REGISTER^(1,2)

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

PHASEx<15:8>

R/W-0

PHASEx<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

PHASEx<15:0>: PWMx Phase-Shift Value or Independent Time Base Period for the PWMx Generator bits

Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);

PHASEx<15:0> = Phase-shift value for PWMxH and PWMxL outputs

• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Phase-shift value for

PWMxH only

• When the PHASEx/SPHASEx registers provide the phase shift with respect to the master time base;

therefore, the valid range is 0x0000 through period

2: If PWMCONx<9> = 1, the following applies based on the mode of operation:

• Complementary, Redundant, and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);

PHASEx<15:0> = Independent time base period value for PWMxH and PWMxL

• True Independent Output mode (IOCONx<11:10> = 11); PHASEx<15:0> = Independent time base

period value for PWMxH only

• When the PHASEx/SPHASEx registers provide the local period, the valid range is 0x0000 through

0xFFF8

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REGISTER 15-16: SPHASEx: PWMx SECONDARY PHASE-SHIFT REGISTER^(1,2)

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

R/W-0

bit 0

SPHASEx<15:8>

R/W-0

SPHASEx<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-0

SPHASEx<15:0>: Secondary Phase Offset for PWMxL Output Pin bits

(used in Independent PWM mode only)

Note 1: If PWMCONx<9> = 0, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);

SPHASEx<15:0> = Not used

• True Independent Output mode (IOCONx<11:10> = 11), SPHASEx<15:0> = Phase-shift value for

PWMxL only

2: If PWMCONx<9> = 1, the following applies based on the mode of operation:

• Complementary, Redundant and Push-Pull Output mode (IOCONx<11:10> = 00, 01or 10);

SPHASEx<15:0> = Not used

• True Independent Output mode (IOCONx<11:10> = 11); SPHASEx<15:0> = Independent time base

period value for PWMxL only

• When the PHASEx/SPHASEx registers provide the local period, the valid range of values is

0x0010-0xFFF8

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REGISTER 15-17: DTRx: PWMx DEAD-TIME REGISTER

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

DTRx<13:8>

bit 15

R/W-0

bit 7

R/W-0

DTRx<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-0

Unimplemented: Read as ‘0’

DTRx<13:0>: Unsigned 14-Bit Dead-Time Value for PWMx Dead-Time Unit bits

REGISTER 15-18: ALTDTRx: PWMx ALTERNATE DEAD-TIME REGISTER

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

ALTDTRx<13:8>

bit 15

R/W-0

bit 7

R/W-0

ALTDTRx<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-0

Unimplemented: Read as ‘0’

ALTDTRx<13:0>: Unsigned 14-Bit Alternate Dead-Time Value for PWMx Dead-Time Unit bits

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REGISTER 15-19: TRGCONx: PWMx TRIGGER CONTROL REGISTER

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

TRGDIV3

TRGDIV2

TRGDIV1

TRGDIV0

bit 15

bit 8

R/W-0

U-0

—

R/W-0

(1)

DTM

TRGSTRT5 TRGSTRT4 TRGSTRT3 TRGSTRT2 TRGSTRT1 TRGSTRT0

bit 0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-12

TRGDIV<3:0>: Trigger # Output Divider bits

1111= Trigger output for every 16th trigger event

1110= Trigger output for every 15th trigger event

1101= Trigger output for every 14th trigger event

1100= Trigger output for every 13th trigger event

1011= Trigger output for every 12th trigger event

1010= Trigger output for every 11th trigger event

1001= Trigger output for every 10th trigger event

1000= Trigger output for every 9th trigger event

0111= Trigger output for every 8th trigger event

0110= Trigger output for every 7th trigger event

0101= Trigger output for every 6th trigger event

0100= Trigger output for every 5th trigger event

0011= Trigger output for every 4th trigger event

0010= Trigger output for every 3rd trigger event

0001= Trigger output for every 2nd trigger event

0000= Trigger output for every trigger event

bit 11-8

bit 7

Unimplemented: Read as ‘0’

(1)

DTM: Dual Trigger Mode bit

1= Secondary trigger event is combined with the primary trigger event to create a PWM trigger

0= Secondary trigger event is not combined with the primary trigger event to create a PWM trigger;

two separate PWM triggers are generated

bit 6

Unimplemented: Read as ‘0’

bit 5-0

TRGSTRT<5:0>: Trigger Postscaler Start Enable Select bits

111111= Wait 63 PWM cycles before generating the first trigger event after the module is enabled

•

000010= Wait 2 PWM cycles before generating the first trigger event after the module is enabled

000001= Wait 1 PWM cycle before generating the first trigger event after the module is enabled

000000= Wait 0 PWM cycles before generating the first trigger event after the module is enabled

Note 1: The secondary PWMx generator cannot generate PWM trigger interrupts.

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REGISTER 15-20: IOCONx: PWMx I/O CONTROL REGISTER

R/W-1

PENH

R/W-1

PENL

R/W-0

POLH

R/W-0

POLL

R/W-0

(1)

PMOD1

PMOD0

OVRENH

OVRENL

bit 15

bit 8

R/W-0

SWAP

R/W-0

(2)

OVRDAT1

OVRDAT0

FLTDAT1

FLTDAT0

CLDAT1

CLDAT0

OSYNC

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

PENH: PWMxH Output Pin Ownership bit

1= PWM module controls the PWMxH pin

0= GPIO module controls the PWMxH pin

bit 14

PENL: PWMxL Output Pin Ownership bit

1= PWM module controls the PWMxL pin

0= GPIO module controls the PWMxL pin

bit 13

POLH: PWMxH Output Pin Polarity bit

1= PWMxH pin is active-low

0= PWMxH pin is active-high

bit 12

POLL: PWMxL Output Pin Polarity bit

1= PWMxL pin is active-low

0= PWMxL pin is active-high

(1)

bit 11-10

PMOD<1:0>: PWMx I/O Pin Mode bits

11= PWMx I/O pin pair is in the True Independent Output mode

10= PWMx I/O pin pair is in the Push-Pull Output mode

01= PWMx I/O pin pair is in the Redundant Output mode

00= PWMx I/O pin pair is in the Complementary Output mode

bit 9

OVRENH: Override Enable for PWMxH Pin bit

1= OVRDAT1 provides data for output on the PWMxH pin

0= PWMx generator provides data for the PWMxH pin

bit 8

OVRENL: Override Enable for PWMxL Pin bit

1= OVRDAT0 provides data for output on the PWMxL pin

0= PWMx generator provides data for the PWMxL pin

bit 7-6

bit 5-4

OVRDAT<1:0>: Data for PWMxH, PWMxL Pins if Override is Enabled bits

If OVERENH = 1, OVRDAT1 provides the data for the PWMxH pin.

If OVERENL = 1, OVRDAT0 provides the data for the PWMxL pin.

(2)

FLTDAT<1:0>: State for PWMxH and PWMxL Pins if FLTMOD<1:0> are Enabled bits

IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:

If Fault is active, then FLTDAT1 provides the state for the PWMxH pin.

If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.

IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:

If current-limit is active, then FLTDAT1 provides the state for the PWMxH pin.

If Fault is active, then FLTDAT0 provides the state for the PWMxL pin.

Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).

2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.

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REGISTER 15-20: IOCONx: PWMx I/O CONTROL REGISTER (CONTINUED)

(2)

bit 3-2

CLDAT<1:0>: State for PWMxH and PWMxL Pins if CLMOD is Enabled bits

IFLTMOD (FCLCONx<15>) = 0: Normal Fault mode:

If current-limit is active, then CLDAT1 provides the state for the PWMxH pin.

If current-limit is active, then CLDAT0 provides the state for the PWMxL pin.

IFLTMOD (FCLCONx<15>) = 1: Independent Fault mode:

CLDAT<1:0> bits are ignored.

bit 1

bit 0

SWAP: SWAP PWMxH and PWMxL Pins bit

1= PWMxH output signal is connected to the PWMxL pins; PWMxL output signal is connected to the

PWMxH pins

0= PWMxH and PWMxL pins are mapped to their respective pins

OSYNC: Output Override Synchronization bit

1= Output overrides via the OVRDAT<1:0> bits are synchronized to the PWMx time base

0= Output overrides via the OVDDAT<1:0> bits occur on the next CPU clock boundary

Note 1: These bits should not be changed after the PWM module is enabled (PTEN = 1).

2: State represents the active/inactive state of the PWMx depending on the POLH and POLL bits settings.

REGISTER 15-21: TRIGx: PWMx PRIMARY TRIGGER COMPARE VALUE REGISTER

R/W-0

bit 15

R/W-0

bit 7

R/W-0

bit 8

TRGCMP<12:5>

R/W-0

U-0

—

U-0

—

U-0

—

TRGCMP<4:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

bit 2-0

TRGCMP<12:0>: Trigger Compare Value bits

When the primary PWM functions in the local time base, this register contains the compare values

that can trigger the ADC module.

Unimplemented: Read as ‘0’

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REGISTER 15-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER

R/W-0

(1)

IFLTMOD

CLSRC4

CLSRC3

CLSRC2

CLSRC1

CLSRC0

CLPOL

CLMOD

bit 15

bit 8

R/W-1

R/W-0

(1)

FLTSRC4

FLTSRC3

FLTSRC2

FLTSRC1

FLTSRC0

FLTPOL

FLTMOD1

FLTMOD0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

IFLTMOD: Independent Fault Mode Enable bit

1= Independent Fault mode: Current-limit input maps FLTDAT1 to the PWMxH output and the Fault input

maps FLTDAT0 to the PWMxL output. The CLDAT<1:0> bits are not used for override functions.

0= Normal Fault mode: Current-Limit mode maps the CLDAT<1:0> bits to the PWMxH and PWMxL

outputs. The PWM Fault mode maps FLTDAT<1:0> to the PWMxH and PWMxL outputs.

bit 14-10

CLSRC<4:0>: Current-Limit Control Signal Source Select for PWMx Generator bits

11111= Fault 31

10001= Reserved

10000= Reserved

01111= Reserved

01110= Analog Comparator 2

01101= Analog Comparator 1

01100= Reserved

01011= Reserved

01010= Reserved

01001= Reserved

01000= Fault 8

00111= Fault 7

00110= Fault 6

00101= Fault 5

00100= Fault 4

00011= Fault 3

00010= Fault 2

00001= Fault 1

00000= Reserved

(1)

bit 9

bit 8

CLPOL: Current-Limit Polarity for PWMx Generator # bit

1= The selected current-limit source is active-low

0= The selected current-limit source is active-high

CLMOD: Current-Limit Mode Enable for PWMx Generator # bit

1= Current-Limit mode is enabled

0= Current-Limit mode is disabled

Note 1: These bits should be changed only when PTEN (PTCON<15>) = 0.

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REGISTER 15-22: FCLCONx: PWMx FAULT CURRENT-LIMIT CONTROL REGISTER (CONTINUED)

bit 7-3

FLTSRC<4:0>: Fault Control Signal Source Select for PWMx Generator # bits

11111= Fault 31 (Default)

10001= Reserved

10000= Reserved

01111= Reserved

01110= Analog Comparator 2

01101= Analog Comparator 1

01100= Reserved

01011= Reserved

01010= Reserved

01001= Reserved

01000= Fault 8

00111= Fault 7

00110= Fault 6

00101= Fault 5

00100= Fault 4

00011= Fault 3

00010= Fault 2

00001= Fault 1

00000= Reserved

(1)

bit 2

FLTPOL: Fault Polarity for PWMx Generator # bit

1= The selected Fault source is active-low

0= The selected Fault source is active-high

bit 1-0

FLTMOD<1:0>: Fault Mode for PWMx Generator # bits

11= Fault input is disabled

10= Reserved

01= The selected Fault source forces the PWMxH, PWMxL pins to the FLTDATx values (cycle)

00= The selected Fault source forces the PWMxH, PWMxL pins to the FLTDATx values (latched condition)

Note 1: These bits should be changed only when PTEN (PTCON<15>) = 0.

REGISTER 15-23: STRIGx: PWMx SECONDARY TRIGGER COMPARE VALUE REGISTER⁽¹⁾

R/W-0

bit 15

R/W-0

bit 7

R/W-0

STRGCMP<12:5>

bit 8

R/W-0

U-0

—

U-0

—

U-0

—

STRGCMP<4:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-3

STRGCMP<12:0>: Secondary Trigger Compare Value bits

When the secondary PWMx functions in the local time base, this register contains the compare values

that can trigger the ADC module.

bit 2-0

Unimplemented: Read as ‘0’

Note 1: STRIGx cannot generate the PWMx trigger interrupts.

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REGISTER 15-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL

REGISTER

R/W-0

PHR

R/W-0

PLR

R/W-0

PLF

R/W-0

U-0

—

U-0

—

PHF

FLTLEBEN

CLLEBEN

bit 15

bit 8

U-0

—

U-0

—

R/W-0

BPHH

R/W-0

BPHL

R/W-0

BPLH

R/W-0

BPLL

(1)

BCH

BCL

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

bit 12

bit 11

bit 10

PHR: PWMxH Rising Edge Trigger Enable bit

1= Rising edge of PWMxH will trigger the Leading-Edge Blanking counter

0= Leading-Edge Blanking ignores the rising edge of PWMxH

PHF: PWMxH Falling Edge Trigger Enable bit

1= Falling edge of PWMxH will trigger the Leading-Edge Blanking counter

0= Leading-Edge Blanking ignores the falling edge of PWMxH

PLR: PWMxL Rising Edge Trigger Enable bit

1= Rising edge of PWMxL will trigger the Leading-Edge Blanking counter

0= Leading-Edge Blanking ignores the rising edge of PWMxL

PLF: PWMxL Falling Edge Trigger Enable bit

1= Falling edge of PWMxL will trigger the Leading-Edge Blanking counter

0= Leading-Edge Blanking ignores the falling edge of PWMxL

FLTLEBEN: Fault Input Leading-Edge Blanking Enable bit

1= Leading-Edge Blanking is applied to the selected Fault input

0= Leading-Edge Blanking is not applied to the selected Fault input

CLLEBEN: Current-Limit Leading-Edge Blanking Enable bit

1= Leading-Edge Blanking is applied to the selected current-limit input

0= Leading-Edge Blanking is not applied to the selected current-limit input

bit 9-6

bit 5

Unimplemented: Read as ‘0’

(1)

BCH: Blanking in Selected Blanking Signal High Enable bit

1= State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is high

0= No blanking when the selected blanking signal is high

(1)

bit 4

bit 3

bit 2

BCL: Blanking in Selected Blanking Signal Low Enable bit

1= State blanking (of current-limit and/or Fault input signals) when the selected blanking signal is low

0= No blanking when the selected blanking signal is low

BPHH: Blanking in PWMxH High Enable bit

1= State blanking (of current-limit and/or Fault input signals) when the PWMxH output is high

0= No blanking when the PWMxH output is high

BPHL: Blanking in PWMxH Low Enable bit

1= State blanking (of current-limit and/or Fault input signals) when the PWMxH output is low

0= No blanking when the PWMxH output is low

Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.

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REGISTER 15-24: LEBCONx: PWMx LEADING-EDGE BLANKING (LEB) CONTROL

REGISTER (CONTINUED)

bit 1

bit 0

BPLH: Blanking in PWMxL High Enable bit

1= State blanking (of current-limit and/or Fault input signals) when the PWMxL output is high

0= No blanking when the PWMxL output is high

BPLL: Blanking in PWMxL Low Enable bit

1= State blanking (of current-limit and/or Fault input signals) when the PWMxL output is low

0= No blanking when the PWMxL output is low

Note 1: The blanking signal is selected via the BLANKSEL<3:0> bits in the AUXCONx register.

REGISTER 15-25: LEBDLYx: PWMx LEADING-EDGE BLANKING DELAY REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

LEB<8:5>

bit 15

R/W-0

bit 7

R/W-0

U-0

—

U-0

—

U-0

—

LEB<4:0>

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-3

Unimplemented: Read as ‘0’

LEB<8:0>: Leading-Edge Blanking Delay for Current-Limit and Fault Inputs bits

The value is in 8.32 ns increments.

bit 2-0

Unimplemented: Read as ‘0’

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REGISTER 15-26: AUXCONx: PWMx AUXILIARY CONTROL REGISTER

R/W-0

U-0

—

U-0

—

R/W-0

HRPDIS

HRDDIS

BLANKSEL3 BLANKSEL2 BLANKSEL1 BLANKSEL0

bit 8

bit 15

U-0

—

U-0

—

R/W-0

CHOPLEN

bit 0

CHOPSEL3 CHOPSEL2 CHOPSEL1 CHOPSEL0

CHOPHEN

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

HRPDIS: High-Resolution PWMx Period Disable bit

1= High-resolution PWMx period is disabled to reduce power consumption

0= High-resolution PWMx period is enabled

HRDDIS: High-Resolution PWMx Duty Cycle Disable bit

1= High-resolution PWMx duty cycle is disabled to reduce power consumption

0= High-resolution PWMx duty cycle is enabled

bit 13-12

bit 11-8

Unimplemented: Read as ‘0’

BLANKSEL<3:0>: PWMx State Blank Source Select bits

The selected state blank signal will block the current-limit and/or Fault input signals

(if enabled via the BCH and BCL bits in the LEBCONx register).

1001= Reserved

1000= Reserved

0111= Reserved

0110= Reserved

0101= Reserved

0100= Reserved

0011= PWM3H is selected as the state blank source

0010= PWM2H is selected as the state blank source

0001= PWM1H is selected as the state blank source

0000= No state blanking

bit 7-6

bit 5-2

Unimplemented: Read as ‘0’

CHOPSEL<3:0>: PWMx Chop Clock Source Select bits

The selected signal will enable and disable (chop) the selected PWMx outputs.

1001= Reserved

1000= Reserved

0111= Reserved

0110= Reserved

0101= Reserved

0100= Reserved

0011= PWM3H is selected as the chop clock source

0010= PWM2H is selected as the chop clock source

0001= PWM1H is selected as the chop clock source

0000= Chop clock generator is selected as the chop clock source

bit 1

bit 0

CHOPHEN: PWMxH Output Chopping Enable bit

1= PWMxH chopping function is enabled

0= PWMxH chopping function is disabled

CHOPLEN: PWMxL Output Chopping Enable bit

1= PWMxL chopping function is enabled

0= PWMxL chopping function is disabled

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REGISTER 15-27: PWMCAPx: PWMx PRIMARY TIME BASE CAPTURE REGISTER

R-0

bit 15

R-0

(1,2,3,4)

R-0

PWMCAP<12:5>

bit 8

bit 0

R-0

U-0

—

U-0

—

U-0

—

(1,2,3,4)

PWMCAP<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

(1,2,3,4)

bit 15-3

PWMCAP<12:0>: Captured PWMx Time Base Value bits

The value in this register represents the captured PWMx time base value when a leading edge is

detected on the current-limit input.

bit 2-0

Unimplemented: Read as ‘0’

Note 1: The capture feature is only available on a primary output (PWMxH).

2: This feature is active only after LEB processing on the current-limit input signal is complete.

3: The minimum capture resolution is 8.32 ns.

4: This feature can be used when the XPRES bit (PWMCONx<1>) is set to ‘0’.

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The dsPIC33EPXXGS202 device family offers one SPI

module on a single device.

16.0 SERIAL PERIPHERAL

INTERFACE (SPI)

The SPI1 module takes advantage of the Peripheral

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Serial Peripheral

Interface (SPI)” (DS70005185) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

web site (www.microchip.com).

Pin Select (PPS) feature to allow for greater flexibility in

pin configuration.

The SPI1 serial interface consists of four pins, as follows:

• SDI1: Serial Data Input

• SDO1: Serial Data Output

• SCK1: Shift Clock Input or Output

• SS1/FSYNC1: Active-Low Slave Select or Frame

Synchronization I/O Pulse

The SPI1 module can be configured to operate with

two, three or four pins. In 3-Pin mode, SS1 is not used.

In 2-Pin mode, neither SDO1 nor SS1 is used.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

Figure 16-1 illustrates the block diagram of the SPI1

module in Standard and Enhanced modes.

The SPI module is a synchronous serial interface,

useful for communicating with other peripherals or

microcontroller devices. These peripheral devices can

be serial EEPROMs, shift registers, display drivers,

ADC Converters, etc. The SPI module is compatible

with Motorola^®SPI and SIOP interfaces.

FIGURE 16-1:

SPI1 MODULE BLOCK DIAGRAM

SCK1

1:1/4/16/64

Primary

Prescaler

1:1 to 1:8

Secondary

Prescaler

F

P

SS1/FSYNC1

Sync

Control

Clock

Select

Edge

SPI1CON1<1:0>

SPI1CON1<4:2>

Shift Control

SDO1

SDI1

Enable

Master Clock

bit 0

SPI1SR

Transfer

8-Level FIFO

Receive Buffer⁽¹⁾Transmit Buffer⁽¹⁾

SPI1BUF

Read SPI1BUF

Write SPI1BUF

16

Internal Data Bus

Note 1: In Standard mode, the FIFO is only one-level deep.

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16.1 SPI Helpful Tips

16.2 SPI Resources

1. In Frame mode, if there is a possibility that the

master may not be initialized before the slave:

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

a) If FRMPOL (SPI1CON2<13>) = 1, use a

pull-down resistor on SS1.

b) If FRMPOL = 0, use a pull-up resistor on

16.2.1

KEY RESOURCES

SS1.

•

“Serial Peripheral Interface (SPI)”

(DS70005185) in the “dsPIC33/PIC24 Family

Reference Manual”

Note:

This ensures that the first frame

transmission after initialization is not

shifted or corrupted.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

2. In Non-Framed 3-Wire mode (i.e., not using SS1

from a master):

a) If CKP (SPI1CON1<6>) = 1, always place a

pull-up resistor on SS1.

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

b) If CKP = 0, always place a pull-down

resistor on SS1.

• Development Tools

Note:

This will ensure that during power-up and

initialization, the master/slave will not lose

synchronization due to an errant SCK1

transition that would cause the slave to

accumulate data shift errors for both

transmit and receive, appearing as

corrupted data.

3. FRMEN (SPI1CON2<15>) = 1 and SSEN

(SPI1CON1<7>) = 1are exclusive and invalid.

In Frame mode, SCK1 is continuous and the

frame sync pulse is active on the SS1 pin, which

indicates the start of a data frame.

Note:

Not all third-party devices support Frame

mode timing. Refer to the SPI1

specifications in Section 25.0 “Electrical

Characteristics” for details.

4. In Master mode only, set the SMP bit

(SPI1CON1<9>) to a ‘1’ for the fastest SPI1

data rate possible. The SMP bit can only be set

at the same time or after the MSTEN bit

(SPI1CON1<5>) is set.

To avoid invalid slave read data to the master, the

user’s master software must ensure enough time for

slave software to fill its write buffer before the user

application initiates a master write/read cycle. It is

always advisable to preload the SPI1BUF Transmit

register in advance of the next master transaction

cycle. SPI1BUF is transferred to the SPI1 Shift register

and is empty once the data transmission begins.

DS70005208E-page 176

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16.3 SPI Control and Status Registers

REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER

R/W-0

SPIEN

U-0

—

R/W-0

U-0

—

U-0

—

R/W-0

SPISIDL

SPIBEC2

SPIBEC1

SPIBEC0

bit 15

bit 8

R/W-0

R/C-0, HS

SPIROV

R/W-0

R-0, HS, HC R-0, HS, HC

SPITBF SPIRBF

bit 0

SRMPT

SRXMPT

SISEL2

SISEL1

SISEL0

bit 7

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HS = Hardware Settable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

bit 15

SPIEN: SPI1 Enable bit

1= Enables the module and configures SCK1, SDO1, SDI1 and SS1 as serial port pins

0= Disables the module

bit 14

bit 13

Unimplemented: Read as ‘0’

SPISIDL: SPI1 Stop in Idle Mode bit

1= Discontinues the module operation when device enters Idle mode

0= Continues the module operation in Idle mode

bit 12-11

bit 10-8

Unimplemented: Read as ‘0’

SPIBEC<2:0>: SPI1 Buffer Element Count bits (valid in Enhanced Buffer mode)

Master mode:

Number of SPI1 transfers that are pending.

Slave mode:

Number of SPI1 transfers that are unread.

bit 7

bit 6

SRMPT: SPI1 Shift Register (SPI1SR) Empty bit (valid in Enhanced Buffer mode)

1= SPI1 Shift register is empty and ready to send or receive the data

0= SPI1 Shift register is not empty

SPIROV: SPI1 Receive Overflow Flag bit

1= A new byte/word is completely received and discarded; the user application has not read the previous

data in the SPI1BUF register

0= No overflow has occurred

bit 5

SRXMPT: SPI1 Receive FIFO Empty bit (valid in Enhanced Buffer mode)

1= RX FIFO is empty

0= RX FIFO is not empty

bit 4-2

SISEL<2:0>: SPI1 Buffer Interrupt Mode bits (valid in Enhanced Buffer mode)

111= Interrupt when the SPI1 transmit buffer is full (SPITBF bit is set)

110= Interrupt when last bit is shifted into SPI1SR, and as a result, the TX FIFO is empty

101= Interrupt when the last bit is shifted out of SPI1SR and the transmit is complete

100= Interrupt when one data is shifted into the SPI1SR, and as a result, the TX FIFO has one open

memory location

011= Interrupt when the SPI1 receive buffer is full (SPIRBF bit is set)

010= Interrupt when the SPI1 receive buffer is 3/4 or more full

001= Interrupt when data is available in the receive buffer (SRMPT bit is set)

000= Interrupt when the last data in the receive buffer is read, and as a result, the buffer is empty

(SRXMPT bit is set)

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REGISTER 16-1: SPI1STAT: SPI1 STATUS AND CONTROL REGISTER (CONTINUED)

bit 1

SPITBF: SPI1 Transmit Buffer Full Status bit

1= Transmit has not yet started, SPI1TXB is full

0= Transmit has started, SPI1TXB is empty

Standard Buffer mode:

Automatically set in hardware when core writes to the SPI1BUF location, loading SPI1TXB.

Automatically cleared in hardware when SPI1 module transfers data from SPI1TXB to SPI1SR.

Enhanced Buffer mode:

Automatically set in hardware when the CPU writes to the SPI1BUF location, loading the last available

buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write

operation.

bit 0

SPIRBF: SPI1 Receive Buffer Full Status bit

1= Receive is complete, SPI1RXB is full

0= Receive is incomplete, SPI1RXB is empty

Standard Buffer mode:

Automatically set in hardware when SPI1 transfers data from SPI1SR to SPI1RXB. Automatically

cleared in hardware when the core reads the SPI1BUF location, reading SPI1RXB.

Enhanced Buffer mode:

Automatically set in hardware when SPI1 transfers data from SPI1SR to the buffer, filling the last unread

buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from

SPI1SR.

DS70005208E-page 178

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REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1

U-0

—

U-0

—

U-0

—

R/W-0

SMP

R/W-0

(1)

DISSCK

DISSDO

MODE16

CKE

bit 15

bit 8

R/W-0

CKP

R/W-0

(2)

(3)

SSEN

bit 7

MSTEN

SPRE2

SPRE1

SPRE0

PPRE1

PPRE0

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12

Unimplemented: Read as ‘0’

DISSCK: Disable SCK1 Pin bit (SPI1 Master modes only)

1= Internal SPI1 clock is disabled, pin functions as I/O

0= Internal SPI1 clock is enabled

bit 11

bit 10

bit 9

DISSDO: Disable SDO1 Pin bit

1= SDO1 pin is not used by the module; pin functions as I/O

0= SDO1 pin is controlled by the module

MODE16: Word/Byte Communication Select bit

1= Communication is word-wide (16 bits)

0= Communication is byte-wide (8 bits)

SMP: SPI1 Data Input Sample Phase bit

Master mode:

1= Input data is sampled at the end of data output time

0= Input data is sampled at the middle of data output time

Slave mode:

SMP must be cleared when SPI1 is used in Slave mode.

(1)

bit 8

bit 7

bit 6

bit 5

CKE: SPI1 Clock Edge Select bit

1= Serial output data changes on transition from active clock state to Idle clock state (refer to bit 6)

0= Serial output data changes on transition from Idle clock state to active clock state (refer to bit 6)

(2)

SSEN: Slave Select Enable bit (Slave mode)

1= SS1 pin is used for Slave mode

0= SS1 pin is not used by the module; pin is controlled by port function

CKP: Clock Polarity Select bit

1= Idle state for clock is a high level; active state is a low level

0= Idle state for clock is a low level; active state is a high level

MSTEN: Master Mode Enable bit

1= Master mode

0= Slave mode

Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).

2: This bit must be cleared when FRMEN = 1.

3: Do not set both primary and secondary prescalers to the value of 1:1.

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REGISTER 16-2: SPI1CON1: SPI1 CONTROL REGISTER 1 (CONTINUED)

(3)

bit 4-2

SPRE<2:0>: Secondary Prescale bits (Master mode)

111= Secondary prescale 1:1

110= Secondary prescale 2:1

•

000= Secondary prescale 8:1

(3)

bit 1-0

PPRE<1:0>: Primary Prescale bits (Master mode)

11= Primary prescale 1:1

10= Primary prescale 4:1

01= Primary prescale 16:1

00= Primary prescale 64:1

Note 1: The CKE bit is not used in Framed SPI modes. Program this bit to ‘0’ for Framed SPI modes (FRMEN = 1).

2: This bit must be cleared when FRMEN = 1.

3: Do not set both primary and secondary prescalers to the value of 1:1.

DS70005208E-page 180

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REGISTER 16-3: SPI1CON2: SPI1 CONTROL REGISTER 2

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

FRMEN

SPIFSD

FRMPOL

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

FRMDLY

SPIBEN

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

bit 13

FRMEN: Framed SPI1 Support bit

1= Framed SPI1 support is enabled (SS1 pin is used as frame sync pulse input/output)

0= Framed SPI1 support is disabled

SPIFSD: Frame Sync Pulse Direction Control bit

1= Frame sync pulse input (slave)

0= Frame sync pulse output (master)

FRMPOL: Frame Sync Pulse Polarity bit

1= Frame sync pulse is active-high

0= Frame sync pulse is active-low

bit 12-2

bit 1

Unimplemented: Read as ‘0’

FRMDLY: Frame Sync Pulse Edge Select bit

1= Frame sync pulse coincides with first bit clock

0= Frame sync pulse precedes first bit clock

bit 0

SPIBEN: Enhanced Buffer Enable bit

1= Enhanced buffer is enabled

0= Enhanced buffer is disabled (Standard mode)

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NOTES:

DS70005208E-page 182

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2

The I C module offers the following key features:

17.0 INTER-INTEGRATED CIRCUIT

(I²C)

2

• I C Interface Supporting Both Master and Slave

modes of Operation

2

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this

data sheet, refer to “Inter-Integrated

Circuit™ (I²C)” (DS70000195) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

web site (www.microchip.com).

• I C Slave mode Supports 7 and 10-Bit Addressing

2

• I C Master mode Supports 7 and 10-Bit Addressing

2

• I C Port allows Bidirectional Transfers between

Master and Slaves

2

• Serial Clock Synchronization for I C Port can be

used as a Handshake Mechanism to Suspend

and Resume Serial Transfer (SCLREL control)

2

• I C Supports Multi-Master Operation, Detects Bus

Collision and Arbitrates Accordingly

• System Management Bus (SMBus) Support

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

2

17.1 I C Resources

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

The dsPIC33EPXXGS202 family of devices contains

2

one Inter-Integrated Circuit (I C) module.

17.1.1

KEY RESOURCES

2

The I C module provides complete hardware support

“Inter-Integrated Circuit™ (I²C)”

(DS70000195) in the “dsPIC33/PIC24 Family

Reference Manual”

2

•

for both Slave and Multi-Master modes of the I C serial

communication standard, with a 16-bit interface.

2

The I C module has a 2-pin interface:

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• The SCL1 pin is clock

• The SDA1 pin is data

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

 2015-2018 Microchip Technology Inc.

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FIGURE 17-1:

I2C1 BLOCK DIAGRAM

Internal

Data Bus

I2C1RCV

Read

Shift

Clock

SCL1

SDA1

I2C1RSR

LSb

Address Match

Write

Read

Match Detect

I2C1MSK

Write

Read

I2C1ADD

Start and Stop

Bit Detect

Write

Start and Stop

Bit Generation

I2C1STAT

Read

Write

Collision

Detect

I2C1CONL

I2C1CONH

Acknowledge

Generation

Read

Write

Clock

Stretching

Read

Write

Read

I2C1TRN

LSb

Shift Clock

Reload

Control

Write

Read

BRG Down Counter

I2C1BRG

FP/2

DS70005208E-page 184

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2

17.2 I C Control and Status Registers

REGISTER 17-1: I2C1CONL: I2C1 CONTROL REGISTER LOW

R/W-0

I2CEN

U-0

—

R/W-0

R/W-1, HC

SCLREL

R/W-0

A10M

R/W-0

SMEN

I2CSIDL

STRICT

DISSLW

bit 15

bit 8

R/W-0

GCEN

R/W-0

R/W-0, HC

ACKEN

R/W-0, HC

RCEN

R/W-0, HC

PEN

R/W-0, HC R/W-0, HC

RSEN SEN

bit 0

STREN

ACKDT

bit 7

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

‘1’ = Bit is set

bit 15

I2CEN: I2C1 Enable bit

1= Enables the I2C1 module and configures the SDA1 and SCL1 pins as serial port pins

2

0= Disables the I2C1 module; all I C pins are controlled by port functions

bit 14

bit 13

Unimplemented: Read as ‘0’

I2CSIDL: I2C1 Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

2

bit 12

SCLREL: SCL1 Release Control bit (when operating as I C slave)

1= Releases SCL1 clock

0= Holds SCL1 clock low (clock stretch)

If STREN = 1:

Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware is clear

at the beginning of every slave data byte transmission. Hardware is clear at the end of every slave

address byte reception. Hardware is clear at the end of every slave data byte reception.

If STREN = 0:

Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware is clear at the beginning of every

slave data byte transmission. Hardware is clear at the end of every slave address byte reception.

bit 11

STRICT: Strict I2C1 Reserved Address Enable bit

1= Strict Reserved Addressing is Enabled:

In Slave mode, the device will NACK any reserved address. In Master mode, the device is allowed

to generate addresses within the reserved address space.

0= Reserved Addressing is Acknowledged:

In Slave mode, the device will ACK any reserved address. In Master mode, the device should not

address a slave device with a reserved address.

bit 10

bit 9

bit 8

bit 7

A10M: 10-Bit Slave Address bit

1= I2C1ADD is a 10-bit slave address

0= I2C1ADD is a 7-bit slave address

DISSLW: Disable Slew Rate Control bit

1= Slew rate control is disabled

0= Slew rate control is enabled

SMEN: SMBus Input Levels bit

1= Enables I/O pin thresholds compliant with SMBus specification

0= Disables SMBus input thresholds

2

GCEN: General Call Enable bit (when operating as I C slave)

1= Enables interrupt when a general call address is received in I2C1RSR (module is enabled for reception)

0= General call address is disabled

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REGISTER 17-1: I2C1CONL: I2C1 CONTROL REGISTER LOW (CONTINUED)

2

bit 6

bit 5

bit 4

STREN: SCL1 Clock Stretch Enable bit (when operating as I C slave)

Used in conjunction with the SCLREL bit.

1= Enables software or receives clock stretching

0= Disables software or receives clock stretching

2

ACKDT: Acknowledge Data bit (when operating as I C master, applicable during master receive)

Value that is transmitted when the software initiates an Acknowledge sequence.

1= Sends NACK during Acknowledge

0= Sends ACK during Acknowledge

ACKEN: Acknowledge Sequence Enable bit

2

(when operating as I C master, applicable during master receive)

1= Initiates Acknowledge sequence on the SDA1 and SCL1 pins and transmits the ACKDT data bit.

Hardware clears it at the end of the master Acknowledge sequence.

0= Acknowledge sequence is not in progress

2

bit 3

bit 2

bit 1

bit 0

RCEN: Receive Enable bit (when operating as I C master)

2

1= Enables Receive mode for I C. Hardware clears it at the end of the eighth bit of the master receive

data byte.

0= Receive sequence is not in progress

2

PEN: Stop Condition Enable bit (when operating as I C master)

1= Initiates Stop condition on the SDA1 and SCL1 pins. Hardware clears it at the end of the master

Stop sequence.

0= Stop condition is not in progress

2

RSEN: Repeated Start Condition Enable bit (when operating as I C master)

1= Initiates Repeated Start condition on the SDA1 and SCL1 pins. Hardware clears it at the end of the

master Repeated Start sequence.

0= Repeated Start condition is not in progress

2

SEN: Start Condition Enable bit (when operating as I C master)

1= Initiates Start condition on the SDA1 and SCL1 pins. Hardware clears it at the end of the master

Start sequence.

0= Start condition is not in progress

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REGISTER 17-2: I2C1CONH: I2C1 CONTROL REGISTER HIGH

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

R/W-0

PCIE

R/W-0

SCIE

R/W-0

BOEN

R/W-0

AHEN

R/W-0

DHEN

SDAHT

SBCDE

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-7

bit 6

Unimplemented: Read as ‘0’

2

PCIE: Stop Condition Interrupt Enable bit (I C Slave mode only)

1= Enables interrupt on detection of Stop condition

0= Stop detection interrupts are disabled

2

bit 5

bit 4

SCIE: Start Condition Interrupt Enable bit (I C Slave mode only)

1= Enables interrupt on detection of Start or Restart conditions

0= Start detection interrupts are disabled

2

BOEN: Buffer Overwrite Enable bit (I C Slave mode only)

1= I2C1RCV is updated and an ACK is generated for a received address/data byte, ignoring the state

of the I2COV bit only if the RBF bit = 0

0= I2C1RCV is only updated when I2COV is clear

bit 3

bit 2

SDAHT: SDA1 Hold Time Selection bit

1= Minimum of 300 ns hold time on SDA1 after the falling edge of SCL1

0= Minimum of 100 ns hold time on SDA1 after the falling edge of SCL1

2

SBCDE: Slave Mode Bus Collision Detect Enable bit (I C Slave mode only)

1= Enables slave bus collision interrupts

0= Slave bus collision interrupts are disabled

If the rising edge of SCL1 and SDA1 is sampled low when the module is in a high state, the BCL bit is

set and the bus goes Idle. This Detection mode is only valid during data and ACK transmit sequences.

2

bit 1

bit 0

AHEN: Address Hold Enable bit (I C Slave mode only)

1= Following the 8th falling edge of SCL1 for a matching received address byte, the SCLREL

(I2C1CONL<12>) bit will be cleared and SCL1 will be held low

0= Address holding is disabled

2

DHEN: Data Hold Enable bit (I C Slave mode only)

1 = Following the 8th falling edge of SCL1 for a received data byte, the slave hardware clears the

SCLREL (I2C1CONL<12>) bit and SCL1 is held low

0= Data holding is disabled

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REGISTER 17-3: I2C1STAT: I2C1 STATUS REGISTER

R-0, HSC

ACKSTAT

bit 15

R-0, HSC R-0, HSC

TRSTAT ACKTIM

U-0

—

U-0

—

R/C-0, HS

BCL

R-0, HSC

GCSTAT

R-0, HSC

ADD10

bit 8

bit 0

R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC

R-0, HSC

R_W

R-0, HSC

RBF

R-0, HSC

TBF

IWCOL

bit 7

I2COV

D_A

P

S

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

2

bit 15

ACKSTAT: Acknowledge Status bit (when operating as I C master, applicable to master transmit operation)

1= NACK was received from slave

0= ACK was received from slave

It is set or cleared by the hardware at the end of a slave Acknowledge.

2

bit 14

TRSTAT: Transmit Status bit (when operating as I C master, applicable to master transmit operation)

1= Master transmit is in progress (8 bits + ACK)

0= Master transmit is not in progress

It is set by the hardware at the beginning of master transmission. Hardware is clear at the end of slave

Acknowledge.

2

bit 13

ACKTIM: Acknowledge Time Status bit (I C Slave mode only)

2

1= I C bus is an Acknowledge sequence, set on the 8th falling edge of SCL1

0= Not an Acknowledge sequence, cleared on the 9th rising edge of SCL1

bit 12-11

bit 10

Unimplemented: Read as ‘0’

BCL: Master Bus Collision Detect bit

1= A bus collision has been detected during a master operation

0= No bus collision detected

It is set by the hardware at detection of a bus collision.

bit 9

bit 8

GCSTAT: General Call Status bit

1= General call address was received

0= General call address was not received

It is set by the hardware when the address matches the general call address. Hardware is clear at Stop

detection.

ADD10: 10-Bit Address Status bit

1= 10-bit address was matched

0= 10-bit address was not matched

Hardware is set at the match of the 2nd byte of the matched 10-bit address. Hardware is clear at Stop

detection.

bit 7

bit 6

bit 5

IWCOL: I2C1 Write Collision Detect bit

2

1= An attempt to write to the I2C1TRN register failed because the I C module is busy

0= No collision

Hardware is set at the occurrence of a write to I2C1TRN while busy (cleared by software).

I2COV: I2C1 Receive Overflow Flag bit

1= A byte was received while the I2C1RCV register was still holding the previous byte

0= No overflow

It is set by the hardware at an attempt to transfer I2C1RSR to I2C1RCV (cleared by software).

2

D_A: Data/Address bit (I C Slave mode only)

1= Indicates that the last byte received was data

0= Indicates that the last byte received was a device address

It is cleared by the hardware at a device address match. Hardware is set by reception of a slave byte.

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REGISTER 17-3: I2C1STAT: I2C1 STATUS REGISTER (CONTINUED)

bit 4

bit 3

bit 2

bit 1

P: Stop bit

1= Indicates that a Stop bit has been detected last

0= Stop bit was not detected last

Hardware is set or clear when a Start, Repeated Start or Stop is detected.

S: Start bit

1= Indicates that a Start (or Repeated Start) bit has been detected last

0= Start bit was not detected last

Hardware is set or clear when a Start, Repeated Start or Stop is detected.

2

R_W: Read/Write Information bit (I C Slave mode only)

1= Read – Indicates data transfer is output from the slave

0= Write – Indicates data transfer is input to the slave

Hardware is set or clear after reception of an I C device address byte.

2

RBF: Receive Buffer Full Status bit

1= Receive is complete, I2C1RCV is full

0= Receive is not complete, I2C1RCV is empty

Hardware is set when I2C1RCV is written with a received byte. Hardware is clear when software reads

I2C1RCV.

bit 0

TBF: Transmit Buffer Full Status bit

1= Transmit is in progress, I2C1TRN is full

0= Transmit is complete, I2C1TRN is empty

Hardware is set when software writes to I2C1TRN. Hardware is clear at completion of a data transmission.

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REGISTER 17-4: I2C1MSK: I2C1 SLAVE MODE ADDRESS MASK REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

AMSK<9:8>

bit 15

R/W-0

bit 7

bit 8

R/W-0

bit 0

R/W-0

AMSK<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

AMSK<9:0>: Address Mask Select bits

For 10-Bit Address:

1= Enables masking for bit Ax of incoming message address; bit match is not required in this position

0= Disables masking for bit Ax; bit match is required in this position

For 7-Bit Address (I2C1MSK<6:0> only):

1= Enables masking for bit Ax + 1 of incoming message address; bit match is not required in this position

0= Disables masking for bit Ax + 1; bit match is required in this position

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The primary features of the UART1 module are:

18.0 UNIVERSAL ASYNCHRONOUS

• Full-Duplex, 8 or 9-Bit Data Transmission through

the U1TX and U1RX Pins

RECEIVER TRANSMITTER

(UART)

• Even, Odd or No Parity Options (for 8-bit data)

• One or Two Stop bits

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Universal Asynchro-

nous Receiver Transmitter (UART)”

(DS70000582) in the “dsPIC33/PIC24

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

• Hardware Flow Control Option with U1CTS and

U1RTS Pins

• Fully Integrated Baud Rate Generator with 16-Bit

Prescaler

• Baud Rates Ranging from 4.375 Mbps to 67 bps in

16x mode at 60 MIPS

• Baud Rates Ranging from 17.5 Mbps to 267 bps in

4x mode at 60 MIPS

• 4-Deep First-In First-Out (FIFO) Transmit Data

Buffer

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• 4-Deep FIFO Receive Data Buffer

• Parity, Framing and Buffer Overrun Error Detection

• Support for 9-bit mode with Address Detect

(9th bit = 1)

• Transmit and Receive Interrupts

• A Separate Interrupt for all UART1 Error Conditions

• Loopback mode for Diagnostic Support

• Support for Sync and Break Characters

• Support for Automatic Baud Rate Detection

• IrDA^®Encoder and Decoder Logic

The dsPIC33EPXXGS202 family of devices contains

one UART module.

The Universal Asynchronous Receiver Transmitter

(UART) module is one of the serial I/O modules

available in the dsPIC33EPXXGS202 device family.

The UART is a full-duplex, asynchronous system that

can communicate with peripheral devices, such as

personal computers, LIN/J2602, RS-232 and RS-485

interfaces. The module also supports a hardware flow

control option with the U1CTS and U1RTS pins, and

also includes an IrDA^®encoder and decoder.

• 16x Baud Clock Output for IrDA Support

A simplified block diagram of the UART1 module is

shown in Figure 18-1. The UART1 module consists of

these key hardware elements:

• Baud Rate Generator

• Asynchronous Transmitter

• Asynchronous Receiver

FIGURE 18-1:

UART1 SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA^®

Hardware Flow Control

UART1 Receiver

U

1RTS/BCLK1

1CTS

U

1RX

UART1 Transmitter

U

1TX

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18.1 UART Helpful Tips

18.2 UART Resources

1. In multi-node, direct connect UART networks,

UART receive inputs react to the complemen-

tary logic level defined by the URXINV bit

(U1MODE<4>), which defines the Idle state, the

default of which is logic high (i.e., URXINV = 0).

Because remote devices do not initialize at the

same time, it is likely that one of the devices,

because the RX line is floating, will trigger a Start

bit detection and will cause the first byte received,

after the device has been initialized, to be invalid.

To avoid this situation, the user should use a pull-

up or pull-down resistor on the RX pin depending

on the value of the URXINV bit.

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

18.2.1

KEY RESOURCES

•

“Universal Asynchronous Receiver

Transmitter (UART)” (DS70000582) in the

“dsPIC33/PIC24 Family Reference Manual”

• Code Samples

• Application Notes

• Software Libraries

• Webinars

a) If UR1INV = 0, use a pull-up resistor on the

UxRX pin.

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

b) If UR1INV = 1, use a pull-down resistor on

the UxRX pin.

• Development Tools

2. The first character received on a wake-up from

Sleep mode, caused by activity on the U1RX pin

of the UART1 module, will be invalid. In Sleep

mode, peripheral clocks are disabled. By the

time the oscillator system has restarted and

stabilized from Sleep mode, the baud rate bit

sampling clock, relative to the incoming U1RX

bit timing, is no longer synchronized, resulting in

the first character being invalid; this is to be

expected.

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18.3 UART Control and Status Registers

REGISTER 18-1: U1MODE: UART1 MODE REGISTER

R/W-0

UARTEN

bit 15

U-0

—

R/W-0

USIDL

R/W-0

U-0

—

R/W-0

UEN1

R/W-0

UEN0

(1)

(2)

IREN

RTSMD

bit 8

R/W-0, HC

WAKE

R/W-0

R/W-0, HC

ABAUD

R/W-0

BRGH

R/W-0

LPBACK

URXINV

PDSEL1

PDSEL0

STSEL

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

W = Writable bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

(1)

bit 15

UARTEN: UART1 Enable bit

1= UART1 is enabled; all UART1 pins are controlled by UART1, as defined by UEN<1:0>

0= UART1 is disabled; all UART1 pins are controlled by PORT latches; UART1 power consumption is

minimal

bit 14

bit 13

Unimplemented: Read as ‘0’

USIDL: UART1 Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

®

(2)

bit 12

bit 11

IREN: IrDA Encoder and Decoder Enable bit

1= IrDA encoder and decoder are enabled

0= IrDA encoder and decoder are disabled

RTSMD: Mode Selection for U1RTS Pin bit

1= U1RTS pin is in Simplex mode

0= U1RTS pin is in Flow Control mode

bit 10

Unimplemented: Read as ‘0’

bit 9-8

UEN<1:0>: UART1 Pin Enable bits

11= U1TX, U1RX and BCLK1 pins are enabled and used; U1CTS pin is controlled by PORT latches

10= U1TX, U1RX, U1CTS and U1RTS pins are enabled and used

01= U1TX, U1RX and U1RTS pins are enabled and used; U1CTS pin is controlled by PORT latches

00= U1TX and U1RX pins are enabled and used; U1CTS and U1RTS/BCLK1 pins are controlled by

PORT latches

bit 7

WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit

1= UART1 continues to sample the U1RX pin, interrupt is generated on the falling edge; bit is cleared

in hardware on the following rising edge

0= No wake-up is enabled

bit 6

bit 5

LPBACK: UART1 Loopback Mode Select bit

1= Enables Loopback mode

0= Loopback mode is disabled

ABAUD: Auto-Baud Enable bit

1= Enables baud rate measurement on the next character – requires reception of a Sync field (55h)

before other data; cleared in hardware upon completion

0= Baud rate measurement is disabled or completed

Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/PIC24

Family Reference Manual” for information on enabling the UART1 module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

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REGISTER 18-1: U1MODE: UART1 MODE REGISTER (CONTINUED)

bit 4

URXINV: UART1 Receive Polarity Inversion bit

1= U1RX Idle state is ‘0’

0= U1RX Idle state is ‘1’

bit 3

BRGH: High Baud Rate Enable bit

1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)

0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)

bit 2-1

PDSEL<1:0>: Parity and Data Selection bits

11= 9-bit data, no parity

10= 8-bit data, odd parity

01= 8-bit data, even parity

00= 8-bit data, no parity

bit 0

STSEL: Stop Bit Selection bit

1= Two Stop bits

0= One Stop bit

Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/PIC24

Family Reference Manual” for information on enabling the UART1 module for receive or transmit operation.

2: This feature is only available for the 16x BRG mode (BRGH = 0).

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REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER

R/W-0

UTXISEL1

bit 15

R/W-0

U-0

—

R/W-0, HC

UTXBRK

R/W-0

R-0

R-1

(1)

UTXINV

UTXISEL0

UTXEN

UTXBF

TRMT

bit 8

R/W-0

URXISEL1

bit 7

R/W-0

R-1

R-0

R/C-0

R-0

URXISEL0

ADDEN

RIDLE

PERR

FERR

OERR

URXDA

bit 0

Legend:

C = Clearable bit

W = Writable bit

‘1’ = Bit is set

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

bit 15,13

UTXISEL<1:0>: UART1 Transmission Interrupt Mode Selection bits

11= Reserved; do not use

10= Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the

transmit buffer becomes empty

01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations

are completed

00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least

one character open in the transmit buffer)

bit 14

UTXINV: UART1 Transmit Polarity Inversion bit

If IREN = 0:

1= U1TX Idle state is ‘0’

0= U1TX Idle state is ‘1’

If IREN = 1:

®

1= IrDA encoded, U1TX Idle state is ‘1’

0= IrDA encoded, U1TX Idle state is ‘0’

bit 12

bit 11

Unimplemented: Read as ‘0’

UTXBRK: UART1 Transmit Break bit

1= Sends Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;

cleared by hardware upon completion

0= Sync Break transmission is disabled or completed

(1)

bit 10

UTXEN: UART1 Transmit Enable bit

1= Transmit is enabled, U1TX pin is controlled by UART1

0= Transmit is disabled, any pending transmission is aborted and buffer is reset; U1TX pin is

controlled by the PORT

bit 9

UTXBF: UART1 Transmit Buffer Full Status bit (read-only)

1= Transmit buffer is full

0= Transmit buffer is not full, at least one more character can be written

bit 8

TRMT: Transmit Shift Register Empty bit (read-only)

1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)

0= Transmit Shift Register is not empty, a transmission is in progress or queued

bit 7-6

URXISEL<1:0>: UART1 Receive Interrupt Mode Selection bits

11= Interrupt is set on U1RSR transfer, making the receive buffer full (i.e., has four data characters)

10= Interrupt is set on U1RSR transfer, making the receive buffer 3/4 full (i.e., has three data characters)

0x= Interrupt is set when any character is received and transferred from the U1RSR to the receive

buffer; receive buffer has one or more characters

Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/PIC24

Family Reference Manual” for information on enabling the UART1 module for transmit operation.

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REGISTER 18-2: U1STA: UART1 STATUS AND CONTROL REGISTER (CONTINUED)

bit 5

bit 4

bit 3

bit 2

bit 1

ADDEN: Address Character Detect bit (bit 8 of received data = 1)

1= Address Detect mode is enabled; if 9-bit mode is not selected, this does not take effect

0= Address Detect mode is disabled

RIDLE: Receiver Idle bit (read-only)

1= Receiver is Idle

0= Receiver is active

PERR: Parity Error Status bit (read-only)

1= Parity error has been detected for the current character (character at the top of the receive FIFO)

0= Parity error has not been detected

FERR: Framing Error Status bit (read-only)

1= Framing error has been detected for the current character (character at the top of the receive FIFO)

0= Framing error has not been detected

OERR: Receive Buffer Overrun Error Status bit (clear/read-only)

1= Receive buffer has overflowed

0= Receive buffer has not overflowed; clearing a previously set OERR bit (1 0transition) resets the

receiver buffer and the U1RSR to the empty state

bit 0

URXDA: UART1 Receive Buffer Data Available bit (read-only)

1= Receive buffer has data, at least one more character can be read

0= Receive buffer is empty

Note 1: Refer to “Universal Asynchronous Receiver Transmitter (UART)” (DS70000582) in the “dsPIC33/PIC24

Family Reference Manual” for information on enabling the UART1 module for transmit operation.

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• Flexible Trigger Options

19.0 HIGH-SPEED, 12-BIT

ANALOG-TO-DIGITAL

CONVERTER (ADC)

• Early Interrupt Generation to Enable Fast

Processing of Converted Data

• Two Integrated Digital Comparators:

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “12-Bit High-Speed,

- Multiple comparison options

- Assignable to specific analog inputs

• Oversampling Filters:

- Provides increased resolution

- Assignable to a specific analog input

• Operation During CPU Sleep and Idle modes

Multiple SARs A/D Converter (ADC)

”

(DS70005213) in the “dsPIC33/PIC24

Family Reference Manual”, which is

available from the Microchip web site

(www.microchip.com).

Simplified block diagrams of the Multiple SARs 12-Bit

ADC are shown in Figure 19-1, Figure 19-2 and

Figure 19-3.

The module consists of two independent SAR ADC

cores. The analog inputs (channels) are connected

through multiplexers and switches to the Sample-and-

Hold (S/H) circuit of each ADC core. The core uses the

channel information (the output format, the measure-

ment mode and the input number) to process the analog

sample. When conversion is complete, the result is

stored in the result buffer for the specific analog input

and passed to the digital filter and digital comparator if

they were configured to use data from this particular

channel.

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

The dsPIC33EPXXGS202 devices have a high-

speed, 12-bit Analog-to-Digital Converter (ADC) that

features a low conversion latency, high resolution and

oversampling capabilities to improve performance in

AC/DC, DC/DC power converters.

The ADC module can sample up to three inputs at a

time (two inputs from the dedicated SAR ADC cores

and one from the shared SAR ADC cores). If multiple

ADC inputs request conversion, the ADC module will

convert them in a sequential manner, starting with the

lowest order input.

19.1 Features Overview

The 12-Bit High Speed Multiple SARs Analog-to-Digital

Converter (ADC) includes the following features:

• 12-Bit Resolution

The ADC provides each analog input the ability to

specify its own trigger source. This capability allows the

ADC to sample and convert analog inputs that are

associated with PWM generators operating on

independent time bases.

• Up to 3.25 Msps Conversion Rate per ADC Core @

12-Bit Resolution

• Two Dedicated ADC Cores

• One Shared (common) ADC Core

• Up to Fifteen Analog Inputs (external and internal)

• Conversion Result can be Formatted as Unsigned

or Signed Data on a per Channel Basis for All

Channels

• Separate 16-Bit Conversion Result Register for

each Analog Input

• Simultaneous Sampling of up to Three Analog Inputs

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FIGURE 19-1:

ADC MODULE BLOCK DIAGRAM

AVDD AVSS

Voltage Reference

AN0

Reference

Dedicated

ADC Core 0

AN7

Output Data

Clock

(3)

(1)

PGA1

PGA2

Digital Comparator 0

Digital Comparator 1

ADCMP0 Interrupt

ADCMP1 Interrupt

Reference

Output Data

Clock

AN1

AN8

Dedicated

ADC Core 1

(3)

Digital Filter 0

ADFL0DAT

(1)

ADFL0 Interrupt

PGA1

PGA2

ADCBUF0

ADCBUF1

ADCAN0 Interrupt

Reference

Output Data

Clock

AN2

ADCAN1 Interrupt

AN11

ADCBUF14

Shared

ADC Core

ADCAN14 Interrupt

(2)

(1)

PGA1(AN12)

PGA2(AN13)

Divider

(CLKDIV<5:0> bits)

V

REF_Band Gap

(1)

(AN14)

Clock Selection

(CLKSEL<1:0> bits)

Instruction FRC

Clock

FOSC

AUX

Clock

Note 1: PGA1, PGA2 and VREF_Band Gap are internal analog inputs and are not available on device pins.

2: Shared ADC core does not support pseudodifferential operation.

3: If the dedicated core uses an alternate channel, then shared core function cannot be used.

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FIGURE 19-2:

DEDICATED ADC CORE 0-1 BLOCK DIAGRAM

Positive Input

Selection

(CxCHS<1:0>

bits)

(1)

PGA1

PGA2

Alternate

+

–

Reference

Positive Input

12-Bit SAR

ADC

Sample-

and-Hold

Output Data

Negative Input

Selection

Negative Input

(DIFFx bit)

ADC Core

Clock Divider

(ADCS<6:0>

bits)

Clock

Trigger Stops

Sampling

AVSS

Note 1: PGA1 and PGA2 are internal analog inputs and are not available on device pins.

FIGURE 19-3:

SHARED ADC CORE BLOCK DIAGRAM

AN2

AN11

+

(1)

PGA1(AN12)

PGA2(AN13)

Reference

12-Bit

SAR ADC

V

REF_Band Gap(AN14)

Output Data

Clock

Shared

Sample-

and-Hold

Analog Channel Number

from Current Trigger

ADC Core

Clock Divider

(SHRADCS<6:0>

bits)

Sampling Time is Defined

by SHRSAMC<9:0> bits

AVSS

Note 1: PGA1, PGA2 and VREF_Band Gap are internal analog inputs and are not available on device pins.

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19.2.1

KEY RESOURCES

19.2 Analog-to-Digital Converter

Resources

•

“12-Bit High-Speed, Multiple SARs A/D

Converter (ADC)” (DS70005213) in the

“dsPIC33/PIC24 Family Reference Manual”

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

19.3 Analog-to-Digital Converter Control and Status Registers

REGISTER 19-1: ADCON1L: ADC CONTROL REGISTER 1 LOW

R/W-0

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

(1)

ADON

bit 15

ADSIDL

bit 8

bit 0

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

(2)

NRE

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

(1)

bit 15

ADON: ADC Enable bit

1= ADC module is enabled

0= ADC module is off

bit 14

bit 13

Unimplemented: Read as ‘0’

ADSIDL: ADC Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode

0= Continues module operation in Idle mode

bit 12-8

bit 7

Unimplemented: Read as ‘0’

(2)

NRE: Noise Reduction Enable bit

1= Holds conversion process for 1 TADCORE when another core completes conversion to reduce noise

between cores

0= Noise reduction feature is disabled

bit 6-0

Unimplemented: Read as ‘0’

Note 1: Set the ADON bit only after the ADC module has been configured. Changing ADC Configuration bits when

ADON = 1will result in unpredictable behavior.

2: If the NRE bit in the ADCON1L register is set, the end of conversion time is adjusted to reduce the noise

between ADC cores. Depending on the number of cores converting and the priority of the input, a few addi-

tional TADs may be inserted, making the conversion time slightly less deterministic.

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REGISTER 19-2: ADCON1H: ADC CONTROL REGISTER 1 HIGH

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

bit 0

R/W-0

FORM

R/W-1

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

SHRRES1

SHRRES0

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-8

bit 7

Unimplemented: Read as ‘0’

FORM: Fractional Data Output Format bit

1= Fractional

0= Integer

bit 6-5

bit 4-0

SHRRES<1:0>: Shared ADC Core Resolution Selection bits

11= 12-bit resolution

10= 10-bit resolution

01= 8-bit resolution

00= 6-bit resolution

Unimplemented: Read as ‘0’

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REGISTER 19-3: ADCON2L: ADC CONTROL REGISTER 2 LOW

R/W-0

REFCIE REFERCIE

bit 15

R/W-0

U-0

—

R/W-0

EIEN

U-0

—

R/W-0

(2)

(1)

SHREISEL2 SHREISEL1 SHREISEL0

bit 8

U-0

R/W-0

SHRADCS0

bit 0

—

SHRADCS6 SHRADCS5 SHRADCS4 SHRADCS3 SHRADCS2

SHRADCS1

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

bit 14

REFCIE: Band Gap and Reference Voltage Ready Common Interrupt Enable bit

1= Common interrupt will be generated when the band gap will become ready

0= Common interrupt is disabled for the band gap ready event

(2)

REFERCIE: Band Gap or Reference Voltage Error Common Interrupt Enable bit

1= Common interrupt will be generated when the band gap or reference voltage error is detected

0= Common interrupt is disabled for the band gap and reference voltage error event

bit 13

bit 12

Unimplemented: Read as ‘0’

EIEN: Early Interrupts Enable bit

1= The early interrupt feature is enabled for the input channels interrupts (when EISTATx flag is set)

0= The individual interrupts are generated when conversion is done (when ANxRDY flag is set)

bit 11

Unimplemented: Read as ‘0’

(1)

bit 10-8

SHREISEL<2:0>: Shared Core Early Interrupt Time Selection bits

111= Early interrupt is set and interrupt is generated 8 TADCORE clocks prior to when the data is ready

110= Early interrupt is set and interrupt is generated 7 TADCORE clocks prior to when the data is ready

101= Early interrupt is set and interrupt is generated 6 TADCORE clocks prior to when the data is ready

100= Early interrupt is set and interrupt is generated 5 TADCORE clocks prior to when the data is ready

011= Early interrupt is set and interrupt is generated 4 TADCORE clocks prior to when the data is ready

010= Early interrupt is set and interrupt is generated 3 TADCORE clocks prior to when the data is ready

001= Early interrupt is set and interrupt is generated 2 TADCORE clocks prior to when the data is ready

000= Early interrupt is set and interrupt is generated 1 TADCORE clock prior to when the data is ready

bit 7

Unimplemented: Read as ‘0’

bit 6-0

SHRADCS<6:0>: Shared ADC Core Input Clock Divider bits

These bits determine the number of TCORESRC (Core Source Clock) periods for one shared TADCORE (ADC

Core Clock) period.

1111111= 254 Core Source Clock periods

•

0000011= 6 Core Source Clock periods

0000010= 4 Core Source Clock periods

0000001= 2 Core Source Clock periods

0000000= 2 Core Source Clock periods

Note 1: For the 6-bit shared ADC core resolution (SHRRES<1:0> = 00), the SHREISEL<2:0> settings,

from ‘100’ to ‘111’, are not valid and should not be used. For the 8-bit shared ADC core resolution

(SHRRES<1:0> = 01), the SHREISEL<2:0> settings, ‘110’ and ‘111’, are not valid and should not be used.

2: To avoid false interrupts, the REFERCIE bit must be set only after the module is enabled (ADON = 1).

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REGISTER 19-4: ADCON2H: ADC CONTROL REGISTER 2 HIGH

R-0, HS, HC R-0, HS, HC

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

REFRDY

bit 15

REFERR

SHRSAMC9 SHRSAMC8

bit 8

R/W-0

SHRSAMC7 SHRSAMC6 SHRSAMC5 SHRSAMC4

bit 7

SHRSAMC3 SHRSAMC2 SHRSAMC1 SHRSAMC0

bit 0

Legend:

HS = Hardware Settable bit HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

bit 14

REFRDY: Band Gap and Reference Voltage Ready Flag bit

1= Band gap is ready

0= Band gap is not ready

REFERR: Band Gap or Reference Voltage Error Flag bit

1= Band gap was removed after the ADC module was enabled (ADON =

0= No band gap error was detected

1)

bit 13-10

bit 9-0

Unimplemented: Read as ‘0’

SHRSAMC<9:0>: Shared ADC Core Sample Time Selection bits

These bits specify the number of shared ADC Core Clock (TADCORE) periods for the shared ADC core

sample time.

1111111111= 1025 TADCORE

•

0000000001= 3 TADCORE

0000000000= 2 TADCORE

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REGISTER 19-5: ADCON3L: ADC CONTROL REGISTER 3 LOW

R/W-0

R-0, HS, HC

SUSPRDY

R/W-0

R-0, HS, HC

CNVRTCH

REFSEL2 REFSEL1

bit 15

REFSEL0

SUSPEND

SUSPCIE

SHRSAMP

bit 8

R/W-0

R-0, HS, HC

R/W-0

SWLCTRG SWCTRG CNVCHSEL5 CNVCHSEL4 CNVCHSEL3 CNVCHSEL2 CNVCHSEL1 CNVCHSEL0

bit 7

bit 0

Legend:

HS = Hardware Settable bit HC = Hardware Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

REFSEL<2:0>: ADC Reference Voltage Selection bits

Value

VREFH

VREFL

000

AVDD

AVSS

001-111= Unimplemented: Should not be used

SUSPEND: All ADC Cores Triggers Disable bit

bit 12

bit 11

1= All new triggers events for all ADC cores are disabled

0= All ADC cores can be triggered

SUSPCIE: Suspend All ADC Cores Common Interrupt Enable bit

1= Common interrupt will be generated when ADC cores triggers are suspended (SUSPEND bit =

and all previous conversions are finished (SUSPRDY bit becomes set)

1)

0= Common interrupt is not generated for suspend ADC cores event

bit 10

bit 9

SUSPRDY: All ADC Cores Suspended Flag bit

1= All ADC cores are suspended (SUSPEND bit =

0= ADC cores have previous conversions in progress

SHRSAMP: Shared ADC Core Sampling Direct Control bit

1) and have no conversions in progress

This bit should be used with the individual channel conversion trigger controlled by the CNVRTCH bit. It

connects an analog input, specified by CNVCHSEL<5:0> bits, to the shared ADC core and allows extend-

ing the sampling time. This bit is not controlled by hardware and must be cleared before the conversion

starts (setting CNVRTCH to ‘1’).

1= Shared ADC core samples an analog input specified by the CNVCHSEL<5:0> bits

0= Sampling is controlled by the shared ADC core hardware

bit 8

bit 7

bit 6

CNVRTCH: Software Individual Channel Conversion Trigger bit

1= Single trigger is generated for an analog input specified by the CNVCHSEL<5:0> bits. When the bit

is set, it is automatically cleared by hardware on the next instruction cycle.

0= Next individual channel conversion trigger can be generated

SWLCTRG: Software Level-Sensitive Common Trigger bit

1= Triggers are continuously generated for all channels with the software, level-sensitive, common

trigger selected as a source in the ADTRIGxL and ADTRIGxH registers

0= No software, level-sensitive, common triggers are generated

SWCTRG: Software Common Trigger bit

1= Single trigger is generated for all channels with the software, common trigger selected as a source

in the ADTRIGxL and ADTRIGxH registers. When the bit is set, it is automatically cleared by

hardware on the next instruction cycle

0= Ready to generate the next software, common trigger

bit 5-0

CNVCHSEL <5:0>: Channel Number Selection for Software Individual Channel Conversion Trigger bits

These bits define a channel to be converted when the CNVRTCH bit is set.

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REGISTER 19-6: ADCON3H: ADC CONTROL REGISTER 3 HIGH

R/W-0

CLKSEL1

bit 15

R/W-0

CLKSEL0

CLKDIV5

CLKDIV4

CLKDIV3

CLKDIV2

CLKDIV1

CLKDIV0

bit 8

R/W-0

SHREN

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

C1EN

R/W-0

C0EN

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-14

bit 13-8

CLKSEL<2:0>: ADC Module Clock Source Selection bits

11= APLL

10= FRC

01= FOSC (System Clock x 2)

00= FSYS (System Clock)

CLKDIV<5:0>: ADC Module Clock Source Divider bits

The divider forms a TCORESRC clock used by all ADC cores (shared and dedicated) from the TSRC ADC

module clock source selected by the CLKSEL<2:0> bits. Then, each ADC core individually divides the

TCORESRC clock to get a core-specific TADCORE clock using the ADCS<6:0> bits in the ADCORExH

register or the SHRADCS<6:0> bits in the ADCON2L register.

111111= 64 Core Source Clock periods

•

000011= 4 Core Source Clock periods

000010= 3 Core Source Clock periods

000001= 2 Core Source Clock periods

000000= 1 Core Source Clock period

bit 7

SHREN: Shared ADC Core Enable bit

This bit does not disable the core clock and analog bias circuitry.

1= Shared ADC core is enabled

0= Shared ADC core is disabled

bit 6-2

bit 1-0

Unimplemented: Read as ‘0’

C1EN:C0EN: Dedicated ADC Core x Enable bits

This bit does not disable the core clock and analog bias circuitry.

1= Dedicated ADC Core x is enabled

0= Dedicated ADC Core x is disabled

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REGISTER 19-7: ADCON4L: ADC CONTROL REGISTER 4 LOW

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

r-0

—

r-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SAMC1EN

SAMC0EN

bit 7

bit 0

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

R = Readable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-10 Unimplemented: Read as ‘0’

bit 9-8

bit 7-2

bit 1-0

Reserved: Maintain as ‘0’

Unimplemented: Read as ‘0’

SAMC1EN:SAMC0EN: Dedicated ADC Core x Conversion Delay Enable bits

1= After trigger, the conversion will be delayed and the ADC core will continue sampling during the time

specified by the SAMC<9:0> bits in the ADCORExL register

0= After trigger, the sampling will be stopped immediately and the conversion will be started on the next

core clock cycle.

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REGISTER 19-8: ADCON4H: ADC CONTROL REGISTER 4 HIGH

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

C1CHS1

C1CHS0

C0CHS1

C0CHS0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-4

bit 3-2

Unimplemented: Read as ‘0’

C1CHS<1:0>: Dedicated ADC Core 1 Input Channel Selection bits

11= PGA2

10= PGA1

01= AN8

00= AN1

AN8 is a negative input when DIFF1 (ADMOD0L<3>) = 1.

bit 1-0

C0CHS<1:0>: Dedicated ADC Core 0 Input Channel Selection bits

11= PGA2

10= PGA1

01= AN7

00= AN0

AN7 is a negative input when DIFF0 (ADMOD0L<1>) = 1.

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REGISTER 19-9: ADCON5L: ADC CONTROL REGISTER 5 LOW

R-0, HC, HS

SHRRDY

bit 15

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R-0, HC, HS R-0, HC, HS

C1RDY

C0RDY

bit 8

R/W-0

SHRPWR

bit 7

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

C1PWR

C0PWR

bit 0

Legend:

HS = Hardware Settable bit

W = Writable bit

HC = Hardware Clearable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

R = Readable bit

-n = Value at POR

‘1’ = Bit is set

bit 15

SHRRDY: Shared ADC Core Ready Flag bit

1= ADC core is powered and ready for operation

0= ADC core is not ready for operation

bit 14-10

bit 9-8

Unimplemented: Read as ‘0’

C1RDY:C0RDY: Dedicated ADC Core x Ready Flag bits

1= ADC Core x is powered and ready for operation

0= ADC Core x is not ready for operation

bit 7

SHRPWR: Shared ADC Core x Power Enable bit

1= ADC Core x is powered

0= ADC Core x is off

bit 6-2

bit 1-0

Unimplemented: Read as ‘0’

C1PWR:C0PWR: Dedicated ADC Core x Power Enable bits

1= ADC Core x is powered

0= ADC Core x is off

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REGISTER 19-10: ADCON5H: ADC CONTROL REGISTER 5 HIGH

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

WARMTIME3 WARMTIME2 WARMTIME1 WARMTIME0

bit 8

bit 15

R/W-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

C1CIE

R/W-0

C0CIE

SHRCIE

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-12

bit 11-8

Unimplemented: Read as ‘0’

WARMTIME<3:0>: ADC Cores Power-up Delay bits

These bits determine the power-up delay in the number of the Core Source Clock (TCORESRC) periods

for all ADC cores.

1111= 32768 Core Source Clock periods

1110= 16384 Core Source Clock periods

1101= 8192 Core Source Clock periods

1100= 4096 Core Source Clock periods

1011= 2048 Core Source Clock periods

1010= 1024 Core Source Clock periods

1001= 512 Core Source Clock periods

1000= 256 Core Source Clock periods

0111= 128 Core Source Clock periods

0110= 64 Core Source Clock periods

0101= 32 Core Source Clock periods

0000-0100= 16 Core Source Clock periods

bit 7

SHRCIE: Shared ADC Core Ready Common Interrupt Enable bit

1= Common interrupt will be generated when ADC core is powered and ready for operation

0= Common interrupt is disabled for an ADC core ready event

bit 6-2

bit 1-0

Unimplemented: Read as ‘0’

C1CIE:C0CIE: Dedicated ADC Core x Ready Common Interrupt Enable bits

1= Common interrupt will be generated when ADC Core x is powered and ready for operation

0= Common interrupt is disabled for an ADC Core x ready event

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REGISTER 19-11: ADCORExL: DEDICATED ADC CORE x CONTROL REGISTER LOW (x = 0,1)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

SAMC<9:8>

bit 15

R/W-0

bit 7

Legend:

bit 8

R/W-0

bit 0

R/W-0

SAMC<7:0>

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-10

bit 9-0

Unimplemented: Read as ‘0’

SAMC<9:0>: Dedicated ADC Core x Conversion Delay Selection bits

These bits determine the time between the trigger event and the start of conversion in the number of the

ADC Core Clock (TADCORE) periods. During this time, the ADC Core x still continues sampling. This

feature is enabled by the SAMCxEN bit in the ADCON4L register.

1111111111= 1025 TADCORE

•

0000000001= 3 TADCORE

0000000000= 2 TADCORE

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REGISTER 19-12: ADCORExH: DEDICATED ADC CORE x CONTROL REGISTER HIGH (x = 0,1)

U-0

—

U-0

—

U-0

—

R/W-0

R/W-1

RES1

R/W-1

RES0

(1)

EISEL2

EISEL1

EISEL0

bit 15

bit 8

U-0

—

R/W-0

ADCS6

ADCS5

ADCS4

ADCS3

ADCS2

ADCS1

ADCS0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-13

bit 12-10

Unimplemented: Read as ‘0’

EISEL<2:0>: ADC Core x Early Interrupt Time Selection bits

(1)

111= Early interrupt is set and an interrupt is generated 8 TADCORE clocks prior to when the data is ready

110= Early interrupt is set and an interrupt is generated 7 TADCORE clocks prior to when the data is ready

101= Early interrupt is set and an interrupt is generated 6 TADCORE clocks prior to when the data is ready

100= Early interrupt is set and an interrupt is generated 5 TADCORE clocks prior to when the data is ready

011= Early interrupt is set and an interrupt is generated 4 TADCORE clocks prior to when the data is ready

010= Early interrupt is set and an interrupt is generated 3 TADCORE clocks prior to when the data is ready

001= Early interrupt is set and an interrupt is generated 2 TADCORE clocks prior to when the data is ready

000= Early interrupt is set and an interrupt is generated 1 TADCORE clock prior to when the data is ready

bit 9-8

RES<1:0>: ADC Core x Resolution Selection bits

11= 12-bit resolution

10= 10-bit resolution

01= 8-bit resolution

00= 6-bit resolution

bit 7

Unimplemented: Read as ‘0’

bit 6-0

ADCS<6:0>: ADC Core x Input Clock Divider bits

These bits determine the number of Core Source Clock (TCORESRC) periods for one ADC Core Clock

(TADCORE) period.

1111111= 254 Core Source Clock periods

•

0000011= 6 Core Source Clock periods

0000010= 4 Core Source Clock periods

0000001= 2 Core Source Clock periods

0000000= 2 Core Source Clock periods

Note 1: For the 6-bit ADC core resolution (RES<1:0> = 00), the EISEL<2:0> bits settings, from ‘100’ to ‘111’, are

not valid and should not be used. For the 8-bit ADC core resolution (RES<1:0> = 01), the EISEL<2:0> bits

settings, ‘110’ and ‘111’, are not valid and should not be used.

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REGISTER 19-13: ADLVLTRGL: ADC LEVEL-SENSITIVE TRIGGER CONTROL REGISTER LOW

U-0

—

R/W-0

bit 8

R/W-0

bit 0

LVLEN<14:8>

bit 15

R/W-0

bit 7

Legend:

R/W-0

LVLEN<7:0>

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

LVLEN<14:0>: Level Trigger x Enable bits

bit 14-0

1= Input Channel x trigger is level-sensitive

0= Input Channel x trigger is edge-sensitive

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REGISTER 19-14: ADEIEL: ADC EARLY INTERRUPT ENABLE REGISTER LOW

U-0

—

R/W-0

bit 8

R/W-0

bit 0

EIEN<14:8>

bit 15

R/W-0

bit 7

Legend:

R/W-0

EIEN<7:0>

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-0

EIEN<14:0>: Early Interrupt Enable for Corresponding Analog Inputs bits

1= Early interrupt is enabled for the channel

0= Early interrupt is disabled for the channel

REGISTER 19-15: ADEISTATL: ADC EARLY INTERRUPT STATUS REGISTER LOW

U-0

—

R/W-0

bit 8

R/W-0

bit 0

EISTAT<14:8>

bit 15

R/W-0

bit 7

Legend:

R/W-0

EISTAT<7:0>

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-0

EISTAT<14:0>: Early Interrupt Status for Corresponding Analog Inputs bits

1= Early interrupt was generated

0= Early interrupt was not generated since the last ADCBUFx read

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REGISTER 19-16: ADMOD0L: ADC INPUT MODE CONTROL REGISTER 0 LOW

U-0

—

R/W-0

SIGN7

U-0

—

R/W-0

SIGN6

U-0

—

R/W-0

SIGN5

U-0

—

R/W-0

SIGN4

bit 15

bit 8

U-0

—

R/W-0

SIGN3

U-0

—

R/W-0

SIGN2

R/W-0

SIGN1

R/W-0

SIGN0

(2)

(1)

DIFF1

DIFF0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit (odd)15-5 Unimplemented: Read as ‘0’

(1,2)

bit (3,1)

DIFF<x>: Pseudodifferential Mode for Corresponding Analog Inputs bits

1= Channel is pseudodifferential

0= Channel is single-ended

bit (even)

SIGNx: Output Data Sign for Corresponding Analog Inputs bits

1= Channel output data is signed

0= Channel output data is unsigned

Note 1: AN7 is a negative input when DIFF0 = 1.

2: AN8 is a negative input when DIFF1 = 1.

REGISTER 19-17: ADMOD0H: ADC INPUT MODE CONTROL REGISTER 0 HIGH

U-0

—

U-0

—

U-0

—

R/W-0

U-0

—

R/W-0

U-0

—

R/W-0

SIGN14

SIGN13

SIGN12

bit 15

bit 8

U-0

—

R/W-0

U-0

—

R/W-0

U-0

—

R/W-0

SIGN9

U-0

—

R/W-0

SIGN8

SIGN11

SIGN10

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit (odd)

bit (even)

Unimplemented: Read as ‘0’

SIGN<x>: Output Data Sign for Corresponding Analog Inputs bits

1= Channel output data is signed

0= Channel output data is unsigned

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REGISTER 19-18: ADIEL: ADC INTERRUPT ENABLE REGISTER LOW

U-0

—

R/W-0

bit 8

R/W-0

bit 0

IE<14:8>

bit 15

R/W-0

bit 7

Legend:

R/W-0

IE<7:0>

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

IE<14:0>: Common Interrupt Enable bits

bit 14-0

1= Common and individual interrupts are enabled for the corresponding channel

0= Common and individual interrupts are disabled for the corresponding channel

REGISTER 19-19: ADSTATL: ADC DATA READY STATUS REGISTER LOW

U-0

—

R-0, HSC

bit 8

R-0, HSC

bit 0

AN<14:8>RDY

bit 15

R-0, HSC

bit 7

Legend:

R-0, HSC

AN<7:0>RDY

HSC = Hardware Settable bit/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-0

AN<14:0>RDY: ADC Conversion Data Ready for Corresponding Analog Input bits

1= Channel conversion result is ready in the corresponding ADCBUFx register

0= Channel conversion result is not ready

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REGISTER 19-20: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW

(x = 0 to 3)

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

TRGSRC(4x+1)<4:0>

bit 15

U-0

—

U-0

—

U-0

—

R/W-0

TRGSRC(4x)<4:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

TRGSRC(4x+1)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits

11111= ADTRG31

11110= Reserved

11101= Reserved

11100= Reserved

11011= Reserved

11010= PWM Generator 3 current-limit trigger

11001= PWM Generator 2 current-limit trigger

11000= PWM Generator 1 current-limit trigger

10111= Reserved

10110= Output Compare 1 trigger

10101= Reserved

10100= Reserved

10011= Reserved

10010= Reserved

10001= PWM Generator 3 secondary trigger

10000= PWM Generator 2 secondary trigger

01111= PWM Generator 1 secondary trigger

01110= PWM secondary Special Event Trigger

01101= Timer2 period match

01100= Timer1 period match

01011= Reserved

01010= Reserved

01001= Reserved

01000= Reserved

00111= PWM Generator 3 primary trigger

00110= PWM Generator 2 primary trigger

00101= PWM Generator 1 primary trigger

00100= PWM Special Event Trigger

00011= Reserved

00010= Level software trigger

00001= Common software trigger

00000= No trigger is enabled

bit 7-5

Unimplemented: Read as ‘0’

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REGISTER 19-20: ADTRIGxL: ADC CHANNEL TRIGGER x SELECTION REGISTER LOW

(x = 0 to 3) (CONTINUED)

bit 4-0

TRGSRC(4x)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits

11111= ADTRG31

11110= Reserved

11101= Reserved

11100= Reserved

11011= Reserved

11010= PWM Generator 3 current-limit trigger

11001= PWM Generator 2 current-limit trigger

11000= PWM Generator 1 current-limit trigger

10111= Reserved

10110= Output Compare 1 trigger

10101= Reserved

10100= Reserved

10011= Reserved

10010= Reserved

10001= PWM Generator 3 secondary trigger

10000= PWM Generator 2 secondary trigger

01111= PWM Generator 1 secondary trigger

01110= PWM secondary Special Event Trigger

01101= Timer2 period match

01100= Timer1 period match

01011= Reserved

01010= Reserved

01001= Reserved

01000= Reserved

00111= PWM Generator 3 primary trigger

00110= PWM Generator 2 primary trigger

00101= PWM Generator 1 primary trigger

00100= PWM Special Event Trigger

00011= Reserved

00010= Level software trigger

00001= Common software trigger

00000= No trigger is enabled

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REGISTER 19-21: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH

(x = 0 to 3)

U-0

—

U-0

—

U-0

—

R/W-0

TRGSRC(4x+3)<4:0>

bit 15

bit 8

bit 0

U-0

—

U-0

—

U-0

—

R/W-0

TRGSRC(4x+2)<4:0>

bit 7

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

TRGSRC(4x+3)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits

11111= ADTRG31

11110= Reserved

11101= Reserved

11100= Reserved

11011= Reserved

11010= PWM Generator 3 current-limit trigger

11001= PWM Generator 2 current-limit trigger

11000= PWM Generator 1 current-limit trigger

10111= Reserved

10110= Output Compare 1 trigger

10101= Reserved

10100= Reserved

10011= Reserved

10010= Reserved

10001= PWM Generator 3 secondary trigger

10000= PWM Generator 2 secondary trigger

01111= PWM Generator 1 secondary trigger

01110= PWM secondary Special Event Trigger

01101= Timer2 period match

01100= Timer1 period match

01011= Reserved

01010= Reserved

01001= Reserved

01000= Reserved

00111= PWM Generator 3 primary trigger

00110= PWM Generator 2 primary trigger

00101= PWM Generator 1 primary trigger

00100= PWM Special Event Trigger

00011= Reserved

00010= Level software trigger

00001= Common software trigger

00000= No trigger is enabled

bit 7-5

Unimplemented: Read as ‘0’

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REGISTER 19-21: ADTRIGxH: ADC CHANNEL TRIGGER x SELECTION REGISTER HIGH

(x = 0 to 3) (CONTINUED)

bit 4-0

TRGSRC(4x+2)<4:0>: Trigger Source Selection for Corresponding Analog Inputs bits

11111= ADTRG31

11110= Reserved

11101= Reserved

11100= Reserved

11011= Reserved

11010= PWM Generator 3 current-limit trigger

11001= PWM Generator 2 current-limit trigger

11000= PWM Generator 1 current-limit trigger

10111= Reserved

10110= Output Compare 1 trigger

10101= Reserved

10100= Reserved

10011= Reserved

10010= Reserved

10001= PWM Generator 3 secondary trigger

10000= PWM Generator 2 secondary trigger

01111= PWM Generator 1 secondary trigger

01110= PWM secondary Special Event Trigger

01101= Timer2 period match

01100= Timer1 period match

01011= Reserved

01010= Reserved

01001= Reserved

01000= Reserved

00111= PWM Generator 3 primary trigger

00110= PWM Generator 2 primary trigger

00101= PWM Generator 1 primary trigger

00100= PWM Special Event Trigger

00011= Reserved

00010= Level software trigger

00001= Common software trigger

00000= No trigger is enabled

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REGISTER 19-22: ADCAL0L: ADC CALIBRATION REGISTER 0 LOW

R-0, HSC

CAL1RDY

bit 15

U-0

—

U-0

—

U-0

—

r-0

—

R/W-0

CAL1RUN

bit 8

CAL1DIFF

CAL1EN

R-0, HSC

CAL0RDY

bit 7

U-0

—

U-0

—

U-0

—

r-0

—

R/W-0

CAL0RUN

bit 0

CAL0DIFF

CAL0EN

Legend:

r = Reserved bit

W = Writable bit

‘1’ = Bit is set

HSC= Hardware Settable/Clearable bit

U = Unimplemented bit, read as ‘0’

R = Readable bit

-n = Value at POR

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

CAL1RDY: Dedicated ADC Core 1 Calibration Status Flag bit

1= Dedicated ADC Core 1 calibration is finished

0= Dedicated ADC Core 1 calibration is in progress

bit 14-12

bit 11

Unimplemented: Read as ‘0’

Reserved: Must be written as ‘0’

bit 10

CAL1DIFF: Dedicated ADC Core 1 Pseudodifferential Input Mode Calibration bit

1= Dedicated ADC Core 1 will be calibrated in Pseudodifferential Input mode

0= Dedicated ADC Core 1 will be calibrated in Single-Ended Input mode

bit 9

bit 8

bit 7

CAL1EN: Dedicated ADC Core 1 Calibration Enable bit

1= Dedicated ADC Core 1 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by

software

0= Dedicated ADC Core 1 calibration bits are disabled

CAL1RUN: Dedicated ADC Core 1 Calibration Start bit

1= If this bit is set by software, the dedicated ADC Core 1 calibration cycle is started; this bit is

automatically cleared by hardware

0= Software can start the next calibration cycle

CAL0RDY: Dedicated ADC Core 0 Calibration Status Flag bit

1= Dedicated ADC Core 0 calibration is finished

0= Dedicated ADC Core 0 calibration is in progress

bit 6-4

bit 3

Unimplemented: Read as ‘0’

Reserved: Must be written as ‘0’

bit 2

CAL0DIFF: Dedicated ADC Core 0 Pseudodifferential Input Mode Calibration bit

1= Dedicated ADC Core 0 will be calibrated in Pseudodifferential Input mode

0= Dedicated ADC Core 0 will be calibrated in Single-Ended Input mode

bit 1

bit 0

CAL0EN: Dedicated ADC Core 0 Calibration Enable bit

1= Dedicated ADC Core 0 calibration bits (CALxRDY, CALxDIFF and CALxRUN) can be accessed by

software

0= Dedicated ADC Core 0 calibration bits are disabled

CAL0RUN: Dedicated ADC Core 0 Calibration Start bit

1= If this bit is set by software, the dedicated ADC Core 0 calibration cycle is started; this bit is

automatically cleared by hardware

0= Software can start the next calibration cycle

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REGISTER 19-23: ADCAL1H: ADC CALIBRATION REGISTER 1 HIGH

R/W-0, HS

CSHRRDY

bit 15

U-0

—

U-0

—

U-0

—

r-0

—

U-0

—

R/W-0

CSHRRUN

bit 8

CSHREN

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 7

bit 0

Legend:

HS = Hardware Settable bit

W = Writable bit

r = Reserved bit

R = Readable bit

-n = Value at POR

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

‘1’ = Bit is set

bit 15

CSHRRDY: Shared ADC Core Calibration Status Flag bit

1= Shared ADC core calibration is finished

0= Shared ADC core calibration is in progress

bit 14-12

bit 11

Unimplemented: Read as ‘0’

Reserved: Must be written as ‘0’

Unimplemented: Read as ‘0’

bit 10

bit 9

CSHREN: Shared ADC Core Calibration Enable bit

1= Shared ADC core calibration bits (CSHRRDY and CSHRRUN) can be accessed by software

0= Shared ADC core calibration bits are disabled

bit 8

CSHRRUN: Shared ADC Core Calibration Start bit

1= If this bit is set by software, the shared ADC core calibration cycle is started; this bit is cleared auto-

matically by hardware

0= Software can start the next calibration cycle

bit 7-0

Unimplemented: Read as ‘0’

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REGISTER 19-24: ADCMPxCON: ADC DIGITAL COMPARATOR x CONTROL REGISTER (x = 0,1)

U-0

—

U-0

—

U-0

—

R-0, HSC

CHNL4

R-0, HSC

CHNL3

R-0, HSC

CHNL2

R-0, HSC

CHNL1

R-0, HSC

CHNL0

bit 15

bit 8

R/W/0

R/W-0

IE

R-0, HC, HS

STAT

R/W-0

BTWN

R/W-0

HIHI

R/W-0

HILO

R/W-0

LOHI

R/W-0

LOLO

CMPEN

bit 7

bit 0

Legend:

HS = Hardware Settable bit HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared HC = Hardware Clearable bit

bit 15-13

bit 12-8

Unimplemented: Read as ‘0’

CHNL<4:0>: Input Channel Number bits

If the comparator has detected an event for a channel, this channel number is written to these bits.

01111-11111= Reserved

01110 = BG (AN14)

01101 = PGA2 (AN13)

01100 = PGA1 (AN12)

•

00001= AN1

00000= AN0

bit 7

bit 6

bit 5

CMPEN: Digital Comparator Enable bit

1= Digital comparator is enabled

0= Digital comparator is disabled and the STAT status bit is cleared

IE: Comparator Common ADC Interrupt Enable bit

1= Common ADC interrupt will be generated if the comparator detects a comparison event

0= Common ADC interrupt will not be generated for the comparator

STAT: Comparator Event Status bit

This bit is cleared by hardware when the channel number is read from the CHNL<4:0> bits.

1= A comparison event has been detected since the last read of the CHNL<4:0> bits

0= A comparison event has not been detected since the last read of the CHNL<4:0> bits

bit 4

bit 3

bit 2

bit 1

bit 0

BTWN: Between Low/High Comparator Event bit

1= Generates a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI

0= Does not generate a digital comparator event when ADCMPxLO ≤ ADCBUFx < ADCMPxHI

HIHI: High/High Comparator Event bit

1= Generates a digital comparator event when ADCBUFx ≥ ADCMPxHI

0= Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxHI

HILO: High/Low Comparator Event bit

1= Generates a digital comparator event when ADCBUFx < ADCMPxHI

0= Does not generate a digital comparator event when ADCBUFx < ADCMPxHI

LOHI: Low/High Comparator Event bit

1= Generates a digital comparator event when ADCBUFx ≥ ADCMPxLO

0= Does not generate a digital comparator event when ADCBUFx ≥ ADCMPxLO

LOLO: Low/Low Comparator Event bit

1= Generates a digital comparator event when ADCBUFx < ADCMPxLO

0= Does not generate a digital comparator event when ADCBUFx < ADCMPxLO

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REGISTER 19-25: ADCMPxENL: ADC DIGITAL COMPARATOR x CHANNEL ENABLE REGISTER

LOW (x = 0,1)

U-0

—

R/W-0

CMPEN<14:8>

bit 15

R/W/0

bit 7

Legend:

bit 8

bit 0

R/W-0

CMPEN<7:0>

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

Unimplemented: Read as ‘0’

bit 14-0

CMPEN<14:0>: Comparator Enable for Corresponding Input Channels bits

1= Conversion result for corresponding channel is used by the comparator

0= Conversion result for corresponding channel is not used by the comparator

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REGISTER 19-26: ADFL0CON: ADC DIGITAL FILTER 0 CONTROL REGISTER

R/W-0

FLEN

R/W-0

IE

R-0, HSC

RDY

MODE1

MODE0

OVRSAM2

OVRSAM1

OVRSAM0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

R/W-0

FLCHSEL4

FLCHSEL3

FLCHSEL2

FLCHSEL1 FLCHSEL0

bit 0

bit 7

Legend:

HSC = Hardware Settable/Clearable bit

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

FLEN: Filter Enable bit

1= Filter is enabled

0= Filter is disabled and the RDY bit is cleared

bit 14-13

MODE<1:0>: Filter Mode bits

11= Averaging mode

10= Reserved

01= Reserved

00= Oversampling mode

bit 12-10

OVRSAM<2:0>: Filter Averaging/Oversampling Ratio bits

If MODE<1:0> = 00:

111= 128x (16-bit result in the ADFL0DAT register is in 12.4 format)

110= 32x (15-bit result in the ADFL0DAT register is in 12.3 format)

101= 8x (14-bit result in the ADFL0DAT register is in 12.2 format)

100= 2x (13-bit result in the ADFL0DAT register is in 12.1 format)

011= 256x (16-bit result in the ADFL0DAT register is in 12.4 format)

010= 64x (15-bit result in the ADFL0DAT register is in 12.3 format)

001= 16x (14-bit result in the ADFL0DAT register is in 12.2 format)

000= 4x (13-bit result in the ADFL0DAT register is in 12.1 format)

If MODE<1:0> = 11(12-bit result in the ADFL0DAT register):

111= 256x

110= 128x

101= 64x

100= 32x

011= 16x

010= 8x

001= 4x

000= 2x

bit 9

bit 8

IE: Filter Common ADC Interrupt Enable bit

1= Common ADC interrupt will be generated when the filter result will be ready

0= Common ADC interrupt will not be generated for the filter

RDY: Oversampling Filter Data Ready Flag bit

This bit is cleared by hardware when the result is read from the ADFL0DAT register.

1= Data in the ADFL0DAT register is ready

0= The ADFL0DAT register has been read and new data in the ADFL0DAT register is not ready

bit 7-5

Unimplemented: Read as ‘0’

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REGISTER 19-26: ADFL0CON: ADC DIGITAL FILTER 0 CONTROL REGISTER (CONTINUED)

bit 4-0

FLCHSEL<4:0>: Oversampling Filter Input Channel Selection bits

01111-11111= Reserved

01110= BG (AN14)

01101= PGA2 (AN13)

01100= PGA1 (AN12)

•

00001= AN1

00000= AN0

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NOTES:

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20.1 Features Overview

20.0 HIGH-SPEED ANALOG

COMPARATOR

The SMPS comparator module offers the following

major features:

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “High-Speed Analog

Comparator Module” (DS70005128) in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

• Two Rail-to-Rail Analog Comparators

• Dedicated 12-Bit DAC for each Analog

Comparator

• Up to Six Selectable Input Sources per

Comparator:

- Four external inputs

- Two internal inputs from the PGAx module

• Programmable Comparator Hysteresis

• Programmable Output Polarity

• Voltage References for the DACx:

- AVDD

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• Interrupt Generation Capability

• Functional Support for PWM:

- PWM duty cycle control

The high-speed analog comparator module monitors

current and/or voltage transients that may be too fast

for the CPU and ADC to capture.

- PWM period control

- PWM Fault detected

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The analog comparator input pins are typically shared

20.2 Module Description

with pins used by the Analog-to-Digital Converter

(ADC) module. Both the comparator and the ADC can

use the same pins at the same time. This capability

enables a user to measure an input voltage with the

ADC and detect voltage transients with the

comparator.

Figure 20-1 shows a functional block diagram of one

analog comparator from the high-speed analog

comparator module. The analog comparator provides

high-speed operation with a typical delay of 15 ns. The

negative input of the comparator is always connected

to the DACx circuit. The positive input of the compara-

tor is connected to an analog multiplexer that selects

the desired source pin.

FIGURE 20-1:

HIGH-SPEED ANALOG COMPARATOR x MODULE BLOCK DIAGRAM

INSEL<1:0>

ALTINP

PWM Trigger

(remappable I/O)

PGA1OUT

PGA2OUT

(1)

CMPxA

Status

(1)

CMPx⁽¹⁾

CMPxB

0

1

Pulse Stretcher

and

Digital Filter

(1)

CMPxC

(1)

CMPxD

Interrupt

Request

CMPPOL

(1)

AVDD

DACx

12

CMREF<11:0>

Note 1: x = 1-2

DS70005208E-page 228

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20.3 Module Applications

20.4 DAC

®

This module provides a means for the SMPS dsPIC

DSC devices to monitor voltage and currents in a

power conversion application. The ability to detect

transient conditions, and stimulate the dsPIC DSC

processor and/or peripherals, without requiring the

processor and ADC to constantly monitor voltages or

currents, frees the dsPIC DSC to perform other tasks.

Each analog comparator has a dedicated 12-bit DAC

that is used to program the comparator threshold voltage

via the CMPxDAC register.

20.5 Pulse Stretcher and Digital Logic

The analog comparator can respond to very fast

transient signals. After the comparator output is given

the desired polarity, the signal is passed to a pulse

stretching circuit. The pulse stretching circuit has an

asynchronous set function and a delay circuit that

ensures the minimum pulse width is three system clock

cycles wide to allow the attached circuitry to properly

respond to a narrow pulse event.

The comparator module has a high-speed comparator

and an associated 12-bit DAC that provides a pro-

grammable reference voltage to the inverting input of

the comparator. The polarity of the comparator output

is user-programmable. The output of the module can

be used in the following modes:

• Generate an Interrupt

The pulse stretcher circuit is followed by a digital filter.

The digital filter is enabled via the FLTREN bit in the

CMPxCON register. The digital filter operates with the

clock specified via the FCLKSEL bit in the CMPxCON

register. The comparator signal must be stable in a high

or low state, for at least three of the selected clock

cycles, for it to pass through the digital filter.

• Trigger an ADC Sample and Convert Process

• Truncate the PWM Signal (current-limit)

• Truncate the PWM Period (current minimum)

• Disable the PWM Outputs (Fault latch)

The output of the comparator module may be used in

multiple modes at the same time, such as: 1) Generate

an interrupt, 2) Have the ADC take a sample and con-

vert it, and 3) Truncate the PWM output in response to a

voltage being detected beyond its expected value.

The comparator module can also be used to wake-up the

system from Sleep or Idle mode when the analog input

voltage exceeds the programmed threshold voltage.

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20.6 Hysteresis

20.7 Analog Comparator Resources

An additional feature of the module is hysteresis con-

trol. Hysteresis can be enabled or disabled and its

amplitude can be controlled by the HYSSEL<1:0> bits

in the CMPxCON register. Three different values are

available: 5 mV, 10 mV and 20 mV. It is also possible to

select the edge (rising or falling) to which hysteresis is

to be applied.

Many useful resources are provided on the main

product page of the Microchip web site for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

20.7.1

KEY RESOURCES

•

“High-Speed Analog Comparator Module”

(DS70005128) in the “dsPIC33/PIC24 Family

Reference Manual”

Hysteresis control prevents the comparator output from

continuously changing state because of small

perturbations (noise) at the input (see Figure 20-2).

• Code Samples

• Application Notes

• Software Libraries

• Webinars

FIGURE 20-2:

HYSTERESIS CONTROL

Output

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

Hysteresis Range

(5 mV/10 mV/20 mV)

Input

DS70005208E-page 230

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20.8 High-Speed Analog Comparator Control Registers

REGISTER 20-1: CMPxCON: COMPARATOR x CONTROL REGISTER (x =

1,2)

R/W-0

U-0

—

R/W-0

U-0

—

CMPON

CMPSIDL

HYSSEL1

HYSSEL0

FLTREN

FCLKSEL

bit 15

bit 8

bit 0

R/W-0

U-0

—

R/W-0

HC/HS-0

R/W-0

U-0

—

INSEL1

INSEL0

HYSPOL

CMPSTAT

ALTINP

CMPPOL

bit 7

Legend:

HC = Hardware Clearable bit HS = Hardware Settable bit

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 15

CMPON: Comparator Operating Mode bit

1= Comparator module is enabled

0= Comparator module is disabled (reduces power consumption)

bit 14

bit 13

Unimplemented: Read as ‘0’

CMPSIDL: Comparator Stop in Idle Mode bit

1= Discontinues module operation when device enters Idle mode.

0= Continues module operation in Idle mode

If a device has multiple comparators, any CMPSIDL bit set to ‘1’ disables all comparators while in Idle mode.

bit 12-11

HYSSEL<1:0>: Comparator Hysteresis Select bits

11= 20 mV hysteresis

10= 10 mV hysteresis

01= 5 mV hysteresis

00= No hysteresis is selected

bit 10

bit 9

FLTREN: Digital Filter Enable bit

1= Digital filter is enabled

0= Digital filter is disabled

FCLKSEL: Digital Filter and Pulse Stretcher Clock Select bit

1= Digital filter and pulse stretcher operate with the PWM clock

0= Digital filter and pulse stretcher operate with the system clock

bit 8

Unimplemented: Read as ‘0’

bit 7-6

INSEL<1:0>: Input Source Select for Comparator bits

If ALTINP = 0, Select from Comparator Inputs:

11= Selects CMPxD input pin

10= Selects CMPxC input pin

01= Selects CMPxB input pin

00= Selects CMPxA input pin

If ALTINP = 1, Select from Alternate Inputs:

11= Reserved

10= Reserved

01= Selects PGA2 output

00= Selects PGA1 output

bit 5

bit 4

Unimplemented: Read as ‘0’

HYSPOL: Comparator Hysteresis Polarity Select bit

1= Hysteresis is applied to the falling edge of the comparator output

0= Hysteresis is applied to the rising edge of the comparator output

bit 3

CMPSTAT: Current State of Comparator Output Including CMPPOL Selection bit

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REGISTER 20-1: CMPxCON: COMPARATOR x CONTROL REGISTER (x = 1,2) (CONTINUED)

bit 2

bit 1

bit 0

ALTINP: Alternate Input Select bit

1= INSEL<1:0> bits select alternate inputs

0= INSEL<1:0> bits select comparator inputs

CMPPOL: Comparator Output Polarity Control bit

1= Output is inverted

0= Output is non-inverted

Unimplemented: Read as ‘0’

REGISTER 20-2: CMPxDAC: COMPARATOR DACx CONTROL REGISTER (x = 1,2)

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

bit 8

R/W-0

bit 0

CMREF<11:8>

bit 15

R/W-0

bit 7

R/W-0

CMREF<7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-12

bit 11-0

Unimplemented: Read as ‘0’

CMREF<11:0>: Comparator Reference Voltage Select bits

111111111111= (CMREF<11:0> * (AVDD)/4096)

•

000000000000= 0.0 volts

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The dsPIC33EPXXGS202 family devices have two

Programmable Gain Amplifiers (PGA1, PGA2). The

PGA is an op amp-based, non-inverting amplifier with

user-programmable gains. The output of the PGA can

be connected to a number of dedicated Sample-and-

Hold inputs of the Analog-to-Digital Converter and/or to

the high-speed analog comparator module. The PGA

has five selectable gains and may be used as a ground

referenced amplifier (single-ended) or used with an

independent ground reference point.

21.0 PROGRAMMABLE GAIN

AMPLIFIER (PGA)

Note 1: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to “Programmable Gain

Amplifier (PGA)” (DS70005146) in the

“dsPIC33/PIC24 Family Reference Man-

ual”, which is available from the Microchip

web site (www.microchip.com).

Key features of the PGA module include:

• Single-Ended or Independent Ground Reference

• Selectable Gains: 4x, 8x, 16x, 32x and 64x

• High Gain Bandwidth

2: Some registers and associated bits

described in this section may not be

available on all devices. Refer to

Section 4.0 “Memory Organization” in

this data sheet for device-specific register

and bit information.

• Rail-to-Rail Output Voltage

• Wide Input Voltage Range

FIGURE 21-1:

PGAx MODULE BLOCK DIAGRAM

GAIN<2:0> = 6

GAIN<2:0> = 5

Gain of 64

Gain of 32

GAIN<2:0> = 4

GAIN<2:0> = 3

Gain of 16

Gain of 8

GAIN<2:0> = 2

Gain of 4

–

PGAx Negative Input

PGAxOUT

AMPx

+

PGAx Positive Input

PGAx Calibrations<5:0> bits

Note 1: x = 1 and 2.

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The gain of the PGAx module is selectable via the

21.1 Module Description

GAIN<2:0> bits in the PGAxCON register. There are

five selectable gains, ranging from 4x to 64x. The

SELPI<2:0> and SELNI<2:0> bits in the PGAxCON

register select one of three positive/negative inputs to

the PGAx module. For single-ended applications, the

SELNI<2:0> bits will select ground as the negative

input source. To provide an independent ground

reference, the PGAxN2 pin is available as the negative

input source to the PGAx module.

The programmable gain amplifiers are used to amplify

small voltages (e.g., voltages across burden/shunt

resistors) to improve the signal-to-noise ratio of the

measured signal. The PGAx output voltage can be

read by the two dedicated Sample-and-Hold circuits on

the ADC module. The output voltage can also be fed to

the comparator module for overcurrent/voltage protec-

tion. Figure 21-2 shows a functional block diagram of

the PGAx module. Refer to Section 19.0 “High-

Speed, 12-Bit Analog-to-Digital Converter (ADC)”

and Section 20.0 “High-Speed Analog Comparator”

for more interconnection details.

FIGURE 21-2:

PGAx FUNCTIONAL BLOCK DIAGRAM

INSEL<1:0>

(CMPxCON)

SELPI<2:0>

(1)

PGAxCON

PGAxCAL

+

PGAEN GAIN<2:0>

PGACAL<5:0>

–

(1)

PGAxP1

DACx

(1)

PGAxP2

(1)

CxCHS<1:0>

(ADCON4H)

PGAxP3

ADC

S&H

+

(1)

PGAx

GND

–

(1)

PGAxN2

GND

SELNI<2:0>

Note 1: x = 1, 2.

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21.2.1

KEY RESOURCES

21.2 PGA Resources

•

“Programmable Gain Amplifier (PGA)”

(DS70005146) in the “dsPIC33/PIC24 Family

Reference Manual”

Many useful resources are provided on the main

product page of the Microchip website for the devices

listed in this data sheet. This product page contains the

latest updates and additional information.

• Code Samples

• Application Notes

• Software Libraries

• Webinars

• All Related “dsPIC33/PIC24 Family Reference

Manual” Sections

• Development Tools

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21.3 PGA Control Registers

REGISTER 21-1: PGAxCON: PGAx CONTROL REGISTER (x = 1,2)

R/W-0

U-0

—

R/W-0

PGAEN

SELPI2

SELPI1

SELPI0

SELNI2

SELNI1

SELNI0

bit 15

bit 8

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

R/W-0

GAIN2

R/W-0

GAIN1

R/W-0

GAIN0

bit 7

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15

PGAEN: PGAx Enable bit

1= PGAx module is enabled

0= PGAx module is disabled (reduces power consumption)

bit 14

Unimplemented: Read as ‘0’

bit 13-11

SELPI<2:0>: PGAx Positive Input Selection bits

111= Reserved

110= Reserved

101= Reserved

100= Reserved

011= Reserved

010= PGAxP3

001= PGAxP2

000= PGAxP1

bit 10-8

SELNI<2:0>: PGAx Negative Input Selection bits

111= Reserved

110= Reserved

101= Reserved

100= Reserved

011= Ground (Single-Ended mode)

010= Reserved

001= PGAxN2

000= Ground (Single-Ended mode)

bit 7-3

bit 2-0

Unimplemented: Read as ‘0’

GAIN<2:0>: PGAx Gain Selection bits

111= Reserved

110= Gain of 64

101= Gain of 32

100= Gain of 16

011= Gain of 8

010= Gain of 4

001= Reserved

000= Reserved

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REGISTER 21-2: PGAxCAL: PGAx CALIBRATION REGISTER (x = 1,2)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

bit 15

bit 8

R/W-0

bit 0

U-0

—

U-0

—

R/W-0

PGACAL<5:0>

bit 7

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 15-6

bit 5-0

Unimplemented: Read as ‘0’

PGACAL<5:0>: PGAx Offset Calibration bits

The calibration values for PGA1 and PGA2 must be copied from Flash addresses, 0x800E48 and

0x800E4C, respectively, into these bits before the module is enabled. Refer to the Device Calibration

Addresses table (Table 22-3) in Section 22.0 “Special Features” for more information.

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22.1 Configuration Bits

22.0 SPECIAL FEATURES

In the dsPIC33EPXXGS202 family devices, the

Note: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be a

comprehensive reference source. To

complement the information in this data

sheet, refer to the related section in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

Configuration Words are implemented as volatile

memory. This means that configuration data must be

programmed each time the device is powered up.

Configuration data is stored at the end of the on-chip

program memory space, known as the Flash Configu-

ration Words. Their specific locations are shown in

Table 22-1 with detailed descriptions in Table 22-2. The

configuration data is automatically loaded from the

Flash Configuration Words to the proper Configuration

Shadow registers during device Resets.

The dsPIC33EPXXGS202 family devices include

several features intended to maximize application

flexibility and reliability, and minimize cost through

elimination of external components. These are:

Note:

Configuration data is reloaded on all types

of device Resets.

When creating applications for these devices, users

should always specifically allocate the location of the

Flash Configuration Words for configuration data in

their code for the compiler. This is to make certain that

program code is not stored in this address when the

code is compiled. Program code executing out of

configuration space will cause a device Reset.

• Flexible Configuration

• Watchdog Timer (WDT)

• Code Protection and CodeGuard™ Security

• JTAG Boundary Scan Interface

• In-Circuit Serial Programming™ (ICSP™)

• In-Circuit Emulation

• Brown-out Reset (BOR)

Note:

Performing a page erase operation on the

last page of program memory clears the

Flash Configuration Words.

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TABLE 22-2: CONFIGURATION BITS DESCRIPTION

Bit Field

BSS<1:0>

Description

Boot Segment Code-Protect Level bits

11= Boot Segment is not code-protected other than BWRP

10= Standard security

0x= High security

BSEN

Boot Segment Control bit

1= No Boot Segment is enabled

0= Boot Segment size is determined by the BSLIM<12:0> bits

BWRP

Boot Segment Write-Protect bit

1= Boot Segment can be written

0= Boot Segment is write-protected

BSLIM<12:0>

Boot Segment Flash Page Address Limit bits

Contains the last active Boot Segment page. The value to be programmed is the inverted

page address, such that programming additional ‘0’s can only increase the Boot Segment

size (i.e., 0x1FFD = 2 Pages or 1024 IW).

GSS<1:0>

General Segment Code-Protect Level bits

11= User program memory is not code-protected

10= Standard security

0x= High security

GWRP

General Segment Write-Protect bit

1= User program memory is not write-protected

0= User program memory is write-protected

CWRP

Configuration Segment Write-Protect bit

1= Configuration data is not write-protected

0= Configuration data is write protected

CSS<2:0>

Configuration Segment Code-Protect Level bits

111= Configuration data is not code-protected

110= Standard security

10x= Enhanced security

0xx= High security

(1)

AIVTDIS

Alternate Interrupt Vector Table bit

1= Alternate Interrupt Vector Table is disabled

0= Alternate Interrupt Vector Table is enabled if INTCON2<8> = 1

IESO

Two-Speed Oscillator Start-up Enable bit

1= Starts up device with FRC, then automatically switches to the user-selected oscillator

source when ready

0= Starts up device with the user-selected oscillator source

PWMLOCK

PWM Lock Enable bit

1= Certain PWM registers may only be written after a key sequence

0= PWM registers may be written without a key sequence

Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.

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TABLE 22-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

FNOSC<2:0>

Description

Oscillator Selection bits

111= Fast RC Oscillator with Divide-by-N (FRCDIVN)

110= Fast RC Oscillator with Divide-by-16

101= Low-Power RC Oscillator (LPRC)

100= Reserved; do not use

011= Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL)

010= Primary Oscillator (XT, HS, EC)

001= Fast RC Oscillator with Divide-by-N with PLL module (FRCPLL)

000= Fast RC Oscillator (FRC)

FCKSM<1:0>

Clock Switching Mode bits

1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled

01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled

IOL1WAY

Peripheral Pin Select Configuration bit

1= Allows only one reconfiguration

0= Allows multiple reconfigurations

OSCIOFNC

POSCMD<1:0>

OSC2 Pin Function bit (except in XT and HS modes)

1= OSC2 is the clock output

0= OSC2 is a general purpose digital I/O pin

Primary Oscillator Mode Select bits

11= Primary Oscillator is disabled

10= HS Crystal Oscillator mode

01= XT Crystal Oscillator mode

00= EC (External Clock) mode

WDTEN<1:0>

Watchdog Timer Enable bits

11= Watchdog Timer is always enabled (LPRC oscillator cannot be disabled; clearing the

SWDTEN bit in the RCON register will have no effect)

10= Watchdog Timer is enabled/disabled by user software (LPRC can be disabled by

clearing the SWDTEN bit in the RCON register)

01= Watchdog Timer is enabled only while device is active and is disabled while in Sleep

mode; software control is disabled in this mode

00= Watchdog Timer and the SWDTEN bit are disabled

WINDIS

Watchdog Timer Window Enable bit

1= Watchdog Timer is in Non-Window mode

0= Watchdog Timer is in Window mode

PLLKEN

PLL Lock Enable bit

1= PLL lock is enabled

0= PLL lock is disabled

WDTPRE

Watchdog Timer Prescaler bit

1= 1:128

0= 1:32

WDTPOST<3:0>

Watchdog Timer Postscaler bits

1111= 1:32,768

1110= 1:16,384

•

0001= 1:2

0000= 1:1

Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.

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TABLE 22-2: CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field

Description

WDTWIN<1:0>

Watchdog Timer Window Select bits

11= WDT window is 25% of the WDT period

10= WDT window is 37.5% of the WDT period

01= WDT window is 50% of the WDT period

00= WDT window is 75% of the WDT period

JTAGEN

ICS<1:0>

JTAG Enable bit

1= JTAG is enabled

0= JTAG is disabled

ICD Communication Channel Select bits

11= Communicates on PGEC1 and PGED1

10= Communicates on PGEC2 and PGED2

01= Communicates on PGEC3 and PGED3

00= Reserved, do not use

CTXT1<2:0>

Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 1 bits

111= Reserved

110= Assigned to IPL of 7

101= Assigned to IPL of 6

100= Assigned to IPL of 5

011= Assigned to IPL of 4

010= Assigned to IPL of 3

001= Assigned to IPL of 2

000= Assigned to IPL of 1

CTXT2<2:0>

Specifies Interrupt Priority Level (IPL) Associated to Alternate Working Register 2 bits

111= Reserved

110= Assigned to IPL of 7

101= Assigned to IPL of 6

100= Assigned to IPL of 5

011= Assigned to IPL of 4

010= Assigned to IPL of 3

001= Assigned to IPL of 2

000= Assigned to IPL of 1

Note 1: The Boot Segment must be present to use the Alternate Interrupt Vector Table.

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The dsPIC33EPXXGS202 devices have two Identifica-

22.2 Device Calibration and

Identification

tion registers near the end of configuration memory

space that store the Device ID (DEVID) and Device

Revision (DEVREV). These registers are used to

determine the mask, variant and manufacturing infor-

mation about the device. These registers are read-only

and are shown in Register 22-1 and Register 22-2.

The PGAx modules on the dsPIC33EPXXGS202 family

devices require Calibration Data registers to improve

performance of the module over a wide operating

range. These Calibration registers are read-only and

are stored in configuration memory space. Prior to

enabling the module, the calibration data must be read

(TBLPAG and Table Read instruction) and loaded into

their respective SFR registers. The device calibration

addresses are shown in Table 22-3.

TABLE 22-3: DEVICE CALIBRATION ADDRESSES⁽¹⁾

Calibration

Name

Address Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

PGA1CAL

800E48

—

PGA1 Calibration Data bits

PGA2 Calibration Data bits

PGA2CAL 800E4C

Note 1: The calibration data must be copied into its respective registers prior to enabling the module.

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REGISTER 22-1: DEVID: DEVICE ID REGISTER

R

DEVID<23:16>

bit 23

bit 15

bit 7

bit 16

bit 8

bit 0

R

DEVID<15:8>

R

DEVID<7:0>

Legend: R = Read-Only bit

bit 23-0 DEVID<23:0>: Device Identifier bits

U = Unimplemented bit

REGISTER 22-2: DEVREV: DEVICE REVISION REGISTER

R

DEVREV<23:16>

bit 23

bit 15

bit 7

bit 16

bit 8

bit 0

R

DEVREV<15:8>

R

DEVREV<7:0>

Legend: R = Read-only bit

bit 23-0 DEVREV<23:0>: Device Revision bits

U = Unimplemented bit

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22.3 One-Time-Programmable (OTP)

Memory Area

22.5 Brown-out Reset (BOR)

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the reg-

ulated supply voltage, VCAP. The main purpose of the

BOR module is to generate a device Reset when a

brown-out condition occurs. Brown-out conditions are

generally caused by glitches on the AC mains (for

example, missing portions of the AC cycle waveform

due to bad power transmission lines or voltage sags

due to excessive current draw when a large inductive

load is turned on).

dsPIC33EPXXGS202 family devices contain thirty-two

OTP areas, located at addresses, 0x800F80 through

0x800FFC. The OTP area can be used for storing

product information, such as serial numbers, system

manufacturing dates, manufacturing lot numbers and

other application-specific information.

22.4 On-Chip Voltage Regulator

All the dsPIC33EPXXGS202 family devices power their

core digital logic at a nominal 1.8V. This can create a

conflict for designs that are required to operate at a

higher typical voltage, such as 3.3V. To simplify system

design, all devices in the dsPIC33EPXXGS202 family

incorporate an on-chip regulator that allows the device

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source, based on

the device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

to run its core logic from VDD

The regulator provides power to the core from the other

DD pins. A low-ESR (less than 1 Ohm) capacitor (such

.

V

Concurrently, the PWRT Time-out (TPWRT) is applied

before the internal Reset is released. If TPWRT = 0and

a crystal oscillator is being used, then a nominal delay

of TFSCM is applied. The total delay in this case is

as tantalum or ceramic) must be connected to the VCAP

pin (Figure 22-1). This helps to maintain the stability

of the regulator. The recommended value for the

filter capacitor is provided in Table 25-5, located in

T

FSCM. Refer to Parameter SY35 in Table 25-23 of

Section 25.0 “Electrical Characteristics” for specific

FSCM values.

Section 25.0 “Electrical Characteristics”

.

Note: It is important for the low-ESR capacitor to be

T

placed as close as possible to the VCAP pin.

The BOR status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to

operate while in Sleep or Idle modes and resets the

device should VDD fall below the BOR threshold

voltage.

FIGURE 22-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR^(1,2,3)

3.3V

dsPIC33EP

V

DD

CAP

SS

C

EFC

Note 1: These are typical operating voltages. Refer to

Table 25-5 located in Section 25.0 “Electrical

Characteristics” for the full operating ranges

of VDD and VCAP

.

2: It is important for the low-ESR capacitor to be

placed as close as possible to the VCAP pin.

3: Typical VCAP pin voltage = 1.8V when

VDD ≥ VDDMIN.

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22.6.2

SLEEP AND IDLE MODES

22.6 Watchdog Timer (WDT)

If the WDT is enabled, it continues to run during Sleep or

Idle modes. When the WDT time-out occurs, the device

wakes and code execution continues from where the

PWRSAV instruction was executed. The corresponding

SLEEP or IDLE bit (RCON<3:2>) needs to be cleared in

software after the device wakes up.

For dsPIC33EPXXGS202 family devices, the WDT is

driven by the LPRC oscillator. When the WDT is

enabled, the clock source is also enabled.

22.6.1

PRESCALER/POSTSCALER

The nominal WDT clock source from LPRC is 32 kHz.

This feeds a prescaler that can be configured for either

5-bit (divide-by-32) or 7-bit (divide-by-128) operation.

The prescaler is set by the WDTPRE Configuration bit.

With a 32 kHz input, the prescaler yields a WDT Time-

out Period (TWDT), as shown in Parameter SY12 in

Table 25-23.

22.6.3

ENABLING WDT

The WDT is enabled or disabled by the WDTEN<1:0>

Configuration bits in the FWDT Configuration register.

When the WDTEN<1:0> Configuration bits have been

programmed to ‘0b11’, the WDT is always enabled.

The WDT can be optionally controlled in software

when the WDTEN<1:0> Configuration bits have been

programmed to ‘0b10’. The WDT is enabled in soft-

ware by setting the SWDTEN control bit (RCON<5>).

The SWDTEN control bit is cleared on any device

Reset. The software WDT option allows the user appli-

cation to enable the WDT for critical Code Segments

and disables the WDT during non-critical segments for

maximum power savings.

A variable postscaler divides down the WDT prescaler

output and allows for a wide range of time-out periods.

The postscaler is controlled by the WDTPOST<3:0>

Configuration bits (FWDT<3:0>), which allow the

selection of 16 settings, from 1:1 to 1:32,768. Using the

prescaler and postscaler, time-out periods, ranges from

1 ms to 131 seconds can be achieved.

The WDT, prescaler and postscaler are reset:

• On any device Reset

The WDT Time-out flag bit, WDTO (RCON<4>), is not

automatically cleared following a WDT time-out. To

detect subsequent WDT events, the flag must be

cleared in software.

• On the completion of a clock switch, whether

invoked by software (i.e., setting the OSWEN bit

after changing the NOSCx bits) or by hardware

(i.e., Fail-Safe Clock Monitor)

22.6.4

WDT WINDOW

• When a PWRSAVinstruction is executed

(i.e., Sleep or Idle mode is entered)

The Watchdog Timer has an optional Windowed mode,

enabled by programming the WINDIS bit in the WDT

Configuration register (FWDT<7>). In the Windowed

mode (WINDIS = 0), the WDT should be cleared based

on the settings in the programmable Watchdog Timer

Window select bits (WDTWIN<1:0>).

• When the device exits Sleep or Idle mode to

resume normal operation

• By a CLRWDTinstruction during normal execution

Note:

The CLRWDT and PWRSAV instructions

clear the prescaler and postscaler counts

when executed.

FIGURE 22-2:

WDT BLOCK DIAGRAM

All Device Resets

Transition to New Clock Source

Exit Sleep or Idle Mode

PWRSAVInstruction

CLRWDTInstruction

Watchdog Timer

Sleep/Idle

WDTPOST<3:0>

WDTPRE

SWDTEN

WDT

Wake-up

WDTEN<1:0>

1

RS

Prescaler

Postscaler

(Divide-by-N1)

(Divide-by-N2)

LPRC Clock

WDT

Reset

0

WINDIS

WDT Window Select

WDTWIN<1:0>

CLRWDTInstruction

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22.7 JTAG Interface

22.10 Code Protection and

CodeGuard™ Security

The dsPIC33EPXXGS202 family devices implement a

JTAG interface, which supports boundary scan device

testing. Detailed information on this interface is

provided in future revisions of the document.

dsPIC33EPXXGS202 devices offer multiple levels of

security for protecting individual intellectual property. The

program Flash protection can be broken up into three

segments: Boot Segment (BS), General Segment (GS)

and Configuration Segment (CS). Boot Segment has the

highest security privilege and can be thought to have

limited restrictions when accessing other segments.

General Segment has the least security and is intended

for the end user system code. Configuration Segment

contains only the device user configuration data which is

located at the end of the program memory space.

Note: Refer to “Programming and Diagnostics”

(DS70608) in the “dsPIC33/PIC24 Family

Reference Manual” for further information on

usage, configuration and operation of the

JTAG interface.

22.8

In-Circuit Serial Programming

The dsPIC33EPXXGS202 family devices can be serially

programmed while in the end application circuit. This is

done with two lines for clock and data, and three other

lines for power, ground and the programming sequence.

Serial programming allows customers to manufacture

boards with unprogrammed devices and then program

the device just before shipping the product. Serial

programming also allows the most recent firmware or a

custom firmware to be programmed. Refer to the

“dsPIC33E/PIC24E Flash Programming Specification

for Devices with Volatile Configuration Bits” (DS70663)

for details about In-Circuit Serial Programming (ICSP).

The code protection features are controlled by the

Configuration registers, FSEC and FBSLIM. The FSEC

register controls the code-protect level for each segment

and if that segment is write-protected. The size of the BS

and GS will depend on the BSLIM<12:0> setting and if

the Alternate Interrupt Vector Table (AIVT) is enabled.

The BSLIM<12:0> bits define the number of pages for

BS with each page containing 512 IW. The smallest BS

size is one page, which will consist of the Interrupt Vector

Table (IVT) and 256 IW of code protection.

If the AIVT is enabled, the last page of BS will contain

the AIVT and will not contain any BS code. With AIVT

enabled, the smallest BS size is now two pages

(1024 IW), with one page for the IVT and BS code, and

the other page for the AIVT. Write protection of the Boot

Segment does not cover the AIVT. The last page of the

BS can always be programmed or erased by BS code.

The General Segment will start at the next page and

will consume the rest of program Flash except for the

Flash Configuration Words. The IVT will assume GS

security only if BS is not enabled. The IVT is protected

from being programmed or page erased when either

security segment has enabled write protection.

Any of the three pairs of programming clock/data pins

can be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

22.9 In-Circuit Debugger

When MPLAB^®ICD 3 or REAL ICE™ is selected as a

debugger, the in-circuit debugging functionality is

enabled. This function allows simple debugging functions

when used with MPLAB X IDE. Debugging functionality is

controlled through the PGECx (Emulation/Debug Clock)

and PGEDx (Emulation/Debug Data) pin functions.

Note: Refer to “CodeGuard™ Intermediate

Security” (DS70005182) in the “dsPIC33/

PIC24 Family Reference Manual” for further

information on usage, configuration and

operation of CodeGuard Security.

Any of the three pairs of debugging clock/data pins can

be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS and the PGECx/PGEDx pin pair. In

addition, when the feature is enabled, some of the

resources are not available for general use. These

resources include the first 80 bytes of data RAM and

two I/O pins (PGECx and PGEDx).

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The different device security segments are shown in

Figure 22-3. Here, all three segments are shown but

are not required. If only basic code protection is

required, then the GS can be enabled independently or

combined with the CS if desired.

FIGURE 22-3:

dsPIC33EPXXGS202

SECURITY SEGMENTS

EXAMPLE

0x000000

IVT

0x000200

IVT and AIVT

Assume

BS Protection

BS

(2)

AIVT + 256 IW

BSLIM<12:0>

GS

(1)

(3)

CS

0xXXXXXX

Note 1: If CS is write-protected, the last page

(GS + CS) of program memory will be

protected from an erase condition.

2: The last half (256 IW) of the last page of the

BS is unusable program memory.

3: dsPIC33EP16GS202 CS is 0x002BFE.

dsPIC33EP32GS202 CS is 0x0057FE

.

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NOTES:

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Most bit-oriented instructions (including simple rotate/

shift instructions) have two operands:

23.0 INSTRUCTION SET SUMMARY

Note: This data sheet summarizes the

features of the dsPIC33EPXXGS202

family of devices. It is not intended to be

a comprehensive reference source. To

complement the information in this data

sheet, refer to the related section in

the “dsPIC33/PIC24 Family Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

• The W register (with or without an address

modifier) or file register (specified by the value of

‘Ws’ or ‘f’)

• The bit in the W register or file register (specified

by a literal value or indirectly by the contents of

register ‘Wb’)

The literal instructions that involve data movement can

use some of the following operands:

• A literal value to be loaded into a W register or file

register (specified by ‘k’)

The dsPIC33EP instruction set is almost identical to

that of the dsPIC30F and dsPIC33F.

• The W register or file register where the literal

value is to be loaded (specified by ‘Wb’ or ‘f’)

Most instructions are a single program memory word

(24 bits). Only three instructions require two program

memory locations.

However, literal instructions that involve arithmetic or

logical operations use some of the following operands:

Each single-word instruction is a 24-bit word, divided

into an 8-bit opcode, which specifies the instruction

type and one or more operands, which further specify

the operation of the instruction.

• The first source operand, which is a register ‘Wb’

without any address modifier

• The second source operand, which is a literal

value

The instruction set is highly orthogonal and is grouped

into five basic categories:

• The destination of the result (only if not the same

as the first source operand), which is typically a

register ‘Wd’ with or without an address modifier

• Word or byte-oriented operations

• Bit-oriented operations

• Literal operations

The MACclass of DSP instructions can use some of the

following operands:

• DSP operations

• The accumulator (A or B) to be used (required

operand)

• Control operations

Table 23-1 lists the general symbols used in describing

the instructions.

• The W registers to be used as the two operands

• The X and Y address space prefetch operations

• The X and Y address space prefetch destinations

• The accumulator write back destination

The dsPIC33EP instruction set summary in Table 23-2

lists all the instructions, along with the status flags

affected by each instruction.

The other DSP instructions do not involve any

multiplication and can include:

Most word or byte-oriented W register instructions

(including barrel shift instructions) have three

operands:

• The accumulator to be used (required)

• The source or destination operand (designated as

Wso or Wdo, respectively) with or without an

address modifier

• The first source operand, which is typically a

register ‘Wb’ without any address modifier

• The second source operand, which is typically a

register ‘Ws’ with or without an address modifier

• The amount of shift specified by a W register ‘Wn’

or a literal value

• The destination of the result, which is typically a

register ‘Wd’ with or without an address modifier

The control instructions can use some of the following

operands:

However, word or byte-oriented file register instructions

have two operands:

• A program memory address

• The mode of the Table Read and Table Write

instructions

• The file register specified by the value ‘f’

• The destination, which could be either the file

register ‘f’ or the W0 register, which is denoted as

‘WREG’

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Most instructions are a single word. Certain double-word

instructions are designed to provide all the required

information in these 48 bits. In the second word, the

8 MSbs are ‘0’s. If this second word is executed as an

instruction (by itself), it executes as a NOP.

cases, the execution takes multiple instruction cycles,

with the additional instruction cycle(s) executed as a NOP.

Certain instructions that involve skipping over the subse-

quent instruction require either two or three cycles if the

skip is performed, depending on whether the instruction

being skipped is a single-word or two-word instruction.

Moreover, double-word moves require two cycles.

The double-word instructions execute in two instruction

cycles.

Note:

For more details on the instruction set,

refer to the “16-bit MCU and DSC

Most single-word instructions are executed in a single

instruction cycle, unless a conditional test is true or the

Program Counter is changed as a result of the instruc-

tion, or a PSV or Table Read is performed. In these

Programmer’s

Reference

Manual”

(DS70157).

TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS

Field

Description

#text

(text)

[text]

{ }

Means literal defined by “text

Means “content of text

”

Means “the location addressed by text

”

Optional field or operation

a  {b, c, d}

<n:m>

.b

a is selected from the set of values b, c, d

Register bit field

Byte mode selection

.d

Double-Word mode selection

Shadow register select

.S

.w

Word mode selection (default)

One of two accumulators {A, B}

Acc

AWB

bit4

Accumulator write-back destination address register {W13, [W13]+ = 2}

4-bit bit selection field (used in word addressed instructions) {0...15}

MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero

Absolute address, label or expression (resolved by the linker)

File register address {0x0000...0x1FFF}

C, DC, N, OV, Z

Expr

f

lit1

1-bit unsigned literal {0,1}

lit4

4-bit unsigned literal {0...15}

lit5

5-bit unsigned literal {0...31}

lit8

8-bit unsigned literal {0...255}

lit10

10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode

14-bit unsigned literal {0...16384}

lit14

lit16

16-bit unsigned literal {0...65535}

lit23

23-bit unsigned literal {0...8388608}; LSb must be ‘0’

None

OA, OB, SA, SB

PC

Field does not require an entry, can be blank

DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate

Program Counter

Slit10

Slit16

Slit6

Wb

10-bit signed literal {-512...511}

16-bit signed literal {-32768...32767}

6-bit signed literal {-16...16}

Base W register {W0...W15}

Wd

Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }

Wdo

Destination W register 

{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }

Wm,Wn

Dividend, Divisor Working register pair (Direct Addressing)

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TABLE 23-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)

Field

Description

Wm*Wm

Wm*Wn

Multiplicand and Multiplier Working register pair for Square instructions 

{W4 * W4,W5 * W5,W6 * W6,W7 * W7}

Multiplicand and Multiplier Working register pair for DSP instructions 

{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}

Wn

One of 16 Working registers {W0...W15}

Wnd

Wns

WREG

Ws

One of 16 Destination Working registers {W0...W15}

One of 16 Source Working registers {W0...W15}

W0 (Working register used in file register instructions)

Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }

Wso

Source W register 

{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }

Wx

X Data Space Prefetch Address register for DSP instructions

 {[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,

[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,

[W9 + W12], none}

Wxd

Wy

X Data Space Prefetch Destination register for DSP instructions {W4...W7}

Y Data Space Prefetch Address register for DSP instructions

 {[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,

[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,

[W11 + W12], none}

Wyd

Y Data Space Prefetch Destination register for DSP instructions {W4...W7}

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TABLE 23-2: INSTRUCTION SET OVERVIEW

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

1

ADD

ADDC

AND

ASR

BCLR

BRA

BSET

Acc

Add Accumulators

1

OA,OB,SA,SB

C,DC,N,OV,Z

OA,OB,SA,SB

C,DC,N,OV,Z

N,Z

f

f = f + WREG

f,WREG

WREG = f + WREG

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Wso,#Slit4,Acc

f

Wd = lit10 + Wd

1

Wd = Wb + Ws

1

Wd = Wb + lit5

1

16-bit Signed Add to Accumulator

f = f + WREG + (C)

1

2

3

4

ADDC

AND

1

f,WREG

WREG = f + WREG + (C)

Wd = lit10 + Wd + (C)

Wd = Wb + Ws + (C)

1

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

Wd = Wb + lit5 + (C)

1

f = f .AND. WREG

1

f,WREG

WREG = f .AND. WREG

Wd = lit10 .AND. Wd

1

N,Z

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

1

N,Z

Wd = Wb .AND. Ws

1

N,Z

Wd = Wb .AND. lit5

1

N,Z

ASR

f = Arithmetic Right Shift f

WREG = Arithmetic Right Shift f

Wd = Arithmetic Right Shift Ws

Wnd = Arithmetic Right Shift Wb by Wns

Wnd = Arithmetic Right Shift Wb by lit5

Bit Clear f

1

C,N,OV,Z

N,Z

f,WREG

1

Ws,Wd

1

Wb,Wns,Wnd

Wb,#lit5,Wnd

f,#bit4

Ws,#bit4

C,Expr

1

N,Z

5

7

BCLR

BRA

1

None

Bit Clear Ws

1

None

Branch if Carry

1 (4)

4

None

GE,Expr

GEU,Expr

GT,Expr

GTU,Expr

LE,Expr

LEU,Expr

LT,Expr

LTU,Expr

N,Expr

Branch if greater than or equal

Branch if unsigned greater than or equal

Branch if greater than

Branch if unsigned greater than

Branch if less than or equal

Branch if unsigned less than or equal

Branch if less than

None

Branch if unsigned less than

Branch if Negative

None

NC,Expr

NN,Expr

NOV,Expr

NZ,Expr

OA,Expr

OB,Expr

OV,Expr

SA,Expr

SB,Expr

Expr

Branch if Not Carry

None

Branch if Not Negative

Branch if Not Overflow

Branch if Not Zero

None

Branch if Accumulator A overflow

Branch if Accumulator B overflow

Branch if Overflow

None

Branch if Accumulator A saturated

Branch if Accumulator B saturated

Branch Unconditionally

Branch if Zero

None

Z,Expr

1 (4)

4

None

Wn

Computed Branch

None

8

BSET

f,#bit4

Ws,#bit4

Bit Set f

1

None

Bit Set Ws

1

None

Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

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TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

9

BSW

BSW.C

BSW.Z

BTG

Ws,Wb

Write C bit to Ws<Wb>

1

None

Ws,Wb

Write Z bit to Ws<Wb>

Bit Toggle f

10

11

BTG

f,#bit4

Ws,#bit4

f,#bit4

BTG

Bit Toggle Ws

BTSC

Bit Test f, Skip if Clear

1

(2 or 3)

BTSC

BTSS

Ws,#bit4

f,#bit4

Ws,#bit4

Bit Test Ws, Skip if Clear

Bit Test f, Skip if Set

1

None

(2 or 3)

12

13

BTSS

BTST

1

(2 or 3)

Bit Test Ws, Skip if Set

1

(2 or 3)

BTST

f,#bit4

Ws,#bit4

Ws,Wb

Bit Test f

1

2

1

4

1

Z

BTST.C

BTST.Z

BTST.C

BTST.Z

BTSTS

Bit Test Ws to C

C

Bit Test Ws to Z

Z

Bit Test Ws<Wb> to C

Bit Test Ws<Wb> to Z

Bit Test then Set f

Bit Test Ws to C, then Set

Bit Test Ws to Z, then Set

Call subroutine

C

Ws,Wb

Z

14

15

16

BTSTS

CALL

CLR

f,#bit4

Z

BTSTS.C Ws,#bit4

BTSTS.Z Ws,#bit4

C

Z

CALL

CALL.L

CLR

lit23

SFA

Wn

Call indirect subroutine

Call indirect subroutine (long address)

f = 0x0000

SFA

Wn

SFA

f

None

CLR

WREG

WREG = 0x0000

Ws = 0x0000

None

CLR

Ws

None

CLR

Acc,Wx,Wxd,Wy,Wyd,AWB

Clear Accumulator

Clear Watchdog Timer

f = f

OA,OB,SA,SB

WDTO,SLEEP

N,Z

17

18

CLRWDT

COM

CLRWDT

COM

f

COM

f,WREG

WREG = f

N,Z

COM

CP

Ws,Wd

Wd = Ws

1

N,Z

19

CP

f

Compare f with WREG

C,DC,N,OV,Z

CP

Wb,#lit8

Compare Wb with lit8

CP

Wb,Ws

Compare Wb with Ws (Wb – Ws)

Compare f with 0x0000

20

21

CP0

CPB

CP0

CPB

f

Ws

Compare Ws with 0x0000

Compare f with WREG, with Borrow

Compare Wb with lit8, with Borrow

f

Wb,#lit8

Wb,Ws

Compare Wb with Ws, with Borrow

(Wb – Ws – C)

22

23

24

25

CPSEQ

Wb,Wn

Compare Wb with Wn, skip if =

1

None

(2 or 3)

CPBEQ

CPSGT

CPBEQ

CPSGT

Wb,Wn,Expr

Wb,Wn

Compare Wb with Wn, branch if =

Compare Wb with Wn, skip if >

1

1 (5)

None

1

(2 or 3)

CPBGT

CPSLT

CPBGT

CPSLT

Wb,Wn,Expr

Wb,Wn

Compare Wb with Wn, branch if >

Compare Wb with Wn, skip if <

1

1 (5)

None

1

(2 or 3)

CPBLT

CPSNE

CPBLT

CPSNE

Wb,Wn,Expr

Wb,Wn

Compare Wb with Wn, branch if <

1

1 (5)

None

Compare Wb with Wn, skip if



1

(2 or 3)

CPBNE

Wb,Wn,Expr

Compare Wb with Wn, branch if



1

1 (5)

None

Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

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TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

26

CTXTSWP

CTXTSWP #1it3

CTXTSWP Wn

Switch CPU register context to context

defined by lit3

1

2

None

Switch CPU register context to context

defined by Wn

27

28

DAW

DEC

DAW

Wn

Wn = decimal adjust Wn

f = f – 1

1

2

1

C

DEC

f

C,DC,N,OV,Z

None

DEC

f,WREG

Ws,Wd

WREG = f – 1

1

DEC

Wd = Ws – 1

1

29

DEC2

DISI

DIV.S

DIV.SD

DIV.U

DIV.UD

DIVF

DO

f

f = f – 2

1

f,WREG

Ws,Wd

WREG = f – 2

1

Wd = Ws – 2

1

30

31

DISI

DIV

#lit14

Wm,Wn

Disable Interrupts for k instruction cycles

Signed 16/16-bit Integer Divide

Signed 32/16-bit Integer Divide

Unsigned 16/16-bit Integer Divide

Unsigned 32/16-bit Integer Divide

Signed 16/16-bit Fractional Divide

Do code to PC + Expr, lit15 + 1 times

Do code to PC + Expr, (Wn) + 1 times

Euclidean Distance (no accumulate)

1

18

2

N,Z,C,OV

None

Wm,Wn

32

33

DIVF

DO

Wm,Wn

#lit15,Expr

Wn,Expr

Wm*Wm,Acc,Wx,Wy,Wxd

DO

2

None

34

35

ED

1

OA,OB,OAB,

SA,SB,SAB

EDAC

Wm*Wm,Acc,Wx,Wy,Wxd

Euclidean Distance

1

OA,OB,OAB,

SA,SB,SAB

36

37

38

39

40

EXCH

FBCL

FF1L

FF1R

GOTO

EXCH

FBCL

FF1L

FF1R

GOTO

GOTO.L

INC

Wns,Wnd

Ws,Wnd

Expr

Swap Wns with Wnd

Find Bit Change from Left (MSb) Side

Find First One from Left (MSb) Side

Find First One from Right (LSb) Side

Go to address

1

2

1

4

1

None

C

None

Wn

Go to indirect

None

Wn

Go to indirect (long address)

f = f + 1

None

41

42

43

INC

f

C,DC,N,OV,Z

N,Z

INC

f,WREG

Ws,Wd

WREG = f + 1

INC

Wd = Ws + 1

INC2

IOR

INC2

IOR

f

f = f + 2

f,WREG

Ws,Wd

WREG = f + 2

Wd = Ws + 2

f

f = f .IOR. WREG

IOR

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Wso,#Slit4,Acc

WREG = f .IOR. WREG

Wd = lit10 .IOR. Wd

Wd = Wb .IOR. Ws

Wd = Wb .IOR. lit5

Load Accumulator

N,Z

IOR

N,Z

IOR

N,Z

IOR

N,Z

44

LAC

OA,OB,OAB,

SA,SB,SAB

45

46

LNK

LSR

LNK

LSR

#lit14

Link Frame Pointer

1

SFA

C,N,OV,Z

N,Z

f

f = Logical Right Shift f

f,WREG

WREG = Logical Right Shift f

Wd = Logical Right Shift Ws

Wnd = Logical Right Shift Wb by Wns

Wnd = Logical Right Shift Wb by lit5

Ws,Wd

Wb,Wns,Wnd

Wb,#lit5,Wnd

N,Z

Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

DS70005208E-page 256

 2015-2018 Microchip Technology Inc.

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TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

47

48

MAC

MOV

MAC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Multiply and Accumulate

Square and Accumulate

1

OA,OB,OAB,

SA,SB,SAB

OA,OB,OAB,

SA,SB,SAB

MOV

f,Wn

Move f to Wn

1

2

None

MOV

f

Move f to f

MOV

f,WREG

#lit16,Wn

#lit8,Wn

Wn,f

Move f to WREG

MOV

Move 16-bit literal to Wn

Move 8-bit literal to Wn

Move Wn to f

MOV.b

MOV

Wso,Wdo

WREG,f

Wns,Wd

Ws,Wnd

Move Ws to Wd

MOV

Move WREG to f

MOV.D

Move Double from W(ns):W(ns + 1) to Wd

Move Double from Ws to

W(nd + 1):W(nd)

49

MOVPAG

#lit10,DSRPAG

#lit8,TBLPAG

Move 10-bit literal to DSRPAG

Move 8-bit literal to TBLPAG

Move Ws<9:0> to DSRPAG

Move Ws<7:0> to TBLPAG

1

None

MOVPAGW Ws, DSRPAG

MOVPAGW Ws, TBLPAG

50

51

MOVSAC

MPY

MOVSAC

MPY

Acc,Wx,Wxd,Wy,Wyd,AWB

Prefetch and store accumulator

Multiply Wm by Wn to Accumulator

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

OA,OB,OAB,

SA,SB,SAB

MPY

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd

Square Wm to Accumulator

1

OA,OB,OAB,

SA,SB,SAB

52

53

MPY.N

MSC

MPY.N

MSC

Wm*Wn,Acc,Wx,Wxd,Wy,Wyd

-(Multiply Wm by Wn) to Accumulator

Multiply and Subtract from Accumulator

1

None

Wm*Wm,Acc,Wx,Wxd,Wy,Wyd,AWB

OA,OB,OAB,

SA,SB,SAB

54

MUL

MUL.SS

MUL.SU

Wb,Ws,Wnd

Wb,Ws,Acc

Wb,Ws,Wnd

{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)

Accumulator = signed(Wb) * signed(Ws)

1

None

{Wnd + 1, Wnd} = signed(Wb) *

unsigned(Ws)

MUL.SU

MUL.US

Wb,Ws,Acc

Accumulator = signed(Wb) * unsigned(Ws)

Accumulator = signed(Wb) * unsigned(lit5)

1

None

Wb,#lit5,Acc

Wb,Ws,Wnd

{Wnd + 1, Wnd} = unsigned(Wb) *

signed(Ws)

MUL.US

MUL.UU

Wb,Ws,Acc

Wb,Ws,Wnd

Accumulator = unsigned(Wb) * signed(Ws)

1

None

{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(Ws)

MUL.UU

Wb,#lit5,Acc

Wb,Ws,Acc

Accumulator = unsigned(Wb) *

unsigned(lit5)

1

None

Accumulator = unsigned(Wb) *

unsigned(Ws)

MULW.SS Wb,Ws,Wnd

MULW.SU Wb,Ws,Wnd

MULW.US Wb,Ws,Wnd

MULW.UU Wb,Ws,Wnd

Wnd = signed(Wb) * signed(Ws)

Wnd = signed(Wb) * unsigned(Ws)

Wnd = unsigned(Wb) * signed(Ws)

Wnd = unsigned(Wb) * unsigned(Ws)

1

None

MUL.SU

Wb,#lit5,Wnd

{Wnd + 1, Wnd} = signed(Wb) *

unsigned(lit5)

MUL.SU

MUL.UU

Wb,#lit5,Wnd

Wnd = signed(Wb) * unsigned(lit5)

1

None

{Wnd + 1, Wnd} = unsigned(Wb) *

unsigned(lit5)

MUL.UU

MUL

Wb,#lit5,Wnd

f

Wnd = unsigned(Wb) * unsigned(lit5)

W3:W2 = f * WREG

1

None

Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

 2015-2018 Microchip Technology Inc.

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TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

55

NEG

Acc

Negate Accumulator

1

OA,OB,OAB,

SA,SB,SAB

NEG

f

f = f + 1

1

2

C,DC,N,OV,Z

None

NEG

f,WREG

Ws,Wd

WREG = f + 1

NEG

Wd = Ws + 1

56

57

NOP

POP

NOP

No Operation

NOPR

POP

No Operation

None

f

Pop f from Top-of-Stack (TOS)

Pop from Top-of-Stack (TOS) to Wdo

None

POP

Wdo

Wnd

None

POP.D

Pop from Top-of-Stack (TOS) to

W(nd):W(nd + 1)

None

POP.S

PUSH

Pop Shadow Registers

1

2

All

58

PUSH

f

Push f to Top-of-Stack (TOS)

Push Wso to Top-of-Stack (TOS)

None

PUSH

Wso

Wns

PUSH.D

Push W(ns):W(ns + 1) to Top-of-Stack

(TOS)

PUSH.S

PWRSAV

RCALL

REPEAT

RESET

RETFIE

RETLW

RETURN

RLC

Push Shadow Registers

1

None

WDTO,SLEEP

SFA

59

60

PWRSAV

RCALL

#lit1

Expr

Wn

Go into Sleep or Idle mode

Relative Call

4

Computed Call

4

SFA

61

REPEAT

#lit15

Wn

Repeat Next Instruction lit15 + 1 times

Repeat Next Instruction (Wn) + 1 times

Software device Reset

1

None

SFA

1

62

63

64

65

66

RESET

RETFIE

RETLW

RETURN

RLC

1

Return from interrupt

6 (5)

1

#lit10,Wn

Return with literal in Wn

SFA

Return from Subroutine

SFA

f

f = Rotate Left through Carry f

WREG = Rotate Left through Carry f

Wd = Rotate Left through Carry Ws

f = Rotate Left (No Carry) f

WREG = Rotate Left (No Carry) f

Wd = Rotate Left (No Carry) Ws

f = Rotate Right through Carry f

WREG = Rotate Right through Carry f

Wd = Rotate Right through Carry Ws

f = Rotate Right (No Carry) f

WREG = Rotate Right (No Carry) f

Wd = Rotate Right (No Carry) Ws

Store Accumulator

C,N,Z

N,Z

RLC

f,WREG

1

RLC

Ws,Wd

1

67

68

69

70

RLNC

RRC

RLNC

RRC

f

1

f,WREG

1

N,Z

Ws,Wd

1

N,Z

f

1

C,N,Z

N,Z

RRC

f,WREG

1

RRC

Ws,Wd

1

RRNC

SAC

RRNC

SAC

f

1

f,WREG

1

N,Z

Ws,Wd

1

N,Z

Acc,#Slit4,Wdo

1

None

C,N,Z

None

SAC.R

SE

Acc,#Slit4,Wdo

Store Rounded Accumulator

Wnd = sign-extended Ws

f = 0xFFFF

1

71

72

SE

Ws,Wnd

f

1

SETM

SFTAC

1

WREG

Ws

WREG = 0xFFFF

1

Ws = 0xFFFF

1

73

SFTAC

Acc,Wn

Arithmetic Shift Accumulator by (Wn)

1

OA,OB,OAB,

SA,SB,SAB

SFTAC

Acc,#Slit6

Arithmetic Shift Accumulator by Slit6

1

OA,OB,OAB,

SA,SB,SAB

Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

DS70005208E-page 258

 2015-2018 Microchip Technology Inc.

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TABLE 23-2: INSTRUCTION SET OVERVIEW (CONTINUED)

Base

Instr

#

Assembly

Mnemonic

# of

Status Flags

Affected

Assembly Syntax

Description

Words Cycles

74

SL

SUB

f

f = Left Shift f

1

C,N,OV,Z

N,Z

f,WREG

WREG = Left Shift f

Ws,Wd

Wd = Left Shift Ws

Wb,Wns,Wnd

Wb,#lit5,Wnd

Acc

Wnd = Left Shift Wb by Wns

Wnd = Left Shift Wb by lit5

Subtract Accumulators

N,Z

75

SUB

OA,OB,OAB,

SA,SB,SAB

SUB

SUBB

f

f = f – WREG

1

C,DC,N,OV,Z

f,WREG

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

WREG = f – WREG

Wn = Wn – lit10

Wd = Wb – Ws

Wd = Wb – lit5

76

SUBB

f = f – WREG – (C)

WREG = f – WREG – (C)

f,WREG

SUBB

SUBR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

f

Wn = Wn – lit10 – (C)

Wd = Wb – Ws – (C)

Wd = Wb – lit5 – (C)

f = WREG – f

1

C,DC,N,OV,Z

77

78

SUBR

f,WREG

WREG = WREG – f

Wd = Ws – Wb

Wb,Ws,Wd

Wb,#lit5,Wd

Wd = lit5 – Wb

SUBBR

f

f = WREG – f – (C)

1

C,DC,N,OV,Z

f,WREG

Wb,Ws,Wd

WREG = WREG – f – (C)

Wd = Ws – Wb – (C)

SUBBR

SWAP.b

SWAP

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

XOR

Wb,#lit5,Wd

Wn

Wd = lit5 – Wb – (C)

1

5

2

1

C,DC,N,OV,Z

None

SFA

79

SWAP

Wn = nibble swap Wn

Wn = byte swap Wn

Wn

80

81

82

83

84

85

TBLRDH

TBLRDL

TBLWTH

TBLWTL

ULNK

Ws,Wd

Read Prog<23:16> to Wd<7:0>

Read Prog<15:0> to Wd

Write Ws<7:0> to Prog<23:16>

Write Ws to Prog<15:0>

Unlink Frame Pointer

f = f .XOR. WREG

XOR

f

N,Z

XOR

f,WREG

WREG = f .XOR. WREG

Wd = lit10 .XOR. Wd

Wd = Wb .XOR. Ws

N,Z

XOR

#lit10,Wn

Wb,Ws,Wd

Wb,#lit5,Wd

Ws,Wnd

N,Z

XOR

N,Z

XOR

Wd = Wb .XOR. lit5

N,Z

86

ZE

Wnd = Zero-extend Ws

C,Z,N

Note: Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 259

dsPIC33EPXXGS202 FAMILY

NOTES:

DS70005208E-page 260

 2015-2018 Microchip Technology Inc.

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24.1 MPLAB X Integrated Development

Environment Software

24.0 DEVELOPMENT SUPPORT

The PIC^®microcontrollers (MCU) and dsPIC^®digital

signal controllers (DSC) are supported with a full range

of software and hardware development tools:

The MPLAB X IDE is a single, unified graphical user

interface for Microchip and third-party software, and

®

hardware development tool that runs on Windows ,

• Integrated Development Environment

- MPLAB^®X IDE Software

• Compilers/Assemblers/Linkers

- MPLAB XC Compiler

- MPASM^TMAssembler

- MPLINK^TMObject Linker/

MPLIB^TMObject Librarian

®

Linux and Mac OS X. Based on the NetBeans IDE,

MPLAB X IDE is an entirely new IDE with a host of free

software components and plug-ins for high-

performance application development and debugging.

Moving between tools and upgrading from software

simulators to hardware debugging and programming

tools is simple with the seamless user interface.

- MPLAB Assembler/Linker/Librarian for

Various Device Families

With complete project management, visual call graphs,

a configurable watch window and a feature-rich editor

that includes code completion and context menus,

MPLAB X IDE is flexible and friendly enough for new

users. With the ability to support multiple tools on

multiple projects with simultaneous debugging, MPLAB

X IDE is also suitable for the needs of experienced

users.

• Simulators

- MPLAB X SIM Software Simulator

• Emulators

- MPLAB REAL ICE™ In-Circuit Emulator

• In-Circuit Debuggers/Programmers

- MPLAB ICD 3

Feature-Rich Editor:

- PICkit™ 3

• Color syntax highlighting

• Device Programmers

- MPLAB PM3 Device Programmer

• Smart code completion makes suggestions and

provides hints as you type

• Low-Cost Demonstration/Development Boards,

Evaluation Kits and Starter Kits

• Automatic code formatting based on user-defined

rules

• Third-party development tools

• Live parsing

User-Friendly, Customizable Interface:

• Fully customizable interface: toolbars, toolbar

buttons, windows, window placement, etc.

• Call graph window

Project-Based Workspaces:

• Multiple projects

• Multiple tools

• Multiple configurations

• Simultaneous debugging sessions

File History and Bug Tracking:

• Local file history feature

• Built-in support for Bugzilla issue tracker

 2015-2018 Microchip Technology Inc.

DS70005208E-page 261

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24.2 MPLAB XC Compilers

24.4 MPLINK Object Linker/

MPLIB Object Librarian

The MPLAB XC Compilers are complete ANSI C

compilers for all of Microchip’s 8, 16 and 32-bit MCU

and DSC devices. These compilers provide powerful

integration capabilities, superior code optimization and

ease of use. MPLAB XC Compilers run on Windows,

Linux or MAC OS X.

The MPLINK Object Linker combines relocatable

objects created by the MPASM Assembler. It can link

relocatable objects from precompiled libraries, using

directives from a linker script.

The MPLIB Object Librarian manages the creation and

modification of library files of precompiled code. When

a routine from a library is called from a source file, only

the modules that contain that routine will be linked in

with the application. This allows large libraries to be

used efficiently in many different applications.

For easy source level debugging, the compilers provide

debug information that is optimized to the MPLAB X

IDE.

The free MPLAB XC Compiler editions support all

devices and commands, with no time or memory

restrictions, and offer sufficient code optimization for

most applications.

The object linker/library features include:

• Efficient linking of single libraries instead of many

smaller files

MPLAB XC Compilers include an assembler, linker and

utilities. The assembler generates relocatable object

files that can then be archived or linked with other

relocatable object files and archives to create an

executable file. MPLAB XC Compiler uses the

assembler to produce its object file. Notable features of

the assembler include:

• Enhanced code maintainability by grouping

related modules together

• Flexible creation of libraries with easy module

listing, replacement, deletion and extraction

24.5 MPLAB Assembler, Linker and

Librarian for Various Device

Families

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

MPLAB Assembler produces relocatable machine

code from symbolic assembly language for PIC24,

PIC32 and dsPIC DSC devices. MPLAB XC Compiler

uses the assembler to produce its object file. The

assembler generates relocatable object files that can

then be archived or linked with other relocatable object

files and archives to create an executable file. Notable

features of the assembler include:

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

24.3 MPASM Assembler

The MPASM Assembler is a full-featured, universal

macro assembler for PIC10/12/16/18 MCUs.

• Support for the entire device instruction set

• Support for fixed-point and floating-point data

• Command-line interface

The MPASM Assembler generates relocatable object

files for the MPLINK Object Linker, Intel^®standard HEX

files, MAP files to detail memory usage and symbol

reference, absolute LST files that contain source lines

and generated machine code, and COFF files for

debugging.

• Rich directive set

• Flexible macro language

• MPLAB X IDE compatibility

The MPASM Assembler features include:

• Integration into MPLAB X IDE projects

• User-defined macros to streamline

assembly code

• Conditional assembly for multipurpose

source files

• Directives that allow complete control over the

assembly process

DS70005208E-page 262

 2015-2018 Microchip Technology Inc.

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24.6 MPLAB X SIM Software Simulator

24.8 MPLAB ICD 3 In-Circuit Debugger

System

The MPLAB X SIM Software Simulator allows code

development in PC-hosted environment by

a

The MPLAB ICD 3 In-Circuit Debugger System is

Microchip’s most cost-effective, high-speed hardware

debugger/programmer for Microchip Flash DSC and

MCU devices. It debugs and programs PIC Flash

microcontrollers and dsPIC DSCs with the powerful,

yet easy-to-use graphical user interface of the

MPLAB IDE.

simulating the PIC MCUs and dsPIC DSCs on an

instruction level. On any given instruction, the data

areas can be examined or modified and stimuli can be

applied from a comprehensive stimulus controller.

Registers can be logged to files for further run-time

analysis. The trace buffer and logic analyzer display

extend the power of the simulator to record and track

program execution, actions on I/O, most peripherals

and internal registers.

The MPLAB ICD 3 In-Circuit Debugger probe is

connected to the design engineer’s PC using a high-

speed USB 2.0 interface and is connected to the target

with a connector compatible with the MPLAB ICD 2 or

MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3

supports all MPLAB ICD 2 headers.

The MPLAB X SIM Software Simulator fully supports

symbolic debugging using the MPLAB XC Compilers,

and the MPASM and MPLAB Assemblers. The

software simulator offers the flexibility to develop and

debug code outside of the hardware laboratory

environment, making it an excellent, economical

software development tool.

24.9 PICkit 3 In-Circuit Debugger/

Programmer

The MPLAB PICkit

3

allows debugging and

programming of PIC and dsPIC Flash microcontrollers

at a most affordable price point using the powerful

graphical user interface of the MPLAB IDE. The

MPLAB PICkit 3 is connected to the design engineer’s

PC using a full-speed USB interface and can be

connected to the target via a Microchip debug (RJ-11)

connector (compatible with MPLAB ICD 3 and MPLAB

REAL ICE). The connector uses two device I/O pins

and the Reset line to implement in-circuit debugging

and In-Circuit Serial Programming™ (ICSP™).

24.7 MPLAB REAL ICE In-Circuit

Emulator System

The MPLAB REAL ICE In-Circuit Emulator System is

Microchip’s next generation high-speed emulator for

Microchip Flash DSC and MCU devices. It debugs and

programs all 8, 16 and 32-bit MCU, and DSC devices

with the easy-to-use, powerful graphical user interface of

the MPLAB X IDE.

The emulator is connected to the design engineer’s

PC using a high-speed USB 2.0 interface and is

connected to the target with either a connector

compatible with in-circuit debugger systems (RJ-11)

or with the new high-speed, noise tolerant, Low-

Voltage Differential Signal (LVDS) interconnection

(CAT5).

24.10 MPLAB PM3 Device Programmer

The MPLAB PM3 Device Programmer is a universal,

CE compliant device programmer with programmable

voltage verification at

VDDMIN and VDDMAX for

maximum reliability. It features a large LCD display

(128 x 64) for menus and error messages, and a

modular, detachable socket assembly to support

various package types. The ICSP cable assembly is

included as a standard item. In Stand-Alone mode, the

MPLAB PM3 Device Programmer can read, verify and

program PIC devices without a PC connection. It can

also set code protection in this mode. The MPLAB PM3

connects to the host PC via an RS-232 or USB cable.

The MPLAB PM3 has high-speed communications and

optimized algorithms for quick programming of large

memory devices, and incorporates an MMC card for file

storage and data applications.

The emulator is field upgradable through future firmware

downloads in MPLAB X IDE. MPLAB REAL ICE offers

significant advantages over competitive emulators

including full-speed emulation, run-time variable

watches, trace analysis, complex breakpoints, logic

probes, a ruggedized probe interface and long (up to

three meters) interconnection cables.

 2015-2018 Microchip Technology Inc.

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24.11 Demonstration/Development

Boards, Evaluation Kits and

Starter Kits

24.12 Third-Party Development Tools

Microchip also offers a great collection of tools from

third-party vendors. These tools are carefully selected

to offer good value and unique functionality.

A wide variety of demonstration, development and

evaluation boards for various PIC MCUs and dsPIC

DSCs allows quick application development on fully

functional systems. Most boards include prototyping

areas for adding custom circuitry and provide

application firmware and source code for examination

and modification.

• Device Programmers and Gang Programmers

from companies, such as SoftLog and CCS

• Software Tools from companies, such as Gimpel

and Trace Systems

• Protocol Analyzers from companies, such as

Saleae and Total Phase

The boards support a variety of features, including LEDs,

temperature sensors, switches, speakers, RS-232

interfaces, LCD displays, potentiometers and additional

EEPROM memory.

• Demonstration Boards from companies, such as

MikroElektronika, Digilent and Olimex

®

• Embedded Ethernet Solutions from companies,

®

such as EZ Web Lynx, WIZnet and IPLogika

The demonstration and development boards can be

used in teaching environments, for prototyping custom

circuits and for learning about various microcontroller

applications.

In addition to the PICDEM™ and dsPICDEM™

demonstration/development board series of circuits,

Microchip has

a

line of evaluation kits and

demonstration software for analog filter design,

®

K

EEL

OQ security ICs, CAN, IrDA^®, PowerSmart

battery management, SEEVAL^®evaluation system,

Sigma-Delta ADC, flow rate sensing, plus many more.

Also available are starter kits that contain everything

needed to experience the specified device. This usually

includes a single application and debug capability, all

on one board.

Check the Microchip web page (www.microchip.com)

for the complete list of demonstration, development

and evaluation kits.

DS70005208E-page 264

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dsPIC33EPXXGS202 FAMILY

25.0 ELECTRICAL CHARACTERISTICS

This section provides an overview of the dsPIC33EPXXGS202 family electrical characteristics. Additional information

will be provided in future revisions of this document as it becomes available.

Absolute maximum ratings for the dsPIC33EPXXGS202 family are listed below. Exposure to these maximum rating

conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other

conditions above the parameters indicated in the operation listings of this specification, is not implied.

(1)

Absolute Maximum Ratings

Ambient temperature under bias.............................................................................................................-40°C to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on VDD with respect to VSS .......................................................................................................... -0.3V to +4.0V

(3)

Voltage on any pin that is not 5V tolerant with respect to VSS ..................................................... -0.3V to (VDD + 0.3V)

(3)

Voltage on any 5V tolerant pin with respect to VSS when VDD  3.0V ................................................... -0.3V to +5.5V

(3)

Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V ................................................... -0.3V to +3.6V

Maximum current out of VSS pin ...........................................................................................................................300 mA

(2)

Maximum current into VDD pin ...........................................................................................................................300 mA

Maximum current sunk/sourced by any 4x I/O pin..................................................................................................15 mA

Maximum current sunk/sourced by any 8x I/O pin..................................................................................................25 mA

(2)

Maximum current sunk by all ports ....................................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those, or any other conditions

above those indicated in the operation listings of this specification, is not implied. Exposure to maximum

rating conditions for extended periods may affect device reliability.

2: Maximum allowable current is a function of device maximum power dissipation (see Table 25-2).

3: See the “Pin Diagrams” section for the 5V tolerant pins.

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25.1 DC Characteristics

TABLE 25-1: OPERATING MIPS vs. VOLTAGE

Maximum MIPS

V

DD Range

Temperature Range

(in °C)

Characteristic

(in Volts)

dsPIC33EPXXGS202 Family

(1)

—

3.0V to 3.6V

-40°C to +85°C

-40°C to +125°C

70

60

Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators)

may have degraded performance. Device functionality is tested but not characterized. Refer to

Parameter BO10 in Table 25-13 for the minimum and maximum BOR values.

TABLE 25-2: THERMAL OPERATING CONDITIONS

Rating

Industrial Temperature Devices

Symbol

Min.

Typ.

Max.

Unit

Operating Junction Temperature Range

Operating Ambient Temperature Range

T

J

-40

—

+125

+85

°C

TA

Extended Temperature Devices

Operating Junction Temperature Range

Operating Ambient Temperature Range

T

J

-40

—

+140

+125

°C

TA

Power Dissipation:

Internal Chip Power Dissipation:

INT = VDD x (IDD –  IOH

I/O Pin Power Dissipation:

P

)

P

D

P

INT + P

I

/

O

W

I/O =  ({VDD – VOH} x IOH) +  (VOL x IOL

)

Maximum Allowed Power Dissipation

P

DMAX

(TJ – TA)/JA

TABLE 25-3: THERMAL PACKAGING CHARACTERISTICS

Characteristic

Symbol

Typ.

Max.

Unit

Notes

Package Thermal Resistance, 28-Pin QFN-S

Package Thermal Resistance, 28-Pin UQFN

Package Thermal Resistance, 28-Pin SOIC

Package Thermal Resistance, 28-Pin SSOP

JA

30.0

26.0

69.7

71.0

—

°C/W

1

Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

DS70005208E-page 266

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dsPIC33EPXXGS202 FAMILY

TABLE 25-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V⁽¹⁾

(unless otherwise stated)

Operating temperature -40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symbol

No.

Characteristic

Min.

Typ.

Max. Units

Conditions

Operating Voltage

DC10

DC12

DC16

V

DD

Supply Voltage

RAM Data Retention Voltage⁽²⁾

DD Start Voltage

3.0

2.0

—

3.6

—

V

DR

POR

V

VSS

to Ensure Internal

Power-on Reset Signal

DC17 SVDD

VDD Rise Rate

1.0

—

V/ms 0V-3V in 3 ms

to Ensure Internal

Power-on Reset Signal

Note 1: Device is functional at VBORMIN < VDD < VDDMIN. Analog modules (ADC, PGAs and comparators) may

have degraded performance. Device functionality is tested but not characterized. Refer to

Parameter BO10 in Table 25-13 for the minimum and maximum BOR values.

2: This is the limit to which VDD may be lowered without losing RAM data.

TABLE 25-5: FILTER CAPACITOR (CEFC) SPECIFICATIONS

Standard Operating Conditions (unless otherwise stated):

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

Symbol

Characteristics

Min.

Typ.

Max.

Units

Comments

CEFC

External Filter Capacitor

Value

4.7

10

—

F

Capacitor must have a low

series resistance (<1 Ohm)

(1)

Note 1: Typical VCAP Voltage = 1.8V when VDD  VDDMIN

.

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TABLE 25-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD

)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Parameter

Typ.

Max.

Units

Conditions

No.

(1)

Operating Current (IDD

)

DC20d

DC20a

DC20b

DC20c

DC22d

DC22a

DC22b

DC22c

DC24d

DC24a

DC24b

DC24c

DC25d

DC25a

DC25b

DC25c

DC26d

DC26a

DC26b

Note 1:

5

10

15

20

28

35

mA

-40°C

5

+25°C

+85°C

+125°C

-40°C

3.3V

10 MIPS

5

10

15

20

30

+25°C

+85°C

+125°C

-40°C

20 MIPS

40 MIPS

+25°C

+85°C

+125°C

-40°C

+25°C

+85°C

+125°C

-40°C

3.3V

60 MIPS

70 MIPS

+25°C

+85°C

I

DD is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption. The test conditions for all IDD measurements are as follows:

• Oscillator is configured in EC mode with PLL, OSC1 is driven with external square wave from

rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required)

• CLKO is configured as an I/O input pin in the Configuration Word

• All I/O pins are configured as outputs and driving low

• MCLR = VDD, WDT and FSCM are disabled

• CPU, SRAM, program memory and data memory are operational

• No peripheral modules are operating or being clocked (defined PMDx bits are all ones)

• CPU executing:

while(1)

{

NOP();

}

• JTAG is disabled

DS70005208E-page 268

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TABLE 25-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE

)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Parameter

Typ.

Max.

Units

Conditions

No.

(1)

Idle Current (IIDLE

DC40d

DC40a

DC40b

DC40c

)

1

3

5

7

9

3

mA

-40°C

+25°C

+85°C

+125°C

-40°C

3.3V

10 MIPS

3

DC42d

DC42a

DC42b

DC42c

5

+25°C

+85°C

+125°C

-40°C

20 MIPS

40 MIPS

5

DC44d

DC44a

DC44b

DC44c

DC45d

DC45a

DC45b

DC45c

DC46d

DC46a

DC46b

7

+25°C

+85°C

+125°C

-40°C

7

9

+25°C

+85°C

+125°C

-40°C

3.3V

60 MIPS

70 MIPS

9

12

+25°C

+85°C

Note 1: Base Idle current (IIDLE) is measured as follows:

•

CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with

external square wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required)

•

CLKO is configured as an I/O input pin in the Configuration Word

All I/O pins are configured as outputs and driving low

MCLR = VDD, WDT and FSCM are disabled

No peripheral modules are operating or being clocked (defined PMDx bits are all ones)

The NVMSIDL bit (NVMCON<12>) = 1(i.e., Flash regulator is set to standby while the device is in

Idle mode)

•

The VREGSF bit (RCON<11>) = 0(i.e., Flash regulator is set to standby while the device is in Sleep

mode)

JTAG is disabled

 2015-2018 Microchip Technology Inc.

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TABLE 25-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD

)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter

Typ.

Max.

Units

Conditions

No.

(1)

Power-Down Current (IPD

)

DC60d

DC60a

DC60b

DC60c

Note 1:

10

16

30

60

A

-40°C

+25°C

+85°C

+125°C

3.3V

60

300

800

300

I

PD (Sleep) current is measured as follows:

•

CPU core is off, oscillator is configured in EC mode and external clock is active; OSC1 is driven with

external square wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required)

CLKO is configured as an I/O input pin in the Configuration Word

•

All I/O pins are configured as output and driving low.

MCLR = VDD, WDT and FSCM are disabled

All peripheral modules are disabled (PMDx bits are all set)

The VREGS bit (RCON<8>) = 0(i.e., core regulator is set to standby while the device is in Sleep

mode)

•

The VREGSF bit (RCON<11>) = 0(i.e., Flash regulator is set to standby while the device is in Sleep

mode)

JTAG is disabled

(1)

TABLE 25-9: DC CHARACTERISTICS: WATCHDOG TIMER DELTA CURRENT (IWDT

)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Parameter No.

Typ.

Max.

Units

Conditions

DC61d

DC61a

DC61b

DC61c

1

2

3

5

A

-40°C

+25°C

+85°C

+125°C

3.3V

Note 1: The IWDT current is the additional current consumed when the module is enabled. This current should be

added to the base IPD current. All parameters are characterized but not tested during manufacturing.

DS70005208E-page 270

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dsPIC33EPXXGS202 FAMILY

TABLE 25-10: DC CHARACTERISTICS: DOZE CURRENT (IDOZE

)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Doze

Ratio

Parameter No.

Typ.

Max.

Units

Conditions

(1)

Doze Current (IDOZE

)

(2)

DC73a

15

7

20

9

1:2

1:128

1:2

mA

-40°C

+25°C

+85°C

+125°C

3.3V

F

OSC = 140 MHz

OSC = 120 MHz

DC73g

(2)

DC70a

15

7

20

9

DC70g

1:128

1:2

(2)

DC71a

15

7

20

9

DC71g

1:128

1:2

(2)

DC72a

15

7

20

9

DC72g

1:128

Note 1:

IDOZE is primarily a function of the operating voltage and frequency. Other factors, such as I/O pin loading

and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact

on the current consumption. The test conditions for all IDOZE measurements are as follows:

•

Oscillator is configured in EC mode and external clock is active, OSC1 is driven with external square

wave from rail-to-rail (EC Clock Overshoot/Undershoot < 250 mV required)

•

CLKO is configured as an I/O input pin in the Configuration Word

All I/O pins are configured as outputs and driving low

MCLR = VDD, WDT and FSCM are disabled

CPU, SRAM, program memory and data memory are operational

No peripheral modules are operating or being clocked (defined PMDx bits are all ones)

CPU executing:

while(1)

{

NOP();

}

•

JTAG is disabled

2: These parameters are characterized but not tested in manufacturing.

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TABLE 25-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

-40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

A

Param

Symbol

No.

Characteristic

Input Low Voltage

Min.

Typ.⁽¹⁾Max.

Units

Conditions

VIL

DI10

DI18

DI19

Any I/O Pin and MCLR

I/O Pins with SDA1, SCL1

Input High Voltage

VSS

—

0.2 VDD

0.3 VDD

0.8

V

SMBus disabled

SMBus enabled

VIH

(4)

DI20

I/O Pins Not 5V Tolerant

0.8 VDD

—

V

DD

V

I/O Pins 5V Tolerant and

5.5

(4)

MCLR

5V Tolerant I/O Pins with

0.8 VDD

2.1

—

V

SMBus disabled

(4)

SDA1, SCL1

(4)

5V I/O Pins with SDA1, SCL1

—

V

SMBus enabled

SMBus disabled

I/O Pins with SDA1, SCL1 Not 0.8 VDD

VDD

(4)

5V Tolerant

I/O Pins with SDA1, SCL1 Not

5V Tolerant

2.1

50

—

250

50

V

DD

V

SMBus enabled

(4)

DI30

DI31

I

CNPU

CNPD

Input Change Notification

Pull-up Current

600

—

A

V

DD = 3.3V, VPIN = VSS

DD = 3.3V, VPIN = VDD

Input Change Notification

Pull-Down Current⁽⁵⁾

V

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current can be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.

5:

6:

V

IL Source < (VSS – 0.3). Characterized but not tested.

IH source > (VDD + 0.3) for non-5V tolerant pins only.

V

7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any

“positive” input injection current.

8: |Injection Currents| > 0 can affect the ADC results by approximately 4-6 counts.

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,

provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS70005208E-page 272

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TABLE 25-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ.⁽¹⁾Max.

Units

Conditions

I

IL

Input Leakage Current^(2,3)

(4)

DI50

DI51

I/O Pins 5V Tolerant

-1

—

+1

A

VSS  VPIN  VDD,

pin at high-impedance

(4)

I/O Pins Not 5V Tolerant

VSS  VPIN  VDD,

pin at high-impedance,

-40°C  T  +85°C

A

(4)

DI51a

DI51b

DI51c

I/O Pins Not 5V Tolerant

-1

—

+1

A

Analog pins shared with

external reference pins,

-40°C  TA  +85°C

(4)

I/O Pins Not 5V Tolerant

VSS  VPIN  VDD,

pin at high-impedance,

-40°C  T  +125°C

A

(4)

I/O Pins Not 5V Tolerant

Analog pins shared with

external reference pins,

-40°C  T

A

 +125°C

SS VPIN VDD

SS VPIN VDD

DI55

DI56

MCLR

OSC1

-5

—

+5

A

V

,

XT and HS modes

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current can be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.

5:

6:

V

IL Source < (VSS – 0.3). Characterized but not tested.

IH source > (VDD + 0.3) for non-5V tolerant pins only.

V

7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any

“positive” input injection current.

8: |Injection Currents| > 0 can affect the ADC results by approximately 4-6 counts.

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,

provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

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TABLE 25-11: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ.⁽¹⁾Max.

Units

Conditions

I

ICL

Input Low Injection Current

(5,8)

DI60a

DI60b

0

—

-5

mA All pins except VDD, VSS,

AVDD, AVSS, MCLR, VCAP

and RB7

I

ICH

Input High Injection Current

(6,7,8)

0

+5

mA All pins except VDD, VSS

,

AVDD, AVSS, MCLR, VCAP

,

RB7 and all 5V tolerant

(7)

pins

IICT

Total Input Injection Current

(7)

DI60c

(sum of all I/O and control

pins)

-20

—

+20

mA Absolute instantaneous

sum of all ± input injection

currents from all I/O pins

( | IICL | + | IICH | )  IICT

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified

levels represent normal operating conditions. Higher leakage current can be measured at different input

voltages.

3: Negative current is defined as current sourced by the pin.

4: See the “Pin Diagrams” section for the 5V tolerant I/O pins.

5:

6:

V

IL Source < (VSS – 0.3). Characterized but not tested.

IH source > (VDD + 0.3) for non-5V tolerant pins only.

V

7: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any

“positive” input injection current.

8: |Injection Currents| > 0 can affect the ADC results by approximately 4-6 counts.

9: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted,

provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not

exceed the specified limit. Characterized but not tested.

DS70005208E-page 274

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TABLE 25-12: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

DC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param. Symbol

Characteristic

Min.⁽¹⁾Typ.

Max. Units

Conditions

DO10

DO20

V

OL

Output Low Voltage

4x Sink Driver Pins

—

0.4

V

I

DD = 3.3V,

OL  6 mA, -40°C  T

OL  5 mA, +85°C < T

DD = 3.3V,

OL  12 mA, -40°C  T

OL  8 mA, +85°C < T

(2)

A  +85°C,

A

 +125°C

Output Low Voltage

—

0.4

V

I

(3)

8x Sink Driver Pins

A

 +85°C,

A  +125°C

VOH

Output High Voltage

4x Source Driver Pins

2.4

—

V

I

OH  -10 mA, VDD = 3.3V

(2)

(3)

(2)

Output High Voltage

8x Source Driver Pins

I

OH  -15 mA, VDD = 3.3V

DO20A VOH

1

Output High Voltage

4x Source Driver Pins

1.5

2.0

3.0

1.5

2.0

3.0

—

V

I

OH  -14 mA, VDD = 3.3V

OH  -12 mA, VDD = 3.3V

OH  -7 mA, VDD = 3.3V

OH  -22 mA, VDD = 3.3V

OH  -18 mA, VDD = 3.3V

OH  -10 mA, VDD = 3.3V

Output High Voltage

8x Source Driver Pins

(3)

Note 1: Parameters are for design guidance only and are not tested in manufacturing.

2: 4x Drive Pins – RA<1:0>, RB1, RB<10:9>.

3: 8x Drive Pins – MCLR, RA<4:2>, RB0, RB<8:2>, RB<15:11>.

TABLE 25-13: ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)⁽¹⁾

Operating temperature -40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  T

Units

V

A  +125°C for Extended

Param

Symbol

No.

Characteristic

Min.⁽²⁾

Typ.

Max.

Conditions

BO10

VBOR

BOR Event on VDD Transition

High-to-Low

2.65

—

2.95

VDD (Notes 2, 3)

Note 1: Device is functional at VBORMIN < VDD < VDDMIN, but will have degraded performance. Device functionality

is tested, but not characterized. Analog modules (ADC, PGAs and comparators) may have degraded

performance.

2: Parameters are for design guidance only and are not tested in manufacturing.

3: The VBOR specification is relative to VDD

.

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TABLE 25-14: DC CHARACTERISTICS: PROGRAM MEMORY

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

-40°C  T

DC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

A

Param

Symbol

No.

Characteristic

Min. Typ.⁽¹⁾Max. Units

Conditions

Program Flash Memory

D130

D131

D132b

D134

E

V

P

Cell Endurance

10,000

3.0

—

3.6

—

E/W -40C to +125C

PR

PEW

VDD for Read

V

VDD for Self-Timed Write

3.0

TRETD

Characteristic Retention

20

Year Provided no other specifications

are violated, -40C to +125C

D135

I

DDP

Supply Current during

Programming

—

10

—

mA

(2)

D136

PEAK

Instantaneous Peak Current

During Start-up

—

150

20.1

20.3

47.3

47.9

679

687

D137a

D137b

D138a

D138b

D139a

D139b

T

PE

Page Erase Time

Word Write Cycle Time

Row Write Time

19.7

19.5

46.5

46.0

667

660

ms

µs

TPE = 146893 FRC Cycles,

TA

= +85°C (Note 3)

TPE = 146893 FRC Cycles,

T

A

= +125°C (Note 3)

WW = 346 FRC Cycles,

= +85°C (Note 3)

WW = 346 FRC Cycles,

= +125°C (Note 3)

RW = 4965 FRC Cycles,

= +85°C (Note 3)

RW = 4965 FRC Cycles,

= +125°C (Note 3)

T

WW

T

TA

T

WW

T

TA

T

RW

T

TA

T

RW

Row Write Time

T

TA

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

2: Parameters are for design guidance only and are not tested in manufacturing.

3: Other conditions: FRC = 7.37 MHz, TUN<5:0> = 011111(for Min.), TUN<5:0> = 100000(for Max.). This

parameter depends on the FRC accuracy (see Table 25-20) and the value of the FRC Oscillator Tuning

register (see Register 8-4). For complete details on calculating the Minimum and Maximum time, see

Section 5.3 “Programming Operations”

.

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25.2 AC Characteristics and Timing

Parameters

This section defines the dsPIC33EPXXGS202 family

AC characteristics and timing parameters.

TABLE 25-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

AC CHARACTERISTICS

-40°C  T

A

Operating voltage VDD range as described in Section 25.1 “DC

Characteristics”

.

FIGURE 25-1:

Load Condition 1 – for all pins except OSC2

DD/2

LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 2 – for OSC2

V

CL

R

L

VSS

CL

R

C

L

= 464

= 50 pF for all pins except OSC2

15 pF for OSC2 output

VSS

TABLE 25-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Param

Symbol

Characteristic

Min.

Typ. Max. Units

Conditions

No.

DO50

COSCO

OSC2 Pin

—

15

pF In XT and HS modes, when

external clock is used to drive

OSC1

DO56

DO58

C

IO

B

All I/O Pins and OSC2

SCL1, SDA1

—

50

pF EC mode

2

C

400

pF In I C mode

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FIGURE 25-2:

EXTERNAL CLOCK TIMING

Q1

Q2

Q3

Q4

Q1

Q2

Q3

Q4

OSC1

OS20

OS30 OS30

OS31 OS31

OS25

CLKO

OS41

OS40

TABLE 25-17: EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symb

No.

Characteristic

Min.

Typ.⁽¹⁾

Max.

Units

Conditions

OS10

F

IN

External CLKI Frequency

(External clocks allowed only

in EC and ECPLL modes)

DC

—

60

MHz EC

Oscillator Crystal Frequency

3.5

10

—

10

40

MHz XT

MHz HS

OS20

OS25

T

OSC

T

OSC = 1/FOSC

8.33

7.14

—

DC

ns

+125°C

TOSC = 1/FOSC

+85°C

+125°C

+85°C

EC

(2)

TCY

Instruction Cycle Time

16.67

DC

14.28

DC

OS30

OS31

TosL, External Clock in (OSC1)

TosH High or Low Time

0.45 x TOSC

0.55 x TOSC

TosR, External Clock in (OSC1)

TosF Rise or Fall Time

—

20

ns

EC

(3,4)

OS40

OS41

OS42

TckR CLKO Rise Time

—

5.2

12

—

ns

(3,4)

TckF

CLKO Fall Time

GM

External Oscillator

Transconductance

mA/V HS, VDD = 3.3V,

= +25°C

mA/V XT, VDD = 3.3V,

= +25°C

(4)

T

A

—

6

—

TA

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

2: Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values

are based on characterization data for that particular oscillator type, under standard operating conditions,

with the device executing code. Exceeding these specified limits may result in an unstable oscillator

operation and/or higher than expected current consumption. All devices are tested to operate at

“Minimum” values with an external clock applied to the OSC1 pin. When an external clock input is used,

the “Maximum” cycle time limit is “DC” (no clock) for all devices.

3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.

4: Parameters are for design guidance only and are not tested in manufacturing.

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TABLE 25-18: PLL CLOCK TIMING SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symbol

No.

Characteristic

Min.

Typ.⁽¹⁾

Max.

Units

Conditions

OS50

FPLLI

PLL Voltage Controlled Oscillator

(VCO) Input Frequency Range

0.8

—

8.0

MHz ECPLL, XTPLL modes

OS51

OS52

OS53

F

VCO

On-Chip VCO System Frequency 120

—

340

3.1

3

MHz

ms

%

TLOCK

PLL Start-up Time (Lock Time)

0.9

-3

1.5

0.5

(2)

D

CLK

CLKO Stability (Jitter)

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only

and are not tested in manufacturing.

2: This jitter specification is based on clock cycle-by-clock cycle measurements. To get the effective jitter for

individual time bases, or communication clocks used by the application, use the following formula:

D

CLK

Effective Jitter = -------------------------------------------------------------------------------------------

F

OSC

--------------------------------------------------------------------------------------

Time Base or Communication Clock

For example, if FOSC = 120 MHz and the SPI1 Bit Rate = 10 MHz, the effective jitter is as follows:

D

CLK

D

CLK

DCLK

3.464

Effective Jitter = ------------- = ------------- = -------------

120

--------

10

12

TABLE 25-19: AUXILIARY PLL CLOCK TIMING SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symbol

No.

Characteristic

Min

Typ.⁽¹⁾

Max

Units

Conditions

OS56

OS57

OS58

F

HPOUT On-Chip 16x PLL CCO

Frequency

112

118

120

MHz

FHPIN

On-Chip 16x PLL Phase

Detector Input Frequency

7.0

—

7.37

—

7.5

10

MHz

µs

TSU

Frequency Generator Lock

Time

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only

and are not tested in manufacturing.

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TABLE 25-20: INTERNAL FRC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Characteristic

Min.

Typ.

Max.

Units

Conditions

No.

Internal FRC Accuracy @ FRC Frequency = 7.37 MHz^(1,2)

F20a

FRC

-2

-0.9

-2

0.5

1

+2

+0.9

+2

%

-40°C  T

-10°C  T

+85°C  T

A

-10°C

VDD = 3.0-3.6V

A

+85°C

F20b

FRC

A

 +125°C

Note 1: Frequency is calibrated at +25°C and 3.3V. TUNx bits can be used to compensate for temperature drift.

2: Over the lifetime of the 28-Lead 4x4 UQFN package device, the internal FRC accuracy could vary

between ±4%.

TABLE 25-21: INTERNAL LPRC ACCURACY

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

Characteristic

Min.

Typ.

Max.

Units

Conditions

LPRC @ 32.768 kHz⁽¹⁾

F21a LPRC

-30

-20

-30

—

+30

+20

+30

%

-40°C  T

-10°C  T

+85°C  T

A

 -10°C

V

DD = 3.0-3.6V

A

 +85°C

DD = 3.0-3.6V

F21b LPRC

A

 +125°C

Note 1: This is the change of the LPRC frequency as VDD changes.

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FIGURE 25-3:

I/O TIMING CHARACTERISTICS

I/O Pin

(Input)

DI35

DI40

I/O Pin

(Output)

New Value

Old Value

DO31

DO32

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-22: I/O TIMING REQUIREMENTS

AC CHARACTERISTICS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

A

 +85°C for Industrial

-40°C  T

A

 +125°C for Extended

Param

No.

Symbol

Characteristic

Min.

Typ.⁽¹⁾Max. Units

Conditions

DO31

T

IO

R

F

Port Output Rise Time

—

20

2

5

10

—

ns

DO32

DI35

DI40

TIO

Port Output Fall Time

TINP

INTx Pin High or Low Time (input)

CNx High or Low Time (input)

—

TRBP

TCY

Note 1: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

FIGURE 25-4:

BOR AND MASTER CLEAR RESET TIMING CHARACTERISTICS

MCLR

T

MCLR

(SY20)

BOR

T

BOR

Various Delays (depending on configuration)

(SY30)

Reset Sequence

CPU Starts Fetching Code

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TABLE 25-23: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic⁽¹⁾

Min.

Typ.⁽²⁾

Max. Units

Conditions

SY00

SY10

SY12

T

PU

Power-up Period

—

400

1024 TOSC

—

600

—

s

TOST

Oscillator Start-up Time

—

TOSC = OSC1 Period

TWDT

Watchdog Timer

Time-out Period

0.81

1.22 ms WDTPRE = 0,

WDTPOST<3:0> = 0000,

using LPRC tolerances indicated in

F21a/F21b (see Table 25-21) at +85°C

3.25

—

4.88 ms WDTPRE = 1,

WDTPOST<3:0> = 0000,

using LPRC tolerances indicated in

F21a/F21b (see Table 25-21) at +85°C

SY13

TIOZ

I/O High-Impedance from 0.68

MCLR Low or Watchdog

Timer Reset

0.72

1.2

s

SY20

SY30

SY35

T

MCLR

BOR

MCLR Pulse Width (low)

BOR Pulse Width (low)

2

1

—

s

FSCM

Fail-Safe Clock Monitor

Delay

—

500

900

s -40°C to +85°C

SY36

T

VREG

Voltage Regulator

Standby-to-Active mode

Transition Time

—

30

s

SY37

SY38

T

OSCDFRC FRC Oscillator Start-up

—

29

70

s

Delay

TOSCDLPRC LPRC Oscillator Start-up

Delay

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

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FIGURE 25-5:

TIMER1-TIMER3 EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK

Tx10

Tx11

Tx15

Tx20

OS60

TMRx

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-24: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS⁽¹⁾

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symbol

No.

Characteristic⁽²⁾

T1CK High Synchronous

Min.

Typ.

Max.

Units

Conditions

TA10

TA11

TA15

T

TX

H

Greater of:

20 or

(TCY + 20)/N

—

ns

Must also meet

Parameter TA15,

N = Prescaler Value

(1, 8, 64, 256)

Time

mode

Asynchronous

35

—

ns

L

T1CK Low Synchronous

Greater of:

20 or

(TCY + 20)/N

Must also meet

Parameter TA15,

N = Prescaler Value

(1, 8, 64, 256)

Time

mode

Asynchronous

10

—

ns

P

T1CK Input Synchronous

Period mode

Greater of:

40 or

N = Prescale Value

(1, 8, 64, 256)

(2 TCY + 40)/N

OS60 Ft1

T1CK Oscillator Input

Frequency Range (oscillator

enabled by setting bit, TCS

(T1CON<1>))

DC

—

50

kHz

TA20

TCKEXTMRL Delay from External T1CK

0.75 TCY + 40

1.75 TCY + 40 ns

Clock Edge to Timer

Increment

Note 1: Timer1 is a Type A timer.

2: These parameters are characterized but not tested in manufacturing.

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TABLE 25-25: TIMER2 (TYPE B TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic⁽¹⁾

T2CK Synchronous

Min.

Typ.

Max.

Units

Conditions

TB10 TtxH

TB11 TtxL

TB15 TtxP

Greater of:

20 or

(TCY + 20)/N

—

ns

Must also meet

Parameter TB15,

N = Prescale Value

(1, 8, 64, 256)

High Time mode

T2CK Low Synchronous

Greater of:

20 or

(TCY + 20)/N

—

ns

Must also meet

Parameter TB15,

N = Prescale Value

(1, 8, 64, 256)

Time

mode

T2CK

Input

Synchronous

mode

Greater of:

40 or

(2 TCY + 40)/N

—

ns

N = Prescale Value

(1, 8, 64, 256)

Period

TB20

TCKEXTMRL Delay from External T2CK 0.75 TCY + 40

1.75 TCY + 40

Clock Edge to Timer

Increment

Note 1: These parameters are characterized but not tested in manufacturing.

TABLE 25-26: TIMER3 (TYPE C TIMER) EXTERNAL CLOCK TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

A  +125°C for Extended

-40°C  T

Param

No.

Symbol

TtxH

Characteristic⁽¹⁾

Min.

CY + 20

Typ.

Max.

Units

Conditions

TC10

TC11

TC15

T3CK

High Time

Synchronous

T

—

ns

Must also meet

Parameter TC15

TtxL

TtxP

T3CK

TCY + 20

—

ns

Must also meet

Parameter TC15

Low Time

T3CK

Input

Synchronous

with Prescaler

2 TCY + 40

N = Prescale Value

(1, 8, 64, 256)

Period

TC20

TCKEXTMRL Delay from External

0.75 TCY + 40

—

1.75 TCY + 40

ns

T3CK Clock Edge to

Timer Increment

Note 1: These parameters are characterized but not tested in manufacturing.

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FIGURE 25-6:

INPUT CAPTURE 1 (IC1) TIMING CHARACTERISTICS

IC1

IC10

IC11

IC15

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-27: INPUT CAPTURE 1 MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param.

No.

Symbol Characteristics⁽¹⁾

Min.

Max. Units

Conditions

IC10

IC11

IC15

T

CC

L

IC1 Input Low Time

IC1 Input High Time

IC1 Input Period

Greater of:

12.5 + 25 or

(0.5 TCY/N) + 25

—

ns

Must also meet

Parameter IC15

TCC

H

P

Greater of:

12.5 + 25 or

(0.5 TCY/N) + 25

Must also meet

Parameter IC15

N = Prescale Value

(1, 4, 16)

TCC

Greater of:

25 + 50 or

(1 TCY/N) + 50

Note 1: These parameters are characterized but not tested in manufacturing.

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FIGURE 25-7:

OUTPUT COMPARE 1 MODULE (OC1) TIMING CHARACTERISTICS

OC1

(Output Compare 1

or PWM Mode)

OC11

Note: Refer to Figure 25-1 for load conditions.

OC10

TABLE 25-28: OUTPUT COMPARE 1 MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

-40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

A

Param

Symbol

No.

Characteristic⁽¹⁾

Min.

Typ.

Max.

Units

Conditions

OC10 TccF

OC11 TccR

OC1 Output Fall Time

OC1 Output Rise Time

—

ns

See Parameter DO32

See Parameter DO31

Note 1: These parameters are characterized but not tested in manufacturing.

FIGURE 25-8:

OC1/PWMx MODULE TIMING CHARACTERISTICS

OC20

OCFA

OC1

OC15

TABLE 25-29: OC1/PWMx MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

-40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

A

Param

Symbol

No.

Characteristic⁽¹⁾

Min.

Typ.

Max.

CY + 20

Units

Conditions

OC15

T

FD

Fault Input to PWMx I/O

Change

—

T

ns

OC20

T

FLT

Fault Input Pulse Width

T

CY + 20

—

Note 1: These parameters are characterized but not tested in manufacturing.

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FIGURE 25-9:

HIGH-SPEED PWMx MODULE FAULT TIMING CHARACTERISTICS

MP30

Fault Input

(active-low)

MP20

PWMx

FIGURE 25-10:

HIGH-SPEED PWMx MODULE TIMING CHARACTERISTICS

MP11 MP10

PWMx

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-30: HIGH-SPEED PWMx MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

Symbol

No.

Characteristic⁽¹⁾

Min.

Typ.

Max.

Units

Conditions

MP10

MP11

MP20

T

FPWM

PWMx Output Fall Time

PWMx Output Rise Time

—

15

ns

See Parameter DO32

See Parameter DO31

TRPWM

T

FD

FH

Fault Input  to PWMx

I/O Change

MP30

T

Fault Input Pulse Width

15

—

ns

Note 1: These parameters are characterized but not tested in manufacturing.

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TABLE 25-31: SPI1 MAXIMUM DATA/CLOCK RATE SUMMARY

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Master

Transmit Only

(Half-Duplex)

Master

Slave

Maximum

Data Rate

Transmit/Receive Transmit/Receive

(Full-Duplex)

CKE

CKP

SMP

(Full-Duplex)

15 MHz

9 MHz

Table 25-31

—

0,1

1

0,1

0

0,1

1

—

Table 25-32

—

9 MHz

Table 25-33

—

0

1

15 MHz

11 MHz

15 MHz

11 MHz

—

Table 25-34

Table 25-35

Table 25-36

Table 25-37

1

0

1

0

1

0

FIGURE 25-11:

SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 0)

TIMING CHARACTERISTICS

SCK1

(CKP =

0

1

)

SP10

SP21

SP20

SP21

SCK1

(CKP =

SP35

MSb

Bit 14 - - - - - -1

LSb

SDO1

SP30, SP31

Note: Refer to Figure 25-1 for load conditions.

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FIGURE 25-12:

SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY, CKE = 1)

TIMING CHARACTERISTICS

SP36

SCK1

(CKP =

0

1

)

SP10

SP21

SP20

SP21

SCK1

(CKP =

SP35

MSb

Bit 14 - - - - - -1

SP30, SP31

LSb

SDO1

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-32: SPI1 MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

FscP

Characteristic⁽¹⁾

Min.

Typ.⁽²⁾Max.

Units

Conditions

SP10

SP20

Maximum SCK1 Frequency

SCK1 Output Fall Time

—

15

—

MHz (Note 3)

TscF

TscR

TdoF

TdoR

ns

See Parameter DO32

(Note 4)

SP21

SP30

SP31

SP35

SP36

SCK1 Output Rise Time

—

30

—

6

—

20

—

See Parameter DO31

(Note 4)

SDO1 Data Output Fall Time

SDO1 Data Output Rise Time

See Parameter DO32

(Note 4)

See Parameter DO31

(Note 4)

TscH2doV, SDO1 Data Output Valid After

TscL2doV SCK1 Edge

TdiV2scH, SDO1 Data Output Setup to

—

TdiV2scL

First SCK1 Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the clock generated in Master mode must not

violate this specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-13:

SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)

TIMING CHARACTERISTICS

SP36

SCK1

(CKP =

0

1

)

SP10

SP21

SP20

SP21

SCK1

(CKP =

SP35

MSb

Bit 14 - - - - - -1

LSb

SDO1

SDI1

SP30, SP31

SP40

MSb In

SP41

Bit 14 - - - -1

LSb In

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-33: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1)

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C

-40°C



T

TA

A



+85°C for Industrial

+125°C for Extended

Param

No.

(1)

(2)

Symbol

Characteristic

Min.

Typ.

Max.

Units

Conditions

SP10 FscP

SP20 TscF

Maximum SCK1 Frequency

SCK1 Output Fall Time

—

9

MHz

ns

(Note 3)

—

See Parameter DO32

(Note 4)

SP21 TscR

SP30 TdoF

SP31 TdoR

SCK1 Output Rise Time

—

30

—

6

—

20

—

ns

See Parameter DO31

(Note 4)

SDO1 Data Output Fall

Time

See Parameter DO32

(Note 4)

SDO1 Data Output Rise

Time

See Parameter DO31

(Note 4)

SP35 TscH2doV, SDO1 Data Output Valid

TscL2doV After SCK1 Edge

SP36 TdoV2sc, SDO1 Data Output Setup

TdoV2scL to First SCK1 Edge

—

SP40 TdiV2scH, Setup Time of SDI1 Data

TdiV2scL Input to SCK1 Edge

SP41 TscH2diL, Hold Time of SDI1 Data

TscL2diL Input to SCK1 Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 111 ns. The clock generated in Master mode must not violate this

specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-14:

SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)

TIMING CHARACTERISTICS

SCK1

(CKP =

0

1

)

SP10

SP21

SP20

SCK1

(CKP =

SP35 SP36

SP20

SP21

MSb

Bit 14 - - - - - -1

SP30, SP31

LSb In

LSb

SDO1

SDI1

SP30, SP31

MSb In

SP40 SP41

Bit 14 - - - -1

Note: Refer to Figure 25-1 for load conditions.

TABLE 25-34: SPI1 MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1)

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

A  +125°C for Extended

-40°C  T

Param

No.

(1)

(2)

Symbol

FscP

Characteristic

Min.

Typ.

Max.

Units

Conditions

SP10

SP20

SP21

SP30

SP31

SP35

SP36

SP40

SP41

Maximum SCK1 Frequency

SCK1 Output Fall Time

—

9

MHz -40°C to +125°C

(Note 3)

TscF

TscR

TdoF

TdoR

—

30

—

6

—

20

—

ns

See Parameter DO32

(Note 4)

SCK1 Output Rise Time

See Parameter DO31

(Note 4)

SDO1 Data Output Fall Time

SDO1 Data Output Rise Time

See Parameter DO32

(Note 4)

See Parameter DO31

(Note 4)

TscH2doV, SDO1 Data Output Valid

TscL2doV After SCK1 Edge

TdoV2scH, SDO1 Data Output Setup to

TdoV2scL First SCK1 Edge

—

TdiV2scH, Setup Time of SDI1 Data

TdiV2scL Input to SCK1 Edge

TscH2diL, Hold Time of SDI1 Data Input

TscL2diL

to SCK1 Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 111 ns. The clock generated in Master mode must not violate this

specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-15:

SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)

TIMING CHARACTERISTICS

SP60

SS1

SP52

SP50

SCK1

(CKP =

0

1

)

SP70

SP73

SP72

SCK1

(CKP =

SP36

SP35

SP72

SP73

SDO1

SDI1

MSb

Bit 14 - - - - - -1

LSb

SP30, SP31

Bit 14 - - - -1

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 25-1 for load conditions.

DS70005208E-page 292

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TABLE 25-35: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0)

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

(1)

(2)

Symbol

FscP

Characteristic

Min.

Typ.

Max.

Units

Conditions

SP70

SP72

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SP50

SP51

SP52

SP60

Maximum SCK1 Input

Frequency

—

Lesserof: MHz (Note 3)

F

P

or 15

—

TscF

TscR

TdoF

TdoR

SCK1 Input Fall Time

—

6

ns

See Parameter DO32

(Note 4)

SCK1 Input Rise Time

—

20

—

50

—

50

See Parameter DO31

(Note 4)

SDO1 Data Output Fall Time

SDO1 Data Output Rise Time

—

See Parameter DO32

(Note 4)

—

See Parameter DO31

(Note 4)

TscH2doV, SDO1 Data Output Valid After

TscL2doV SCK1 Edge

—

TdoV2scH, SDO1 Data Output Setup to

TdoV2scL First SCK1 Edge

30

—

TdiV2scH, Setup Time of SDI1 Data Input

30

TdiV2scL

TscH2diL, Hold Time of SDI1 Data Input

TscL2diL to SCK1 Edge

TssL2scH, SS1  to SCK1  or SCK1 

TssL2scL Input

to SCK1 Edge

30

120

TssH2doZ SS1  to SDO1 Output

10

1.5 TCY + 40

—

(Note 4)

High-Impedance

TscH2ssH, SS1 after SCK1 Edge

TscL2ssH

TssL2doV SDO1 Data Output Valid After

SS1 Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must

not violate this specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-16:

SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)

TIMING CHARACTERISTICS

SP60

SS1

SP52

SP50

SCK1

(CKP =

0

1

)

SP70

SP73

SP36

SP72

SCK1

(CKP =

SP35

SP72

SP73

MSb

Bit 14 - - - - - -1

LSb

SDO1

SDI1

SP30, SP31

Bit 14 - - - -1

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 25-1 for load conditions.

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TABLE 25-36: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0)

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

(1)

(2)

Symbol

FscP

Characteristic

Min.

Typ.

Max.

Units

Conditions

SP70

SP72

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SP50

SP51

SP52

SP60

Maximum SCK1 Input

Frequency

—

Lesser of: MHz (Note 3)

F

P

or 11

—

TscF

TscR

TdoF

TdoR

SCK1 Input Fall Time

—

6

ns

See ParameterDO32

(Note 4)

SCK1 Input Rise Time

—

20

—

50

—

50

See ParameterDO31

(Note 4)

SDO1 Data Output Fall Time

SDO1 Data Output Rise Time

—

See Parameter DO32

(Note 4)

—

See Parameter DO31

(Note 4)

TscH2doV, SDO1 Data Output Valid After

TscL2doV SCK1 Edge

—

TdoV2scH, SDO1 Data Output Setup to

TdoV2scL First SCK1 Edge

30

—

TdiV2scH, Setup Time of SDI1 Data Input

TdiV2scL to SCK1 Edge

30

TscH2diL, Hold Time of SDI1 Data Input

30

TscL2diL

to SCK1 Edge

TssL2scH, SS1  to SCK1  or SCK1 

120

TssL2scL Input

TssH2doZ SS1  to SDO1 Output

10

1.5 TCY + 40

—

(Note 4)

High-Impedance

TscH2ssH, SS1 after SCK1 Edge

TscL2ssH

TssL2doV SDO1 Data Output Valid after

SS1 Edge

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must not

violate this specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-17:

SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)

TIMING CHARACTERISTICS

SS1

SP50

SP52

SCK1

(CKP =

0

1

)

SP70

SP73

SP72

SP73

SCK1

(CKP =

SP35 SP36

MSb

SDO1

SDI1

Bit 14 - - - - - -1

SP30, SP31

Bit 14 - - - -1

LSb

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 25-1 for load conditions.

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TABLE 25-37: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0)

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

(1)

(2)

Symbol

FscP

Characteristic

Min.

Typ.

Max. Units

Conditions

SP70

SP72

Maximum SCK1 Input Frequency

SCK1 Input Fall Time

—

15

—

MHz (Note 3)

TscF

TscR

TdoF

TdoR

ns

See ParameterDO32

(Note 4)

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SP50

SP51

SP52

SCK1 Input Rise Time

—

6

—

20

—

50

—

See ParameterDO31

(Note 4)

SDO1 Data Output Fall Time

SDO1 Data Output Rise Time

—

See Parameter DO32

(Note 4)

—

See Parameter DO31

(Note 4)

TscH2doV, SDO1 Data Output Valid After

TscL2doV SCK1 Edge

—

TdoV2scH, SDO1 Data Output Setup to

TdoV2scL First SCK1 Edge

30

—

TdiV2scH, Setup Time of SDI1 Data Input

30

TdiV2scL

TscH2diL, Hold Time of SDI1 Data Input

TscL2diL to SCK1 Edge

TssL2scH, SS1  to SCK1  or SCK1 

TssL2scL Input

to SCK1 Edge

30

120

TssH2doZ SS1  to SDO1 Output

10

(Note 4)

High-Impedance

TscH2ssH, SS1 After SCK1 Edge

1.5 TCY + 40

TscL2ssH

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 66.7 ns. Therefore, the SCK1 clock generated by the master must

not violate this specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-18:

SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)

TIMING CHARACTERISTICS

SS1

SP50

SP52

SCK1

(CKP =

0

1

)

SP70

SP73

SP72

SP73

SCK1

(CKP =

SP35 SP36

MSb

SDO1

SDI1

Bit 14 - - - - - -1

SP30, SP31

Bit 14 - - - -1

LSb

SP51

MSb In

SP41

LSb In

SP40

Note: Refer to Figure 25-1 for load conditions.

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TABLE 25-38: SPI1 SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0)

TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

(1)

(2)

Symbol

FscP

Characteristic

Min.

Typ.

Max. Units

Conditions

SP70

SP72

Maximum SCK1 Input Frequency

SCK1 Input Fall Time

—

11

—

MHz (Note 3)

TscF

TscR

TdoF

TdoR

ns

See ParameterDO32

(Note 4)

SP73

SP30

SP31

SP35

SP36

SP40

SP41

SP50

SP51

SP52

SCK1 Input Rise Time

—

6

—

20

—

50

—

See ParameterDO31

(Note 4)

SDO1 Data Output Fall Time

SDO1 Data Output Rise Time

—

See Parameter DO32

(Note 4)

—

See Parameter DO31

(Note 4)

TscH2doV, SDO1 Data Output Valid After

TscL2doV SCK1 Edge

—

TdoV2scH, SDO1 Data Output Setup to

TdoV2scL First SCK1 Edge

30

—

TdiV2scH, Setup Time of SDI1 Data Input

30

TdiV2scL

TscH2diL, Hold Time of SDI1 Data Input

TscL2diL to SCK1 Edge

TssL2scH, SS1  to SCK1  or SCK1 

TssL2scL Input

to SCK1 Edge

30

120

TssH2doZ SS1  to SDO1 Output

10

(Note 4)

High-Impedance

TscH2ssH, SS1 After SCK1 Edge

1.5 TCY + 40

TscL2ssH

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated.

3: The minimum clock period for SCK1 is 91 ns. Therefore, the SCK1 clock generated by the master must

not violate this specification.

4: Assumes 50 pF load on all SPI1 pins.

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FIGURE 25-19:

I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCL1

IM31

IM34

IM30

IM33

SDA1

Stop

Condition

Start

Condition

Note: Refer to Figure 25-1 for load conditions.

FIGURE 25-20:

I2C1 BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20

IM21

IM11

IM10

SCL1

IM26

IM11

IM25

IM33

IM10

SDA1

In

IM40

IM45

SDA1

Out

Note: Refer to Figure 25-1 for load conditions.

DS70005208E-page 300

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TABLE 25-39: I2C1 BUS DATA TIMING REQUIREMENTS (MASTER MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symbol

No.

(4)

(1)

Characteristic

Min.

Max.

Units

Conditions

IM10

IM11

IM20

IM21

IM25

IM26

IM30

IM31

IM33

IM34

IM40

IM45

T

LO

:

SCL Clock Low Time 100 kHz mode

400 kHz mode

T

CY (BRG + 1)

—

s

ns

s

ns

s

pF

ns

T

(2)

1 MHz mode

T

—

HI:

SCL Clock High Time 100 kHz mode

400 kHz mode

T

—

T

—

(2)

1 MHz mode

T

—

F

:

SCL

SDA1 and SCL1 100 kHz mode

—

300

100

1000

300

—

C

B

is specified to be

Fall Time

from 10 to 400 pF

400 kHz mode

20 + 0.1 C

B

(2)

1 MHz mode

—

TR

:

SCL

SDA1 and SCL1 100 kHz mode

—

CB is specified to be

from 10 to 400 pF

Rise Time

400 kHz mode

20 + 0.1 C

B

(2)

1 MHz mode

—

250

100

40

0

TSU

:

DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

—

(2)

1 MHz mode

—

THD

:

DAT Data Input

Hold Time

100 kHz mode

400 kHz mode

—

0

0.9

—

(2)

1 MHz mode

0.2

TSU

:

STA Start Condition 100 kHz mode

T

CY (BRG + 1)

—

Only relevant for

Repeated Start

condition

Setup Time

400 kHz mode

T

—

(2)

1 MHz mode

T

—

THD

:

STA Start Condition 100 kHz mode

T

—

After this period, the

first clock pulse is

generated

Hold Time

400 kHz mode

T

—

(2)

1 MHz mode

T

—

TSU

:

STO Stop Condition 100 kHz mode

T

—

Setup Time

400 kHz mode

T

—

(2)

1 MHz mode

T

—

THD

:

STO Stop Condition 100 kHz mode

T

—

Hold Time

400 kHz mode

T

—

(2)

1 MHz mode

T

—

TAA

:

SCL Output Valid

from Clock

100 kHz mode

400 kHz mode

—

3500

1000

400

—

(2)

1 MHz mode

—

TBF

:

SDA Bus Free Time 100 kHz mode

4.7

1.3

0.5

—

Time the bus must be

free before a new

transmission can start

400 kHz mode

—

(2)

1 MHz mode

—

IM50

IM51

C

B

Bus Capacitive Loading

400

390

TPGD

Pulse Gobbler Delay

65

(Note 3)

2

Note 1: BRG is the value of the I C Baud Rate Generator.

2: Maximum Pin Capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).

3: Typical value for this parameter is 130 ns.

4: These parameters are characterized but not tested in manufacturing.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 301

dsPIC33EPXXGS202 FAMILY

FIGURE 25-21:

I2C1 BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCL1

IS31

IS34

IS30

IS33

SDA1

Stop

Condition

Start

Condition

FIGURE 25-22:

I2C1 BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20

IS11

IS21

IS10

IS26

SCL1

IS30

IS25

IS33

IS31

SDA1

In

IS45

IS40

SDA1

Out

DS70005208E-page 302

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

TABLE 25-40: I2C1 BUS DATA TIMING REQUIREMENTS (SLAVE MODE)

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature

-40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

Symbol

No.

(3)

Characteristic

Min.

Max. Units

Conditions

IS10

T

LO

:

SCL Clock Low Time 100 kHz mode

400 kHz mode

4.7

1.3

0.5

4.0

—

s

(1)

1 MHz mode

IS11

T

HI

:

SCL Clock High Time 100 kHz mode

Device must operate at a

minimum of 1.5 MHz

400 kHz mode

0.6

—

s

Device must operate at a

minimum of 10 MHz

(1)

1 MHz mode

0.5

—

300

100

1000

300

—

s

ns

s

ns

s

pF

ns

IS20

IS21

IS25

IS26

IS30

IS31

IS33

IS34

IS40

IS45

T

F

:

SCL

SDA1 and SCL1 100 kHz mode

—

CB

is specified to be from

Fall Time

10 to 400 pF

400 kHz mode

20 + 0.1 C

B

(1)

1 MHz mode

—

TR

:

SCL

SDA1 and SCL1 100 kHz mode

CB is specified to be from

10 to 400 pF

Rise Time

400 kHz mode

20 + 0.1 C

—

B

(1)

1 MHz mode

TSU

:

DAT Data Input

Setup Time

100 kHz mode

400 kHz mode

250

100

0

—

(1)

1 MHz mode

—

T

HD

:

DAT Data Input

Hold Time

100 kHz mode

400 kHz mode

—

0

0.9

0.3

—

(1)

1 MHz mode

0

TSU

:

STA Start Condition

Setup Time

100 kHz mode

400 kHz mode

4.7

0.6

0.25

4.0

0.6

0.25

4

Only relevant for Repeated

Start condition

—

(1)

1 MHz mode

—

T

HD

:

STA Start Condition

Hold Time

100 kHz mode

400 kHz mode

—

After this period, the first

clock pulse is generated

—

(1)

1 MHz mode

—

TSU

:

STO Stop Condition

Setup Time

100 kHz mode

400 kHz mode

—

0.6

0.25

4

—

(1)

1 MHz mode

—

T

HD

:

STO Stop Condition

Hold Time

100 kHz mode

400 kHz mode

—

0.6

0.25

0

—

(1)

1 MHz mode

TAA

:

SCL Output Valid from 100 kHz mode

3500

1000

350

—

Clock

400 kHz mode

0

(1)

1 MHz mode

0

T

BF

:

SDA Bus Free Time

100 kHz mode

400 kHz mode

4.7

1.3

0.5

—

Time the bus must be free

before a new transmission

can start

—

(1)

1 MHz mode

—

IS50

IS51

C

B

Bus Capacitive Loading

Pulse Gobbler Delay

400

390

T

PGD

65

(Note 2)

Note 1: Maximum Pin Capacitance = 10 pF for all I2C1 pins (for 1 MHz mode only).

2: Typical value for this parameter is 130 ns.

3: These parameters are characterized but not tested in manufacturing.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 303

dsPIC33EPXXGS202 FAMILY

FIGURE 25-23:

UART1 MODULE I/O TIMING CHARACTERISTICS

UA20

U1RX

U1TX

MSb In

UA10

Bits 6-1

LSb In

TABLE 25-41: UART1 MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +125°C

Param

Symbol

No.

(1)

(2)

Characteristic

Min. Typ.

Max. Units

Conditions

UA10

UA11

UA20

T

UABAUD

BAUD

CWF

UART1 Baud Time

66.67

—

15

—

ns

Mbps

ns

F

UART1 Baud Frequency

T

Start Bit Pulse Width to Trigger

UART1 Wake-up

500

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

TABLE 25-42: ANALOG CURRENT SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

AC CHARACTERISTICS

(unless otherwise stated)

Operating temperature -40°C  T

A

 +125°C

Conditions

Param

Symbol

No.

(1)

(2)

Characteristic

Min. Typ.

Max. Units

AVD01

I

DD

Analog Modules Current

Consumption

—

9

—

mA Characterized data with the

following modules enabled:

APLL, 5 ADC Cores, 2 PGAs

and 4 Analog Comparators

Note 1: These parameters are characterized but not tested in manufacturing.

2: Data in “Typ.” column is at 3.3V, +25°C unless otherwise stated. Parameters are for design guidance only

and are not tested.

DS70005208E-page 304

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

TABLE 25-43: ADC MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(4)

(unless otherwise stated)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

(3)

Symbol

Characteristics

Min.

Typical

Max.

Units

Conditions

Device Supply

AD01 AVDD

Module VDD Supply

Greater of:

—

Lesser of:

V

The difference between

AVDD supply and VDD

supply must not exceed

±300 mV at all times,

VDD – 0.3

VDD + 0.3

or 3.0

or 3.6

including device power-up

AD02 AVSS

Module VSS Supply

VSS

—

VSS + 0.3

V

Analog Input

AD12

AD14

AD15

V

INH-VINL Full-Scale Input Span

AVSS

—

AVDD

V

IN

Absolute Input Voltage

AVSS – 0.3

0

AVDD + 0.3

3.3

+

-

Pseudodifferential

Mode

V

IN- = (VR+ + VR-)/2

±150 mV

IN+ = (VR+ + VR-)/2

AD16

AD17

VIN

Pseudodifferential

Mode

0

—

3.3

—

V

±150 mV

R

IN

Recommended

—

100



For minimum sampling

Impedance of Analog

Voltage Source

time (Note 1)

AD66

VREF

1

Internal Voltage

1.176

1.2

1.224

V

Reference Source

ADC Accuracy: Pseudodifferential Input

AD20a Nr

AD21a INL

AD22a DNL

Resolution

12

bits

Integral Nonlinearity

> -4

> -1

—

< 4

< 1

LSb AVSS = 0V, AVDD = 3.3V

Pseudodifferential

Nonlinearity

LSb AVSS = 0V, AVDD = 3.3V

(Note 5)

AD23a GERR

AD24a EOFF

Gain Error

(Dedicated Core)

> -5

—

< 5

—

LSb AVSS = 0V, AVDD = 3.3V

Offset Error

(Dedicated Core)

LSb AVSS = 0V, AVDD = 3.3V

AD25a

—

Monotonicity

—

Guaranteed

Note 1: These parameters are not characterized or tested in manufacturing.

2: These parameters are characterized but not tested in manufacturing.

3: Characterized with a 1 kHz sine wave.

4: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

otherwise stated, module functionality is ensured, but not characterized.

5: No missing codes, limits are based on the characterization results.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 305

dsPIC33EPXXGS202 FAMILY

TABLE 25-43: ADC MODULE SPECIFICATIONS (CONTINUED)

Standard Operating Conditions: 3.0V to 3.6V

(4)

(unless otherwise stated)

Operating temperature -40°C  T

-40°C  T

AC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

A

Param

No.

(3)

Symbol

Characteristics

Min.

Typical

Max.

Units

Conditions

ADC Accuracy: Single-Ended Input

AD20b Nr

AD21b INL

AD22b DNL

Resolution

12

bits

Integral Nonlinearity

> -4

> -1

—

< 4

LSb AVSS = 0V, AVDD = 3.3V

Pseudodifferential

Nonlinearity

< 1.5

LSb AVSS = 0V, AVDD = 3.3V

(Note 5)

AD23b GERR

Gain Error

(Dedicated Core)

> -5

> -6

0

—

7

< 5

LSb AVSS = 0V, AVDD = 3.3V

Gain Error

(Shared Core)

LSb AVSS = 0V, AVDD = 3.3V,

-40°C  T

LSb AVSS = 0V, AVDD = 3.3V,

-85°C  T  +125°C

A  +85°C

< 6

A

AD24b EOFF

Offset Error

(Dedicated Core)

< 12

—

LSb AVSS = 0V, AVDD = 3.3V

Offset Error

(Shared Core)

0

7

LSb

AD25b

—

Monotonicity

—

Guaranteed

Dynamic Performance

AD31b SINAD

AD34b ENOB

Signal-to-Noise and

Distortion

63

—

> 65

—

dB (Notes 2, 3)

bits (Notes 2, 3)

Effective Number of bits

10.3

—

Note 1: These parameters are not characterized or tested in manufacturing.

2: These parameters are characterized but not tested in manufacturing.

3: Characterized with a 1 kHz sine wave.

4: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

otherwise stated, module functionality is ensured, but not characterized.

5: No missing codes, limits are based on the characterization results.

DS70005208E-page 306

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

TABLE 25-44: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS

Standard Operating Conditions: 3.0V to 3.6V

(2)

(unless otherwise stated)

(2)

AC CHARACTERISTICS

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Param

No.

(1)

Symbol

Characteristics

Min.

Typ.

Max.

Units

Conditions

Clock Parameters

14.28

Throughput Rate

3.25

AD50

AD51

T

AD

ADC Clock Period

ADC Core 0, 1, 2

—

ns

FTP

—

Msps 70 MHz ADC clock, 12 bits,

no pending conversions at time of

trigger

Note 1: These parameters are characterized but not tested in manufacturing.

2: The ADC module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

otherwise stated, module functionality is guaranteed, but not characterized.

TABLE 25-45: HIGH-SPEED ANALOG COMPARATOR MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

-40°C  T

(2)

AC/DC CHARACTERISTICS

A

 +85°C for Industrial

 +125°C for Extended

A

Param

No.

Symbol

Characteristic

Min.

Typ.

Max.

Units

Comments

CM10

CM11

V

IOFF

ICM

Input Offset Voltage

Input Common-Mode

Voltage Range

-35

0

±5

—

+35

mV

V

AVDD

(1)

CM13 CMRR Common-Mode

Rejection Ratio

60

—

dB

CM14

TRESP

Large Signal Response

15

ns V+ input step of 100 mV while

V- input is held at AVDD/2. Delay

measured from analog input pin to

PWMx output pin.

CM15

CM16

V

HYST

Input Hysteresis

5

10

—

20

1

mV Depends on HYSSEL<1:0>

µs

TON

Comparator Enabled to

Valid Output

—

Note 1: These parameters are for design guidance only and are not tested in manufacturing.

2: The comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

otherwise stated, module functionality is tested, but not characterized.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 307

dsPIC33EPXXGS202 FAMILY

TABLE 25-46: DACx MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

Operating temperature -40°C  T

(2)

AC/DC CHARACTERISTICS

A

 +85°C for Industrial

-40°C  TA  +125°C for Extended

Param

No.

Symbol

Characteristic

Resolution

Min.

Typ.

Max.

Units

Comments

DA02

DA03

DA04

DA05

DA06

DA07

CVRES

INL

12

-12

±0.5

3

bits

LSb

%

Integral Nonlinearity Error

Differential Nonlinearity Error

Offset Error

—

-1.8

-8

—

1.8

15

—

DNL

EOFF

EG

Gain Error

-0.8

—

-0.4

700

(1)

TSET

Settling Time

—

ns

Output with 2% of desired

output voltage with a

10-90% or 90-10% step

Note 1: Parameters are for design guidance only and are not tested in manufacturing.

2: The DACx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

otherwise stated, module functionality is tested, but not characterized.

DS70005208E-page 308

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

TABLE 25-47: PGAx MODULE SPECIFICATIONS

Standard Operating Conditions: 3.0V to 3.6V

(unless otherwise stated)

(1)

AC/DC CHARACTERISTICS

Param

Operating temperature -40°C  T

A

 +85°C for Industrial

 +125°C for Extended

-40°C  T

A

Symbol

Characteristic

Min.

Typ.

Max.

Units

Comments

No.

PA01

PA02

V

IN

Input Voltage Range

AVSS – 0.3

AVSS

—

AVDD + 0.3

AVDD – 1.6

V

VCM

Common-Mode Input

Voltage Range

PA03

PA04

V

OS

Input Offset Voltage

-20

—

+20

—

mV

VOS

Input Offset Voltage Drift

with Temperature

15

µV/C

PA05

PA06

PA07

R

IN

+

-

Input Impedance of

Positive Input

—

>1M || 7 pf

10K || 7 pf

—

|| pF

R

Input Impedance of

Negative Input

G

ERR

Gain Error

-2

-3

-4

—

+2

+3

+4

0.5

%

Gain = 4x and 8x

Gain = 16x

Gain = 32x and 64x

PA08

PA09

LERR

Gain Nonlinearity Error

Current Consumption

% of full scale,

Gain = 16x

I

DD

—

2.0

—

mA

Module is enabled with

a 2-volt P-P output

voltage swing

PA10a BW

PA10b

Small Signal

Bandwidth (-3 dB)

G = 4x

—

10

5

—

MHz

µs

G = 8x

PA10c

G = 16x

G = 32x

G = 64x

2.5

PA10d

1.25

0.625

0.4

PA10e

PA11

OST

Output Settling Time to 1%

of Final Value

Gain = 16x, 100 mV

input step change

PA12 SR

Output Slew Rate

—

40

1

—

10

V/µs Gain = 16x

PA13

PA14

T

GSEL

Gain Selection Time

µs

TON

Module Turn On/Setting

Time

—

Note 1: The PGAx module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless

otherwise stated, module functionality is tested, but not characterized.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 309

dsPIC33EPXXGS202 FAMILY

NOTES:

DS70005208E-page 310

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

NOTES:

DS70005208E-page 314

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

27.0 PACKAGING INFORMATION

27.1 Package Marking Information

28-Lead SSOP

Example

XXXXXXXXXXXX

dsPIC33EP16

GS202

1610017

YYWWNNN

28-Lead SOIC (.300”)

Example

XXXXXXXXXXXXXXXXXXXX

dsPIC33EP32GS202

1610017

YYWWNNN

28-Lead UQFN (4x4x0.6 mm)

Example

XXXXXXXX

YYWWNNN

33EP32

GS202

1610017

28-Lead UQFN (6x6x0.5 mm)

Example

XXXXXXXX

YYWWNNN

33EP32

GS202

1610017

28-Lead QFN-S (6x6x0.9 mm)

Example

XXXXXXXX

YYWWNNN

33EP32

GS202

1610017

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 315

dsPIC33EPXXGS202 FAMILY

27.2 Package Details

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DS70005208E-page 316

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2015-2018 Microchip Technology Inc.

DS70005208E-page 317

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS70005208E-page 318

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

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DS70005208E-page 319

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Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS70005208E-page 320

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28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]

With Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

N

NOTE 1

1

2

E

(DATUM B)

(DATUM A)

2X

0.10 C

2X

TOP VIEW

0.10 C

A1

0.10 C

0.08 C

C

A

SEATING

PLANE

28X

(A3)

SIDE VIEW

0.10

C A B

4x b2

4x b1

D2

4x b2

0.10

C A B

E2

NOTE 1

e

2

1

K

N

4x b1

L

28X b

0.07

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-333-M6 Rev B Sheet 1 of 2

 2015-2018 Microchip Technology Inc.

DS70005208E-page 321

dsPIC33EPXXGS202 FAMILY

28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]

With Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Corner Anchor Pad

Corner Pad, Metal Free Zone

Terminal Length

Terminal-to-Exposed-Pad

N

28

0.40 BSC

-

e

A

A1

A3

E

E2

D

D2

b

b1

-

0.60

0.05

0.00

0.02

0.152 REF

4.00 BSC

1.90

4.00 BSC

1.90

1.80

2.00

1.80

0.15

0.40

0.18

0.30

-

2.00

0.25

0.50

0.28

0.50

-

0.20

0.45

0.23

0.45

b2

L

K

0.60

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-333-M6 Rev A Sheet 2 of 2

DS70005208E-page 322

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28-Lead Ultra Thin Plastic Quad Flat, No Lead Package (M6) - 4x4x0.6 mm Body [UQFN]

With Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

EV

28

G3

1

2

ØV

G2

C2 Y2 EV

G1

Y1

Y3

X1

X3

SILK SCREEN

E

RECOMMENDED LAND PATTERN

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Contact Pitch

E

0.40 BSC

Center Pad Width

Center Pad Length

Contact Pad Spacing

Contact Pad Width (X28)

Contact Pad Length (X28)

Contact Pad to Center Pad (X28)

Contact Pad to Pad (X24)

Contact Pad to Corner Pad (X8)

Corner Anchor Width (X4)

Corner Anchor Length (X4)

Thermal Via Diameter

X2

Y2

C1

C2

X1

Y1

G1

G2

G3

X3

Y3

V

2.00

3.90

0.20

0.85

0.52

0.20

0.78

0.30

1.00

Thermal Via Pitch

EV

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-2333-M6 Rev B

 2015-2018 Microchip Technology Inc.

DS70005208E-page 323

dsPIC33EPXXGS202 FAMILY

28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN]

Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM A)

(DATUM B)

2X

0.15 C

2X

0.15 C

TOP VIEW

A

C

0.10 C

SEATING

PLANE

(A3)

A1

NOTE 4

0.08 C

SIDE VIEW

4x b1

4x b2

0.10

C A B

4x b1

D2

0.10

C A B

4x b2

K

E2

2

1

N

L

b

0.10

0.05

C A B

C

NOTE 4

e

BOTTOM VIEW

Microchip Technology Drawing C04-0209 Rev C Sheet 1 of 2

DS70005208E-page 324

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

28-Lead Plastic Quad Flat, No Lead Package (MX) - 6x6x0.5mm Body [UQFN]

Ultra-Thin with 0.40 x 0.60 mm Terminal Width/Length and Corner Anchors

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Pins

Pitch

Overall Height

Standoff

Terminal Thickness

Overall Width

Exposed Pad Width

Overall Length

Exposed Pad Length

Terminal Width

Corner Pad

N

28

0.65 BSC

0.50

e

A

A1

(A3)

0.40

0.00

0.60

0.05

0.02

0.127 REF

6.00 BSC

4.00

6.00 BSC

4.00

E

E2

D

D2

b

b1

b2

L

0.35

0.55

0.15

0.55

0.20

0.40

0.60

0.20

0.60

0.45

0.65

0.25

0.65

-

Corner Pad, Metal Free Zone

Terminal Length

Terminal-to-Exposed Pad

K

-

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

4. Outermost portions of corner structures may vary slightly.

Microchip Technology Drawing C04-0209 Rev C Sheet 2 of 2

 2015-2018 Microchip Technology Inc.

DS70005208E-page 325

dsPIC33EPXXGS202 FAMILY

Note: )RUꢀWKHꢀPRVWꢀFXUUHQWꢀSDFNDJHꢀGUDZLQJVꢁꢀSOHDVHꢀVHHꢀWKHꢀ0LFURFKLSꢀ3DFNDJLQJꢀ6SHFLILFDWLRQꢀORFDWHGꢀDW

KWWSꢂꢃꢃZZZꢄPLFURFKLSꢄFRPꢃSDFNDJLQJ

Note:

Corner anchor pads are not connected internally and are designed as mechanical features when the

package is soldered to the PCB.

DS70005208E-page 326

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 2015-2018 Microchip Technology Inc.

DS70005208E-page 327

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DS70005208E-page 328

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DS70005208E-page 329

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NOTES:

DS70005208E-page 330

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

Revision E (April 2018)

APPENDIX A: REVISION HISTORY

This revision of the document adds all the Data Sheet

Clarifications listed in the “dsPIC33EPXXGS202

Family Silicon Errata and Data Sheet Clarification”

(DS80000655), along with the following updates:

Revision A (January 2015)

This is the initial version of this document.

• Registers:

Revision B (May 2015)

- Adds Note to Register 8-4.

Changes to Register 19-7 ADCON4L.

- Updates Register 19-1, Register 19-13,

Register 19-14, Register 19-15, Register 19-18,

Register 19-19, Register 19-22, Register 19-23,

Register 19-24, Register 19-25 and

Register 19-26.

Changes to the hysteresis values in Section 20.6

“Hysteresis” and Register 20-1 CMPxCON.

A note has been added to Table 23-2 Instruction Set

Overview.

• Tables:

Changes to Section 25.0 “Electrical Characteristics”

New packaging diagrams have been added to

Section 27.0 “Packaging Information”

.

- Adds Table 25-42.

- Updates Table 1-1, Table 4-3, Table 4-14,

Table 7-1, Table 25-4 Table 25-12, Table 25-40,

Table 25-43 and Table 25-46.

.

Minor text edits throughout document.

• Figures:

Revision C (November 2015)

- Updates Pin Diagrams, Figure 19-1, Figure 19-3

and Figure 25-22.

Changes for this revision of the document have been

effected in the following:

• Adds:

-

Section 4.2 “Unique Device Identifier

(UDID)”

• Removes:

- Table 4-21: JTAG Interface Register Map

• Updates and modifies:

- Tables:

Table 4-3; Table 4-14; Table 4-17; Table 22-1;

Table 25-6; Table 25-8; Table 25-9; Table 25-13;

Table 25-43; Table 25-45; Table 25-46

- Figures:

Figure 19-1; Figure 19-2; Figure 19-3

- Registers:

Register 19-16; Register 19-22; Register 19-23

• Replaces:

- Register 19-20

- Three revised drawings of 28-Lead Ultra Thin

Plastic Quad Flat (M6) 4x4x0.6 mm Body in

Section 27.0 “Packaging Information”

Revision D (May 2016)

This revision of the document:

• Adds a new chapter Section 26.0 “DC and AC

Device Characteristics Graphs”

• Updates Table 25-2 and Register 19-23

• Modifies the “Qualification and Class B Support”

section

• Provides the family device number in Section 4.2

“Unique Device Identifier (UDID)”

• Wherever applicable, changes occurrences of

PWMx to PWM

 2015-2018 Microchip Technology Inc.

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NOTES:

DS70005208E-page 332

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INDEX

Data Access from Program Space

A

Address Generation............................................ 58

Absolute Maximum Ratings .............................................. 265

AC Characteristics ............................................................ 277

ADC Specifications ................................................... 305

Analog Current Specifications................................... 304

Analog-to-Digital Conversion Requirements............. 307

Auxiliary PLL Clock................................................... 279

Capacitive Loading Requirements on

Dedicated ADC Core 0-1.......................................... 199

dsPIC33EPXXGS202 Family ....................................... 7

High-Speed Analog Comparator x............................ 228

High-Speed PWM Architecture................................. 151

Hysteresis Control .................................................... 230

I2C1 Module ............................................................. 184

Input Capture Module............................................... 139

Interleaved PFC.......................................................... 14

MCLR Pin Connections .............................................. 12

Multiplexing Remappable Outputs for RPn .............. 110

Off-Line UPS .............................................................. 16

Oscillator System........................................................ 87

Output Compare Module .......................................... 143

PGAx Functions........................................................ 234

PGAx Module ........................................................... 233

Phase-Shifted Full-Bridge Converter.......................... 15

PLL Module ................................................................ 88

Programmer’s Model .................................................. 20

PSV Read Address Generation.................................. 49

Recommended Minimum Connection ........................ 12

Remappable Input for U1RX .................................... 108

Reset System ............................................................. 69

Security Segments Example .................................... 249

Shared ADC Core..................................................... 199

Shared Port Structure............................................... 105

Simplified Conceptual of High-Speed PWM............. 152

SPI1 Module............................................................. 175

Suggested Oscillator Circuit Placement ..................... 13

Timerx Module (x = 2,3)............................................ 136

Type B/Type C Timer Pair (32-Bit Timer)................. 136

UART1 Module......................................................... 191

Watchdog Timer (WDT)............................................ 247

Brown-out Reset (BOR)............................................ 239, 246

Output Pins....................................................... 277

External Clock Requirements ................................... 278

High-Speed PWMx Requirements............................ 287

I/O Requirements...................................................... 281

I2C1 Bus Data Requirements (Master Mode)........... 301

I2C1 Bus Data Requirements (Slave Mode)............. 303

Input Capture 1 Requirements.................................. 285

Internal FRC Accuracy.............................................. 280

Internal LPRC Accuracy............................................ 280

Load Conditions........................................................ 277

OC1/PWMx Mode Requirements.............................. 286

Output Compare 1 Requirements............................. 286

PLL Clock.................................................................. 279

Reset, WDT, OST, PWRT Requirements................. 282

SPI1 Master Mode (Full-Duplex, CKE = 0,

CKP = x, SMP = 1) Requirements.................... 291

SPI1 Master Mode (Full-Duplex, CKE = 1,

CKP = x, SMP = 1) Requirements.................... 290

SPI1 Master Mode (Half-Duplex,

Transmit Only) Requirements........................... 289

SPI1 Maximum Data/Clock Rate Summary.............. 288

SPI1 Slave Mode (Full-Duplex, CKE = 0,

CKP = 0, SMP = 0) Requirements.................... 299

SPI1 Slave Mode (Full-Duplex, CKE = 0,

CKP = 1, SMP = 0) Requirements.................... 297

SPI1 Slave Mode (Full-Duplex, CKE = 1,

CKP = 0, SMP = 0) Requirements.................... 293

SPI1 Slave Mode (Full-Duplex, CKE = 1,

C

CKP = 1, SMP = 0) Requirements.................... 295

Temperature and Voltage Specifications.................. 277

Timer1 External Clock Requirements ....................... 283

Timer2 External Clock Requirements ....................... 284

Timer3 External Clock Requirements ....................... 284

UART1 I/O Requirements......................................... 304

AC/DC Characteristics

DACx Specifications ................................................. 308

High-Speed Analog Comparator Specifications........ 307

PGAx Specifications ................................................. 309

Arithmetic Logic Unit (ALU)................................................. 26

Assembler

C Compilers

MPLAB XC ............................................................... 262

Code Examples

Port Write/Read........................................................ 106

PWM Write-Protected Register

Unlock Sequence ............................................. 150

PWRSAVInstruction Syntax......................................... 97

Code Protection........................................................ 239, 248

CodeGuard Security ................................................. 239, 248

Configuration Bits ............................................................. 239

Description................................................................ 241

CPU

MPASM Assembler................................................... 262

Addressing Modes...................................................... 17

Clocking System Options ........................................... 88

Fast RC (FRC) Oscillator.................................... 88

FRC Oscillator with PLL ..................................... 88

FRC Oscillator with Postscaler........................... 88

Low-Power RC (LPRC) Oscillator ...................... 88

Primary (XT, HS, EC) Oscillator ......................... 88

Primary Oscillator with PLL ................................ 88

Control Registers........................................................ 22

Data Space Addressing.............................................. 17

Instruction Set............................................................. 17

Registers .................................................................... 17

Resources .................................................................. 21

B

Bit-Reversed Addressing .................................................... 56

Example...................................................................... 57

Implementation ........................................................... 56

Sequence Table (16-Entry)......................................... 57

Block Diagrams

16-Bit Timer1 Module................................................ 131

ADC Module.............................................................. 198

Addressing for Table Registers................................... 61

CALLStack Frame..................................................... 52

Connections for On-Chip Voltage Regulator............. 246

CPU Core.................................................................... 18

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Customer Change Notification Service .............................338

Customer Notification Service...........................................338

G

Getting Started Guidelines.................................................. 11

Customer Support.............................................................338

Connection Requirements.......................................... 11

CPU Logic Filter Capacitor Connection (VCAP) .......... 12

Decoupling Capacitors................................................ 11

External Oscillator Pins............................................... 13

ICSP Pins ................................................................... 13

Master Clear (MCLR) Pin ........................................... 12

Oscillator Value Conditions on Start-up...................... 14

Targeted Applications................................................. 14

Unused I/Os................................................................ 14

D

Data Address Space ...........................................................31

Memory Map for dsPIC33EP16/32GS202

Devices ...............................................................32

Near Data Space ........................................................31

Organization, Alignment..............................................31

SFR Space..................................................................31

Width...........................................................................31

Data Space

Extended X .................................................................52

Paged Data Memory Space (figure) ...........................50

Paged Memory Scheme .............................................49

DC Characteristics

Brown-out Reset (BOR)............................................275

Doze Current (IDOZE) ................................................271

I/O Pin Input Specifications.......................................272

I/O Pin Output Specifications....................................275

Idle Current (IIDLE) ....................................................269

Operating Current (IDD).............................................268

Operating MIPS vs. Voltage......................................266

Power-Down Current (IPD)........................................270

Program Memory ......................................................276

Temperature and Voltage Specifications..................267

Watchdog Timer Delta Current (IWDT) ....................270

DC/AC Characteristics

H

High-Speed Analog Comparator

Applications .............................................................. 229

Control Registers...................................................... 231

Description................................................................ 228

Digital-to-Analog Comparator (DAC) ........................ 229

Features Overview.................................................... 227

Hysteresis................................................................. 230

Pulse Stretcher and Digital Logic.............................. 229

Resources ................................................................ 230

High-Speed PWM

Feature Description .................................................. 149

Features ................................................................... 149

Resources ................................................................ 150

Write-Protected Registers......................................... 150

High-Speed, 12-Bit Analog-to-Digital

Converter (ADC)....................................................... 197

Control and Status Registers.................................... 200

Features Overview.................................................... 197

Resources ................................................................ 200

Graphs and Tables ...................................................311

Demo/Development Boards, Evaluation and

Starter Kits ................................................................264

Development Support .......................................................261

Device Calibration.............................................................244

Addresses.................................................................244

and Identification.......................................................244

Doze Mode..........................................................................99

DSP Engine.........................................................................26

I

I/O Ports............................................................................ 105

Configuring Analog/Digital Port Pins......................... 106

Helpful Tips............................................................... 111

Open-Drain Configuration......................................... 106

Parallel I/O (PIO) ...................................................... 105

Resources ................................................................ 112

Write/Read Timing.................................................... 106

In-Circuit Debugger........................................................... 248

In-Circuit Emulation .......................................................... 239

In-Circuit Serial Programming (ICSP)....................... 239, 248

Input Capture.................................................................... 139

Control Registers...................................................... 140

Resources ................................................................ 139

Input Change Notification (ICN)........................................ 106

Instruction Addressing Modes ............................................ 53

File Register Instructions............................................ 53

Fundamental Modes Supported ................................. 53

MACInstructions......................................................... 54

MCU Instructions ........................................................ 53

Move and Accumulator Instructions............................ 54

Other Instructions ....................................................... 54

Instruction Set

E

Electrical Characteristics...................................................265

AC .............................................................................277

Equations

Device Operating Frequency ......................................88

F

PLLO Calculation........................................................88

VCO Calculation.........................................................88

Errata ....................................................................................6

F

Filter Capacitor (CEFC) Specifications...............................267

Flash Program Memory.......................................................61

and Table Instructions.................................................61

Control Registers ........................................................63

Operations ..................................................................62

Resources...................................................................63

RTSP Operation..........................................................62

Flexible Configuration .......................................................239

Overview................................................................... 254

Summary .................................................................. 251

Symbols Used in Opcode Descriptions .................... 252

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Instruction-Based Power-Saving Modes............................. 97

Peripheral Pin Select (PPS).............................................. 107

Available Peripherals................................................ 107

Available Pins........................................................... 107

Control...................................................................... 107

Control Registers...................................................... 113

Input Mapping........................................................... 108

Output Mapping........................................................ 110

Output Selection for Remappable Pins .................... 110

Selectable Input Sources.......................................... 109

Peripheral Pin Select. See PPS.

PICkit 3 In-Circuit Debugger/Programmer........................ 263

Pinout I/O Descriptions (table).............................................. 8

Power-Saving Features...................................................... 97

Clock Frequency and Switching ................................. 97

Control Registers...................................................... 100

Resources .................................................................. 99

Program Address Space..................................................... 27

Construction ............................................................... 58

Data Access from Program Memory Using

Idle .............................................................................. 98

Sleep........................................................................... 98

2

Inter-Integrated Circuit (I C).............................................. 183

Control and Status Registers.................................... 185

Resources................................................................. 183

2

Inter-Integrated Circuit. See I C.

Internet Address................................................................ 338

Interrupt Controller

Alternate Interrupt Vector Table (AIVT) ...................... 73

Control and Status Registers...................................... 78

INTCON1 ............................................................ 78

INTCON2 ............................................................ 78

INTCON3 ............................................................ 78

INTCON4 ............................................................ 78

INTTREG ............................................................ 78

Interrupt Vector Details ............................................... 76

Interrupt Vector Table (IVT) ........................................ 73

Reset Sequence ......................................................... 73

Resources................................................................... 78

Interrupts Coincident with Power Save Instructions............ 98

Table Instructions ............................................... 59

Memory Map (dsPIC33EP16GS202 Devices)............ 28

Memory Map (dsPIC33EP32GS202 Devices)............ 29

Table Read High Instructions (TBLRDH)..................... 59

Table Read Low Instructions (TBLRDL)...................... 59

Program Memory

J

JTAG Boundary Scan Interface ........................................ 239

JTAG Interface.................................................................. 248

Organization ............................................................... 30

Reset Vector............................................................... 30

Programmable Gain Amplifier (PGA)................................ 233

Control Registers...................................................... 236

Description................................................................ 234

Resources ................................................................ 235

Programmable Gain Amplifier. See PGA.

Programmer’s Model .......................................................... 19

Register Descriptions ................................................. 19

Pulse-Width Modulation. See PWM.

L

Leading-Edge Blanking (LEB)........................................... 149

LPRC Oscillator

Use with WDT........................................................... 247

M

Memory Organization.......................................................... 27

Resources................................................................... 33

Microchip Internet Web Site.............................................. 338

Modulo Addressing ............................................................. 55

Applicability................................................................. 56

Operation Example ..................................................... 55

Start and End Address................................................ 55

W Address Register Selection .................................... 55

MPLAB Assembler, Linker, Librarian ................................ 262

MPLAB ICD 3 In-Circuit Debugger ................................... 263

MPLAB PM3 Device Programmer .................................... 263

MPLAB REAL ICE In-Circuit Emulator System................. 263

MPLAB X Integrated Development

R

Register Maps

ADC............................................................................ 43

Analog Comparator .................................................... 47

Configuration ............................................................ 240

CPU Core ................................................................... 34

I2C1............................................................................ 42

Input Capture 1........................................................... 38

Interrupt Controller...................................................... 36

NVM............................................................................ 46

Output Compare 1...................................................... 38

Peripheral Pin Select Output ...................................... 45

PMD............................................................................ 46

PORTA ....................................................................... 48

PORTB ....................................................................... 48

Programmable Gain Amplifier .................................... 47

PWM........................................................................... 39

PWM Generator 1....................................................... 39

PWM Generator 2....................................................... 40

PWM Generator 3....................................................... 41

SPI1............................................................................ 42

System Control........................................................... 46

Timer1 through Timer3............................................... 38

UART1........................................................................ 42

Environment Software............................................... 261

MPLINK Object Linker/MPLIB Object Librarian ................ 262

O

Oscillator

Control Registers ........................................................ 90

Resources................................................................... 89

Oscillator Configuration....................................................... 87

OTP Memory Area ............................................................ 246

Output Compare ............................................................... 143

Control Registers ...................................................... 144

Resources................................................................. 143

P

Packaging ......................................................................... 315

Details....................................................................... 316

Marking ..................................................................... 315

Peripheral Module Disable (PMD) ...................................... 99

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Registers

ACLKCON (Auxiliary Clock Divisor Control)...............95

NVMADR (Nonvolatile Memory Lower Address)........ 65

NVMADRU (Nonvolatile Memory Upper Address) ..... 66

NVMCON (Nonvolatile Memory (NVM) Control)......... 64

NVMKEY (Nonvolatile Memory Key) .......................... 66

NVMSRCADRH (NVM Source Data

ADCAL0L (ADC Calibration 0 Low) ..........................220

ADCAL1H (ADC Calibration 1 High).........................221

ADCMPxCON (ADC Digital Comparator x

Control) .............................................................222

ADCMPxENL (ADC Digital Comparator x

Address High)..................................................... 67

NVMSRCADRL (NVM Source Data

Channel Enable Low)........................................223

ADCON1H (ADC Control 1 High) .............................201

ADCON1L (ADC Control 1 Low)...............................200

ADCON2H (ADC Control 2 High) .............................203

ADCON2L (ADC Control 2 Low)...............................202

ADCON3H (ADC Control 3 High) .............................205

ADCON3L (ADC Control 3 Low)...............................204

ADCON4H (ADC Control 4 High) .............................207

ADCON4L (ADC Control 4 Low)...............................206

ADCON5H (ADC Control 5 High) .............................209

ADCON5L (ADC Control 5 Low)...............................208

ADCORExH (Dedicated ADC Core x

Address Low)...................................................... 67

OC1CON1 (Output Compare Control 1)................... 144

OC1CON2 (Output Compare Control 2)................... 146

OSCCON (Oscillator Control)..................................... 90

OSCTUN (FRC Oscillator Tuning).............................. 94

PDCx (PWMx Generator Duty Cycle)....................... 162

PGAxCAL (PGAx Calibration) .................................. 237

PGAxCON (PGAx Control)....................................... 236

PHASEx (PWMx Primary Phase-Shift)..................... 163

PLLFBD (PLL Feedback Divisor)................................ 93

PMD1 (Peripheral Module Disable Control 1)........... 100

PMD2 (Peripheral Module Disable Control 2)........... 101

PMD3 (Peripheral Module Disable Control 3)........... 101

PMD6 (Peripheral Module Disable Control 6)........... 102

PMD7 (Peripheral Module Disable Control 7)........... 103

PMD8 (Peripheral Module Disable Control 8)........... 103

PTCON (PWM Time Base Control) .......................... 153

PTCON2 (PWM Clock Divider Select 2)................... 154

PTPER (PWM Primary Master

Control High).....................................................211

ADCORExL (Dedicated ADC Core x

Control Low)......................................................210

ADEIEL (ADC Early Interrupt Enable Low)...............213

ADEISTATL (ADC Early Interrupt Status Low) .........213

ADFL0CON (ADC Digital Filter 0 Control) ................224

ADIEL (ADC Interrupt Enable Low) ..........................215

ADLVLTRGL (ADC Level-Sensitive Trigger

Control Low)......................................................212

ADMOD0H (ADC Input Mode Control 0 High)..........214

ADMOD0L (ADC Input Mode Control 0 Low) ...........214

ADSTATL (ADC Data Ready Status Low)................215

ADTRIGxH (ADC Channel Trigger x

Time Base Period)............................................ 155

PWMCAPx (PWMx Primary

Time Base Capture) ......................................... 174

PWMCONx (PWMx Control)..................................... 160

PWMKEY (PWM Protection Lock/Unlock Key)......... 159

RCON (Reset Control)................................................ 71

RPINR0 (Peripheral Pin Select Input 0).................... 113

RPINR1 (Peripheral Pin Select Input 1).................... 113

RPINR11 (Peripheral Pin Select Input 11)................ 116

RPINR12 (Peripheral Pin Select Input 12)................ 117

RPINR13 (Peripheral Pin Select Input 13)................ 118

RPINR18 (Peripheral Pin Select Input 18)................ 119

RPINR2 (Peripheral Pin Select Input 2).................... 114

RPINR20 (Peripheral Pin Select Input 20)................ 120

RPINR21 (Peripheral Pin Select Input 21)................ 121

RPINR3 (Peripheral Pin Select Input 3).................... 115

RPINR37 (Peripheral Pin Select Input 37)................ 121

RPINR38 (Peripheral Pin Select Input 38)................ 122

RPINR42 (Peripheral Pin Select Input 42)................ 123

RPINR43 (Peripheral Pin Select Input 43)................ 124

RPINR7 (Peripheral Pin Select Input 7).................... 116

RPOR0 (Peripheral Pin Select Output 0).................. 125

RPOR1 (Peripheral Pin Select Output 1).................. 125

RPOR10 (Peripheral Pin Select Output 10).............. 130

RPOR2 (Peripheral Pin Select Output 2).................. 126

RPOR3 (Peripheral Pin Select Output 3).................. 126

RPOR4 (Peripheral Pin Select Output 4).................. 127

RPOR5 (Peripheral Pin Select Output 5).................. 127

RPOR6 (Peripheral Pin Select Output 6).................. 128

RPOR7 (Peripheral Pin Select Output 7).................. 128

RPOR8 (Peripheral Pin Select Output 8).................. 129

RPOR9 (Peripheral Pin Select Output 9).................. 129

SDCx (PWMx Secondary Duty Cycle)...................... 162

SEVTCMP (PWM Special Event Compare) ............. 155

SPHASEx (PWMx Secondary Phase-Shift).............. 164

SPI1CON1 (SPI1 Control 1) ..................................... 179

SPI1CON2 (SPI1 Control 2) ..................................... 181

SPI1STAT (SPI1 Status and Control)....................... 177

SR (CPU STATUS)............................................... 22, 79

Selection High)..................................................218

ADTRIGxL (ADC Channel Trigger x

Selection Low) ..................................................216

ALTDTRx (PWMx Alternate Dead-Time) ..................165

AUXCONx (PWMx Auxiliary Control)........................173

CHOP (PWM Chop Clock Generator).......................158

CLKDIV (Clock Divisor)...............................................92

CMPxCON (Comparator x Control) ..........................231

CMPxDAC (Comparator DACx Control) ...................232

CORCON (Core Control) ...................................... 24, 80

CTXTSTAT (CPU W Register Context Status) ...........25

DEVID (Device ID)....................................................245

DEVREV (Device Revision)......................................245

DTRx (PWMx Dead-Time)........................................165

FCLCONx (PWMx Fault Current-Limit Control) ........169

I2C1CONH (I2C1 Control High)................................187

I2C1CONL (I2C1 Control Low) .................................185

I2C1MSK (I2C1 Slave Mode Address Mask)............190

I2C1STAT (I2C1 Status)...........................................188

IC1CON1 (Input Capture Control 1)..........................140

IC1CON2 (Input Capture Control 2)..........................141

INTCON1 (Interrupt Control 1)....................................81

INTCON2 (Interrupt Control 2)....................................83

INTCON3 (Interrupt Control 3)....................................84

INTCON4 (Interrupt Control 4)....................................84

INTTREG (Interrupt Control and Status).....................85

IOCONx (PWMx I/O Control)....................................167

LEBCONx (PWMx Leading-Edge

Blanking Control) ..............................................171

LEBDLYx (PWMx Leading-Edge

Blanking Delay).................................................172

LFSR (Linear Feedback Shift) ....................................96

MDC (PWM Master Duty Cycle) ...............................159

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SSEVTCMP (PWM Secondary

Timing Diagrams

Special Event Compare)................................... 158

STCON (PWM Secondary Master

Time Base Control)........................................... 156

STCON2 (PWM Secondary

Clock Divider Select 2) ..................................... 157

STPER (PWM Secondary Master

Time Base Period)............................................ 157

STRIGx (PWMx Secondary Trigger

Compare Value)................................................ 170

T1CON (Timer1 Control)........................................... 133

T2CON (Timer2 Control)........................................... 137

T3CON (Timer3 Control)........................................... 138

TRGCONx (PWMx Trigger Control).......................... 166

TRIGx (PWMx Primary Trigger

BOR and Master Clear Reset Characteristics.......... 281

External Clock .......................................................... 278

High-Speed PWMx Fault Characteristics ................. 287

High-Speed PWMx Module Characteristics ............. 287

I/O Characteristics.................................................... 281

I2C1 Bus Data (Master Mode).................................. 300

I2C1 Bus Data (Slave Mode).................................... 302

I2C1 Bus Start/Stop Bits (Master Mode) .................. 300

I2C1 Bus Start/Stop Bits (Slave Mode) .................... 302

Input Capture 1 (IC1) Characteristics....................... 285

OC1/PWMx Characteristics...................................... 286

Output Compare 1 (OC1) Characteristics ................ 286

SPI1 Master Mode (Full-Duplex, CKE = 0,

CKP = x, SMP = 1)........................................... 291

SPI1 Master Mode (Full-Duplex, CKE = 1,

Compare Value)................................................ 168

U1MODE (UART1 Mode) ......................................... 193

U1STA (UART1 Status and Control) ........................ 195

Resets................................................................................. 69

Brown-out Reset (BOR).............................................. 69

Configuration Mismatch Reset (CM)........................... 69

Illegal Condition Reset (IOPUWR).............................. 69

Illegal Opcode..................................................... 69

Security............................................................... 69

Uninitialized W Register...................................... 69

Master Clear (MCLR) Pin Reset ................................. 69

Power-on Reset (POR)............................................... 69

RESETInstruction (SWR) .......................................... 69

Resources................................................................... 70

Trap Conflict Reset (TRAPR)...................................... 69

Watchdog Timer Time-out Reset (WDTO).................. 69

Revision History................................................................ 331

CKP = x, SMP = 1)........................................... 290

SPI1 Master Mode (Half-Duplex,

Transmit Only, CKE = 0) .................................. 288

SPI1 Master Mode (Half-Duplex,

Transmit Only, CKE = 1) .................................. 289

SPI1 Slave Mode (Full-Duplex, CKE = 0,

CKP = 0, SMP = 0)........................................... 298

SPI1 Slave Mode (Full-Duplex, CKE = 0,

CKP = 1, SMP = 0)........................................... 296

SPI1 Slave Mode (Full-Duplex, CKE = 1,

CKP = 0, SMP = 0)........................................... 292

SPI1 Slave Mode (Full-Duplex, CKE = 1,

CKP = 1, SMP = 0)........................................... 294

Timer1-Timer3 External Clock Characteristics......... 283

UART1 I/O Characteristics ....................................... 304

U

S

Unique Device Identifier (UDID) ......................................... 27

Universal Asynchronous Receiver

Serial Peripheral Interface (SPI) ....................................... 175

Serial Peripheral Interface. See SPI.

Software Simulator (MPLAB X SIM) ................................. 263

Special Features of the CPU ............................................ 239

SPI

Transmitter (UART) .................................................. 191

Control and Status Registers.................................... 193

Helpful Tips............................................................... 192

Resources ................................................................ 192

Universal Asynchronous Receiver Transmitter. See UART.

Control and Status Registers.................................... 177

Helpful Tips............................................................... 176

Resources................................................................. 176

V

Voltage Regulator (On-Chip) ............................................ 246

T

W

Thermal Operating Conditions.......................................... 266

Thermal Packaging Characteristics .................................. 266

Third-Party Development Tools ........................................ 264

Timer1............................................................................... 131

Control Register........................................................ 133

Resources................................................................. 132

Timer2/3............................................................................ 135

Control Registers ...................................................... 137

Resources................................................................. 135

Watchdog Timer (WDT)............................................ 239, 247

Programming Considerations................................... 247

WWW Address ................................................................. 338

WWW, On-Line Support ....................................................... 6

 2015-2018 Microchip Technology Inc.

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NOTES:

DS70005208E-page 338

 2015-2018 Microchip Technology Inc.

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THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

•

Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

Customers

should

contact

their

distributor,

representative or Field Application Engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

•

General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://microchip.com/support

Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com. Under “Support”, click on

“Customer Change Notification” and follow the

registration instructions.

 2015-2018 Microchip Technology Inc.

DS70005208E-page 339

dsPIC33EPXXGS202 FAMILY

NOTES:

DS70005208E-page 340

 2015-2018 Microchip Technology Inc.

dsPIC33EPXXGS202 FAMILY

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office

.

Examples:

dsPIC 33 EP XX GS2 02 T - I / PT XXX

dsPIC33EP32GS202-I/SS:

dsPIC33, Enhanced Performance,

32-Kbyte Program Memory, SMPS,

28-Pin, Industrial Temperature,

SSOP Package.

Microchip Trademark

Architecture

Flash Memory Family

Program Memory Size (Kbyte)

Product Group

Pin Count

Tape and Reel Flag (if applicable)

Temperature Range

Package

Pattern

Architecture:

33 = 16-Bit Digital Signal Controller

Flash Memory Family: EP = Enhanced Performance

Product Group:

Pin Count:

GS = SMPS Family

02 = 28-pin

Temperature Range:

I

E

= -40



C to +85



C (Industrial)

= -40



C to +125



C (Extended)

Package:

MM = Plastic Quad, No Lead Package – (28-pin) 6x6 mm body (QFN-S)

M6 = Plastic Quad Flat, No Lead Package – (28-pin) 4x4x0.6 mm body (UQFN)

MX = Plastic Quad Flat, No Lead Package – (28-pin) 6x6x0.5 mm body (UQFN)

SO = Plastic Small Outline, Wide – (28-pin) 7.50 mm body (SOIC)

SS = Plastic Shrink Small Outline – (28-pin) 5.30 mm body (SSOP)

 2015-2018 Microchip Technology Inc.

DS70005208E-page 341

dsPIC33EPXXGS202 FAMILY

NOTES:

DS70005208E-page 342

 2015-2018 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, AVR,

AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,

CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEE

LOQ,

K

EEL

OQ logo, Kleer, LANCheck, LINK MD, maXStylus,

maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,

OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip

Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST

Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

and other countries.

ClockWorks, The Embedded Control Solutions Company,

EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and Quiet-Wire are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,

CodeGuard, CryptoAuthentication, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

Silicon Storage Technology is a registered trademark of Microchip

Technology Inc. in other countries.

are for its PIC^®MCUs and dsPIC^®DSCs, KEE OQ^®code hopping

L

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

GestIC is a registered trademark of Microchip Technology

Germany II GmbH & Co. KG, a subsidiary of Microchip Technology

Inc., in other countries.

All other trademarks mentioned herein are property of their

respective companies.

QUALITY MANAGEMENT SYSTEM

CERTIFIED BY DNV

Reserved.

ISBN: 978-1-5224-2860-2

== ISO/TS 16949 ==

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DS70005208E-page 343

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Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7289-7561

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS70005208E-page 344

 2015-2018 Microchip Technology Inc.

10/25/17


型号：	DSPIC33EPGS02-TI/SS
厂家：	MICROCHIP
描述：	16-Bit Digital Signal Controllers for Digital Power Applications with Interconnected High-Speed PWM, ADC, PGA and Comparators
文件：	总344页 (文件大小：3559K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

DSPIC33EPGS02-TI/SS [MICROCHIP]

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