DSPIC33FJ32GP202TI/SP [MICROCHIP]
High-Performance, 16-bit Digital Signal Controllers; 高性能16位数字信号控制器
| 型号： | DSPIC33FJ32GP202TI/SP |
| 厂家： | 
MICROCHIP |
| 描述： | High-Performance, 16-bit Digital Signal Controllers |
| 文件： | 总403页 (文件大小：2499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04
Data Sheet
High-Performance,
16-bit Digital Signal Controllers
2009 Microchip Technology Inc.
Preliminary
DS70292D
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
32
PICtail, PIC logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS70292D-page 2
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, AND
dsPIC33FJ128GPX02/X04
High-Performance, 16-Bit Digital Signal Controllers
Operating Range:
Timers/Capture/Compare/PWM:
• Up to 40 MIPS operation (at 3.0-3.6V):
- Industrial temperature range (-40°C to +85°C)
- Extended temperature range (-40°C to +125°C)
• Up to 20 MIPS operation (at 3.0-3.6V):
- High temperature range (-40°C to +140°C)
• Timer/Counters, up to five 16-bit timers:
- Can pair up to make two 32-bit timers
- One timer runs as a Real-Time Clock with an
external 32.768 kHz oscillator
- Programmable prescaler
• Input Capture (up to four channels):
- Capture on up, down or both edges
- 16-bit capture input functions
High-Performance DSC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
- 4-deep FIFO on each capture
• Output Compare (up to four channels):
- Single or Dual 16-bit Compare mode
- 16-bit Glitchless PWM mode
• 24-bit wide instructions
• Linear program memory addressing up to 4M
instruction words
• Hardware Real-Time Clock/Calendar (RTCC):
- Provides clock, calendar and alarm functions
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
Interrupt Controller:
• Two 40-bit accumulators with rounding and
saturation options
• 5-cycle latency
• Flexible and powerful addressing modes:
- Indirect
• Up to 49 available interrupt sources
• Up to three external interrupts
• Seven programmable priority levels
• Five processor exceptions
- Modulo
- Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate:
- Accumulator write back for DSP operations
- Dual data fetch
Digital I/O:
• Peripheral pin Select functionality
• Up to 35 programmable digital I/O pins
• Wake-up/Interrupt-on-Change for up to 31 pins
• Output pins can drive from 3.0V to 3.6V
• Up to 5V output with open drain configuration
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
• Up to ±16-bit shifts for up to 40-bit data
Direct Memory Access (DMA):
• 8-channel hardware DMA
• Up to 2 Kbytes dual ported DMA buffer area (DMA
RAM) to store data transferred via DMA:
On-Chip Flash and SRAM:
• Flash program memory (up to 128 Kbytes)
• Data SRAM (up to 16 Kbytes)
-
Allows data transfer between RAM and a
peripheral while CPU is executing code (no
cycle stealing)
• Boot, Secure and General Security for program
Flash
• Most peripherals support DMA
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 3
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
System Management:
Communication Modules:
• Flexible clock options:
• 4-wire SPI (up to two modules):
- External, crystal, resonator, internal RC
- Fully integrated Phase-Locked Loop (PLL)
- Extremely low jitter PLL
- Framing supports I/O interface to simple
codecs
- Supports 8-bit and 16-bit data
- Supports all serial clock formats and
sampling modes
• Power-up Timer
• Oscillator Start-up Timer/Stabilizer
• Watchdog Timer with its own RC oscillator
• Fail-Safe Clock Monitor
• I2C™:
- Full Multi-Master Slave mode support
- 7-bit and 10-bit addressing
• Reset by multiple sources
- Bus collision detection and arbitration
- Integrated signal conditioning
- Slave address masking
Power Management:
• On-chip 2.5V voltage regulator
• UART (up to two modules):
• Switch between clock sources in real time
• Idle, Sleep, and Doze modes with fast wake-up
- Interrupt on address bit detect
- Interrupt on UART error
- Wake-up on Start bit from Sleep mode
- 4-character TX and RX FIFO buffers
- LIN bus support
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion:
- Two and four simultaneous samples (10-bit ADC)
- Up to 13 input channels with auto-scanning
- IrDA® encoding and decoding in hardware
- High-Speed Baud mode
- Conversion start can be manual or
synchronized with one of four trigger sources
- Hardware Flow Control with CTS and RTS
• Enhanced CAN (ECAN™ module) 2.0B active:
- Up to eight transmit and up to 32 receive buffers
- 16 receive filters and three masks
- Loopback, Listen Only and Listen All
- Conversion possible in Sleep mode
- ±2 LSb max integral nonlinearity
- ±1 LSb max differential nonlinearity
- Messages modes for diagnostics and bus
monitoring
Audio Digital-to-Analog Converter (DAC):
• 16-bit Dual Channel DAC module
- Wake-up on CAN message
• 100 ksps maximum sampling rate
- Automatic processing of Remote
Transmission Requests
• Second-Order Digital Delta-Sigma Modulator
- FIFO mode using DMA
- DeviceNet™ addressing support
• Parallel Master Slave Port (PMP/EPSP):
- Supports 8-bit or 16-bit data
Data Converter Interface (DCI) module:
• Codec interface
• Supports I2S and AC’97 protocols
• Up to 16-bit data words, up to 16 words per frame
• 4-word deep TX and RX buffers
- Supports 16 address lines
• Programmable Cyclic Redundancy Check (CRC):
- Programmable bit length for the CRC
generator polynomial (up to 16-bit length)
Comparator Module:
- 8-deep, 16-bit or 16-deep, 8-bit FIFO for data
input
• Two analog comparators with programmable
input/output configuration
Packaging:
CMOS Flash Technology:
• 28-pin SDIP/SOIC/QFN-S
• 44-pin TQFP/QFN
• Low-power, high-speed Flash technology
• Fully static design
Note:
See the device variant tables for exact
peripheral features per device.
• 3.3V (±10%) operating voltage
• Industrial and Extended temperature
• Low power consumption
DS70292D-page 4
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, AND
dsPIC33FJ128GPX02/X04 PRODUCT
FAMILIES
The device names, pin counts, memory sizes, and
peripheral availability of each device are listed below.
The following pages show their pinout diagrams.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04
Controller Families
Remappable Peripheral
Device
dsPIC33FJ128GP804
dsPIC33FJ128GP802
44
28
128
128
16 26
16 16
5
5
4
4
4
4
1
1
2
2
2
2
1
1
1
1
1
1
1
1
13
10
6
4
1/1
1/0
11
2
35
21
QFN
TQFP
3
3
SDIP
SOIC
QFN-S
dsPIC33FJ128GP204
dsPIC33FJ128GP202
44
28
128
128
8
8
26
16
5
5
4
4
4
4
1
1
2
2
2
2
0
0
3
3
1
1
1
1
1
1
13
10
0
0
1/1
1/0
11
2
35
21
QFN
TQFP
SDIP
SOIC
QFN-S
dsPIC33FJ64GP804
dsPIC33FJ64GP802
44
28
64
64
16 26
16 16
5
5
4
4
4
4
1
1
2
2
2
2
1
1
3
3
1
1
1
1
1
1
13
10
6
4
1/1
1/0
11
2
35
21
QFN
TQFP
SDIP
SOIC
QFN-S
dsPIC33FJ64GP204
dsPIC33FJ64GP202
44
28
64
64
8
8
26
16
5
5
4
4
4
4
1
1
2
2
2
2
0
0
3
3
1
1
1
1
1
1
13
10
0
0
1/1
1/0
11
2
35
21
QFN
TQFP
SDIP
SOIC
QFN-S
dsPIC33FJ32GP304
dsPIC33FJ32GP302
44
28
32
32
4
4
26
16
5
5
4
4
4
4
1
1
2
2
2
2
0
0
3
3
1
1
1
1
1
1
13
10
0
0
1/1
1/0
11
2
35
21
QFN
TQFP
SDIP
SOIC
QFN-S
Note 1:
RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except dsPIC33FJ32GP302/304, which include 1 Kbyte of DMA RAM.
Only four out of five timers are remappable.
Only two out of three interrupts are remappable.
2:
3:
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 5
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams
= Pins are up to 5V tolerant
28-Pin SDIP, SOIC
MCLR
AN0/VREF+/CN2/RA0
AN1/VREF-/CN3/RA1
AVDD
AVSS
1
2
3
4
5
28
27
26
25
24
AN9/DAC1LN/RP15(1)/CN11/PMCS1/RB15
AN10/DAC1LP/RTCC/RP14(1)/CN12/PMWR/RB14
AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
PGED2/TDI/RP10(1)/CN16/PMD2/RB10
VCAP/VDDCORE
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
6
7
8
23
22
21
OSC1/CLKI/CN30/RA2
9
20
19
18
17
16
15
OSC2/CLKO/CN29/PMA0/RA3
SOSCI/RP4(1)/CN1/PMBE/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
VSS
10
11
12
13
14
TDO/SDA1/RP9(1)/CN21/PMD3/RB9
TCK/SCL1/RP8(1)/CN22/PMD4/RB8
INT0/RP7(1)/CN23/PMD5/RB7
PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5
PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6
= Pins are up to 5V tolerant
28-Pin SDIP, SOIC
MCLR
AN0/VREF+/CN2/RA0
AVDD
1
2
3
4
5
28
27
26
25
24
AVSS
AN1/VREF-/CN3/RA1
AN9/RP15(1)/CN11/PMCS1/RB15
AN10/RTCC/RP14(1)/CN12/PMWR/RB14
AN11/RP13(1)/CN13/PMRD/RB13
AN12/RP12(1)/CN14/PMD0/RB12
PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
PGED2/TDI/RP10(1)/CN16/PMD2/RB10
VCAP/VDDCORE
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/ AN3/C2IN+/RP1(1)/CN5/RB1
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
6
7
8
23
22
21
OSC1/CLKI/CN30/RA2
9
20
19
18
17
16
15
OSC2/CLKO/CN29/PMA0/RA3
SOSCI/RP4(1)/CN1/PMBE/RB4
SOSCO/T1CK/CN0/PMA1/RA4
VDD
VSS
10
11
12
13
14
TDO/SDA1/RP9(1)/CN21/PMD3/RB9
TCK/SCL1/RP8(1)/CN22/PMD4/RB8
INT0/RP7(1)/CN23/PMD5/RB7
PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6
PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
DS70292D-page 6
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
28-Pin QFN-S(2)
= Pins are up to 5V tolerant
PGED1/AN2/C2IN-/RP0(1)/CN4/RB0
PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1
AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
PGEC2/TMS/RP11(1)/CN15/PMD1/RB11
PGED2/TDI/RP10(1)/CN16/PMD2/RB10
VCAP/VDDCORE
1
2
3
4
5
6
7
21
20
19
18
17
16
15
AN4/C1IN-/RP2(1)/CN6/RB2
dsPIC33FJ64GP802
dsPIC33FJ128GP802
AN5/C1IN+/RP3(1)/CN7/RB3
VSS
OSC1/CLKI/CN30/RA2
VSS
TDO/SDA1/RP9(1)/CN21/PMD3/RB9
OSC2/CLKO/CN29/PMA0/RA3
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 7
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
28-Pin QFN-S(2)
=
Pins are up to 5V tolerant
(1)
(1)
PGED1/AN2/C2IN-/RP0 /CN4/RB0
AN11/RP13 /CN13/PMRD/RB13
1
2
3
4
5
6
7
21
20
19
18
17
16
15
(1)
(1)
PGEC1/AN3/C2IN+/RP1 /CN5/RB1
AN12/RP12 /CN14/PMD0/RB12
(1)
(1)
AN4/C1IN-/RP2 /CN6/RB2
dsPIC33FJ32GP302
dsPIC33FJ64GP202
dsPIC33FJ128GP202
PGEC2/TMS/RP11 /CN15/PMD1/RB11
(1)
(1)
AN5/C1IN+/RP3 /CN7/RB3
PGED2/TDI/RP10 /CN16/PMD2/RB10
VSS
VCAP/VDDCORE
VSS
OSC1/CLKI/CN30/RA2
(1)
OSC2/CLKO/CN29/PMA0/RA3
TDO/SDA1/RP9 /CN21/PMD3/RB9
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70292D-page 8
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
44-Pin QFN(2)
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/DAC1RM/RP16(1)/CN8/RC0
AN7/DAC1LM/RP17(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
PGEC2/RP11(1)/CN15/PMD1/RB11
PGED2/RP10(1)/CN16/PMD2/RB10
VCAP/VDDCORE
11
10
9
23
24
25
26
27
28
29
30
31
32
33
8
7
dsPIC33FJ64GP804
dsPIC33FJ128GP804
VSS
6
VSS
RP25(1)/CN19/PMA6/RC9
RP24(1)/CN20/PMA5/RC8
RP23(1)/CN17/PMA0/RC7
RP22(1)/CN18/PMA1/RC6
SDA1/RP9(1)/CN21/PMD3/RB9
5
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/PMA8/RA8
4
3
2
SOSCI/RP4(1)/CN1/RB4
1
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 9
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagrams (Continued)
44-Pin QFN(2)
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
11 AN11/RP13(1)/CN13/PMRD/RB13
23
24
25
26
27
28
29
30
31
32
33
AN12/RP12(1)/CN14/PMD0/RB12
10
PGEC2/RP11(1)/CN15/PMD1/RB11
9
PGED2/RP10(1)/CN16/PMD2/RB10
8
dsPIC33FJ32GP304
dsPIC33FJ64GP204
dsPIC33FJ128GP204
VCAP/VDDCORE
7
VSS
6
5
4
3
VSS
RP25(1)/CN19/PMA6/RC9
RP24(1)/CN20/PMA5/RC8
RP23(1)/CN17/PMA0/RC7
RP22(1)/CN18/PMA1/RC6
SDA1/RP9(1)/CN21/PMD3/RB9
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/PMA8/RA8
2
SOSCI/RP4(1)/CN1/RB4
1
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.
DS70292D-page 10
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagram
44-Pin TQFP
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN11/DAC1RN/RP13(1)/CN13/PMRD/RB13
11
10
9
8
7
23
24
25
26
27
28
29
30
31
32
33
AN12/DAC1RP/RP12(1)/CN14/PMD0/RB12
PGEC2/RP11(1)/CN15/PMD1/RB11
PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10
VCAP/VDDCORE
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/DAC1RM/RP16(1)/CN8/RC0
AN7/DAC1LM/RP17/(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
dsPIC33FJ64GP804
dsPIC33FJ128GP804 65
VSS
RP25(1)/CN19/PMA6/RC9
RP24(1)/CN20/PMA5/RC8
RP23(1)/CN17/PMA0/RC7
RP22(1)/CN18/PMA1/RC6
SDA1/RP9(1)/CN21/PMD3/RB9
VSS
4
3
2
1
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/PMA8/RA8
SOSCI/RP4(1)/CN1/RB4
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 11
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Pin Diagram
44-Pin TQFP
= Pins are up to 5V tolerant
AN4/C1IN-/RP2(1)/CN6/RB2
AN11/RP13(1)/CN13/PMRD/RB13
11
10
9
8
7
23
24
25
26
27
28
AN12/RP12(1)/CN14/PMD0/RB12
PGEC2/RP11(1)/CN15/PMD1/RB11
PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10
VCAP/VDDCORE
AN5/C1IN+/RP3(1)/CN7/RB3
AN6/RP16(1)/CN8/RC0
AN7/RP17(1)/CN9/RC1
AN8/CVREF/RP18(1)/PMA2/CN10/RC2
VDD
dsPIC33FJ32GP304
dsPIC33FJ64GP204
6
VSS
RP25(1)/CN19/PMA6/RC9
RP24(1)/CN20/PMA5/RC8
RP23(1)/CN17/PMA0/RC7
RP22(1)/CN18/PMA1/RC6
SDA1/RP9(1)/CN21/PMD3/RB9
5
3209 dsPIC33FJ128GP204
VSS
4
3
2
1
OSC1/CLKI/CN30/RA2
OSC2/CLKO/CN29/RA3
TDO/PMA8/RA8
31
32
33
SOSCI/RP4(1)/CN1/RB4
Note 1: The RPx pins can be used by any remappable peripheral. See the table “dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 Controller Families” in this section for the list of available peripherals.
DS70292D-page 12
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Table of Contents
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04 Product Families............................................. 5
1.0 Device Overview ........................................................................................................................................................................ 15
2.0 Guidelines for Getting Started with 16-Bit Digital Signal Controllers.......................................................................................... 21
3.0 CPU............................................................................................................................................................................................ 25
4.0 Memory Organization................................................................................................................................................................. 37
5.0 Flash Program Memory.............................................................................................................................................................. 73
6.0 Resets ....................................................................................................................................................................................... 79
7.0 Interrupt Controller ..................................................................................................................................................................... 87
8.0 Direct Memory Access (DMA).................................................................................................................................................. 129
9.0 Oscillator Configuration............................................................................................................................................................ 141
10.0 Power-Saving Features............................................................................................................................................................ 153
11.0 I/O Ports ................................................................................................................................................................................... 159
12.0 Timer1 ...................................................................................................................................................................................... 187
13.0 Timer2/3 and Timer4/5 feature ................................................................................................................................................ 189
14.0 Input Capture............................................................................................................................................................................ 195
15.0 Output Compare....................................................................................................................................................................... 197
16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 201
2
17.0 Inter-Integrated Circuit™ (I C™).............................................................................................................................................. 207
18.0 Universal Asynchronous Receiver Transmitter (UART)........................................................................................................... 215
19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 221
20.0 Data Converter Interface (DCI) Module.................................................................................................................................... 247
21.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 253
22.0 Audio Digital-to-Analog Converter (DAC)................................................................................................................................. 265
23.0 Comparator Module.................................................................................................................................................................. 271
24.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 277
25.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 287
26.0 Parallel Master Port (PMP)....................................................................................................................................................... 291
27.0 Special Features ...................................................................................................................................................................... 299
28.0 Instruction Set Summary.......................................................................................................................................................... 309
29.0 Development Support............................................................................................................................................................... 317
30.0 Electrical Characteristics.......................................................................................................................................................... 321
31.0 High Temperature Electrical Characteristics............................................................................................................................ 367
32.0 Packaging Information.............................................................................................................................................................. 377
Appendix A: Revision History............................................................................................................................................................. 387
Index .................................................................................................................................................................................................. 393
The Microchip Web Site..................................................................................................................................................................... 399
Customer Change Notification Service .............................................................................................................................................. 399
Customer Support.............................................................................................................................................................................. 399
Reader Response.............................................................................................................................................................................. 400
Product Identification System ............................................................................................................................................................ 401
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 13
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TO OUR VALUED CUSTOMERS
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An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
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DS70292D-page 14
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
This document contains device specific information for
1.0
DEVICE OVERVIEW
the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 Digital Signal
Controller (DSC) Devices. The dsPIC33F devices
contain extensive Digital Signal Processor (DSP)
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to the “dsPIC33F/PIC24H Family
Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest dsPIC33F/PIC24H Family
Reference Manual sections.
functionality with
microcontroller (MCU) architecture.
a
high performance 16-bit
Figure 1-1 shows a general block diagram of the
core
and
peripheral
modules
in
the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 families of devices.
Table 1-1 lists the functions of the various pins
shown in the pinout diagrams.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 15
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 1-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
PORTA
PORTB
16
16
16
8
16
DMA
RAM
Data Latch
Data Latch
X RAM
23
PCH PCL
Program Counter
Y RAM
PCU
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
16
DMA
Controller
23
16
16
PORTC
Address Generator Units
Address Latch
Program Memory
Data Latch
Remappable
Pins
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
16
Control Signals
to Various Blocks
DSP Engine
16 x 16
W Register Array
Power-up
Timer
Timing
Generation
OSC2/CLKO
OSC1/CLKI
Divide Support
16
Oscillator
Start-up Timer
FRC/LPRC
Oscillators
Power-on
Reset
16-bit ALU
Precision
Band Gap
Reference
Watchdog
Timer
16
Brown-out
Reset
Voltage
Regulator
VCAP/VDDCORE
VDD, VSS
MCLR
OC/
PWM1-4
Comparator
ECAN1
Timers
PMP/
EPSP
UART1, 2
ADC1
2 Ch.
1-5
DAC1
SPI1, 2
RTCC
IC1, 2, 7, 8
DCI
CNx
I2C1
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features pres-
ent on each device.
DS70292D-page 16
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS
Pin
Buffer
Type
PPS
Description
Type
AN0-AN12
CLKI
I
I
Analog
Analog input channels.
ST/CMOS No External clock source input. Always associated with OSC1 pin
function.
CLKO
O
—
No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
Always associated with OSC2 pin function.
OSC1
OSC2
I
ST/CMOS No Oscillator crystal input. ST buffer when configured in RC mode;
CMOS otherwise.
I/O
—
No Oscillator crystal output. Connects to crystal or resonator in Crystal
Oscillator mode. Optionally functions as CLKO in RC and EC modes.
SOSCI
I
ST/CMOS No 32.768 kHz low-power oscillator crystal input; CMOS otherwise.
SOSCO
O
—
No 32.768 kHz low-power oscillator crystal output.
CN0-CN30
I
ST
No Change notification inputs.
No Can be software programmed for internal weak pull-ups on all inputs.
IC1-IC2
IC7-IC8
I
I
ST
ST
Yes Capture inputs 1/2.
Yes Capture inputs 7/8.
OCFA
OC1-OC4
I
O
ST
—
Yes Compare Fault A input (for Compare Channels 1, 2, 3 and 4).
Yes Compare outputs 1 through 4.
INT0
INT1
INT2
I
I
I
ST
ST
ST
No External interrupt 0.
Yes External interrupt 1.
Yes External interrupt 2.
I/O
I/O
ST
ST
No PORTA is a bidirectional I/O port.
No PORTA is a bidirectional I/O port.
RA0-RA4
RA7-RA10
RB0-RB15
RC0-RC9
I/O
I/O
ST
ST
No PORTB is a bidirectional I/O port.
No PORTC is a bidirectional I/O port.
T1CK
T2CK
T3CK
T4CK
T5CK
I
I
I
I
I
ST
ST
ST
ST
ST
No Timer1 external clock input.
Yes Timer2 external clock input.
Yes Timer3 external clock input.
Yes Timer4 external clock input.
Yes Timer5 external clock input.
I
O
I
ST
—
ST
—
Yes UART1 clear to send.
Yes UART1 ready to send.
Yes UART1 receive.
U1CTS
U1RTS
U1RX
U1TX
O
Yes UART1 transmit.
I
O
I
ST
—
ST
—
Yes UART2 clear to send.
Yes UART2 ready to send.
Yes UART2 receive.
U2CTS
U2RTS
U2RX
U2TX
O
Yes UART2 transmit.
SCK1
SDI1
SDO1
I/O
I
O
ST
ST
—
Yes Synchronous serial clock input/output for SPI1.
Yes SPI1 data in.
Yes SPI1 data out.
SS1
I/O
ST
Yes SPI1 slave synchronization or frame pulse I/O.
SCK2
SDI2
SDO2
I/O
I
O
ST
ST
—
Yes Synchronous serial clock input/output for SPI2.
Yes SPI2 data in.
Yes SPI2 data out.
SS2
I/O
ST
Yes SPI2 slave synchronization or frame pulse I/O.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 17
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
PPS
Description
Type
SCL1
SDA1
ASCL1
ASDA1
I/O
I/O
I/O
I/O
ST
ST
ST
ST
No Synchronous serial clock input/output for I2C1.
No Synchronous serial data input/output for I2C1.
No Alternate synchronous serial clock input/output for I2C1.
No Alternate synchronous serial data input/output for I2C1.
TMS
TCK
TDI
I
I
I
ST
ST
ST
—
No JTAG Test mode select pin.
No JTAG test clock input pin.
No JTAG test data input pin.
No JTAG test data output pin.
TDO
O
C1RX
C1TX
I
O
ST
—
Yes ECAN1 bus receive pin.
Yes ECAN1 bus transmit pin.
RTCC
CVREF
O
O
—
No Real-Time Clock Alarm Output.
ANA
No Comparator Voltage Reference Output.
C1IN-
C1IN+
C1OUT
I
I
O
ANA
ANA
—
No Comparator 1 Negative Input.
No Comparator 1 Positive Input.
Yes Comparator 1 Output.
C2IN-
C2IN+
C2OUT
I
I
O
ANA
ANA
—
No Comparator 2 Negative Input.
No Comparator 2 Positive Input.
Yes Comparator 2 Output.
PMA0
I/O
TTL/ST
No Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and
Output (Master modes).
PMA1
I/O
TTL/ST
No Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and
Output (Master modes).
PMA2 -PMPA10
PMBE
PMCS1
O
O
O
—
—
—
No Parallel Master Port Address (Demultiplexed Master Modes).
No Parallel Master Port Byte Enable Strobe.
No Parallel Master Port Chip Select 1 Strobe.
No Parallel Master Port Data (Demultiplexed Master mode) or Address/
Data (Multiplexed Master modes).
PMD0-PMPD7
I/O
TTL/ST
PMRD
PMWR
O
O
—
—
No Parallel Master Port Read Strobe.
No Parallel Master Port Write Strobe.
O
O
O
—
—
—
No DAC1 Right Channel Negative Output.
No DAC1 Right Channel Positive Output.
No DAC1 Right Channel Middle Point Value (typically 1.65V).
DAC1RN
DAC1RP
DAC1RM
O
O
O
—
—
—
No DAC1 Left Channel Negative Output.
No DAC1 Left Channel Positive Output.
No DAC1 Left Channel Middle Point Value (typically 1.65V).
DAC1LN
DAC1LP
DAC1LM
I/O
I/O
I
ST
ST
ST
—
Yes Data Converter Interface frame synchronization pin.
Yes Data Converter Interface serial clock input/output pin.
Yes Data Converter Interface serial data input pin
Yes Data Converter Interface serial data output pin.
COFS
CSCK
CSDI
O
CSDO
PGWD1
PGEC1
PGWD2
PGEC2
PGWD3
PGEC3
I/O
ST
ST
ST
ST
ST
ST
No Data I/O pin for programming/debugging communication channel 1.
No Clock input pin for programming/debugging communication channel 1.
No Data I/O pin for programming/debugging communication channel 2.
No Clock input pin for programming/debugging communication channel 2.
No Data I/O pin for programming/debugging communication channel 3.
No Clock input pin for programming/debugging communication channel 3.
I
I/O
I
I/O
I
I/P
ST
No Master Clear (Reset) input. This pin is an active-low Reset to the
device.
MCLR
AVDD
P
P
No Positive supply for analog modules. This pin must be connected at all
times.
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
DS70292D-page 18
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 1-1:
Pin Name
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin
Buffer
Type
PPS
Description
Type
AVSS
P
P
P
P
I
P
—
No Ground reference for analog modules.
No Positive supply for peripheral logic and I/O pins.
No CPU logic filter capacitor connection.
No Ground reference for logic and I/O pins.
No Analog voltage reference (high) input.
No Analog voltage reference (low) input.
VDD
VCAP/VDDCORE
Vss
—
—
VREF+
VREF-
Analog
Analog
I
Legend: CMOS = CMOS compatible input or output
ST = Schmitt Trigger input with CMOS levels
TTL = TTL input buffer
Analog = Analog input
O = Output
PPS = Peripheral Pin Select
P = Power
I = Input
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 19
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 20
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2.2
Decoupling Capacitors
2.0
GUIDELINES FOR GETTING
STARTED WITH 16-BIT
DIGITAL SIGNAL
The use of decoupling capacitors on every pair of
power supply pins, such as VDD, VSS, AVDD and
AVSS is required.
CONTROLLERS
Consider the following criteria when using decoupling
capacitors:
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
• Value and type of capacitor: Recommendation
of 0.1 µF (100 nF), 10-20V. This capacitor should
be a low-ESR and have resonance frequency in
the range of 20 MHz and higher. It is
dsPIC33FJ128GPX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to the “dsPIC33F/PIC24H
Family Reference Manual”, which is
available from the Microchip website
(www.microchip.com).
recommended that ceramic capacitors be used.
• Placement on the printed circuit board: The
decoupling capacitors should be placed as close
to the pins as possible. It is recommended to
place the capacitors on the same side of the
board as the device. If space is constricted, the
capacitor can be placed on another layer on the
PCB using a via; however, ensure that the trace
length from the pin to the capacitor is within
one-quarter inch (6 mm) in length.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Handling high frequency noise: If the board is
experiencing high frequency noise, upward of
tens of MHz, add a second ceramic-type capacitor
in parallel to the above described decoupling
capacitor. The value of the second capacitor can
be in the range of 0.01 µF to 0.001 µF. Place this
second capacitor next to the primary decoupling
capacitor. In high-speed circuit designs, consider
implementing a decade pair of capacitances as
close to the power and ground pins as possible.
For example, 0.1 µF in parallel with 0.001 µF.
2.1
Basic Connection Requirements
Getting started with the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 family of 16-bit Digital Signal Controllers (DSCs)
requires attention to a minimal set of device pin
connections before proceeding with development. The
following is a list of pin names, which must always be
connected:
• Maximizing performance: On the board layout
from the power supply circuit, run the power and
return traces to the decoupling capacitors first,
and then to the device pins. This ensures that the
decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum thereby reducing PCB track inductance.
• All VDD and VSS pins
(see Section 2.2 “Decoupling Capacitors”)
• All AVDD and AVSS pins (regardless if ADC module
is not used)
(see Section 2.2 “Decoupling Capacitors”)
• VCAP/VDDCORE
(see Section 2.3 “Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)”)
• MCLR pin
(see Section 2.4 “Master Clear (MCLR) Pin”)
• PGECx/PGEDx pins used for In-Circuit Serial
Programming™ (ICSP™) and debugging purposes
(see Section 2.5 “ICSP Pins”)
• OSC1 and OSC2 pins when external oscillator
source is used
(see Section 2.6 “External Oscillator Pins”)
Additionally, the following pins may be required:
• VREF+/VREF- pins used when external voltage
reference for ADC module is implemented
Note:
The AVDD and AVSS pins must be
connected independent of the ADC
voltage reference source.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 21
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 2-1:
RECOMMENDED
MINIMUM CONNECTION
2.4
Master Clear (MCLR) Pin
The MCLR pin provides for two specific device
functions:
0.1 µF
Ceramic
• Device Reset
VDD
• Device programming and debugging
During device programming and debugging, the
resistance and capacitance that can be added to the
pin must be considered. Device programmers and
debuggers drive the MCLR pin. Consequently,
specific voltage levels (VIH and VIL) and fast signal
transitions must not be adversely affected. Therefore,
specific values of R and C will need to be adjusted
based on the application and PCB requirements.
R
R1
MCLR
C
dsPIC33F
VDD
VSS
VDD
For example, as shown in Figure 2-2, it is
recommended that the capacitor C, be isolated from
the MCLR pin during programming and debugging
operations.
VSS
0.1 µF
Ceramic
0.1 µF
Ceramic
0.1 µF
0.1 µF
Ceramic
Ceramic
Place the components shown in Figure 2-2 within
one-quarter inch (6 mm) from the MCLR pin.
10
FIGURE 2-2:
EXAMPLE OF MCLR PIN
CONNECTIONS
2.2.1
TANK CAPACITORS
On boards with power traces running longer than six
inches in length, it is suggested to use a tank capacitor
for integrated circuits including DSCs to supply a local
power source. The value of the tank capacitor should
be determined based on the trace resistance that con-
nects the power supply source to the device, and the
maximum current drawn by the device in the applica-
tion. In other words, select the tank capacitor so that it
meets the acceptable voltage sag at the device. Typical
values range from 4.7 µF to 47 µF.
VDD
R
R1
MCLR
dsPIC33F
JP
C
2.3
Capacitor on Internal Voltage
Regulator (VCAP/VDDCORE)
Note 1: R 10 k is recommended. A suggested
starting value is 10 k. Ensure that the
MCLR pin VIH and VIL specifications are met.
A low-ESR (< 5 Ohms) capacitor is required on the
VCAP/VDDCORE pin, which is used to stabilize the
voltage regulator output voltage. The VCAP/VDDCORE
pin must not be connected to VDD, and must have a
capacitor between 4.7 µF and 10 µF, 16V connected to
ground. The type can be ceramic or tantalum. Refer to
Section 30.0 “Electrical Characteristics” for
additional information.
2: R1 470 will limit any current flowing into
MCLR from the external capacitor C, in the
event of MCLR pin breakdown, due to
Electrostatic Discharge (ESD) or Electrical
Overstress (EOS). Ensure that the MCLR pin
VIH and VIL specifications are met.
The placement of this capacitor should be close to the
VCAP/VDDCORE. It is recommended that the trace
length not exceed one-quarter inch (6 mm). Refer to
Section 27.2 “On-Chip Voltage Regulator” for
details.
DS70292D-page 22
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2.5
ICSP Pins
2.6
External Oscillator Pins
The PGECx and PGEDx pins are used for In-Circuit
Serial Programming™ (ICSP™) and debugging pur-
poses. It is recommended to keep the trace length
between the ICSP connector and the ICSP pins on the
device as short as possible. If the ICSP connector is
expected to experience an ESD event, a series resistor
is recommended, with the value in the range of a few
tens of Ohms, not to exceed 100 Ohms.
Many DSCs have options for at least two oscillators: a
high-frequency primary oscillator and a low-frequency
secondary oscillator (refer to Section 9.0 “Oscillator
Configuration” for details).
The oscillator circuit should be placed on the same
side of the board as the device. Also, place the
oscillator circuit close to the respective oscillator pins,
not exceeding one-half inch (12 mm) distance
between them. The load capacitors should be placed
next to the oscillator itself, on the same side of the
board. Use a grounded copper pour around the
oscillator circuit to isolate them from surrounding
circuits. The grounded copper pour should be routed
directly to the MCU ground. Do not run any signal
traces or power traces inside the ground pour. Also, if
using a two-sided board, avoid any traces on the
other side of the board where the crystal is placed. A
suggested layout is shown in Figure 2-3.
Pull-up resistors, series diodes, and capacitors on the
PGECx and PGEDx pins are not recommended as they
will interfere with the programmer/debugger communi-
cations to the device. If such discrete components are
an application requirement, they should be removed
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and
timing requirements information in the respective
device Flash programming specification for information
on capacitive loading limits and pin input voltage high
(VIH) and input low (VIL) requirements.
FIGURE 2-3:
SUGGESTED PLACEMENT
OF THE OSCILLATOR
CIRCUIT
Ensure that the “Communication Channel Select” (i.e.,
PGECx/PGEDx pins) programmed into the device
matches the physical connections for the ICSP to
MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™.
For more information on ICD 2, ICD 3 and REAL ICE
connection requirements, refer to the following
documents that are available on the Microchip website.
• “MPLAB® ICD 2 In-Circuit Debugger User’s
Guide” DS51331
• “Using MPLAB® ICD 2” (poster) DS51265
• “MPLAB® ICD 2 Design Advisory” DS51566
• “Using MPLAB® ICD 3 In-Circuit Debugger”
Main Oscillator
Guard Ring
13
14
15
16
17
18
19
20
Guard Trace
Secondary
Oscillator
(poster) DS51765
• “MPLAB® ICD 3 Design Advisory” DS51764
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s
Guide” DS51616
• “Using MPLAB® REAL ICE™” (poster) DS51749
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 23
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2.7
Oscillator Value Conditions on
Device Start-up
If the PLL of the target device is enabled and
configured for the device start-up oscillator, the
maximum oscillator source frequency must be limited
to 4 MHz < FIN < 8 MHz to comply with device PLL
start-up conditions. This means that if the external
oscillator frequency is outside this range, the
application must start-up in the FRC mode first. The
default PLL settings after a POR with an oscillator
frequency outside this range will violate the device
operating speed.
Once the device powers up, the application firmware
can initialize the PLL SFRs, CLKDIV and PLLDBF to a
suitable value, and then perform a clock switch to the
Oscillator + PLL clock source. Note that clock switching
must be enabled in the device Configuration word.
2.8
Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the A/D input
pins (ANx) as “digital” pins, by setting all bits in the
AD1PCFGL register.
The bits in this register that correspond to the A/D pins
that are initialized by MPLAB ICD 2, ICD 3 or REAL
ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain A/D pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFGL register during initialization of the ADC
module.
When MPLAB ICD 2, ICD 3 or REAL ICE is used as a
programmer, the user application firmware must
correctly configure the AD1PCFGL register. Automatic
initialization of this register is only done during
debugger operation. Failure to correctly configure the
register(s) will result in all A/D pins being recognized as
analog input pins, resulting in the port value being read
as a logic ‘0’, which may affect user application
functionality.
2.9
Unused I/Os
Unused I/O pins should be configured as outputs and
driven to a logic-low state.
Alternatively, connect a 1k to 10k resistor to VSS on
unused pins and drive the output to logic low.
DS70292D-page 24
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
cycle. As a result, three parameter instructions can be
supported, allowing A + B = C operations to be
executed in a single cycle.
3.0
CPU
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
A block diagram of the CPU is shown in Figure 3-1, and
the programmer’s model for the dsPIC33FJ32GP302/
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 2. CPU” (DS70204) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
304,
dsPIC33FJ64GPX02/X04,
and
dsPIC33FJ128GPX02/X04 is shown in Figure 3-2.
3.2
Data Addressing Overview
The data space can be addressed as 32K words or
64 Kbytes and is split into two blocks, referred to as X
and Y data memory. Each memory block has its own
independent Address Generation Unit (AGU). The
MCU class of instructions operates solely through the
X memory AGU, which accesses the entire memory
map as one linear data space. Certain DSP instructions
operate through the X and Y AGUs to support dual
operand reads, which splits the data address space
into two parts. The X and Y data space boundary is
device-specific.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
3.1
Overview
Overhead-free circular buffers (Modulo Addressing
mode) are supported in both X and Y address spaces.
The Modulo Addressing removes the software
boundary checking overhead for DSP algorithms.
Furthermore, the X AGU circular addressing can be
used with any of the MCU class of instructions. The X
AGU also supports Bit-Reversed Addressing to greatly
simplify input or output data reordering for radix-2 FFT
algorithms.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 CPU module has
a 16-bit (data) modified Harvard architecture with an
enhanced instruction set, including significant support
for DSP. The CPU has a 24-bit instruction word with a
variable length opcode field. The Program Counter
(PC) is 23 bits wide and addresses up to 4M x 24 bits
of user program memory space. The actual amount of
program memory implemented varies by device. A
single-cycle instruction prefetch mechanism is used to
help maintain throughput and provides predictable
execution. All instructions execute in a single cycle,
with the exception of instructions that change the
program flow, the double-word move (MOV.D)
instruction and the table instructions. Overhead-free
program loop constructs are supported using the DO
and REPEAT instructions, both of which are
interruptible at any time.
The upper 32 Kbytes of the data space memory map
can optionally be mapped into program space at any
16K program word boundary defined by the 8-bit
Program Space Visibility Page (PSVPAG) register. The
program-to-data-space mapping feature lets any
instruction access program space as if it were data
space.
3.3
DSP Engine Overview
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices have six-
teen, 16-bit working registers in the programmer’s
model. Each of the working registers can serve as a
data, address or address offset register. The 16th work-
ing register (W15) operates as a software Stack Pointer
(SP) for interrupts and calls.
The DSP engine features a high-speed 17-bit by 17-bit
multiplier, 40-bit ALU, two 40-bit saturating
a
accumulators and a 40-bit bidirectional barrel shifter.
The barrel shifter is capable of shifting a 40-bit value up
to 16 bits right or left, in a single cycle. The DSP
instructions operate seamlessly with all other
instructions and have been designed for optimal real-
time performance. The MAC instruction and other
associated instructions can concurrently fetch two data
operands from memory while multiplying two W
registers and accumulating and optionally saturating
the result in the same cycle. This instruction
functionality requires that the RAM data space be split
for these instructions and linear for all others. Data
space partitioning is achieved in a transparent and
flexible manner through dedicating certain working
registers to each address space.
There are two classes of instruction in the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices: MCU and
DSP. These two instruction classes are seamlessly
integrated into a single CPU. The instruction set
includes many addressing modes and is designed for
optimum C compiler efficiency. For most instructions,
the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 is capable of exe-
cuting a data (or program data) memory read, a work-
ing register (data) read, a data memory write and a
program (instruction) memory read per instruction
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 25
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
3.4
Special MCU Features
X04, and dsPIC33FJ128GPX02/X04 supports 16/16
and 32/16 divide operations, both fractional and inte-
ger. All divide instructions are iterative operations. They
must be executed within a REPEATloop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without loss of data.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 features a 17-bit
by 17-bit single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for
special operations, such as (-1.0) x (-1.0).
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
FIGURE 3-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 CPU CORE BLOCK DIAGRAM
PSV and Table
Data Access
Control Block
Y Data Bus
X Data Bus
Interrupt
Controller
16
16
16
8
16
Data Latch
Data Latch
X RAM
DMA
RAM
23
16
PCH PCL
Program Counter
PCU
Y RAM
23
Address
Latch
Address
Latch
Loop
Control
Logic
Stack
Control
Logic
23
16
16
DMA
Controller
Address Generator Units
Address Latch
Program Memory
Data Latch
EA MUX
ROM Latch
24
16
16
Instruction
Decode and
Control
Instruction Reg
Control Signals
to Various Blocks
16
DSP Engine
16 x 16
W Register Array
Divide Support
16
16-bit ALU
16
To Peripheral Modules
DS70292D-page 26
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 3-2:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 PROGRAMMER’S MODEL
D15
D0
W0/WREG
W1
PUSH.SShadow
DOShadow
W2
W3
Legend
W4
DSP Operand
Registers
W5
W6
W7
Working Registers
W8
W9
DSP Address
Registers
W10
W11
W12/DSP Offset
W13/DSP Write Back
W14/Frame Pointer
W15/Stack Pointer
SPLIM
Stack Pointer Limit Register
AD15
AD39
ACCA
AD31
AD0
DSP
Accumulators
ACCB
PC22
PC0
0
Program Counter
0
7
TBLPAG
Data Table Page Address
7
0
PSVPAG
Program Space Visibility Page Address
15
0
0
RCOUNT
REPEATLoop Counter
DOLoop Counter
15
DCOUNT
22
0
DOSTART
DOEND
DOLoop Start Address
DOLoop End Address
22
15
0
Core Configuration Register
CORCON
OA OB SA SB OAB SAB DA DC
SRH
IPL0 RA
N
OV
Z
C
IPL2 IPL1
STATUS Register
SRL
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 27
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.5
CPU Control Registers
REGISTER 3-1:
SR: CPU STATUS REGISTER
R-0
OA
R-0
OB
R/C-0
SA(1)
R/C-0
SB(1)
R-0
R/C-0
SAB(4)
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0(3)
R/W-0(3)
IPL<2:0>(2)
R/W-0(3)
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
OA: Accumulator A Overflow Status bit
1= Accumulator A overflowed
0= Accumulator A has not overflowed
OB: Accumulator B Overflow Status bit
1= Accumulator B overflowed
0= Accumulator B has not overflowed
SA: Accumulator A Saturation ‘Sticky’ Status bit(1)
1= Accumulator A is saturated or has been saturated at some time
0= Accumulator A is not saturated
SB: Accumulator B Saturation ‘Sticky’ Status bit(1)
1= Accumulator B is saturated or has been saturated at some time
0= Accumulator B is not saturated
OAB: OA || OB Combined Accumulator Overflow Status bit
1= Accumulators A or B have overflowed
0= Neither Accumulators A or B have overflowed
SAB: SA || SB Combined Accumulator (Sticky) Status bit(4)
1= Accumulators A or B are saturated or have been saturated at some time in the past
0= Neither Accumulator A or B are saturated
DA: DOLoop Active bit
1= DOloop in progress
0= DOloop not in progress
bit 8
DC: MCU ALU Half Carry/Borrow bit
1= A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data)
of the result occurred
0= No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized
data) of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
DS70292D-page 28
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 3-1:
SR: CPU STATUS REGISTER (CONTINUED)
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
bit 4
bit 3
bit 2
RA: REPEATLoop Active bit
1= REPEATloop in progress
0= REPEATloop not in progress
N: MCU ALU Negative bit
1= Result was negative
0= Result was non-negative (zero or positive)
OV: MCU ALU Overflow bit
This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that
causes the sign bit to change state.
1= Overflow occurred for signed arithmetic (in this arithmetic operation)
0= No overflow occurred
bit 1
bit 0
Z: MCU ALU Zero bit
1= An operation that affects the Z bit has set it at some time in the past
0= The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result)
C: MCU ALU Carry/Borrow bit
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Note 1: This bit can be read or cleared (not set).
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read only when NSTDIS = 1(INTCON1<15>).
4: This bit can be read or cleared (not set). Clearing this bit clears SA and SB.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 29
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT(1)
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 15-13
bit 12
Unimplemented: Read as ‘0’
US: DSP Multiply Unsigned/Signed Control bit
1= DSP engine multiplies are unsigned
0= DSP engine multiplies are signed
bit 11
EDT: Early DOLoop Termination Control bit(1)
1= Terminate executing DOloop at end of current loop iteration
0= No effect
bit 10-8
DL<2:0>: DOLoop Nesting Level Status bits
111= 7 DOloops active
•
•
•
001= 1 DOloop active
000= 0 DOloops active
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
SATA: ACCA Saturation Enable bit
1= Accumulator A saturation enabled
0= Accumulator A saturation disabled
SATB: ACCB Saturation Enable bit
1= Accumulator B saturation enabled
0= Accumulator B saturation disabled
SATDW: Data Space Write from DSP Engine Saturation Enable bit
1= Data space write saturation enabled
0= Data space write saturation disabled
ACCSAT: Accumulator Saturation Mode Select bit
1= 9.31 saturation (super saturation)
0= 1.31 saturation (normal saturation)
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
PSV: Program Space Visibility in Data Space Enable bit
1= Program space visible in data space
0= Program space not visible in data space
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
DS70292D-page 30
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 3-2:
CORCON: CORE CONTROL REGISTER (CONTINUED)
bit 1
RND: Rounding Mode Select bit
1= Biased (conventional) rounding enabled
0= Unbiased (convergent) rounding enabled
bit 0
IF: Integer or Fractional Multiplier Mode Select bit
1= Integer mode enabled for DSP multiply ops
0= Fractional mode enabled for DSP multiply ops
Note 1: This bit is always read as ‘0’.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU interrupt priority level.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 31
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.6.2
DIVIDER
3.6
Arithmetic Logic Unit (ALU)
The divide block supports 32-bit/16-bit and 16-bit/16-bit
signed and unsigned integer divide operations with the
following data sizes:
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 ALU is 16 bits
wide and is capable of addition, subtraction, bit shifts
and logic operations. Unless otherwise mentioned,
arithmetic operations are two’s complement in nature.
Depending on the operation, the ALU can affect the
values of the Carry (C), Zero (Z), Negative (N),
Overflow (OV) and Digit Carry (DC) Status bits in the
SR register. The C and DC Status bits operate as
Borrow and Digit Borrow bits, respectively, for
subtraction operations.
1. 32-bit signed/16-bit signed divide
2. 32-bit unsigned/16-bit unsigned divide
3. 16-bit signed/16-bit signed divide
4. 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0
and the remainder in W1. 16-bit signed and unsigned
DIV instructions can specify any W register for both
the 16-bit divisor (Wn) and any W register (aligned)
pair (W(m + 1):Wm) for the 32-bit dividend. The divide
algorithm takes one cycle per bit of divisor, so both
32-bit/16-bit and 16-bit/16-bit instructions take the
same number of cycles to execute.
The ALU can perform 8-bit or 16-bit operations,
depending on the mode of the instruction that is used.
Data for the ALU operation can come from the W
register array or data memory, depending on the
addressing mode of the instruction. Likewise, output
data from the ALU can be written to the W register array
or a data memory location.
3.7
DSP Engine
The DSP engine consists of a high-speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
Refer to the “16-bit MCU and DSC Programmer’s Ref-
erence Manual” (DS70157) for information on the SR
bits affected by each instruction.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 CPU incorpo-
rates hardware support for both multiplication and divi-
sion. This includes a dedicated hardware multiplier and
support hardware for 16-bit-divisor division.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 is a single-cycle
instruction flow architecture; therefore, concurrent
operation of the DSP engine with MCU instruction flow
is not possible. However, some MCU ALU and DSP
engine resources can be used concurrently by the
same instruction (e.g., ED, EDAC).
3.6.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier of the
DSP engine, the ALU supports unsigned, signed or
mixed-sign operation in several MCU multiplication
modes:
The DSP engine can also perform inherent accumula-
tor-to-accumulator operations that require no additional
data. These instructions are ADD,SUBand NEG.
The DSP engine has options selected through bits in
the CPU Core Control register (CORCON), as listed
below:
• 16-bit x 16-bit signed
• 16-bit x 16-bit unsigned
• 16-bit signed x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit unsigned
• 16-bit unsigned x 5-bit (literal) unsigned
• 16-bit unsigned x 16-bit signed
• 8-bit unsigned x 8-bit unsigned
• Fractional or integer DSP multiply (IF)
• Signed or unsigned DSP multiply (US)
• Conventional or convergent rounding (RND)
• Automatic saturation on/off for ACCA (SATA)
• Automatic saturation on/off for ACCB (SATB)
• Automatic saturation on/off for writes to data
memory (SATDW)
• Accumulator Saturation mode selection
(ACCSAT)
A block diagram of the DSP engine is shown in
Figure 3-3.
DS70292D-page 32
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 3-1:
DSP INSTRUCTIONS SUMMARY
Instruction Algebraic Operation
ACC Write Back
CLR
A = 0
Yes
No
ED
A = (x – y)2
A = A + (x – y)2
A = A + (x • y)
A = A + x2
No change in A
A = x • y
EDAC
MAC
No
Yes
No
MAC
MOVSAC
MPY
Yes
No
MPY
A = x 2
No
MPY.N
MSC
A = – x • y
A = A – x • y
No
Yes
FIGURE 3-3:
DSP ENGINE BLOCK DIAGRAM
S
a
40
40-bit Accumulator A
40-bit Accumulator B
t
16
40
Round
Logic
u
r
a
t
Carry/Borrow Out
Carry/Borrow In
Saturate
Adder
e
Negate
40
40
40
Barrel
Shifter
16
40
Sign-Extend
32
16
Zero Backfill
32
33
17-bit
Multiplier/Scaler
16
16
To/From W Array
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 33
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The adder/subtracter generates Overflow Status bits,
SA/SB and OA/OB, which are latched and reflected in
the STATUS register:
3.7.1
MULTIPLIER
The 17-bit x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the
multiplier input value. The output of the 17-bit x 17-bit
multiplier/scaler is a 33-bit value that is sign-extended
to 40 bits. Integer data is inherently represented as a
signed two’s complement value, where the Most
Significant bit (MSb) is defined as a sign bit. The range
of an N-bit two’s complement integer is -2N-1 to 2N-1 – 1.
• Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
• Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits are not identical to each other.
The adder has an additional saturation block that
controls accumulator data saturation, if selected. It
uses the result of the adder, the Overflow Status bits
described
previously
and
the
SAT<A:B>
• For a 16-bit integer, the data range is -32768
(0x8000) to 32767 (0x7FFF) including 0.
(CORCON<7:6>) and ACCSAT (CORCON<4>) mode
control bits to determine when and to what value to
saturate.
• For a 32-bit integer, the data range is -
2,147,483,648 (0x8000 0000) to 2,147,483,647
(0x7FFF FFFF).
Six STATUS register bits support saturation and
overflow:
When the multiplier is configured for fractional
multiplication, the data is represented as a two’s
complement fraction, where the MSb is defined as a
sign bit and the radix point is implied to lie just after the
sign bit (QX format). The range of an N-bit two’s
complement fraction with this implied radix point is -1.0
to (1 – 21-N). For a 16-bit fraction, the Q15 data range
is -1.0 (0x8000) to 0.999969482 (0x7FFF) including 0
and has a precision of 3.01518x10-5. In Fractional
mode, the 16 x 16 multiply operation generates a 1.31
• OA: ACCA overflowed into guard bits
• OB: ACCB overflowed into guard bits
• SA: ACCA saturated (bit 31 overflow and
saturation)
or
ACCA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
• SB: ACCB saturated (bit 31 overflow and
saturation)
or
ACCB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
product that has a precision of 4.65661 x 10-10
.
The same multiplier is used to support the MCU
multiply instructions, which include integer 16-bit
signed, unsigned and mixed sign multiply operations.
• OAB: Logical OR of OA and OB
• SAB: Logical OR of SA and SB
The MUL instruction can be directed to use byte or
word-sized operands. Byte operands direct a 16-bit
result, and word operands direct a 32-bit result to the
specified registers in the W array.
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the
corresponding Overflow Trap Flag Enable bits (OVATE,
OVBTE) in the INTCON1 register are set (refer to
Section 7.0 “Interrupt Controller”). This allows the
user application to take immediate action, for example,
to correct system gain.
3.7.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation
source
and
post-accumulation
destination. For the ADDand LACinstructions, the data
to be accumulated or loaded can be optionally scaled
using the barrel shifter prior to accumulation.
The SA and SB bits are modified each time data
passes through the adder/subtracter, but can only be
cleared by the user application. When set, they indicate
that the accumulator has overflowed its maximum
range (bit 31 for 32-bit saturation or bit 39 for 40-bit sat-
uration) and is saturated (if saturation is enabled).
When saturation is not enabled, SA and SB default to
bit 39 overflow and thus indicate that a catastrophic
overflow has occurred. If the COVTE bit in the
INTCON1 register is set, the SA and SB bits generate
an arithmetic warning trap when saturation is disabled.
3.7.2.1
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side, and either true or complement
data into the other input.
• In the case of addition, the Carry/Borrow input is
active-high and the other input is true data (not
complemented).
• In the case of subtraction, the Carry/Borrow input
is active-low and the other input is complemented.
DS70292D-page 34
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The Overflow and Saturation Status bits can
optionally be viewed in the STATUS Register (SR) as
the logical OR of OA and OB (in bit OAB) and the
logical OR of SA and SB (in bit SAB). Programmers
can check one bit in the STATUS register to
determine if either accumulator has overflowed, or
one bit to determine if either accumulator has
saturated. This is useful for complex number
arithmetic, which typically uses both accumulators.
3.7.3.1
Round Logic
The round logic is a combinational block that performs
a conventional (biased) or convergent (unbiased)
round function during an accumulator write (store). The
Round mode is determined by the state of the RND bit
in the CORCON register. It generates a 16-bit, 1.15
data value that is passed to the data space write
saturation logic. If rounding is not indicated by the
instruction, a truncated 1.15 data value is stored and
the least significant word is simply discarded.
The device supports three Saturation and Overflow
modes:
Conventional rounding zero-extends bit 15 of the accu-
mulator and adds it to the ACCxH word (bits 16 through
31 of the accumulator).
• Bit 39 Overflow and Saturation:
When bit 39 overflow and saturation occurs, the
saturation logic loads the maximally positive 9.31
(0x7FFFFFFFFF) or maximally negative 9.31 value
(0x8000000000) into the target accumulator. The
SA or SB bit is set and remains set until cleared by
the user application. This condition is referred to as
‘super saturation’ and provides protection against
erroneous data or unexpected algorithm problems
(such as gain calculations).
• If the ACCxL word (bits 0 through 15 of the accu-
mulator) is between 0x8000 and 0xFFFF (0x8000
included), ACCxH is incremented.
• If ACCxL is between 0x0000 and 0x7FFF, ACCxH
is left unchanged.
A consequence of this algorithm is that over a succes-
sion of random rounding operations, the value tends to
be biased slightly positive.
• Bit 31 Overflow and Saturation:
When bit 31 overflow and saturation occurs, the
saturation logic then loads the maximally positive
1.31 value (0x007FFFFFFF) or maximally nega-
tive 1.31 value (0x0080000000) into the target
accumulator. The SA or SB bit is set and remains
set until cleared by the user application. When
this Saturation mode is in effect, the guard bits are
not used, so the OA, OB or OAB bits are never
set.
Convergent (or unbiased) rounding operates in the
same manner as conventional rounding, except when
ACCxL equals 0x8000. In this case, the Least
Significant bit (bit 16 of the accumulator) of ACCxH is
examined:
• If it is ‘1’, ACCxH is incremented.
• If it is ‘0’, ACCxH is not modified.
Assuming that bit 16 is effectively random in nature,
this scheme removes any rounding bias that may
accumulate.
• Bit 39 Catastrophic Overflow:
The bit 39 Overflow Status bit from the adder is
used to set the SA or SB bit, which remains set
until cleared by the user application. No saturation
operation is performed, and the accumulator is
allowed to overflow, destroying its sign. If the
COVTE bit in the INTCON1 register is set, a
catastrophic overflow can initiate a trap exception.
The SAC and SAC.R instructions store either a
truncated (SAC), or rounded (SAC.R) version of the
contents of the target accumulator to data memory via
the
X
bus, subject to data saturation (see
Section 3.7.3.2 “Data Space Write Saturation”). For
the MAC class of instructions, the accumulator write-
back operation functions in the same manner,
addressing combined MCU (X and Y) data space
though the X bus. For this class of instructions, the data
is always subject to rounding.
3.7.3
ACCUMULATOR ‘WRITE BACK’
The MAC class of instructions (with the exception of
MPY, MPY.N, ED and EDAC) can optionally write a
rounded version of the high word (bits 31 through 16)
of the accumulator that is not targeted by the instruction
into data space memory. The write is performed across
the X bus into combined X and Y address space. The
following addressing modes are supported:
• W13, Register Direct:
The rounded contents of the non-target
accumulator are written into W13 as a
1.15 fraction.
• [W13] + = 2, Register Indirect with Post-Increment:
The rounded contents of the non-target accumu-
lator are written into the address pointed to by
W13 as a 1.15 fraction. W13 is then incremented
by 2 (for a word write).
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 35
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
3.7.3.2
Data Space Write Saturation
3.7.4
BARREL SHIFTER
In addition to adder/subtracter saturation, writes to data
space can also be saturated, but without affecting the
contents of the source accumulator. The data space
write saturation logic block accepts a 16-bit, 1.15
fractional value from the round logic block as its input,
together with overflow status from the original source
(accumulator) and the 16-bit round adder. These inputs
are combined and used to select the appropriate 1.15
fractional value as output to write to data space
memory.
The barrel shifter can perform up to 16-bit arithmetic or
logic right shifts, or up to 16-bit left shifts in a single
cycle. The source can be either of the two DSP
accumulators or the X bus (to support multi-bit shifts of
register or memory data).
The shifter requires a signed binary value to determine
both the magnitude (number of bits) and direction of the
shift operation. A positive value shifts the operand right.
A negative value shifts the operand left. A value of ‘0’
does not modify the operand.
If the SATDW bit in the CORCON register is set, data
(after rounding or truncation) is tested for overflow and
adjusted accordingly:
The barrel shifter is 40 bits wide, thereby obtaining a
40-bit result for DSP shift operations and a 16-bit result
for MCU shift operations. Data from the X bus is
presented to the barrel shifter between bit positions 16
and 31 for right shifts, and between bit positions 0 and
16 for left shifts.
• For input data greater than 0x007FFF, data
written to memory is forced to the maximum
positive 1.15 value, 0x7FFF.
• For input data less than 0xFF8000, data written to
memory is forced to the maximum negative 1.15
value, 0x8000.
The Most Significant bit of the source (bit 39) is used to
determine the sign of the operand being tested.
If the SATDW bit in the CORCON register is not set, the
input data is always passed through unmodified under
all conditions.
DS70292D-page 36
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.1
Program Address Space
4.0
MEMORY ORGANIZATION
The program address memory space of the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in Section 4.6
“Interfacing Program and Data Memory Spaces”.
Note:
This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
“Section 3. Data Memory” (DS70202) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access of program memory from the data space during
code execution.
The memory map for the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices is shown in Figure 4-1.
FIGURE 4-1:
PROGRAM MEMORY MAP FOR dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, AND dsPIC33FJ128GPX02/X04 DEVICES
dsPIC33FJ32GP302/304
dsPIC33FJ64GPX02/X04
dsPIC33FJ128GPX02/X04
0x000000
0x000002
0x000004
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
GOTOInstruction
Reset Address
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
Interrupt Vector Table
Reserved
0x0000FE
0x000100
0x000104
0x0001FE
0x000200
Alternate Vector Table
Alternate Vector Table
Alternate Vector Table
User Program
Flash Memory
(11264 instructions)
User Program
Flash Memory
(22016 instructions)
0x0057FE
0x005800
User Program
Flash Memory
(44032 instructions)
0x00ABFE
0x00AC00
Unimplemented
Unimplemented
(Read ‘0’s)
0x0157FE
0x015800
(Read ‘0’s)
Unimplemented
(Read ‘0’s)
0x7FFFFE
0x800000
Reserved
Reserved
Reserved
0xF7FFFE
0xF80000
0xF80017
0xF80018
Device Configuration
Registers
Device Configuration
Registers
Device Configuration
Registers
Reserved
Reserved
Reserved
0xFEFFFE
0xFF0000
0xFF0002
DEVID (2)
Reserved
DEVID (2)
Reserved
DEVID (2)
Reserved
0xFFFFFE
Note:
Memory areas are not shown to scale.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 37
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.1.1
PROGRAM MEMORY
ORGANIZATION
4.1.2
INTERRUPT AND TRAP VECTORS
All dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices reserve
the addresses between 0x00000 and 0x000200 for
hard-coded program execution vectors. A hardware
Reset vector is provided to redirect code execution
from the default value of the PC on device Reset to the
actual start of code. A GOTOinstruction is programmed
by the user application at 0x000000, with the actual
address for the start of code at 0x000002.
The program memory space is organized in word-
addressable blocks. Although it is treated as 24 bits
wide, it is more appropriate to think of each address of
the program memory as a lower and upper word, with
the upper byte of the upper word being unimplemented.
The lower word always has an even address, while the
upper word has an odd address (Figure 4-2).
Program memory addresses are always word-aligned
on the lower word, and addresses are incremented or
decremented by two during code execution. This
arrangement provides compatibility with data memory
space addressing and makes data in the program
memory space accessible.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices also have two
interrupt vector tables, located from 0x000004 to
0x0000FF and 0x000100 to 0x0001FF. These vector
tables allow each of the device interrupt sources to be
handled by separate Interrupt Service Routines (ISRs).
A more detailed discussion of the interrupt vector
tables is provided in Section 7.1 “Interrupt Vector
Table”.
FIGURE 4-2:
PROGRAM MEMORY ORGANIZATION
least significant word
PC Address
most significant word
23
msw
Address
(lsw Address)
16
8
0
0x000001
0x000003
0x000005
0x000007
0x000000
0x000002
0x000004
0x000006
00000000
00000000
00000000
00000000
Program Memory
‘Phantom’ Byte
(read as ‘0’)
Instruction Width
DS70292D-page 38
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
All word accesses must be aligned to an even address.
4.2
Data Address Space
Misaligned word data fetches are not supported, so
care must be taken when mixing byte and word
operations, or translating from 8-bit MCU code. If a
misaligned read or write is attempted, an address error
trap is generated. If the error occurred on a read, the
instruction underway is completed. If the error occurred
on a write, the instruction is executed but the write does
not occur. In either case, a trap is then executed,
allowing the system and/or user application to examine
the machine state prior to execution of the address
Fault.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 CPU has a
separate 16-bit-wide data memory space. The data
space is accessed using separate Address Generation
Units (AGUs) for read and write operations. The data
memory maps is shown in Figure 4-4.
All Effective Addresses (EAs) in the data memory space
are 16 bits wide and point to bytes within the data space.
This arrangement gives a data space address range of
64 Kbytes or 32K words. The lower half of the data
memory space (that is, when EA<15> = 0) is used for
implemented memory addresses, while the upper half
(EA<15> = 1) is reserved for the Program Space
Visibility area (see Section 4.6.3 “Reading Data from
Program Memory Using Program Space Visibility”).
All byte loads into any W register are loaded into the
Least Significant Byte. The Most Significant Byte is not
modified.
A sign-extend instruction (SE) is provided to allow user
applications to translate 8-bit signed data to 16-bit
signed values. Alternatively, for 16-bit unsigned data,
user applications can clear the MSB of any W register
by executing a zero-extend (ZE) instruction on the
appropriate address.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices implement up
to 16 Kbytes of data memory. Should an EA point to a
location outside of this area, an all-zero word or byte is
returned.
4.2.3
SFR SPACE
4.2.1
DATA SPACE WIDTH
The first 2 Kbytes of the Near Data Space, from 0x0000
to 0x07FF, is primarily occupied by Special Function
Registers (SFRs). These are used by the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 core and peripheral
modules for controlling the operation of the device.
The data memory space is organized in byte
addressable, 16-bit wide blocks. Data is aligned in data
memory and registers as 16-bit words, but all data
space EAs resolve to bytes. The Least Significant
Bytes (LSBs) of each word have even addresses, while
the Most Significant Bytes (MSBs) have odd
addresses.
SFRs are distributed among the modules that they
control, and are generally grouped together by module.
Much of the SFR space contains unused addresses;
these are read as ‘0’.
4.2.2
DATA MEMORY ORGANIZATION
AND ALIGNMENT
To maintain backward compatibility with PIC® MCU
devices and improve data space memory usage
Note:
The actual set of peripheral features and
interrupts varies by the device. Refer to
the corresponding device tables and pin-
out diagrams for device-specific
information.
efficiency,
the
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 instruction set supports both word and byte
operations. As a consequence of byte accessibility, all
effective address calculations are internally scaled to
step through word-aligned memory. For example, the
core recognizes that Post-Modified Register Indirect
Addressing mode [Ws++] results in a value of Ws + 1
for byte operations and Ws + 2 for word operations.
4.2.4
NEAR DATA SPACE
The 8 Kbyte area between 0x0000 and 0x1FFF is
referred to as the near data space. Locations in this
space are directly addressable via a 13-bit absolute
address field within all memory direct instructions.
Additionally, the whole data space is addressable using
MOV instructions, which support Memory Direct
Addressing mode with a 16-bit address field, or by
using Indirect Addressing mode using a working
register as an address pointer.
A data byte read, reads the complete word that
contains the byte, using the LSB of any EA to
determine which byte to select. The selected byte is
placed onto the LSB of the data path. That is, data
memory and registers are organized as two parallel
byte-wide entities with shared (word) address decode
but separate write lines. Data byte writes only write to
the corresponding side of the array or register that
matches the byte address.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 39
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 4-3:
DATA MEMORY MAP FOR dsPIC33FJ32GP302/304 DEVICES WITH 4 KB RAM
MSB
LSB
Address
Address
16 bits
MSB
LSB
0x0000
0x0000
2 Kbyte
SFR Space
SFR Space
0x07FF
0x0801
0x07FE
0x0800
X Data RAM (X)
6 Kbyte
Near
Data
0x0FFE
0x1000
0x0FFF
0x1001
Space
4 Kbyte
SRAM Space
Y Data RAM (Y)
DMA RAM
0x13FE
0x1400
0x13FF
0x1401
0x17FE
0x1800
0x17FF
0x1801
0x8001
0x8000
Optionally
Mapped
into Program
Memory
X Data
Unimplemented (X)
0xFFFF
0xFFFE
DS70292D-page 40
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 4-4:
DATA MEMORY MAP FOR dsPIC33FJ128GP202/204 AND dsPIC33FJ64GP202/
204 DEVICES WITH 8 KB RAM
MSB
Address
LSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
0x07FE
0x0800
0x07FF
0x0801
8 Kbyte
Near
Data
X Data RAM (X)
Space
8 Kbyte
0x17FF
0x1801
0x17FE
0x1800
SRAM Space
Y Data RAM (Y)
DMA RAM
0x1FFF
0x2001
0x1FFE
0x2000
0x27FF
0x2801
0x27FE
0x2800
0x8001
0x8000
X Data
Optionally
Mapped
Unimplemented (X)
into Program
Memory
0xFFFF
0xFFFE
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 41
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 4-5:
DATA MEMORY MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/
804 DEVICES WITH 16 KB RAM
LSB
Address
MSB
Address
16 bits
MSB
LSB
0x0000
0x0001
2 Kbyte
SFR Space
SFR Space
8 Kbyte
Near
0x07FE
0x0800
0x07FF
0x0801
Data
Space
X Data RAM (X)
0x1FFF
0x1FFE
0x27FF
0x2801
16 Kbyte
SRAM Space
0x27FE
0x2800
Y Data RAM (Y)
DMA RAM
0x3FFF
0x4001
0x3FFE
0x4000
0x47FF
0x4801
0x47FE
0x4800
0x8001
0x8000
X Data
Unimplemented (X)
Optionally
Mapped
into Program
Memory
0xFFFF
0xFFFE
DS70292D-page 42
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.2.5
X AND Y DATA SPACES
4.2.6
DMA RAM
The core has two data spaces, X and Y. These data
spaces can be considered either separate (for some
DSP instructions), or as one unified linear address
range (for MCU instructions). The data spaces are
accessed using two Address Generation Units (AGUs)
and separate data paths. This feature allows certain
instructions to concurrently fetch two words from RAM,
thereby enabling efficient execution of DSP algorithms
such as Finite Impulse Response (FIR) filtering and
Fast Fourier Transform (FFT).
Every dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 device contains
up to 2 Kbytes of dual ported DMA RAM located at
the end of Y data space, and is part of Y data space.
Memory locations in the DMA RAM space are
accessible simultaneously by the CPU and the DMA
controller module. DMA RAM is utilized by the DMA
controller to store data to be transferred to various
peripherals using DMA, as well as data transferred
from various peripherals using DMA. The DMA RAM
can be accessed by the DMA controller without
having to steal cycles from the CPU.
The X data space is used by all instructions and
supports all addressing modes. X data space has
separate read and write data buses. The X read data
bus is the read data path for all instructions that view
data space as combined X and Y address space. It is
also the X data prefetch path for the dual operand DSP
instructions (MACclass).
When the CPU and the DMA controller attempt to
concurrently write to the same DMA RAM location, the
hardware ensures that the CPU is given precedence in
accessing the DMA RAM location. Therefore, the DMA
RAM provides a reliable means of transferring DMA
data without ever having to stall the CPU.
The Y data space is used in concert with the X data
space by the MAC class of instructions (CLR, ED,
EDAC, MAC, MOVSAC, MPY, MPY.N and MSC) to
provide two concurrent data read paths.
Note:
DMA RAM can be used for general
purpose data storage if the DMA function
is not required in an application.
Both the X and Y data spaces support Modulo
Addressing mode for all instructions, subject to
addressing mode restrictions. Bit-Reversed Addressing
mode is only supported for writes to X data space.
All data memory writes, including in DSP instructions,
view data space as combined X and Y address space.
The boundary between the X and Y data spaces is
device-dependent and is not user-programmable.
All effective addresses are 16 bits wide and point to
bytes within the data space. Therefore, the data space
address range is 64 Kbytes, or 32K words, though the
implemented memory locations vary by device.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 43
TABLE 4-1:
CPU CORE REGISTERS MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
WREG0
WREG1
WREG2
WREG3
WREG4
WREG5
WREG6
WREG7
WREG8
WREG9
WREG10
WREG11
WREG12
WREG13
WREG14
WREG15
SPLIM
0000
0002
0004
0006
0008
000A
000C
000E
0010
0012
0014
0016
0018
001A
001C
001E
0020
0022
0024
0026
0028
002A
002C
002E
0030
0032
0034
0036
0038
003A
003C
003E
0040
0042
0044
0046
Working Register 0
Working Register 1
Working Register 2
Working Register 3
Working Register 4
Working Register 5
Working Register 6
Working Register 7
Working Register 8
Working Register 9
Working Register 10
Working Register 11
Working Register 12
Working Register 13
Working Register 14
Working Register 15
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0800
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
0000
xxxx
xxxx
xxxx
00xx
xxxx
00xx
0000
0020
0000
Stack Pointer Limit Register
ACCAL
ACCAL
ACCAH
ACCAU
ACCBL
ACCAH
ACCA<39>
ACCB<39>
ACCAU
ACCBL
ACCBH
ACCBH
ACCBU
PCL
ACCBU
Program Counter Low Word Register
PCH
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Program Counter High Byte Register
Table Page Address Pointer Register
TBLPAG
PSVPAG
RCOUNT
DCOUNT
DOSTARTL
DOSTARTH
DOENDL
DOENDH
SR
Program Memory Visibility Page Address Pointer Register
Repeat Loop Counter Register
DCOUNT<15:0>
DOSTARTL<15:1>
0
0
—
—
—
—
—
—
—
—
—
—
DOENDL<15:1>
—
—
—
—
DOSTARTH<5:0>
DOENDH
—
OA
—
—
OB
—
—
SA
—
—
—
—
SB
US
—
OAB
EDT
SAB
DA
DC
IPL<2:0>
SATB
RA
N
OV
Z
C
CORCON
MODCON
Legend:
DL<2:0>
SATA
SATDW ACCSAT
IPL3
PSV
RND
IF
XMODEN YMODEN
—
BWM<3:0>
YWM<3:0>
XWM<3:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-1:
CPU CORE REGISTERS MAP (CONTINUED)
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
0048
004A
004C
004E
0050
0052
XS<15:1>
XE<15:1>
YS<15:1>
YE<15:1>
0
1
0
1
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
BREN
—
XB<14:0>
DISICNT
—
Disable Interrupts Counter Register
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-2:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302
SFR
Name
Addr
SFR
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0060
0062
CN15IE
—
CN14IE
CN30IE
CN13IE
CN29IE
CN12IE
—
CN11IE
CN27IE
—
—
—
—
—
—
—
—
—
CN24IE
—
CN7IE
CN6IE
CN5IE
CN4IE
—
CN3IE
—
CN2IE
—
CN1IE
—
CN0IE
CNEN1
CNEN2
CNPU1
0000
0000
0000
0000
CN23IE
CN22IE
CN21IE
CN16IE
0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
006A CN30PUE CN29PUE CN27PUE
CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
CN16PUE
—
—
CN24PUE CN23PUE CN22PUE CN21PUE
—
—
—
—
CNPU2
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-3:
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0060
0062
CN15IE
—
CN14IE
CN30IE
CN13IE
CN29IE
CN12IE
CN28IE
CN11IE
CN27IE
CN10IE
CN26IE
CN9IE
CN8IE
CN7IE
CN6IE
CN5IE
CN4IE
CN3IE
CN2IE
CN1IE
CN0IE
CNEN1
CNEN2
CNPU1
0000
0000
0000
0000
CN25IE
CN24IE
CN23IE
CN22IE
CN21IE
CN20IE
CN19IE
CN18IE
CN17IE
CN16IE
0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE
006A CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
—
CNPU2
Legend:
TABLE 4-4:
INTERRUPT CONTROLLER REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
INTCON1 0080
INTCON2 0082
NSTDIS
ALTIVT
—
OVAERR OVBERR COVAERR COVBERR OVATE OVBTE COVTE SFTACERR DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL
—
0000
DISI
—
AD1IF
—
U1TXIF
T5IF
—
—
U1RXIF
T4IF
—
—
—
—
—
T2IF
IC8IF
—
—
OC2IF
IC7IF
—
—
IC2IF
—
—
—
T1IF
INT2EP
OC1IF
CMIF
INT1EP INT0EP 0000
IC1IF INT0IF 0000
MI2C1IF SI2C1IF 0000
IFS0
0084
0086
0088
008A
DMA1IF
U2RXIF
DMA4IF
RTCIF
SPI1IF SPI1EIF
T3IF
DMA0IF
INT1IF
DMA3IF
—
IFS1
U2TXIF
—
INT2IF
OC4IF
—
OC3IF DMA2IF
CNIF
C1IF(1)
—
IFS2
PMPIF
—
—
—
—
—
—
C1RXIF(1) SPI2IF SPI2EIF 0000
IFS3
—
DMA5IF
—
DCIIF
—
DCIEIF
—
—
—
—
—
—
—
—
—
0000
0000
IFS4
008C DAC1LIF(2) DAC1RIF(2)
—
—
—
C1TXIF(1) DMA7IF
DMA6IF
DMA0IE
INT1IE
DMA3IE
—
CRCIF
T1IE
CNIE
U2EIF
OC1IE
CMIE
U1EIF
IC1IE
IEC0
IEC1
IEC2
IEC3
IEC4
IPC0
IPC1
IPC2
IPC3
IPC4
IPC5
IPC6
IPC7
IPC8
IPC9
IPC11
IPC14
IPC15
IPC16
IPC17
IPC19
0094
0096
0098
009A
—
U2TXIE
—
DMA1IE
U2RXIE
DMA4IE
RTCIE
AD1IE
U1TXIE
T5IE
—
U1RXIE
T4IE
—
SPI1IE SPI1EIE
T3IE
T2IE
IC8IE
—
OC2IE
IC7IE
—
IC2IE
—
INT0IE 0000
INT2IE
OC4IE
—
OC3IE DMA2IE
MI2C1IE SI2C1IE 0000
PMPIE
—
—
—
—
—
C1IE(1) C1RXIE(1) SPI2IE SPI2EIE 0000
—
DMA5IE
—
DCIIE
—
DCIEIE
—
—
—
—
—
—
—
CRCIE
—
—
—
U1EIE
—
—
0000
0000
4444
4444
4444
0444
4444
4404
4444
4444
4444
0004
0440
4000
0444
4440
0444
4400
4444
009C DAC1LIE(2) DAC1RIE(2)
—
—
—
C1TXIE(1) DMA7IE
DMA6IE
U2EIE
00A4
00A6
00A8
00AA
00AC
00AE
00B0
00B2
00B4
00B6
00BA
00C0
00C2
00C4
00C6
00CA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
T1IP<2:0>
T2IP<2:0>
U1RXIP<2:0>
—
—
OC1IP<2:0>
OC2IP<2:0>
SPI1IP<2:0>
DMA1IP<2:0>
CMIP<2:0>
IC7IP<2:0>
OC4IP<2:0>
U2RXIP<2:0>
—
IC1IP<2:0>
INT0IP<2:0>
DMA0IP<2:0>
T3IP<2:0>
U1TXIP<2:0>
SI2C1IP<2:0>
INT1IP<2:0>
DMA2IP<2:0>
T5IP<2:0>
SPI2EIP<2:0>
DMA3IP<2:0>
—
—
—
IC2IP<2:0>
—
—
—
SPI1EIP<2:0>
AD1IP<2:0>
—
—
—
—
—
—
CNIP<2:0>
IC8IP<2:0>
T4IP<2:0>
U2TXIP<2:0>
C1IP<2:0>(1)
—
—
—
MI2C1IP<2:0>
—
—
—
—
—
—
—
—
—
OC3IP<2:0>
INT2IP<2:0>
SPI2IP<2:0>
—
—
—
—
—
—
C1RXIP<2:0>(1)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
DMA4IP<2:0>
—
—
PMPIP<2:0>
—
—
—
—
—
—
DCIEIP<2:0>
—
—
—
—
—
—
—
—
—
—
—
RTCIP<2:0>
U2EIP<2:0>
C1TXIP<2:0>(1)
DAC1RIP<2:0>(2)
—
DMA5IP<2:0>
U1EIP<2:0>
DMA7IP<2:0>
—
—
DCIIP<2:0>
—
CRCIP<2:0>
—
DAC1LIP<2:0>(2)
—
—
—
—
—
—
—
—
—
—
DMA6IP<2:0>
—
—
—
—
—
—
INTTREG 00E0
—
—
ILR<3:0>>
—
VECNUM<6:0>
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
2:
Interrupts disabled on devices without ECAN™ modules.
Interrupts disabled on devices without Audio DAC modules.
TABLE 4-5:
TIMER REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TMR1
0100
0102
0104
0106
Timer1 Register
Period Register 1
xxxx
FFFF
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
xxxx
xxxx
xxxx
FFFF
FFFF
0000
0000
PR1
T1CON
TMR2
TON
—
TSIDL
—
—
—
—
—
—
TGATE
TCKPS<1:0>
—
TSYNC
TCS
—
Timer2 Register
TMR3HLD 0108
Timer3 Holding Register (for 32-bit timer operations only)
Timer3 Register
TMR3
PR2
010A
010C
010E
0110
0112
0114
Period Register 2
PR3
Period Register 3
T2CON
T3CON
TMR4
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
Timer4 Register
TMR5HLD 0116
Timer5 Holding Register (for 32-bit timer operations only)
Timer5 Register
TMR5
PR4
0118
011A
011C
011E
0120
Period Register 4
PR5
Period Register 5
T4CON
T5CON
Legend:
TON
TON
—
—
TSIDL
TSIDL
—
—
—
—
—
—
—
—
—
—
—
—
TGATE
TGATE
TCKPS<1:0>
TCKPS<1:0>
T32
—
—
—
TCS
TCS
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-6:
INPUT CAPTURE REGISTER MAP
SFR
Name
SFR
Addr
All
Resets
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
IC1BUF
IC1CON
IC2BUF
IC2CON
IC7BUF
IC7CON
IC8BUF
IC8CON
Legend:
0140
0142
0144
0146
0158
015A
015C
015E
Input 1 Capture Register
ICTMR
Input 2 Capture Register
ICTMR
Input 7 Capture Register
ICTMR
Input 8Capture Register
ICTMR
xxxx
0000
xxxx
0000
xxxx
0000
xxxx
0000
—
—
—
—
—
—
—
—
ICSIDL
ICSIDL
ICSIDL
ICSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ICI<1:0>
ICOV
ICOV
ICOV
ICOV
ICBNE
ICBNE
ICBNE
ICBNE
ICM<2:0>
ICM<2:0>
ICM<2:0>
ICM<2:0>
—
ICI<1:0>
ICI<1:0>
ICI<1:0>
—
—
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-7:
OUTPUT COMPARE REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
OC1RS
OC1R
0180
0182
0184
0186
0188
018A
018C
018E
0190
0192
0194
0196
Output Compare 1 Secondary Register
Output Compare 1 Register
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
xxxx
xxxx
0000
OC1CON
OC2RS
OC2R
—
—
—
—
—
—
—
—
OCSIDL
OCSIDL
OCSIDL
OCSIDL
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
Output Compare 2 Secondary Register
Output Compare 2 Register
OC2CON
OC3RS
OC3R
—
—
—
Output Compare 3 Secondary Register
Output Compare 3 Register
OC3CON
OC4RS
OC4R
—
—
—
Output Compare 4 Secondary Register
Output Compare 4 Register
OC4CON
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-8:
I2C1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
0200
0202
0204
0206
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Receive Register
Transmit Register
0000
00FF
0000
1000
0000
0000
0000
—
—
—
—
Baud Rate Generator Register
I2CEN
I2CSIDL SCLREL
IPMIEN
—
A10M
BCL
—
DISSLW
GCSTAT
SMEN
GCEN
STREN
I2COV
ACKDT
D_A
ACKEN
P
RCEN
S
PEN
R_W
RSEN
RBF
SEN
TBF
0208 ACKSTAT TRSTAT
—
—
—
—
—
—
ADD10
IWCOL
020A
020C
—
—
—
—
—
Address Register
—
—
Address Mask Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-9:
UART1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U1MODE
U1STA
0220
0222
0224
0226
0228
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UEN0
TRMT
UTX8
URX8
WAKE
LPBACK
ABAUD URXINV
ADDEN RIDLE
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN UTXBF
URXISEL<1:0>
FERR
OERR
URXDA
U1TXREG
U1RXREG
U1BRG
—
—
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Received Register
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-10: UART2 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
U2MODE
U2STA
0230
0232
0234
0236
0238
UARTEN
—
USIDL
IREN
—
RTSMD
—
UEN1
UEN0
TRMT
UTX8
URX8
WAKE
LPBACK
ABAUD URXINV
BRGH
PERR
PDSEL<1:0>
STSEL
0000
0110
xxxx
0000
0000
UTXISEL1 UTXINV UTXISEL0
UTXBRK UTXEN UTXBF
URXISEL<1:0>
ADDEN
RIDLE
FERR
OERR
URXDA
U2TXREG
U2RXREG
U2BRG
—
—
—
—
—
—
—
—
—
—
—
—
—
UART Transmit Register
UART Receive Register
—
Baud Rate Generator Prescaler
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-11: SPI1 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI1STAT
SPI1CON1
SPI1CON2
SPI1BUF
Legend:
0240
0242
0244
0248
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI1 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-12: SPI2 REGISTER MAP
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SPI2STAT
SPI2CON1
SPI2CON2
SPI2BUF
Legend:
0260
0262
0264
0268
SPIEN
—
—
—
SPISIDL
—
—
—
—
—
SMP
—
—
CKE
—
—
SSEN
—
SPIROV
CKP
—
MSTEN
—
—
—
SPRE<2:0>
—
—
SPITBF
SPIRBF
0000
0000
0000
0000
DISSCK DISSDO MODE16
PPRE<1:0>
FRMEN
SPIFSD
FRMPOL
—
—
—
—
—
—
FRMDLY
—
SPI2 Transmit and Receive Buffer Register
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-13: ADC1 REGISTER MAP FOR dsPIC33FJ64GP202/802, dsPIC33FJ128GP202/802 AND dsPIC33FJ32GP302
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC1BUF0
AD1CON1
AD1CON2
AD1CON3
AD1CHS123
AD1CHS0
AD1PCFGL
AD1CSSL
AD1CON4
Legend:
0300
0320
0322
0324
0326
ADC Data Buffer 0
FORM<1:0>
CHPS<1:0>
xxxx
0000
0000
0000
ADON
—
ADSIDL ADDMABM
—
—
AD12B
CSCNA
SSRC<2:0>
—
—
SIMSAM
ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
—
BUFS
SMPI<3:0>
ADCS<7:0>
ADRC
—
—
—
—
—
—
—
—
SAMC<4:0>
—
—
—
—
—
—
—
CH123NB<1:0>
CH0SB<4:0>
PCFG11 PCFG10 PCFG9
CH123SB
—
CH0NA
—
—
—
—
—
—
—
—
—
—
CH123NA<1:0>
CH0SA<4:0>
PCFG2 PCFG1
CH123SA 0000
0328 CH0NB
0000
032C
0330
0332
—
—
—
PCFG12
CSS12
—
—
—
—
PCFG5
CSS5
—
PCFG4
CSS4
—
PCFG3
CSS3
—
PCFG0
CSS0
0000
0000
0000
CSS11
—
CSS10
—
CSS9
—
—
CSS2
CSS1
—
DMABL<2:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-14: ADC1 REGISTER MAP FOR dsPIC33FJ64GP204/804, dsPIC33FJ128GP204/804 AND dsPIC33FJ32GP304
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ADC1BUF0
AD1CON1
AD1CON2
AD1CON3
0300
0320
0322
0324
ADC Data Buffer 0
FORM<1:0>
CHPS<1:0>
xxxx
0000
0000
0000
ADON
—
ADSIDL ADDMABM
—
—
AD12B
CSCNA
SSRC<2:0>
—
—
SIMSAM
ASAM
SAMP
BUFM
DONE
ALTS
VCFG<2:0>
—
BUFS
SMPI<3:0>
ADCS<7:0>
ADRC
—
—
—
—
—
—
—
—
SAMC<4:0>
AD1CHS123 0326
—
—
—
—
—
—
—
CH123NB<1:0>
CH0SB<4:0>
PCFG11 PCFG10 PCFG9
CH123SB
—
—
—
—
—
—
—
CH123NA<1:0>
CH123SA 0000
AD1CHS0
AD1PCFGL
AD1CSSL
AD1CON4
Legend:
0328 CH0NB
CH0NA
PCFG7
CSS7
—
CH0SA<4:0>
PCFG2 PCFG1
0000
032C
0330
0332
—
—
—
PCFG12
CSS12
—
PCFG8
CSS8
—
PCFG6
CSS6
—
PCFG5
CSS5
—
PCFG4
CSS4
—
PCFG3
CSS3
—
PCFG0
CSS0
0000
0000
0000
CSS11
—
CSS10
—
CSS9
—
CSS2
CSS1
DMABL<2:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-15: DAC1 REGISTER MAP FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804
SFR
Addr
All
Resets
SFR Name
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DAC1CON
DAC1STAT
DAC1DFLT
DAC1RDAT
DAC1LDAT
Legend:
03F0 DACEN
—
—
DACSIDL AMPON
LMVOEN
—
—
—
—
FORM
—
DACFDIV<6:0>
—
0000
0000
0000
0000
0000
03F2
03F4
03F6
03F8
LOEN
—
LITYPE
LFULL
LEMPTY
ROEN
—
RMVOEN
—
RITYPE
RFULL REMPTY
DAC1DFLT<15:0>
DAC1RDAT<15:0>
DAC1LDAT<15:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-16: DMA REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA0CON 0380
CHEN
SIZE
—
DIR
—
HALF
—
NULLW
—
—
—
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
DMA0REQ 0382 FORCE
IRQSEL<6:0>
DMA0STA
DMA0STB
0384
0386
STA<15:0>
STB<15:0>
PAD<15:0>
DMA0PAD 0388
DMA0CNT 038A
DMA1CON 038C
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
—
—
—
—
—
AMODE<1:0>
—
—
—
—
—
—
MODE<1:0>
MODE<1:0>
MODE<1:0>
MODE<1:0>
MODE<1:0>
DMA1REQ 038E FORCE
IRQSEL<6:0>
DMA1STA
DMA1STB
0390
0392
STA<15:0>
STB<15:0>
PAD<15:0>
DMA1PAD 0394
DMA1CNT 0396
DMA2CON 0398
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
AMODE<1:0>
—
DMA2REQ 039A FORCE
DMA2STA 039C
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA2STB 039E
DMA2PAD 03A0
DMA2CNT 03A2
DMA3CON 03A4
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
AMODE<1:0>
—
DMA3REQ 03A6 FORCE
DMA3STA 03A8
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA3STB 03AA
DMA3PAD 03AC
DMA3CNT 03AE
DMA4CON 03B0
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
AMODE<1:0>
—
DMA4REQ 03B2 FORCE
DMA4STA 03B4
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA4STB 03B6
DMA4PAD 03B8
DMA4CNT 03BA
DMA5CON 03BC
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
AMODE<1:0>
—
DMA5REQ 03BE FORCE
DMA5STA 03C0
DMA5STB 03C2
Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
IRQSEL<6:0>
STA<15:0>
STB<15:0>
TABLE 4-16: DMA REGISTER MAP (CONTINUED)
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
DMA5PAD 03C4
DMA5CNT 03C6
DMA6CON 03C8
PAD<15:0>
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
DMA6REQ 03CA FORCE
DMA6STA 03CC
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA6STB 03CE
DMA6PAD 03D0
DMA6CNT 03D2
DMA7CON 03D4
—
—
SIZE
—
—
DIR
—
—
HALF
—
—
NULLW
—
—
—
—
CNT<9:0>
CHEN
—
—
—
—
—
—
—
AMODE<1:0>
—
—
MODE<1:0>
DMA7REQ 03D6 FORCE
DMA7STA 03D8
IRQSEL<6:0>
STA<15:0>
STB<15:0>
PAD<15:0>
DMA7STB 03DA
DMA7PAD 03DC
DMA7CNT 03DE
—
—
—
—
—
—
CNT<9:0>
DMACS0
DMACS1
DSADR
03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 XWCOL7 XWCOL6 XWCOL5 XWCOL4 XWCOL3 XWCOL2 XWCOL1 XWCOL0 0000
03E2
03E4
—
—
—
—
LSTCH<3:0>
PPST7
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
0000
0000
DSADR<15:0>
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-17: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0OR 1 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1CTRL1
C1CTRL2
C1VEC
0400
0402
0404
0406
0408
040A
040C
040E
0410
0412
—
—
—
—
CSIDL
—
ABAT
—
—
—
REQOP<2:0>
—
OPMODE<2:0>
—
—
CANCAP
—
—
WIN
0480
0000
0000
0000
0000
0000
0000
0000
0000
0000
FFFF
0000
0000
—
—
—
—
—
—
—
—
DNCNT<4:0>
ICODE<6:0>
FSA<4:0>
FNRB<5:0>
FIFOIF RBOVIF
FIFOIE RBOVIE
—
—
FILHIT<4:0>
—
C1FCTRL
C1FIFO
C1INTF
C1INTE
C1EC
DMABS<2:0>
—
—
—
—
—
—
—
—
—
—
—
FBP<5:0>
—
—
TXBO
—
TXBP
—
RXBP
—
TXWAR RXWAR EWARN
IVRIF
IVRIE
WAKIF
WAKIE
ERRIF
ERRIE
—
—
RBIF
RBIE
TBIF
TBIE
—
—
—
TERRCNT<7:0>
RERRCNT<7:0>
BRP<5:0>
C1CFG1
C1CFG2
C1FEN1
—
—
—
—
—
—
—
—
—
—
—
—
SJW<1:0>
WAKFIL
SEG2PH<2:0>
SEG2PHTS
FLTEN7
SAM
FLTEN6 FLTEN5 FLTEN4
SEG1PH<2:0>
FLTEN3
F1MSK<1:0>
F9MSK<1:0>
PRSEG<2:0>
0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 FLTEN9 FLTEN8
FLTEN2 FLTEN1 FLTEN0
C1FMSKSEL1 0418
C1FMSKSEL2 041A
F7MSK<1:0>
F15MSK<1:0>
F6MSK<1:0>
F14MSK<1:0>
F5MSK<1:0>
F13MSK<1:0>
F4MSK<1:0>
F12MSK<1:0>
F3MSK<1:0>
F11MSK<1:0>
F2MSK<1:0>
F10MSK<1:0>
F0MSK<1:0>
F8MSK<1:0>
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-18: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 (FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804)
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400-
041E
See definition when WIN = x
C1RXFUL1
C1RXFUL2
0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0
0000
0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0000
C1RXOVF1 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
C1RXOVF2 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C1TR01CON 0430
C1TR23CON 0432
C1TR45CON 0434
C1TR67CON 0436
TXEN1
TXEN3
TXEN5
TXEN7
TXABT1 TXLARB1 TXERR1 TXREQ1 RTREN1
TXABT3 TXLARB3 TXERR3 TXREQ3 RTREN3
TXABT5 TXLARB5 TXERR5 TXREQ5 RTREN5
TXABT7 TXLARB7 TXERR7 TXREQ7 RTREN7
TX1PRI<1:0>
TX3PRI<1:0>
TX5PRI<1:0>
TX7PRI<1:0>
TXEN0
TXEN2
TXEN4
TXEN6
TXABT0 TXLARB0 TXERR0 TXREQ0 RTREN0
TXABT2 TXLARB2 TXERR2 TXREQ2 RTREN2
TXABT4 TXLARB4 TXERR4 TXREQ4 RTREN4
TXABT6 TXLARB6 TXERR6 TXREQ6 RTREN6
TX0PRI<1:0>
TX2PRI<1:0>
TX4PRI<1:0>
TX6PRI<1:0>
0000
0000
0000
0000
xxxx
xxxx
C1RXD
C1TXD
Legend:
0440
0442
Received Data Word
Transmit Data Word
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
See definition when WIN = x
F1BP<3:0>
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0400-
041E
C1BUFPNT1
C1BUFPNT2
C1BUFPNT3
C1BUFPNT4
C1RXM0SID
C1RXM0EID
C1RXM1SID
C1RXM1EID
C1RXM2SID
C1RXM2EID
C1RXF0SID
C1RXF0EID
C1RXF1SID
C1RXF1EID
C1RXF2SID
C1RXF2EID
C1RXF3SID
C1RXF3EID
C1RXF4SID
C1RXF4EID
C1RXF5SID
C1RXF5EID
C1RXF6SID
C1RXF6EID
C1RXF7SID
C1RXF7EID
C1RXF8SID
C1RXF8EID
C1RXF9SID
C1RXF9EID
C1RXF10SID
C1RXF10EID
C1RXF11SID
Legend:
0420
0422
0424
0426
0430
0432
0434
0436
0438
043A
0440
0442
0444
0446
0448
044A
044C
044E
0450
0452
0454
0456
0458
045A
045C
045E
0460
0462
0464
0466
0468
046A
046C
F3BP<3:0>
F2BP<3:0>
F0BP<3:0>
0000
0000
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
F7BP<3:0>
F11BP<3:0>
F15BP<3:0>
F6BP<3:0>
F10BP<3:0>
F14BP<3:0>
F5BP<3:0>
F9BP<3:0>
F13BP<3:0>
F4BP<3:0>
F8BP<3:0>
F12BP<3:0>
SID<10:3>
SID<2:0>
—
MIDE
MIDE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
EID<17:16>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<7:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
EID<17:16>
EID<7:0>
—
MIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-19: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1(FOR dsPIC33FJ128GP802/804 AND dsPIC33FJ64GP802/804) (CONTINUED)
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
C1RXF11EID
C1RXF12SID
C1RXF12EID
C1RXF13SID
C1RXF13EID
C1RXF14SID
C1RXF14EID
C1RXF15SID
C1RXF15EID
Legend:
046E
0470
0472
0474
0476
0478
047A
047C
047E
EID<15:8>
EID<7:0>
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<10:3>
EID<15:8>
SID<2:0>
SID<2:0>
SID<2:0>
SID<2:0>
—
—
EXIDE
—
—
—
—
EID<17:16>
EID<7:0>
EXIDE
EID<17:16>
EID<17:16>
EID<17:16>
EID<7:0>
—
EXIDE
EID<7:0>
—
EXIDE
EID<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-20: DCI REGISTER MAP
SFR Name
Addr.
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5 Bit 4 Bit 3
Bit 2
Bit 1
Bit 0
Reset State
DCICON1
DCICON2
DCICON3
DCISTAT
TSCON
0280
0282
0284
0286
0288
028C
0290
0292
0294
0296
0298
029A
029C
029E
DCIEN
—
—
—
—
—
DCISIDL
—
—
—
DLOOP CSCKD CSCKE COFSD UNFM CSDOM DJST
—
—
—
—
COFSM1 COFSM0 0000 0000 0000 0000
BLEN1
BLEN0
—
COFSG<3:0>
BCG<11:0>
WS<3:0>
0000 0000 0000 0000
0000 0000 0000 0000
—
—
—
—
—
—
SLOT3
TSE11
SLOT2
TSE10
RSE10
SLOT1
TSE9
SLOT0
TSE8
—
—
—
—
ROV RFUL
TUNF
TSE1
RSE1
TMPTY 0000 0000 0000 0000
TSE15 TSE14
RSE15 RSE14
TSE13
RSE13
TSE12
TSE7
RSE7
TSE6
RSE6
TSE5 TSE4 TSE3 TSE2
RSE5 RSE4 RSE3 RSE2
TSE0
RSE0
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
0000 0000 0000 0000
RSCON
RSE12 RSE11
RSE9
RSE8
RXBUF0
RXBUF1
RXBUF2
RXBUF3
TXBUF0
TXBUF1
TXBUF2
TXBUF3
Legend:
Receive Buffer 0 Data Register
Receive Buffer 1 Data Register
Receive Buffer 2 Data Register
Receive Buffer 3 Data Register
Transmit Buffer 0 Data Register
Transmit Buffer 1 Data Register
Transmit Buffer 2 Data Register
Transmit Buffer 3 Data Register
— = unimplemented, read as ‘0’.
TABLE 4-21: PERIPHERAL PIN SELECT INPUT REGISTER MAP
All
Resets
File Name Addr Bit 15 Bit 14 Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RPINR0
1F00
001F
1F1F
1F1F
1F1F
1F1F
001F
1F1F
1F1F
1F1F
001F
1F1F
001F
1F1F
001F
001F
0680
0682
0686
0688
068E
0694
0696
06A4
06A6
06A8
06AA
06AC
06AE
06B0
06B2
06B4
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
INT1R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RPINR1
—
—
—
—
INT2R<4:0>
T2CKR<4:0>
T4CKR<4:0>
IC1R<4:0>
RPINR3
T3CKR<4:0>
T5CKR<4:0>
IC2R<4:0>
IC8R<4:0>
—
RPINR4
RPINR7
RPINR10
RPINR11
RPINR18
RPINR19
RPINR20
RPINR21
RPINR22
RPINR23
RPINR24
RPINR25
RPINR26(1)
IC7R<4:0>
—
—
—
—
OCFAR<4:0>
U1RXR<4:0>
U2RXR<4:0>
SDI1R<4:0>
SS1R<4:0>
SDI2R<4:0>
SS2R<4:0>
CSDIR<4:0>
COFSR<4:0>
C1RXR<4:0>
U1CTSR<4:0>
U2CTSR<4:0>
SCK1R<4:0>
—
—
—
—
—
—
—
—
—
SCK2R<4:0>
—
CSCKR<4:0>
—
—
—
—
—
—
—
—
—
—
Legend:
Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register is present only for dsPIC33FJ128GP802/804 and dsPIC33FJ64GP802/804
TABLE 4-22: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND
dsPIC33FJ32GP302
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000
0000
0000
0000
0000
0000
0000
0000
RPOR0
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
06C0
06C2
06C4
06C6
06C8
06CA
06CC
06CE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R<4:0>
RP3R<4:0>
RP5R<4:0>
RP7R<4:0>
RP9R<4:0>
RP11R<4:0>
RP13R<4:0>
RP15R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R<4:0>
RP2R<4:0>
RP4R<4:0>
RP6R<4:0>
RP8R<4:0>
RP10R<4:0>
RP12R<4:0>
RP14R<4:0>
RPOR7
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-23: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND
dsPIC33FJ32GP304
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0000
0000
0000
0000
0000
0000
0000
0000
RPOR0
RPOR1
RPOR2
RPOR3
RPOR4
RPOR5
RPOR6
06C0
06C2
06C4
06C6
06C8
06CA
06CC
06CE
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP1R<4:0>
RP3R<4:0>
RP5R<4:0>
RP7R<4:0>
RP9R<4:0>
RP11R<4:0>
RP13R<4:0>
RP15R<4:0>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
RP0R<4:0>
RP2R<4:0>
RP4R<4:0>
RP6R<4:0>
RP8R<4:0>
RP10R<4:0>
RP12R<4:0>
RP14R<4:0>
RPOR7
RPOR8
0000
0000
06D0
06D2
—
—
—
—
—
—
RP17R<4:0>
RP19R<4:0>
—
—
—
—
—
—
RP16R<4:0>
RP18R<4:0>
RPOR9
RPOR10
RPOR11
0000
0000
0000
06D4
06D6
06D8
—
—
—
—
—
—
—
—
—
RP21R<4:0>
RP23R<4:0>
RP25R<4:0>
—
—
—
—
—
—
—
—
—
RP20R<4:0>
RP22R<4:0>
RP24R<4:0>
RPOR12
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-24: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND
dsPIC33FJ32GP302
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMCON
0600
0602
PMPEN
BUSY
—
PSIDL
ADRMUX<1:0>
INCM<1:0>
PTBEEN PTWREN PTRDEN
CSF1
CSF0
ALP
—
CS1P
BEP
WRSP
RDSP
0000
0000
0000
0000
0000
0000
0000
0000
0000
PMMODE
PMADDR
PMDOUT1
PMDOUT2
PMDIN1
IRQM<1:0>
MODE16
MODE<1:0>
WAITB<1:0>
ADDR<13:0>
WAITM<3:0>
WAITE<1:0>
ADDR15
CS1
0604
Parallel Port Data Out Register 1 (Buffers 0 and 1)
Parallel Port Data Out Register 2 (Buffers 2 and 3)
Parallel Port Data In Register 1 (Buffers 0 and 1)
Parallel Port Data In Register 2 (Buffers 2 and 3)
0606
0608
060A
060C
060E
PMPDIN2
PMAEN
—
PTEN14
IBOV
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PTEN<1:0>
PMSTAT
Legend:
IBF
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
OB3E
OB2E
OB1E
OB0E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-25: PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND
dsPIC33FJ32GP304
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PMCON
0600
0602
PMPEN
BUSY
—
PSIDL
ADRMUX<1:0>
INCM<1:0>
PTBEEN PTWREN PTRDEN
MODE16 MODE<1:0>
CSF1
CSF0
ALP
—
CS1P
BEP
WRSP
RDSP
0000
0000
0000
0000
0000
0000
0000
0000
0000
PMMODE
PMADDR
PMDOUT1
PMDOUT2
PMDIN1
IRQM<1:0>
WAITB<1:0>
ADDR<13:0>
WAITM<3:0>
WAITE<1:0>
ADDR15
CS1
0604
Parallel Port Data Out Register 1 (Buffers 0 and 1)
Parallel Port Data Out Register 2 (Buffers 2 and 3)
Parallel Port Data In Register 1 (Buffers 0 and 1)
Parallel Port Data In Register 2 (Buffers 2 and 3)
0606
0608
060A
060C
060E
PMPDIN2
PMAEN
—
PTEN14
IBOV
—
—
—
—
PTEN<10:0>
—
PMSTAT
Legend:
IBF
—
IB3F
IB2F
IB1F
IB0F
OBE
OBUF
—
OB3E
OB2E
OB1E
OB0E
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-26: REAL-TIME CLOCK AND CALENDAR REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ALRMVAL
ALCFGRPT
RTCVAL
0620
Alarm Value Register Window based on APTR<1:0>
ALRMPTR<1:0>
xxxx
0000
xxxx
0000
0622 ALRMEN CHIME
0624
AMASK<3:0>
ARPT<7:-0>
RTCC Value Register Window based on RTCPTR<1:0>
RCFGCAL
Legend:
0626
RTCEN
—
RTCWREN RTCSYNC HALFSEC RTCOE
RTCPTR<1:0>
CAL<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-27: CRC REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
CRCCON
CRCXOR
CRCDAT
CRCWDAT
Legend:
0640
0642
0644
0646
—
—
CSIDL
VWORD<4:0>
CRCFUL CRCMPT
X<15:0>
—
CRCGO
PLEN<3:0>
0000
0000
0000
0000
CRC Data Input Register
CRC Result Register
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-28: DUAL COMPARATOR REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
C2POS
Bit 1
Bit 0
CMCON
CVRCON
Legend:
0630
0632
CMIDL
—
—
—
C2EVT
—
C1EVT
—
C2EN
—
C1EN
—
C2OUTEN C1OUTEN C2OUT
CVREN
C1OUT
CVROE
C2INV
CVRR
C1INV
C2NEG
C1NEG
C1POS
0000
0000
—
—
CVRSS
CVR<3:0>
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-29: PORTA REGISTER MAP FOR dsPIC33FJ128GP202/802, dsPIC33FJ64GP202/802 AND dsPIC33FJ32GP302
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
02C0
02C2
02C4
02C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1
RA1
TRISA0
RA0
079F
xxxx
xxxx
0000
LATA4
—
LATA3
—
LATA2
—
LATA1
—
LATA0
—
ODCA
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-30: PORTA REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISA
PORTA
LATA
02C0
02C2
02C4
02C6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISA10
RA10
TRISA9
RA9
TRISA8
RA8
TRISA7
RA7
—
—
—
—
—
—
—
—
TRISA4
RA4
TRISA3
RA3
TRISA2
RA2
TRISA1
RA1
TRISA0
RA0
079F
xxxx
xxxx
0000
LATA10
ODCA10
LATA9
ODCA9
LATA8
ODCA8
LATA7
ODCA7
LATA4
—
LATA3
—
LATA2
—
LATA1
—
LATA0
—
ODCA
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-31: PORTB REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
TRISB
PORTB
LATB
02C8
02CA
02CC
02CE
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9
TRISB8
RB8
TRISB7
RB7
TRISB6
RB6
TRISB5
RB5
TRISB4
RB4
TRISB3
RB3
TRISB2
RB2
TRISB1 TRISB0
FFFF
xxxx
xxxx
0000
RB15
LATB15
—
RB14
LATB14
—
RB13
LATB13
—
RB12
LATB12
—
RB11
RB10
RB9
RB1
LATB1
—
RB0
LATB0
—
LATB11
ODCB11
LATB10
ODCB10
LATB9
ODCB9
LATB8
ODCB8
LATB7
ODCB7
LATB6
ODCB6
LATB5
ODCB5
LATB4
—
LATB3
—
LATB2
—
ODCB
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-32: PORTC REGISTER MAP FOR dsPIC33FJ128GP204/804, dsPIC33FJ64GP204/804 AND dsPIC33FJ32GP304
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
TRISC
PORTC
LATC
02D0
02D2
02D4
02D6
TRISC9
RC9
TRISC8 TRISC7 TRISC6
TRISC5
RC5
TRISC4
RC4
TRISC3
RC3
TRISC2
RC2
TRISC1
RC1
TRISC0
RC0
03FF
xxxx
xxxx
0000
RC8
RC7
RC6
LATC9
ODCC9
LATC8
ODCC8
LATC7
ODCC7
LATC6
ODCC6
LATC5
ODCC5
LATC4
ODCC4
LATC3
ODCC3
LATC2
—
LATC1
—
LATC0
—
ODCC
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-33: SYSTEM CONTROL REGISTER MAP
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCON
0740 TRAPR IOPUWR
—
—
—
—
—
CM
NOSC<2:0>
FRCDIV<2:0>
—
VREGS
EXTR
SWR
SWDTEN WDTO
SLEEP
CF
IDLE
—
BOR
POR
xxxx(1)
0300(2)
3040
0742
0744
0746
0748
—
ROI
—
COSC<2:0>
DOZE<2:0>
—
CLKLOCK IOLOCK
PLLPOST<1:0>
LOCK
—
—
PLLDIV<8:0>
—
LPOSCEN OSWEN
OSCCON
CLKDIV
DOZEN
—
PLLPRE<4:0>
—
—
—
—
—
—
—
0030
PLLFBD
OSCTUN
ACLKCON
—
—
—
—
—
—
—
—
TUN<5:0>
—
0000
0000
—
SELACLK
AOSCMD<1:0>
APSTSCLR<2:0>
ASRCSEL
—
—
—
—
074A
Legend:
Note 1:
2:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
RCON register Reset values dependent on type of Reset.
OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset.
TABLE 4-34: SECURITY REGISTER MAP(1)
All
Resets
File Name Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
BSRAM
SSRAM
0750
0752
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
IW_BSR
IR_BSR
IR_SSR
RL_BSR
RL_SSR
0000
0000
IW_ SSR
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1:
This register is not present in devices with 4K RAM and 32K Flash memory.
TABLE 4-35: NVM REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
NVMCON
NVMKEY
Legend:
0760
0766
WR
—
WREN
—
WRERR
—
—
—
—
—
—
—
—
—
—
—
—
ERASE
—
—
NVMOP<3:0>
0000
0000
NVMKEY<7:0>
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 4-36: PMD REGISTER MAP
All
Resets
File Name
Addr
Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
—
—
—
DCIMD
IC1MD
—
PMD1
PMD2
0770
0772
0774
T5MD
IC8MD
—
T4MD
IC7MD
—
T3MD
—
T2MD
—
T1MD
—
I2C1MD
—
U2MD
—
U1MD
—
SPI2MD SPI1MD
C1MD
OC2MD
—
AD1MD
OC1MD
—
0000
0000
0000
IC2MD
—
—
OC4MD OC3MD
PMD3
—
—
—
CMPMD RTCCMD PMPMD CRCMD DAC1MD
—
—
—
Legend:
x= unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.2.7
SOFTWARE STACK
4.2.8
DATA RAM PROTECTION FEATURE
The dsPIC33F product family supports Data RAM
protection features that enable segments of RAM to be
protected when used in conjunction with Boot and
Secure Code Segment Security. BSRAM (Secure RAM
segment for BS) is accessible only from the Boot
Segment Flash code when enabled. SSRAM (Secure
RAM segment for RAM) is accessible only from the
Secure Segment Flash code when enabled. See
Table 4-1 for an overview of the BSRAM and SSRAM
SFRs.
In addition to its use as a working register, the W15
register in the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices is also used as a software Stack Pointer.
The Stack Pointer always points to the first available
free word and grows from lower to higher addresses. It
pre-decrements for stack pops and post-increments for
stack pushes, as shown in Figure 4-6. For a PC push
during any CALLinstruction, the MSb of the PC is zero-
extended before the push, ensuring that the MSb is
always clear.
4.3
Instruction Addressing Modes
Note:
A PC push during exception processing
concatenates the SRL register to the MSb
of the PC prior to the push.
The addressing modes shown in Table 4-37 form the
basis of the addressing modes optimized to support the
specific features of individual instructions. The
addressing modes provided in the MAC class of
instructions differ from those in the other instruction
types.
The Stack Pointer Limit register (SPLIM) associated
with the Stack Pointer sets an upper address boundary
for the stack. SPLIM is uninitialized at Reset. As is the
case for the Stack Pointer, SPLIM<0> is forced to ‘0’
because all stack operations must be word aligned.
4.3.1
FILE REGISTER INSTRUCTIONS
Whenever an EA is generated using W15 as a source
or destination pointer, the resulting address is
compared with the value in SPLIM. If the contents of
the Stack Pointer (W15) and the SPLIM register are
equal and a push operation is performed, a stack error
trap does not occur. The stack error trap occurs on a
subsequent push operation. For example, to cause a
stack error trap when the stack grows beyond address
0x2000 in RAM, initialize the SPLIM with the value
0x1FFE.
Most file register instructions use a 13-bit address field
(f) to directly address data present in the first 8192
bytes of data memory (near data space). Most file
register instructions employ a working register, W0,
which is denoted as WREG in these instructions. The
destination is typically either the same file register or
WREG (with the exception of the MUL instruction),
which writes the result to a register or register pair. The
MOV instruction allows additional flexibility and can
access the entire data space.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0x0800. This prevents the stack from
interfering with the Special Function Register (SFR)
space.
4.3.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form:
Operand 3 = Operand 1 <function> Operand 2
where Operand 1 is always a working register (that is,
the addressing mode can only be register direct), which
is referred to as Wb. Operand 2 can be a W register,
fetched from data memory, or a 5-bit literal. The result
location can be either a W register or a data memory
location. The following addressing modes are
supported by MCU instructions:
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-6:
CALLSTACK FRAME
0x0000
15
0
• Register Direct
• Register Indirect
• Register Indirect Post-Modified
• Register Indirect Pre-Modified
• 5-bit or 10-bit Literal
PC<15:0>
000000000
W15 (before CALL)
PC<22:16>
<Free Word>
W15 (after CALL)
Note:
Not all instructions support all the
addressing modes given above. Individual
instructions can support different subsets
of these addressing modes.
POP : [--W15]
PUSH: [W15++]
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 63
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 4-37: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Addressing Mode
File Register Direct
Description
The address of the file register is specified explicitly.
The contents of a register are accessed directly.
The contents of Wn forms the Effective Address (EA).
Register Direct
Register Indirect
Register Indirect Post-Modified
The contents of Wn forms the EA. Wn is post-modified (incremented
or decremented) by a constant value.
Register Indirect Pre-Modified
Wn is pre-modified (incremented or decremented) by a signed constant value
to form the EA.
Register Indirect with Register Offset The sum of Wn and Wb forms the EA.
(Register Indexed)
Register Indirect with Literal Offset
The sum of Wn and a literal forms the EA.
4.3.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
4.3.4
MACINSTRUCTIONS
The dual source operand DSP instructions (CLR, ED,
EDAC, MAC, MPY, MPY.N, MOVSACand MSC), also referred
to as MACinstructions, use a simplified set of addressing
modes to allow the user application to effectively
manipulate the data pointers through register indirect
tables.
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
addressing modes supported by most MCU
instructions, move and accumulator instructions also
support Register Indirect with Register Offset
Addressing mode, also referred to as Register Indexed
mode.
The two-source operand prefetch registers must be
members of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 are always directed to the X RAGU,
and W10 and W11 are always directed to the Y AGU.
The effective addresses generated (before and after
modification) must, therefore, be valid addresses within
X data space for W8 and W9 and Y data space for W10
and W11.
Note:
For the MOV instructions, the addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (Register Offset)
field is shared by both source and
destination (but typically only used by
one).
Note:
Register Indirect with Register Offset
Addressing mode is available only for W9
(in X space) and W11 (in Y space).
In summary, the following addressing modes are
supported by move and accumulator instructions:
In summary, the following addressing modes are
• Register Direct
supported by the MACclass of instructions:
• Register Indirect
• Register Indirect
• Register Indirect Post-modified
• Register Indirect Pre-modified
• Register Indirect with Register Offset (Indexed)
• Register Indirect with Literal Offset
• 8-bit Literal
• Register Indirect Post-Modified by 2
• Register Indirect Post-Modified by 4
• Register Indirect Post-Modified by 6
• Register Indirect with Register Offset (Indexed)
4.3.5
OTHER INSTRUCTIONS
• 16-bit Literal
Besides the addressing modes outlined previously, some
instructions use literal constants of various sizes. For
example, BRA(branch) instructions use 16-bit signed lit-
erals to specify the branch destination directly, whereas
the DISIinstruction uses a 14-bit unsigned literal field. In
some instructions, such as ADD Acc, the source of an
operand or result is implied by the opcode itself. Certain
operations, such as NOP, do not have any operands.
Note:
Not all instructions support all the address-
ing modes given above. Individual instruc-
tions may support different subsets of
these addressing modes.
DS70292D-page 64
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The length of a circular buffer is not directly specified. It
4.4
Modulo Addressing
is determined by the difference between the
corresponding start and end addresses. The maximum
possible length of the circular buffer is 32K words
(64 Kbytes).
Modulo Addressing mode is a method of providing an
automated means to support circular data buffers using
hardware. The objective is to remove the need for
software to perform data address boundary checks
when executing tightly looped code, as is typical in
many DSP algorithms.
4.4.2
W ADDRESS REGISTER
SELECTION
Modulo Addressing can operate in either data or program
space (since the data pointer mechanism is essentially
the same for both). One circular buffer can be supported
in each of the X (which also provides the pointers into
program space) and Y data spaces. Modulo Addressing
can operate on any W register pointer. However, it is not
advisable to use W14 or W15 for Modulo Addressing
since these two registers are used as the Stack Frame
Pointer and Stack Pointer, respectively.
The Modulo and Bit-Reversed Addressing Control
register, MODCON<15:0>, contains enable flags as well
as a W register field to specify the W Address registers.
The XWM and YWM fields select the registers that
operate with Modulo Addressing:
• If XWM = 15, X RAGU and X WAGU Modulo
Addressing is disabled.
• If YWM = 15, Y AGU Modulo Addressing is
disabled.
In general, any particular circular buffer can be config-
ured to operate in only one direction as there are
certain restrictions on the buffer start address (for incre-
menting buffers), or end address (for decrementing
buffers), based upon the direction of the buffer.
The X Address Space Pointer W register (XWM), to
which Modulo Addressing is to be applied, is stored in
MODCON<3:0> (see Table 4-1). Modulo Addressing is
enabled for X data space when XWM is set to any value
other than ‘15’ and the XMODEN bit is set at
MODCON<15>.
The only exception to the usage restrictions is for
buffers that have a power-of-two length. As these
buffers satisfy the start and end address criteria, they
can operate in a bidirectional mode (that is, address
boundary checks are performed on both the lower and
upper address boundaries).
The Y Address Space Pointer W register (YWM) to
which Modulo Addressing is to be applied is stored in
MODCON<7:4>. Modulo Addressing is enabled for Y
data space when YWM is set to any value other than
‘15’ and the YMODEN bit is set at MODCON<14>.
4.4.1
START AND END ADDRESS
The Modulo Addressing scheme requires that a
starting and ending address be specified and loaded
into the 16-bit Modulo Buffer Address registers:
XMODSRT, XMODEND, YMODSRT and YMODEND
(see Table 4-1).
Note:
Y space Modulo Addressing EA calcula-
tions assume word-sized data (LSb of
every EA is always clear).
FIGURE 4-7:
MODULO ADDRESSING OPERATION EXAMPLE
MOV
MOV
MOV
MOV
MOV
MOV
#0x1100, W0
Byte
Address
W0, XMODSRT
#0x1163, W0
W0, MODEND
#0x8001, W0
W0, MODCON
;set modulo start address
;set modulo end address
;enable W1, X AGU for modulo
;W0 holds buffer fill value
;point W1 to buffer
0x1100
MOV
MOV
#0x0000, W0
#0x1110, W1
DO
MOV
AGAIN, #0x31
W0, [W1++]
;fill the 50 buffer locations
;fill the next location
0x1163
AGAIN: INC W0, W0
;increment the fill value
Start Addr = 0x1100
End Addr = 0x1163
Length = 0x0032 words
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 65
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point,’ which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
4.4.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. Address boundaries check for addresses
equal to:
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
• The upper boundary addresses for incrementing
buffers
• The lower boundary addresses for decrementing
buffers
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or Post-
Increment Addressing and word-sized data writes. It
does not function for any other addressing mode or for
byte-sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB), and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
It is important to realize that the address boundaries
check for addresses less than or greater than the upper
(for incrementing buffers) and lower (for decrementing
buffers) boundary addresses (not just equal to).
Address changes can, therefore, jump beyond
boundaries and still be adjusted correctly.
Note:
The modulo corrected effective address is
written back to the register only when Pre-
Modify or Post-Modify Addressing mode is
used to compute the effective address.
When an address offset (such as [W7 +
W2]) is used, Modulo Address correction
is performed but the contents of the regis-
ter remain unchanged.
Note:
Modulo Addressing and Bit-Reversed
Addressing should not be enabled
together. If an application attempts to do so,
Bit-Reversed Addressing assumes priority
when active for the X WAGU and X WAGU,
Modulo Addressing is disabled. However,
Modulo Addressing continues to function in
the X RAGU.
4.5
Bit-Reversed Addressing
Bit-Reversed Addressing mode is intended to simplify
data reordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed.
The address source and destination are kept in normal
order. Thus, the only operand requiring reversal is the
modifier.
4.5.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing)
• The BREN bit is set in the XBREV register
• The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment
If the length of a bit-reversed buffer is M = 2N bytes,
the last ‘N’ bits of the data buffer start address must
be zeros.
DS70292D-page 66
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 4-8:
BIT-REVERSED ADDRESS EXAMPLE
Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1
0
Bit Locations Swapped Left-to-Right
Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4
0
Bit-Reversed Address
Pivot Point
XB = 0x0008 for a 16-Word Bit-Reversed Buffer
TABLE 4-38: BIT-REVERSED ADDRESS SEQUENCE (16-ENTRY)
Normal Address Bit-Reversed Address
A3
A2
A1
A0
Decimal
A3
A2
A1
A0
Decimal
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
8
2
4
3
12
2
4
5
10
6
6
7
14
1
8
9
9
10
11
12
13
14
15
5
13
3
11
7
15
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 67
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4.6.1
ADDRESSING PROGRAM SPACE
4.6
Interfacing Program and Data
Memory Spaces
Since the address ranges for the data and program
spaces are 16 and 24 bits, respectively, a method is
needed to create a 23-bit or 24-bit program address
from 16-bit data registers. The solution depends on the
interface method to be used.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 architecture uses
a 24-bit-wide program space and a 16-bit-wide data
space. The architecture is also a modified Harvard
scheme, meaning that data can also be present in the
program space. To use this data successfully, it must
be accessed in a way that preserves the alignment of
information in both spaces.
For table operations, the 8-bit Table Page register
(TBLPAG) is used to define a 32K word region within
the program space. This is concatenated with a 16-bit
EA to arrive at a full 24-bit program space address. In
this format, the Most Significant bit of TBLPAG is used
to determine if the operation occurs in the user memory
(TBLPAG<7> = 0) or the configuration memory
(TBLPAG<7> = 1).
Aside
from
normal
execution,
the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 architecture provides
two methods by which program space can be
accessed during operation:
For remapping operations, the 8-bit Program Space
Visibility register (PSVPAG) is used to define a
16K word page in the program space. When the Most
Significant bit of the EA is ‘1’, PSVPAG is concatenated
with the lower 15 bits of the EA to form a 23-bit program
space address. Unlike table operations, this limits
remapping operations strictly to the user memory area.
• Using table instructions to access individual bytes
or words anywhere in the program space
• Remapping a portion of the program space into
the data space (Program Space Visibility)
Table instructions allow an application to read or write
to small areas of the program memory. This capability
makes the method ideal for accessing data tables that
need to be updated periodically. It also allows access
to all bytes of the program word. The remapping
method allows an application to access a large block of
data on a read-only basis, which is ideal for look-ups
from a large table of static data. The application can
only access the least significant word of the program
word.
Table 4-39 and Figure 4-9 show how the program EA is
created for table operations and remapping accesses
from the data EA. Here, P<23:0> refers to a program
space word, and D<15:0> refers to a data space word.
TABLE 4-39: PROGRAM SPACE ADDRESS CONSTRUCTION
Program Space Address
Access
Space
Access Type
<23>
<22:16>
<15>
<14:1>
<0>
Instruction Access
(Code Execution)
User
User
0
PC<22:1>
0
0xx xxxx xxxx xxxx xxxx xxx0
TBLRD/TBLWT
(Byte/Word Read/Write)
TBLPAG<7:0>
0xxx xxxx
Data EA<15:0>
xxxx xxxx xxxx xxxx
Data EA<15:0>
Configuration
TBLPAG<7:0>
1xxx xxxx
xxxx xxxx xxxx xxxx
Program Space Visibility User
(Block Remap/Read)
0
0
PSVPAG<7:0>
xxxx xxxx
Data EA<14:0>(1)
xxx xxxx xxxx xxxx
Note 1: Data EA<15> is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of
the address is PSVPAG<0>.
DS70292D-page 68
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 4-9:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
Program Counter
23 bits
0
0
1/0
EA
Table Operations(2)
1/0
TBLPAG
8 bits
16 bits
24 bits
Select
1
0
EA
Program Space Visibility(1)
(Remapping)
0
PSVPAG
8 bits
15 bits
23 bits
Byte Select
User/Configuration
Space Select
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain
word alignment of data in the program and data spaces.
2: Table operations are not required to be word aligned. Table read operations are permitted
in the configuration memory space.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 69
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
- In Byte mode, either the upper or lower byte
of the lower program word is mapped to the
lower byte of a data address. The upper byte
is selected when Byte Select is ‘1’; the lower
byte is selected when it is ‘0’.
4.6.2
DATA ACCESS FROM PROGRAM
MEMORY USING TABLE
INSTRUCTIONS
The TBLRDL and TBLWTL instructions offer a direct
method of reading or writing the lower word of any
address within the program space without going
through data space. The TBLRDH and TBLWTH
instructions are the only method to read or write the
upper 8 bits of a program space word as data.
• TBLRDH (Table Read High):
- In Word mode, this instruction maps the entire
upper word of a program address (P<23:16>)
to a data address. The ‘phantom’ byte
(D<15:8>), is always ‘0’.
The PC is incremented by two for each successive
24-bit program word. This allows program memory
addresses to directly map to data space addresses.
Program memory can thus be regarded as two 16-bit-
wide word address spaces, residing side by side, each
with the same address range. TBLRDL and TBLWTL
access the space that contains the least significant
data word. TBLRDHand TBLWTHaccess the space that
contains the upper data byte.
- In Byte mode, this instruction maps the upper
or lower byte of the program word to D<7:0>
of the data address, in the TBLRDL instruc-
tion. The data is always ‘0’ when the upper
‘phantom’ byte is selected (Byte Select = 1).
In a similar fashion, two table instructions, TBLWTH
and TBLWTL, are used to write individual bytes or
words to a program space address. The details of
their operation are explained in Section 5.0 “Flash
Program Memory”.
Two table instructions are provided to move byte or
word-sized (16-bit) data to and from program space.
Both function as either byte or word operations.
For all table operations, the area of program memory
space to be accessed is determined by the Table Page
register (TBLPAG). TBLPAG covers the entire program
memory space of the device, including user application
and configuration spaces. When TBLPAG<7> = 0, the
table page is located in the user memory space. When
TBLPAG<7> = 1, the page is located in configuration
space.
• TBLRDL(Table Read Low):
- In Word mode, this instruction maps the
lower word of the program space
location (P<15:0>) to a data address
(D<15:0>).
FIGURE 4-10:
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
TBLPAG
02
23
15
0
0x000000
23
16
8
0
00000000
00000000
00000000
0x020000
0x030000
00000000
‘Phantom’ Byte
TBLRDH.B (Wn<0> = 0)
TBLRDL.B (Wn<0> = 1)
TBLRDL.B (Wn<0> = 0)
TBLRDL.W
The address for the table operation is determined by the data EA
within the page defined by the TBLPAG register.
Only read operations are shown; write operations are also valid in
the user memory area.
0x800000
DS70292D-page 70
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
24-bit program word are used to contain the data. The
upper 8 bits of any program space location used as
data should be programmed with ‘1111 1111’ or
‘0000 0000’ to force a NOP. This prevents possible
issues should the area of code ever be accidentally
executed.
4.6.3
READING DATA FROM PROGRAM
MEMORY USING PROGRAM SPACE
VISIBILITY
The upper 32 Kbytes of data space may optionally be
mapped into any 16K word page of the program space.
This option provides transparent access to stored
constant data from the data space without the need to
use special instructions (such as TBLRDL/H).
Note:
PSV access is temporarily disabled during
table reads/writes.
Program space access through the data space occurs
if the Most Significant bit of the data space EA is ‘1’ and
program space visibility is enabled by setting the PSV
bit in the Core Control register (CORCON<2>). The
location of the program memory space to be mapped
into the data space is determined by the Program
Space Visibility Page register (PSVPAG). This 8-bit
register defines any one of 256 possible pages of
16K words in program space. In effect, PSVPAG
functions as the upper 8 bits of the program memory
address, with the 15 bits of the EA functioning as the
lower bits. By incrementing the PC by 2 for each
program memory word, the lower 15 bits of data space
addresses directly map to the lower 15 bits in the
corresponding program space addresses.
For operations that use PSV and are executed outside
a REPEAT loop, the MOV and MOV.D instructions
require one instruction cycle in addition to the specified
execution time. All other instructions require two
instruction cycles in addition to the specified execution
time.
For operations that use PSV, and are executed inside
a REPEATloop, these instances require two instruction
cycles in addition to the specified execution time of the
instruction:
• Execution in the first iteration
• Execution in the last iteration
• Execution prior to exiting the loop due to an
interrupt
• Execution upon re-entering the loop after an
interrupt is serviced
Data reads to this area add a cycle to the instruction
being executed, since two program memory fetches
are required.
Any other iteration of the REPEAT loop allows the
instruction using PSV to access data, to execute in a
single cycle.
Although each data space address 8000h and higher
maps directly into a corresponding program memory
address (see Figure 4-11), only the lower 16 bits of the
FIGURE 4-11:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON<2> = 1and EA<15> = 1:
Program Space
Data Space
PSVPAG
02
23
15
0
0x000000
0x0000
Data EA<14:0>
0x010000
0x018000
The data in the page
designated by PSV-
PAG is mapped into
the upper half of the
data memory
0x8000
space...
PSV Area
...while the lower 15 bits
of the EA specify an
exact address within
the PSV area. This
corresponds exactly to
the same lower 15 bits
of the actual program
space address.
0xFFFF
0x800000
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 71
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 72
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
programming data (one of the alternate programming
5.0
FLASH PROGRAM MEMORY
pin pairs: PGECx/PGEDx), and three other lines for
power (VDD), ground (VSS) and Master Clear (MCLR).
This allows customers to manufacture boards with
unprogrammed devices and then program the digital
signal controller just before shipping the product. This
also allows the most recent firmware or a custom firm-
ware to be programmed.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 5. Flash Program-
ming” (DS70191) of the “dsPIC33F/
PIC24H Family Reference Manual”,
which is available from the Microchip
website (www.microchip.com).
RTSP is accomplished using TBLRD (table read) and
TBLWT (table write) instructions. With RTSP, the user
application can write program memory data either in
blocks or ‘rows’ of 64 instructions (192 bytes) at a time
or a single program memory word, and erase program
memory in blocks or ‘pages’ of 512 instructions (1536
bytes) at a time.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
5.1
Table Instructions and Flash
Programming
Regardless of the method used, all programming of
Flash memory is done with the table read and table
write instructions. These allow direct read and write
access to the program memory space from the data
memory while the device is in normal operating mode.
The 24-bit target address in the program memory is
formed using bits <7:0> of the TBLPAG register and the
Effective Address (EA) from a W register specified in
the table instruction, as shown in Figure 5-1.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices contain
internal Flash program memory for storing and
executing application code. The memory is readable,
writable and erasable during normal operation over the
entire VDD range.
Flash memory can be programmed in two ways:
• In-Circuit Serial Programming™ (ICSP™)
programming capability
The TBLRDLand the TBLWTLinstructions are used to
read or write to bits <15:0> of program memory.
TBLRDLand TBLWTLcan access program memory in
both Word and Byte modes.
• Run-Time Self-Programming (RTSP)
ICSP allows any of the following devices,
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04, to be serially pro-
grammed while in the end application circuit. This is
done with two lines for programming clock and
The TBLRDHand TBLWTHinstructions are used to read
or write to bits <23:16> of program memory. TBLRDH
and TBLWTHcan also access program memory in Word
or Byte mode.
FIGURE 5-1:
ADDRESSING FOR TABLE REGISTERS
24 bits
Program Counter
Using
Program Counter
0
0
Working Reg EA
Using
Table Instruction
1/0
TBLPAG Reg
8 bits
16 bits
User/Configuration
Space Select
Byte
Select
24-bit EA
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 73
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
5.2
RTSP Operation
5.3
Programming Operations
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 Flash program
memory array is organized into rows of 64 instructions
or 192 bytes. RTSP allows the user application to erase
a page of memory, which consists of eight rows (512
instructions) at a time, and to program one row or one
word at a time. Table 30-12 shows typical erase and
programming times. The 8-row erase pages and single
row write rows are edge-aligned from the beginning of
program memory, on boundaries of 1536 bytes and
192 bytes, respectively.
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode. The processor stalls (waits) until the
programming operation is finished.
The programming time depends on the FRC accuracy
(see Table 30-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4). Use the following
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time and Word
Write Cycle Time parameters (see Table 30-12).
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
EQUATION 5-1:
PROGRAMMING TIME
T
-------------------------------------------------------------------------------------------------------------------------
7.37 MHz FRC Accuracy% FRC Tuning%
For example, if the device is operating at +125°C,
the FRC accuracy will be ±5%. If the TUN<5:0> bits
(see Register 9-4) are set to ‘b111111, the
Minimum Row Write Time is:
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWTinstructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
11064 Cycles
TRW = ---------------------------------------------------------------------------------------------- = 1 . 4 3 5 ms
7.37 MHz 1 + 0.05 1 – 0.00375
and, the Maximum Row Write Time is:
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
11064 Cycles
TRW = --------------------------------------------------------------------------------------------- = 1.586ms
7.37 MHz 1 – 0.05 1 – 0.00375
written.
A
programming cycle is required for
programming each row.
Setting the WR bit (NVMCON<15>) starts the opera-
tion, and the WR bit is automatically cleared when the
operation is finished.
5.4
Control Registers
Two SFRs are used to read and write the program
Flash memory: NVMCON and NVMKEY.
The NVMCON register (Register 5-1) controls which
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY (Register 5-2) is a write-only register that is
used for write protection. To start a programming or
erase sequence, the user application must consecu-
tively write 0x55 and 0xAA to the NVMKEY register.
Refer to Section 5.3 “Programming Operations” for
further details.
DS70292D-page 74
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 5-1:
NVMCON: FLASH MEMORY CONTROL REGISTER
R/SO-0(1)
WR
R/W-0(1)
WREN
R/W-0(1)
WRERR
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
R/W-0(1)
ERASE
U-0
—
U-0
—
R/W-0(1)
R/W-0(1)
R/W-0(1)
R/W-0(1)
NVMOP<3:0>(2)
bit 7
bit 0
Legend:
SO = Settable only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
WR: Write Control bit
1= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is
cleared by hardware once operation is complete
0= Program or erase operation is complete and inactive
bit 14
bit 13
WREN: Write Enable bit
1= Enable Flash program/erase operations
0= Inhibit Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1= An improper program or erase sequence attempt or termination has occurred (bit is set
automatically on any set attempt of the WR bit)
0= The program or erase operation completed normally
bit 12-7
bit 6
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1= Perform the erase operation specified by NVMOP<3:0> on the next WR command
0= Perform the program operation specified by NVMOP<3:0> on the next WR command
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits(2)
If ERASE = 1:
1111= Memory bulk erase operation
1110= Reserved
1101= Erase General Segment
1100= Erase Secure Segment
1011= Reserved
0011= No operation
0010= Memory page erase operation
0001= No operation
0000= Erase a single Configuration register byte
If ERASE = 0:
1111= No operation
1110= Reserved
1101= No operation
1100= No operation
1011= Reserved
0011= Memory word program operation
0010= No operation
0001= Memory row program operation
0000= Program a single Configuration register byte
Note 1: These bits can only be reset on POR.
2: All other combinations of NVMOP<3:0> are unimplemented.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 75
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 5-2:
NVMKEY: NONVOLATILE MEMORY KEY REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
W-0
bit 7
W-0
W-0
W-0
W-0
W-0
W-0
W-0
NVMKEY<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Unimplemented: Read as ‘0’
NVMKEY<7:0>: Key Register (write-only) bits
DS70292D-page 76
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
4. Write the first 64 instructions from data RAM into
the program memory buffers (see Example 5-2).
5.4.1
PROGRAMMING ALGORITHM FOR
FLASH PROGRAM MEMORY
5. Write the program block to Flash memory:
Programmers can program one row of program Flash
memory at a time. To do this, it is necessary to erase
the 8-row erase page that contains the desired row.
The general process is:
a) Set the NVMOP bits to ‘0001’ to configure
for row programming. Clear the ERASE bit
and set the WREN bit.
b) Write 0x55 to NVMKEY.
c) Write 0xAA to NVMKEY.
1. Read eight rows of program memory
(512 instructions) and store in data RAM.
d) Set the WR bit. The programming cycle
begins and the CPU stalls for the duration of
the write cycle. When the write to Flash mem-
ory is done, the WR bit is cleared
automatically.
2. Update the program data in RAM with the
desired new data.
3. Erase the block (see Example 5-1):
a) Set the NVMOP bits (NVMCON<3:0>) to
‘0010’ to configure for block erase. Set the
ERASE (NVMCON<6>) and WREN
(NVMCON<14>) bits.
6. Repeat steps 4 and 5, using the next available
64 instructions from the block in data RAM by
incrementing the value in TBLPAG, until all
512 instructions are written back to Flash memory.
b) Write the starting address of the page to be
erased into the TBLPAG and W registers.
For protection against accidental operations, the write
initiate sequence for NVMKEY must be used to allow
any erase or program operation to proceed. After the
programming command has been executed, the user
application must wait for the programming time until
programming is complete. The two instructions
following the start of the programming sequence
should be NOPs, as shown in Example 5-3.
c) Write 0x55 to NVMKEY.
d) Write 0xAA to NVMKEY.
e) Set the WR bit (NVMCON<15>). The erase
cycle begins and the CPU stalls for the dura-
tion of the erase cycle. When the erase is
done, the WR bit is cleared automatically.
EXAMPLE 5-1:
ERASING A PROGRAM MEMORY PAGE
; Set up NVMCON for block erase operation
MOV
MOV
#0x4042, W0
W0, NVMCON
;
; Initialize NVMCON
; Init pointer to row to be ERASED
MOV
MOV
MOV
#tblpage(PROG_ADDR), W0
W0, TBLPAG
#tbloffset(PROG_ADDR), W0
;
; Initialize PM Page Boundary SFR
; Initialize in-page EA[15:0] pointer
; Set base address of erase block
; Block all interrupts with priority <7
; for next 5 instructions
TBLWTL W0, [W0]
DISI
#5
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the erase
; command is asserted
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 77
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
EXAMPLE 5-2:
LOADING THE WRITE BUFFERS
; Set up NVMCON for row programming operations
MOV
MOV
#0x4001, W0
W0, NVMCON
;
; Initialize NVMCON
; Set up a pointer to the first program memory location to be written
; program memory selected, and writes enabled
MOV
MOV
MOV
#0x0000, W0
W0, TBLPAG
#0x6000, W0
;
; Initialize PM Page Boundary SFR
; An example program memory address
; Perform the TBLWT instructions to write the latches
; 0th_program_word
MOV
MOV
#LOW_WORD_0, W2
#HIGH_BYTE_0, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
; 1st_program_word
MOV
MOV
#LOW_WORD_1, W2
#HIGH_BYTE_1, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
;
2nd_program_word
MOV
MOV
#LOW_WORD_2, W2
#HIGH_BYTE_2, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
•
•
•
; 63rd_program_word
MOV
MOV
#LOW_WORD_31, W2
#HIGH_BYTE_31, W3
;
;
TBLWTL W2, [W0]
TBLWTH W3, [W0++]
; Write PM low word into program latch
; Write PM high byte into program latch
EXAMPLE 5-3:
INITIATING A PROGRAMMING SEQUENCE
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
MOV
MOV
MOV
BSET
NOP
NOP
#0x55, W0
W0, NVMKEY
#0xAA, W1
W1, NVMKEY
NVMCON, #WR
; Write the 55 key
;
; Write the AA key
; Start the erase sequence
; Insert two NOPs after the
; erase command is asserted
DS70292D-page 78
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
• IOPUWR: Illegal Condition Device Reset
6.0
RESETS
- Illegal Opcode Reset
- Uninitialized W Register Reset
- Security Reset
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
A simplified block diagram of the Reset module is
shown in Figure 6-1.
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 8. Reset” (DS70192) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
Any active source of reset will make the SYSRST sig-
nal active. On system Reset, some of the registers
associated with the CPU and peripherals are forced to
a known Reset state and some are unaffected.
Note:
Refer to the specific peripheral section or
Section 3.0 “CPU” of this manual for
register Reset states.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
All types of device Reset sets a corresponding status
bit in the RCON register to indicate the type of Reset
(see Register 6-1).
A POR clears all the bits, except for the POR bit
(RCON<0>), that are set. The user application can set
or clear any bit at any time during code execution. The
RCON bits only serve as status bits. Setting a particular
Reset status bit in software does not cause a device
Reset to occur.
The Reset module combines all reset sources and
controls the device Master Reset Signal, SYSRST. The
following is a list of device Reset sources:
• POR: Power-on Reset
• BOR: Brown-out Reset
The RCON register also has other bits associated with
the Watchdog Timer and device power-saving states.
The function of these bits is discussed in other sections
of this manual.
• MCLR: Master Clear Pin Reset
• SWR: RESETInstruction
• WDTO: Watchdog Timer Reset
• CM: Configuration Mismatch Reset
• TRAPR: Trap Conflict Reset
Note:
The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset is meaningful.
FIGURE 6-1:
RESET SYSTEM BLOCK DIAGRAM
RESETInstruction
Glitch Filter
MCLR
WDT
Module
Sleep or Idle
BOR
Internal
Regulator
SYSRST
VDD
POR
VDD Rise
Detect
Trap Conflict
Illegal Opcode
Uninitialized W Register
Configuration Mismatch
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 79
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1)
R/W-0
TRAPR
bit 15
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
CM
R/W-0
IOPUWR
VREGS
bit 8
R/W-0
EXTR
R/W-0
SWR
R/W-0
SWDTEN(2)
R/W-0
WDTO
R/W-0
R/W-0
IDLE
R/W-1
BOR
R/W-1
POR
SLEEP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
TRAPR: Trap Reset Flag bit
1= A Trap Conflict Reset has occurred
0= A Trap Conflict Reset has not occurred
IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit
1= An illegal opcode detection, an illegal address mode or uninitialized W register used as an
Address Pointer caused a Reset
0= An illegal opcode or uninitialized W Reset has not occurred
bit 13-10
bit 9
Unimplemented: Read as ‘0’
CM: Configuration Mismatch Flag bit
1 = A configuration mismatch Reset has occurred.
0 = A configuration mismatch Reset has NOT occurred
bit 8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
VREGS: Voltage Regulator Standby During Sleep bit
1= Voltage regulator is active during Sleep
0= Voltage regulator goes into Standby mode during Sleep
EXTR: External Reset (MCLR) Pin bit
1= A Master Clear (pin) Reset has occurred
0= A Master Clear (pin) Reset has not occurred
SWR: Software Reset (Instruction) Flag bit
1= A RESETinstruction has been executed
0= A RESETinstruction has not been executed
SWDTEN: Software Enable/Disable of WDT bit(2)
1= WDT is enabled
0= WDT is disabled
WDTO: Watchdog Timer Time-out Flag bit
1= WDT time-out has occurred
0= WDT time-out has not occurred
SLEEP: Wake-up from Sleep Flag bit
1= Device has been in Sleep mode
0= Device has not been in Sleep mode
IDLE: Wake-up from Idle Flag bit
1= Device was in Idle mode
0= Device was not in Idle mode
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
DS70292D-page 80
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 6-1:
RCON: RESET CONTROL REGISTER(1) (CONTINUED)
bit 1
BOR: Brown-out Reset Flag bit
1= A Brown-out Reset has occurred
0= A Brown-out Reset has not occurred
bit 0
POR: Power-on Reset Flag bit
1= A Power-on Reset has occurred
0= A Power-on Reset has not occurred
Note 1: All of the Reset status bits can be set or cleared in software. Setting one of these bits in software does not
cause a device Reset.
2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the
SWDTEN bit setting.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 81
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2. BOR Reset: The on-chip voltage regulator has
6.1
System Reset
a BOR circuit that keeps the device in Reset
until VDD crosses the VBOR threshold and the
delay TBOR has elapsed. The delay TBOR
ensures that the voltage regulator output
becomes stable.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 family of devices
have two types of Reset:
• Cold Reset
• Warm Reset
3. PWRT Timer: The programmable power-up
timer continues to hold the processor in Reset
for a specific period of time (TPWRT) after a
BOR. The delay TPWRT ensures that the system
power supplies have stabilized at the appropri-
ate level for full-speed operation. After the delay
TPWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected
oscillator to start generating clock cycles.
A cold Reset is the result of a Power-on Reset (POR)
or a Brown-out Reset (BOR). On a cold Reset, the
FNOSC configuration bits in the FOSC device
configuration register selects the device clock source.
A warm Reset is the result of all other reset sources,
including the RESET instruction. On warm Reset, the
device will continue to operate from the current clock
source as indicated by the Current Oscillator Selection
(COSC<2:0>) bits in the Oscillator Control
(OSCCON<14:12>) register.
4. Oscillator Delay: The total delay for the clock to
be ready for various clock source selections is
given in Table 6-1. Refer to Section 9.0
The device is kept in a Reset state until the system
power supplies have stabilized at appropriate levels
and the oscillator clock is ready. The sequence in
which this occurs is detailed below and is shown in
Figure 6-2.
“Oscillator
information.
Configuration”
for
more
5. When the oscillator clock is ready, the processor
begins execution from location 0x000000. The
user application programs a GOTOinstruction at
the reset address, which redirects program
execution to the appropriate start-up routine.
1. POR Reset: A POR circuit holds the device in
Reset when the power supply is turned on. The
POR circuit is active until VDD crosses the VPOR
threshold and the delay TPOR has elapsed.
6. The Fail-safe clock monitor (FSCM), if enabled,
begins to monitor the system clock when the
system clock is ready and the delay TFSCM
elapsed.
TABLE 6-1:
OSCILLATOR DELAY
Oscillator
Oscillator Startup
Timer
Oscillator Mode
PLL Lock Time
Total Delay
Startup Delay
FRC, FRCDIV16,
FRCDIVN
TOSCD
—
—
TOSCD
FRCPLL
XT
TOSCD
TOSCD
TOSCD
—
—
TOST
TOST
—
TLOCK
—
TOSCD + TLOCK
TOSCD + TOST
TOSCD + TOST
—
HS
—
EC
—
XTPLL
HSPLL
ECPLL
SOSC
LPRC
TOSCD
TOSCD
—
TOST
TOST
—
TLOCK
TLOCK
TLOCK
—
TOSCD + TOST + TLOCK
TOSCD + TOST + TLOCK
TLOCK
TOSCD
TOSCD
TOST
—
TOSCD + TOST
TOSCD
—
Note 1: TOSCD = Oscillator Start-up Delay (1.1 s max for FRC, 70 s max for LPRC). Crystal Oscillator start-up
times vary with crystal characteristics, load capacitance, etc.
2: TOST = Oscillator Start-up Timer Delay (1024 oscillator clock period). For example, TOST = 102.4 s for a
10 MHz crystal and TOST = 32 ms for a 32 kHz crystal.
3: TLOCK = PLL lock time (1.5 ms nominal), if PLL is enabled.
DS70292D-page 82
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 6-2:
SYSTEM RESET TIMING
VBOR
Vbor
VPOR
VDD
TPOR
1
POR Reset
BOR Reset
SYSRST
TBOR
2
3
TPWRT
4
Oscillator Clock
TLOCK
TOSCD
TOST
6
TFSCM
FSCM
5
Reset
Device Status
Run
Time
Note 1: POR Reset: A POR circuit holds the device in Reset when the power supply is turned on. The POR circuit is
active until VDD crosses the VPOR threshold and the delay TPOR has elapsed.
2: BOR Reset: The on-chip voltage regulator has a BOR circuit that keeps the device in Reset until VDD crosses
the VBOR threshold and the delay TBOR has elapsed. The delay TBOR ensures the voltage regulator output
becomes stable.
3: PWRT Timer: The programmable power-up timer continues to hold the processor in Reset for a specific
period of time (TPWRT) after a BOR. The delay TPWRT ensures that the system power supplies have stabilized
at the appropriate level for full-speed operation. After the delay TPWRT has elapsed, the SYSRST becomes
inactive, which in turn enables the selected oscillator to start generating clock cycles.
4: Oscillator Delay: The total delay for the clock to be ready for various clock source selections are given in
Table 6-1. Refer to Section 9.0 “Oscillator Configuration” for more information.
5: When the oscillator clock is ready, the processor begins execution from location 0x000000. The user
application programs a GOTO instruction at the reset address, which redirects program execution to the
appropriate start-up routine.
6: The Fail-safe clock monitor (FSCM), if enabled, begins to monitor the system clock when the system clock is
ready and the delay TFSCM elapsed.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 83
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 6-2:
OSCILLATOR DELAY
Symbol
Parameter
POR threshold
Value
VPOR
TPOR
VBOR
TBOR
TPWRT
TFSCM
1.8V nominal
POR extension time
30 s maximum
2.5V nominal
BOR threshold
BOR extension time
100 s maximum
Programmable power-up time delay
Fail-Safe Clock Monitor Delay
0-128 ms nominal
900 s maximum
6.2.1
Brown-out Reset (BOR) and
Power-up timer (PWRT)
Note: When the device exits the Reset condi-
tion (begins normal operation), the
device operating parameters (voltage,
frequency, temperature, etc.) must be
within their operating ranges, otherwise
the device may not function correctly.
The user application must ensure that
the delay between the time power is
first applied, and the time SYSRST
becomes inactive, is long enough to get
The on-chip regulator has a Brown-out Reset (BOR)
circuit that resets the device when the VDD is too low
(VDD < VBOR) for proper device operation. The BOR cir-
cuit keeps the device in Reset until VDD crosses VBOR
threshold and the delay TBOR has elapsed. The delay
TBOR ensures the voltage regulator output becomes
stable.
The BOR status (BOR) bit in the Reset Control
(RCON<1>) register is set to indicate the Brown-out
Reset.
all
operating
parameters
within
specification.
The device will not run at full speed after a BOR as the
VDD should rise to acceptable levels for full-speed
operation. The PWRT provides power-up time delay
(TPWRT) to ensure that the system power supplies have
stabilized at the appropriate levels for full-speed
operation before the SYSRST is released.
6.2
Power-on Reset (POR)
A Power-on Reset (POR) circuit ensures the device is
reset from power-on. The POR circuit is active until
VDD crosses the VPOR threshold and the delay TPOR
has elapsed. The delay TPOR ensures the internal
device bias circuits become stable.
The power-up timer delay (TPWRT) is programmed by
The device supply voltage characteristics must meet
the specified starting voltage and rise rate
requirements to generate the POR. Refer to
Section 30.0 “Electrical Characteristics” for details.
the
Power-on
Reset
Timer
Value
Select
(FPWRT<2:0>) bits in the POR Configuration
(FPOR<2:0>) register, which provides eight settings
(from 0 ms to 128 ms). Refer to Section 27.0 “Special
Features” for further details.
The POR status (POR) bit in the Reset Control
(RCON<0>) register is set to indicate the Power-on
Reset.
Figure 6-3 shows the typical brown-out scenarios. The
reset delay (TBOR + TPWRT) is initiated each time VDD
rises above the VBOR trip point
DS70292D-page 84
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 6-3:
BROWN-OUT SITUATIONS
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD
VBOR
TBOR + TPWRT
SYSRST
VDD dips before PWRTexpires
VDD
VBOR
TBOR + TPWRT
SYSRST
The Software Reset (Instruction) Flag (SWR) bit in the
Reset Control (RCON<6>) register is set to indicate
the software Reset.
6.3
External Reset (EXTR)
The external Reset is generated by driving the MCLR
pin low. The MCLR pin is a Schmitt trigger input with an
additional glitch filter. Reset pulses that are longer than
the minimum pulse-width will generate a Reset. Refer
to Section 30.0 “Electrical Characteristics” for
minimum pulse-width specifications. The External
Reset (MCLR) Pin (EXTR) bit in the Reset Control
(RCON) register is set to indicate the MCLR Reset.
6.5
Watchdog Time-out Reset (WDTO)
Whenever a Watchdog time-out occurs, the device will
asynchronously assert SYSRST. The clock source will
remain unchanged. A WDT time-out during Sleep or
Idle mode will wake-up the processor, but will not reset
the processor.
6.3.0.1
EXTERNAL SUPERVISORY CIRCUIT
The Watchdog Timer Time-out Flag (WDTO) bit in the
Reset Control (RCON<4>) register is set to indicate
the Watchdog Reset. Refer to Section 27.4
“Watchdog Timer (WDT)” for more information on
Watchdog Reset.
Many systems have external supervisory circuits that
generate reset signals to Reset multiple devices in the
system. This external Reset signal can be directly con-
nected to the MCLR pin to Reset the device when the
rest of system is Reset.
6.6
Trap Conflict Reset
6.3.0.2
INTERNAL SUPERVISORY CIRCUIT
If a lower-priority hard trap occurs while a higher-prior-
ity trap is being processed, a hard trap conflict Reset
occurs. The hard traps include exceptions of priority
level 13 through level 15, inclusive. The address error
(level 13) and oscillator error (level 14) traps fall into
this category.
When using the internal power supervisory circuit to
Reset the device, the external reset pin (MCLR) should
be tied directly or resistively to VDD. In this case, the
MCLR pin will not be used to generate a Reset. The
external reset pin (MCLR) does not have an internal
pull-up and must not be left unconnected.
The Trap Reset Flag (TRAPR) bit in the Reset Control
(RCON<15>) register is set to indicate the Trap Conflict
Reset. Refer to Section 7.0 “Interrupt Controller” for
more information on trap conflict Resets.
6.4
Software RESETInstruction (SWR)
Whenever the RESET instruction is executed, the
device will assert SYSRST, placing the device in a spe-
cial Reset state. This Reset state will not re-initialize the
clock. The clock source in effect prior to the RESET
instruction will remain. SYSRST is released at the next
instruction cycle, and the reset vector fetch will com-
mence.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 85
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
each program memory section to store the data values.
The upper 8 bits should be programmed with 3Fh,
which is an illegal opcode value.
6.7
Configuration Mismatch Reset
To maintain the integrity of the peripheral pin select
control registers, they are constantly monitored with
shadow registers in hardware. If an unexpected
change in any of the registers occur (such as cell dis-
turbances caused by ESD or other external events), a
configuration mismatch Reset occurs.
6.8.0.2
UNINITIALIZED W REGISTER
RESET
Any attempts to use the uninitialized W register as an
address pointer will Reset the device. The W register
array (with the exception of W15) is cleared during all
resets and is considered uninitialized until written to.
The Configuration Mismatch Flag (CM) bit in the Reset
Control (RCON<9>) register is set to indicate the
configuration mismatch Reset. Refer to Section 11.0
“I/O Ports” for more information on the configuration
mismatch Reset.
6.8.0.3
SECURITY RESET
If a Program Flow Change (PFC) or Vector Flow
Change (VFC) targets a restricted location in a
protected segment (Boot and Secure Segment), that
operation will cause a security Reset.
Note:
The configuration mismatch feature and
associated reset flag is not available on all
devices.
The PFC occurs when the Program Counter is
reloaded as a result of a Call, Jump, Computed Jump,
Return, Return from Subroutine, or other form of
branch instruction.
6.8
Illegal Condition Device Reset
An illegal condition device Reset occurs due to the
following sources:
The VFC occurs when the Program Counter is
reloaded with an Interrupt or Trap vector.
• Illegal Opcode Reset
• Uninitialized W Register Reset
• Security Reset
Refer to Section 27.8 “Code Protection and
CodeGuard™ Security” for more information on
Security Reset.
The Illegal Opcode or Uninitialized W Access Reset
Flag (IOPUWR) bit in the Reset Control (RCON<14>)
register is set to indicate the illegal condition device
Reset.
6.9
Using the RCON Status Bits
The user application can read the Reset Control
(RCON) register after any device Reset to determine
the cause of the reset.
6.8.0.1
ILLEGAL OPCODE RESET
A device Reset is generated if the device attempts to
execute an illegal opcode value that is fetched from
program memory.
Note: The status bits in the RCON register
should be cleared after they are read so
that the next RCON register value after a
device Reset will be meaningful.
The illegal opcode Reset function can prevent the
device from executing program memory sections that
are used to store constant data. To take advantage of
the illegal opcode Reset, use only the lower 16 bits of
Table 6-3 provides a summary of the reset flag bit
operation.
TABLE 6-3:
RESET FLAG BIT OPERATION
Flag Bit
Set by:
Cleared by:
TRAPR (RCON<15>)
IOPWR (RCON<14>)
Trap conflict event
POR,BOR
POR,BOR
Illegal opcode or uninitialized
W register access or Security Reset
CM (RCON<9>)
Configuration Mismatch
MCLR Reset
POR,BOR
POR
EXTR (RCON<7>)
SWR (RCON<6>)
WDTO (RCON<4>)
RESETinstruction
WDT time-out
POR,BOR
PWRSAVinstruction,
CLRWDTinstruction, POR,BOR
SLEEP (RCON<3>)
IDLE (RCON<2>)
BOR (RCON<1>)
POR (RCON<0>)
PWRSAV #SLEEPinstruction
PWRSAV #IDLEinstruction
POR, BOR
POR,BOR
POR,BOR
—
POR
—
Note: All Reset flag bits can be set or cleared by user software.
DS70292D-page 86
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
7.0
INTERRUPT CONTROLLER
and dsPIC33FJ128GPX02/X04 devices implement up
to 53 unique interrupts and five nonmaskable traps.
These are summarized in Table 7-1.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
7.1.1
ALTERNATE INTERRUPT VECTOR
TABLE
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 32. Interrupts (Part
III)” (DS70214) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
The Alternate Interrupt Vector Table (AIVT) is located
after the IVT, as shown in Figure 7-1. Access to the
AIVT is provided by the ALTIVT control bit
(INTCON2<15>). If the ALTIVT bit is set, all interrupt
and exception processes use the alternate vectors
instead of the default vectors. The alternate vectors are
organized in the same manner as the default vectors.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The AIVT supports debugging by providing a means to
switch between an application and
a
support
environment without requiring the interrupt vectors to
be reprogrammed. This feature also enables switching
between applications for evaluation of different
software algorithms at run time. If the AIVT is not
needed, the AIVT should be programmed with the
same addresses used in the IVT.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04,
and
dsPIC33FJ128GPX02/X04
interrupt
controller reduces the numerous peripheral interrupt
request signals to a single interrupt request signal to
the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 CPU.
7.2
Reset Sequence
A device Reset is not a true exception because the
interrupt controller is not involved in the Reset process.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 device clears its
registers in response to a Reset, which forces the PC
to zero. The digital signal controller then begins
program execution at location 0x000000. A GOTO
instruction at the Reset address can redirect program
execution to the appropriate start-up routine.
The interrupt controller has the following features:
• Up to eight processor exceptions and software
traps
• Eight user-selectable priority levels
• Interrupt Vector Table (IVT) with up to 118 vectors
• A unique vector for each interrupt or exception
source
Note: Any unimplemented or unused vector
locations in the IVT and AIVT should be
programmed with the address of a default
interrupt handler routine that contains a
RESETinstruction.
• Fixed priority within a specified user priority level
• Alternate Interrupt Vector Table (AIVT) for debug
support
• Fixed interrupt entry and return latencies
7.1
Interrupt Vector Table
The Interrupt Vector Table (IVT), shown in Figure 7-1,
resides in program memory, starting at location
000004h. The IVT contains 126 vectors consisting of
eight nonmaskable trap vectors plus up to 118 sources
of interrupt. In general, each interrupt source has its
own vector. Each interrupt vector contains a 24-bit-
wide address. The value programmed into each
interrupt vector location is the starting address of the
associated Interrupt Service Routine (ISR).
Interrupt vectors are prioritized in terms of their natural
priority. This priority is linked to their position in the
vector table. Lower addresses generally have a higher
natural priority. For example, the interrupt associated
with vector 0 takes priority over interrupts at any other
vector address.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 87
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 7-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 INTERRUPT VECTOR TABLE
Reset – GOTOInstruction
Reset – GOTOAddress
Reserved
0x000000
0x000002
0x000004
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000014
~
~
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00007C
0x00007E
0x000080
(1)
Interrupt Vector Table (IVT)
~
~
Interrupt Vector 116
Interrupt Vector 117
Reserved
0x0000FC
0x0000FE
0x000100
0x000102
Reserved
Reserved
Oscillator Fail Trap Vector
Address Error Trap Vector
Stack Error Trap Vector
Math Error Trap Vector
DMA Error Trap Vector
Reserved
Reserved
Interrupt Vector 0
Interrupt Vector 1
~
0x000114
~
~
(1)
Alternate Interrupt Vector Table (AIVT)
Interrupt Vector 52
Interrupt Vector 53
Interrupt Vector 54
~
0x00017C
0x00017E
0x000180
~
~
Interrupt Vector 116
Interrupt Vector 117
Start of Code
0x0001FE
0x000200
Note 1: See Table 7-1 for the list of implemented interrupt vectors.
DS70292D-page 88
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 7-1:
INTERRUPT VECTORS
Vector
Number
IVT Address
AIVT Address
Interrupt Source
0
0x000004
0x000006
0x000008
0x00000A
0x00000C
0x00000E
0x000010
0x000012
0x000014
0x000016
0x000018
0x00001A
0x00001C
0x00001E
0x000020
0x000022
0x000024
0x000026
0x000028
0x00002A
0x00002C
0x00002E
0x000030
0x000032
0x000034
0x000036
0x000038
0x00003A
0x00003C
0x00003E
0x000040
0x000042
0x000044
0x000046
0x000048
0x00004A
0x00004C
0x00004E
0x000050
0x000052
0x000054
0x000056
0x000058
0x00005A
0x00005C
0x00005E
0x000060
0x000104
0x000106
0x000108
0x00010A
0x00010C
0x00010E
0x000110
0x000112
0x000114
0x000116
0x000118
0x00011A
0x00011C
0x00011E
0x000120
0x000122
0x000124
0x000126
0x000128
0x00012A
0x00012C
0x00012E
0x000130
0x000132
0x000134
0x000136
0x000138
0x00013A
0x00013C
0x00013E
0x000140
0x000142
0x000144
0x000146
0x000148
0x00014A
0x00014C
0x00014E
0x000150
0x000152
0x000154
0x000156
0x000158
0x00015A
0x00015C
0x00015E
0x000160
Reserved
1
Oscillator Failure
Address Error
Stack Error
Math Error
DMA Error
Reserved
2
3
4
5
6
7
Reserved
8
INT0 – External Interrupt 0
IC1 – Input Compare 1
OC1 – Output Compare 1
T1 – Timer1
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DMA0 – DMA Channel 0
IC2 – Input Capture 2
OC2 – Output Compare 2
T2 – Timer2
T3 – Timer3
SPI1E – SPI1 Error
SPI1 – SPI1 Transfer Done
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC1 – ADC 1
DMA1 – DMA Channel 1
Reserved
SI2C1 – I2C1 Slave Events
MI2C1 – I2C1 Master Events
CM – Comparator Interrupt
CN – Change Notification Interrupt
INT1 – External Interrupt 1
Reserved
IC7 – Input Capture 7
IC8 – Input Capture 8
DMA2 – DMA Channel 2
OC3 – Output Compare 3
OC4 – Output Compare 4
T4 – Timer4
T5 – Timer5
INT2 – External Interrupt 2
U2RX – UART2 Receiver
U2TX – UART2 Transmitter
SPI2E – SPI2 Error
SPI2 – SPI2 Transfer Done
C1RX – ECAN1 RX Data Ready
C1 – ECAN1 Event
DMA3 – DMA Channel 3
Reserved
Reserved
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 89
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 7-1:
INTERRUPT VECTORS (CONTINUED)
Vector
Number
IVT Address
AIVT Address
Interrupt Source
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88-126
0x000062
0x000064
0x000066
0x000068
0x00006A
0x00006C
0x00006E
0x000070
0x000072
0x000074
0x000076
0x000078
0x00007A
0x00007C
0x00007E
0x000080
0x000082
0x000084
0x000086
0x000088
0x00008A
0x00008C
0x00008E
0x000090
0x000092
0x000094
0x000096
0x000098
0x00009A
0x00009C
0x00009E
0x0000A0
0x0000A2
0x0000A4
0x0000A6
0x0000A8
0x0000AA
0x0000AC
0x0000AE
0x0000B0
0x0000B2
0x000162
0x000164
0x000166
0x000168
0x00016A
0x00016C
0x00016E
0x000170
0x000172
0x000174
0x000176
0x000178
0x00017A
0x00017C
0x00017E
0x000180
0x000182
0x000184
0x000186
0x000188
0x00018A
0x00018C
0x00018E
0x000190
0x000192
0x000194
0x000196
0x000198
0x00019A
0x00019C
0x00019E
0x0001A0
0x0001A2
0x0001A4
0x0001A6
0x0001A8
0x0001AA
0x0001AC
0x0001AE
0x0001B0
0x0001B2
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PMP – Parallel Master Port
DMA – DMA Channel 4
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DCIE – DCI Error
DCI – DCI Transfer Done
DMA5 – DMA Channel 5
RTCC – Real Time Clock
Reserved
Reserved
U1E – UART1 Error
U2E – UART2 Error
CRC – CRC Generator Interrupt
DMA6 – DMA Channel 6
DMA7 – DMA Channel 7
C1TX – ECAN1 TX Data Request
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
DAC1R – DAC1 Right Data Request
DAC1L – DAC1 Left Data Request
0x0000B4-0x0000FE 0x0001B4-0x0001FE Reserved
DS70292D-page 90
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
7.3.4
IPCX
7.3
Interrupt Control and Status
Registers
The IPC registers are used to set the interrupt priority
level for each source of interrupt. Each user interrupt
source can be assigned to one of eight priority levels.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices implement a
total of 30 registers for the interrupt controller:
7.3.5
INTTREG
• INTCON1
• INTCON2
• IFSx
The INTTREG register contains the associated
interrupt vector number and the new CPU interrupt
priority level, which are latched into vector number
(VECNUM<6:0>) and Interrupt level (ILR<3:0>) bit
fields in the INTTREG register. The new interrupt
priority level is the priority of the pending interrupt.
• IECx
• IPCx
• INTTREG
The interrupt sources are assigned to the IFSx, IECx
and IPCx registers in the same sequence that they are
listed in Table 7-1. For example, the INT0 (External
Interrupt 0) is shown as having vector number 8 and a
natural order priority of 0. Thus, the INT0IF bit is found
in IFS0<0>, the INT0IE bit in IEC0<0>, and the INT0IP
bits in the first position of IPC0 (IPC0<2:0>).
7.3.1
INTCON1 AND INTCON2
Global interrupt control functions are controlled from
INTCON1 and INTCON2. INTCON1 contains the
Interrupt Nesting Disable (NSTDIS) bit as well as the
control and status flags for the processor trap sources.
The INTCON2 register controls the external interrupt
request signal behavior and the use of the Alternate
Interrupt Vector Table.
7.3.6
STATUS/CONTROL REGISTERS
Although they are not specifically part of the interrupt
control hardware, two of the CPU Control registers
contain bits that control interrupt functionality.
7.3.2
IFSX
The IFS registers maintain all of the interrupt request
flags. Each source of interrupt has a status bit, which is
set by the respective peripherals or external signal and
is cleared via software.
• The CPU STATUS register, SR, contains the
IPL<2:0> bits (SR<7:5>). These bits indicate the
current CPU interrupt priority level. The user
software can change the current CPU priority
level by writing to the IPL bits.
7.3.3
IECX
• The CORCON register contains the IPL3 bit
which, together with IPL<2:0>, also indicates the
current CPU priority level. IPL3 is a read-only bit
so that trap events cannot be masked by the user
software.
The IEC registers maintain all of the interrupt enable
bits. These control bits are used to individually enable
interrupts from the peripherals or external signals.
All Interrupt registers are described in Register 7-1
through Register 7-31 in the following pages.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 91
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-1:
SR: CPU STATUS REGISTER(1)
R-0
OA
R-0
OB
R/C-0
SA
R/C-0
SB
R-0
R/C-0
SAB
R -0
DA
R/W-0
DC
OAB
bit 15
bit 8
R/W-0
R/W-0
IPL<2:0>(2,3)
R/W-0
R-0
RA
R/W-0
N
R/W-0
OV
R/W-0
Z
R/W-0
C
bit 7
bit 0
Legend:
C = Clear only bit
S = Set only bit
‘1’ = Bit is set
R = Readable bit
W = Writable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
-n = Value at POR
x = Bit is unknown
bit 7-5
IPL<2:0>: CPU Interrupt Priority Level Status bits(2)
111= CPU Interrupt Priority Level is 7 (15), user interrupts disabled
110= CPU Interrupt Priority Level is 6 (14)
101= CPU Interrupt Priority Level is 5 (13)
100= CPU Interrupt Priority Level is 4 (12)
011= CPU Interrupt Priority Level is 3 (11)
010= CPU Interrupt Priority Level is 2 (10)
001= CPU Interrupt Priority Level is 1 (9)
000= CPU Interrupt Priority Level is 0 (8)
Note 1: For complete register details, see Register 3-1: “SR: CPU Status Register”.
2: The IPL<2:0> bits are concatenated with the IPL<3> bit (CORCON<3>) to form the CPU Interrupt Priority
Level. The value in parentheses indicates the IPL if IPL<3> = 1. User interrupts are disabled when
IPL<3> = 1.
3: The IPL<2:0> Status bits are read-only when NSTDIS (INTCON1<15>) = 1.
DS70292D-page 92
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-2:
CORCON: CORE CONTROL REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-0
US
R/W-0
EDT
R-0
R-0
R-0
DL<2:0>
bit 15
bit 8
R/W-0
SATA
R/W-0
SATB
R/W-1
R/W-0
R/C-0
IPL3(2)
R/W-0
PSV
R/W-0
RND
R/W-0
IF
SATDW
ACCSAT
bit 7
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘x = Bit is unknown
R = Readable bit
0’ = Bit is cleared
-n = Value at POR
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
bit 3
IPL3: CPU Interrupt Priority Level Status bit 3(2)
1= CPU interrupt priority level is greater than 7
0= CPU interrupt priority level is 7 or less
Note 1: For complete register details, see Register 3-2: “CORCON: Core Control Register”.
2: The IPL3 bit is concatenated with the IPL<2:0> bits (SR<7:5>) to form the CPU Interrupt Priority Level.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 93
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1
R/W-0
NSTDIS
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVAERR
OVBERR
COVAERR COVBERR
OVATE
OVBTE
COVTE
bit 8
R/W-0
SFTACERR
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
DIV0ERR
DMACERR MATHERR ADDRERR
STKERR
OSCFAIL
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
NSTDIS: Interrupt Nesting Disable bit
1= Interrupt nesting is disabled
0= Interrupt nesting is enabled
OVAERR: Accumulator A Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator A
0= Trap was not caused by overflow of Accumulator A
OVBERR: Accumulator B Overflow Trap Flag bit
1= Trap was caused by overflow of Accumulator B
0= Trap was not caused by overflow of Accumulator B
COVAERR: Accumulator A Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator A
0= Trap was not caused by catastrophic overflow of Accumulator A
COVBERR: Accumulator B Catastrophic Overflow Trap Flag bit
1= Trap was caused by catastrophic overflow of Accumulator B
0= Trap was not caused by catastrophic overflow of Accumulator B
OVATE: Accumulator A Overflow Trap Enable bit
1= Trap overflow of Accumulator A
0= Trap disabled
OVBTE: Accumulator B Overflow Trap Enable bit
1= Trap overflow of Accumulator B
0= Trap disabled
bit 8
COVTE: Catastrophic Overflow Trap Enable bit
1= Trap on catastrophic overflow of Accumulator A or B enabled
0= Trap disabled
bit 7
SFTACERR: Shift Accumulator Error Status bit
1= Math error trap was caused by an invalid accumulator shift
0= Math error trap was not caused by an invalid accumulator shift
bit 6
DIV0ERR: Arithmetic Error Status bit
1= Math error trap was caused by a divide by zero
0= Math error trap was not caused by a divide by zero
bit 5
bit 4
DMACERR: DMA Controller Error Status bit
1= DMA controller error trap has occurred
0= DMA controller error trap has not occurred
MATHERR: Arithmetic Error Status bit
1= Math error trap has occurred
0= Math error trap has not occurred
DS70292D-page 94
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-3:
INTCON1: INTERRUPT CONTROL REGISTER 1 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
ADDRERR: Address Error Trap Status bit
1= Address error trap has occurred
0= Address error trap has not occurred
STKERR: Stack Error Trap Status bit
1= Stack error trap has occurred
0= Stack error trap has not occurred
OSCFAIL: Oscillator Failure Trap Status bit
1= Oscillator failure trap has occurred
0= Oscillator failure trap has not occurred
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 95
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-4:
INTCON2: INTERRUPT CONTROL REGISTER 2
R/W-0
ALTIVT
bit 15
R-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DISI
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
INT2EP
INT1EP
INT0EP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ALTIVT: Enable Alternate Interrupt Vector Table bit
1= Use alternate vector table
0= Use standard (default) vector table
DISI: DISIInstruction Status bit
1= DISIinstruction is active
0= DISIinstruction is not active
bit 13-3
bit 2
Unimplemented: Read as ‘0’
INT2EP: External Interrupt 2 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
bit 1
bit 0
INT1EP: External Interrupt 1 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
INT0EP: External Interrupt 0 Edge Detect Polarity Select bit
1= Interrupt on negative edge
0= Interrupt on positive edge
DS70292D-page 96
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IF
R/W-0
R/W-0
R/W-0
SPI1IF
R/W-0
R/W-0
T3IF
DMA1IF
U1TXIF
U1RXIF
SPI1EIF
bit 15
bit 8
R/W-0
T2IF
R/W-0
OC2IF
R/W-0
IC2IF
R/W-0
R/W-0
T1IF
R/W-0
OC1IF
R/W-0
IC1IF
R/W-0
INT0IF
DMA0IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IF: DMA Channel 1 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IF: ADC1 Conversion Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1TXIF: UART1 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1RXIF: UART1 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1IF: SPI1 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI1EIF: SPI1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
T3IF: Timer3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
T2IF: Timer2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
OC2IF: Output Compare Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
IC2IF: Input Capture Channel 2 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 4
DMA0IF: DMA Channel 0 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
T1IF: Timer1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 97
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-5:
IFS0: INTERRUPT FLAG STATUS REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IF: Output Compare Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
IC1IF: Input Capture Channel 1 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT0IF: External Interrupt 0 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70292D-page 98
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1
R/W-0
U2TXIF
bit 15
R/W-0
R/W-0
INT2IF
R/W-0
T5IF
R/W-0
T4IF
R/W-0
OC4IF
R/W-0
OC3IF
R/W-0
U2RXIF
DMA2IF
bit 8
R/W-0
IC8IF
R/W-0
IC7IF
U-0
—
R/W-0
INT1IF
R/W-0
CNIF
R/W-0
CMIF
R/W-0
R/W-0
MI2C1IF
SI2C1IF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIF: UART2 Transmitter Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2RXIF: UART2 Receiver Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
INT2IF: External Interrupt 2 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T5IF: Timer5 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
T4IF: Timer4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC4IF: Output Compare Channel 4 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
OC3IF: Output Compare Channel 3 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 8
DMA2IF: DMA Channel 2 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 7
IC8IF: Input Capture Channel 8 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 6
IC7IF: Input Capture Channel 7 Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IF: External Interrupt 1 Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
CNIF: Input Change Notification Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 99
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-6:
IFS1: INTERRUPT FLAG STATUS REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
CMIF: Comparator Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
MI2C1IF: I2C1 Master Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SI2C1IF: I2C1 Slave Events Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DS70292D-page 100
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-7:
IFS2: INTERRUPT FLAG STATUS REGISTER 2
U-0
—
R/W-0
R/W-0
PMPIF
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMA4IF
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
C1IF(1)
R/W-0
C1RXIF(1)
R/W-0
SPI2IF
R/W-0
DMA3IF
SPI2EIF
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA4IF: DMA Channel 4 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
PMPIF: Parallel Master Port Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 12-5
bit 4
Unimplemented: Read as ‘0’
DMA3IF: DMA Channel 3 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 3
bit 2
bit 1
bit 0
C1IF: ECAN1 Event Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
C1RXIF: ECAN1 Receive Data Ready Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2IF: SPI2 Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
SPI2EIF: SPI2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Note 1: Interrupts disabled on devices without ECAN™ modules.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 101
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-8:
IFS3: INTERRUPT FLAG STATUS REGISTER 3
U-0
—
R/W-0
RTCIF
R/W-0
R/W-0
DCIIF
R/W-0
U-0
—
U-0
—
U-0
—
DMA5IF
DCIEIF
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
RTCIF: Real-Time Clock and Calendar Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13
bit 12
bit 11
DMA5IF: DMA Channel 5 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DCIIF: DCI Event Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DCIEIF: DCI Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 10-0
Unimplemented: Read as ‘0’
DS70292D-page 102
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-9:
IFS4: INTERRUPT FLAG STATUS REGISTER 4
R/W-0
DAC1LIF(2)
R/W-0
DAC1RIF(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
C1TXIF(1)
R/W-0
R/W-0
R/W-0
CRCIF
R/W-0
U2EIF
R/W-0
U1EIF
U-0
—
DMA7IF
DMA6IF
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
DAC1LIF: DAC Left Channel Interrupt Flag Status bit(2)
1= Interrupt request has occurred
0= Interrupt request has not occurred
DAC1RIF: DAC Right Channel Interrupt Flag Status bit(2)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 13-7
bit 6
Unimplemented: Read as ‘0’
C1TXIF: ECAN1 Transmit Data Request Interrupt Flag Status bit(1)
1= Interrupt request has occurred
0= Interrupt request has not occurred
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DMA7IF: DMA Channel 7 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
DMA6IF: DMA Channel 6 Data Transfer Complete Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
CRCIF: CRC Generator Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U2EIF: UART2 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
U1EIF: UART1 Error Interrupt Flag Status bit
1= Interrupt request has occurred
0= Interrupt request has not occurred
Unimplemented: Read as ‘0’
Note 1: Interrupts disabled on devices without ECAN™ modules.
2: Interrupts disabled on devices without Audio DAC modules.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 103
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0
U-0
—
R/W-0
R/W-0
AD1IE
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
T3IE
DMA1IE
U1TXIE
U1RXIE
SPI1IE
SPI1EIE
bit 15
bit 8
R/W-0
T2IE
R/W-0
OC2IE
R/W-0
IC2IE
R/W-0
R/W-0
T1IE
R/W-0
OC1IE
R/W-0
IC1IE
R/W-0
DMA0IE
INT0IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA1IE: DMA Channel 1 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
bit 11
bit 10
bit 9
AD1IE: ADC1 Conversion Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1TXIE: UART1 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1RXIE: UART1 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1IE: SPI1 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI1EIE: SPI1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
T3IE: Timer3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
T2IE: Timer2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
OC2IE: Output Compare Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
IC2IE: Input Capture Channel 2 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 4
DMA0IE: DMA Channel 0 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
T1IE: Timer1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70292D-page 104
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-10: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 (CONTINUED)
bit 2
bit 1
bit 0
OC1IE: Output Compare Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
IC1IE: Input Capture Channel 1 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT0IE: External Interrupt 0 Flag Status bit
1= Interrupt request enabled
0= Interrupt request not enabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 105
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1
R/W-0
R/W-0
R/W-0
R/W-0
T5IE
R/W-0
T4IE
R/W-0
OC4IE
R/W-0
OC3IE
R/W-0
U2TXIE
U2RXIE
INT2IE
DMA2IE
bit 15
bit 8
R/W-0
IC8IE
R/W-0
IC7IE
U-0
—
R/W-0
R/W-0
CNIE
R/W-0
CMIE
R/W-0
R/W-0
INT1IE
MI2C1IE
SI2C1IE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
U2TXIE: UART2 Transmitter Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U2RXIE: UART2 Receiver Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
INT2IE: External Interrupt 2 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T5IE: Timer5 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
T4IE: Timer4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC4IE: Output Compare Channel 4 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
OC3IE: Output Compare Channel 3 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 8
DMA2IE: DMA Channel 2 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 7
IC8IE: Input Capture Channel 8 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 6
IC7IE: Input Capture Channel 7 Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 5
bit 4
Unimplemented: Read as ‘0’
INT1IE: External Interrupt 1 Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 3
CNIE: Input Change Notification Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DS70292D-page 106
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-11: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED)
bit 2
bit 1
bit 0
CMIE: Comparator Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
MI2C1IE: I2C1 Master Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SI2C1IE: I2C1 Slave Events Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 107
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-12: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMA4IE
PMPIE
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
C1IE(1)
R/W-0
C1RXIE(1)
R/W-0
R/W-0
DMA3IE
SPI2IE
SPI2EIE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
DMA4IE: DMA Channel 4 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
PMPIE: Parallel Master Port Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 12-5
bit 4
Unimplemented: Read as ‘0’
DMA3IE: DMA Channel 3 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request has enabled
bit 3
bit 2
bit 1
bit 0
C1IE: ECAN1 Event Interrupt Enable bit(1)
1= Interrupt request enabled
0= Interrupt request not enabled
C1RXIE: ECAN1 Receive Data Ready Interrupt Enable bit(1)
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2IE: SPI2 Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
SPI2EIE: SPI2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
Note 1: Interrupts disabled on devices without ECAN™ modules.
DS70292D-page 108
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3
U-0
—
R/W-0
RTCIE
R/W-0
R/W-0
DCIIE
R/W-0
U-0
—
U-0
—
U-0
—
DMA5IE
DCIEIE
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
RTCIE: Real-Time Clock and Calendar Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13
bit 12
bit 11
DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DCIIE: DCI Event Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DCIEIE: DCI Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
bit 10-0
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 109
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-14: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4
R/W-0
DAC1LIE(2)
bit 15
R/W-0
DAC1RIE(2)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
bit 0
U-0
—
R/W-0
C1TXIE(1)
R/W-0
R/W-0
R/W-0
R/W-0
U2EIE
R/W-0
U1EIE
U-0
—
DMA7IE
DMA6IE
CRCIE
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
DAC1LIE: DAC Left Channel Interrupt Enable bit(2)
1= Interrupt request enabled
0= Interrupt request not enabled
DAC1RIE: DAC Right Channel Interrupt Enable bit(2)
1= Interrupt request enabled
0= Interrupt request not enabled
bit 13-7
bit 6
Unimplemented: Read as ‘0’
C1TXIE: ECAN1 Transmit Data Request Interrupt Enable bit(1)
1= Interrupt request occurred
0= Interrupt request not occurred
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DMA7IE: DMA Channel 7 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
DMA6IE: DMA Channel 6 Data Transfer Complete Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
CRCIE: CRC Generator Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U2EIE: UART2 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
U1EIE: UART1 Error Interrupt Enable bit
1= Interrupt request enabled
0= Interrupt request not enabled
Unimplemented: Read as ‘0’
Note 1: Interrupts disabled on devices without ECAN™ modules.
2: Interrupts disabled on devices without Audio DAC modules.
DS70292D-page 110
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-15: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
T1IP<2:0>
OC1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
IC1IP<2:0>
INT0IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T1IP<2:0>: Timer1 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC1IP<2:0>: Output Compare Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC1IP<2:0>: Input Capture Channel 1 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
INT0IP<2:0>: External Interrupt 0 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 111
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-16: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
T2IP<2:0>
OC2IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
IC2IP<2:0>
DMA0IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T2IP<2:0>: Timer2 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC2IP<2:0>: Output Compare Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
IC2IP<2:0>: Input Capture Channel 2 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA0IP<2:0>: DMA Channel 0 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70292D-page 112
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-17: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
U1RXIP<2:0>
SPI1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
SPI1EIP<2:0>
T3IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U1RXIP<2:0>: UART1 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
SPI1IP<2:0>: SPI1 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI1EIP<2:0>: SPI1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T3IP<2:0>: Timer3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 113
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-18: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
DMA1IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
AD1IP<2:0>
U1TXIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
DMA1IP<2:0>: DMA Channel 1 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
AD1IP<2:0>: ADC1 Conversion Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
U1TXIP<2:0>: UART1 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70292D-page 114
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-19: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
CNIP<2:0>
CMIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
MI2C1IP<2:0>
SI2C1IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CNIP<2:0>: Change Notification Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
CMIP<2:0>: Comparator Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MI2C1IP<2:0>: I2C1 Master Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SI2C1IP<2:0>: I2C1 Slave Events Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 115
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-20: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
IC8IP<2:0>
IC7IP<2:0>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
INT1IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
IC8IP<2:0>: Input Capture Channel 8 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
IC7IP<2:0>: Input Capture Channel 7 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7-3
bit 2-0
Unimplemented: Read as ‘0’
INT1IP<2:0>: External Interrupt 1 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70292D-page 116
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-21: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
T4IP<2:0>
OC4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
OC3IP<2:0>
DMA2IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
T4IP<2:0>: Timer4 Interrupt Priority bits
bit 14-12
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
OC4IP<2:0>: Output Compare Channel 4 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
OC3IP<2:0>: Output Compare Channel 3 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA2IP<2:0>: DMA Channel 2 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 117
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-22: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
R/W-0
U2TXIP<2:0>
U2RXIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
INT2IP<2:0>
T5IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
U2TXIP<2:0>: UART2 Transmitter Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2RXIP<2:0>: UART2 Receiver Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70292D-page 118
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-23: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8
U-0
—
R/W-1
R/W-0
C1IP<2:0>(1)
R/W-0
U-0
—
R/W-1
R/W-0
C1RXIP<2:0>(1)
R/W-0
bit 8
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
SPI2IP<2:0>
SPI2EIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
C1IP<2:0>: ECAN1 Event Interrupt Priority bits(1)
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
C1RXIP<2:0>: ECAN1 Receive Data Ready Interrupt Priority bits(1)
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SPI2IP<2:0>: SPI2 Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
SPI2EIP<2:0>: SPI2 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
Note 1: Interrupts disabled on devices without ECAN™ modules.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 119
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-24: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
DMA3IP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
DMA3IP<2:0>: DMA Channel 3 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
DS70292D-page 120
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-25: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
DMA4IP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
PMPIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
DMA4IP<2:0>: DMA Channel 4 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
PMPIP<2:0>: Parallel Master Port Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 121
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-26: IPC14: INTERRUPT PRIORITY CONTROL REGISTER 14
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
DCIEIP<2:0>
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
DCIEIP<2:0>: DCI Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11-0
Unimplemented: Read as ‘0’
DS70292D-page 122
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-27: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
RTCIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
DMA5IP<2:0>
DCIIP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
RTCIP<2:0>: Real-Time Clock and Calendar Interrupt Flag Status bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DMA5IP<2:0>: DMA Channel 5 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
DCIIP<2:0>: DCI Event Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 123
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-28: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 8
CRCIP<2:0>
U2EIP<2:0>
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U1EIP<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
CRCIP<2:0>: CRC Generator Error Interrupt Flag Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
U2EIP<2:0>: UART2 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
U1EIP<2:0>: UART1 Error Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3-0
Unimplemented: Read as ‘0’
DS70292D-page 124
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-29: IPC17: INTERRUPT PRIORITY CONTROL REGISTER 17
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-1
R/W-0
C1TXIP<2:0>(1)
R/W-0
bit 8
bit 15
U-0
—
R/W-1
R/W-0
R/W-0
U-0
—
R/W-1
R/W-0
R/W-0
bit 0
DMA7IP<2:0>
DMA6IP<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
Unimplemented: Read as ‘0’
C1TXIP<2:0>: ECAN1 Transmit Data Request Interrupt Priority bits(1)
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7
Unimplemented: Read as ‘0’
bit 6-4
DMA7IP<2:0>: DMA Channel 7 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
DMA6IP<2:0>: DMA Channel 6 Data Transfer Complete Interrupt Priority bits
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
Note 1: Interrupts disabled on devices without ECAN™ modules.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 125
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-30: IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19
U-0
—
R/W-1
R/W-0
DAC1LIP<2:0>(1)
R/W-0
U-0
—
R/W-0
R/W-0
DAC1RIP<2:0>(1)
R/W-0
bit 8
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
DAC1LIP<2:0>: DAC Left Channel Interrupt Flag Status bit(1)
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 11
Unimplemented: Read as ‘0’
bit 10-8
DAC1RIP<2:0>: DAC Right Channel Interrupt Flag Status bit(1)
111= Interrupt is priority 7 (highest priority interrupt)
•
•
•
001= Interrupt is priority 1
000= Interrupt source is disabled
bit 7-0
Unimplemented: Read as ‘0’
Note 1: Interrupts disabled on devices without Audio DAC modules.
DS70292D-page 126
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 7-31: INTTREG: INTERRUPT CONTROL AND STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
ILR<3:0>
bit 15
bit 8
bit 0
U-0
—
R-0
R-0
R-0
R-0
R-0
VECNUM<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
ILR<3:0>: New CPU Interrupt Priority Level bits
1111= CPU Interrupt Priority Level is 15
•
•
•
0001= CPU Interrupt Priority Level is 1
0000= CPU Interrupt Priority Level is 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
VECNUM<6:0>: Vector Number of Pending Interrupt bits
0111111= Interrupt Vector pending is number 135
•
•
•
0000001= Interrupt Vector pending is number 9
0000000= Interrupt Vector pending is number 8
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 127
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
7.4.3
TRAP SERVICE ROUTINE
7.4
Interrupt Setup Procedures
A Trap Service Routine (TSR) is coded like an ISR,
except that the appropriate trap status flag in the
INTCON1 register must be cleared to avoid re-entry
into the TSR.
7.4.1
INITIALIZATION
To configure an interrupt source at initialization:
1. Set the NSTDIS bit (INTCON1<15>) if nested
interrupts are not desired.
7.4.4
INTERRUPT DISABLE
2. Select the user-assigned priority level for the
interrupt source by writing the control bits in the
appropriate IPCx register. The priority level
depends on the specific application and type of
interrupt source. If multiple priority levels are not
desired, the IPCx register control bits for all
enabled interrupt sources can be programmed
to the same non-zero value.
All user interrupts can be disabled using this
procedure:
1. Push the current SR value onto the software
stack using the PUSHinstruction.
2. Force the CPU to priority level 7 by inclusive
ORing the value OEh with SRL.
To enable user interrupts, the POP instruction can be
Note: At a device Reset, the IPCx registers are
initialized such that all user interrupt
sources are assigned to priority level 4.
used to restore the previous SR value.
Note:
Only user interrupts with a priority level of
7 or lower can be disabled. Trap sources
(level 8-level 15) cannot be disabled.
3. Clear the interrupt flag status bit associated with
the peripheral in the associated IFSx register.
The DISI instruction provides a convenient way to
disable interrupts of priority levels 1-6 for a fixed period
of time. Level 7 interrupt sources are not disabled by
the DISI instruction.
4. Enable the interrupt source by setting the inter-
rupt enable control bit associated with the
source in the appropriate IECx register.
7.4.2
INTERRUPT SERVICE ROUTINE
The method used to declare an ISR and initialize the
IVT with the correct vector address depends on the
programming language (C or assembler) and the
language development tool suite used to develop the
application.
In general, the user application must clear the interrupt
flag in the appropriate IFSx register for the source of
interrupt that the ISR handles. Otherwise, the program
re-enters the ISR immediately after exiting the routine.
If the ISR is coded in assembly language, it must be
terminated using a RETFIE instruction to unstack the
saved PC value, SRL value and old CPU priority level.
DS70292D-page 128
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Direct Memory Access (DMA) is a very efficient
8.0
DIRECT MEMORY ACCESS
(DMA)
mechanism of copying data between peripheral SFRs
(e.g., UART Receive register, Input Capture 1 buffer),
and buffers or variables stored in RAM, with minimal
CPU intervention. The DMA controller can
automatically copy entire blocks of data without
requiring the user software to read or write the
peripheral Special Function Registers (SFRs) every
time a peripheral interrupt occurs. The DMA controller
uses a dedicated bus for data transfers and therefore,
does not steal cycles from the code execution flow of
the CPU. To exploit the DMA capability, the
corresponding user buffers or variables must be
located in DMA RAM.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 38. Direct Memory
Access (DMA) (Part III)” (DS70215) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 peripherals that
can utilize DMA are listed in Table 8-1.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
TABLE 8-1:
DMA CHANNEL TO PERIPHERAL ASSOCIATIONS
DMAxPAD Register
Values to Read from
Peripheral
DMAxPAD Register
Values to Write to
Peripheral
DMAxREQ Register
IRQSEL<6:0> Bits
Peripheral to DMA Association
INT0 – External Interrupt 0
IC1 – Input Capture 1
0000000
0000001
0000010
0000010
0000101
0000110
0000110
0000111
0001000
0001010
0001011
0001100
0001101
0011110
0011111
0100001
0100010
0101101
1000110
0111100
1001110
1001111
—
—
—
0x0140 (IC1BUF)
OC1 – Output Compare 1 Data
OC1 – Output Compare 1 Secondary Data
IC2 – Input Capture 2
—
0x0182 (OC1R)
0x0180 (OC1RS)
—
—
0x0144 (IC2BUF)
OC2 – Output Compare 2 Data
OC2 – Output Compare 2 Secondary Data
TMR2 – Timer2
—
0x0188 (OC2R)
0x0186 (OC2RS)
—
—
—
TMR3 – Timer3
—
0x0248 (SPI1BUF)
0x0226 (U1RXREG)
—
—
SPI1 – Transfer Done
0x0248 (SPI1BUF)
—
UART1RX – UART1 Receiver
UART1TX – UART1 Transmitter
ADC1 – ADC1 convert done
UART2RX – UART2 Receiver
UART2TX – UART2 Transmitter
SPI2 – Transfer Done
0x0224 (U1TXREG)
—
0x0300 (ADC1BUF0)
0x0236 (U2RXREG)
—
—
0x0234 (U2TXREG)
0x0268 (SPI2BUF)
—
0x0268 (SPI2BUF)
0x0440 (C1RXD)
0x0608 (PMDIN1)
—
ECAN1 – RX Data Ready
PMP – Master Data Transfer
ECAN1 – TX Data Request
DCI – Codec Transfer Done
DAC1 – Right Data Output
DAC2 – Left Data Output
0x0608 (PMDIN1)
0x0442 (C1TXD)
0x0298 (TXBUF0)
0x03F6 (DAC1RDAT)
0x03F8 (DAC1LDAT)
0x0290 (RXBUF0)
—
—
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 129
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The DMA controller features eight identical data
transfer channels.
• Byte or word transfers
• Fixed priority channel arbitration
• Manual (software) or Automatic (peripheral DMA
requests) transfer initiation
Each channel has its own set of control and status
registers. Each DMA channel can be configured to
copy data either from buffers stored in dual port DMA
RAM to peripheral SFRs, or from peripheral SFRs to
buffers in DMA RAM.
• One-Shot or Auto-Repeat block transfer modes
• Ping-Pong mode (automatic switch between two
DPSRAM start addresses after each block trans-
fer complete)
The DMA controller supports the following features:
• Eight DMA channels
• DMA request for each channel can be selected
from any supported interrupt source
• Register Indirect With Post-increment Addressing
mode
• Debug support features
For each DMA channel, a DMA interrupt request is
• Register Indirect Without Post-increment
Addressing mode
generated when
a
block transfer is complete.
Alternatively, an interrupt can be generated when half of
the block has been filled.
• Peripheral Indirect Addressing mode (peripheral
generates destination address)
• CPU interrupt after half or full block transfer
complete
FIGURE 8-1:
TOP LEVEL SYSTEM ARCHITECTURE USING A DEDICATED TRANSACTION BUS
Peripheral Indirect Address
DMA Controller
DMA
Ready
Peripheral 3
DMA
Channels
DMA RAM
SRAM
PORT 1 PORT 2
CPU DMA
SRAM X-Bus
DMA DS Bus
CPU Peripheral DS Bus
CPU
DMA
CPU DMA
Non-DMA
Ready
Peripheral
DMA
Ready
Peripheral 2
DMA
Ready
Peripheral 1
CPU
Note:
CPU and DMA address buses are not shown for clarity.
DS70292D-page 130
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The DMAxCON, DMAxREQ, DMAxPAD and
8.1
DMAC Registers
DMAxCNT are all conventional read/write registers.
Reads of DMAxSTA or DMAxSTB reads the contents
of the DMA RAM Address register. Writes to DMAx-
STA or DMAxSTB write to the registers. This allows
the user to determine the DMA buffer pointer value
(address) at any time.
Each DMAC Channel x (x = 0, 1, 2, 3, 4, 5, 6 or 7)
contains the following registers:
• A 16-bit DMA Channel Control register
(DMAxCON)
• A 16-bit DMA Channel IRQ Select register
(DMAxREQ)
The interrupt flags (DMAxIF) are located in an IFSx
register in the interrupt controller. The corresponding
interrupt enable control bits (DMAxIE) are located in
an IECx register in the interrupt controller, and the cor-
responding interrupt priority control bits (DMAxIP) are
located in an IPCx register in the interrupt controller.
• A 16-bit DMA RAM Primary Start Address register
(DMAxSTA)
• A 16-bit DMA RAM Secondary Start Address
register (DMAxSTB)
• A 16-bit DMA Peripheral Address register
(DMAxPAD)
• A 10-bit DMA Transfer Count register (DMAxCNT)
An additional pair of status registers, DMACS0 and
DMACS1, are common to all DMAC channels.
DMACS0 contains the DMA RAM and SFR write colli-
sion flags, XWCOLx and PWCOLx, respectively.
DMACS1 indicates DMA channel and Ping-Pong mode
status.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 131
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-1:
DMAxCON: DMA CHANNEL x CONTROL REGISTER
R/W-0
CHEN
R/W-0
SIZE
R/W-0
DIR
R/W-0
HALF
R/W-0
U-0
—
U-0
—
U-0
—
NULLW
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
AMODE<1:0>
MODE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
CHEN: Channel Enable bit
1= Channel enabled
0= Channel disabled
SIZE: Data Transfer Size bit
1= Byte
0= Word
DIR: Transfer Direction bit (source/destination bus select)
1= Read from DMA RAM address, write to peripheral address
0= Read from peripheral address, write to DMA RAM address
HALF: Early Block Transfer Complete Interrupt Select bit
1= Initiate block transfer complete interrupt when half of the data has been moved
0= Initiate block transfer complete interrupt when all of the data has been moved
NULLW: Null Data Peripheral Write Mode Select bit
1= Null data write to peripheral in addition to DMA RAM write (DIR bit must also be clear)
0= Normal operation
bit 10-6
bit 5-4
Unimplemented: Read as ‘0’
AMODE<1:0>: DMA Channel Operating Mode Select bits
11= Reserved (acts as Peripheral Indirect Addressing mode)
10= Peripheral Indirect Addressing mode
01= Register Indirect without Post-Increment mode
00= Register Indirect with Post-Increment mode
bit 3-2
bit 1-0
Unimplemented: Read as ‘0’
MODE<1:0>: DMA Channel Operating Mode Select bits
11= One-Shot, Ping-Pong modes enabled (one block transfer from/to each DMA RAM buffer)
10= Continuous, Ping-Pong modes enabled
01= One-Shot, Ping-Pong modes disabled
00= Continuous, Ping-Pong modes disabled
DS70292D-page 132
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-2:
DMAxREQ: DMA CHANNEL x IRQ SELECT REGISTER
R/W-0
FORCE(1)
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
IRQSEL6<6:0>(2)
R/W-0
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
FORCE: Force DMA Transfer bit(1)
1= Force a single DMA transfer (Manual mode)
0= Automatic DMA transfer initiation by DMA request
bit 14-7
bit 6-0
Unimplemented: Read as ‘0’
IRQSEL<6:0>: DMA Peripheral IRQ Number Select bits(2)
0000000-1111111= DMAIRQ0-DMAIRQ127 selected to be Channel DMAREQ
Note 1: The FORCE bit cannot be cleared by the user. The FORCE bit is cleared by hardware when the forced
DMA transfer is complete.
2: Refer to Table 7-1 for a complete listing of IRQ numbers for all interrupt sources.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 133
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-3:
DMAxSTA: DMA CHANNEL x RAM START ADDRESS REGISTER A(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STA<15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
STA<7:0>
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STA<15:0>: Primary DMA RAM Start Address bits (source or destination)
Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the
contents written to STA<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
REGISTER 8-4:
DMAxSTB: DMA CHANNEL x RAM START ADDRESS REGISTER B(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
STB<15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0 R/W-0
STB<7:0>
R/W-0
R/W-0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
STB<15:0>: Secondary DMA RAM Start Address bits (source or destination)
Note 1: A read of this address register returns the current contents of the DMA RAM Address register, not the con-
tents written to STB<15:0>. If the channel is enabled (i.e., active), writes to this register may result in
unpredictable behavior of the DMA channel and should be avoided.
DS70292D-page 134
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-5:
DMAxPAD: DMA CHANNEL x PERIPHERAL ADDRESS REGISTER(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
PAD<15:8>
bit 15
R/W-0
bit 7
R/W-0
PAD<7:0>
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
PAD<15:0>: Peripheral Address Register bits
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
REGISTER 8-6:
DMAxCNT: DMA CHANNEL x TRANSFER COUNT REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CNT<9:8>(2)
bit 15
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
CNT<7:0>(2)
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
CNT<9:0>: DMA Transfer Count Register bits(2)
Note 1: If the channel is enabled (i.e., active), writes to this register may result in unpredictable behavior of the
DMA channel and should be avoided.
2: Number of DMA transfers = CNT<9:0> + 1.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 135
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0
R/C-0
PWCOL7
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
PWCOL6
PWCOL5
PWCOL4
PWCOL3
PWCOL2
PWCOL1
PWCOL0
bit 8
R/C-0
XWCOL7
bit 7
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
XWCOL6
XWCOL5
XWCOL4
XWCOL3
XWCOL2
XWCOL1
XWCOL0
bit 0
Legend:
C = Clear only bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
PWCOL7: Channel 7 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL6: Channel 6 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL5: Channel 5 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL4: Channel 4 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL3: Channel 3 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL2: Channel 2 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
PWCOL1: Channel 1 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 8
PWCOL0: Channel 0 Peripheral Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 7
XWCOL7: Channel 7 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 6
XWCOL6: Channel 6 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 5
XWCOL5: Channel 5 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
bit 4
XWCOL4: Channel 4 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
DS70292D-page 136
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-7:
DMACS0: DMA CONTROLLER STATUS REGISTER 0 (CONTINUED)
bit 3
bit 2
bit 1
bit 0
XWCOL3: Channel 3 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL2: Channel 2 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL1: Channel 1 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
XWCOL0: Channel 0 DMA RAM Write Collision Flag bit
1= Write collision detected
0= No write collision detected
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 137
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-8:
DMACS1: DMA CONTROLLER STATUS REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
R-1
R-1
R-1
R-1
LSTCH<3:0>
bit 15
bit 8
R-0
PPST7
bit 7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
PPST6
PPST5
PPST4
PPST3
PPST2
PPST1
PPST0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
LSTCH<3:0>: Last DMA Channel Active bits
1111= No DMA transfer has occurred since system Reset
1110-1000= Reserved
0111= Last data transfer was by DMA Channel 7
0110= Last data transfer was by DMA Channel 6
0101= Last data transfer was by DMA Channel 5
0100= Last data transfer was by DMA Channel 4
0011= Last data transfer was by DMA Channel 3
0010= Last data transfer was by DMA Channel 2
0001= Last data transfer was by DMA Channel 1
0000= Last data transfer was by DMA Channel 0
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PPST7: Channel 7 Ping-Pong Mode Status Flag bit
1= DMA7STB register selected
0= DMA7STA register selected
PPST6: Channel 6 Ping-Pong Mode Status Flag bit
1= DMA6STB register selected
0= DMA6STA register selected
PPST5: Channel 5 Ping-Pong Mode Status Flag bit
1= DMA5STB register selected
0= DMA5STA register selected
PPST4: Channel 4 Ping-Pong Mode Status Flag bit
1= DMA4STB register selected
0= DMA4STA register selected
PPST3: Channel 3 Ping-Pong Mode Status Flag bit
1= DMA3STB register selected
0= DMA3STA register selected
PPST2: Channel 2 Ping-Pong Mode Status Flag bit
1= DMA2STB register selected
0= DMA2STA register selected
PPST1: Channel 1 Ping-Pong Mode Status Flag bit
1= DMA1STB register selected
0= DMA1STA register selected
PPST0: Channel 0 Ping-Pong Mode Status Flag bit
1= DMA0STB register selected
0= DMA0STA register selected
DS70292D-page 138
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 8-9:
DSADR: MOST RECENT DMA RAM ADDRESS
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DSADR<15:8>
bit 15
R-0
bit 8
bit 0
R-0
R-0
R-0
R-0
DSADR<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DSADR<15:0>: Most Recent DMA RAM Address Accessed by DMA Controller bits
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 139
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 140
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
• External and internal oscillator options as clock
sources
9.0 OSCILLATOR CONFIGURATION
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
• An on-chip Phase-Locked Loop (PLL) to scale the
internal operating frequency to the required sys-
tem clock frequency
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 39. Oscillator (Part
III)” (DS70216) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
• An internal FRC oscillator that can also be used
with the PLL, thereby allowing full-speed
operation without any external clock generation
hardware
• Clock switching between various clock sources
• Programmable clock postscaler for system power
savings
• A Fail-Safe Clock Monitor (FSCM) that detects
clock failure and takes fail-safe measures
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• A Clock Control register (OSCCON)
• Non-volatile Configuration bits for main oscillator
selection
• An auxiliary crystal oscillator for Audio DAC
A simplified diagram of the oscillator system is shown
in Figure 9-1.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 oscillator system
provides:
FIGURE 9-1:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 OSCILLATOR SYSTEM DIAGRAM
Primary Oscillator
OSC1
DOZE<2:0>
POSCCLK
XT, HS, EC
S2
R(2)
XTPLL, HSPLL,
ECPLL, FRCPLL
S3
S1
FCY
S1/S3
PLL
(1)
OSC2
FVCO
POSCMD<1:0>
÷
2
FRC
Oscillator
FRCDIVN
FRCDIV16
S7
S6
FP
FOSC
FRCDIV<2:0>
TUN<5:0>
÷ 16
FRC
S0
S5
LPRC
Oscillator
LPRC
Secondary Oscillator
SOSC
SOSCO
SOSCI
S4
LPOSCEN
Clock Switch
Reset
Clock Fail
S7
WDT, PWRT,
NOSC<2:0> FNOSC<2:0>
FSCM
Timer1
POSCCLK
AOSCCLK
(1)
Auxiliary Oscillator
FVCO
ACLK
DAC
÷ N
AOSCMD<1:0>
APSTSCLR<2:0>
SELACK
ASRCSEL
Note 1: See Figure 9-2 for PLL details.
2: If the Oscillator is used with XT or HS modes, an extended parallel resistor with the value of 1 M must be connected.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 141
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
9.1.2
SYSTEM CLOCK SELECTION
9.1
CPU Clocking System
The oscillator source used at a device Power-on
Reset event is selected using Configuration bit
settings. The oscillator Configuration bit settings are
located in the Configuration registers in the program
memory. (Refer to Section 27.1 “Configuration
Bits” for further details.) The Initial Oscillator
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices provide
seven system clock options:
• Fast RC (FRC) Oscillator
• FRC Oscillator with Phase Locked Loop (PLL)
• Primary (XT, HS or EC) Oscillator
• Primary Oscillator with PLL
Selection
(FOSCSEL<2:0>), and the Primary Oscillator Mode
Select Configuration bits, POSCMD<1:0>
Configuration
bits,
FNOSC<2:0>
• Secondary (LP) Oscillator
(FOSC<1:0>), select the oscillator source that is used
at a Power-on Reset. The FRC primary oscillator is
the default (unprogrammed) selection.
• Low-Power RC (LPRC) Oscillator
• FRC Oscillator with postscaler
The Configuration bits allow users to choose among 12
different clock modes, shown in Table 9-1.
9.1.1
SYSTEM CLOCK SOURCES
The Fast RC (FRC) internal oscillator runs at a nominal
frequency of 7.37 MHz. User software can tune the
FRC frequency. User software can optionally specify a
factor (ranging from 1:2 to 1:256) by which the FRC
clock frequency is divided. This factor is selected using
the FRCDIV<2:0> (CLKDIV<10:8>) bits.
The output of the oscillator (or the output of the PLL if
a PLL mode has been selected) FOSC is divided by 2 to
generate the device instruction clock (FCY) and
peripheral clock time base (FP). FCY defines the
operating speed of the device, and speeds up to 40
MHz are supported by the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 architecture.
The primary oscillator can use one of the following as
its clock source:
• Crystal (XT): Crystals and ceramic resonators in
the range of 3 MHz to 10 MHz. The crystal is
connected to the OSC1 and OSC2 pins.
Instruction execution speed or device operating
frequency, FCY, is given by:
• High-Speed Crystal (HS): Crystals in the range of
10 MHz to 40 MHz. The crystal is connected to
the OSC1 and OSC2 pins.
EQUATION 9-1:
DEVICE OPERATING
FREQUENCY
FCY = FOSC/2
• External Clock (EC): External clock signal is
directly applied to the OSC1 pin.
9.1.3
AUXILIARY OSCILLATOR
The secondary (LP) oscillator is designed for low power
and uses a 32.768 kHz crystal or ceramic resonator.
The LP oscillator uses the SOSCI and SOSCO pins.
The Auxiliary Oscillator (AOSC) can be used for periph-
erals that need to operate at a frequency unrelated to
the system clock such as a Digital-to-Analog Converter
(DAC).
The Low-Power RC (LPRC) internal oscIllator runs at a
nominal frequency of 32.768 kHz. It is also used as a
reference clock by the Watchdog Timer (WDT) and
Fail-Safe Clock Monitor (FSCM).
The Auxiliary Oscillator can use one of the following as
its clock source:
The clock signals generated by the FRC and primary
oscillators can be optionally applied to an on-chip PLL
to provide a wide range of output frequencies for device
operation. PLL configuration is described in
Section 9.1.4 “PLL Configuration”.
Crystal (XT): Crystal and ceramic resonators in the
range of 3 MHz to 10 MHz. The crystal is connected to
the SOCI and SOSCO pins.
High-Speed Crystal (HS): Crystals in the range of 10 to
40 MHz. The crystal is connected to the SOSCI and
SOSCO pins.
The FRC frequency depends on the FRC accuracy
(see Table 30-19) and the value of the FRC Oscillator
Tuning register (see Register 9-4).
External Clock (EC): External clock signal up to
64 MHz. The external clock signal is directly applied to
SOSCI pin.
DS70292D-page 142
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
For a primary oscillator or FRC oscillator, output ‘FIN’,
the PLL output ‘FOSC’ is given by:
9.1.4
PLL CONFIGURATION
The primary oscillator and internal FRC oscillator can
optionally use an on-chip PLL to obtain higher speeds
of operation. The PLL provides significant flexibility in
selecting the device operating speed. A block diagram
of the PLL is shown in Figure 9-2.
EQUATION 9-2:
FOSC CALCULATION
M
N1 • N2
FOSC = FIN •
(
)
The output of the primary oscillator or FRC, denoted as
‘FIN’, is divided down by a prescale factor (N1) of 2, 3,
... or 33 before being provided to the PLL’s Voltage
Controlled Oscillator (VCO). The input to the VCO must
be selected in the range of 0.8 MHz to 8 MHz. The
prescale factor ‘N1’ is selected using the
PLLPRE<4:0> bits (CLKDIV<4:0>).
For example, suppose a 10 MHz crystal is being used
with the selected oscillator mode of XT with PLL.
• If PLLPRE<4:0> = 0, then N1 = 2. This yields a
VCO input of 10/2 = 5 MHz, which is within the
acceptable range of 0.8-8 MHz.
• If PLLDIV<8:0> = 0x1E, then M = 32. This yields a
VCO output of 5 x 32 = 160 MHz, which is within
the 100-200 MHz ranged needed.
The PLL Feedback Divisor, selected using the
PLLDIV<8:0> bits (PLLFBD<8:0>), provides a factor ‘M,’
by which the input to the VCO is multiplied. This factor
must be selected such that the resulting VCO output
frequency is in the range of 100 MHz to 200 MHz.
• If PLLPOST<1:0> = 0, then N2 = 2. This provides
a Fosc of 160/2 = 80 MHz. The resultant device
operating speed is 80/2 = 40 MIPS.
The VCO output is further divided by a postscale factor
‘N2.’ This factor is selected using the PLLPOST<1:0>
bits (CLKDIV<7:6>). ‘N2’ can be either 2, 4 or 8, and
must be selected such that the PLL output frequency
(FOSC) is in the range of 12.5 MHz to 80 MHz, which
generates device operating speeds of 6.25-40 MIPS.
EQUATION 9-3:
XT WITH PLL MODE
EXAMPLE
FOSC
1
2
10000000 • 32
FCY =
=
= 40 MIPS
(
)
2
2 • 2
FIGURE 9-2:
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/
X04 PLL BLOCK DIAGRAM
FVCO
0.8-8.0 MHz
Here(1)
12.5-80 MHz
Here(1)
100-200 MHz
Here(1)
Source (Crystal, External Clock
or Internal RC)
FOSC
PLLPRE
X
VCO
PLLPOST
PLLDIV
N1
Divide by
2-33
N2
Divide by
2, 4, 8
M
Divide by
2-513
Note 1: This frequency range must be satisfied at all times.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 143
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 9-1:
CONFIGURATION BIT VALUES FOR CLOCK SELECTION
Oscillator Mode
Oscillator Source
POSCMD<1:0>
FNOSC<2:0>
Note
1, 2
Fast RC Oscillator with Divide-by-N
(FRCDIVN)
Internal
xx
111
Internal
xx
110
1
Fast RC Oscillator with Divide-by-16
(FRCDIV16)
Low-Power RC Oscillator (LPRC)
Internal
Secondary
Primary
xx
xx
10
101
100
011
1
1
Secondary (Timer1) Oscillator (SOSC)
Primary Oscillator (HS) with PLL
(HSPLL)
—
Primary Oscillator (XT) with PLL
(XTPLL)
Primary
Primary
01
00
011
011
—
1
Primary Oscillator (EC) with PLL
(ECPLL)
Primary Oscillator (HS)
Primary
Primary
Primary
Internal
Internal
10
01
00
xx
xx
010
010
010
001
000
—
—
1
Primary Oscillator (XT)
Primary Oscillator (EC)
Fast RC Oscillator with PLL (FRCPLL)
Fast RC Oscillator (FRC)
1
1
Note 1: OSC2 pin function is determined by the OSCIOFNC Configuration bit.
2: This is the default oscillator mode for an unprogrammed (erased) device.
DS70292D-page 144
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1)
U-0
—
R-0
R-0
R-0
U-0
—
R/W-y
R/W-y
NOSC<2:0>(2)
R/W-y
bit 8
COSC<2:0>
bit 15
R/W-0
CLKLOCK
bit 7
R/W-0
R-0
U-0
—
R/C-0
CF
U-0
—
R/W-0
R/W-0
IOLOCK
LOCK
LPOSCEN
OSWEN
bit 0
Legend:
y = Value set from Configuration bits on POR
C = Clear only bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
bit 14-12
COSC<2:0>: Current Oscillator Selection bits (read-only)
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 11
Unimplemented: Read as ‘0’
bit 10-8
NOSC<2:0>: New Oscillator Selection bits(2)
000= Fast RC oscillator (FRC)
001= Fast RC oscillator (FRC) with PLL
010= Primary oscillator (XT, HS, EC)
011= Primary oscillator (XT, HS, EC) with PLL
100= Secondary oscillator (SOSC)
101= Low-Power RC oscillator (LPRC)
110= Fast RC oscillator (FRC) with Divide-by-16
111= Fast RC oscillator (FRC) with Divide-by-n
bit 7
CLKLOCK: Clock Lock Enable bit
If clock switching is enabled and FSCM is disabled, (FOSC<FCKSM> = 0b01)
1= Clock switching is disabled, system clock source is locked
0= Clock switching is enabled, system clock source can be modified by clock switching
bit 6
bit 5
IOLOCK: Peripheral Pin Select Lock bit
1= Peripherial pin select is locked, write to peripheral pin select registers not allowed
0= Peripherial pin select is not locked, write to peripheral pin select registers allowed
LOCK: PLL Lock Status bit (read-only)
1= Indicates that PLL is in lock, or PLL start-up timer is satisfied
0= Indicates that PLL is out of lock, start-up timer is in progress or PLL is disabled
bit 4
bit 3
Unimplemented: Read as ‘0’
CF: Clock Fail Detect bit (read/clear by application)
1= FSCM has detected clock failure
0= FSCM has not detected clock failure
Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216)
in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 145
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 9-1:
OSCCON: OSCILLATOR CONTROL REGISTER(1) (CONTINUED)
bit 2
bit 1
Unimplemented: Read as ‘0’
LPOSCEN: Secondary (LP) Oscillator Enable bit
1= Enable secondary oscillator
0= Disable secondary oscillator
bit 0
OSWEN: Oscillator Switch Enable bit
1= Request oscillator switch to selection specified by NOSC<2:0> bits
0= Oscillator switch is complete
Note 1: Writes to this register require an unlock sequence. Refer to Section 39. “Oscillator (Part III)” (DS70216)
in the “dsPIC33F/PIC24H Family Reference Manual” (available from the Microchip website) for details.
2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted.
This applies to clock switches in either direction. In these instances, the application must switch to FRC mode
as a transition clock source between the two PLL modes.
DS70292D-page 146
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 9-2:
CLKDIV: CLOCK DIVISOR REGISTER
R/W-0
ROI
R/W-0
R/W-1
R/W-1
R/W-0
DOZEN(1)
R/W-0
R/W-0
R/W-0
bit 8
DOZE<2:0>
FRCDIV<2:0>
bit 15
R/W-0
R/W-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLLPOST<1:0>
PLLPRE<4:0>
bit 7
bit 0
Legend:
y = Value set from Configuration bits on POR
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ROI: Recover on Interrupt bit
1= Interrupts clears the DOZEN bit and the processor clock/peripheral clock ratio is set to 1:1
0= Interrupts have no effect on the DOZEN bit
bit 14-12
DOZE<2:0>: Processor Clock Reduction Select bits
000= FCY/1
001= FCY/2
010= FCY/4
011= FCY/8 (default)
100= FCY/16
101= FCY/32
110= FCY/64
111= FCY/128
bit 11
DOZEN: DOZE Mode Enable bit(1)
1= DOZE<2:0> field specifies the ratio between the peripheral clocks and the processor clocks
0= Processor clock/peripheral clock ratio forced to 1:1
bit 10-8
FRCDIV<2:0>: Internal Fast RC Oscillator Postscaler bits
000= FRC divide by 1 (default)
001= FRC divide by 2
010= FRC divide by 4
011= FRC divide by 8
100= FRC divide by 16
101= FRC divide by 32
110= FRC divide by 64
111= FRC divide by 256
bit 7-6
PLLPOST<1:0>: PLL VCO Output Divider Select bits (also denoted as ‘N2’, PLL postscaler)
00= Output/2
01= Output/4 (default)
10= Reserved
11= Output/8
bit 5
Unimplemented: Read as ‘0’
bit 4-0
PLLPRE<4:0>: PLL Phase Detector Input Divider bits (also denoted as ‘N1’, PLL prescaler)
00000= Input/2 (default)
00001= Input/3
•
•
•
11111= Input/33
Note 1: This bit is cleared when the ROI bit is set and an interrupt occurs.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 147
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 9-3:
PLLFBD: PLL FEEDBACK DIVISOR REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
PLLDIV<8>
bit 8
bit 15
R/W-0
bit 7
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
PLLDIV<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-9
bit 8-0
Unimplemented: Read as ‘0’
PLLDIV<8:0>: PLL Feedback Divisor bits (also denoted as ‘M’, PLL multiplier)
000000000= 2
000000001= 3
000000010= 4
•
•
•
000110000= 50 (default)
•
•
•
111111111= 513
DS70292D-page 148
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 9-4:
OSCTUN: FRC OSCILLATOR TUNING REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
TUN<5:0>(1)
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-6
bit 5-0
Unimplemented: Read as ‘0’
TUN<5:0>: FRC Oscillator Tuning bits(1)
011111= Center frequency +11.625% (8.23 MHz)
011110= Center frequency +11.25% (8.20 MHz)
•
•
•
000001= Center frequency +0.375% (7.40 MHz)
000000= Center frequency (7.37 MHz nominal)
111111= Center frequency -0.375% (7.345 MHz)
•
•
•
100001= Center frequency -11.625% (6.52 MHz)
100000= Center frequency -12% (6.49 MHz)
Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation and is neither
characterized nor tested.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 149
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 9-5:
ACLKCON: AUXILIARY CONTROL REGISTER
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
SELACLK
AOSCMD<1:0>
APSTSCLR<2:0>
bit 15
R/W-0
ASRCSEL
bit 7
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
SELACLK: Select Auxiliary Clock Source for Auxiliary Clock Divider
1= Auxiliary Oscillators provides the source clock for Auxiliary Clock Divider
0= PLL output (Fvco) provides the source clock for the Auxiliary Clock Divider
bit 12-11
bit 10-8
AOSCMD<1:0>: Auxiliary Oscillator Mode
11= EC External Clock Mode Select
10= XT Oscillator Mode Select
01= HS Oscillator Mode Select
00= Auxiliary Oscillator Disabled
APSTSCLR<2:0>: Auxiliary Clock Output Divider
111= divided by 1
110= divided by 2
101= divided by 4
100= divided by 8
011= divided by 16
010= divided by 32
001= divided by 64
000= divided by 256 (default)
bit 7
ASRCSEL: Select Reference Clock Source for Auxiliary Clock
1= Primary Oscillator is the Clock Source
0= Auxiliary Oscillator is the Clock Source
bit 6-0
Unimplemented: Read as ‘0’
DS70292D-page 150
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
2. If a valid clock switch has been initiated, the
9.2
Clock Switching Operation
LOCK
(OSCCON<5>)
and
the
CF
Applications are free to switch among any of the four
clock sources (Primary, LP, FRC and LPRC) under
software control at any time. To limit the possible side
effects of this flexibility, dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices have a safeguard lock built into the switch
process.
(OSCCON<3>) status bits are cleared.
3. The new oscillator is turned on by the hardware
if it is not currently running. If a crystal oscillator
must be turned on, the hardware waits until the
Oscillator Start-up Timer (OST) expires. If the
new source is using the PLL, the hardware waits
until a PLL lock is detected (LOCK = 1).
Note:
Primary Oscillator mode has three different
submodes (XT, HS and EC), which are
determined by the POSCMD<1:0> Config-
uration bits. While an application can
switch to and from Primary Oscillator
mode in software, it cannot switch among
the different primary submodes without
reprogramming the device.
4. The hardware waits for 10 clock cycles from the
new clock source and then performs the clock
switch.
5. The hardware clears the OSWEN bit to indicate a
successful clock transition. In addition, the NOSC
bit values are transferred to the COSC status bits.
6. The old clock source is turned off at this time,
with the exception of LPRC (if WDT or FSCM
are enabled) or LP (if LPOSCEN remains set).
9.2.1
ENABLING CLOCK SWITCHING
Note 1: The processor continues to execute code
throughout the clock switching sequence.
Timing-sensitive code should not be
executed during this time.
To enable clock switching, the FCKSM1 Configuration
bit in the Configuration register must be programmed to
‘0’. (Refer to Section 27.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
2: Direct clock switches between any primary
oscillator mode with PLL and FRCPLL
mode are not permitted. This applies to
clock switches in either direction. In these
instances, the application must switch to
FRC mode as a transition clock source
between the two PLL modes.
3: Refer to Section 39. “Oscillator
(Part III)” (DS70216) in the “dsPIC33F/
PIC24H Family Reference Manual” for
details.
The NOSC control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is
disabled. However, the COSC bits (OSCCON<14:12>)
reflect the clock source selected by the FNOSC
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
9.2.2
OSCILLATOR SWITCHING SEQUENCE
9.3
Fail-Safe Clock Monitor (FSCM)
Performing
sequence:
a
clock switch requires this basic
The Fail-Safe Clock Monitor (FSCM) allows the device
to continue to operate even in the event of an oscillator
failure. The FSCM function is enabled by programming.
If the FSCM function is enabled, the LPRC internal
oscillator runs at all times (except during Sleep mode)
and is not subject to control by the Watchdog Timer.
1. If
desired, read the COSC bits
(OSCCON<14:12>) to determine the current
oscillator source.
2. Perform the unlock sequence to allow a write to
the OSCCON register high byte.
In the event of an oscillator failure, the FSCM
generates a clock failure trap event and switches the
system clock over to the FRC oscillator. Then the
application program can either attempt to restart the
oscillator or execute a controlled shutdown. The trap
can be treated as a warm Reset by simply loading the
Reset address into the oscillator fail trap vector.
3. Write the appropriate value to the NOSC control
bits (OSCCON<10:8>) for the new oscillator
source.
4. Perform the unlock sequence to allow a write to
the OSCCON register low byte.
5. Set the OSWEN bit (OSCCON<0>) to initiate
the oscillator switch.
If the PLL multiplier is used to scale the system clock,
the internal FRC is also multiplied by the same factor
on clock failure. Essentially, the device switches to
FRC with PLL on a clock failure.
Once the basic sequence is completed, the system
clock hardware responds automatically as follows:
1. The clock switching hardware compares the
COSC status bits with the new value of the
NOSC control bits. If they are the same, the
clock switch is a redundant operation. In this
case, the OSWEN bit is cleared automatically
and the clock switch is aborted.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 151
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 152
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
10.2 Instruction-Based Power-Saving
Modes
10.0 POWER-SAVING FEATURES
Note 1: This data sheet summarizes the features
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices have two
special power-saving modes that are entered through
the execution of a special PWRSAV instruction. Sleep
mode stops clock operation and halts all code
execution. Idle mode halts the CPU and code
execution, but allows peripheral modules to continue
operation. The assembler syntax of the PWRSAV
instruction is shown in Example 10-1.
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 9. Watchdog Timer
and Power-Saving Modes” (DS70196)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
Note: SLEEP_MODE and IDLE_MODE are
constants defined in the assembler
include file for the selected device.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Sleep and Idle modes can be exited as a result of an
enabled interrupt, WDT time-out or a device Reset. When
the device exits these modes, it is said to wake up.
10.2.1
SLEEP MODE
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices provide
the ability to manage power consumption by selectively
managing clocking to the CPU and the peripherals. In
general, a lower clock frequency and a reduction in the
number of circuits being clocked constitutes lower
The following occur in Sleep mode:
• The system clock source is shut down. If an
on-chip oscillator is used, it is turned off.
• The device current consumption is reduced to a
minimum, provided that no I/O pin is sourcing
current.
consumed
power.
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices can manage power consumption in four
ways:
• The Fail-Safe Clock Monitor does not operate,
since the system clock source is disabled.
• The LPRC clock continues to run in Sleep mode if
the WDT is enabled.
• Clock frequency
• The WDT, if enabled, is automatically cleared
prior to entering Sleep mode.
• Instruction-based Sleep and Idle modes
• Software-controlled Doze mode
• Selective peripheral control in software
• Some device features or peripherals can continue
to operate. This includes items such as the input
change notification on the I/O ports, or peripherals
that use an external clock input.
Combinations of these methods can be used to selec-
tively tailor an application’s power consumption while
still maintaining critical application features, such as
timing-sensitive communications.
• Any peripheral that requires the system clock
source for its operation is disabled.
The device wakes up from Sleep mode on any of these
events:
10.1 Clock Frequency and Clock
Switching
• Any interrupt source that is individually enabled
• Any form of device Reset
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices allow a wide
range of clock frequencies to be selected under
application control. If the system clock configuration is
not locked, users can choose low-power or high-
precision oscillators by simply changing the NOSC bits
(OSCCON<10:8>). The process of changing a system
clock during operation, as well as limitations to the
process, are discussed in more detail in Section 9.0
“Oscillator Configuration”.
• A WDT time-out
On wake-up from Sleep mode, the processor restarts
with the same clock source that was active when Sleep
mode was entered.
EXAMPLE 10-1:
PWRSAVINSTRUCTION SYNTAX
PWRSAV #SLEEP_MODE
PWRSAV #IDLE_MODE
; Put the device into SLEEP mode
; Put the device into IDLE mode
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 153
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Doze mode is enabled by setting the DOZEN bit (CLK-
DIV<11>). The ratio between peripheral and core clock
speed is determined by the DOZE<2:0> bits (CLK-
DIV<14:12>). There are eight possible configurations,
from 1:1 to 1:128, with 1:1 being the default setting.
10.2.2
IDLE MODE
The following occur in Idle mode:
• The CPU stops executing instructions.
• The WDT is automatically cleared.
• The system clock source remains active. By
default, all peripheral modules continue to operate
normally from the system clock source, but can
also be selectively disabled (see Section 10.4
“Peripheral Module Disable”).
Programs can use Doze mode to selectively reduce
power consumption in event-driven applications. This
allows clock-sensitive functions, such as synchronous
communications, to continue without interruption while
the CPU idles, waiting for something to invoke an
interrupt routine. An automatic return to full-speed CPU
operation on interrupts can be enabled by setting the
ROI bit (CLKDIV<15>). By default, interrupt events
have no effect on Doze mode operation.
• If the WDT or FSCM is enabled, the LPRC also
remains active.
The device wakes from Idle mode on any of these
events:
For example, suppose the device is operating at
20 MIPS and the ECAN module has been configured
for 500 kbps based on this device operating speed. If
the device is placed in Doze mode with a clock
frequency ratio of 1:4, the ECAN module continues to
communicate at the required bit rate of 500 kbps, but
the CPU now starts executing instructions at a
frequency of 5 MIPS.
• Any interrupt that is individually enabled
• Any device Reset
• A WDT time-out
On wake-up from Idle mode, the clock is reapplied to
the CPU and instruction execution will begin (2-4 clock
cycles later), starting with the instruction following the
PWRSAVinstruction, or the first instruction in the ISR.
10.2.3
INTERRUPTS COINCIDENT WITH
POWER SAVE INSTRUCTIONS
10.4 Peripheral Module Disable
The Peripheral Module Disable (PMD) registers
provide a method to disable a peripheral module by
stopping all clock sources supplied to that module.
When a peripheral is disabled using the appropriate
PMD control bit, the peripheral is in a minimum power
consumption state. The control and status registers
associated with the peripheral are also disabled, so
writes to those registers do not have effect and read
values are invalid.
Any interrupt that coincides with the execution of a
PWRSAV instruction is held off until entry into Sleep or
Idle mode has completed. The device then wakes up
from Sleep or Idle mode.
10.3 Doze Mode
The preferred strategies for reducing power
consumption are changing clock speed and invoking
one of the power-saving modes. In some
circumstances, this cannot be practical. For example, it
may be necessary for an application to maintain
uninterrupted synchronous communication, even while
it is doing nothing else. Reducing system clock speed
can introduce communication errors, while using a
power-saving mode can stop communications
completely.
A peripheral module is enabled only if both the
associated bit in the PMD register is cleared and the
peripheral is supported by the specific dsPIC® DSC
variant. If the peripheral is present in the device, it is
enabled in the PMD register by default.
Note:
If a PMD bit is set, the corresponding mod-
ule is disabled after a delay of one instruc-
tion cycle. Similarly, if a PMD bit is cleared,
the corresponding module is enabled after
a delay of one instruction cycle (assuming
the module control registers are already
configured to enable module operation).
Doze mode is a simple and effective alternative method
to reduce power consumption while the device is still
executing code. In this mode, the system clock
continues to operate from the same source and at the
same speed. Peripheral modules continue to be
clocked at the same speed, while the CPU clock speed
is reduced. Synchronization between the two clock
domains is maintained, allowing the peripherals to
access the SFRs while the CPU executes code at a
slower rate.
DS70292D-page 154
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 10-1: PMD1: PERIPHERAL MODULE DISABLE CONTROL REGISTER 1
R/W-0
T5MD
R/W-0
T4MD
R/W-0
T3MD
R/W-0
T2MD
R/W-0
T1MD
U-0
—
U-0
—
R/W-0
DCIMD
bit 15
bit 8
R/W-0
R/W-0
U2MD
R/W-0
U1MD
R/W-0
R/W-0
U-0
—
R/W-0
C1MD
R/W-0
I2C1MD
SPI2MD
SPI1MD
AD1MD
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
bit 12
bit 11
T5MD: Timer5 Module Disable bit
1= Timer5 module is disabled
0= Timer5 module is enabled
T4MD: Timer4 Module Disable bit
1= Timer4 module is disabled
0= Timer4 module is enabled
T3MD: Timer3 Module Disable bit
1= Timer3 module is disabled
0= Timer3 module is enabled
T2MD: Timer2 Module Disable bit
1= Timer2 module is disabled
0= Timer2 module is enabled
T1MD: Timer1 Module Disable bit
1= Timer1 module is disabled
0= Timer1 module is enabled
bit 10-9
bit 8
Unimplemented: Read as ‘0’
DCIMD: DCI Module Disable bit
1= DCI module is disabled
0= DCI module is enabled
bit 7
bit 6
bit 5
bit 4
bit 3
I2C1MD: I2C1 Module Disable bit
1= I2C1 module is disabled
0= I2C1 module is enabled
U2MD: UART2 Module Disable bit
1= UART2 module is disabled
0= UART2 module is enabled
U1MD: UART1 Module Disable bit
1= UART1 module is disabled
0= UART1 module is enabled
SPI2MD: SPI2 Module Disable bit
1= SPI2 module is disabled
0= SPI2 module is enabled
SPI1MD: SPI1 Module Disable bit
1= SPI1 module is disabled
0= SPI1 module is enabled
bit 2
bit 1
Unimplemented: Read as ‘0’
C1MD: ECAN1 Module Disable bit
1= ECAN1 module is disabled
0= ECAN1 module is enabled
bit 0
AD1MD: ADC1 Module Disable bit
1= ADC1 module is disabled
0= ADC1 module is enabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 155
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 10-2: PMD2: PERIPHERAL MODULE DISABLE CONTROL REGISTER 2
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
IC8MD
IC7MD
IC2MD
IC1MD
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
OC4MD
OC3MD
OC2MD
OC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
IC8MD: Input Capture 8 Module Disable bit
1= Input Capture 8 module is disabled
0= Input Capture 8 module is enabled
IC7MD: Input Capture 2 Module Disable bit
1= Input Capture 7 module is disabled
0= Input Capture 7 module is enabled
bit 13-10
bit 9
Unimplemented: Read as ‘0’
IC2MD: Input Capture 2 Module Disable bit
1= Input Capture 2 module is disabled
0= Input Capture 2 module is enabled
bit 8
IC1MD: Input Capture 1 Module Disable bit
1= Input Capture 1 module is disabled
0= Input Capture 1 module is enabled
bit 7-4
bit 3
Unimplemented: Read as ‘0’
OC4MD: Output Compare 4 Module Disable bit
1= Output Compare 4 module is disabled
0= Output Compare 4 module is enabled
bit 2
bit 1
bit 0
OC3MD: Output Compare 3 Module Disable bit
1= Output Compare 3 module is disabled
0= Output Compare 3 module is enabled
OC2MD: Output Compare 2 Module Disable bit
1= Output Compare 2 module is disabled
0= Output Compare 2 module is enabled
OC1MD: Output Compare 1 Module Disable bit
1= Output Compare 1 module is disabled
0= Output Compare 1 module is enabled
DS70292D-page 156
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 10-3: PMD3: PERIPHERAL MODULE DISABLE CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CMPMD
RTCCMD
PMPMD
bit 15
bit 8
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
CRCMD
DAC1MD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-11
bit 10
Unimplemented: Read as ‘0’
CMPMD: Comparator Module Disable bit
1= Comparator module is disabled
0= Comparator module is enabled
bit 9
bit 8
bit 7
bit 6
bit 5-0
RTCCMD: RTCC Module Disable bit
1= RTCC module is disabled
0= RTCC module is enabled
PMPMD: PMP Module Disable bit
1= PMP module is disabled
0= PMP module is enabled
CRCMD: CRC Module Disable bit
1= CRC module is disabled
0= CRC module is enabled
DAC1MD: DAC1 Module Disable bit
1= DAC1 module is disabled
0= DAC1 module is enabled
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 157
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 158
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
has ownership of the output data and control signals of
the I/O pin. The logic also prevents “loop through,” in
11.0 I/O PORTS
which a port’s digital output can drive the input of a
peripheral that shares the same pin. Figure 11-1 shows
how ports are shared with other peripherals and the
associated I/O pin to which they are connected.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 10. I/O Ports”
(DS70193) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
When a peripheral is enabled and the peripheral is
actively driving an associated pin, the use of the pin as
a general purpose output pin is disabled. The I/O pin
can be read, but the output driver for the parallel port bit
is disabled. If a peripheral is enabled, but the peripheral
is not actively driving a pin, that pin can be driven by a
port.
All port pins have three registers directly associated
with their operation as digital I/O. The data direction
register (TRISx) determines whether the pin is an input
or an output. If the data direction bit is a ‘1’, then the pin
is an input. All port pins are defined as inputs after a
Reset. Reads from the latch (LATx) read the latch.
Writes to the latch write the latch. Reads from the port
(PORTx) read the port pins, while writes to the port pins
write the latch.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
All of the device pins (except VDD, VSS, MCLR and
OSC1/CLKI) are shared among the peripherals and the
parallel I/O ports. All I/O input ports feature Schmitt
Trigger inputs for improved noise immunity.
Any bit and its associated data and control registers
that are not valid for a particular device is disabled.
This means the corresponding LATx and TRISx
registers and the port pin are read as zeros.
11.1 Parallel I/O (PIO) Ports
When a pin is shared with another peripheral or
function that is defined as an input only, it is
nevertheless regarded as a dedicated port because
there is no other competing source of outputs.
Generally a parallel I/O port that shares a pin with a
peripheral is subservient to the peripheral. The
peripheral’s output buffer data and control signals are
provided to a pair of multiplexers. The multiplexers
select whether the peripheral or the associated port
FIGURE 11-1:
BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE
Output Multiplexers
Peripheral Module
Peripheral Input Data
Peripheral Module Enable
I/O
Peripheral Output Enable
Peripheral Output Data
1
0
Output Enable
Output Data
PIO Module
1
0
Read TRIS
Data Bus
WR TRIS
D
Q
I/O Pin
CK
TRIS Latch
D
Q
WR LAT +
WR Port
CK
Data Latch
Read LAT
Read Port
Input Data
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 159
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
11.2 Open-Drain Configuration
11.4 I/O Port Write/Read Timing
In addition to the PORT, LAT and TRIS registers for
data control, some port pins can also be individually
configured for either digital or open-drain output. This
is controlled by the Open-Drain Control register,
ODCx, associated with each port. Setting any of the
bits configures the corresponding pin to act as an
open-drain output.
One instruction cycle is required between a port
direction change or port write operation and a read
operation of the same port. Typically this instruction
would be an NOP, as shown in Example 11-1.
11.5 Input Change Notification
The input change notification function of the I/O ports
The open-drain feature allows the generation of
outputs higher than VDD (e.g., 5V) on any desired 5V
tolerant pins by using external pull-up resistors. The
maximum open-drain voltage allowed is the same as
the maximum VIH specification.
allows
the
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices to generate interrupt requests to the pro-
cessor in response to a change-of-state on selected
input pins. This feature can detect input change-of-
states even in Sleep mode, when the clocks are dis-
abled. Depending on the device pin count, up to 21
external signals (CNx pin) can be selected (enabled)
for generating an interrupt request on a change-of-
state.
Refer to “Pin Diagrams” for the available pins and
their functionality.
11.3 Configuring Analog Port Pins
The AD1PCFGL and TRIS registers control the opera-
tion of the analog-to-digital (A/D) port pins. The port
pins that are to function as analog inputs must have
their corresponding TRIS bit set (input). If the TRIS bit
is cleared (output), the digital output level (VOH or VOL)
is converted.
Four control registers are associated with the CN mod-
ule. The CNEN1 and CNEN2 registers contain the
interrupt enable control bits for each of the CN input
pins. Setting any of these bits enables a CN interrupt
for the corresponding pins.
Each CN pin also has a weak pull-up connected to it.
The pull-ups act as a current source connected to the
pin, and eliminate the need for external resistors when
push-button or keypad devices are connected. The
pull-ups are enabled separately using the CNPU1 and
CNPU2 registers, which contain the control bits for
each of the CN pins. Setting any of the control bits
enables the weak pull-ups for the corresponding pins.
The AD1PCFGL register has a default value of 0x0000;
therefore, all pins that share ANx functions are analog
(not digital) by default.
When the PORT register is read, all pins configured as
analog input channels are read as cleared (a low level).
Pins configured as digital inputs do not convert an
analog input. Analog levels on any pin defined as a
digital input (including the ANx pins) can cause the
input buffer to consume current that exceeds the
device specifications.
Note:
Pull-ups on change notification pins
should always be disabled when the port
pin is configured as a digital output.
EXAMPLE 11-1:
PORT WRITE/READ EXAMPLE
MOV
MOV
NOP
0xFF00, W0
W0, TRISBB
; Configure PORTB<15:8> as inputs
; and PORTB<7:0> as outputs
; Delay 1 cycle
btss PORTB, #13
; Next Instruction
DS70292D-page 160
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
11.6.2.1
Input Mapping
11.6 Peripheral Pin Select
The inputs of the peripheral pin select options are
mapped on the basis of the peripheral. A control
register associated with a peripheral dictates the pin it
is mapped to. The RPINRx registers are used to
configure peripheral input mapping (see Register 11-1
through Register 11-16). Each register contains sets of
5-bit fields, with each set associated with one of the
Peripheral pin select configuration enables peripheral
set selection and placement on a wide range of I/O
pins. By increasing the pinout options available on a
particular device, programmers can better tailor the
microcontroller to their entire application, rather than
trimming the application to fit the device.
The peripheral pin select configuration feature
operates over a fixed subset of digital I/O pins.
Programmers can independently map the input and/or
output of most digital peripherals to any one of these
I/O pins. Peripheral pin select is performed in
software, and generally does not require the device to
be reprogrammed. Hardware safeguards are included
that prevent accidental or spurious changes to the
peripheral mapping, once it has been established.
remappable peripherals. Programming
a
given
peripheral’s bit field with an appropriate 5-bit value
maps the RPn pin with that value to that peripheral.
For any given device, the valid range of values for any
bit field corresponds to the maximum number of
peripheral pin selections supported by the device.
Figure 11-2 illustrates remappable pin selection for
U1RX input.
Note:
For input mapping only, the Peripheral Pin
Select (PPS) functionality does not have
priority over the TRISx settings. Therefore,
when configuring the RPx pin for input, the
corresponding bit in the TRISx register
must also be configured for input (i.e., set
to ‘1’).
11.6.1
AVAILABLE PINS
The peripheral pin select feature is used with a range
of up to 26 pins. The number of available pins depends
on the particular device and its pin count. Pins that
support the peripheral pin select feature include the
designation “RPn” in their full pin designation, where
“RP” designates a remappable peripheral and “n” is the
remappable pin number.
FIGURE 11-2:
REMAPPABLE MUX
INPUT FOR U1RX
11.6.2
CONTROLLING PERIPHERAL PIN
SELECT
U1RXR<4:0>
Peripheral pin select features are controlled through
two sets of special function registers: one to map
peripheral inputs, and one to map outputs. Because
they are separately controlled, a particular peripheral’s
input and output (if the peripheral has both) can be
placed on any selectable function pin without
constraint.
0
RP0
RP1
RP2
1
U1RX input
to peripheral
2
The association of a peripheral to a peripheral select-
able pin is handled in two different ways, depending on
whether an input or output is being mapped.
25
RP 25
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 161
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 11-1: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1)
Configuration
Input Name
Function Name
Register
Bits
External Interrupt 1
INT1
INT2
RPINR0
RPINR1
INT1R<4:0>
INT2R<4:0>
T2CKR<4:0>
T3CKR<4:0>
T4CKR<4:0>
T5CKR<4:0>
IC1R<4:0>
External Interrupt 2
Timer2 External Clock
Timer3 External Clock
Timer4 External Clock
Timer5 External Clock
Input Capture 1
T2CK
T3CK
T4CK
T5CK
IC1
RPINR3
RPINR3
RPINR4
RPINR4
RPINR7
Input Capture 2
IC2
RPINR7
IC2R<4:0>
Input Capture 7
IC7
RPINR10
RPINR10
RPINR11
RPINR18
RPINR18
RPINR19
RPINR19
RPINR20
RPINR20
RPINR21
RPINR22
RPINR22
RPINR23
RPINR24
RPINR24
RPINR25
RPINR26
IC7R<4:0>
Input Capture 8
IC8
IC8R<4:0>
Output Compare Fault A
UART1 Receive
OCFA
U1RX
U1CTS
U2RX
U2CTS
SDI1
SCK1
SS1
OCFAR<4:0>
U1RXR<4:0>
U1CTSR<4:0>
U2RXR<4:0>
U2CTSR<4:0>
SDI1R<4:0>
SCK1R<4:0>
SS1R<4:0>
SDI2R<4:0>
SCK2R<4:0>
SS2R<4:0>
CSDIR<4:0>
CSCKR<4:0>
COFSR<4:0>
CIRXR<4:0>
UART1 Clear To Send
UART2 Receive
UART2 Clear To Send
SPI1 Data Input
SPI1 Clock Input
SPI1 Slave Select Input
SPI2 Data Input
SDI2
SCK2
SS2
SPI2 Clock Input
SPI2 Slave Select Input
DCI Serial Data Input
DCI Serial Clock Input
DCI Frame Sync Input
ECAN1 Receive
CSDI
CSCK
COFS
CIRX
Note 1: Unless otherwise noted, all inputs use Schmitt input buffers.
DS70292D-page 162
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
11.6.2.2
Output Mapping
FIGURE 11-3:
MULTIPLEXING OF
REMAPPABLE OUTPUT
FOR RPn
In contrast to inputs, the outputs of the peripheral pin
select options are mapped on the basis of the pin. In
this case, a control register associated with a particular
pin dictates the peripheral output to be mapped. The
RPORx registers are used to control output mapping.
Like the RPINRx registers, each register contains sets
of 5-bit fields, with each set associated with one RPn
pin (see Register 11-17 through Register 11-29). The
value of the bit field corresponds to one of the
peripherals, and that peripheral’s output is mapped to
the pin (see Table 11-2 and Figure 11-3).
RPnR<4:0>
default
0
3
4
U1TX Output enable
U1RTS Output enable
Output Enable
The list of peripherals for output mapping also includes
a null value of ‘00000’ because of the mapping
technique. This permits any given pin to remain
unconnected from the output of any of the pin
selectable peripherals.
OC4 Output
21
default
0
3
4
U1TX Output
U1RTS Output
RPn
Output Data
OC4 Output
21
TABLE 11-2: OUTPUT SELECTION FOR REMAPPABLE PIN (RPn)
Function
RPnR<4:0>
Output Name
RPn tied to default port pin
NULL
C1OUT
C2OUT
U1TX
U1RTS
U2TX
U2RTS
SDO1
SCK1
SS1
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10010
10011
10100
10101
RPn tied to Comparator1 Output
RPn tied to Comparator2 Output
RPn tied to UART1 Transmit
RPn tied to UART1 Ready To Send
RPn tied to UART2 Transmit
RPn tied to UART2 Ready To Send
RPn tied to SPI1 Data Output
RPn tied to SPI1 Clock Output
RPn tied to SPI1 Slave Select Output
RPn tied to SPI2 Data Output
RPn tied to SPI2 Clock Output
RPn tied to SPI2 Slave Select Output
RPn tied to DCI Serial Data Output
RPn tied to DCI Serial Clock Output
RPn tied to DCI Frame Sync Output
RPn tied to ECAN1 Transmit
SDO2
SCK2
SS2
CSDO
CSCK
COFS
C1TX
OC1
RPn tied to Output Compare 1
RPn tied to Output Compare 2
RPn tied to Output Compare 3
RPn tied to Output Compare 4
OC2
OC3
OC4
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Preliminary
DS70292D-page 163
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
11.6.3
CONTROLLING CONFIGURATION
CHANGES
11.6.3.2
Continuous State Monitoring
In addition to being protected from direct writes, the
contents of the RPINRx and RPORx registers are
constantly monitored in hardware by shadow registers.
If an unexpected change in any of the registers occurs
(such as cell disturbances caused by ESD or other
external events), a configuration mismatch Reset is
triggered.
Because peripheral remapping can be changed during
run time, some restrictions on peripheral remapping
are needed to prevent accidental configuration
changes. dsPIC33F devices include three features to
prevent alterations to the peripheral map:
• Control register lock sequence
• Continuous state monitoring
• Configuration bit pin select lock
11.6.3.3
Configuration Bit Pin Select Lock
As an additional level of safety, the device can be
configured to prevent more than one write session to
the RPINRx and RPORx registers. The IOL1WAY
(FOSC<IOL1WAY>) configuration bit blocks the
IOLOCK bit from being cleared after it has been set
once. If IOLOCK remains set, the register unlock
procedure does not execute, and the peripheral pin
select control registers cannot be written to. The only
way to clear the bit and re-enable peripheral remapping
is to perform a device Reset.
11.6.3.1
Control Register Lock
Under normal operation, writes to the RPINRx and
RPORx registers are not allowed. Attempted writes
appear to execute normally, but the contents of the reg-
isters remain unchanged. To change these registers,
they must be unlocked in hardware. The register lock is
controlled by the IOLOCK bit (OSCCON<6>). Setting
IOLOCK prevents writes to the control registers;
clearing IOLOCK allows writes.
In the default (unprogrammed) state, IOL1WAY is set,
restricting users to one write session. Programming
IOL1WAY allows user applications unlimited access
(with the proper use of the unlock sequence) to the
peripheral pin select registers.
To set or clear IOLOCK, a specific command sequence
must be executed:
1. Write 0x46 to OSCCON<7:0>.
2. Write 0x57 to OSCCON<7:0>.
3. Clear (or set) IOLOCK as a single operation.
Note:
MPLAB® C30 provides built-in C language
functions for unlocking the OSCCON
register:
__builtin_write_OSCCONL(value)
__builtin_write_OSCCONH(value)
See MPLAB Help for more information.
Unlike the similar sequence with the oscillator’s LOCK
bit, IOLOCK remains in one state until changed. This
allows all of the peripheral pin selects to be configured
with a single unlock sequence followed by an update to
all control registers, then locked with a second lock
sequence.
DS70292D-page 164
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
11.7 Peripheral Pin Select Registers
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 family of devices
implement 33 registers for remappable peripheral
configuration:
• 16 Input Remappable Peripheral Registers:
- RPINR0-RPINR1, RPINR3-RPINR4,
RPINR7, RPINR10-RPINR11 and
PRINR18-RPINR26
• 13 Output Remappable Peripheral Registers:
- RPOR0-RPOR12
Note:
Input and Output Register values can only
be changed if the IOLOCK bit
(OSCCON<6>) is set to ‘0’. See
Section 11.6.3.1 “Control Register
Lock” for a specific command sequence.
REGISTER 11-1: RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT1R<4:0>
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
INT1R<4:0>: Assign External Interrupt 1 (INTR1) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-0
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 165
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
INT2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
INT2R<4:0>: Assign External Interrupt 2 (INTR2) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 166
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-3: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
T3CKR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
T2CKR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
T3CKR<4:0>: Assign Timer3 External Clock (T3CK) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
T2CKR<4:0>: Assign Timer2 External Clock (T2CK) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 167
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-4: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
T5CKR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
T4CKR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
T5CKR<4:0>: Assign Timer5 External Clock (T5CK) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
T4CKR<4:0>: Assign Timer4 External Clock (T4CK) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 168
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-5: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
IC2R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
IC1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
IC2R<4:0>: Assign Input Capture 2 (IC2) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
IC1R<4:0>: Assign Input Capture 1 (IC1) to the corresponding RPn pin
11111= Input tied to VSS
11001 = Input tied to RP25.
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 169
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-6: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
IC8R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
IC7R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
IC8R<4:0>: Assign Input Capture 8 (IC8) to the corresponding pin RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
IC7R<4:0>: Assign Input Capture 7 (IC7) to the corresponding pin RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 170
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-7: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
OCFAR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
OCFAR<4:0>: Assign Output Compare A (OCFA) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 171
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-8: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
U1CTSR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
U1RXR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
U1CTSR<4:0>: Assign UART1 Clear to Send (U1CTS) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
U1RXR<4:0>: Assign UART1 Receive (U1RX) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 172
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-9: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
U2CTSR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
U2RXR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
U2CTSR<4:0>: Assign UART2 Clear to Send (U2CTS) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
U2RXR<4:0>: Assign UART2 Receive (U2RX) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 173
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-10: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
SCK1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
SDI1R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
SCK1R<4:0>: Assign SPI1 Clock Input (SCK1) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
SDI1R<4:0>: Assign SPI1 Data Input (SDI1) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 174
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-11: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
SS1R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
SS1R<4:0>: Assign SPI1 Slave Select Input (SS1) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 175
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-12: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
SCK2R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
SDI2R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
SCK2R<4:0>: Assign SPI2 Clock Input (SCK2) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
SDI2R<4:0>: Assign SPI2 Data Input (SDI2) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 176
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-13: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
SS2R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
SS2R<4:0>: Assign SPI2 Slave Select Input (SS2) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 177
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-14: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 8
R/W-1
CSCKR<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
CSDIR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
CSCKR<4:0>: Assign DCI Serial Clock Input (CSCK) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
bit 4-0
CSDIR<4:0>: Assign DCI Serial Data Input (CSDI) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
DS70292D-page 178
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-15: RPINR25: PERIPHERAL PIN SELECT INPUT REGISTER 25
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
bit 0
COFSR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
COFSR<4:0>: Assign DCI Frame Sync Input (COFS) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
REGISTER 11-16: RPINR26: PERIPHERAL PIN SELECT INPUT REGISTER 26(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-1
bit 0
U-0
—
U-0
—
U-0
—
R/W-1
R/W-1
R/W-1
R/W-1
C1RXR<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
C1RXR<4:0>: Assign ECAN1Receive (C1RX) to the corresponding RPn pin
11111= Input tied to VSS
11001= Input tied to RP25
•
•
•
00001= Input tied to RP1
00000= Input tied to RP0
Note 1: This register is disabled on devices without ECAN™ module.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 179
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-17: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP1R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP0R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP1R<4:0>: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP0R<4:0>: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-18: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP3R<4:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP2R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP3R<4:0>: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP2R<4:0>: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 11-2 for
peripheral function numbers)
DS70292D-page 180
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-19: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP5R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP4R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP5R<4:0>: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP4R<4:0>: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-20: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP7R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP6R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP7R<4:0>: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP6R<4:0>: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 11-2 for
peripheral function numbers)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 181
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-21: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP9R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP8R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP9R<4:0>: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP8R<4:0>: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-22: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP11R<4:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
RP10R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP11R<4:0>: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP10R<4:0>: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 11-2 for
peripheral function numbers)
DS70292D-page 182
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-23: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP13R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP12R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP13R<4:0>: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP12R<4:0>: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 11-2 for
peripheral function numbers)
REGISTER 11-24: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP15R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP14R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP15R<4:0>: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP14R<4:0>: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 11-2 for
peripheral function numbers)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 183
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-25: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP17R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP16R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP17R<4:0>: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP16R<4:0>: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 11-2 for
peripheral function numbers)
Note 1: This register is implemented in 44-pin devices only.
REGISTER 11-26: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RP19R<4:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP18R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP19R<4:0>: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP18R<4:0>: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 11-2 for
peripheral function numbers)
Note 1: This register is implemented in 44-pin devices only.
DS70292D-page 184
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-27: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP21R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP20R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP21R<4:0>: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP20R<4:0>: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 11-2 for
peripheral function numbers)
Note 1: This register is implemented in 44-pin devices only.
REGISTER 11-28: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
RP23R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
RP22R<4:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP23R<4:0>: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP22R<4:0>: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 11-2 for
peripheral function numbers)
Note 1: This register is implemented in 44-pin devices only.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 185
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 11-29: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12(1)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
RP25R<4:0>
bit 15
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
RP24R<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
RP25R<4:0>: Peripheral Output Function is Assigned to RP25 Output Pin bits (see Table 11-2 for
peripheral function numbers)
bit 7-5
bit 4-0
Unimplemented: Read as ‘0’
RP24R<4:0>: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 11-2 for
peripheral function numbers)
Note 1: This register is implemented in 44-pin devices only.
DS70292D-page 186
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The unique features of Timer1 allow it to be used for
Real-Time Clock (RTC) applications. A block diagram
12.0 TIMER1
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
of Timer1 is shown in Figure 12-1.
The Timer1 module can operate in one of the following
modes:
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 11. Timers” (DS70205)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
• Asynchronous Counter mode
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous and Asynchronous Counter modes,
the input clock is derived from the external clock input
at the T1CK pin.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Timer modes are determined by the following bits:
• Timer Clock Source Control bit (TCS): T1CON<1>
• Timer Synchronization Control bit (TSYNC):
T1CON<2>
The Timer1 module is a 16-bit timer, which can serve
as the time counter for the real-time clock, or operate
as a free-running interval timer/counter.
• Timer Gate Control bit (TGATE): T1CON<6>
Timer control bit setting for different operating modes
are given in the Table 12-1.
The Timer1 module has the following unique features
over other timers:
TABLE 12-1: TIMER MODE SETTINGS
• Can be operated from the low power 32 kHz
crystal oscillator available on the device
Mode
Timer
TCS
TGATE
TSYNC
• Can be operated in Asynchronous Counter mode
from an external clock source.
0
0
1
0
1
x
x
x
1
Gated timer
• The external clock input (T1CK) can optionally be
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler.
Synchronous
counter
Asynchronous
counter
1
x
0
FIGURE 12-1:
16-BIT TIMER1 MODULE BLOCK DIAGRAM
Falling Edge
Gate
Sync
1
0
Detect
Set T1IF flag
FCY
10
Prescaler
(/n)
TGATE
Reset
Equal
TMR1
00
x1
TCKPS<1:0>
1
0
SOSCO/
T1CK
Prescaler
(/n)
Comparator
PR1
Sync
TGATE
TCS
TSYNC
TCKPS<1:0>
SOSCI
LPOSCEN(1)
Note 1: Refer to Section 9.0 “Oscillator Configuration” for information on enabling the secondary oscillator.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 187
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 12-1: T1CON: TIMER1 CONTROL REGISTER
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
TSYNC
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timer1 On bit
1= Starts 16-bit Timer1
0= Stops 16-bit Timer1
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timer1 Gated Time Accumulation Enable bit
When T1CS = 1:
This bit is ignored.
When T1CS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timer1 Input Clock Prescale Select bits
11 = 1:256
10 = 1:64
01 = 1:8
00 = 1:1
bit 3
bit 2
Unimplemented: Read as ‘0’
TSYNC: Timer1 External Clock Input Synchronization Select bit
When TCS = 1:
1= Synchronize external clock input
0= Do not synchronize external clock input
When TCS = 0:
This bit is ignored.
bit 1
bit 0
TCS: Timer1 Clock Source Select bit
1= External clock from pin T1CK (on the rising edge)
0= Internal clock (FCY)
Unimplemented: Read as ‘0’
DS70292D-page 188
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
• A Type B timer can be concatenated with a Type
C timer to form a 32-bit timer
13.0 TIMER2/3 AND TIMER4/5
FEATURE
• The external clock input (TxCK) is always
synchronized to the internal device clock and the
clock synchronization is performed after the
prescaler.
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 11. Timers” (DS70205)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
A block diagram of the Type B timer is shown in
Figure 13-1.
Timer3 and Timer5 are Type C timers with the following
specific features:
• A Type C timer can be concatenated with a Type
B timer to form a 32-bit timer
• At least one Type C timer has the ability to trigger
an A/D conversion.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• The external clock input (TxCK) is always syn-
chronized to the internal device clock and the
clock synchronization is performed before the
prescaler
A block diagram of the Type C timer is shown in
Figure 13-2.
Timer2 and Timer4 are Type B timers with the following
specific features:
FIGURE 13-1:
TYPE B TIMER BLOCK DIAGRAM (x = 2 or 4)
Falling Edge
Detect
Gate
Sync
1
Set TxIF flag
0
FCY
10
Prescaler
(/n)
Reset
00
x1
TMRx
Comparator
PRx
TGATE
TCKPS<1:0>
Sync
Prescaler
(/n)
Equal
TxCK
TCKPS<1:0>
TGATE
TCS
FIGURE 13-2:
TYPE C TIMER BLOCK DIAGRAM (x = 3 or 5)
Falling Edge
Detect
Gate
Sync
1
Set TxIF flag
0
Prescaler
(/n)
10
00
x1
FCY
Reset
Equal
TMRx
TGATE
TCKPS<1:0>
Prescaler
(/n)
Sync
ADC SOC Trigger
Comparator
TxCK
TCKPS<1:0>
TGATE
TCS
PRx
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 189
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The Timer2/3 and Timer4/5 modules can operate in
one of the following modes:
For interrupt control, the combined 32-bit timer uses
the interrupt enable, interrupt flag and interrupt priority
control bits of the Type C timer. The interrupt control
and status bits for the Type B timer are ignored during
32-bit timer operation.
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
The Type B and Type C timers that can be combined to
form a 32-bit timer are listed in Table 13-2.
In Timer and Gated Timer modes, the input clock is
derived from the internal instruction cycle clock (FCY).
In Synchronous Counter mode, the input clock is
derived from the external clock input at TxCK pin.
TABLE 13-2: 32-BIT TIMER
TYPE B Timer (lsw)
TYPE C Timer (msw)
The timer modes are determined by the following bits:
Timer2
Timer4
Timer3
Timer5
• TCS (TxCON<1>): Timer Clock Source Control bit
• TGATE (TxCON<6>): Timer Gate Control bit
Timer control bit settings for different operating modes
are given in the Table 13-1.
A block diagram representation of the 32-bit timer mod-
ule is shown in Figure 13-3. The 32-bit timer module
can operate in one of the following modes:
TABLE 13-1: TIMER MODE SETTINGS
• Timer mode
• Gated Timer mode
• Synchronous Counter mode
Mode
TCS
TGATE
Timer
0
0
1
0
1
x
To configure the features of Timer2/3 or Timer4/5 for
32-bit operation:
Gated timer
Synchronous coun-
ter
1. Set the T32 control bit.
2. Select the prescaler ratio for Timer2 or Timer4
using the TCKPS<1:0> bits.
13.1 16-Bit Operation
3. Set the Clock and Gating modes using the
corresponding TCS and TGATE bits.
To configure any of the timers for individual 16-bit
operation:
4. Load the timer period value. PR3 or PR5 con-
tains the most significant word of the value,
while PR2 or PR4 contains the least significant
word.
1. Clear the T32 bit corresponding to that timer.
2. Select the timer prescaler ratio using the
TCKPS<1:0> bits.
5. If interrupts are required, set the interrupt enable
bits, T3IE or T5IE. Use the priority bits,
T3IP<2:0> or T5IP<2:0> to set the interrupt pri-
ority. While Timer2 or Timer4 controls the timer,
the interrupt appears as a Timer3 or Timer5
interrupt.
3. Set the Clock and Gating modes using the TCS
and TGATE bits.
4. Load the timer period value into the PRx
register.
5. If interrupts are required, set the interrupt enable
bit, TxIE. Use the priority bits, TxIP<2:0>, to set
the interrupt priority.
6. Set the corresponding TON bit.
The timer value at any point is stored in the register
pair, TMR3:TMR2 or TMR5:TMR4, which always
contains the most significant word of the count, while
TMR2 or TMR4 contains the least significant word.
6. Set the TON bit.
Note:
Only Timer2 and Timer3 can trigger a
DMA data transfer.
13.2 32-Bit Operation
A 32-bit timer module can be formed by combining a
Type B and a Type C 16-bit timer module. For 32-bit
timer operation, the T32 control bit in the Type B Timer
Control (TxCON<3>) register must be set. The Type C
timer holds the most significant word (msw) and the
Type B timer holds the least significant word (lsw) for
32-bit operation.
When configured for 32-bit operation, only the Type B
Timer Control (TxCON) register bits are required for
setup and control. Type C timer control register bits are
ignored (except TSIDL bit).
DS70292D-page 190
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 13-3:
32-BIT TIMER BLOCK DIAGRAM
Falling Edge
Detect
Gate
Sync
1
0
Set TyIF
Flag
PRy
PRx
Equal
Reset
Comparator
TGATE
Prescaler
(/n)
10
00
x1
FCY
lsw
TMRx
msw
ADC SOC trigger
TMRy
TCKPS<1:0>
Sync
Prescaler
(/n)
TxCK
TMRyHLD
TGATE
TCS
TCKPS<1:0>
Data Bus <15:0>
Note 1: ADC trigger is available only on TMR3:TMR2 and TMR5:TMR2 32-bit timers
2: Timer x is a Type B Timer (x = 2 and 4)
3: Timer y is a Type C Timer (y = 3 and 5)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 191
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 13-1: TxCON: TIMER CONTROL REGISTER (x = 2 or 4, y = 3 or 5)
R/W-0
TON
U-0
—
R/W-0
TSIDL
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
T32
U-0
—
R/W-0
TCS
U-0
—
TGATE
TCKPS<1:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timerx On bit
When T32 = 1 (in 32-bit Timer mode):
1= Starts 32-bit TMRx:TMRy timer pair
0= Stops 32-bit TMRx:TMRy timer pair
When T32 = 0 (in 16-bit Timer mode):
1= Starts 16-bit timer
0= Stops 16-bit timer
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit
1= Discontinue timer operation when device enters Idle mode
0= Continue timer operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
bit 3
TCKPS<1:0>: Timerx Input Clock Prescale Select bits
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
T32: 32-bit Timerx Mode Select bit
1= TMRx and TMRy form a 32-bit timer
0= TMRx and TMRy form separate 16-bit timer
bit 2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit
1= External clock from TxCK pin
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
DS70292D-page 192
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 13-2: TxCON: TIMER CONTROL REGISTER (x = 3 OR 5)
R/W-0
TON(2)
U-0
—
R/W-0
TSIDL(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
R/W-0
TGATE(2)
R/W-0
TCKPS<1:0>(2)
R/W-0
U-0
—
U-0
—
R/W-0
TCS(2)
U-0
—
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
TON: Timery On bit(2)
1= Starts 16-bit Timerx
0= Stops 16-bit Timerx
bit 14
bit 13
Unimplemented: Read as ‘0’
TSIDL: Stop in Idle Mode bit(1)
1= Discontinue timer operation when device enters Idle mode
0= Continue timer operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
TGATE: Timerx Gated Time Accumulation Enable bit(2)
When TCS = 1:
This bit is ignored.
When TCS = 0:
1= Gated time accumulation enabled
0= Gated time accumulation disabled
bit 5-4
TCKPS<1:0>: Timerx Input Clock Prescale Select bits(2)
11= 1:256 prescale value
10= 1:64 prescale value
01= 1:8 prescale value
00= 1:1 prescale value
bit 3-2
bit 1
Unimplemented: Read as ‘0’
TCS: Timerx Clock Source Select bit(2)
1= External clock from TxCK pin
0= Internal clock (FOSC/2)
bit 0
Unimplemented: Read as ‘0’
Note 1: When 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, the TSIDL bit
must be cleared to operate the 32-bit timer in Idle mode.
2: When the 32-bit timer operation is enabled (T32 = 1) in the Timer Control (TxCON<3>) register, these bits
have no effect.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 193
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 194
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
- Capture timer value on every falling edge of
input at ICx pin
14.0 INPUT CAPTURE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
- Capture timer value on every rising edge of
input at ICx pin
2. Capture timer value on every edge (rising and
falling)
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 12. Input Capture”
(DS70198) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
3. Prescaler Capture Event modes:
- Capture timer value on every 4th rising edge
of input at ICx pin
- Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of two 16-
bit timers (Timer2 or Timer3) for the time base. The
selected timer can use either an internal or external
clock.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices support
up to four input capture channels.
• 4-word FIFO buffer for capture values
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of input capture to provide additional sources
of external interrupts
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
at the ICx pin. The events that cause a capture event
are listed below in three categories:
Note:
Only IC1 and IC2 can trigger a DMA data
transfer. If DMA data transfers are
required, the FIFO buffer size must be set
to ‘1’ (ICI<1:0> = 00)
1. Simple Capture Event modes:
FIGURE 14-1:
INPUT CAPTURE BLOCK DIAGRAM
ICM<2:0>
Prescaler Mode
(16th Rising Edge)
101
TMR2 TMR3
Prescaler Mode
(4th Rising Edge)
100
ICTMR
Rising Edge Mode
Falling Edge Mode
To CPU
ICx pin
011
010
CaptureEvent
FIFO CONTROL
ICxBUF
FIFO
Edge Detection
Mode
ICI<1:0>
/N
ICM<2:0>
001
Set Flag ICxIF
(In IFSx Register)
Sleep/Idle
Wake-up Mode
001
111
Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 195
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
14.1 Input Capture Registers
REGISTER 14-1: ICxCON: INPUT CAPTURE x CONTROL REGISTER (x = 1, 2, 7 OR 8)
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
ICSIDL
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-0, HC
ICOV
R-0, HC
ICBNE
R/W-0
R/W-0
R/W-0
bit 0
ICTMR
ICI<1:0>
ICM<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
ICSIDL: Input Capture Module Stop in Idle Control bit
1= Input capture module halts in CPU Idle mode
0= Input capture module continues to operate in CPU Idle mode
bit 12-8
bit 7
Unimplemented: Read as ‘0’
ICTMR: Input Capture Timer Select bits
1= TMR2 contents are captured on capture event
0= TMR3 contents are captured on capture event
bit 6-5
ICI<1:0>: Select Number of Captures per Interrupt bits
11= Interrupt on every fourth capture event
10= Interrupt on every third capture event
01= Interrupt on every second capture event
00= Interrupt on every capture event
bit 4
ICOV: Input Capture Overflow Status Flag bit (read-only)
1= Input capture overflow occurred
0= No input capture overflow occurred
bit 3
ICBNE: Input Capture Buffer Empty Status bit (read-only)
1= Input capture buffer is not empty, at least one more capture value can be read
0= Input capture buffer is empty
bit 2-0
ICM<2:0>: Input Capture Mode Select bits
111= Input capture functions as interrupt pin only when device is in Sleep or Idle mode
(Rising edge detect only, all other control bits are not applicable.)
110= Unused (module disabled)
101= Capture mode, every 16th rising edge
100= Capture mode, every 4th rising edge
011= Capture mode, every rising edge
010= Capture mode, every falling edge
001= Capture mode, every edge (rising and falling)
(ICI<1:0> bits do not control interrupt generation for this mode.)
000= Input capture module turned off
DS70292D-page 196
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The Output Compare module can select either Timer2
or Timer3 for its time base. The module compares the
15.0 OUTPUT COMPARE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
value of the timer with the value of one or two compare
registers depending on the operating mode selected.
The state of the output pin changes when the timer
value matches the compare register value. The Output
Compare module generates either a single output
pulse or a sequence of output pulses, by changing the
state of the output pin on the compare match events.
The Output Compare module can also generate inter-
rupts on compare match events.
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 13. Output Compare”
(DS70209) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
The Output Compare module has multiple operating
modes:
• Active-Low One-Shot mode
• Active-High One-Shot mode
• Toggle mode
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Delayed One-Shot mode
• Continuous Pulse mode
• PWM mode without fault protection
• PWM mode with fault protection
FIGURE 15-1:
OUTPUT COMPARE MODULE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Output
Logic
S
R
Q
OCx
Output Enable
3
OCM<2:0>
Mode Select
OCFA
Comparator
0
1
0
OCTSEL
1
16
16
TMR2
Rollover
TMR3
Rollover
TMR3
TMR2
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 197
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
15.1 Output Compare Modes
Note 1: Only OC1 and OC2 can trigger a DMA
data transfer.
Configure the Output Compare modes by setting the
appropriate Output Compare Mode (OCM<2:0>) bits in
the Output Compare Control (OCxCON<2:0>) register.
Table 15-1 lists the different bit settings for the Output
Compare modes. Figure 15-2 illustrates the output
compare operation for various modes. The user appli-
cation must disable the associated timer when writing
to the output compare control registers to avoid mal-
functions.
2: See Section 13. “Output Compare” in
the “dsPIC33F/PIC24H Family Reference
Manual” (DS70209) for OCxR and
OCxRS register restrictions.
TABLE 15-1: OUTPUT COMPARE MODES
OCM<2:0>
Mode
Module Disabled
OCx Pin Initial State
OCx Interrupt Generation
000
001
010
011
100
101
110
Controlled by GPIO register
—
Active-Low One-Shot
Active-High One-Shot
Toggle Mode
0
1
OCx Rising edge
OCx Falling edge
Current output is maintained OCx Rising and Falling edge
Delayed One-Shot
Continuous Pulse mode
0
0
OCx Falling edge
OCx Falling edge
No interrupt
PWM mode without fault
protection
0, if OCxR is zero
1, if OCxR is non-zero
111
PWM mode with fault protection 0, if OCxR is zero
1, if OCxR is non-zero
OCFA Falling edge for OC1 to OC4
FIGURE 15-2:
OUTPUT COMPARE OPERATION
Output Compare
Mode enabled
Timer is reset on
period match
OCxRS
OCxR
TMRy
Active-Low One-Shot
(OCM = 001)
Active-High One-Shot
(OCM = 010)
Toggle Mode
(OCM = 011)
Delayed One-Shot
(OCM = 100)
Continuous Pulse Mode
(OCM = 101)
PWM Mode
(OCM = 110or 111)
DS70292D-page 198
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 15-1: OCxCON: OUTPUT COMPARE x CONTROL REGISTER (x = 1, 2, 3 OR 4)
U-0
—
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
OCSIDL
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R-0 HC
OCFLT
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
OCTSEL
OCM<2:0>
bit 7
Legend:
HC = Cleared in Hardware
W = Writable bit
HS = Set in Hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15-14
bit 13
Unimplemented: Read as ‘0’
OCSIDL: Stop Output Compare in Idle Mode Control bit
1= Output Compare x halts in CPU Idle mode
0= Output Compare x continues to operate in CPU Idle mode
bit 12-5
bit 4
Unimplemented: Read as ‘0’
OCFLT: PWM Fault Condition Status bit
1= PWM Fault condition has occurred (cleared in hardware only)
0= No PWM Fault condition has occurred
(This bit is only used when OCM<2:0> = 111.)
bit 3
OCTSEL: Output Compare Timer Select bit
1= Timer3 is the clock source for Compare x
0= Timer2 is the clock source for Compare x
bit 2-0
OCM<2:0>: Output Compare Mode Select bits
111= PWM mode on OCx, Fault pin enabled
110= PWM mode on OCx, Fault pin disabled
101= Initialize OCx pin low, generate continuous output pulses on OCx pin
100= Initialize OCx pin low, generate single output pulse on OCx pin
011= Compare event toggles OCx pin
010= Initialize OCx pin high, compare event forces OCx pin low
001= Initialize OCx pin low, compare event forces OCx pin high
000= Output compare channel is disabled
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 199
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 200
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The Serial Peripheral Interface (SPI) module is a syn-
16.0 SERIAL PERIPHERAL
chronous serial interface useful for communicating with
INTERFACE (SPI)
other peripheral or microcontroller devices. These
peripheral devices can be serial EEPROMs, shift regis-
ters, display drivers, analog-to-digital converters, etc.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
The SPI module is compatible with SPI and SIOP from
dsPIC33FJ64GPX02/X04,
Motorola®.
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 18. Serial Peripheral
Interface (SPI)” (DS70206) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
Each SPI module consists of a 16-bit shift register,
SPIxSR (where x = 1 or 2), used for shifting data in and
out, and a buffer register, SPIxBUF. A control register,
SPIxCON, configures the module. Additionally, a status
register, SPIxSTAT, indicates status conditions.
The serial interface consists of 4 pins:
• SDIx (serial data input)
• SDOx (serial data output)
• SCKx (shift clock input or output)
• SSx (active-low slave select).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
In Master mode operation, SCK is a clock output. In
Slave mode, it is a clock input.
FIGURE 16-1:
SPI MODULE BLOCK DIAGRAM
SCKx
SSx
1:1 to 1:8
Secondary
Prescaler
1:1/4/16/64
Primary
Prescaler
FCY
Sync
Control
Select
Edge
Control
Clock
SPIxCON1<1:0>
SPIxCON1<4:2>
Shift Control
SDOx
SDIx
Enable
Master Clock
bit 0
SPIxSR
Transfer
Transfer
SPIxRXB SPIxTXB
SPIxBUF
Write SPIxBUF
Read SPIxBUF
16
Internal Data Bus
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 201
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 16-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER
R/W-0
SPIEN
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
SPISIDL
bit 15
bit 8
U-0
—
R/C-0
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
SPIROV
SPITBF
SPIRBF
bit 0
bit 7
Legend:
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
SPIEN: SPIx Enable bit
1= Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
SPISIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-7
bit 6
Unimplemented: Read as ‘0’
SPIROV: Receive Overflow Flag bit
1= A new byte/word is completely received and discarded. The user software has not read the
previous data in the SPIxBUF register
0= No overflow has occurred
bit 5-2
bit 1
Unimplemented: Read as ‘0’
SPITBF: SPIx Transmit Buffer Full Status bit
1= Transmit not yet started, SPIxTXB is full
0= Transmit started, SPIxTXB is empty
Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
bit 0
SPIRBF: SPIx Receive Buffer Full Status bit
1= Receive complete, SPIxRXB is full
0= Receive is not complete, SPIxRXB is empty
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB.
DS70292D-page 202
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
SMP
R/W-0
CKE(1)
DISSCK
DISSDO
MODE16
bit 15
bit 8
R/W-0
SSEN(3)
R/W-0
CKP
R/W-0
R/W-0
R/W-0
SPRE<2:0>(2)
R/W-0
R/W-0
R/W-0
MSTEN
PPRE<1:0>(2)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
DISSCK: Disable SCKx pin bit (SPI Master modes only)
1= Internal SPI clock is disabled, pin functions as I/O
0= Internal SPI clock is enabled
bit 11
bit 10
bit 9
DISSDO: Disable SDOx pin bit
1= SDOx pin is not used by module; pin functions as I/O
0= SDOx pin is controlled by the module
MODE16: Word/Byte Communication Select bit
1= Communication is word-wide (16 bits)
0= Communication is byte-wide (8 bits)
SMP: SPIx Data Input Sample Phase bit
Master mode:
1= Input data sampled at end of data output time
0= Input data sampled at middle of data output time
Slave mode:
SMP must be cleared when SPIx is used in Slave mode.
bit 8
bit 7
bit 6
bit 5
CKE: SPIx Clock Edge Select bit(1)
1= Serial output data changes on transition from active clock state to Idle clock state (see bit 6)
0= Serial output data changes on transition from Idle clock state to active clock state (see bit 6)
SSEN: Slave Select Enable bit (Slave mode)(3)
1= SSx pin used for Slave mode
0= SSx pin not used by module. Pin controlled by port function
CKP: Clock Polarity Select bit
1= Idle state for clock is a high level; active state is a low level
0= Idle state for clock is a low level; active state is a high level
MSTEN: Master Mode Enable bit
1= Master mode
0= Slave mode
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: Do not set both Primary and Secondary prescalers to the value of 1:1.
3: This bit must be cleared when FRMEN = 1.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 203
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 16-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED)
bit 4-2
SPRE<2:0>: Secondary Prescale bits (Master mode)(2)
111= Secondary prescale 1:1
110= Secondary prescale 2:1
•
•
•
000= Secondary prescale 8:1
bit 1-0
PPRE<1:0>: Primary Prescale bits (Master mode)(2)
11= Primary prescale 1:1
10= Primary prescale 4:1
01= Primary prescale 16:1
00= Primary prescale 64:1
Note 1: The CKE bit is not used in the Framed SPI modes. Program this bit to ‘0’ for the Framed SPI modes
(FRMEN = 1).
2: Do not set both Primary and Secondary prescalers to the value of 1:1.
3: This bit must be cleared when FRMEN = 1.
DS70292D-page 204
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 16-3: SPIxCON2: SPIx CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
FRMEN
SPIFSD
FRMPOL
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
U-0
—
FRMDLY
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
bit 13
FRMEN: Framed SPIx Support bit
1= Framed SPIx support enabled (SSx pin used as frame sync pulse input/output)
0= Framed SPIx support disabled
SPIFSD: Frame Sync Pulse Direction Control bit
1= Frame sync pulse input (slave)
0= Frame sync pulse output (master)
FRMPOL: Frame Sync Pulse Polarity bit
1= Frame sync pulse is active-high
0= Frame sync pulse is active-low
bit 12-2
bit 1
Unimplemented: Read as ‘0’
FRMDLY: Frame Sync Pulse Edge Select bit
1= Frame sync pulse coincides with first bit clock
0= Frame sync pulse precedes first bit clock
bit 0
Unimplemented: Read as ‘0’
This bit must not be set to ‘1’ by the user application.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 205
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 206
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
17.1 Operating Modes
17.0 INTER-INTEGRATED
2
CIRCUIT™ (I C™)
The hardware fully implements all the master and slave
functions of the I2C Standard and Fast mode
specifications, as well as 7 and 10-bit addressing.
The I2C module can operate either as a slave or a
master on an I2C bus.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 19. Inter-Integrated
Circuit™ (I2C™)” (DS70195) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
The following types of I2C operation are supported:
• I2C slave operation with 7-bit address
• I2C slave operation with 10-bit address
• I2C master operation with 7- or 10-bit address
For details about the communication sequence in each
of these modes, refer to the “dsPIC33F/PIC24H Family
Reference Manual”. Please see the Microchip website
(www.microchip.com) for the latest dsPIC33F Family
Reference Manual chapters.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
2
17.2 I C Registers
I2CxCON and I2CxSTAT are control and status
registers, respectively. The I2CxCON register is
readable and writable. The lower six bits of I2CxSTAT
are read-only. The remaining bits of the I2CSTAT are
read/write:
The Inter-Integrated Circuit (I2C) module provides
complete hardware support for both Slave and Multi-
Master modes of the I2C serial communication
standard, with a 16-bit interface.
• I2CxRSR is the shift register used for shifting data
internal to the module and the user application
has no access to it.
The I2C module has a 2-pin interface:
• The SCLx pin is clock.
• The SDAx pin is data.
The I2C module offers the following key features:
• I2C interface supporting both Master and Slave
modes of operation.
• I2C Slave mode supports 7 and 10-bit address.
• I2C Master mode supports 7 and 10-bit address.
• I2C Port allows bidirectional transfers between
master and slaves.
• Serial clock synchronization for I2C port can be
used as a handshake mechanism to suspend and
resume serial transfer (SCLREL control).
• I2C supports multi-master operation, detects bus
collision and arbitrates accordingly.
• I2CxRCV is the receive buffer and the register to
which data bytes are written, or from which data
bytes are read.
• I2CxTRN is the transmit register to which bytes
are written during a transmit operation.
• The I2CxADD register holds the slave address.
• A status bit, ADD10, indicates 10-bit Address
mode.
• The I2CxBRG acts as the Baud Rate Generator
(BRG) reload value.
In receive operations, I2CxRSR and I2CxRCV together
form a double-buffered receiver. When I2CxRSR
receives a complete byte, it is transferred to I2CxRCV,
and an interrupt pulse is generated.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 207
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 17-1:
I2C™ BLOCK DIAGRAM (X = 1)
Internal
Data Bus
I2CxRCV
Read
Shift
Clock
SCLx
SDAx
I2CxRSR
LSb
Address Match
Write
Read
Match Detect
I2CxMSK
Write
Read
I2CxADD
Start and Stop
Bit Detect
Write
Start and Stop
Bit Generation
I2CxSTAT
I2CxCON
Read
Write
Collision
Detect
Acknowledge
Generation
Read
Clock
Stretching
Write
Read
I2CxTRN
LSb
Shift Clock
Reload
Control
Write
Read
BRG Down Counter
TCY/2
I2CxBRG
DS70292D-page 208
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER
R/W-0
I2CEN
U-0
—
R/W-0
R/W-1 HC
SCLREL
R/W-0
R/W-0
A10M
R/W-0
R/W-0
SMEN
I2CSIDL
IPMIEN
DISSLW
bit 15
bit 8
R/W-0
GCEN
R/W-0
R/W-0
R/W-0 HC
ACKEN
R/W-0 HC
RCEN
R/W-0 HC
PEN
R/W-0 HC
RSEN
R/W-0 HC
SEN
STREN
ACKDT
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HC = Cleared in hardware
x = Bit is unknown
bit 15
I2CEN: I2Cx Enable bit
1= Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins
0= Disables the I2Cx module. All I2C™ pins are controlled by port functions
bit 14
bit 13
Unimplemented: Read as ‘0’
I2CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters an Idle mode
0= Continue module operation in Idle mode
bit 12
SCLREL: SCLx Release Control bit (when operating as I2C slave)
1= Release SCLx clock
0= Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear
at beginning of slave transmission. Hardware clear at end of slave reception.
If STREN = 0:
Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave
transmission.
bit 11
bit 10
bit 9
IPMIEN: Intelligent Peripheral Management Interface (IPMI) Enable bit
1= IPMI mode is enabled; all addresses Acknowledged
0= IPMI mode disabled
A10M: 10-bit Slave Address bit
1= I2CxADD is a 10-bit slave address
0= I2CxADD is a 7-bit slave address
DISSLW: Disable Slew Rate Control bit
1= Slew rate control disabled
0= Slew rate control enabled
bit 8
SMEN: SMbus Input Levels bit
1= Enable I/O pin thresholds compliant with SMbus specification
0= Disable SMbus input thresholds
bit 7
GCEN: General Call Enable bit (when operating as I2C slave)
1= Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0= General call address disabled
bit 6
STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1= Enable software or receive clock stretching
0= Disable software or receive clock stretching
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 209
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 17-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
bit 5
bit 4
ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an Acknowledge sequence.
1= Send NACK during Acknowledge
0= Send ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit
(when operating as I2C master, applicable during master receive)
1= Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence
0= Acknowledge sequence not in progress
bit 3
bit 2
bit 1
RCEN: Receive Enable bit (when operating as I2C master)
1= Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte
0= Receive sequence not in progress
PEN: Stop Condition Enable bit (when operating as I2C master)
1= Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence
0= Stop condition not in progress
RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1= Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of
master Repeated Start sequence
0= Repeated Start condition not in progress
bit 0
SEN: Start Condition Enable bit (when operating as I2C master)
1= Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence
0= Start condition not in progress
DS70292D-page 210
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER
R-0 HSC
R-0 HSC
TRSTAT
U-0
—
U-0
—
U-0
—
R/C-0 HS
BCL
R-0 HSC
GCSTAT
R-0 HSC
ADD10
ACKSTAT
bit 15
bit 8
R/C-0 HS
IWCOL
R/C-0 HS
I2COV
R-0 HSC
D_A
R/C-0 HSC R/C-0 HSC
R-0 HSC
R_W
R-0 HSC
RBF
R-0 HSC
TBF
P
S
bit 7
bit 0
Legend:
U = Unimplemented bit, read as ‘0’
C = Clear only bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
HS = Set in hardware
‘0’ = Bit is cleared
HSC = Hardware set/cleared
x = Bit is unknown
-n = Value at POR
bit 15
bit 14
ACKSTAT: Acknowledge Status bit
(when operating as I2C™ master, applicable to master transmit operation)
1= NACK received from slave
0= ACK received from slave
Hardware set or clear at end of slave Acknowledge.
TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
1= Master transmit is in progress (8 bits + ACK)
0= Master transmit is not in progress
Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge.
bit 13-11
bit 10
Unimplemented: Read as ‘0’
BCL: Master Bus Collision Detect bit
1= A bus collision has been detected during a master operation
0= No collision
Hardware set at detection of bus collision.
bit 9
bit 8
bit 7
bit 6
bit 5
bit 4
GCSTAT: General Call Status bit
1= General call address was received
0= General call address was not received
Hardware set when address matches general call address. Hardware clear at Stop detection.
ADD10: 10-Bit Address Status bit
1= 10-bit address was matched
0= 10-bit address was not matched
Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection.
IWCOL: Write Collision Detect bit
1= An attempt to write the I2CxTRN register failed because the I2C module is busy
0= No collision
Hardware set at occurrence of write to I2CxTRN while busy (cleared by software).
I2COV: Receive Overflow Flag bit
1= A byte was received while the I2CxRCV register is still holding the previous byte
0= No overflow
Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
D_A: Data/Address bit (when operating as I2C slave)
1= Indicates that the last byte received was data
0= Indicates that the last byte received was device address
Hardware clear at device address match. Hardware set by reception of slave byte.
P: Stop bit
1= Indicates that a Stop bit has been detected last
0= Stop bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 211
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 17-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED)
bit 3
bit 2
bit 1
S: Start bit
1= Indicates that a Start (or Repeated Start) bit has been detected last
0= Start bit was not detected last
Hardware set or clear when Start, Repeated Start or Stop detected.
R_W: Read/Write Information bit (when operating as I2C slave)
1= Read – indicates data transfer is output from slave
0= Write – indicates data transfer is input to slave
Hardware set or clear after reception of I2C device address byte.
RBF: Receive Buffer Full Status bit
1= Receive complete, I2CxRCV is full
0= Receive not complete, I2CxRCV is empty
Hardware set when I2CxRCV is written with received byte. Hardware clear when software
reads I2CxRCV.
bit 0
TBF: Transmit Buffer Full Status bit
1= Transmit in progress, I2CxTRN is full
0= Transmit complete, I2CxTRN is empty
Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission.
DS70292D-page 212
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 17-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
AMSK9
AMSK8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
AMSK7
AMSK6
AMSK5
AMSK4
AMSK3
AMSK2
AMSK1
AMSK0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9-0
Unimplemented: Read as ‘0’
AMSKx: Mask for Address Bit x Select bit
1= Enable masking for bit x of incoming message address; bit match not required in this position
0= Disable masking for bit x; bit match required in this position
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 213
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 214
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The primary features of the UART module are:
18.0 UNIVERSAL ASYNCHRONOUS
• Full-Duplex, 8- or 9-bit Data Transmission through
the UxTX and UxRX pins
RECEIVER TRANSMITTER
(UART)
• Even, Odd or No Parity Options (for 8-bit data)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
• One or two stop bits
• Hardware flow control option with UxCTS and
UxRTS pins
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 17. UART” (DS70188)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
• Fully integrated Baud Rate Generator with 16-bit
prescaler
• Baud rates ranging from 10 Mbps to 38 bps at 40
MIPS
• 4-deep First-In First-Out (FIFO) Transmit Data
buffer
• 4-deep FIFO Receive Data buffer
• Parity, framing and buffer overrun error detection
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Support for 9-bit mode with Address Detect
(9th bit = 1)
• Transmit and Receive interrupts
• A separate interrupt for all UART error conditions
• Loopback mode for diagnostic support
• Support for sync and break characters
• Support for automatic baud rate detection
• IrDA® encoder and decoder logic
The Universal Asynchronous Receiver Transmitter
(UART) module is one of the serial I/O modules
available
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 device family. The UART is full-duplex
in
the
dsPIC33FJ32GP302/304,
• 16x baud clock output for IrDA® support
a
asynchronous system that can communicate with
peripheral devices, such as personal computers, LIN,
RS-232 and RS-485 interfaces. The module also
supports a hardware flow control option with the
UxCTS and UxRTS pins and also includes an IrDA®
encoder and decoder.
A simplified block diagram of the UART module is
shown in Figure 18-1. The UART module consists of
these key hardware elements:
• Baud Rate Generator
• Asynchronous Transmitter
• Asynchronous Receiver
FIGURE 18-1:
UART SIMPLIFIED BLOCK DIAGRAM
Baud Rate Generator
IrDA®
BCLK
Hardware Flow Control
UART Receiver
UxRTS
UxCTS
UxRX
UxTX
UART Transmitter
Note 1: Both UART1 and UART2 can trigger a DMA data transfer.
2: If DMA transfers are required, the UART TX/RX FIFO buffer must be set to a size of 1 byte/word
(i.e., UTXISEL<1:0> = 00and URXISEL<1:0> = 00).
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 215
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 18-1: UxMODE: UARTx MODE REGISTER
R/W-0
UARTEN(1)
U-0
—
R/W-0
USIDL
R/W-0
IREN(2)
R/W-0
U-0
—
R/W-0
R/W-0
RTSMD
UEN<1:0>
bit 15
bit 8
R/W-0 HC
WAKE
R/W-0
R/W-0 HC
ABAUD
R/W-0
R/W-0
BRGH
R/W-0
R/W-0
R/W-0
LPBACK
URXINV
PDSEL<1:0>
STSEL
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15
UARTEN: UARTx Enable bit(1)
1= UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN<1:0>
0= UARTx is disabled; all UARTx pins are controlled by port latches; UARTx power consumption
minimal
bit 14
bit 13
Unimplemented: Read as ‘0’
USIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
bit 11
IREN: IrDA® Encoder and Decoder Enable bit(2)
1= IrDA® encoder and decoder enabled
0= IrDA® encoder and decoder disabled
RTSMD: Mode Selection for UxRTS Pin bit
1= UxRTS pin in Simplex mode
0= UxRTS pin in Flow Control mode
bit 10
Unimplemented: Read as ‘0’
UEN<1:0>: UARTx Enable bits
bit 9-8
11= UxTX, UxRX and BCLK pins are enabled and used; UxCTS pin controlled by port latches
10= UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01= UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by port latches
00= UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLK pins controlled by
port latches
bit 7
WAKE: Wake-up on Start bit Detect During Sleep Mode Enable bit
1= UARTx continues to sample the UxRX pin; interrupt generated on falling edge; bit cleared
in hardware on following rising edge
0= No wake-up enabled
bit 6
bit 5
LPBACK: UARTx Loopback Mode Select bit
1= Enable Loopback mode
0= Loopback mode is disabled
ABAUD: Auto-Baud Enable bit
1= Enable baud rate measurement on the next character – requires reception of a Sync field (55h)
before other data; cleared in hardware upon completion
0= Baud rate measurement disabled or completed
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
DS70292D-page 216
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 18-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 4
URXINV: Receive Polarity Inversion bit
1= UxRX Idle state is ‘0’
0= UxRX Idle state is ‘1’
bit 3
BRGH: High Baud Rate Enable bit
1= BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode)
0= BRG generates 16 clocks per bit period (16x baud clock, Standard mode)
bit 2-1
PDSEL<1:0>: Parity and Data Selection bits
11= 9-bit data, no parity
10= 8-bit data, odd parity
01= 8-bit data, even parity
00= 8-bit data, no parity
bit 0
STSEL: Stop Bit Selection bit
1= Two Stop bits
0= One Stop bit
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for receive or transmit operation.
2: This feature is only available for the 16x BRG mode (BRGH = 0).
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 217
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0 HC
UTXBRK
R/W-0
UTXEN(1)
R-0
R-1
UTXISEL1
UTXINV
UTXISEL0
UTXBF
TRMT
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R-1
R-0
R-0
R/C-0
R-0
URXISEL<1:0>
ADDEN
RIDLE
PERR
FERR
OERR
URXDA
bit 7
bit 0
Legend:
HC = Hardware cleared
W = Writable bit
C = Clear only bit
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
‘1’ = Bit is set
bit 15,13
UTXISEL<1:0>: Transmission Interrupt Mode Selection bits
11= Reserved; do not use
10= Interrupt when a character is transferred to the Transmit Shift Register, and as a result, the
transmit buffer becomes empty
01= Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
operations are completed
00= Interrupt when a character is transferred to the Transmit Shift Register (this implies there is
at least one character open in the transmit buffer)
bit 14
UTXINV: Transmit Polarity Inversion bit
If IREN = 0:
1= UxTX Idle state is ‘0’
0= UxTX Idle state is ‘1’
If IREN = 1:
1= IrDA® encoded UxTX Idle state is ‘1’
0= IrDA® encoded UxTX Idle state is ‘0’
bit 12
bit 11
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1= Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
cleared by hardware upon completion
0= Sync Break transmission disabled or completed
bit 10
UTXEN: Transmit Enable bit(1)
1= Transmit enabled, UxTX pin controlled by UARTx
0= Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled
by port
bit 9
UTXBF: Transmit Buffer Full Status bit (read-only)
1= Transmit buffer is full
0= Transmit buffer is not full, at least one more character can be written
bit 8
TRMT: Transmit Shift Register Empty bit (read-only)
1= Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed)
0= Transmit Shift Register is not empty, a transmission is in progress or queued
bit 7-6
URXISEL<1:0>: Receive Interrupt Mode Selection bits
11= Interrupt is set on UxRSR transfer making the receive buffer full (i.e., has 4 data characters)
10= Interrupt is set on UxRSR transfer making the receive buffer 3/4 full (i.e., has 3 data characters)
0x= Interrupt is set when any character is received and transferred from the UxRSR to the receive
buffer. Receive buffer has one or more characters.
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for transmit operation.
DS70292D-page 218
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 18-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1= Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect
0= Address Detect mode disabled
RIDLE: Receiver Idle bit (read-only)
1= Receiver is Idle
0= Receiver is active
PERR: Parity Error Status bit (read-only)
1= Parity error has been detected for the current character (character at the top of the receive FIFO)
0= Parity error has not been detected
FERR: Framing Error Status bit (read-only)
1= Framing error has been detected for the current character (character at the top of the receive
FIFO)
0= Framing error has not been detected
bit 1
bit 0
OERR: Receive Buffer Overrun Error Status bit (read/clear only)
1= Receive buffer has overflowed
0= Receive buffer has not overflowed. Clearing a previously set OERR bit (1 0transition) resets
the receiver buffer and the UxRSR to the empty state.
URXDA: Receive Buffer Data Available bit (read-only)
1= Receive buffer has data, at least one more character can be read
0= Receive buffer is empty
Note 1: Refer to Section 17. “UART” (DS70188) in the “dsPIC33F/PIC24H Family Reference Manual” for infor-
mation on enabling the UART module for transmit operation.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 219
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 220
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
• Programmable Loopback mode supports self-test
operation
19.0 ENHANCED CAN (ECAN™)
MODULE
• Signaling via interrupt capabilities for all CAN
receiver and transmitter error states
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
• Programmable clock source
• Programmable link to input capture module (IC2
for CAN1) for time-stamping and network
synchronization
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 21. Enhanced Control-
ler Area Network (ECAN™)” (DS70185)
of the “dsPIC33F/PIC24H Family Refer-
ence Manual”, which is available from the
Microchip website (www.microchip.com).
• Low-power Sleep and Idle mode
The CAN bus module consists of a protocol engine and
message buffering/control. The CAN protocol engine
handles all functions for receiving and transmitting
messages on the CAN bus. Messages are transmitted
by first loading the appropriate data registers. Status
and errors can be checked by reading the appropriate
registers. Any message detected on the CAN bus is
checked for errors and then matched against filters to
see if it should be received and stored in one of the
receive registers.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
19.2 Frame Types
The ECAN module transmits various types of frames
which include data messages, or remote transmission
requests initiated by the user, as other frames that are
automatically generated for control purposes. The
following frame types are supported:
19.1 Overview
The Enhanced Controller Area Network (ECAN™)
module is a serial interface, useful for communicating
with other CAN modules or microcontroller devices.
This interface/protocol was designed to allow commu-
• Standard Data Frame:
nications
within
noisy
environments.
The
A standard data frame is generated by a node when
the node wishes to transmit data. It includes an 11-
bit Standard Identifier (SID), but not an
18-bit Extended Identifier (EID).
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices contain up to
two ECAN modules.
The ECAN module is a communication controller imple-
menting the CAN 2.0 A/B protocol, as defined in the
BOSCH CAN specification. The module supports
CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B
Active versions of the protocol. The module implementa-
tion is a full CAN system. The CAN specification is not
covered within this data sheet. The reader can refer to
the BOSCH CAN specification for further details.
• Extended Data Frame:
An extended data frame is similar to a standard data
frame, but includes an extended identifier as well.
• Remote Frame:
It is possible for a destination node to request the
data from the source. For this purpose, the
destination node sends a remote frame with an iden-
tifier that matches the identifier of the required data
frame. The appropriate data source node sends a
data frame as a response to this remote request.
The module features are as follows:
• Implementation of the CAN protocol, CAN 1.2,
CAN 2.0A and CAN 2.0B
• Error Frame:
• Standard and extended data frames
• 0-8 bytes data length
An error frame is generated by any node that detects
a bus error. An error frame consists of two fields: an
error flag field and an error delimiter field.
• Programmable bit rate up to 1 Mbit/sec
• Automatic response to remote transmission
requests
• Overload Frame:
An overload frame can be generated by a node as
a result of two conditions. First, the node detects
a dominant bit during interframe space which is an
illegal condition. Second, due to internal condi-
tions, the node is not yet able to start reception of
the next message. A node can generate a maxi-
mum of 2 sequential overload frames to delay the
start of the next message.
• Up to eight transmit buffers with application speci-
fied prioritization and abort capability (each buffer
can contain up to 8 bytes of data)
• Up to 32 receive buffers (each buffer can contain
up to 8 bytes of data)
• Up to 16 full (standard/extended identifier)
acceptance filters
• Three full acceptance filter masks
• DeviceNet™ addressing support
• Interframe Space:
Interframe space separates a proceeding frame (of
whatever type) from a following data or remote
frame.
• Programmable wake-up functionality with
integrated low-pass filter
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 221
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 19-1:
ECAN™ MODULE BLOCK DIAGRAM
RxF15 Filter
RxF14 Filter
RxF13 Filter
RxF12 Filter
RxF11 Filter
RxF10 Filter
RxF9 Filter
RxF8 Filter
RxF7 Filter
RxF6 Filter
RxF5 Filter
RxF4 Filter
RxF3 Filter
RxF2 Filter
RxF1 Filter
RxF0 Filter
DMA Controller
TRB7 Tx/Rx Buffer Control Register
TRB6 Tx/Rx Buffer Control Register
TRB5 Tx/Rx Buffer Control Register
TRB4 Tx/Rx Buffer Control Register
TRB3 Tx/Rx Buffer Control Register
TRB2 Tx/Rx Buffer Control Register
TRB1 Tx/Rx Buffer Control Register
TRB0 Tx/Rx Buffer Control Register
RxM2 Mask
RxM1 Mask
RxM0 Mask
Transmit Byte
Sequencer
Message Assembly
Buffer
Control
Configuration
Logic
CPU
Bus
CAN Protocol
Engine
Interrupts
C1Tx
C1Rx
DS70292D-page 222
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The module can be programmed to apply a low-pass
19.3 Modes of Operation
filter function to the CiRX input line while the module or
The ECAN module can operate in one of several
the CPU is in Sleep mode. The WAKFIL bit
operation modes selected by the user. These modes
(CiCFG2<14>) enables or disables the filter.
include:
Note:
Typically, if the ECAN module is allowed to
transmit in a particular mode of operation
and a transmission is requested immedi-
ately after the ECAN module has been
placed in that mode of operation, the mod-
ule waits for 11 consecutive recessive bits
on the bus before starting transmission. If
the user switches to Disable mode within
this 11-bit period, then this transmission is
aborted and the corresponding TXABT bit
is set and TXREQ bit is cleared.
• Initialization mode
• Disable mode
• Normal Operation mode
• Listen Only mode
• Listen All Messages mode
• Loopback mode
Modes are requested by setting the REQOP<2:0> bits
(CiCTRL1<10:8>). Entry into a mode is Acknowledged
by
monitoring
the
OPMODE<2:0>
bits
(CiCTRL1<7:5>). The module does not change the
mode and the OPMODE bits until a change in mode is
acceptable, generally during bus Idle time, which is
defined as at least 11 consecutive recessive bits.
19.3.3
NORMAL OPERATION MODE
Normal Operation mode is selected when
REQOP<2:0> = 000. In this mode, the module is
activated and the I/O pins assumes the CAN bus
functions. The module transmits and receive CAN bus
messages via the CiTX and CiRX pins.
19.3.1
INITIALIZATION MODE
In the Initialization mode, the module does not transmit
or receive. The error counters are cleared and the inter-
rupt flags remain unchanged. The user application has
access to Configuration registers that are access
restricted in other modes. The module protects the user
from accidentally violating the CAN protocol through
programming errors. All registers which control the
configuration of the module can not be modified while
the module is on-line. The ECAN module is not allowed
to enter the Configuration mode while a transmission is
taking place. The Configuration mode serves as a lock
to protect the following registers:
19.3.4
LISTEN ONLY MODE
If the Listen Only mode is activated, the module on the
CAN bus is passive. The transmitter buffers revert to
the port I/O function. The receive pins remain inputs.
For the receiver, no error flags or Acknowledge signals
are sent. The error counters are deactivated in this
state. The Listen Only mode can be used for detecting
the baud rate on the CAN bus. To use this, it is neces-
sary that there are at least two further nodes that
communicate with each other.
• All Module Control registers
• Baud Rate and Interrupt Configuration registers
• Bus Timing registers
• Identifier Acceptance Filter registers
• Identifier Acceptance Mask registers
19.3.5
LISTEN ALL MESSAGES MODE
The module can be set to ignore all errors and receive
any message. The Listen All Messages mode is acti-
vated by setting REQOP<2:0> = ‘111’. In this mode,
the data which is in the message assembly buffer, until
the time an error occurred, is copied in the receive buf-
fer and can be read via the CPU interface.
19.3.2
DISABLE MODE
In Disable mode, the module does not transmit or
receive. The module has the ability to set the WAKIF bit
due to bus activity, however, any pending interrupts
remains and the error counters retains their value.
19.3.6
LOOPBACK MODE
If the Loopback mode is activated, the module con-
nects the internal transmit signal to the internal receive
signal at the module boundary. The transmit and
receive pins revert to their port I/O function.
If the REQOP<2:0> bits (CiCTRL1<10:8>) = 001, the
module enters the Module Disable mode. If the module is
active, the module waits for 11 recessive bits on the CAN
bus, detect that condition as an Idle bus, then accept the
module disable command. When the OPMODE<2:0>
bits (CiCTRL1<7:5>) = 001, that indicates whether the
module successfully went into Module Disable mode.
The I/O pins reverts to normal I/O function when the
module is in the Module Disable mode.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 223
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-1: CiCTRL1: ECAN™ CONTROL REGISTER 1
U-0
—
U-0
—
R/W-0
CSIDL
R/W-0
ABAT
r-0
—
R/W-1
R/W-0
R/W-0
bit 8
REQOP<2:0>
bit 15
R-1
R-0
R-0
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
WIN
OPMODE<2:0>
CANCAP
bit 7
Legend:
bit 0
r = Bit is reserved
W = Writable bit
‘1’ = Bit is set
R = Readable bit
-n = Value at POR
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
ABAT: Abort All Pending Transmissions bit
1= Signal all transmit buffers to abort transmission.
0= Module will clear this bit when all transmissions are aborted
bit 11
Reserved: Do not use
bit 10-8
REQOP<2:0>: Request Operation Mode bits
000= Set Normal Operation mode
001= Set Disable mode
010= Set Loopback mode
011= Set Listen Only Mode
100= Set Configuration mode
101= Reserved
110= Reserved
111= Set Listen All Messages mode
bit 7-5
OPMODE<2:0>: Operation Mode bits
000= Module is in Normal Operation mode
001= Module is in Disable mode
010= Module is in Loopback mode
011= Module is in Listen Only mode
100= Module is in Configuration mode
101= Reserved
110= Reserved
111= Module is in Listen All Messages mode
bit 4
bit 3
Unimplemented: Read as ‘0’
CANCAP: CAN Message Receive Timer Capture Event Enable bit
1= Enable input capture based on CAN message receive
0= Disable CAN capture
bit 2-1
bit 0
Unimplemented: Read as ‘0’
WIN: SFR Map Window Select bit
1= Use filter window
0= Use buffer window
DS70292D-page 224
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-2: CiCTRL2: ECAN™ CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
bit 0
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
DNCNT<4:0>
bit 7
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
bit 4-0
Unimplemented: Read as ‘0’
DNCNT<4:0>: DeviceNet™ Filter Bit Number bits
10010-11111= Invalid selection
10001= Compare up to data byte 3, bit 6 with EID<17>
•
•
•
00001= Compare up to data byte 1, bit 7 with EID<0>
00000= Do not compare data bytes
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 225
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-3: CiVEC: ECAN™ INTERRUPT CODE REGISTER
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FILHIT<4:0>
bit 15
bit 8
bit 0
U-0
—
R-1
R-0
R-0
R-0
R-0
ICODE<6:0>
bit 7
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Number bits
10000-11111= Reserved
01111= Filter 15
•
•
•
00001= Filter 1
00000= Filter 0
bit 7
Unimplemented: Read as ‘0’
bit 6-0
ICODE<6:0>: Interrupt Flag Code bits
1000101-1111111= Reserved
1000100= FIFO almost full interrupt
1000011= Receiver overflow interrupt
1000010= Wake-up interrupt
1000001= Error interrupt
1000000= No interrupt
•
•
•
0010000-0111111= Reserved
0001111= RB15 buffer Interrupt
•
•
•
0001001= RB9 buffer interrupt
0001000= RB8 buffer interrupt
0000111= TRB7 buffer interrupt
0000110= TRB6 buffer interrupt
0000101= TRB5 buffer interrupt
0000100= TRB4 buffer interrupt
0000011= TRB3 buffer interrupt
0000010= TRB2 buffer interrupt
0000001= TRB1 buffer interrupt
0000000= TRB0 Buffer interrupt
DS70292D-page 226
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-4: CiFCTRL: ECAN™ FIFO CONTROL REGISTER
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
DMABS<2:0>
bit 15
bit 8
R/W-0
bit 0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
FSA<4:0>
bit 7
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
DMABS<2:0>: DMA Buffer Size bits
111= Reserved
110= 32 buffers in DMA RAM
101= 24 buffers in DMA RAM
100= 16 buffers in DMA RAM
011= 12 buffers in DMA RAM
010= 8 buffers in DMA RAM
001= 6 buffers in DMA RAM
000= 4 buffers in DMA RAM
bit 12-5
bit 4-0
Unimplemented: Read as ‘0’
FSA<4:0>: FIFO Area Starts with Buffer bits
11111= Read buffer RB31
11110= Read buffer RB30
•
•
•
00001= Tx/Rx buffer TRB1
00000= Tx/Rx buffer TRB0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 227
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-5: CiFIFO: ECAN™ FIFO STATUS REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
FBP<5:0>
R-0
R-0
R-0
R-0
bit 15
bit 8
bit 0
U-0
—
U-0
—
R-0
R-0
R-0
R-0
FNRB<5:0>
bit 7
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13-8
Unimplemented: Read as ‘0’
FBP<5:0>: FIFO Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
•
•
•
000001= TRB1 buffer
000000= TRB0 buffer
bit 7-6
bit 5-0
Unimplemented: Read as ‘0’
FNRB<5:0>: FIFO Next Read Buffer Pointer bits
011111= RB31 buffer
011110= RB30 buffer
•
•
•
000001= TRB1 buffer
000000= TRB0 buffer
DS70292D-page 228
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-6: CiINTF: ECAN™ INTERRUPT FLAG REGISTER
U-0
—
U-0
—
R-0
R-0
R-0
R-0
R-0
R-0
TXBO
TXBP
RXBP
TXWAR
RXWAR
EWARN
bit 15
bit 8
R/C-0
IVRIF
R/C-0
R/C-0
U-0
—
R/C-0
R/C-0
R/C-0
RBIF
R/C-0
TBIF
WAKIF
ERRIF
FIFOIF
RBOVIF
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
bit 13
Unimplemented: Read as ‘0’
TXBO: Transmitter in Error State Bus Off bit
1= Transmitter is in Bus Off state
0 = Transmitter is not in Bus Off state
bit 12
bit 11
bit 10
bit 9
TXBP: Transmitter in Error State Bus Passive bit
1= Transmitter is in Bus Passive state
0= Transmitter is not in Bus Passive state
RXBP: Receiver in Error State Bus Passive bit
1= Receiver is in Bus Passive state
0= Receiver is not in Bus Passive state
TXWAR: Transmitter in Error State Warning bit
1= Transmitter is in Error Warning state
0= Transmitter is not in Error Warning state
RXWAR: Receiver in Error State Warning bit
1= Receiver is in Error Warning state
0= Receiver is not in Error Warning state
bit 8
EWARN: Transmitter or Receiver in Error State Warning bit
1= Transmitter or Receiver is in Error State Warning state
0= Transmitter or Receiver is not in Error State Warning state
bit 7
IVRIF: Invalid Message Received Interrupt Flag bit
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
bit 6
WAKIF: Bus Wake-up Activity Interrupt Flag bit
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
bit 5
ERRIF: Error Interrupt Flag bit (multiple sources in CiINTF<13:8> register)
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
bit 4
bit 3
Unimplemented: Read as ‘0’
FIFOIF: FIFO Almost Full Interrupt Flag bit
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
bit 2
bit 1
bit 0
RBOVIF: RX Buffer Overflow Interrupt Flag bit
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
RBIF: RX Buffer Interrupt Flag bit
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
TBIF: TX Buffer Interrupt Flag bit
1= Interrupt Request has occurred
0= Interrupt Request has not occurred
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 229
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-7: CiINTE: ECAN™ INTERRUPT ENABLE REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
IVRIE
R/W-0
R/W-0
ERRIE
R/W-0
—
R/W-0
R/W-0
R/W-0
RBIE
R/W-0
TBIE
WAKIE
FIFOIE
RBOVIE
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
IVRIE: Invalid Message Received Interrupt Enable bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
bit 6
bit 5
WAKIE: Bus Wake-up Activity Interrupt Flag bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
ERRIE: Error Interrupt Enable bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
bit 4
bit 3
Unimplemented: Read as ‘0’
FIFOIE: FIFO Almost Full Interrupt Enable bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
bit 2
bit 1
bit 0
RBOVIE: RX Buffer Overflow Interrupt Enable bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
RBIE: RX Buffer Interrupt Enable bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
TBIE: TX Buffer Interrupt Enable bit
1= Interrupt Request Enabled
0= Interrupt Request not enabled
DS70292D-page 230
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-8: CiEC: ECAN™ TRANSMIT/RECEIVE ERROR COUNT REGISTER
R-0
bit 15
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
TERRCNT<7:0>
bit 8
bit 0
R-0
R-0
R-0
R-0
R-0
R-0
RERRCNT<7:0>
bit 7
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
TERRCNT<7:0>: Transmit Error Count bits
RERRCNT<7:0>: Receive Error Count bits
REGISTER 19-9: CiCFG1: ECAN™ BAUD RATE CONFIGURATION REGISTER 1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
SJW<1:0>
BRP<5:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-6
Unimplemented: Read as ‘0’
SJW<1:0>: Synchronization Jump Width bits
11= Length is 4 x TQ
10= Length is 3 x TQ
01= Length is 2 x TQ
00= Length is 1 x TQ
bit 5-0
BRP<5:0>: Baud Rate Prescaler bits
11 1111= TQ = 2 x 64 x 1/FCAN
•
•
•
00 0010= TQ = 2 x 3 x 1/FCAN
00 0001= TQ = 2 x 2 x 1/FCAN
00 0000= TQ = 2 x 1 x 1/FCAN
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 231
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-10: CiCFG2: ECAN™ BAUD RATE CONFIGURATION REGISTER 2
U-0
—
R/W-x
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
WAKFIL
SEG2PH<2:0>
bit 15
R/W-x
R/W-x
SAM
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
SEG2PHTS
SEG1PH<2:0>
PRSEG<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
WAKFIL: Select CAN bus Line Filter for Wake-up bit
1= Use CAN bus line filter for wake-up
0= CAN bus line filter is not used for wake-up
bit 13-11
bit 10-8
Unimplemented: Read as ‘0’
SEG2PH<2:0>: Phase Segment 2 bits
111= Length is 8 x TQ
•
•
•
000= Length is 1 x TQ
bit 7
SEG2PHTS: Phase Segment 2 Time Select bit
1= Freely programmable
0= Maximum of SEG1PH bits or Information Processing Time (IPT), whichever is greater
bit 6
SAM: Sample of the CAN bus Line bit
1= Bus line is sampled three times at the sample point
0= Bus line is sampled once at the sample point
bit 5-3
SEG1PH<2:0>: Phase Segment 1 bits
111= Length is 8 x TQ
•
•
•
000= Length is 1 x TQ
bit 2-0
PRSEG<2:0>: Propagation Time Segment bits
111= Length is 8 x TQ
•
•
•
000= Length is 1 x TQ
DS70292D-page 232
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-11: CiFEN1: ECAN™ ACCEPTANCE FILTER ENABLE REGISTER
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN15
FLTEN14
FLTEN13
FLTEN12
FLTEN11
FLTEN10
FLTEN9
FLTEN8
bit 15
bit 8
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FLTEN7
FLTEN6
FLTEN5
FLTEN4
FLTEN3
FLTEN2
FLTEN1
FLTEN0
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
FLTENn: Enable Filter n to Accept Messages bits
1= Enable Filter n
0= Disable Filter n
REGISTER 19-12: CiBUFPNT1: ECAN™ FILTER 0-3 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F3BP<3:0>
F2BP<3:0>
R/W-0
F1BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F0BP<3:0>
R/W-0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F3BP<3:0>: RX Buffer mask for Filter 3
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F2BP<3:0>: RX Buffer mask for Filter 2 (same values as bit 15-12)
F1BP<3:0>: RX Buffer mask for Filter 1 (same values as bit 15-12)
F0BP<3:0>: RX Buffer mask for Filter 0 (same values as bit 15-12)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 233
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-13: CiBUFPNT2: ECAN™ FILTER 4-7 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F7BP<3:0>
F6BP<3:0>
R/W-0
F5BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F4BP<3:0>
R/W-0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F7BP<3:0>: RX Buffer mask for Filter 7
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F6BP<3:0>: RX Buffer mask for Filter 6 (same values as bit 15-12)
F5BP<3:0>: RX Buffer mask for Filter 5 (same values as bit 15-12)
F4BP<3:0>: RX Buffer mask for Filter 4 (same values as bit 15-12)
REGISTER 19-14: CiBUFPNT3: ECAN™ FILTER 8-11 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F11BP<3:0>
F10BP<3:0>
R/W-0
F9BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F8BP<3:0>
R/W-0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F11BP<3:0>: RX Buffer mask for Filter 11
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F10BP<3:0>: RX Buffer mask for Filter 10 (same values as bit 15-12)
F9BP<3:0>: RX Buffer mask for Filter 9 (same values as bit 15-12)
F8BP<3:0>: RX Buffer mask for Filter 8 (same values as bit 15-12)
DS70292D-page 234
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-15: CiBUFPNT4: ECAN™ FILTER 12-15 BUFFER POINTER REGISTER
R/W-0
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
bit 0
F15BP<3:0>
F14BP<3:0>
R/W-0
F13BP<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
F12BP<3:0>
R/W-0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
F15BP<3:0>: RX Buffer mask for Filter 15
1111= Filter hits received in RX FIFO buffer
1110= Filter hits received in RX Buffer 14
•
•
•
0001= Filter hits received in RX Buffer 1
0000= Filter hits received in RX Buffer 0
bit 11-8
bit 7-4
bit 3-0
F14BP<3:0>: RX Buffer mask for Filter 14 (same values as bit 15-12)
F13BP<3:0>: RX Buffer mask for Filter 13 (same values as bit 15-12)
F12BP<3:0>: RX Buffer mask for Filter 12 (same values as bit 15-12)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 235
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-16: CiRXFnSID: ECAN™ ACCEPTANCE FILTER STANDARD IDENTIFIER REGISTER
n (n = 0-15)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
EXIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Message address bit SIDx must be ‘1’ to match filter
0= Message address bit SIDx must be ‘0’ to match filter
bit 4
bit 3
Unimplemented: Read as ‘0’
EXIDE: Extended Identifier Enable bit
If MIDE = 1then:
1= Match only messages with extended identifier addresses
0= Match only messages with standard identifier addresses
If MIDE = 0then:
Ignore EXIDE bit.
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Message address bit EIDx must be ‘1’ to match filter
0= Message address bit EIDx must be ‘0’ to match filter
DS70292D-page 236
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-17: CiRXFnEID: ECAN™ ACCEPTANCE FILTER EXTENDED IDENTIFIER REGISTER
n (n = 0-15)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 15
bit 8
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Message address bit EIDx must be ‘1’ to match filter
0= Message address bit EIDx must be ‘0’ to match filter
REGISTER 19-18: CiFMSKSEL1: ECAN™ FILTER 7-0 MASK SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F7MSK<1:0>
F6MSK<1:0>
F5MSK<1:0>
F4MSK<1:0>
bit 15
bit 8
R/W-0 R/W-0
F3MSK<1:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F2MSK<1:0>
F1MSK<1:0>
F0MSK<1:0>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
F7MSK<1:0>: Mask Source for Filter 7 bit
11= No mask
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
bit 13-12
bit 11-10
bit 9-8
F6MSK<1:0>: Mask Source for Filter 6 bit (same values as bit 15-14)
F5MSK<1:0>: Mask Source for Filter 5 bit (same values as bit 15-14)
F4MSK<1:0>: Mask Source for Filter 4 bit (same values as bit 15-14)
F3MSK<1:0>: Mask Source for Filter 3 bit (same values as bit 15-14)
F2MSK<1:0>: Mask Source for Filter 2 bit (same values as bit 15-14)
F1MSK<1:0>: Mask Source for Filter 1 bit (same values as bit 15-14)
F0MSK<1:0>: Mask Source for Filter 0 bit (same values as bit 15-14)
bit 7-6
bit 5-4
bit 3-2
bit 1-0
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 237
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-19: CiFMSKSEL2: ECAN™ FILTER 15-8 MASK SELECTION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F15MSK<1:0>
F14MSK<1:0>
F13MSK<1:0>
F12MSK<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
F11MSK<1:0>
F10MSK<1:0>
F9MSK<1:0>
F8MSK<1:0>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-14
F15MSK<1:0>: Mask Source for Filter 15 bit
11= No mask
10= Acceptance Mask 2 registers contain mask
01= Acceptance Mask 1 registers contain mask
00= Acceptance Mask 0 registers contain mask
bit 13-12
bit 11-10
bit 9-8
F14MSK<1:0>: Mask Source for Filter 14 bit (same values as bit 15-14)
F13MSK<1:0>: Mask Source for Filter 13 bit (same values as bit 15-14)
F12MSK<1:0>: Mask Source for Filter 12 bit (same values as bit 15-14)
F11MSK<1:0>: Mask Source for Filter 11 bit (same values as bit 15-14)
F10MSK<1:0>: Mask Source for Filter 10 bit (same values as bit 15-14)
F9MSK<1:0>: Mask Source for Filter 9 bit (same values as bit 15-14)
F8MSK<1:0>: Mask Source for Filter 8 bit (same values as bit 15-14)
bit 7-6
bit 5-4
bit 3-2
bit 1-0
DS70292D-page 238
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-20: CiRXMnSID: ECAN™ ACCEPTANCE FILTER MASK STANDARD IDENTIFIER
REGISTER n (n = 0-2)
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
bit 15
bit 8
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
U-0
—
R/W-x
MIDE
U-0
—
R/W-x
EID17
R/W-x
EID16
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-5
SID<10:0>: Standard Identifier bits
1= Include bit SIDx in filter comparison
0= Bit SIDx is don’t care in filter comparison
bit 4
bit 3
Unimplemented: Read as ‘0’
MIDE: Identifier Receive Mode bit
1= Match only message types (standard or extended address) that correspond to EXIDE bit in filter
0= Match either standard or extended address message if filters match
(i.e., if (Filter SID) = (Message SID) or if (Filter SID/EID) = (Message SID/EID))
bit 2
Unimplemented: Read as ‘0’
bit 1-0
EID<17:16>: Extended Identifier bits
1= Include bit EIDx in filter comparison
0= Bit EIDx is don’t care in filter comparison
REGISTER 19-21: CiRXMnEID: ECAN™ ACCEPTANCE FILTER MASK EXTENDED IDENTIFIER
REGISTER n (n = 0-2)
R/W-x
EID15
R/W-x
EID14
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
bit 15
bit 8
R/W-x
EID7
R/W-x
EID6
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
EID<15:0>: Extended Identifier bits
1= Include bit EIDx in filter comparison
0= Bit EIDx is don’t care in filter comparison
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 239
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-22: CiRXFUL1: ECAN™ RECEIVE BUFFER FULL REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL15
RXFUL14
RXFUL13
RXFUL12
RXFUL11
RXFUL10
RXFUL9
RXFUL8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL7
RXFUL6
RXFUL5
RXFUL4
RXFUL3
RXFUL2
RXFUL1
RXFUL0
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXFUL<15:0>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty
REGISTER 19-23: CiRXFUL2: ECAN™ RECEIVE BUFFER FULL REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL24
bit 8
RXFUL31
RXFUL30
RXFUL29
RXFUL28
RXFUL27
RXFUL26
RXFUL25
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXFUL23
RXFUL22
RXFUL21
RXFUL20
RXFUL19
RXFUL18
RXFUL17
RXFUL16
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXFUL<31:16>: Receive Buffer n Full bits
1= Buffer is full (set by module)
0= Buffer is empty
DS70292D-page 240
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-24: CiRXOVF1: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 1
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF15
RXOVF14
RXOVF13
RXOVF12
RXOVF11
RXOVF10
RXOVF9
RXOVF8
bit 15
bit 8
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF7
RXOVF6
RXOVF5
RXOVF4
RXOVF3
RXOVF2
RXOVF1
RXOVF0
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXOVF<15:0>: Receive Buffer n Overflow bits
1= Module attempted to write to a full buffer (set by module)
0= No overflow condition
REGISTER 19-25: CiRXOVF2: ECAN™ RECEIVE BUFFER OVERFLOW REGISTER 2
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF24
bit 8
RXOVF31
RXOVF30
RXOVF29
RXOVF28
RXOVF27
RXOVF26
RXOVF25
bit 15
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
R/C-0
RXOVF23
RXOVF22
RXOVF21
RXOVF20
RXOVF19
RXOVF18
RXOVF17
RXOVF16
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-0
RXOVF<31:16>: Receive Buffer n Overflow bits
1= Module attempted to write to a full buffer (set by module)
0= No overflow condition
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 241
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 19-26: CiTRmnCON: ECAN™ Tx/Rx BUFFER m CONTROL REGISTER
(m = 0,2,4,6; n = 1,3,5,7)
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENn
TXABTn
TXLARBn
TXERRn
TXREQn
RTRENn
TXnPRI<1:0>
bit 15
bit 8
R/W-0
R-0
R-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
TXENm
TXABTm(1) TXLARBm(1) TXERRm(1) TXREQm
RTRENm
TXmPRI<1:0>
bit 7
bit 0
Legend:
C = Writable bit, but only ‘0’ can be written to clear the bit
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
See Definition for Bits 7-0, Controls Buffer n
TXENm: TX/RX Buffer Selection bit
1= Buffer TRBn is a transmit buffer
0= Buffer TRBn is a receive buffer
bit 6
bit 5
bit 4
bit 3
TXABTm: Message Aborted bit(1)
1= Message was aborted
0= Message completed transmission successfully
TXLARBm: Message Lost Arbitration bit(1)
1= Message lost arbitration while being sent
0= Message did not lose arbitration while being sent
TXERRm: Error Detected During Transmission bit(1)
1= A bus error occurred while the message was being sent
0= A bus error did not occur while the message was being sent
TXREQm: Message Send Request bit
1= Requests that a message be sent. The bit automatically clears when the message is successfully
sent
0= Clearing the bit to ‘0’ while set requests a message abort
bit 2
RTRENm: Auto-Remote Transmit Enable bit
1= When a remote transmit is received, TXREQ will be set
0= When a remote transmit is received, TXREQ will be unaffected
bit 1-0
TXmPRI<1:0>: Message Transmission Priority bits
11= Highest message priority
10= High intermediate message priority
01= Low intermediate message priority
00= Lowest message priority
Note 1: This bit is cleared when TXREQ is set.
Note:
The buffers, SID, EID, DLC, Data Field and Receive Status registers are located in DMA RAM.
DS70292D-page 242
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
19.4 ECAN Message Buffers
ECAN Message Buffers are part of DMA RAM Memory.
They are not ECAN special function registers. The user
application must directly write into the DMA RAM area
that is configured for ECAN Message Buffers. The
location and size of the buffer area is defined by the
user application.
BUFFER 19-1:
ECAN™ MESSAGE BUFFER WORD 0
U-0
—
U-0
—
U-0
—
R/W-x
SID10
R/W-x
SID9
R/W-x
SID8
R/W-x
SID7
R/W-x
SID6
bit 15
bit 8
R/W-x
SID5
R/W-x
SID4
R/W-x
SID3
R/W-x
SID2
R/W-x
SID1
R/W-x
SID0
R/W-x
SRR
R/W-x
IDE
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-2
bit 1
Unimplemented: Read as ‘0’
SID<10:0>: Standard Identifier bits
SRR: Substitute Remote Request bit
1= Message will request remote transmission
0= Normal message
bit 0
IDE: Extended Identifier bit
1= Message will transmit extended identifier
0= Message will transmit standard identifier
BUFFER 19-2:
ECAN™ MESSAGE BUFFER WORD 1
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
EID17
R/W-x
EID16
R/W-x
EID15
R/W-x
EID14
bit 15
bit 8
R/W-x
EID13
R/W-x
EID12
R/W-x
EID11
R/W-x
EID10
R/W-x
EID9
R/W-x
EID8
R/W-x
EID7
R/W-x
EID6
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
EID<17:6>: Extended Identifier bits
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 243
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
(
BUFFER 19-3:
ECAN™ MESSAGE BUFFER WORD 2
R/W-x
EID5
R/W-x
EID4
R/W-x
EID3
R/W-x
EID2
R/W-x
EID1
R/W-x
EID0
R/W-x
RTR
R/W-x
RB1
bit 15
bit 8
U-0
—
U-0
—
U-0
—
R/W-x
RB0
R/W-x
DLC3
R/W-x
DLC2
R/W-x
DLC1
R/W-x
DLC0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-10
bit 9
EID<5:0>: Extended Identifier bits
RTR: Remote Transmission Request bit
1= Message will request remote transmission
0= Normal message
bit 8
RB1: Reserved Bit 1
User must set this bit to ‘0’ per CAN protocol.
Unimplemented: Read as ‘0’
RB0: Reserved Bit 0
bit 7-5
bit 4
User must set this bit to ‘0’ per CAN protocol.
DLC<3:0>: Data Length Code bits
bit 3-0
BUFFER 19-4:
ECAN
R/W-x
™ MESSAGE BUFFER WORD 3
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
Byte 1
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 1<15:8>: ECAN™ Message Byte 0
Byte 0<7:0>: ECAN Message Byte 1
DS70292D-page 244
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
BUFFER 19-5:
ECAN
R/W-x
™ MESSAGE BUFFER WORD 4
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
Byte 3
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 2
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 3<15:8>: ECAN™ Message Byte 3
Byte 2<7:0>: ECAN Message Byte 2
BUFFER 19-6:
ECAN
R/W-x
™ MESSAGE BUFFER WORD 5
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
Byte 5
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 4
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 5<15:8>: ECAN™ Message Byte 5
Byte 4<7:0>: ECAN Message Byte 4
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 245
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
BUFFER 19-7:
ECAN
R/W-x
™ MESSAGE BUFFER WORD 6
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
R/W-x
bit 0
Byte 7
bit 15
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
Byte 6
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-0
Byte 7<15:8>: ECAN™ Message Byte 7
Byte 6<7:0>: ECAN Message Byte 6
BUFFER 19-8:
ECAN™ MESSAGE BUFFER WORD 7
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
FILHIT<4:0>(1)
R/W-x
R/W-x
bit 8
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-8
Unimplemented: Read as ‘0’
FILHIT<4:0>: Filter Hit Code bits(1)
Encodes number of filter that resulted in writing this buffer.
bit 7-0
Unimplemented: Read as ‘0’
Note 1: Only written by module for receive buffers, unused for transmit buffers.
DS70292D-page 246
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
20.1 Module Introduction
20.0 DATA CONVERTER
INTERFACE (DCI) MODULE
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 Data Converter
Interface (DCI) module allows simple interfacing of
devices, such as audio coder/decoders (Codecs), ADC
and D/A converters. The following interfaces are sup-
ported:
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 20. Data Converter
Interface (DCI)” (DS70288) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
• Framed Synchronous Serial Transfer (Single or
Multi-Channel)
• Inter-IC Sound (I2S) Interface
• AC-Link Compliant mode
• The DCI module provides the following general
features:
• Programmable word size up to 16 bits
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
• Supports up to 16 time slots, for a maximum
frame size of 256 bits
• Data buffering for up to 4 samples without CPU
overhead
FIGURE 20-1:
DCI MODULE BLOCK DIAGRAM
BCG Control bits
SCKD
FSD
Sample Rate
FOSC/4
CSCK
COFS
Generator
Word Size Selection bits
Frame Length Selection bits
DCI Mode Selection bits
Frame
Synchronization
Generator
Receive Buffer
Registers w/Shadow
DCI Buffer
Control Unit
15
0
Transmit Buffer
Registers w/Shadow
DCI Shift Register
CSDI
CSDO
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 247
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 20-1: DCICON1: DCI CONTROL REGISTER 1
R/W-0
U-0
—
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
DCIEN
DCISIDL
DLOOP
CSCKD
CSCKE
COFSD
bit 15
bit 8
R/W-0
UNFM
R/W-0
R/W-0
DJST
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CSDOM
COFSM<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
DCIEN: DCI Module Enable bit
1= Module is enabled
0= Module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
DCISIDL: DCI Stop in Idle Control bit
1= Module will halt in CPU Idle mode
0= Module will continue to operate in CPU Idle mode
bit 12
bit 11
Unimplemented: Read as ‘0’
DLOOP: Digital Loopback Mode Control bit
1= Digital Loopback mode is enabled. CSDI and CSDO pins internally connected.
0= Digital Loopback mode is disabled
bit 10
bit 9
bit 8
bit 7
bit 6
bit 5
CSCKD: Sample Clock Direction Control bit
1= CSCK pin is an input when DCI module is enabled
0= CSCK pin is an output when DCI module is enabled
CSCKE: Sample Clock Edge Control bit
1= Data changes on serial clock falling edge, sampled on serial clock rising edge
0= Data changes on serial clock rising edge, sampled on serial clock falling edge
COFSD: Frame Synchronization Direction Control bit
1= COFS pin is an input when DCI module is enabled
0= COFS pin is an output when DCI module is enabled
UNFM: Underflow Mode bit
1= Transmit last value written to the transmit registers on a transmit underflow
0= Transmit ‘0’s on a transmit underflow
CSDOM: Serial Data Output Mode bit
1= CSDO pin will be tri-stated during disabled transmit time slots
0= CSDO pin drives ‘0’s during disabled transmit time slots
DJST: DCI Data Justification Control bit
1= Data transmission/reception is begun during the same serial clock cycle as the frame
synchronization pulse
0= Data transmission/reception is begun one serial clock cycle after frame synchronization pulse
bit 4-2
bit 1-0
Unimplemented: Read as ‘0’
COFSM<1:0>: Frame Sync Mode bits
11= 20-bit AC-Link mode
10= 16-bit AC-Link mode
01= I2S Frame Sync mode
00= Multi-Channel Frame Sync mode
DS70292D-page 248
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 20-2: DCICON2: DCI CONTROL REGISTER 2
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
BLEN<1:0>
COFSG3
bit 15
bit 8
R/W-0
bit 7
Legend:
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
COFSG<2:0>
WS<3:0>
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-10
Unimplemented: Read as ‘0’
BLEN<1:0>: Buffer Length Control bits
11= Four data words will be buffered between interrupts
10= Three data words will be buffered between interrupts
01= Two data words will be buffered between interrupts
00= One data word will be buffered between interrupts
bit 9
Unimplemented: Read as ‘0’
bit 8-5
COFSG<3:0>: Frame Sync Generator Control bits
1111= Data frame has 16 words
•
•
•
0010= Data frame has 3 words
0001= Data frame has 2 words
0000= Data frame has 1 word
bit 4
Unimplemented: Read as ‘0’
bit 3-0
WS<3:0>: DCI Data Word Size bits
1111= Data word size is 16 bits
•
•
•
0100= Data word size is 5 bits
0011= Data word size is 4 bits
0010= Invalid Selection. Do not use. Unexpected results may occur.
0001= Invalid Selection. Do not use. Unexpected results may occur.
0000= Invalid Selection. Do not use. Unexpected results may occur.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 249
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 20-3: DCICON3: DCI CONTROL REGISTER 3
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
BCG<11:8>
bit 15
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BCG<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
BCG<11:0>: DCI Bit Clock Generator Control bits
DS70292D-page 250
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 20-4: DCISTAT: DCI STATUS REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
SLOT<3:0>
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
R-0
R-0
R-0
R-0
ROV
RFUL
TUNF
TMPTY
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-8
Unimplemented: Read as ‘0’
SLOT<3:0>: DCI Slot Status bits
1111= Slot 15 is currently active
•
•
•
0010= Slot 2 is currently active
0001= Slot 1 is currently active
0000= Slot 0 is currently active
bit 7-4
bit 3
Unimplemented: Read as ‘0’
ROV: Receive Overflow Status bit
1= A receive overflow has occurred for at least one receive register
0= A receive overflow has not occurred
bit 2
bit 1
bit 0
RFUL: Receive Buffer Full Status bit
1= New data is available in the receive registers
0= The receive registers have old data
TUNF: Transmit Buffer Underflow Status bit
1= A transmit underflow has occurred for at least one transmit register
0= A transmit underflow has not occurred
TMPTY: Transmit Buffer Empty Status bit
1= The transmit registers are empty
0= The transmit registers are not empty
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 251
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 20-5: RSCON: DCI RECEIVE SLOT CONTROL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
RSE11
R/W-0
R/W-0
RSE9
R/W-0
RSE8
RSE15
RSE14
RSE13
RSE12
RSE10
bit 15
bit 8
R/W-0
RSE7
R/W-0
RSE6
R/W-0
RSE5
R/W-0
RSE4
R/W-0
RSE3
R/W-0
RSE2
R/W-0
RSE1
R/W-0
RSE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
RSE<15:0>: Receive Slot Enable bits
1= CSDI data is received during the individual time slot n
0= CSDI data is ignored during the individual time slot n
REGISTER 20-6: TSCON: DCI TRANSMIT SLOT CONTROL REGISTER
R/W-0
TSE15
R/W-0
TSE14
R/W-0
TSE13
R/W-0
TSE12
R/W-0
TSE11
R/W-0
TSE10
R/W-0
TSE9
R/W-0
TSE8
bit 15
bit 8
R/W-0
TSE7
R/W-0
TSE6
R/W-0
TSE5
R/W-0
TSE4
R/W-0
TSE3
R/W-0
TSE2
R/W-0
TSE1
R/W-0
TSE0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
TSE<15:0>: Transmit Slot Enable Control bits
1= Transmit buffer contents are sent during the individual time slot n
0= CSDO pin is tri-stated or driven to logic ‘0’, during the individual time slot, depending on the state
of the CSDOM bit
DS70292D-page 252
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Depending on the particular device pinout, the ADC
21.0 10-BIT/12-BIT ANALOG-TO-
can have up to 13 analog input pins, designated AN0
DIGITAL CONVERTER (ADC)
through AN12. In addition, there are two analog input
pins for external voltage reference connections. These
voltage reference inputs can be shared with other ana-
log input pins. The actual number of analog input pins
and external voltage reference input configuration
depends on the specific device.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 16. Analog-to-Digital
Converter (ADC)” (DS70183) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
Block diagrams of the ADC module are shown in
Figure 21-1 and Figure 21-2.
21.2 ADC Initialization
The following configuration steps should be performed.
1. Configure the ADC module:
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
a) Select port pins as analog inputs
(AD1PCFGH<15:0> or AD1PCFGL<15:0>)
b) Select voltage reference source to match
expected range on analog inputs
(AD1CON2<15:13>)
c) Select the analog conversion clock to
match desired data rate with processor
clock (AD1CON3<7:0>)
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices have up
to 13 ADC input channels.
d) Determine how many S/H channels are
used
(AD1CON2<9:8>
and
The AD12B bit (AD1CON1<10>) allows each of the
ADC modules to be configured by the user as either a
10-bit, 4-sample/hold ADC (default configuration) or a
12-bit, 1-sample/hold ADC.
AD1PCFGH<15:0> or AD1PCFGL<15:0>)
e) Select the appropriate sample/conversion
sequence
(AD1CON1<7:5>
and
AD1CON3<12:8>)
Note:
The ADC module needs to be disabled
before modifying the AD12B bit.
f) Select how conversion results are
presented in the buffer (AD1CON1<9:8>)
g) Turn on ADC module (AD1CON1<15>)
2. Configure ADC interrupt (if required):
a) Clear the AD1IF bit
21.1 Key Features
The 10-bit ADC configuration has the following key
features:
b) Select ADC interrupt priority
• Successive Approximation (SAR) conversion
• Conversion speeds of up to 1.1 Msps
• Up to 13 analog input pins
21.3 ADC and DMA
If more than one conversion result needs to be buffered
before triggering an interrupt, DMA data transfers can
be used. ADC1 can trigger a DMA data transfer. If
ADC1 is selected as the DMA IRQ source, a DMA
transfer occurs when the AD1IF bit gets set as a result
of an ADC1 sample conversion sequence.
• External voltage reference input pins
• Simultaneous sampling of up to four analog input
pins
• Automatic Channel Scan mode
• Selectable conversion trigger source
• Selectable Buffer Fill modes
The SMPI<3:0> bits (AD1CON2<5:2>) are used to
select how often the DMA RAM buffer pointer is
incremented.
• Four result alignment options (signed/unsigned,
fractional/integer)
• Operation during CPU Sleep and Idle modes
The ADDMABM bit (AD1CON1<12>) determines how
the conversion results are filled in the DMA RAM buffer
area being used for ADC. If this bit is set, DMA buffers
are written in the order of conversion. The module
provides an address to the DMA channel that is the
same as the address used for the non-DMA stand-
alone buffer. If the ADDMABM bit is cleared, then DMA
buffers are written in Scatter/Gather mode. The module
provides a scatter/gather address to the DMA channel,
based on the index of the analog input and the size of
the DMA buffer.
The 12-bit ADC configuration supports all the above
features, except:
• In the 12-bit configuration, conversion speeds of
up to 500 ksps are supported
• There is only one sample/hold amplifier in the
12-bit configuration, so simultaneous sampling of
multiple channels is not supported.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 253
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 21-1:
ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP304,
dsPIC33FJ64GP204/804 AND dsPIC33FJ128GP204/804 DEVICES
AN0
AN12
S/H0
CHANNEL
SCAN
+
CH0SB<4:0>
-
CH0SA<4:0>
CH0
CSCNA
AN1
VREFL
CH0NB
CH0NA
AN0
AN3
AVDD VREFL-(1)
VREFL+(1)
AVSS
S/H1
+
-
CH123SA
CH123SB
CH1(2)
AN6
VCFG<2:0>
AN9
VREFL
VREFH
VREFL
CH123NB
CH123NA
ADC1BUF0
SAR ADC
AN1
AN4
S/H2
+
-
CH123SA
CH123SB
CH2(2)
AN7
AN10
VREFL
CH123NA
CH123NB
AN2
AN5
S/H3
+
-
CH123SA CH123SB
AN8
CH3(2)
AN11
VREFL
CH123NA CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
DS70292D-page 254
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 21-2:
ADC1 MODULE BLOCK DIAGRAM FOR dsPIC33FJ32GP302,
dsPIC33FJ64GP202/802 AND dsPIC33FJ128GP202/802 DEVICES
AN0
AN12
S/H0
CHANNEL
SCAN
+
CH0SB<4:0>
-
CH0SA<4:0>
CH0
CSCNA
AN1
VREFL
CH0NB
CH0NA
AN0
AN3
AVDD VREFL-(1)
VREFL+(1)
AVSS
S/H1
+
-
CH123SA CH123SB
CH1(2)
AN9
VCFG<2:0>
VREFL
VREFH
VREFL
CH123NB
CH123NA
ADC1BUF0
SAR ADC
AN1
AN4
S/H2
+
-
CH123SA CH123SB
CH2(2)
AN10
VREFL
CH123NA
CH123NB
AN2
AN5
S/H3
+
-
CH123SA CH123SB
CH3(2)
AN11
VREFL
CH123NA
CH123NB
Alternate
Input Selection
Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs.
2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 255
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 21-3:
ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM
AD1CON3<15>
ADC Internal
RC Clock
(2)
0
TAD
AD1CON3<5:0>
6
1
ADC Conversion
Clock Multiplier
TCY
(1)
TOSC
X2
1, 2, 3, 4, 5,..., 64
Note 1: Refer to Figure 8-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, Fosc
is equal to the clock source frequency. Tosc = 1/Fosc.
2: See the ADC electrical characteristics for the exact RC clock value.
DS70292D-page 256
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1
R/W-0
ADON
U-0
—
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
R/W-0
ADSIDL
ADDMABM
AD12B
FORM<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
U-0
—
R/W-0
R/W-0
ASAM
R/W-0
HC,HS
R/C-0
HC, HS
SSRC<2:0>
SIMSAM
SAMP
DONE
bit 7
Legend:
bit 0
HC = Cleared by hardware
W = Writable bit
HS = Set by hardware
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
C = Clear only bit
R = Readable bit
-n = Value at POR
‘1’ = Bit is set
bit 15
ADON: ADC Operating Mode bit
1= ADC module is operating
0= ADC is off
bit 14
bit 13
Unimplemented: Read as ‘0’
ADSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
ADDMABM: DMA Buffer Build Mode bit
1= DMA buffers are written in the order of conversion. The module provides an address to the DMA
channel that is the same as the address used for the non-DMA stand-alone buffer
0= DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address
to the DMA channel, based on the index of the analog input and the size of the DMA buffer
bit 11
bit 10
Unimplemented: Read as ‘0’
AD12B: 10-Bit or 12-Bit Operation Mode bit
1= 12-bit, 1-channel ADC operation
0= 10-bit, 4-channel ADC operation
bit 9-8
FORM<1:0>: Data Output Format bits
For 10-bit operation:
11= Signed fractional (DOUT = sddd dddd dd00 0000, where s=.NOT.d<9>)
10= Fractional (DOUT = dddd dddd dd00 0000)
01= Signed integer (DOUT = ssss sssd dddd dddd, where s= .NOT.d<9>)
00= Integer (DOUT = 0000 00dd dddd dddd)
For 12-bit operation:
11= Signed fractional (DOUT = sddd dddd dddd 0000, where s= .NOT.d<11>)
10= Fractional (DOUT = dddd dddd dddd 0000)
01= Signed Integer (DOUT = ssss sddd dddd dddd, where s= .NOT.d<11>)
00= Integer (DOUT = 0000 dddd dddd dddd)
bit 7-5
SSRC<2:0>: Sample Clock Source Select bits
111= Internal counter ends sampling and starts conversion (auto-convert)
110= Reserved
101= Reserved
100= GP timer (Timer5 for ADC1) compare ends sampling and starts conversion
011= Reserved
010= GP timer (Timer3 for ADC1) compare ends sampling and starts conversion
001= Active transition on INT0 pin ends sampling and starts conversion
000= Clearing sample bit ends sampling and starts conversion
bit 4
Unimplemented: Read as ‘0’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 257
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-1: AD1CON1: ADC1 CONTROL REGISTER 1 (CONTINUED)
bit 3
SIMSAM: Simultaneous Sample Select bit (only applicable when CHPS<1:0> = 01or 1x)
When AD12B = 1, SIMSAM is: U-0, Unimplemented, Read as ‘0’
1= Samples CH0, CH1, CH2, CH3 simultaneously (when CHPS<1:0> = 1x); or
Samples CH0 and CH1 simultaneously (when CHPS<1:0> = 01)
0= Samples multiple channels individually in sequence
bit 2
bit 1
ASAM: ADC Sample Auto-Start bit
1= Sampling begins immediately after last conversion. SAMP bit is auto-set
0= Sampling begins when SAMP bit is set
SAMP: ADC Sample Enable bit
1= ADC sample/hold amplifiers are sampling
0= ADC sample/hold amplifiers are holding
If ASAM = 0, software can write ‘1’ to begin sampling. Automatically set by hardware if ASAM = 1.
If SSRC = 000, software can write ‘0’ to end sampling and start conversion. If SSRC 000,
automatically cleared by hardware to end sampling and start conversion.
bit 0
DONE: ADC Conversion Status bit
1= ADC conversion cycle is completed.
0= ADC conversion not started or in progress
Automatically set by hardware when ADC conversion is complete. Software can write ‘0’ to clear
DONE status (software not allowed to write ‘1’). Clearing this bit does NOT affect any operation in
progress. Automatically cleared by hardware at start of a new conversion.
DS70292D-page 258
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-2: AD1CON2: ADC1 CONTROL REGISTER 2
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
VCFG<2:0>
CSCNA
CHPS<1:0>
bit 15
bit 8
R-0
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUFM
R/W-0
ALTS
BUFS
SMPI<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
VCFG<2:0>: Converter Voltage Reference Configuration bits
ADREF+
ADREF-
000
AVDD
AVSS
AVSS
001 External VREF+
010
011 External VREF+
1xx
AVDD
External VREF-
External VREF-
Avss
AVDD
bit 12-11
bit 10
Unimplemented: Read as ‘0’
CSCNA: Scan Input Selections for CH0+ during Sample A bit
1= Scan inputs
0= Do not scan inputs
bit 9-8
bit 7
CHPS<1:0>: Selects Channels Utilized bits
When AD12B = 1, CHPS<1:0> is: U-0, Unimplemented, Read as ‘0’
1x= Converts CH0, CH1, CH2 and CH3
01= Converts CH0 and CH1
00= Converts CH0
BUFS: Buffer Fill Status bit (only valid when BUFM = 1)
1= ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0= ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
bit 6
Unimplemented: Read as ‘0’
bit 5-2
SMPI<3:0>: Selects Increment Rate for DMA Addresses bits or number of sample/conversion
operations per interrupt
1111= Increments the DMA address or generates interrupt after completion of every 16th sample/
conversion operation
1110= Increments the DMA address or generates interrupt after completion of every 15th sample/
conversion operation
•
•
•
0001= Increments the DMA address after completion of every 2nd sample/conversion operation
0000= Increments the DMA address after completion of every sample/conversion operation
bit 1
bit 0
BUFM: Buffer Fill Mode Select bit
1= Starts buffer filling at address 0x0 on first interrupt and 0x8 on next interrupt
0= Always starts filling buffer at address 0x0
ALTS: Alternate Input Sample Mode Select bit
1= Uses channel input selects for Sample A on first sample and Sample B on next sample
0= Always uses channel input selects for Sample A
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 259
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-3: AD1CON3: ADC1 CONTROL REGISTER 3
R/W-0
ADRC
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
SAMC<4:0>(1)
R/W-0
R/W-0
R/W-0
bit 8
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
ADCS<7:0>(2)
R/W-0
R/W-0
R/W-0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ADRC: ADC Conversion Clock Source bit
1= ADC internal RC clock
0= Clock derived from system clock
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
SAMC<4:0>: Auto Sample Time bits(1)
11111= 31 TAD
•
•
•
00001= 1 TAD
00000= 0 TAD
bit 7-0
ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111= Reserved
•
•
•
•
01000000= Reserved
00111111= TCY ·(ADCS<7:0> + 1) = 64 ·TCY = TAD
•
•
•
00000010= TCY ·(ADCS<7:0> + 1) = 3 ·TCY = TAD
00000001= TCY ·(ADCS<7:0> + 1) = 2 ·TCY = TAD
00000000= TCY ·(ADCS<7:0> + 1) = 1 ·TCY = TAD
Note 1: This bit only used if AD1CON1<7:5> (SSRC<2:0>) = 111.
2: This bit is not used if AD1CON3<15> (ADRC) = 1.
DS70292D-page 260
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-4: AD1CON4: ADC1 CONTROL REGISTER 4
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
DMABL<2:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-3
bit 2-0
Unimplemented: Read as ‘0’
DMABL<2:0>: Selects Number of DMA Buffer Locations per Analog Input bits
111= Allocates 128 words of buffer to each analog input
110= Allocates 64 words of buffer to each analog input
101= Allocates 32 words of buffer to each analog input
100= Allocates 16 words of buffer to each analog input
011= Allocates 8 words of buffer to each analog input
010= Allocates 4 words of buffer to each analog input
001= Allocates 2 words of buffer to each analog input
000= Allocates 1 word of buffer to each analog input
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 261
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-5: AD1CHS123: ADC1 INPUT CHANNEL 1, 2, 3 SELECT REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NB<1:0>
CH123SB
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH123NA<1:0>
CH123SA
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-9
Unimplemented: Read as ‘0’
CH123NB<1:0>: Channel 1, 2, 3 Negative Input Select for Sample B bits
When AD12B = 1, CHxNB is: U-0, Unimplemented, Read as ‘0’
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8(1)
0x= CH1, CH2, CH3 negative input is VREF-
bit 8
CH123SB: Channel 1, 2, 3 Positive Input Select for Sample B bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
bit 7-3
bit 2-1
Unimplemented: Read as ‘0’
CH123NA<1:0>: Channel 1, 2, 3 Negative Input Select for Sample A bits
When AD12B = 1, CHxNA is: U-0, Unimplemented, Read as ‘0’
11= CH1 negative input is AN9, CH2 negative input is AN10, CH3 negative input is AN11
10= CH1 negative input is AN6, CH2 negative input is AN7, CH3 negative input is AN8(1)
0x= CH1, CH2, CH3 negative input is VREF-
bit 0
CH123SA: Channel 1, 2, 3 Positive Input Select for Sample A bit
When AD12B = 1, CHxSA is: U-0, Unimplemented, Read as ‘0’
1= CH1 positive input is AN3, CH2 positive input is AN4, CH3 positive input is AN5
0= CH1 positive input is AN0, CH2 positive input is AN1, CH3 positive input is AN2
Note 1: This bit setting is Reserved in dsPIC33FJ128GPX02, dsPIC33FJ64GPX02 and dsPIC33FJGPX02 (28-
pin) devices.
DS70292D-page 262
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-6: AD1CHS0: ADC1 INPUT CHANNEL 0 SELECT REGISTER
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
R/W-0
CH0NB
CH0SB<4:0>
bit 15
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
CH0NA
CH0SA<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CH0NB: Channel 0 Negative Input Select for Sample B bit
Same definition as bit 7.
bit 14-13
bit 12-8
Unimplemented: Read as ‘0’
CH0SB<4:0>: Channel 0 Positive Input Select for Sample B bits
01100= Channel 0 positive input is AN12
01011= Channel 0 positive input is AN11
•
•
•
01000= Channel 0 positive input is AN8(1)
00111= Channel 0 positive input is AN7(1)
00110= Channel 0 positive input is AN6(1)
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
bit 7
CH0NA: Channel 0 Negative Input Select for Sample A bit
1= Channel 0 negative input is AN1
0= Channel 0 negative input is VREF-
bit 6-5
bit 4-0
Unimplemented: Read as ‘0’
CH0SA<4:0>: Channel 0 Positive Input Select for Sample A bits
01100= Channel 0 positive input is AN12
01011= Channel 0 positive input is AN11
•
•
•
01000= Channel 0 positive input is AN8(1)
00111= Channel 0 positive input is AN7(1)
00110= Channel 0 positive input is AN6(1)
•
•
•
00010= Channel 0 positive input is AN2
00001= Channel 0 positive input is AN1
00000= Channel 0 positive input is AN0
Note 1: These bit settings (AN6, AN7 and AN8) are reserved on dsPIC33FJ128GPX02, dsPIC33FJ64GPX02 and
dsPIC33FJ32GPX02 (28-pin) devices.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 263
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 21-7: AD1CSSL: ADC1 INPUT SCAN SELECT REGISTER LOW(1,2)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
CSS11
R/W-0
R/W-0
CSS9
R/W-0
CSS8
CSS12
CSS10
bit 15
bit 8
R/W-0
CSS7
R/W-0
CSS6
R/W-0
CSS5
R/W-0
CSS4
R/W-0
CSS3
R/W-0
CSS2
R/W-0
CSS1
R/W-0
CSS0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-12
bit 11-0
Unimplemented: Read as ‘0’
CSS<11:0>: ADC Input Scan Selection bits
1= Select ANx for input scan
0= Skip ANx for input scan
Note 1: On devices without 13 analog inputs, all AD1CSSL bits can be selected by the user application. However,
inputs selected for scan without a corresponding input on device converts VREFL.
2: CSSx = ANx, where x = 0 through 12.
REGISTER 21-8: AD1PCFGL: ADC1 PORT CONFIGURATION REGISTER LOW(1,2,3)
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG12
PCFG11
PCFG10
PCFG9
PCFG8
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PCFG7
PCFG6
PCFG5
PCFG4
PCFG3
PCFG2
PCFG1
PCFG0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12-0
Unimplemented: Read as ‘0’
PCFG<12:0>: ADC Port Configuration Control bits
1= Port pin in Digital mode, port read input enabled, ADC input multiplexor connected to AVSS
0= Port pin in Analog mode, port read input disabled, ADC samples pin voltage
Note 1: On devices without 13 analog inputs, all PCFG bits are R/W by user software. However, the PCFG bits are
ignored on ports without a corresponding input on device.
2: PCFGx = ANx, where x = 0 through 12.
3: PCFGx bits have no effect if ADC module is disabled by setting ADxMD bit in the PMDx Register. In this
case all port pins multiplexed with ANx will be in Digital mode.
DS70292D-page 264
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
the DAC output controls an important processor or
22.0 AUDIO DIGITAL-TO-ANALOG
machinery. The DACDFLT register should be initialized
CONVERTER (DAC)
with a “safe” output value. Often the safe output value
is either the midpoint value (0x8000) or a zero value
(0x0000).
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
The digital interpolator up-samples the input signals,
where the over-sampling ratio is 256x which creates
data points between the user supplied data points.
The interpolator also includes processing by digital
filters to provide “noise shaping” to move the
converter noise above 20 kHz (upper limit of the pass
band). The output of the interpolator drives the Sigma-
Delta modulator. The serial data bit stream from the
Sigma-Delta modulator is processed by the
reconstruction filter. The differential outputs of the
reconstruction filter are amplified by Op Amps to
provide the required peak-to-peak voltage swing.
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 33. Audio Digital-to-
Analog Converter (DAC)”, (DS70211) of
the “dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Note:
The DAC module is designed specifically
for audio applications and is not
recommended
applications.
for
control
type
The Audio Digital-to-Analog Converter (DAC) module
is a 16-bit Delta-Sigma signal converter designed for
audio applications. It has two output channels, left and
right to support stereo applications. Each DAC output
channel provides three voltage outputs, positive DAC
output, negative DAC output, and the midpoint voltage
22.3 DAC Output Format
The DAC output data stream can be in a two’s comple-
ment signed number format or as an unsigned number
format.
output
dsPIC33FJ128GP804
dsPIC33FJ64GP802
devices provide positive DAC output and negative DAC
output voltages.
for
the
dsPIC33FJ64GP804
devices.
and
The
The Audio DAC module features the ability to accept
the 16-bit input data in a two’s complement signed
number format or as an unsigned number format.
The data formatting is controlled by the Data Format
Control (FORM<8>) bit in the DAC1CON register.
The supported formats are:
and
dsPIC33FJ128GP802
22.1 Key Features
• 1= Signed (two’s complement)
• 0= Unsigned
• 16-bit resolution (14-bit accuracy)
• Second-Order Digital Delta-Sigma Modulator
• 256 X Over-Sampling Ratio
If the FORM bit is configured for “Unsigned data” then
the user input data yields the following behavior:
• 0xFFFF = most positive output voltage
• 0x8000 = mid point output voltage
• 0x7FFF = a value just below the midpoint
• 0x0000 = minimum output voltage
• 128-Tap FIR Current-Steering Analog Recon-
struction Filter
• 100 ksps Maximum Sampling Rate
• User controllable Sample Clock
• Input Frequency 45 kHz max
• Differential Analog Outputs
• Signal-To-Noise: 90 dB
If the FORM bit is configured for “signed data” then the
user input data yields the following behavior:
• 0x7FFF = most positive output voltage
• 0x0000 = mid point output voltage
• 0xFFFF = value just below the midpoint
• 0x8000 = minimum output voltage
• 4-deep input Buffer
• 16-bit Processor I/O, and DMA interfaces
22.2 DAC Module Operation
The Audio DAC provides an analog output proportional
to the digital input value. The maximum 100,000 sam-
ples per second (100 ksps) update rate provides good
quality audio reproduction.
The functional block diagram of the Audio DAC module
is shown in Figure 22-1. The Audio DAC module pro-
vides a 4-deep data input FIFO buffer for each output
channel. If the DMA module and/or the processor can-
not provide output data in a timely manner, and the
FIFO becomes empty, the DAC accepts data from the
DAC Default Data register (DACDFLT). This safety fea-
ture is useful for industrial control applications where
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 265
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The divisor ratio is programmed by clock divider bits
22.4 DAC Clock
(DACFDIV<6:0>) in the DAC Control register
The DAC clock signal clocks the internal logic of the
(DAC1CON). The resulting DAC clock must not exceed
Audio DAC module. The data sample rate of the Audio
25.6 MHz. If lower sample rates are to be used, then
DAC is an integer division of the rate of the DAC clock.
the DAC filter clock frequency may be reduced to
The DAC clock is generated via a clock divider circuit
reduce power consumption. The DAC clock frequency
that accepts an auxiliary clock from the auxiliary
is 256 times the sampling frequency.
oscillator.
FIGURE 22-1:
BLOCK DIAGRAM OF AUDIO DIGITAL-TO-ANALOG (DAC) CONVERTER
Right Channel
DAC1RM
DAC1RDAT
DAC1RP
DAC1RN
Amp
D/A
Note 1
ACLK
DACDFLT
CONTROL
CLK DIV
DACFDIV<6:0>
DAC1LM
DAC1LP
DAC1LN
Amp
D/A
DAC1LDAT
Note 1
Left Channel
Note 1: If DAC1RDAT and DAC1LDAT are empty, data will be taken from the DACDFLT register.
FIGURE 22-2:
AUDIO DAC OUTPUT FOR RAMP INPUT (UNSIGNED)
0xFFFF
DAC input
Count (DAC1RDAT)
0x0000
VDACH
VDACM
Positive DAC
Output (DAC1RP)
VDACL
VDACH
VDACM
Negative DAC
Output (DAC1RN)
VDACL
Note: VOD+ = VDACH – VDACL, VOD- = VDACL – VDACH; refer to Audio DAC Module Specifications, Table 30-42, for typical values.
DS70292D-page 266
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 22-1: DAC1CON: DAC CONTROL REGISTER
R/W-0
U-0
—
R/W-0
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
FORM
DACEN
DACSIDL
AMPON
bit 15
bit 8
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
bit 0
DACFDIV<6:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
DACEN: DAC1 Enable bit
1= Enables module
0= Disables module
bit 14
bit 13
Unimplemented: Read as ‘0’
DACSIDL: Stop in Ideal Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12
AMPON: Enable Analog Output Amplifier in Sleep Mode/Stop-in Idle Mode
1= Analog Output Amplifier is enabled during Sleep Mode/Stop-in Idle mode
0= Analog Output Amplifier is disabled during Sleep Mode/Stop-in Idle mode
bit 11-9
bit 8
Unimplemented: Read as ‘0’
FORM: Data Format Select bit
1= Signed integer
0 = Unsigned integer
bit 7
Unimplemented: Read as ‘0’
bit 6-0
DACFDIV<6:0>: DAC Clock Divider
1111111= Divide input clock by 128
•
•
•
0000101= Divide input clock by 6 (default)
•
•
•
0000010= Divide input clock by 3
0000001= Divide input clock by 2
0000000= Divide input clock by 1 (no divide)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 267
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 22-2: DAC1STAT: DAC STATUS REGISTER
R/W-0
LOEN
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R-0
R-0
LMVOEN
LITYPE
LFULL
LEMPTY
bit 15
bit 8
R/W-0
ROEN
U-0
—
R/W-0
U-0
—
U-0
—
R/W-0
R-0
R-0
RMVOEN
RITYPE
RFULL
REMPTY
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
LOEN: Left Channel DAC output enable
1= Positive and negative DAC outputs are enabled.
0= DAC outputs are disabled.
bit 14
bit 13
Unimplemented: Read as ‘0’
LMVOEN: Left Channel Midpoint DAC output voltage enable
1= Midpoint DAC output is enabled.
0= Midpoint output is disabled.
bit 12-11
bit 10
Unimplemented: Read as ‘0’
LITYPE: Left Channel Type of Interrupt
1= Interrupt if FIFO is EMPTY.
0= Interrupt if FIFO is NOT FULL.
bit 9
bit 8
bit 7
LFULL: Status, Left Channel Data input FIFO is FULL
1= FIFO is Full.
0= FIFO is not full.
LEMPTY: Status, Left Channel Data input FIFO is EMPTY
1= FIFO is Empty.
0= FIFO is not Empty.
ROEN: Right Channel DAC output enable
1= Positive and negative DAC outputs are enabled.
0= DAC outputs are disabled.
bit 6
bit 5
Unimplemented: Read as ‘0’
RMVOEN: Right Channel Midpoint DAC output voltage enable
1= Midpoint DAC output is enabled.
0= Midpoint output is disabled.
bit 4-3
bit 2
Unimplemented: Read as ‘0’
RITYPE: Right Channel Type of Interrupt
1= Interrupt if FIFO is EMPTY.
0= Interrupt if FIFO is NOT FULL.
bit 1
bit 0
RFULL: Status, Right Channel Data input FIFO is FULL
1= FIFO is Full.
0= FIFO is not full.
REMPTY: Status, Right Channel Data input FIFO is EMPTY
1= FIFO is Empty.
0= FIFO is not Empty.
DS70292D-page 268
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 22-3: DAC1DFLT: DAC DEFAULT DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
DACDFLT<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
DACDFLT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DACDFLT<15:0>: DAC Default Value
REGISTER 22-4: DAC1LDAT: DAC LEFT DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DACLDAT<15:8>
bit 15
R/W-0
bit 7
bit 8
R/W-0
bit 0
R/W-0
R/W-0
R/W-0
R/W-0
DACLDAT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DACLDAT<15:0>: Left Channel Data Port
REGISTER 22-5: DAC1RDAT: DAC RIGHT DATA REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
DACRDAT<15:8>
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
DACRDAT<7:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-0
DACRDAT<15:0>: Right Channel Data Port
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 269
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 270
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The Comparator module provides a set of dual input
comparators. The inputs to the comparator can be con-
23.0 COMPARATOR MODULE
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
figured to use any one of the four pin inputs (C1IN+,
C1IN-, C2IN+ and C2IN-) as well as the Comparator
Voltage Reference Input (CVREF).
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 34. Comparator”
(DS70212) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
Note:
This peripheral contains output func-
tions that may need to be configured by
the peripheral pin select feature. For
more information, see Section 11.6
“Peripheral Pin Select”.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
FIGURE 23-1:
COMPARATOR I/O OPERATING MODES
C1NEG
C1EN
CMCON<6>
C1OUT(1)
C1INV
C1IN+
C1IN-
VIN-
C1POS
C1
C1IN+
CVREF
VIN+
C1OUTEN
C2NEG
C2POS
CMCON<7>
C2OUT(1)
C2EN
C2
C2INV
C2IN+
C2IN-
VIN-
VIN+
C2IN+
CVREF
C2OUTEN
Note 1: This peripheral’s outputs must be assigned to an available RPn pin before use. Refer to
Section 11.6 “Peripheral Pin Select” for more information.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 271
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER
R/W-0
CMIDL
U-0
—
R/W-0
R/W-0
R/W-0
C2EN
R/W-0
C1EN
R/W-0
R/W-0
C2EVT
C1EVT
C2OUTEN(1) C1OUTEN(2)
bit 15
bit 8
R-0
R-0
R/W-0
C2INV
R/W-0
C1INV
R/W-0
R/W-0
R/W-0
R/W-0
C2OUT
C1OUT
C2NEG
C2POS
C1NEG
C1POS
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
CMIDL: Stop in Idle Mode
1= When device enters Idle mode, module does not generate interrupts. Module is still enabled.
0= Continue normal module operation in Idle mode
bit 14
bit 13
Unimplemented: Read as ‘0’
C2EVT: Comparator 2 Event
1= Comparator output changed states
0= Comparator output did not change states
bit 12
bit 11
bit 10
bit 9
C1EVT: Comparator 1 Event
1= Comparator output changed states
0= Comparator output did not change states
C2EN: Comparator 2 Enable
1= Comparator is enabled
0= Comparator is disabled
C1EN: Comparator 1 Enable
1= Comparator is enabled
0= Comparator is disabled
C2OUTEN: Comparator 2 Output Enable(1)
1= Comparator output is driven on the output pad
0= Comparator output is not driven on the output pad
bit 8
C1OUTEN: Comparator 1 Output Enable(2)
1= Comparator output is driven on the output pad
0= Comparator output is not driven on the output pad
bit 7
C2OUT: Comparator 2 Output bit
When C2INV = 0:
1= C2 VIN+ > C2 VIN-
0= C2 VIN+ < C2 VIN-
When C2INV = 1:
0= C2 VIN+ > C2 VIN-
1= C2 VIN+ < C2 VIN-
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See
Section 11.6 “Peripheral Pin Select” for more information.
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See
Section 11.6 “Peripheral Pin Select” for more information.
DS70292D-page 272
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 23-1: CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
bit 6
C1OUT: Comparator 1 Output bit
When C1INV = 0:
1= C1 VIN+ > C1 VIN-
0= C1 VIN+ < C1 VIN-
When C1INV = 1:
0= C1 VIN+ > C1 VIN-
1= C1 VIN+ < C1 VIN-
bit 5
bit 4
bit 3
C2INV: Comparator 2 Output Inversion bit
1= C2 output inverted
0= C2 output not inverted
C1INV: Comparator 1 Output Inversion bit
1= C1 output inverted
0= C1 output not inverted
C2NEG: Comparator 2 Negative Input Configure bit
1= Input is connected to VIN+
0= Input is connected to VIN-
See Figure 23-1 for the comparator modes.
bit 2
bit 1
bit 0
C2POS: Comparator 2 Positive Input Configure bit
1= Input is connected to VIN+
0= Input is connected to CVREF
See Figure 23-1 for the comparator modes.
C1NEG: Comparator 1 Negative Input Configure bit
1= Input is connected to VIN+
0= Input is connected to VIN-
See Figure 23-1 for the comparator modes.
C1POS: Comparator 1 Positive Input Configure bit
1= Input is connected to VIN+
0= Input is connected to CVREF
See Figure 23-1 for the comparator modes.
Note 1: If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See
Section 11.6 “Peripheral Pin Select” for more information.
2: If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See
Section 11.6 “Peripheral Pin Select” for more information.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 273
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
The comparator reference supply voltage can come
from either VDD and VSS, or the external VREF+ and
23.1 Comparator Voltage Reference
VREF-. The voltage source is selected by the CVRSS
bit (CVRCON<4>).
23.1.1
CONFIGURING THE COMPARATOR
VOLTAGE REFERENCE
The settling time of the comparator voltage reference
must be considered when changing the CVREF
output.
The voltage reference module is controlled through the
CVRCON register (Register 23-2). The comparator
voltage reference provides two ranges of output
voltage, each with 16 distinct levels. The range to be
used is selected by the CVRR bit (CVRCON<5>). The
primary difference between the ranges is the size of the
steps selected by the CVREF Selection bits
(CVR3:CVR0), with one range offering finer resolution.
FIGURE 23-2:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
CVRSS = 1
CVRSS = 0
CVRSRC
8R
VREF+
AVDD
CVRCON<3:0>
R
CVREFIN
CVREN
R
R
R
16 Steps
CVREF
R
R
R
CVRCON<CVROE>
CVRR
VREF-
8R
CVRSS = 1
CVRSS = 0
AVSS
DS70292D-page 274
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 23-2: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-0
R/W-0
R/W-0
CVRR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
CVREN
CVROE
CVRSS
CVR<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7
Unimplemented: Read as ‘0’
CVREN: Comparator Voltage Reference Enable bit
1= CVREF circuit powered on
0= CVREF circuit powered down
bit 6
CVROE: Comparator VREF Output Enable bit
1= CVREF voltage level is output on CVREF pin
0= CVREF voltage level is disconnected from CVREF pin
bit 5
CVRR: Comparator VREF Range Selection bit
1= CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size
0= CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size
bit 4
CVRSS: Comparator VREF Source Selection bit
1= Comparator reference source CVRSRC = VREF+ – VREF-
0= Comparator reference source CVRSRC = AVDD – AVSS
bit 3-0
CVR<3:0>: Comparator VREF Value Selection 0 CVR<3:0> 15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/ 24) (CVRSRC)
When CVRR = 0:
CVREF = 1/4 (CVRSRC) + (CVR<3:0>/32) (CVRSRC)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 275
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 276
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
• Time: hours, minutes, and seconds
24.0 REAL-TIME CLOCK AND
• 24-hour format (military time)
CALENDAR (RTCC)
• Calendar: weekday, date, month and year
Note 1: This data sheet summarizes the features
• Alarm configurable
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
• Year range: 2000 to 2099
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 37. Real-Time Clock
and Calendar (RTCC)” of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
• Leap year correction
• BCD format for compact firmware
• Optimized for low-power operation
• User calibration with auto-adjust
• Calibration range: ±2.64 seconds error per month
• Requirements: External 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The RTCC module is intended for applications where
accurate time must be maintained for extended periods
of time with minimum to no intervention from the CPU.
The RTCC module is optimized for low-power usage to
provide extended battery lifetime while keeping track of
time.
This chapter discusses the Real-Time Clock and
The RTCC module is a 100-year clock and calendar
with automatic leap year detection. The range of the
clock is from 00:00:00 (midnight) on January 1, 2000 to
23:59:59 on December 31, 2099.
Calendar
(RTCC)
module,
available
on
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices, and its
operation. The following are some of the key
features of this module:
The hours are available in 24-hour (military time)
format. The clock provides a granularity of one second
with half-second visibility to the user.
FIGURE 24-1:
RTCC BLOCK DIAGRAM
CPU Clock Domain
RTCC Clock Domain
32.768 kHz Input
from SOSC Oscillator
RCFGCAL
RTCC Prescalers
0.5s
ALCFGRPT
RTCVAL
RTCC Timer
Alarm
Event
Comparator
Compare Registers
with Masks
ALRMVAL
Repeat Counter
RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
RTCC Pin
RTCOE
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 277
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
By writing the ALRMVALH byte, the Alarm Pointer
value, ALRMPTR<1:0> bits, decrement by one until
they reach ‘00’. Once they reach ‘00’, the ALRMMIN
and ALRMSEC value will be accessible through
24.1 RTCC Module Registers
The RTCC module registers are organized into three
categories:
ALRMVALH and ALRMVALL until the pointer value is
manually changed.
• RTCC Control Registers
• RTCC Value Registers
• Alarm Value Registers
TABLE 24-2: ALRMVAL REGISTER
MAPPING
24.1.1
REGISTER MAPPING
To limit the register interface, the RTCC Timer and
Alarm Time registers are accessed through corre-
sponding register pointers. The RTCC Value register
window (RTCVALH and RTCVALL) uses the RTCPTR
bits (RCFGCAL<9:8>) to select the desired timer
register pair (see Table 24-1).
Alarm Value Register Window
ALRMPTR
<1:0>
ALRMVAL<15:8> ALRMVAL<7:0>
00
01
10
11
ALRMMIN
ALRMWD
ALRMMNTH
—
ALRMSEC
ALRMHR
ALRMDAY
—
By writing the RTCVALH byte, the RTCC Pointer value,
RTCPTR<1:0> bits, decrement by one until they reach
‘00’. Once they reach ‘00’, the MINUTES and
SECONDS value will be accessible through RTCVALH
and RTCVALL until the pointer value is manually
changed.
Considering that the 16-bit core does not distinguish
between 8-bit and 16-bit read operations, the user must
be aware that when reading either the ALRMVALH or
ALRMVALL bytes will decrement the ALRMPTR<1:0>
value. The same applies to the RTCVALH or RTCVALL
bytes with the RTCPTR<1:0> being decremented.
TABLE 24-1: RTCVAL REGISTER MAPPING
RTCC Value Register Window
RTCPTR
Note:
This only applies to read operations and
not write operations.
<1:0>
RTCVAL<15:8> RTCVAL<7:0>
24.1.2
WRITE LOCK
00
01
10
11
MINUTES
WEEKDAY
MONTH
—
SECONDS
HOURS
DAY
In order to perform a write to any of the RTCC Timer
registers, the RTCWREN bit (RCFGCAL<13>) must be
set (refer to Example 24-1).
YEAR
Note:
To avoid accidental writes to the timer, it is
recommended that the RTCWREN bit
(RCFGCAL<13>) is kept clear at any
other time. For the RTCWREN bit to be
set, there is only 1 instruction cycle time
window allowed between the 55h/AA
sequence and the setting of RTCWREN;
therefore, it is recommended that code
follow the procedure in Example 24-1.
The Alarm Value register window (ALRMVALH and
ALRMVALL) uses the ALRMPTR bits
(ALCFGRPT<9:8>) to select the desired Alarm register
pair (see Table 24-2).
EXAMPLE 24-1:
SETTING THE RTCWREN BIT
MOV
MOV
MOV
MOV
MOV
BSET
#NVMKEY, W1
;move the address of NVMKEY into W1
#0x55, W2
#0xAA, W3
W2, [W1]
W3, [W1]
RCFGCAL, #13
;start 55/AA sequence
;set the RTCWREN bit
DS70292D-page 278
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-1:
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1)
R/W-0
RTCEN(2)
bit 15
U-0
—
R/W-0
R-0
R-0
R/W-0
R/W-0
R/W-0
RTCWREN RTCSYNC HALFSEC(3)
RTCOE
RTCPTR<1:0>
bit 8
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL<7:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
RTCEN: RTCC Enable bit(2)
1= RTCC module is enabled
0= RTCC module is disabled
bit 14
bit 13
Unimplemented: Read as ‘0’
RTCWREN: RTCC Value Registers Write Enable bit
1= RTCVALH and RTCVALL registers can be written to by the user
0= RTCVALH and RTCVALL registers are locked out from being written to by the user
bit 12
RTCSYNC: RTCC Value Registers Read Synchronization bit
1= RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple
resulting in an invalid data read. If the register is read twice and results in the same data, the data
can be assumed to be valid.
0= RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple
bit 11
bit 10
bit 9-8
HALFSEC: Half-Second Status bit(3)
1= Second half period of a second
0= First half period of a second
RTCOE: RTCC Output Enable bit
1= RTCC output enabled
0= RTCC output disabled
RTCPTR<1:0>: RTCC Value Register Window Pointer bits
Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers;
the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches ‘00’.
RTCVAL<15:8>:
00= MINUTES
01= WEEKDAY
10= MONTH
11= Reserved
RTCVAL<7:0>:
00= SECONDS
01= HOURS
10= DAY
11= YEAR
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 279
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-1:
RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED)
bit 7-0
CAL<7:0>: RTC Drift Calibration bits
01111111= Maximum positive adjustment; adds 508 RTC clock pulses every one minute
•
•
•
00000001= Minimum positive adjustment; adds 4 RTC clock pulses every one minute
00000000= No adjustment
11111111= Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute
•
•
•
10000000= Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute
Note 1: The RCFGCAL register is only affected by a POR.
2: A write to the RTCEN bit is only allowed when RTCWREN = 1.
3: This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register.
DS70292D-page 280
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
RTSECSEL(1)
R/W-0
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1= RTCC seconds clock is selected for the RTCC pin
0= RTCC alarm pulse is selected for the RTCC pin
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1= PMP module uses TTL input buffers
0= PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 281
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-3: ALCFGRPT: ALARM CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ALRMEN
CHIME
AMASK<3:0>
ALRMPTR<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0 R/W-0
ARPT<7:0>
R/W-0
R/W-0
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
ALRMEN: Alarm Enable bit
1= Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and
CHIME = 0)
0= Alarm is disabled
bit 14
CHIME: Chime Enable bit
1= Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh
0= Chime is disabled; ARPT<7:0> bits stop once they reach 00h
bit 13-10
AMASK<3:0>: Alarm Mask Configuration bits
0000= Every half second
0001= Every second
0010= Every 10 seconds
0011= Every minute
0100= Every 10 minutes
0101= Every hour
0110= Once a day
0111= Once a week
1000= Once a month
1001= Once a year (except when configured for February 29th, once every 4 years)
101x= Reserved – do not use
11xx= Reserved – do not use
bit 9-8
ALRMPTR<1:0>: Alarm Value Register Window Pointer bits
Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers;
the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches ‘00’.
ALRMVAL<15:8>:
00= ALRMMIN
01= ALRMWD
10= ALRMMNTH
11= Unimplemented
ALRMVAL<7:0>:
00= ALRMSEC
01= ALRMHR
10= ALRMDAY
11= Unimplemented
bit 7-0
ARPT<7:0>: Alarm Repeat Counter Value bits
11111111= Alarm will repeat 255 more times
•
•
•
00000000= Alarm will not repeat
The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to
FFh unless CHIME = 1.
DS70292D-page 282
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-4: RTCVAL (WHEN RTCPTR<1:0> = 11): YEAR VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
R/W-x
bit 7
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
YRTEN<3:0>
YRONE<3:0>
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-4
bit 3-0
Unimplemented: Read as ‘0’
YRTEN<3:0>: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9
YRONE<3:0>: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9
Note 1: A write to the YEAR register is only allowed when RTCWREN = 1.
REGISTER 24-5: RTCVAL (WHEN RTCPTR<1:0> = 10): MONTH AND DAY VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
R-x
R-x
R-x
R-x
R-x
MTHTEN0
MTHONE<3:0>
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYTEN<1:0>
DAYONE<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1
bit 11-8
bit 7-6
bit 5-4
bit 3-0
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9
Note 1: A write to this register is only allowed when RTCWREN = 1.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 283
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-6: RTCVAL (WHEN RTCPTR<1:0> = 01): WKDYHR: WEEKDAY AND HOURS VALUE
REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
bit 8
WDAY<2:0>
bit 15
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
HRTEN<1:0>
HRONE<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
bit 7-6
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9
bit 3-0
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 24-7: RTCVAL (WHEN RTCPTR<1:0> = 00): MINUTES AND SECONDS VALUE
REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
MINTEN<2:0>
MINONE<3:0>
bit 15
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
SECTEN<2:0>
SECONE<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5
bit 14-12
bit 11-8
bit 7
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9
Unimplemented: Read as ‘0’
bit 6-4
bit 3-0
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9
DS70292D-page 284
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-8: ALRMVAL (WHEN ALRMPTR<1:0> = 10): ALARM MONTH AND DAY VALUE
REGISTER(1)
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
MTHTEN0
MTHONE<3:0>
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
DAYTEN<1:0>
DAYONE<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1
bit 11-8
bit 7-6
bit 5-4
bit 3-0
MTHONE<3:0>: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9
Unimplemented: Read as ‘0’
DAYTEN<1:0>: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3
DAYONE<3:0>: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9
Note 1: A write to this register is only allowed when RTCWREN = 1.
REGISTER 24-9: ALRMVAL (WHEN ALRMPTR<1:0> = 01): ALARM WEEKDAY AND HOURS
VALUE REGISTER(1)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
WDAY2
WDAY1
WDAY0
bit 15
bit 8
U-0
—
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
HRTEN<1:0>
HRONE<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-11
bit 10-8
bit 7-6
Unimplemented: Read as ‘0’
WDAY<2:0>: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6
Unimplemented: Read as ‘0’
bit 5-4
HRTEN<1:0>: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2
HRONE<3:0>: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9
bit 3-0
Note 1: A write to this register is only allowed when RTCWREN = 1.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 285
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 24-10: ALRMVAL (WHEN ALRMPTR<1:0> = 00): ALARM MINUTES AND SECONDS
VALUE REGISTER
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
R/W-x
bit 8
MINTEN<2:0>
MINONE<3:0>
bit 15
U-0
—
R/W-x
R/W-x
R/W-x
R/W-x
bit 0
SECTEN<2:0>
SECONE<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
Unimplemented: Read as ‘0’
MINTEN<2:0>: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5
bit 14-12
bit 11-8
bit 7
MINONE<3:0>: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9
Unimplemented: Read as ‘0’
bit 6-4
bit 3-0
SECTEN<2:0>: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5
SECONE<3:0>: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9
DS70292D-page 286
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
25.1 Overview
25.0 PROGRAMMABLE CYCLIC
REDUNDANCY CHECK (CRC)
GENERATOR
The module implements a software configurable CRC
generator. The terms of the polynomial and its length
can be programmed using the CRCXOR (X<15:1>) bits
and the CRCCON (PLEN<3:0>) bits, respectively.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
EQUATION 25-1: CRC EQUATION
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 36. Programmable
Cyclic Redundancy Check (CRC)”
(DS70298) of the “dsPIC33F/PIC24H
Family Reference Manual”, which is avail-
able from the Microchip website
(www.microchip.com).
16
12
5
x
+ x + x + 1
To program this polynomial into the CRC generator,
the CRC register bits should be set as shown in
Table 25-1.
TABLE 25-1: EXAMPLE CRC SETUP
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
Bit Name
Bit Value
PLEN<3:0>
X<15:1>
1111
000100000010000
For the value of X<15:1>, the 12th bit and the 5th bit are
set to ‘1’, as required by the CRC equation. The 0th bit
required by the CRC equation is always XORed. For a
16-bit polynomial, the 16th bit is also always assumed
to be XORed; therefore, the X<15:1> bits do not have
the 0th bit or the 16th bit.
The programmable CRC generator offers the following
features:
• User-programmable polynomial CRC equation
• Interrupt output
The topology of a standard CRC generator is shown in
Figure 25-2.
• Data FIFO
FIGURE 25-1:
CRC SHIFTER DETAILS
PLEN<3:0>
0
1
2
15
CRC Shift Register
Hold
Hold
X2
Hold
Hold
X1
X3
X15
0
0
0
0
XOR
OUT
OUT
OUT
OUT
IN
BIT 0
IN
BIT 1
IN
BIT 2
IN
BIT 15
DOUT
1
1
1
1
p_clk
p_clk
p_clk
p_clk
CRC Read Bus
CRC Write Bus
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 287
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 25-2:
CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1
XOR
D
Q
D
Q
D
Q
D
Q
D
Q
SDOx
BIT 0
BIT 4
BIT 5
BIT 12
BIT 15
p_clk
p_clk
p_clk
p_clk
p_clk
CRC Read Bus
CRC Write Bus
To empty words already written into a FIFO, the
CRCGO bit must be set to ‘1’ and the CRC shifter
allowed to run until the CRCMPT bit is set.
25.2 User Interface
25.2.1
DATA INTERFACE
Also, to get the correct CRC reading, it will be
necessary to wait for the CRCMPT bit to go high before
reading the CRCWDAT register.
To start serial shifting, a ‘1’ must be written to the
CRCGO bit.
The module incorporates a FIFO that is 8 deep when
PLEN (PLEN<3:0>) > 7, and 16 deep, otherwise. The
data for which the CRC is to be calculated must first be
written into the FIFO. The smallest data element that
can be written into the FIFO is one byte. For example,
if PLEN = 5, then the size of the data is PLEN + 1 = 6.
The data must be written as follows:
If a word is written when the CRCFUL bit is set, the
VWORD Pointer will roll over to 0. The hardware will
then behave as if the FIFO is empty. However, the con-
dition to generate an interrupt will not be met; therefore,
no interrupt will be generated (See Section 25.2.2
“Interrupt Operation”).
At least one instruction cycle must pass after a write to
CRCWDAT before a read of the VWORD bits is done.
data[5:0] = crc_input[5:0]
data[7:6] = ‘bxx
Once data is written into the CRCWDAT MSb (as
defined by PLEN), the value of VWORD
(VWORD<4:0>) increments by one. The serial shifter
starts shifting data into the CRC engine when
CRCGO = 1 and VWORD > 0. When the MSb is
shifted out, VWORD decrements by one. The serial
shifter continues shifting until the VWORD reaches 0.
Therefore, for a given value of PLEN, it will take
(PLEN + 1) * VWORD number of clock cycles to
complete the CRC calculations.
25.2.2
INTERRUPT OPERATION
When the VWORD4:VWORD0 bits make a transition
from a value of ‘1’ to ‘0’, an interrupt will be generated.
25.3 Operation in Power Save Modes
25.3.1
SLEEP MODE
If Sleep mode is entered while the module is operating,
the module will be suspended in its current state until
clock execution resumes.
When VWORD reaches 8 (or 16), the CRCFUL bit will
be set. When VWORD reaches 0, the CRCMPT bit will
be set.
25.3.2
IDLE MODE
To continually feed data into the CRC engine, the rec-
ommended mode of operation is to initially “prime” the
FIFO with a sufficient number of words so no interrupt
is generated before the next word can be written. Once
that is done, start the CRC by setting the CRCGO bit to
‘1’. From that point onward, the VWORD bits should be
polled. If they read less than 8 or 16, another word can
be written into the FIFO.
To continue full module operation in Idle mode, the
CSIDL bit must be cleared prior to entry into the mode.
If CSIDL = 1, the module will behave the same way as
it does in Sleep mode; pending interrupt events will be
passed on, even though the module clocks are not
available.
DS70292D-page 288
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
25.4 Registers
The CRC module provides the following registers:
• CRC Control Register
• CRC XOR Polynomial Register
REGISTER 25-1: CRCCON: CRC CONTROL REGISTER
U-0
—
U-0
—
R/W-0
CSIDL
R-0
R-0
R-0
R-0
R-0
VWORD<4:0>
bit 15
bit 8
R-0
R-1
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CRCFUL
CRCMPT
CRCGO
PLEN<3:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15-14
bit 13
Unimplemented: Read as ‘0’
CSIDL: CRC Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-8
bit 7
VWORD<4:0>: Pointer Value bits
Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN<3:0> is
greater than 7, or 16 when PLEN<3:0> is less than or equal to 7.
CRCFUL: FIFO Full bit
1= FIFO is full
0= FIFO is not full
bit 6
CRCMPT: FIFO Empty bit
1= FIFO is empty
0= FIFO is not empty
bit 5
bit 4
Unimplemented: Read as ‘0’
CRCGO: Start CRC bit
1= Start CRC serial shifter
0= Turn off CRC serial shifter after FIFO is empty
bit 3-0
PLEN<3:0>: Polynomial Length bits
Denotes the length of the polynomial to be generated minus 1.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 289
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 25-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
X<15:8>
bit 15
R/W-0
bit 7
R/W-0
U-0
—
X<7:1>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-1
bit 0
X<15:1>: XOR of Polynomial Term Xn Enable bits
Unimplemented: Read as ‘0’
DS70292D-page 290
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
devices and microcontrollers. Because the interface
to parallel peripherals varies significantly, the PMP is
highly configurable.
26.0 PARALLEL MASTER PORT
(PMP)
Note 1: This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
Key features of the PMP module include:
• Fully multiplexed address/data mode
• Demultiplexed or partially multiplexed address/
data mode
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to “Section 35. Parallel Master
Port (PMP)” (DS70299) of the
“dsPIC33F/PIC24H Family Reference
Manual”, which is available from the
Microchip website (www.microchip.com).
- up to 11 address lines with single chip select
- up to 12 address lines without chip select
• One Chip Select Line
• Programmable Strobe Options
- Individual Read and Write Strobes or;
- Read/Write Strobe with Enable Strobe
• Address Auto-Increment/Auto-Decrement
• Programmable Address/Data Multiplexing
• Programmable Polarity on Control Signals
• Legacy Parallel Slave Port Support
• Enhanced Parallel Slave Support
- Address Support
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Parallel Master Port (PMP) module is a parallel
8-bit I/O module, specifically designed to communi-
cate with a wide variety of parallel devices, such as
communication peripherals, LCDs, external memory
- 4-Byte Deep Auto-Incrementing Buffer
• Programmable Wait States
• Selectable Input Voltage Levels
FIGURE 26-1:
PMP MODULE OVERVIEW
Address Bus
Data Bus
PMA<0>
PMALL
Control Lines
dsPIC33F
Parallel Master Port
PMA<1>
PMALH
Up to 11-Bit Address
EEPROM
PMA<10:2>(1)
PMA<14>
PMCS1
PMBE
PMRD
PMRD/PMWR
PMWR
PMENB
FIFO
Buffer
Microcontroller
LCD
PMD<7:0>
PMA<7:0>
PMA<10:8>
8-Bit Data
Note 1: 28-pin devices do not have PMA<10:2>.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 291
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 26-1: PMCON: PARALLEL PORT CONTROL REGISTER
R/W-0
U-0
—
R/W-0
PSIDL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PMPEN
ADRMUX1 ADRMUX0
PTBEEN
PTWREN
PTRDEN
bit 15
bit 8
R/W-0
CSF1
R/W-0
CSF0
R/W-0(1)
ALP
U-0
—
R/W-0(1)
CS1P
R/W-0
BEP
R/W-0
WRSP
R/W-0
RDSP
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
PMPEN: Parallel Master Port Enable bit
1= PMP enabled
0= PMP disabled, no off-chip access performed
bit 14
bit 13
Unimplemented: Read as ‘0’
PSIDL: Stop in Idle Mode bit
1= Discontinue module operation when device enters Idle mode
0= Continue module operation in Idle mode
bit 12-11
ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1)
11= Reserved
10= All 16 bits of address are multiplexed on PMD<7:0> pins
01= Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on
PMA<10:8>
00= Address and data appear on separate pins
bit 10
bit 9
PTBEEN: Byte Enable Port Enable bit (16-bit Master mode)
1= PMBE port enabled
0= PMBE port disabled
PTWREN: Write Enable Strobe Port Enable bit
1= PMWR/PMENB port enabled
0= PMWR/PMENB port disabled
bit 8
PTRDEN: Read/Write Strobe Port Enable bit
1= PMRD/PMWR port enabled
0= PMRD/PMWR port disabled
bit 7-6
CSF1:CSF0: Chip Select Function bits
11= Reserved
10= PMCS1 functions as chip select
0x= PMCS1 functions as address bit 14
bit 5
ALP: Address Latch Polarity bit(1)
1= Active-high (PMALL and PMALH)
0= Active-low (PMALL and PMALH)
bit 4
bit 3
Unimplemented: Read as ‘0’
CS1P: Chip Select 1 Polarity bit(1)
1= Active-high (PMCS1/PMCS1)
0= Active-low (PMCS1/PMCS1)
bit 2
BEP: Byte Enable Polarity bit
1= Byte enable active-high (PMBE)
0= Byte enable active-low (PMBE)
Note 1: These bits have no effect when their corresponding pins are used as address lines.
DS70292D-page 292
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 26-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 1
WRSP: Write Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1= Write strobe active-high (PMWR)
0= Write strobe active-low (PMWR)
For Master mode 1 (PMMODE<9:8> = 11):
1= Enable strobe active-high (PMENB)
0= Enable strobe active-low (PMENB)
bit 0
RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1= Read strobe active-high (PMRD)
0= Read strobe active-low (PMRD)
For Master mode 1 (PMMODE<9:8> = 11):
1= Read/write strobe active-high (PMRD/PMWR)
0= Read/write strobe active-low (PMRD/PMWR)
Note 1: These bits have no effect when their corresponding pins are used as address lines.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 293
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 26-2: PMMODE: PARALLEL PORT MODE REGISTER
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
BUSY
IRQM<1:0>
INCM<1:0>
MODE16
MODE<1:0>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WAITB<1:0>(1)
WAITM<3:0>
WAITE<1:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
BUSY: Busy bit (Master mode only)
1= Port is busy (not useful when the processor stall is active)
0= Port is not busy
bit 14-13
IRQM<1:0>: Interrupt Request Mode bits
11= Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> = 11(Addressable PSP mode only)
10= No interrupt generated, processor stall activated
01= Interrupt generated at the end of the read/write cycle
00= No interrupt generated
bit 12-11
INCM<1:0>: Increment Mode bits
11= PSP read and write buffers auto-increment (Legacy PSP mode only)
10= Decrement ADDR<10:0> by 1 every read/write cycle
01= Increment ADDR<10:0> by 1 every read/write cycle
00= No increment or decrement of address
bit 10
MODE16: 8-Bit/16-Bit Mode bit
1= 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers
0= 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer
bit 9-8
MODE<1:0>: Parallel Port Mode Select bits
11= Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>)
10= Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>)
01= Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>)
00= Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>)
bit 7-6
bit 5-2
WAITB<1:0>: Data Setup to Read/Write Wait State Configuration bits(1)
11= Data wait of 4 TCY; multiplexed address phase of 4 TCY
10= Data wait of 3 TCY; multiplexed address phase of 3 TCY
01= Data wait of 2 TCY; multiplexed address phase of 2 TCY
00= Data wait of 1 TCY; multiplexed address phase of 1 TCY
WAITM<3:0>: Read to Byte Enable Strobe Wait State Configuration bits
1111= Wait of additional 15 TCY
•
•
•
0001= Wait of additional 1 TCY
0000= No additional wait cycles (operation forced into one TCY)
WAITE<1:0>: Data Hold After Strobe Wait State Configuration bits(1)
bit 1-0
11= Wait of 4 TCY
10= Wait of 3 TCY
01= Wait of 2 TCY
00= Wait of 1 TCY
Note 1: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000.
DS70292D-page 294
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 26-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
R/W-0
R/W-0
CS1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR15
ADDR<13:8>
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ADDR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
ADDR15: Parallel Port Destination Address bits
CS1: Chip Select 1 bit
1= Chip select 1 is active
0= Chip select 1 is inactive
bit 13-0
ADDR13:ADDR0: Parallel Port Destination Address bits
REGISTER 26-4: PMAEN: PARALLEL PORT ENABLE REGISTER
U-0
—
R/W-0
U-0
—
U-0
—
U-0
—
R/W-0
R/W-0
PTEN<10:8>(1)
R/W-0
bit 8
PTEN14
bit 15
R/W-0
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PTEN<7:2>(1)
PTEN<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15
bit 14
Unimplemented: Read as ‘0’
PTEN14: PMCS1 Strobe Enable bit
1= PMA14 functions as either PMA<14> bit or PMCS1
0= PMA14 pin functions as port I/O
bit 13-11
bit 10-2
Unimplemented: Read as ‘0’
PTEN<10:2>: PMP Address Port Enable bits(1)
1= PMA<10:2> function as PMP address lines
0= PMA<10:2> function as port I/O
bit 1-0
PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1= PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL
0= PMA1 and PMA0 pads functions as port I/O
Note 1: Devices with 28 pins do not have PMA<10:2>.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 295
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 26-5: PMSTAT: PARALLEL PORT STATUS REGISTER
R-0
IBF
R/W-0, HS
IBOV
U-0
—
U-0
—
R-0
R-0
R-0
R-0
IB3F
IB2F
IB1F
IB0F
bit 15
bit 8
R-1
R/W-0, HS
OBUF
U-0
—
U-0
—
R-1
R-1
R-1
R-1
OBE
OB3E
OB2E
OB1E
OB0E
bit 0
bit 7
Legend:
HS = Hardware Set bit
W = Writable bit
‘1’ = Bit is set
R = Readable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 15
bit 14
IBF: Input Buffer Full Status bit
1= All writable input buffer registers are full
0= Some or all of the writable input buffer registers are empty
IBOV: Input Buffer Overflow Status bit
1= A write attempt to a full input byte register occurred (must be cleared in software)
0= No overflow occurred
bit 13-12
bit 11-8
Unimplemented: Read as ‘0’
IB3F:IB0F: Input Buffer x Status Full bits
1= Input buffer contains data that has not been read (reading buffer will clear this bit)
0= Input buffer does not contain any unread data
bit 7
bit 6
OBE: Output Buffer Empty Status bit
1= All readable output buffer registers are empty
0= Some or all of the readable output buffer registers are full
OBUF: Output Buffer Underflow Status bits
1= A read occurred from an empty output byte register (must be cleared in software)
0= No underflow occurred
bit 5-4
bit 3-0
Unimplemented: Read as ‘0’
OB3E:OB0E: Output Buffer x Status Empty bit
1= Output buffer is empty (writing data to the buffer will clear this bit)
0= Output buffer contains data that has not been transmitted
DS70292D-page 296
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
REGISTER 26-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
RTSECSEL(1)
R/W-0
PMPTTL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-2
bit 1
Unimplemented: Read as ‘0’
RTSECSEL: RTCC Seconds Clock Output Select bit(1)
1= RTCC seconds clock is selected for the RTCC pin
0= RTCC alarm pulse is selected for the RTCC pin
bit 0
PMPTTL: PMP Module TTL Input Buffer Select bit
1= PMP module uses TTL input buffers
0= PMP module uses Schmitt Trigger input buffers
Note 1: To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 297
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 298
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
27.1 Configuration Bits
27.0 SPECIAL FEATURES
The Configuration bits can be programmed (read as
‘0’), or left unprogrammed (read as ‘1’), to select vari-
ous device configurations. These bits are mapped
starting at program memory location 0xF80000.
Note 1: This data sheet summarizes the features
of
the
dsPIC33FJ32GP302/304,
and
dsPIC33FJ64GPX02/X04,
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To comple-
ment the information in this data sheet,
refer to the “dsPIC33F/PIC24H Family
Reference Manual”. Please see the
Microchip web site (www.microchip.com)
for the latest dsPIC33F/PIC24H Family
Reference Manual sections.
The individual Configuration bit descriptions for the
Configuration registers are shown in Table 27-2.
Note that address 0xF80000 is beyond the user program
memory space. It belongs to the configuration memory
space (0x800000-0xFFFFFF), which can only be
accessed using table reads and table writes.
To prevent inadvertent configuration changes during
code execution, all programmable Configuration bits
are write-once. After a bit is initially programmed during
a power cycle, it cannot be written to again. Changing
a device configuration requires that power to the device
be cycled.
2: Some registers and associated bits
described in this section may not be avail-
able on all devices. Refer to Section 4.0
“Memory Organization” in this data
sheet for device-specific register and bit
information.
The Device Configuration register map is shown in
Table 27-1.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices include
several features intended to maximize application
flexibility and reliability, and minimize cost through
elimination of external components. These are:
• Flexible configuration
• Watchdog Timer (WDT)
• Code Protection and CodeGuard™ Security
• JTAG Boundary Scan Interface
• In-Circuit Serial Programming™ (ICSP™)
• In-Circuit emulation
TABLE 27-1: DEVICE CONFIGURATION REGISTER MAP
Address
Name
Bit 7
RBS<1:0>
RSS<1:0>
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0xF80000 FBS
0xF80002 FSS(1)
—
—
—
—
BSS<2:0>
SSS<2:0>
BWRP
SWRP
GWRP
—
0xF80004 FGS
—
—
—
—
—
—
—
GSS<1:0>
FNOSC<2:0>
0xF80006 FOSCSEL
0xF80008 FOSC
0xF8000A FWDT
0xF8000C FPOR
0xF8000E FICD
0xF80010 FUID0
0xF80012 FUID1
0xF80014 FUID2
0xF80016 FUID3
IESO
—
FCKSM<1:0>
FWDTEN WINDIS
Reserved(2)
IOL1WAY
—
—
OSCIOFNC POSCMD<1:0>
WDTPOST<3:0>
WDTPRE
ALTI2C
—
—
—
FPWRT<2:0>
Reserved(3)
JTAGEN
—
ICS<1:0>
User Unit ID Byte 0
User Unit ID Byte 1
User Unit ID Byte 2
User Unit ID Byte 3
Legend: — = unimplemented bit, read as ‘0’.
Note 1: This Configuration register is not available and reads as 0xFF on dsPIC33FJ32GP302/304 devices.
2: These bits are reserved and always read as ‘1’.
3: These bits are reserved for use by development tools and must be programmed as ‘1’.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 299
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION
Bit Field
Register
Description
BWRP
FBS
Boot Segment Program Flash Write Protection
1= Boot segment can be written
0= Boot segment is write-protected
BSS<2:0>
FBS
Boot Segment Program Flash Code Protection Size
X11= No Boot program Flash segment
Boot space is 1K Instruction Words (except interrupt vectors)
110= Standard security; boot program Flash segment ends at
0x0007FE
010= High security; boot program Flash segment ends at 0x0007FE
Boot space is 4K Instruction Words (except interrupt vectors)
101= Standard security; boot program Flash segment, ends at
0x001FFE
001= High security; boot program Flash segment ends at 0x001FFE
Boot space is 8K Instruction Words (except interrupt vectors)
100= Standard security; boot program Flash segment ends at
0x003FFE
000= High security; boot program Flash segment ends at 0x003FFE
RBS<1:0>(1)
FBS
Boot Segment RAM Code Protection Size
11= No Boot RAM defined
10= Boot RAM is 128 bytes
01= Boot RAM is 256 bytes
00= Boot RAM is 1024 bytes
SWRP(1)
FSS(1)
FSS(1)
Secure Segment Program Flash Write-Protect bit
1= Secure Segment can bet written
0= Secure Segment is write-protected
SSS<2:0>(1)
Secure Segment Program Flash Code Protection Size
(Secure segment is not implemented on 32K devices)
X11= No Secure program flash segment
Secure space is 4K IW less BS
110= Standard security; secure program flash segment starts at End
of BS, ends at 0x001FFE
010= High security; secure program flash segment starts at End of BS,
ends at 0x001FFE
Secure space is 8K IW less BS
101= Standard security; secure program flash segment starts at End
of BS, ends at 0x003FFE
001= High security; secure program flash segment starts at End of BS,
ends at 0x003FFE
Secure space is 16K IW less BS
100= Standard security; secure program flash segment starts at End
of BS, ends at 007FFEh
000= High security; secure program flash segment starts at End of BS,
ends at 0x007FFE
RSS<1:0>(1)
FSS(1)
Secure Segment RAM Code Protection
11= No Secure RAM defined
10= Secure RAM is 256 Bytes less BS RAM
01= Secure RAM is 2048 Bytes less BS RAM
00= Secure RAM is 4096 Bytes less BS RAM
Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices.
DS70292D-page 300
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
GSS<1:0>
FGS
General Segment Code-Protect bit
11= User program memory is not code-protected
10= Standard security
0x= High security
GWRP
IESO
FGS
General Segment Write-Protect bit
1= User program memory is not write-protected
0= User program memory is write-protected
FOSCSEL
Two-speed Oscillator Start-up Enable bit
1= Start-up device with FRC, then automatically switch to the
user-selected oscillator source when ready
0= Start-up device with user-selected oscillator source
FNOSC<2:0>
FOSCSEL
Initial Oscillator Source Selection bits
111= Internal Fast RC (FRC) oscillator with postscaler
110= Internal Fast RC (FRC) oscillator with divide-by-16
101= LPRC oscillator
100= Secondary (LP) oscillator
011= Primary (XT, HS, EC) oscillator with PLL
010= Primary (XT, HS, EC) oscillator
001= Internal Fast RC (FRC) oscillator with PLL
000= FRC oscillator
FCKSM<1:0>
FOSC
Clock Switching Mode bits
1x= Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01= Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00= Clock switching is enabled, Fail-Safe Clock Monitor is enabled
IOL1WAY
OSCIOFNC
FOSC
FOSC
FOSC
Peripheral pin select configuration
1= Allow only one reconfiguration
0= Allow multiple reconfigurations
OSC2 Pin Function bit (except in XT and HS modes)
1= OSC2 is clock output
0= OSC2 is general purpose digital I/O pin
POSCMD<1:0>
Primary Oscillator Mode Select bits
11= Primary oscillator disabled
10= HS Crystal Oscillator mode
01= XT Crystal Oscillator mode
00= EC (External Clock) mode
FWDTEN
FWDT
Watchdog Timer Enable bit
1= Watchdog Timer always enabled (LPRC oscillator cannot be disabled.
Clearing the SWDTEN bit in the RCON register has no effect.)
0= Watchdog Timer enabled/disabled by user software (LPRC can be
disabled by clearing the SWDTEN bit in the RCON register)
WINDIS
FWDT
FWDT
Watchdog Timer Window Enable bit
1= Watchdog Timer in Non-Window mode
0= Watchdog Timer in Window mode
WDTPRE
Watchdog Timer Prescaler bit
1= 1:128
0= 1:32
Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 301
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED)
Bit Field
Register
Description
WDTPOST<3:0>
FWDT
Watchdog Timer Postscaler bits
1111= 1:32,768
1110= 1:16,384
•
•
•
0001= 1:2
0000= 1:1
FPWRT<2:0>
FPOR
Power-on Reset Timer Value Select bits
111= PWRT = 128 ms
110= PWRT = 64 ms
101= PWRT = 32 ms
100= PWRT = 16 ms
011= PWRT = 8 ms
010= PWRT = 4 ms
001= PWRT = 2 ms
000= PWRT = Disabled
ALTI2C
FPOR
FICD
Alternate I2C™ pins
1 = I2C mapped to SDA1/SCL1 pins
0 = I2C mapped to ASDA1/ASCL1 pins
JTAGEN
JTAG Enable bit
1= JTAG enabled
0= JTAG disabled
ICS<1:0>
FICD
ICD Communication Channel Select bits
11= Communicate on PGEC1 and PGED1
10= Communicate on PGEC2 and PGED2
01= Communicate on PGEC3 and PGED3
00= Reserved, do not use
Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices.
DS70292D-page 302
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
27.2 On-Chip Voltage Regulator
27.3 BOR: Brown-out Reset
All
of
the
dsPIC33FJ32GP302/304,
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage VCAP/VDDCORE. The main pur-
pose of the BOR module is to generate a device Reset
when a brown-out condition occurs. Brown-out condi-
tions are generally caused by glitches on the AC mains
(for example, missing portions of the AC cycle wave-
form due to bad power transmission lines, or voltage
sags due to excessive current draw when a large
inductive load is turned on).
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 devices power their core digital logic at a nominal
2.5V. This can create a conflict for designs that are
required to operate at a higher typical voltage, such as
3.3V. To simplify system design, all devices in the
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 family incorporate an
on-chip regulator that allows the device to run its core
logic from VDD.
The regulator provides power to the core from the other
VDD pins. When the regulator is enabled, a low-ESR
(less than 5 Ohms) capacitor (such as tantalum or
ceramic) must be connected to the VCAP/VDDCORE pin
(Figure 27-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 30-13 located in Section 30.1
“DC Characteristics”.
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Note:
It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP/VDDCORE pin.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
On a POR, it takes approximately 20 s for the on-chip
voltage regulator to generate an output voltage. During
this time, designated as TSTARTUP, code execution is
disabled. TSTARTUP is applied every time the device
resumes operation after any power-down.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
FIGURE 27-1:
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR(1)
3.3V
dsPIC33F
VDD
VCAP/VDDCORE
VSS
CEFC
Note 1: These are typical operating voltages. Refer
to Section TABLE 30-13: “Internal Volt-
age Regulator Specifications” located in
Section 30.1 “DC Characteristics” for
the full operating ranges of VDD and VCAP/
VDDCORE.
2: It is important for the low-ESR capacitor to
be placed as close as possible to the
VCAP/VDDCORE pin.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 303
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
27.4.2
SLEEP AND IDLE MODES
27.4 Watchdog Timer (WDT)
If the WDT is enabled, it continues to run during Sleep or
Idle modes. When the WDT time-out occurs, the device
wakes the device and code execution continues from
where the PWRSAVinstruction was executed. The corre-
sponding SLEEP or IDLE bits (RCON<3,2>) needs to be
cleared in software after the device wakes up.
For dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices, the WDT
is driven by the LPRC oscillator. When the WDT is
enabled, the clock source is also enabled.
27.4.1
PRESCALER/POSTSCALER
The nominal WDT clock source from LPRC is 32 kHz.
This feeds a prescaler than can be configured for either
5-bit (divide-by-32) or 7-bit (divide-by-128) operation.
The prescaler is set by the WDTPRE Configuration bit.
With a 32 kHz input, the prescaler yields a nominal
WDT time-out period (TWDT) of 1 ms in 5-bit mode, or
4 ms in 7-bit mode.
27.4.3
ENABLING WDT
The WDT is enabled or disabled by the FWDTEN
Configuration bit in the FWDT Configuration register.
When the FWDTEN Configuration bit is set, the WDT is
always enabled.
The WDT can be optionally controlled in software
when the FWDTEN Configuration bit has been
programmed to ‘0’. The WDT is enabled in software
by setting the SWDTEN control bit (RCON<5>). The
SWDTEN control bit is cleared on any device Reset.
The software WDT option allows the user application
to enable the WDT for critical code segments and
disable the WDT during non-critical segments for
maximum power savings.
A variable postscaler divides down the WDT prescaler
output and allows for a wide range of time-out periods.
The postscaler is controlled by the WDTPOST<3:0>
Configuration bits (FWDT<3:0>), which allow the selec-
tion of 16 settings, from 1:1 to 1:32,768. Using the pres-
caler and postscaler, time-out periods ranging from
1 ms to 131 seconds can be achieved.
The WDT, prescaler and postscaler are reset:
• On any device Reset
Note:
If the WINDIS bit (FWDT<6>) is cleared, the
CLRWDTinstruction should be executed by
the application software only during the last
1/4 of the WDT period. This CLRWDT win-
dow can be determined by using a timer. If
a CLRWDT instruction is executed before
this window, a WDT Reset occurs.
• On the completion of a clock switch, whether
invoked by software (i.e., setting the OSWEN bit
after changing the NOSC bits) or by hardware
(i.e., Fail-Safe Clock Monitor)
• When a PWRSAVinstruction is executed
(i.e., Sleep or Idle mode is entered)
The WDT flag bit, WDTO (RCON<4>), is not automatically
cleared following a WDT time-out. To detect subsequent
WDT events, the flag must be cleared in software.
• When the device exits Sleep or Idle mode to
resume normal operation
• By a CLRWDTinstruction during normal execution
Note:
The CLRWDT and PWRSAV instructions
clear the prescaler and postscaler counts
when executed.
FIGURE 27-2:
WDT BLOCK DIAGRAM
All Device Resets
Transition to New Clock Source
Exit Sleep or Idle Mode
PWRSAVInstruction
CLRWDTInstruction
Watchdog Timer
Sleep/Idle
WDTPRE
WDTPOST<3:0>
SWDTEN
FWDTEN
WDT
Wake-up
1
RS
RS
Prescaler
(divide by N1)
Postscaler
WDT
Reset
LPRC Clock
(divide by N2)
0
WDT Window Select
WINDIS
CLRWDTInstruction
DS70292D-page 304
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
27.5 JTAG Interface
27.8 Code Protection and
CodeGuard™ Security
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 devices implement a
JTAG interface, which supports boundary scan device
testing, as well as in-circuit programming. Detailed
information on this interface is provided in future
revisions of the document.
The
dsPIC33FJ64GPX02/X04
and
dsPIC33FJ128GPX02/X04 devices offer advanced
implementation of CodeGuard Security that supports
BS, SS and GS while, the dsPIC33FJ32GP302/304
devices offer the intermediate level of CodeGuard
Security that supports only BS and GS. CodeGuard
Security enables multiple parties to securely share
resources (memory, interrupts and peripherals) on a
single chip. This feature helps protect individual
Intellectual Property in collaborative system designs.
Note:
Refer to Section 24. “Programming and
Diagnostics” (DS70207) of the
“dsPIC33F/PIC24H Family Reference
Manual” for further information on usage,
configuration and operation of the JTAG
interface.
When coupled with software encryption libraries,
CodeGuard Security can be used to securely update
Flash even when multiple IPs reside on the single chip.
The code protection features vary depending on the
actual dsPIC33F implemented. The following sections
provide an overview of these features.
27.6
In-Circuit Serial Programming
The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/
X04, and dsPIC33FJ128GPX02/X04 devices can be
serially programmed while in the end application circuit.
This is done with two lines for clock and data and three
other lines for power, ground and the programming
sequence. Serial programming allows customers to
manufacture boards with unprogrammed devices and
then program the digital signal controller just before
shipping the product. Serial programming also allows
the most recent firmware or a custom firmware to be
programmed. Refer to the “dsPIC33F/PIC24H Flash
Programming Specification” (DS70152) for details
about In-Circuit Serial Programming (ICSP).
Secure segment and RAM protection is implemented
on
the
dsPIC33FJ64GPX02/X04
devices.
and
The
dsPIC33FJ128GPX02/X04
dsPIC33FJ32GP302/304 devices do not support
secure segment and RAM protection.
Note:
Refer to Section 23. “CodeGuard™
Security” (DS70199) of the “dsPIC33F/
PIC24H Family Reference Manual” for
further
information
on
usage,
configuration and operation of CodeGuard
Security.
Any of the three pairs of programming clock/data pins
can be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
27.7 In-Circuit Debugger
When MPLAB® ICD 2 is selected as a debugger, the in-
circuit debugging functionality is enabled. This function
allows simple debugging functions when used with
MPLAB IDE. Debugging functionality is controlled
through the PGECx (Emulation/Debug Clock) and
PGEDx (Emulation/Debug Data) pin functions.
Any of the three pairs of debugging clock/data pins can
be used:
• PGEC1 and PGED1
• PGEC2 and PGED2
• PGEC3 and PGED3
To use the in-circuit debugger function of the device,
the design must implement ICSP connections to
MCLR, VDD, VSS, PGC, PGD and the PGECx and
PGEDx pin pairs. In addition, when the feature is
enabled, some of the resources are not available for
general use. These resources include the first 80 bytes
of data RAM and two I/O pins.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 305
TABLE 27-3: CODE FLASH SECURITY SEGMENT SIZES FOR 32 KB DEVICES
CONFIG BITS
BSS<2:0> = x11 0K
BSS<2:0> = x10 1K
BSS<2:0> = x01 4K
BSS<2:0> = x00 8K
0x000000h
0x000000h
0x000000h
0x000000h
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x0057FEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x0057FEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x0057FEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x0057FEh
SSS<2:0> = x11
0K
GS = 11008 IW
GS = 10240 IW
GS = 7168 IW
GS = 3072 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
TABLE 27-4: CODE FLASH SECURITY SEGMENT SIZES FOR 64 KB DEVICES
CONFIG BITS
BSS<2:0> = x11 0K
BSS<2:0> = x10 1K
BSS<2:0> = x01 4K
BSS<2:0> = x00 8K
0x000000h
0x000000h
0x000000h
0x000000h
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
SSS<2:0> = x11
0K
GS = 21760 IW
GS = 20992 IW
GS = 17920 IW
GS = 13824 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
VS = 256 IW
SS = 3840 IW
VS = 256 IW
BS = 768 IW
SS = 3072 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
SSS<2:0> = x10
4K
GS = 17920 IW
VS = 256 IW
GS = 17920 IW
GS = 17920 IW
GS = 13824 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
SSS<2:0> = x01
SS = 7936 IW
SS = 7168 IW
SS = 4096 IW
8K
GS = 13824 IW
GS = 13824 IW
GS = 13824 IW
GS = 13824 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
SSS<2:0> = x00
SS = 16128 IW
GS = 5632 IW
SS = 15360 IW
GS = 5632 IW
SS = 12288 IW
GS = 5632 IW
SS = 8192 IW
GS = 5632 IW
16K
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
TABLE 27-5: CODE FLASH SECURITY SEGMENT SIZES FOR 128 KB DEVICES
CONFIG BITS
BSS<2:0> = x11 0K
BSS<2:0> = x10 1K
BSS<2:0> = x01 4K
BSS<2:0> = x00 8K
0x000000h
0x000000h
0x000000h
0x000000h
VS = 256 IW
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x0001FEh
0x000200h
0x0007FEh
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
SSS<2:0> = x11
0x003FFEh
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
0x004000h
0K
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
GS = 43776 IW
GS = 43008 IW
GS = 39936 IW
GS = 35840 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
0x000000h
0x000000h
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x000000h
VS = 256 IW
SS = 3840 IW
VS = 256 IW
BS = 768 IW
SS = 3072 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
0x0001FEh
0x000200h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00ABFEh
SSS<2:0> = x10
0x003FFEh
0x004000h
4K
0x007FFEh
0x008000h
0x00ABFEh
GS = 39936 IW
VS = 256 IW
GS = 39936 IW
GS = 39936 IW
GS = 35840 IW
0x0157FEh
0x000000h
0x0157FEh
0x000000h
0x0157FEh
0x0157FEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
SSS<2:0> = x01
SS = 7936 IW
SS = 7168 IW
SS = 4096 IW
8K
0x007FFEh
0x008000h
0x008000h
0x00FFFEh
0x010000h
0x00FFFEh
0x010000h
GS = 35840 IW
VS = 256 IW
GS = 35840 IW
GS = 35840 IW
GS = 35840 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
0x000000h
0x0001FEh
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
0x000000h
0x0001FEh
VS = 256 IW
BS = 768 IW
VS = 256 IW
BS = 3840 IW
VS = 256 IW
BS = 7936 IW
0x000200h
0x0007FEh
0x000800h
0x001FFEh
0x002000h
0x003FFEh
SSS<2:0> = x00
0x004000h
0x007FFEh
0x008000h
0x00FFFEh
0x010000h
SS = 16128 IW
GS = 27648 IW
SS = 15360 IW
GS = 27648 IW
SS = 12288 IW
GS = 27648 IW
SS = 8192 IW
16K
GS = 27648 IW
0x0157FEh
0x0157FEh
0x0157FEh
0x0157FEh
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Most bit-oriented instructions (including simple rotate/
shift instructions) have two operands:
28.0 INSTRUCTION SET SUMMARY
Note:
This data sheet summarizes the features
of the dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
• The W register (with or without an address
modifier) or file register (specified by the value of
‘Ws’ or ‘f’)
dsPIC33FJ128GPX02/X04 families of
devices. It is not intended to be a compre-
hensive reference source. To complement
the information in this data sheet, refer to
the “dsPIC33F/PIC24H Family Reference
Manual”. Please see the Microchip web
site (www.microchip.com) for the latest
dsPIC33F/PIC24H Family Reference
Manual sections.
• The bit in the W register or file register (specified
by a literal value or indirectly by the contents of
register ‘Wb’)
The literal instructions that involve data movement can
use some of the following operands:
• A literal value to be loaded into a W register or file
register (specified by ‘k’)
• The W register or file register where the literal
value is to be loaded (specified by ‘Wb’ or ‘f’)
The dsPIC33F instruction set is identical to that of the
dsPIC30F.
However, literal instructions that involve arithmetic or
logical operations use some of the following operands:
Most instructions are a single program memory word
(24 bits). Only three instructions require two program
memory locations.
• The first source operand, which is a register ‘Wb’
without any address modifier
Each single-word instruction is a 24-bit word, divided
into an 8-bit opcode, which specifies the instruction
type and one or more operands, which further specify
the operation of the instruction.
• The second source operand, which is a literal
value
• The destination of the result (only if not the same
as the first source operand), which is typically a
register ‘Wd’ with or without an address modifier
The instruction set is highly orthogonal and is grouped
into five basic categories:
The MACclass of DSP instructions can use some of the
following operands:
• Word or byte-oriented operations
• Bit-oriented operations
• Literal operations
• The accumulator (A or B) to be used (required
operand)
• The W registers to be used as the two operands
• The X and Y address space prefetch operations
• The X and Y address space prefetch destinations
• The accumulator write back destination
• DSP operations
• Control operations
Table 28-1 shows the general symbols used in
describing the instructions.
The other DSP instructions do not involve any
multiplication and can include:
The dsPIC33F instruction set summary in Table 28-2
lists all the instructions, along with the status flags
affected by each instruction.
• The accumulator to be used (required)
Most word or byte-oriented W register instructions
(including barrel shift instructions) have three
operands:
• The source or destination operand (designated as
Wso or Wdo, respectively) with or without an
address modifier
• The amount of shift specified by a W register ‘Wn’
or a literal value
• The first source operand, which is typically a
register ‘Wb’ without any address modifier
• The second source operand, which is typically a
register ‘Ws’ with or without an address modifier
The control instructions can use some of the following
operands:
• The destination of the result, which is typically a
register ‘Wd’ with or without an address modifier
• A program memory address
• The mode of the table read and table write
instructions
However, word or byte-oriented file register instructions
have two operands:
• The file register specified by the value ‘f’
• The destination, which could be either the file
register ‘f’ or the W0 register, which is denoted as
‘WREG’
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 309
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Most instructions are a single word. Certain double-
word instructions are designed to provide all the
required information in these 48 bits. In the second
word, the 8 MSbs are ‘0’s. If this second word is exe-
cuted as an instruction (by itself), it executes as a NOP.
tional/computed branch), indirect CALL/GOTO, all table
reads and writes and RETURN/RETFIE instructions,
which are single-word instructions but take two or three
cycles. Certain instructions that involve skipping over the
subsequent instruction require either two or three cycles
if the skip is performed, depending on whether the
instruction being skipped is a single-word or two-word
instruction. Moreover, double-word moves require two
cycles.
The double-word instructions execute in two instruction
cycles.
Most single-word instructions are executed in a single
instruction cycle, unless a conditional test is true, or the
program counter is changed as a result of the instruc-
tion. In these cases, the execution takes two instruction
cycles with the additional instruction cycle(s) executed
as a NOP. Notable exceptions are the BRA (uncondi-
Note:
For more details on the instruction set,
refer to the “16-bit MCU and DSC Pro-
grammer’s
Reference
Manual”
(DS70157).
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS
Field
Description
#text
(text)
[text]
{ }
Means literal defined by “text”
Means “content of text”
Means “the location addressed by text”
Optional field or operation
Register bit field
<n:m>
.b
Byte mode selection
.d
Double-Word mode selection
Shadow register select
.S
.w
Word mode selection (default)
One of two accumulators {A, B}
Acc
AWB
bit4
Accumulator write back destination address register {W13, [W13]+ = 2}
4-bit bit selection field (used in word addressed instructions) {0...15}
MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero
Absolute address, label or expression (resolved by the linker)
File register address {0x0000...0x1FFF}
C, DC, N, OV, Z
Expr
f
lit1
1-bit unsigned literal {0,1}
lit4
4-bit unsigned literal {0...15}
lit5
5-bit unsigned literal {0...31}
lit8
8-bit unsigned literal {0...255}
lit10
10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode
14-bit unsigned literal {0...16384}
lit14
lit16
16-bit unsigned literal {0...65535}
lit23
23-bit unsigned literal {0...8388608}; LSb must be ‘0’
Field does not require an entry, can be blank
DSP Status bits: ACCA Overflow, ACCB Overflow, ACCA Saturate, ACCB Saturate
Program Counter
None
OA, OB, SA, SB
PC
Slit10
Slit16
Slit6
Wb
10-bit signed literal {-512...511}
16-bit signed literal {-32768...32767}
6-bit signed literal {-16...16}
Base W register {W0...W15}
Wd
Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] }
Wdo
Destination W register
{ Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] }
Wm,Wn
Dividend, Divisor working register pair (direct addressing)
Wm*Wm
Multiplicand and Multiplier working register pair for Square instructions
{W4 * W4,W5 * W5,W6 * W6,W7 * W7}
DS70292D-page 310
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 28-1: SYMBOLS USED IN OPCODE DESCRIPTIONS (CONTINUED)
Field
Description
Wm*Wn
Multiplicand and Multiplier working register pair for DSP instructions
{W4 * W5,W4 * W6,W4 * W7,W5 * W6,W5 * W7,W6 * W7}
Wn
One of 16 working registers {W0...W15}
Wnd
Wns
WREG
Ws
One of 16 destination working registers {W0...W15}
One of 16 source working registers {W0...W15}
W0 (working register used in file register instructions)
Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] }
Wso
Source W register
{ Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
Wx
X data space prefetch address register for DSP instructions
{[W8] + = 6, [W8] + = 4, [W8] + = 2, [W8], [W8] - = 6, [W8] - = 4, [W8] - = 2,
[W9] + = 6, [W9] + = 4, [W9] + = 2, [W9], [W9] - = 6, [W9] - = 4, [W9] - = 2,
[W9 + W12], none}
Wxd
Wy
X data space prefetch destination register for DSP instructions {W4...W7}
Y data space prefetch address register for DSP instructions
{[W10] + = 6, [W10] + = 4, [W10] + = 2, [W10], [W10] - = 6, [W10] - = 4, [W10] - = 2,
[W11] + = 6, [W11] + = 4, [W11] + = 2, [W11], [W11] - = 6, [W11] - = 4, [W11] - = 2,
[W11 + W12], none}
Wyd
Y data space prefetch destination register for DSP instructions {W4...W7}
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 311
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 28-2: INSTRUCTION SET OVERVIEW
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
1
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADD
ADDC
ADDC
ADDC
ADDC
ADDC
AND
AND
AND
AND
AND
ASR
ASR
ASR
ASR
ASR
BCLR
BCLR
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BRA
BSET
BSET
BSW.C
BSW.Z
BTG
BTG
Acc
Add Accumulators
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,SA,SB
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
f
f = f + WREG
f,WREG
WREG = f + WREG
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
f
Wd = lit10 + Wd
1
Wd = Wb + Ws
1
Wd = Wb + lit5
1
16-bit Signed Add to Accumulator
f = f + WREG + (C)
1
2
3
4
ADDC
AND
1
f,WREG
WREG = f + WREG + (C)
Wd = lit10 + Wd + (C)
Wd = Wb + Ws + (C)
Wd = Wb + lit5 + (C)
1
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
1
1
f = f .AND. WREG
1
f,WREG
WREG = f .AND. WREG
Wd = lit10 .AND. Wd
Wd = Wb .AND. Ws
1
N,Z
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
1
N,Z
1
N,Z
Wd = Wb .AND. lit5
1
N,Z
ASR
f = Arithmetic Right Shift f
WREG = Arithmetic Right Shift f
Wd = Arithmetic Right Shift Ws
Wnd = Arithmetic Right Shift Wb by Wns
Wnd = Arithmetic Right Shift Wb by lit5
Bit Clear f
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
1
Ws,Wd
1
Wb,Wns,Wnd
Wb,#lit5,Wnd
f,#bit4
Ws,#bit4
C,Expr
1
1
N,Z
5
6
BCLR
BRA
1
None
Bit Clear Ws
1
None
Branch if Carry
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
1 (2)
2
None
GE,Expr
GEU,Expr
GT,Expr
GTU,Expr
LE,Expr
LEU,Expr
LT,Expr
LTU,Expr
N,Expr
Branch if greater than or equal
Branch if unsigned greater than or equal
Branch if greater than
Branch if unsigned greater than
Branch if less than or equal
Branch if unsigned less than or equal
Branch if less than
None
None
None
None
None
None
None
Branch if unsigned less than
Branch if Negative
None
None
NC,Expr
NN,Expr
NOV,Expr
NZ,Expr
OA,Expr
OB,Expr
OV,Expr
SA,Expr
SB,Expr
Expr
Branch if Not Carry
None
Branch if Not Negative
Branch if Not Overflow
Branch if Not Zero
None
None
None
Branch if Accumulator A overflow
Branch if Accumulator B overflow
Branch if Overflow
None
None
None
Branch if Accumulator A saturated
Branch if Accumulator B saturated
Branch Unconditionally
Branch if Zero
None
None
None
Z,Expr
1 (2)
2
None
Wn
Computed Branch
None
7
8
9
BSET
BSW
f,#bit4
Ws,#bit4
Ws,Wb
Bit Set f
1
None
Bit Set Ws
1
None
Write C bit to Ws<Wb>
Write Z bit to Ws<Wb>
Bit Toggle f
1
None
Ws,Wb
1
None
BTG
f,#bit4
Ws,#bit4
1
None
Bit Toggle Ws
1
None
DS70292D-page 312
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
10
BTSC
BTSS
BTST
BTSC
BTSC
BTSS
BTSS
f,#bit4
Ws,#bit4
f,#bit4
Ws,#bit4
Bit Test f, Skip if Clear
1
1
1
1
1
None
None
None
None
(2 or 3)
Bit Test Ws, Skip if Clear
Bit Test f, Skip if Set
1
(2 or 3)
11
12
1
(2 or 3)
Bit Test Ws, Skip if Set
1
(2 or 3)
BTST
f,#bit4
Ws,#bit4
Ws,#bit4
Ws,Wb
Bit Test f
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
Z
BTST.C
BTST.Z
BTST.C
BTST.Z
BTSTS
Bit Test Ws to C
Bit Test Ws to Z
Bit Test Ws<Wb> to C
Bit Test Ws<Wb> to Z
Bit Test then Set f
Bit Test Ws to C, then Set
Bit Test Ws to Z, then Set
Call subroutine
C
Z
C
Ws,Wb
Z
13
BTSTS
f,#bit4
Z
C
BTSTS.C Ws,#bit4
BTSTS.Z Ws,#bit4
Z
14
15
CALL
CLR
CALL
CALL
CLR
lit23
None
Wn
Call indirect subroutine
f = 0x0000
None
f
None
CLR
WREG
WREG = 0x0000
Ws = 0x0000
None
CLR
Ws
None
CLR
Acc,Wx,Wxd,Wy,Wyd,AWB
Clear Accumulator
Clear Watchdog Timer
f = f
OA,OB,SA,SB
WDTO,Sleep
N,Z
16
17
CLRWDT
COM
CLRWDT
COM
f
COM
COM
CP
f,WREG
Ws,Wd
f
WREG = f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
N,Z
Wd = Ws
N,Z
18
CP
Compare f with WREG
Compare Wb with lit5
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
CP
Wb,#lit5
Wb,Ws
f
CP
Compare Wb with Ws (Wb – Ws)
Compare f with 0x0000
Compare Ws with 0x0000
Compare f with WREG, with Borrow
Compare Wb with lit5, with Borrow
19
20
CP0
CPB
CP0
CP0
CPB
CPB
CPB
Ws
f
Wb,#lit5
Wb,Ws
Compare Wb with Ws, with Borrow
(Wb – Ws – C)
21
22
23
24
CPSEQ
CPSGT
CPSLT
CPSNE
CPSEQ
CPSGT
CPSLT
CPSNE
Wb, Wn
Wb, Wn
Wb, Wn
Wb, Wn
Compare Wb with Wn, skip if =
Compare Wb with Wn, skip if >
Compare Wb with Wn, skip if <
Compare Wb with Wn, skip if
1
1
1
1
1
None
None
None
None
(2 or 3)
1
(2 or 3)
1
(2 or 3)
1
(2 or 3)
25
26
DAW
DEC
DAW
Wn
Wn = decimal adjust Wn
f = f – 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C
DEC
f
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
DEC
f,WREG
Ws,Wd
f
WREG = f – 1
DEC
Wd = Ws – 1
27
28
DEC2
DISI
DEC2
DEC2
DEC2
DISI
f = f – 2
f,WREG
Ws,Wd
#lit14
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k instruction cycles
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 313
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
29
DIV
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
Wm,Wn
Signed 16/16-bit Integer Divide
1
1
1
1
1
2
2
1
18
18
18
18
18
2
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
None
Wm,Wn
Signed 32/16-bit Integer Divide
Wm,Wn
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit14 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
Wm,Wn
30
31
DIVF
DO
Wm,Wn
#lit14,Expr
Wn,Expr
DO
2
None
32
33
ED
ED
Wm*Wm,Acc,Wx,Wy,Wxd
1
OA,OB,OAB,
SA,SB,SAB
EDAC
EDAC
Wm*Wm,Acc,Wx,Wy,Wxd
Euclidean Distance
1
1
OA,OB,OAB,
SA,SB,SAB
34
35
36
37
38
EXCH
FBCL
FF1L
FF1R
GOTO
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
INC
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
1
1
1
1
1
1
None
C
C
C
None
Wn
Go to indirect
None
39
40
41
INC
f
f = f + 1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
N,Z
INC
f,WREG
Ws,Wd
WREG = f + 1
INC
Wd = Ws + 1
INC2
IOR
INC2
INC2
INC2
IOR
f
f = f + 2
f,WREG
Ws,Wd
WREG = f + 2
Wd = Ws + 2
f
f = f .IOR. WREG
IOR
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
N,Z
IOR
N,Z
IOR
N,Z
IOR
N,Z
42
LAC
LAC
OA,OB,OAB,
SA,SB,SAB
43
44
LNK
LSR
LNK
LSR
LSR
LSR
LSR
LSR
MAC
#lit14
Link Frame Pointer
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f
f = Logical Right Shift f
f,WREG
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
N,Z
45
46
MAC
MOV
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply and Accumulate
,
AWB
OA,OB,OAB,
SA,SB,SAB
MAC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square and Accumulate
1
1
OA,OB,OAB,
SA,SB,SAB
MOV
f,Wn
Move f to Wn
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
None
N,Z
MOV
f
Move f to f
MOV
f,WREG
Move f to WREG
N,Z
MOV
#lit16,Wn
#lit8,Wn
Wn,f
Move 16-bit literal to Wn
Move 8-bit literal to Wn
Move Wn to f
None
None
None
None
N,Z
MOV.b
MOV
MOV
Wso,Wdo
Move Ws to Wd
MOV
WREG,f
Move WREG to f
MOV.D
MOV.D
MOVSAC
Wns,Wd
Move Double from W(ns):W(ns + 1) to Wd
Move Double from Ws to W(nd + 1):W(nd)
Prefetch and store accumulator
None
None
None
Ws,Wnd
47
MOVSAC
Acc,Wx,Wxd,Wy,Wyd,AWB
DS70292D-page 314
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
48
MPY
MPY
Multiply Wm by Wn to Accumulator
Square Wm to Accumulator
1
1
1
1
1
1
1
1
OA,OB,OAB,
SA,SB,SAB
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MPY
OA,OB,OAB,
SA,SB,SAB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
49
50
MPY.N
MSC
MPY.N
-(Multiply Wm by Wn) to Accumulator
None
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd
MSC
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Multiply and Subtract from Accumulator
OA,OB,OAB,
SA,SB,SAB
,
AWB
51
MUL
MUL.SS
MUL.SU
MUL.US
MUL.UU
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
Wb,Ws,Wnd
{Wnd + 1, Wnd} = signed(Wb) * signed(Ws)
{Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws)
{Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws)
1
1
1
1
1
1
1
1
None
None
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(Ws)
MUL.SU
MUL.UU
Wb,#lit5,Wnd
Wb,#lit5,Wnd
{Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5)
1
1
1
1
None
None
{Wnd + 1, Wnd} = unsigned(Wb) *
unsigned(lit5)
MUL
NEG
f
W3:W2 = f * WREG
Negate Accumulator
1
1
1
1
None
52
NEG
Acc
OA,OB,OAB,
SA,SB,SAB
NEG
f
f = f + 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
None
NEG
f,WREG
Ws,Wd
WREG = f + 1
NEG
Wd = Ws + 1
53
54
NOP
POP
NOP
No Operation
NOPR
POP
No Operation
None
f
Pop f from Top-of-Stack (TOS)
Pop from Top-of-Stack (TOS) to Wdo
None
POP
Wdo
Wnd
None
POP.D
Pop from Top-of-Stack (TOS) to
W(nd):W(nd + 1)
None
POP.S
PUSH
Pop Shadow Registers
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
All
None
None
None
None
WDTO,Sleep
None
None
None
None
None
None
None
None
C,N,Z
C,N,Z
C,N,Z
N,Z
55
PUSH
f
Push f to Top-of-Stack (TOS)
Push Wso to Top-of-Stack (TOS)
Push W(ns):W(ns + 1) to Top-of-Stack (TOS)
Push Shadow Registers
PUSH
Wso
Wns
1
PUSH.D
PUSH.S
PWRSAV
RCALL
RCALL
REPEAT
REPEAT
RESET
RETFIE
RETLW
RETURN
RLC
2
1
56
57
PWRSAV
RCALL
#lit1
Expr
Wn
Go into Sleep or Idle mode
1
Relative Call
2
Computed Call
2
58
REPEAT
#lit14
Wn
Repeat Next Instruction lit14 + 1 times
Repeat Next Instruction (Wn) + 1 times
Software device Reset
1
1
59
60
61
62
63
RESET
RETFIE
RETLW
RETURN
RLC
1
Return from interrupt
3 (2)
3 (2)
3 (2)
1
#lit10,Wn
Return with literal in Wn
Return from Subroutine
f
f = Rotate Left through Carry f
WREG = Rotate Left through Carry f
Wd = Rotate Left through Carry Ws
f = Rotate Left (No Carry) f
RLC
f,WREG
Ws,Wd
f
1
RLC
1
64
65
66
RLNC
RRC
RLNC
1
RLNC
f,WREG
Ws,Wd
f
WREG = Rotate Left (No Carry) f
Wd = Rotate Left (No Carry) Ws
f = Rotate Right through Carry f
WREG = Rotate Right through Carry f
Wd = Rotate Right through Carry Ws
f = Rotate Right (No Carry) f
WREG = Rotate Right (No Carry) f
Wd = Rotate Right (No Carry) Ws
1
N,Z
RLNC
1
N,Z
RRC
1
C,N,Z
C,N,Z
C,N,Z
N,Z
RRC
f,WREG
Ws,Wd
f
1
RRC
1
RRNC
RRNC
1
RRNC
f,WREG
Ws,Wd
1
N,Z
RRNC
1
N,Z
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 315
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 28-2: INSTRUCTION SET OVERVIEW (CONTINUED)
Base
Instr
#
Assembly
Mnemonic
# of
# of
Status Flags
Affected
Assembly Syntax
Description
Words Cycles
67
SAC
SAC
Acc,#Slit4,Wdo
Store Accumulator
1
1
1
1
1
1
1
1
1
1
1
1
1
1
None
None
C,N,Z
None
None
None
SAC.R
SE
Acc,#Slit4,Wdo
Store Rounded Accumulator
Wnd = sign-extended Ws
f = 0xFFFF
68
69
SE
Ws,Wnd
f
SETM
SETM
SETM
SETM
SFTAC
WREG
Ws
WREG = 0xFFFF
Ws = 0xFFFF
70
71
SFTAC
SL
Acc,Wn
Arithmetic Shift Accumulator by (Wn)
OA,OB,OAB,
SA,SB,SAB
SFTAC
Acc,#Slit6
Arithmetic Shift Accumulator by Slit6
1
1
OA,OB,OAB,
SA,SB,SAB
SL
SL
SL
SL
SL
SUB
f
f = Left Shift f
1
1
1
1
1
1
1
1
1
1
1
1
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
N,Z
f,WREG
Ws,Wd
WREG = Left Shift f
Wd = Left Shift Ws
Wb,Wns,Wnd
Wb,#lit5,Wnd
Acc
Wnd = Left Shift Wb by Wns
Wnd = Left Shift Wb by lit5
Subtract Accumulators
N,Z
72
SUB
OA,OB,OAB,
SA,SB,SAB
SUB
SUB
SUB
SUB
SUB
SUBB
SUBB
f
f = f – WREG
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
WREG = f – WREG
Wn = Wn – lit10
Wd = Wb – Ws
Wd = Wb – lit5
73
SUBB
f = f – WREG – (C)
WREG = f – WREG – (C)
f,WREG
SUBB
SUBB
SUBB
SUBR
SUBR
SUBR
SUBR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
f
Wn = Wn – lit10 – (C)
Wd = Wb – Ws – (C)
Wd = Wb – lit5 – (C)
f = WREG – f
1
1
1
1
1
1
1
1
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
74
75
SUBR
f,WREG
WREG = WREG – f
Wd = Ws – Wb
Wb,Ws,Wd
Wb,#lit5,Wd
Wd = lit5 – Wb
SUBBR
SUBBR
SUBBR
SUBBR
f
f = WREG – f – (C)
1
1
1
1
1
1
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
f,WREG
Wb,Ws,Wd
WREG = WREG – f – (C)
Wd = Ws – Wb – (C)
SUBBR
SWAP.b
SWAP
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
XOR
Wb,#lit5,Wd
Wn
Wd = lit5 – Wb – (C)
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
1
1
1
1
1
1
1
C,DC,N,OV,Z
None
None
None
None
None
None
None
N,Z
76
SWAP
Wn = nibble swap Wn
Wn = byte swap Wn
Wn
77
78
79
80
81
82
TBLRDH
TBLRDL
TBLWTH
TBLWTL
ULNK
Ws,Wd
Ws,Wd
Ws,Wd
Ws,Wd
Read Prog<23:16> to Wd<7:0>
Read Prog<15:0> to Wd
Write Ws<7:0> to Prog<23:16>
Write Ws to Prog<15:0>
Unlink Frame Pointer
f = f .XOR. WREG
XOR
f
XOR
f,WREG
WREG = f .XOR. WREG
Wd = lit10 .XOR. Wd
Wd = Wb .XOR. Ws
N,Z
XOR
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Ws,Wnd
N,Z
XOR
N,Z
XOR
Wd = Wb .XOR. lit5
N,Z
83
ZE
ZE
Wnd = Zero-extend Ws
C,Z,N
DS70292D-page 316
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
29.1 MPLAB Integrated Development
Environment Software
29.0 DEVELOPMENT SUPPORT
The PIC® microcontrollers and dsPIC® digital signal
controllers are supported with a full range of software
and hardware development tools:
The MPLAB IDE software brings an ease of software
development previously unseen in the 8/16/32-bit
microcontroller market. The MPLAB IDE is a Windows®
operating system-based application that contains:
• Integrated Development Environment
- MPLAB® IDE Software
• A single graphical interface to all debugging tools
- Simulator
• Compilers/Assemblers/Linkers
- MPLAB C Compiler for Various Device
Families
- Programmer (sold separately)
- In-Circuit Emulator (sold separately)
- In-Circuit Debugger (sold separately)
• A full-featured editor with color-coded context
• A multiple project manager
- HI-TECH C for Various Device Families
- MPASMTM Assembler
- MPLINKTM Object Linker/
MPLIBTM Object Librarian
- MPLAB Assembler/Linker/Librarian for
Various Device Families
• Customizable data windows with direct edit of
contents
• Simulators
• High-level source code debugging
• Mouse over variable inspection
- MPLAB SIM Software Simulator
• Emulators
• Drag and drop variables from source to watch
windows
- MPLAB REAL ICE™ In-Circuit Emulator
• In-Circuit Debuggers
• Extensive on-line help
• Integration of select third party tools, such as
IAR C Compilers
- MPLAB ICD 3
- PICkit™ 3 Debug Express
• Device Programmers
- PICkit™ 2 Programmer
- MPLAB PM3 Device Programmer
The MPLAB IDE allows you to:
• Edit your source files (either C or assembly)
• One-touch compile or assemble, and download to
emulator and simulator tools (automatically
updates all project information)
• Low-Cost Demonstration/Development Boards,
Evaluation Kits, and Starter Kits
• Debug using:
- Source files (C or assembly)
- Mixed C and assembly
- Machine code
MPLAB IDE supports multiple debugging tools in a
single development paradigm, from the cost-effective
simulators, through low-cost in-circuit debuggers, to
full-featured emulators. This eliminates the learning
curve when upgrading to tools with increased flexibility
and power.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 317
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
29.2 MPLAB C Compilers for Various
Device Families
29.5 MPLINK Object Linker/
MPLIB Object Librarian
The MPLAB C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC18,
PIC24 and PIC32 families of microcontrollers and the
dsPIC30 and dsPIC33 families of digital signal control-
lers. These compilers provide powerful integration
capabilities, superior code optimization and ease of
use.
The MPLINK Object Linker combines relocatable
objects created by the MPASM Assembler and the
MPLAB C18 C Compiler. It can link relocatable objects
from precompiled libraries, using directives from a
linker script.
The MPLIB Object Librarian manages the creation and
modification of library files of precompiled code. When
a routine from a library is called from a source file, only
the modules that contain that routine will be linked in
with the application. This allows large libraries to be
used efficiently in many different applications.
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
29.3 HI-TECH C for Various Device
Families
The object linker/library features include:
• Efficient linking of single libraries instead of many
smaller files
The HI-TECH C Compiler code development systems
are complete ANSI C compilers for Microchip’s PIC
family of microcontrollers and the dsPIC family of digital
signal controllers. These compilers provide powerful
integration capabilities, omniscient code generation
and ease of use.
• Enhanced code maintainability by grouping
related modules together
• Flexible creation of libraries with easy module
listing, replacement, deletion and extraction
29.6 MPLAB Assembler, Linker and
Librarian for Various Device
Families
For easy source level debugging, the compilers provide
symbol information that is optimized to the MPLAB IDE
debugger.
The compilers include a macro assembler, linker, pre-
processor, and one-step driver, and can run on multiple
platforms.
MPLAB Assembler produces relocatable machine
code from symbolic assembly language for PIC24,
PIC32 and dsPIC devices. MPLAB C Compiler uses
the assembler to produce its object file. The assembler
generates relocatable object files that can then be
archived or linked with other relocatable object files and
archives to create an executable file. Notable features
of the assembler include:
29.4 MPASM Assembler
The MPASM Assembler is a full-featured, universal
macro assembler for PIC10/12/16/18 MCUs.
The MPASM Assembler generates relocatable object
files for the MPLINK Object Linker, Intel® standard HEX
files, MAP files to detail memory usage and symbol
reference, absolute LST files that contain source lines
and generated machine code and COFF files for
debugging.
• Support for the entire device instruction set
• Support for fixed-point and floating-point data
• Command line interface
• Rich directive set
• Flexible macro language
The MPASM Assembler features include:
• Integration into MPLAB IDE projects
• MPLAB IDE compatibility
• User-defined macros to streamline
assembly code
• Conditional assembly for multi-purpose
source files
• Directives that allow complete control over the
assembly process
DS70292D-page 318
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
29.7 MPLAB SIM Software Simulator
29.9 MPLAB ICD 3 In-Circuit Debugger
System
The MPLAB SIM Software Simulator allows code
development in a PC-hosted environment by simulat-
ing the PIC MCUs and dsPIC® DSCs on an instruction
level. On any given instruction, the data areas can be
examined or modified and stimuli can be applied from
a comprehensive stimulus controller. Registers can be
logged to files for further run-time analysis. The trace
buffer and logic analyzer display extend the power of
the simulator to record and track program execution,
actions on I/O, most peripherals and internal registers.
MPLAB ICD 3 In-Circuit Debugger System is Micro-
chip's most cost effective high-speed hardware
debugger/programmer for Microchip Flash Digital Sig-
nal Controller (DSC) and microcontroller (MCU)
devices. It debugs and programs PIC® Flash microcon-
trollers and dsPIC® DSCs with the powerful, yet easy-
to-use graphical user interface of MPLAB Integrated
Development Environment (IDE).
The MPLAB ICD 3 In-Circuit Debugger probe is con-
nected to the design engineer's PC using a high-speed
USB 2.0 interface and is connected to the target with a
connector compatible with the MPLAB ICD 2 or MPLAB
REAL ICE systems (RJ-11). MPLAB ICD 3 supports all
MPLAB ICD 2 headers.
The MPLAB SIM Software Simulator fully supports
symbolic debugging using the MPLAB C Compilers,
and the MPASM and MPLAB Assemblers. The soft-
ware simulator offers the flexibility to develop and
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software
development tool.
29.10 PICkit 3 In-Circuit Debugger/
Programmer and
29.8 MPLAB REAL ICE In-Circuit
Emulator System
PICkit 3 Debug Express
The MPLAB PICkit 3 allows debugging and program-
ming of PIC® and dsPIC® Flash microcontrollers at a
most affordable price point using the powerful graphical
user interface of the MPLAB Integrated Development
Environment (IDE). The MPLAB PICkit 3 is connected
to the design engineer's PC using a full speed USB
interface and can be connected to the target via an
Microchip debug (RJ-11) connector (compatible with
MPLAB ICD 3 and MPLAB REAL ICE). The connector
uses two device I/O pins and the reset line to imple-
ment in-circuit debugging and In-Circuit Serial Pro-
gramming™.
MPLAB REAL ICE In-Circuit Emulator System is
Microchip’s next generation high-speed emulator for
Microchip Flash DSC and MCU devices. It debugs and
programs PIC® Flash MCUs and dsPIC® Flash DSCs
with the easy-to-use, powerful graphical user interface of
the MPLAB Integrated Development Environment (IDE),
included with each kit.
The emulator is connected to the design engineer’s PC
using a high-speed USB 2.0 interface and is connected
to the target with either a connector compatible with in-
circuit debugger systems (RJ11) or with the new high-
speed, noise tolerant, Low-Voltage Differential Signal
(LVDS) interconnection (CAT5).
The PICkit 3 Debug Express include the PICkit 3, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
The emulator is field upgradable through future firmware
downloads in MPLAB IDE. In upcoming releases of
MPLAB IDE, new devices will be supported, and new
features will be added. MPLAB REAL ICE offers signifi-
cant advantages over competitive emulators including
low-cost, full-speed emulation, run-time variable
watches, trace analysis, complex breakpoints, a rugge-
dized probe interface and long (up to three meters) inter-
connection cables.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 319
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
29.11 PICkit 2 Development
Programmer/Debugger and
PICkit 2 Debug Express
29.13 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
The PICkit™ 2 Development Programmer/Debugger is
a low-cost development tool with an easy to use inter-
face for programming and debugging Microchip’s Flash
families of microcontrollers. The full featured
Windows® programming interface supports baseline
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully func-
tional systems. Most boards include prototyping areas for
adding custom circuitry and provide application firmware
and source code for examination and modification.
(PIC10F,
PIC12F5xx,
PIC16F5xx),
midrange
(PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30,
dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit
microcontrollers, and many Microchip Serial EEPROM
products. With Microchip’s powerful MPLAB Integrated
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
Development Environment (IDE) the PICkit™
2
enables in-circuit debugging on most PIC® microcon-
trollers. In-Circuit-Debugging runs, halts and single
steps the program while the PIC microcontroller is
embedded in the application. When halted at a break-
point, the file registers can be examined and modified.
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™ demon-
stration/development board series of circuits, Microchip
has a line of evaluation kits and demonstration software
The PICkit 2 Debug Express include the PICkit 2, demo
board and microcontroller, hookup cables and CDROM
with user’s guide, lessons, tutorial, compiler and
MPLAB IDE software.
®
for analog filter design, KEELOQ security ICs, CAN,
IrDA®, PowerSmart battery management, SEEVAL®
evaluation system, Sigma-Delta ADC, flow rate
sensing, plus many more.
29.12 MPLAB PM3 Device Programmer
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
The MPLAB PM3 Device Programmer is a universal,
CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
maximum reliability. It features a large LCD display
(128 x 64) for menus and error messages and a modu-
lar, detachable socket assembly to support various
package types. The ICSP™ cable assembly is included
as a standard item. In Stand-Alone mode, the MPLAB
PM3 Device Programmer can read, verify and program
PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices and incorporates an MMC card for file
storage and data applications.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.
DS70292D-page 320
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
30.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 electrical characteristics. Additional information is provided in future revisions of this document as it becomes avail-
able.
Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04
family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability.
Functional operation of the device at these or any other conditions above the parameters indicated in the operation list-
ings of this specification is not implied.
(1)
Absolute Maximum Ratings
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(4) .................................................. -0.3V to +5.6V
Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(4)......................................... -0.3V to (VDD + 0.3V)
Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V
Maximum current out of VSS pin ...........................................................................................................................300 mA
Maximum current into VDD pin(2)...........................................................................................................................250 mA
Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA
Maximum output current sourced by any I/O pin(3)...................................................................................................4 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports(2)...............................................................................................................200 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 30-2).
3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx
and PGEDx pins, which are able to sink/source 12 mA.
4: See the “Pin Diagrams” section for 5V tolerant pins.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 321
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
30.1 DC Characteristics
TABLE 30-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temp Range
(in °C)
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04
Characteristic
3.0-3.6V
3.0-3.6V
-40°C to +85°C
-40°C to +125°C
40
40
TABLE 30-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
Industrial Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
Extended Temperature Devices
TJ
TA
-40
-40
—
—
+125
+85
°C
°C
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+140
+125
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD – IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = ({VDD – VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
TABLE 30-3: THERMAL PACKAGING CHARACTERISTICS
Characteristic
Symbol
Typ
Max
Unit
Notes
Package Thermal Resistance, 44-pin QFN
Package Thermal Resistance, 44-pin TFQP
Package Thermal Resistance, 28-pin SPDIP
Package Thermal Resistance, 28-pin SOIC
Package Thermal Resistance, 28-pin QFN-S
JA
JA
JA
JA
JA
30
40
45
50
30
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
1
1
1
1
1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.
DS70292D-page 322
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max Units
Conditions
Operating Voltage
DC10 Supply Voltage
VDD
—
3.0
1.8
—
—
—
—
3.6
—
V
V
V
Industrial and Extended
DC12
DC16
VDR
RAM Data Retention Voltage(2)
VDD Start Voltage(4)
—
—
VPOR
VSS
to ensure internal
Power-on Reset signal
DC17
DC18
SVDD
VDD Rise Rate
to ensure internal
Power-on Reset signal
VDD Core(3)
0.03
2.25
—
—
—
V/ms 0-3.0V in 0.1s
VCORE
2.75
V
Voltage is dependent on
Internal regulator voltage
load, temperature and
VDD
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: This is the limit to which VDD can be lowered without losing RAM data.
3: These parameters are characterized but not tested in manufacturing.
4: VDD voltage must remain at VSS for a minimum of 200 µs to ensure POR.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 323
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Operating Current (IDD)(2)
DC20d
DC20a
DC20b
DC20c
DC21d
DC21a
DC21b
DC21c
DC22d
DC22a
DC22b
DC22c
DC23d
DC23a
DC23b
DC23c
DC24d
DC24a
DC24b
DC24c
19
19
19
19
29
29
28
28
33
33
33
33
47
48
48
48
60
60
60
60
30
30
30
35
40
40
45
45
50
50
55
55
70
70
70
70
90
90
90
90
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
3.3V
3.3V
3.3V
10 MIPS
16 MIPS
20 MIPS
30 MIPS
40 MIPS
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O
pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have
an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1
driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS.
MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are
operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits
are all zeroed).
DS70292D-page 324
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Idle Current (IIDLE): Core OFF Clock ON Base Current(2)
DC40d
DC40a
DC40b
DC40c
DC41d
DC41a
DC41b
DC41c
DC42d
DC42a
DC42b
DC42c
DC43a
DC43d
DC43b
DC43c
DC44d
DC44a
DC44b
DC44c
4
4
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
+125°C
-40°C
10 MIPS
16 MIPS
20 MIPS
30 MIPS
40 MIPS
3.3V
3.3V
4
4
6
6
+25°C
+85°C
+125°C
-40°C
6
6
9
9
+25°C
+85°C
+125°C
+25°C
-40°C
3.3V
3.3V
3.3V
9
9
16
16
16
16
18
18
19
19
+85°C
+125°C
-40°C
+25°C
+85°C
+125°C
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module
Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 325
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Parameter
Typical(1)
Max
Units
Conditions
No.
Power-Down Current (IPD)(2)
DC60d
DC60a
DC60b
DC60c
DC61d
DC61a
DC61b
DC61c
24
28
124
350
8
500
500
750
1000
13
A
A
A
A
A
A
A
A
-40°C
+25°C
+85°C
+125°C
-40°C
3.3V
3.3V
Base Power-Down Current(3,4)
10
12
13
15
+25°C
+85°C
+125°C
(3)
Watchdog Timer Current: IWDT
20
25
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
2: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off and VREGS (RCON<8>) = 1.
3: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: These currents are measured on the device containing the most memory in this family.
TABLE 30-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Doze
Ratio
Parameter No.
Typical(1)
Max
Units
Conditions
DC73a
DC73f
DC73g
DC70a
DC70f
DC70g
DC71a
DC71f
DC71g
DC72a
DC72f
DC72g
42
23
23
42
26
25
41
25
24
42
26
25
50
30
30
50
30
30
50
30
30
50
30
30
1:2
1:64
1:128
1:2
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
-40°C
+25°C
+85°C
3.3V
3.3V
3.3V
40 MIPS
40 MIPS
40 MIPS
40 MIPS
1:64
1:128
1:2
1:64
1:128
1:2
1:64
1:128
+125°C 3.3V
Note 1: Data in the Typical column is at 3.3V, 25°C unless otherwise stated.
DS70292D-page 326
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ(1)
Max
Units
Conditions
VIL
Input Low Voltage
I/O pins
DI10
DI11
DI15
DI16
DI18
DI19
VSS
VSS
VSS
VSS
VSS
VSS
—
—
—
—
—
—
0.2 VDD
0.15 VDD
0.2 VDD
0.2 VDD
0.3 VDD
0.2 VDD
V
V
V
V
V
V
PMP pins
PMPTTL = 1
MCLR
I/O Pins with OSC1 or SOSCI
I/O Pins with SDAx, SCLx
I/O Pins with SDAx, SCLx
Input High Voltage
SMbus disabled
SMbus enabled
VIH
DI20
DI21
I/O Pins Not 5V Tolerant(4)
0.7 VDD
0.7 VDD
—
—
—
VDD
5.5
VDD
V
V
V
I/O Pins 5V Tolerant(4)
I/O Pins Not 5V Tolerant with 0.24 VDD + 0.8
PMP(4)
I/O Pins 5V Tolerant with
PMP(4)
0.24 VDD + 0.8
50
—
5.5
V
ICNPU
IIL
CNx Pull-up Current
DI30
250
400
A VDD = 3.3V, VPIN = VSS
Input Leakage Current(2)(3)
DI50
DI51
I/O pins 5V Tolerant(4)
—
—
—
—
±2
±1
A VSS VPIN VDD,
Pin at high-impedance
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
I/O Pins Not 5V Tolerant(4)
A VSS VPIN VDD,
Pin at high-impedance,
40°C TA +85°C
DI51a
DI51b
DI51c
—
—
—
—
—
—
±2
±3.5
±8
A Shared with external
reference pins,
40°C TA +85°C
A VSS VPIN VDD, Pin
at high-impedance,
-40°C TA +125°C
A Analog pins shared
with external reference
pins,
-40°C TA +125°C
—
—
DI55
DI56
MCLR
OSC1
—
—
±2
±2
A VSS VPIN VDD
A VSS VPIN VDD,
XT and HS modes
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current can be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: See “Pin Diagrams” for the 5V tolerant I/O pins.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 327
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min
Typ
Max Units
Conditions
VOL
Output Low Voltage
I/O ports
DO10
DO16
—
—
—
—
0.4
0.4
V
V
IOL = 2 mA, VDD = 3.3V
IOL = 2 mA, VDD = 3.3V
OSC2/CLKO
VOH
Output High Voltage
I/O ports
DO20
DO26
2.40
2.41
—
—
—
—
V
V
IOH = -2.3 mA, VDD = 3.3V
IOH = -1.3 mA, VDD = 3.3V
OSC2/CLKO
TABLE 30-11: ELECTRICAL CHARACTERISTICS: BOR
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
DC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min(1) Typ Max(1) Units
2.40 2.55
Conditions
BO10
VBOR
BOR Event on VDD transition
high-to-low
—
V
—
BOR event is tied to VDD core voltage
decrease
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
DS70292D-page 328
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-12: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min Typ(1)
Max
Units
Conditions
Program Flash Memory
Cell Endurance
D130a EP
10,000
VMIN
—
—
—
E/W -40C to +125C
D131
VPR
VDD for Read
3.6
V
VMIN = Minimum operating
voltage
D132B VPEW
VDD for Self-Timed Write
Characteristic Retention
VMIN
20
—
—
10
—
—
—
—
—
—
3.6
—
V
VMIN = Minimum operating
voltage
D134
D135
TRETD
IDDP
Year Provided no other specifications
are violated
Supply Current during
Programming
—
—
mA
D136a TRW
D136b TRW
D137a TPE
D137b TPE
D138a TWW
D138b TWW
Row Write Time
1.32
1.28
20.1
19.5
42.3
41.1
1.74
1.79
26.5
27.3
55.9
57.6
ms TRW = 11064 FRC cycles,
TA = +85°C, See Note 2
Row Write Time
ms TRW = 11064 FRC cycles,
TA = +125°C, See Note 2
Page Erase Time
Page Erase Time
Word Write Cycle Time
Word Write Cycle Time
ms TPE = 168517 FRC cycles,
TA = +85°C, See Note 2
ms TPE = 168517 FRC cycles,
TA = +125°C, See Note 2
µs TWW = 355 FRC cycles,
TA = +85°C, See Note 2
µs TWW = 355 FRC cycles,
TA = +125°C, See Note 2
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Other conditions: FRC = 7.37 MHz, TUN<5:0> = b'011111(for Min), TUN<5:0> = b'100000(for Max).
This parameter depends on the FRC accuracy (see Table 30-19) and the value of the FRC Oscillator Tun-
ing register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see
Section 5.3 “Programming Operations”.
TABLE 30-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Standard Operating Conditions (unless otherwise stated):
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristics
Min
Typ
Max
Units
Comments
CEFC
External Filter Capacitor
Value
4.7
10
—
F
Capacitor must be low
series resistance
(< 5 Ohms)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 329
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
30.2 AC Characteristics and Timing
Parameters
This section defines dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 AC characteristics and timing parameters.
TABLE 30-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Operating voltage VDD range as described in Section 30.0 “Electrical
Characteristics”.
FIGURE 30-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 30-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param
Symbol
Characteristic
Min
Typ
Max Units
Conditions
No.
DO50 COSCO
OSC2/SOSCO pin
—
—
15
pF In XT and HS modes when
external clock is used to drive
OSC1
DO56 CIO
DO58 CB
All I/O pins and OSC2
SCLx, SDAx
—
—
—
—
50
pF EC mode
pF In I2C™ mode
400
DS70292D-page 330
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-2:
EXTERNAL CLOCK TIMING
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
OSC1
CLKO
OS20
OS30 OS30
OS25
OS31 OS31
OS41
OS40
TABLE 30-16: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS10
FIN
External CLKI Frequency
(External clocks allowed only
in EC and ECPLL modes)
DC
—
40
MHz EC
Oscillator Crystal Frequency
3.5
10
—
—
—
10
40
33
MHz XT
MHz HS
kHz SOSC
OS20
OS25
OS30
TOSC
TCY
TOSC = 1/FOSC
Instruction Cycle Time(2)
12.5
25
—
—
—
DC
DC
ns
ns
TosL,
TosH
External Clock in (OSC1)
High or Low Time
0.375 x TOSC
0.625 x TOSC
ns
EC
EC
OS31
TosR,
TosF
External Clock in (OSC1)
Rise or Fall Time
—
—
20
ns
OS40
OS41
OS42
TckR
TckF
GM
CLKO Rise Time(3)
CLKO Fall Time(3)
—
—
14
5.2
5.2
16
—
—
18
ns
ns
—
—
External Oscillator
mA/V VDD = 3.3V
TA = +25ºC
Transconductance(4)
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2: Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values
are based on characterization data for that particular oscillator type under standard operating conditions
with the device executing code. Exceeding these specified limits may result in an unstable oscillator
operation and/or higher than expected current consumption. All devices are tested to operate at “min.”
values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the
“max.” cycle time limit is “DC” (no clock) for all devices.
3: Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin.
4: Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 331
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
OS50
FPLLI
PLL Voltage Controlled
Oscillator (VCO) Input
Frequency Range
0.8
—
8
MHz ECPLL, HSPLL, XTPLL
modes
OS51
FSYS
On-Chip VCO System
Frequency
100
—
200
MHz
—
—
OS52
OS53
TLOCK
DCLK
PLL Start-up Time (Lock Time)
CLKO Stability (Jitter)
0.9
-3
1.5
0.5
3.1
3
mS
%
Measured over 100 ms
period
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
TABLE 30-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature
-40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
Internal FRC Accuracy @ 7.3728 MHz(1,2)
F20a
F20b
FRC
FRC
-2
-5
—
—
+2
+5
%
%
-40°C TA +85°C VDD = 3.0-3.6V
-40°C TA +125°C VDD = 3.0-3.6V
Note 1: Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift.
2: FRC is set to initial frequency of 7.37 MHz (±2%) at 25°C.
TABLE 30-19: INTERNAL RC ACCURACY
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
No.
Characteristic
Min
Typ
Max
Units
Conditions
LPRC @ 32.768 kHz(1)
F21a LPRC
F21b LPRC
-20
-70
±6
—
+20
+70
%
%
-40°C TA +85°C VDD = 3.0-3.6V
-40°C TA +125°C VDD = 3.0-3.6V
Note 1: Change of LPRC frequency as VDD changes.
DS70292D-page 332
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-3:
CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin
(Input)
DI35
DI40
I/O Pin
(Output)
New Value
Old Value
DO31
DO32
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-20: I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ(1)
Max
Units
Conditions
DO31
DO32
DI35
TIOR
TIOF
TINP
TRBP
Port Output Rise Time
—
—
20
2
10
10
—
—
25
25
—
—
ns
ns
—
—
—
—
Port Output Fall Time
INTx Pin High or Low Time (output)
CNx High or Low Time (input)
ns
DI40
TCY
Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 333
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-4:
RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP
TIMER TIMING CHARACTERISTICS
VDD
SY12
MCLR
SY10
Internal
POR
SY11
PWRT
Time-out
SY30
OSC
Time-out
Internal
Reset
Watchdog
Timer
Reset
SY20
SY13
SY13
I/O Pins
SY35
FSCM
Delay
Note: Refer to Figure 30-1 for load conditions.
DS70292D-page 334
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max Units
Conditions
SY10
SY11
TMCL
MCLR Pulse-Width (low)
2
—
—
—
s -40°C to +85°C
ms -40°C to +85°C
TPWRT Power-up Timer Period
—
2
4
User programmable
8
16
32
64
128
SY12
SY13
TPOR
TIOZ
Power-on Reset Delay
3
10
30
s -40°C to +85°C
s
I/O High-Impedance
from MCLR Low or
Watchdog Timer Reset
0.68
0.72
1.2
SY20
TWDT1
Watchdog Timer
Time-out Period
—
—
—
—
—
See Section 27.4 “Watchdog
Timer (WDT)” and LPRC
specification F21 (Table 30-19)
SY30
SY35
TOST
Oscillator Start-up
Timer Period
—
—
1024 TOSC
500
—
TOSC = OSC1 period
TFSCM
Fail-Safe Clock
Monitor Delay
900
s -40°C to +85°C
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 335
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-5:
TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS
TxCK
Tx11
Tx10
Tx15
Tx20
OS60
TMRx
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
TA10
TA11
TA15
TTXH
TTXL
TTXP
TxCK High Time
TxCK Low Time
Synchronous,
no prescaler
0.5 TCY + 20
—
—
—
ns
ns
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
Asynchronous
10
—
—
—
—
ns
ns
Synchronous,
no prescaler
0.5 TCY + 20
Must also meet
parameter TA15
Synchronous,
with prescaler
10
—
—
ns
Asynchronous
10
—
—
—
—
ns
ns
TxCK Input Period Synchronous,
no prescaler
TCY + 40
—
Synchronous,
with prescaler
Greater of:
20 ns or
—
—
—
N = prescale
value
(TCY + 40)/N
(1, 8, 64, 256)
Asynchronous
20
—
—
—
ns
—
—
OS60
TA20
Ft1
SOSCI/T1CK Oscillator Input
DC
50
kHz
frequency Range (oscillator enabled
by setting bit TCS (T1CON<1>))
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
—
Note 1: Timer1 is a Type A.
DS70292D-page 336
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-23: TIMER2 AND TIMER4 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TtxH
Characteristic
Min
Typ
Max
Units
Conditions
TB10
TxCK High Time Synchronous, 0.5 TCY + 20
no prescaler
—
—
ns
Must also meet
parameter TB15
Synchronous,
with prescaler
10
—
—
—
—
—
—
—
—
ns
ns
ns
ns
TB11
TB15
TtxL
TtxP
TxCK Low Time
Synchronous, 0.5 TCY + 20
no prescaler
Must also meet
parameter TB15
Synchronous,
with prescaler
10
TxCK Input
Period
Synchronous,
no prescaler
TCY + 40
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TB20
TCKEXT-
MRL
Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5 TCY
—
—
TABLE 30-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Symbol
TtxH
Characteristic
Min
Typ
Max Units
Conditions
TC10
TC11
TC15
TxCK High Time
TxCK Low Time
Synchronous
Synchronous
0.5 TCY + 20
—
—
—
—
ns
ns
ns
Must also meet
parameter TC15
TtxL
TtxP
0.5 TCY + 20
TCY + 40
—
—
Must also meet
parameter TC15
TxCK Input Period Synchronous,
no prescaler
N = prescale
value
(1, 8, 64, 256)
Synchronous,
with prescaler
Greater of:
20 ns or
(TCY + 40)/N
TC20
TCKEXTMRL Delay from External TxCK Clock
Edge to Timer Increment
0.5 TCY
—
1.5
TCY
—
—
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 337
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-6:
INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx
IC10
IC11
IC15
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-25: INPUT CAPTURE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Max
Units
Conditions
IC10
IC11
IC15
TccL
TccH
TccP
ICx Input Low Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
—
—
—
—
ns
ns
ns
ns
ns
—
ICx Input High Time No Prescaler
With Prescaler
0.5 TCY + 20
10
—
ICx Input Period
(TCY + 40)/N
N = prescale
value (1, 4, 16)
Note 1: These parameters are characterized but not tested in manufacturing.
FIGURE 30-7:
OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS
OCx
(Output Compare
or PWM Mode)
OC10
OC11
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC10 TccF
OC11 TccR
OCx Output Fall Time
OCx Output Rise Time
—
—
—
—
—
—
ns
ns
See parameter D032
See parameter D031
Note 1: These parameters are characterized but not tested in manufacturing.
DS70292D-page 338
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-8:
OC/PWM MODULE TIMING CHARACTERISTICS
OC20
OCFA
OC15
OCx
TABLE 30-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
OC15
TFD
Fault Input to PWM I/O
Change
—
—
50
ns
—
OC20
TFLT
Fault Input Pulse-Width
50
—
—
ns
—
Note 1: These parameters are characterized but not tested in manufacturing.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 339
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-9:
SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SCKx
(CKP = 1)
SP35
SP31
SP21
LSb
Bit 14 - - - - - -1
MSb
SDOx
SDIx
SP30
MSb In
SP40
LSb In
Bit 14 - - - -1
SP41
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
See Note 3
SP10
SP11
SP20
TscL
TscH
TscF
SCKx Output Low Time
SCKx Output High Time
SCKx Output Fall Time
TCY/2
TCY/2
—
—
—
—
—
—
—
ns
ns
ns
See Note 3
See parameter D032
and Note 4
SP21
SP30
SP31
SP35
SP40
SP41
TscR
TdoF
TdoR
SCKx Output Rise Time
—
—
—
—
23
30
—
—
—
6
—
—
—
20
—
—
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 4
SDOx Data Output Fall Time
SDOx Data Output Rise Time
See parameter D032
and Note 4
See parameter D031
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data Input
—
—
TdiV2scL
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.
DS70292D-page 340
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-10:
SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)
SP11
SP10
SP21
SP20
SP20
SP21
SCKX
(CKP = 1)
SP35
LSb
MSb
SP40
Bit 14 - - - - - -1
SDOX
SDIX
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SCKx Output Low Time(3)
SCKx Output High Time(3)
SCKx Output Fall Time(4)
TCY/2
TCY/2
—
—
—
—
—
—
—
ns
ns
ns
See Note 3
SP10
SP11
SP20
TscH
TscF
See Note 3
See parameter D032
and Note 4
SP21
SP30
SP31
SP35
SP36
SP40
SP41
TscR
TdoF
TdoR
SCKx Output Rise Time(4)
—
—
—
—
30
23
30
—
—
—
6
—
—
—
20
—
—
—
ns
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 4
SDOx Data Output Fall
Time(4)
See parameter D032
and Note 4
SDOx Data Output Rise
Time(4)
See parameter D031
and Note 4
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
—
—
TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
—
—
—
TdiV2scH, Setup Time of SDIx Data
TdiV2scL Input to SCKx Edge
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 341
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-11:
SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS
SSX
SP52
SP50
SCKX
(CKP = 0)
SP71
SP70
SP72
SP73
SP72
SCKX
(CKP = 1)
SP73
LSb
SP35
MSb
SDOX
SDIX
Bit 14 - - - - - -1
SP51
SP30,SP31
Bit 14 - - - -1
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 30-1 for load conditions.
TABLE 30-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2) Max Units
Conditions
SP70
SP71
SP72
SP73
SP30
SCKx Input Low Time
30
30
—
—
—
—
—
10
10
—
—
—
25
25
—
ns
ns
ns
ns
ns
—
—
TscH
TscF
TscR
TdoF
SCKx Input High Time
SCKx Input Fall Time(3)
SCKx Input Rise Time(3)
SDOx Data Output Fall Time(3)
See Note 3
See Note 3
See parameter D032
and Note 3
SP31
SP35
SP40
SP41
SP50
SP51
SP52
TdoR
SDOx Data Output Rise Time(3)
—
—
—
—
—
—
—
—
—
30
—
—
—
50
—
ns
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 3
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
20
120
—
—
to SCKx Edge
TssL2scH, SSx to SCKx or SCKx Input
TssL2scL
See Note 3
TssH2doZ SSx to SDOx Output
10
High-Impedance(3)
TscH2ssH SSx after SCKx Edge
TscL2ssH
1.5 TCY + 40
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: Assumes 50 pF load on all SPIx pins.
DS70292D-page 342
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-12:
SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx
SP52
SP50
SCKx
(CKP = 0)
SP71
SP70
SP72
SP73
SP73
SCKx
(CKP = 1)
SP35
SP72
LSb
MSb
Bit 14 - - - - - -1
SDOx
SDIx
SP30,SP31
Bit 14 - - - -1
SP51
MSb In
SP41
LSb In
SP40
Note: Refer to Figure 30-1 for load conditions.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 343
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
TscL
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
SP70
SP71
SP72
SP73
SP30
SCKx Input Low Time
30
30
—
—
—
—
—
10
10
—
—
—
25
25
—
ns
ns
ns
ns
ns
—
—
TscH
TscF
TscR
TdoF
SCKx Input High Time
SCKx Input Fall Time(3)
SCKx Input Rise Time(3)
SDOx Data Output Fall Time(3)
See Note 3
See Note 3
See parameter D032
and Note 3
SP31
SP35
SP40
SP41
SP50
SP51
SP52
SP60
TdoR
SDOx Data Output Rise Time(3)
—
—
—
—
—
—
—
—
—
—
30
—
—
—
50
—
50
ns
ns
ns
ns
ns
ns
ns
ns
See parameter D031
and Note 3
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
20
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL to SCKx Edge
20
—
TssL2scH, SSx to SCKx or SCKx
TssL2scL Input
120
—
TssH2doZ SSx to SDOX Output
10
1.5 TCY + 40
—
—
See Note 4
—
High-Impedance(4)
TscH2ssH SSx after SCKx Edge
TscL2ssH
TssL2doV SDOx Data Output Valid after
SSx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
3: The minimum clock period for SCKx is 100 ns. The clock generated in Master mode must not violate this
specification.
4: Assumes 50 pF load on all SPIx pins.
DS70292D-page 344
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-13:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)
SCLx
IM31
IM34
IM30
IM33
SDAx
Stop
Condition
Start
Condition
Note: Refer to Figure 30-1 for load conditions.
FIGURE 30-14:
I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)
IM20
IM21
IM11
IM10
SCLx
IM11
IM26
IM10
IM33
IM25
SDAx
In
IM45
IM40
IM40
SDAx
Out
Note: Refer to Figure 30-1 for load conditions.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 345
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min(1)
Max
Units
Conditions
IM10
TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
—
—
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
s
s
s
pF
—
—
—
—
—
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
IM11
IM20
IM21
IM25
IM26
IM30
IM31
IM33
IM34
IM40
IM45
THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1)
—
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
TF:SCL
TR:SCL
SDAx and SCLx 100 kHz mode
—
300
300
100
1000
300
300
—
CB is specified to be
from 10 to 400 pF
Fall Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
SDAx and SCLx 100 kHz mode
—
CB is specified to be
from 10 to 400 pF
Rise Time
400 kHz mode
20 + 0.1 CB
1 MHz mode(2)
—
250
100
40
0
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(2)
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
—
0.2
TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
Only relevant for
Repeated Start
condition
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1)
—
After this period the
first clock pulse is
generated
Hold Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1)
—
—
Setup Time
400 kHz mode TCY/2 (BRG + 1)
—
1 MHz mode(2) TCY/2 (BRG + 1)
—
THD:STO Stop Condition
Hold Time
100 kHz mode TCY/2 (BRG + 1)
400 kHz mode TCY/2 (BRG + 1)
1 MHz mode(2) TCY/2 (BRG + 1)
—
—
—
—
TAA:SCL Output Valid
From Clock
100 kHz mode
400 kHz mode
1 MHz mode(2)
—
—
3500
1000
400
—
—
—
—
—
TBF:SDA Bus Free Time 100 kHz mode
4.7
1.3
0.5
—
Time the bus must be
free before a new
transmission can start
400 kHz mode
1 MHz mode(2)
—
—
IM50
IM51
CB
Bus Capacitive Loading
400
—
TPGD
Pulse Gobbler Delay
65
390
ns
See Note 3
Note 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit™
(I2C™)” (DS70195) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web-
site (www.microchip.com) for the latest dsPIC33F Family Reference Manual chapters.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
3: Typical value for this parameter is 130 ns.
DS70292D-page 346
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-15:
I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)
SCLx
IS34
IS31
IS30
IS33
SDAx
Stop
Condition
Start
Condition
FIGURE 30-16:
I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)
IS20
IS21
IS11
IS10
SCLx
IS30
IS26
IS31
IS33
IS25
SDAx
In
IS45
IS40
IS40
SDAx
Out
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 347
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for
Extended
Param. Symbol
Characteristic
Min
Max
Units
Conditions
IS10
IS11
TLO:SCL Clock Low Time 100 kHz mode
4.7
—
s
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
1.3
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
4.0
—
—
s
s
—
THI:SCL Clock High Time 100 kHz mode
Device must operate at a
minimum of 1.5 MHz
400 kHz mode
0.6
—
s
Device must operate at a
minimum of 10 MHz
1 MHz mode(1)
0.5
—
300
300
100
1000
300
300
—
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
s
s
s
s
s
s
s
s
s
s
s
ns
ns
ns
ns
ns
ns
s
s
s
pF
—
IS20
IS21
IS25
IS26
IS30
IS31
IS33
IS34
IS40
IS45
IS50
TF:SCL SDAx and SCLx 100 kHz mode
—
CB is specified to be from
10 to 400 pF
Fall Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
—
TR:SCL SDAx and SCLx 100 kHz mode
CB is specified to be from
10 to 400 pF
Rise Time
400 kHz mode
1 MHz mode(1)
20 + 0.1 CB
—
TSU:DAT Data Input
Setup Time
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
100 kHz mode
400 kHz mode
1 MHz mode(1)
250
100
100
0
—
—
—
—
THD:DAT Data Input
Hold Time
—
0
0.9
0.3
—
0
TSU:STA Start Condition
Setup Time
4.7
0.6
0.25
4.0
0.6
0.25
4.7
0.6
0.6
4000
600
250
0
Only relevant for Repeated
Start condition
—
—
THD:STA Start Condition
Hold Time
—
After this period, the first
clock pulse is generated
—
—
TSU:STO Stop Condition
Setup Time
—
—
—
—
—
—
THD:ST Stop Condition
—
O
Hold Time
—
TAA:SCL Output Valid
From Clock
3500
1000
350
—
0
0
TBF:SDA Bus Free Time
4.7
1.3
0.5
—
Time the bus must be free
before a new transmission
can start
—
—
CB
Bus Capacitive Loading
400
—
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only).
DS70292D-page 348
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-17:
DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING CHARACTERISTICS
CSCK
(SCKE =
0
)
)
CS11
CS10
CS21
CS20
CS20
CS21
CSCK
(SCKE =
1
COFS
CS55 CS56
CS35
70
CS51
High-Z
CS50
LSb
High-Z
MSb
CSDO
CSDI
CS30
CS31
LSb In
MSb In
CS40 CS41
Note: Refer to Figure 30-1 for load conditions.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 349
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-34: DCI MODULE (MULTI-CHANNEL, I2S MODES) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CS10
TCSCKL
CSCK Input Low Time
(CSCK pin is an input)
TCY/2 + 20
—
—
ns
—
CSCK Output Low Time(3)
(CSCK pin is an output)
30
—
—
—
10
10
—
—
—
25
25
ns
ns
ns
ns
ns
—
—
—
—
—
CS11
TCSCKH
CSCK Input High Time
(CSCK pin is an input)
CSCK Output High Time(3)
(CSCK pin is an output)
CSCK Output Fall Time(4)
(CSCK pin is an output)
TCY/2 + 20
30
—
—
CS20
CS21
TCSCKF
TCSCKR
CSCK Output Rise Time(4)
(CSCK pin is an output)
CS30
CS31
CS35
CS36
CS40
TCSDOF
TCSDOR
TDV
CSDO Data Output Fall Time(4)
CSDO Data Output Rise Time(4)
Clock Edge to CSDO Data Valid
Clock Edge to CSDO Tri-Stated
—
—
—
10
20
10
10
—
—
—
25
25
10
20
—
ns
ns
ns
ns
ns
—
—
—
—
—
TDIV
TCSDI
Setup Time of CSDI Data Input to
CSCK Edge (CSCK pin is input
or output)
CS41
THCSDI
Hold Time of CSDI Data Input to
CSCK Edge (CSCK pin is input
or output)
20
—
—
ns
—
CS50
CS51
CS55
TCOFSF
TCOFSR
TSCOFS
COFS Fall Time
(COFS pin is output)
—
—
20
10
10
—
25
25
—
ns
ns
ns
Note 1
Note 1
—
COFS Rise Time
(COFS pin is output)
Setup Time of COFS Data Input
to CSCK Edge (COFS pin is
input)
CS56
THCOFS
Hold Time of COFS Data Input to
CSCK Edge (COFS pin is input)
20
—
—
ns
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for CSCK is 100 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all DCI pins.
DS70292D-page 350
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-18:
DCI MODULE (AC-LINK MODE) TIMING CHARACTERISTICS
BIT_CLK
(CSCK)
CS62
CS71
CS61
CS60
CS21
CS20
CS70
CS72
SYNC
(COFS)
CS76
CS75
CS80
MSb
LSb
LSb
SDOx
(CSDO)
CS76
CS75
MSb In
SDIx
(CSDI)
CS65 CS66
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 351
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-35: DCI MODULE (AC-LINK MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic(1,2)
BIT_CLK Low Time
Min
Typ(3)
Max
Units
Conditions
CS60
CS61
CS62
CS65
TBCLKL
TBCLKH
TBCLK
TSACL
36
36
—
—
40.7
40.7
81.4
—
45
45
—
10
ns
ns
ns
ns
—
BIT_CLK High Time
BIT_CLK Period
—
Bit clock is input
—
Input Setup Time to
Falling Edge of BIT_CLK
CS66
THACL
Input Hold Time from
—
—
10
ns
—
Falling Edge of BIT_CLK
CS70
CS71
CS72
CS75
CS76
CS80
TSYNCLO SYNC Data Output Low Time
—
—
—
—
—
—
19.5
1.3
20.8
—
—
—
—
30
30
15
s
s
s
ns
ns
ns
Note 1
TSYNCHI
TSYNC
TRACL
TFACL
SYNC Data Output High Time
SYNC Data Output Period
Note 1
Note 1
Rise Time, SYNC, SDATA_OUT
Fall Time, SYNC, SDATA_OUT
CLOAD = 50 pF, VDD = 3V
CLOAD = 50 pF, VDD = 3V
—
—
TOVDACL Output Valid Delay from Rising
Edge of BIT_CLK
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: These values assume BIT_CLK frequency is 12.288 MHz.
3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
DS70292D-page 352
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-19:
ECAN™ MODULE I/O TIMING CHARACTERISTICS
CiTx Pin
(output)
New Value
Old Value
CA10 CA11
CiRx Pin
(input)
CA20
TABLE 30-36: ECAN™ MODULE I/O TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ(2)
Max
Units
Conditions
CA10
CA11
CA20
TioF
TioR
Tcwf
Port Output Fall Time
Port Output Rise Time
—
—
—
—
—
—
ns
ns
ns
See parameter D032
See parameter D031
—
Pulse-Width to Trigger
CAN Wake-up Filter
120
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 353
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-37: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
Device Supply
AD01
AVDD
Module VDD Supply
Greater of
VDD – 0.3
or 3.0
—
—
Lesser of
VDD + 0.3
or 3.6
V
V
—
—
AD02
AVSS
Module VSS Supply
VSS – 0.3
VSS + 0.3
Reference Inputs
AD05
VREFH
Reference Voltage High
AVSS + 2.7
—
—
AVDD
3.6
V
V
See Note 1
AD05a
3.0
VREFH = AVDD
VREFL = AVSS = 0
AD06
VREFL
VREF
Reference Voltage Low
AVSS
0
—
—
AVDD – 2.7
0
V
V
See Note 1
AD06a
VREFH = AVDD
VREFL = AVSS = 0
AD07
Absolute Reference
Voltage
2.7
—
3.6
V
VREF = VREFH - VREFL
AD08
AD09
IREF
IAD
Current Drain
—
—
—
10
A ADC off
Operating Current
7.0
9.0
mA ADC operating in 10-bit
mode, see Note 1
—
2.7
3.2
mA ADC operating in 12-bit
mode, see Note 1
Analog Input
AD12
AD13
AD17
VINH
VINL
RIN
Input Voltage Range VINH
Input Voltage Range VINL
VINL
—
VREFH
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), positive
input
VREFL
—
AVSS + 1V
V
This voltage reflects Sample
and Hold Channels 0, 1, 2,
and 3 (CH0-CH3), negative
input
Recommended Imped-
ance of Analog Voltage
Source
—
—
—
—
200
200
10-bit ADC
12-bit ADC
Note 1: These parameters are not characterized or tested in manufacturing.
DS70292D-page 354
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-38: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREF-
AD20a Nr
AD21a INL
Resolution
12 data bits
—
bits
Integral Nonlinearity
-2
>-1
1.25
-0.2
—
+2
<1
10
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22a DNL
Differential Nonlinearity
Gain Error
—
3.4
0.9
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
Guaranteed
ADC Accuracy (12-bit Mode) – Measurements with internal VREF+/VREF-
AD20a Nr
AD21a INL
AD22a DNL
Resolution
12 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
>-1
2
—
—
+2
<1
20
10
—
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23a
AD24a
AD25a
GERR
EOFF
—
10.5
3.8
—
Offset Error
2
Monotonicity
—
—
Guaranteed
Dynamic Performance (12-bit Mode)
AD30a THD
Total Harmonic Distortion
—
—
-75
—
dB
dB
—
—
AD31a SINAD
Signal to Noise and
Distortion
68.5
69.5
AD32a SFDR
Spurious Free Dynamic
Range
80
—
—
dB
—
AD33a
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
250
—
kHz
bits
—
—
AD34a ENOB
11.09
11.3
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 355
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-39: ADC MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max. Units
Conditions
ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREF-
AD20b Nr
AD21b INL
Resolution
10 data bits
—
bits
Integral Nonlinearity
-1.5
>-1
0.4
0.2
—
+1.5
<1
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD22b DNL
Differential Nonlinearity
Gain Error
—
3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
2
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Monotonicity
—
—
—
Guaranteed
ADC Accuracy (10-bit Mode) – Measurements with internal VREF+/VREF-
AD20b Nr
AD21b INL
AD22b DNL
Resolution
10 data bits
bits
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-1
>-1
3
—
—
7
+1
<1
15
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
AD23b
AD24b
AD25b
GERR
EOFF
—
Offset Error
1.5
—
3
Monotonicity
—
—
—
Guaranteed
Dynamic Performance (10-bit Mode)
AD30b THD
Total Harmonic Distortion
—
—
-64
—
dB
dB
—
—
AD31b SINAD
Signal to Noise and
Distortion
57
58.5
AD32b SFDR
Spurious Free Dynamic
Range
72
—
—
dB
—
AD33b
FNYQ
Input Signal Bandwidth
Effective Number of Bits
—
—
550
—
kHz
bits
—
—
AD34b ENOB
9.16
9.4
DS70292D-page 356
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-20:
ADC CONVERSION (12-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 0, SSRC<2:0> = 000)
AD50
ADCLK
Instruction
Execution
Set SAMP
AD61
Clear SAMP
SAMP
AD60
TSAMP
AD55
DONE
AD1IF
1
2
3
4
5
6
7
8
9
– Software sets AD1CON. SAMP to start sampling.
– Sampling ends, conversion sequence starts.
1
2
4
– Sampling starts after discharge period. TSAMP is described in
Section 28. “Analog-to-Digital Converter (ADC) without DMA”
(DS70210) in the “dsPIC33F/PIC24H Family Reference Manual”.
Please see the Microchip web site (www.microchip.com)
for the latest dsPIC33F Family Reference Manual sections.
– Convert bit 11.
5
6
7
8
9
– Convert bit 10.
– Convert bit 1.
– Convert bit 0.
– Software clears AD1CON. SAMP to start conversion.
3
– One TAD for end of conversion.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 357
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-40: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ(2) Max.
Units
Conditions
Clock Parameters(1)
AD50
AD51
TAD
ADC Clock Period
117.6
—
—
—
—
ns
ns
—
—
tRC
ADC Internal RC Oscillator
Period
250
Conversion Rate
AD55
AD56
AD57
tCONV
FCNV
Conversion Time
Throughput Rate
Sample Time
—
—
14 TAD
ns
ksps
—
—
—
—
—
—
500
—
TSAMP
3 TAD
Timing Parameters
AD60
tPCS
2 TAD
—
3 TAD
—
Auto convert trigger not
selected
Conversion Start from Sample
Trigger(2)
AD61
AD62
AD63
tPSS
tCSS
tDPU
Sample Start from Setting
Sample (SAMP) bit(2)
2 TAD
—
—
0.5 TAD
—
3 TAD
—
—
—
s
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2,3)
—
20
Note 1: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
2: These parameters are characterized but not tested in manufacturing.
3: The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is
turned on (AD1CON1<ADON>=’1’). During this time, the ADC result is indeterminate.
DS70292D-page 358
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-21:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(CHPS<1:0> = 01, SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)
AD50
Set SAMP
AD61
ADCLK
Instruction
Execution
Clear SAMP
AD60
SAMP
TSAMP
AD55
AD55
DONE
AD1IF
1
2
3
4
5
6
7
8
5
6
7
8
– Software sets AD1CON. SAMP to start sampling.
1
2
– Sampling starts after discharge period. TSAMP is described in Section 28. “Analog-to-Digital Converter (ADC)
without DMA” (DS70210) in the “dsPIC33F/PIC24H Family Reference Manual”.
– Software clears AD1CON. SAMP to start conversion.
– Sampling ends, conversion sequence starts.
– Convert bit 9.
3
4
5
6
7
8
– Convert bit 8.
– Convert bit 0.
– One TAD for end of conversion.
FIGURE 30-22:
ADC CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)
AD50
ADCLK
Instruction
Set ADON
Execution
SAMP
AD1IF
TSAMP
TSAMP
AD55
AD55
AD55
DONE
1
2
3
4
5
6
7
3
4
5
6
8
– Convert bit 8.
– Convert bit 0.
4
– Software sets AD1CON. ADON to start AD operation.
1
2
5
6
7
8
– Sampling starts after discharge period. TSAMP is described in
Section 28. “Analog-to-Digital Converter (ADC) without DMA”
(DS70210) in the “dsPIC33F/PIC24H Family Reference Manual'.
– One TAD for end of conversion.
– Begin conversion of next channel.
– Convert bit 9.
3
– Sample for time specified by SAMC<4:0>.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 359
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-41: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ(2)
Max.
Units
Conditions
Clock Parameters(1)
AD50 TAD
AD51 tRC
ADC Clock Period
ADC Internal RC Oscillator Period
76
—
—
—
—
ns
ns
—
—
250
Conversion Rate
AD55 tCONV
AD56 FCNV
Conversion Time
Throughput Rate
—
—
12 TAD
—
1.1
—
—
Msps
—
—
—
—
—
—
AD57 TSAMP Sample Time
2 TAD
Timing Parameters
AD60 tPCS
AD61 tPSS
AD62 tCSS
AD63 tDPU
Conversion Start from Sample
2 TAD
2 TAD
—
—
3 TAD
3 TAD
—
—
—
—
s
Auto-Convert Trigger
not selected
Trigger(2)
Sample Start from Setting
Sample (SAMP) bit(2)
—
0.5 TAD
—
—
—
—
Conversion Completion to
Sample Start (ASAM = 1)(2)
Time to Stabilize Analog Stage
from ADC Off to ADC On(2,3)
—
20
Note 1: Because the sample caps eventually loses charge, clock rates below 10 kHz may affect linearity
performance, especially at elevated temperatures.
2: These parameters are characterized but not tested in manufacturing.
3: The tDPU is the time required for the ADC module to stabilize at the appropriate level when the module is
turned on (AD1CON1<ADON>=’1’). During this time, the ADC result is indeterminate.
TABLE 30-42: AUDIO DAC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC/DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ Max. Units
Conditions
Clock Parameters
DA01
DA02
VOD+
VOD-
Positive Output Differential
Voltage
1
1.15
2
V
V
VOD+ = VDACH – VDACL
See Note 1, 2
Negative Output Differential
Voltage
-2
-1.15
-1
VOD- = VDACL – VDACH
See Note 1, 2
DA03
DA04
DA08
DA09
DA10
DA11
VRES
GERR
FDAC
FSAMP
FINPUT
TINIT
Resolution
—
—
16
3.1
—
—
—
bits
%
—
—
—
—
Gain Error
Clock frequency
Sample Rate
—
25.6 MHz
0
—
100
45
kHz
Input data frequency
Initialization period
Signal-to-Noise Ratio
0
—
kHz Sampling frequency = 100 kHz
Clks Time before first sample
1024
—
—
—
DA12 SNR
61
dB Sampling frequency = 96 kHz
Note 1: Measured VDACH and VDACL output with respect to VSS, with no load and FORM bit (DACXCON<8>) = 0.
2: This parameter is tested at -40°C TA 85°C only.
DS70292D-page 360
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-43: COMPARATOR TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
Symbol
Characteristic
Min.
Typ
Max. Units
Conditions
No.
300
301
TRESP
Response Time(1,2)
—
—
150
—
400
10
ns
—
—
TMC2OV
Comparator Mode Change
to Output Valid(1)
s
Note 1: Parameters are characterized but not tested.
2: Response time measured with one comparator input at (VDD - 1.5)/2, while the other input transitions from
VSS to VDD.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 361
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 30-44: COMPARATOR MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Min.
Typ
Max.
Units
Conditions
D300
D301
VIOFF
VICM
Input Offset Voltage(1)
Input Common Mode Voltage(1)
—
0
±10
—
—
mV
V
—
—
AVDD-1.5V
D302
CMRR
Common Mode Rejection Ratio (1)
-54
—
—
dB
—
Note 1: Parameters are characterized but not tested.
TABLE 30-45: COMPARATOR REFERENCE VOLTAGE SETTLING TIME SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
AC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Settling Time(1)
Min.
Typ
Max.
Units
Conditions
VR310
TSET
—
—
10
s
—
Note 1: Settling time measured while CVRR = 1and CVR3:CVR0 bits transition from ‘0000’ to ‘1111’.
TABLE 30-46: COMPARATOR REFERENCE VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
DC CHARACTERISTICS
-40°C TA +125°C for Extended
Param
No.
Symbol
Characteristic
Resolution
Min.
Typ
Max.
Units
Conditions
VRD310 CVRES
VRD311 CVRAA
VRD312 CVRUR
CVRSRC/24
—
—
2k
CVRSRC/32 LSb
—
—
—
Absolute Accuracy
—
—
0.5
—
LSb
Unit Resistor Value (R)
DS70292D-page 362
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-23:
PARALLEL SLAVE PORT TIMING DIAGRAM
CS
RD
WR
PS4
PMD<7:0>
PS1
PS3
PS2
TABLE 30-47: PARALLEL SLAVE PORT TIME SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
PS1
PS2
PS3
PS4
TdtV2wrH Data in Valid before WR or CS
Inactive (setup time)
20
—
—
ns
—
TwrH2dtI
WR or CS Inactive to Data-In
Invalid (hold time)
20
—
10
—
—
—
—
80
30
ns
ns
ns
—
—
—
TrdL2dtV RD and CS to Active Data-Out
Valid
TrdH2dtI
RD Active or CS Inactive to
Data-Out Invalid
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 363
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-24:
PARALLEL MASTER PORT READ TIMING DIAGRAM
P2
P2
P1
P3
P3
P4
P1
P4
P2
P1
System
Clock
PMA<13:8>
PMD<7:0>
Address
Data
PM7
Address <7:0>
PM2
PM6
PM3
PMRD
PMWR
PM5
PMALL/PMALH
PMCS1
PM1
TABLE 30-48: PARALLEL MASTER PORT READ TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for
Extended
Param
Characteristic
Min.
Typ
Max.
Units
Conditions
No.
PM1
PMALL/PMALH Pulse-Width
—
—
0.5 TCY
—
—
ns
ns
—
—
PM2
Address Out Valid to PMALL/PMALH Invalid
(address setup time)
0.75 TCY
PM3
PMALL/PMALH Invalid to Address Out Invalid
(address hold time)
—
0.25 TCY
—
ns
—
PM5
PM6
PMRD Pulse-Width
—
—
0.5 TCY
—
—
—
ns
ns
—
—
PMRD or PMENB Active to Data In Valid (data
setup time)
PM7
PMRD or PMENB Inactive to Data In Invalid
(data hold time)
—
—
—
ns
—
DS70292D-page 364
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
FIGURE 30-25:
PARALLEL MASTER PORT WRITE TIMING DIAGRAM
P2
P1
P3
P4
P1
P2
P3
P4
P2
P1
System
Clock
PMA<13:8>
PMD<7:0>
Address
Address <7:0>
Data
PM12
PM13
PMRD
PMWR
PM11
PMALL/PMALH
PM16
PMCS1
TABLE 30-49: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +85°C for Industrial
-40°C TA +125°C for Extended
AC CHARACTERISTICS
Param
No.
Characteristic
Min.
Typ
Max.
Units
Conditions
PM11 PMWR Pulse-Width
—
—
0.5 TCY
—
—
—
ns
ns
—
—
PM12 Data Out Valid before PMWR or PMENB goes
Inactive (data setup time)
PM13 PMWR or PMEMB Invalid to Data Out Invalid
(data hold time)
—
—
—
—
—
ns
ns
—
—
PM16 PMCSx Pulse-Width
TCY - 5
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 365
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 366
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
31.0 HIGH TEMPERATURE ELECTRICAL CHARACTERISTICS
This section provides an overview of dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/
X04 electrical characteristics for devices operating in an ambient temperature range of -40°C to +140°C.
Note:
Programming of the Flash memory is not allowed above 125°C.
The specifications between -40°C to +140°C are identical to those shown in Section 30.0 “Electrical Characteristics”
for operation between -40°C to +125°C, with the exception of the parameters listed in this section.
Parameters in this section begin with an H, which denotes High temperature. For example, parameter DC10 in
Section 30.0 “Electrical Characteristics” is the Industrial and Extended temperature equivalent of HDC10.
Absolute maximum ratings for the dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/X04
high temperature devices are listed below. Exposure to these maximum rating conditions for extended periods can affect
device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in
the operation listings of this specification is not implied.
(1)
Absolute Maximum Ratings
Ambient temperature under bias(4) .........................................................................................................-40°C to +140°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant with respect to VSS(5) .................................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD < 3.0V(5) ....................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD 3.0V(5) .................................................... -0.3V to 5.6V
Voltage on VCAP/VDDCORE with respect to VSS ....................................................................................... 2.25V to 2.75V
Maximum current out of VSS pin .............................................................................................................................60 mA
Maximum current into VDD pin(2).............................................................................................................................60 mA
Maximum junction temperature............................................................................................................................. +145°C
Maximum output current sunk by any I/O pin(3) ........................................................................................................1 mA
Maximum output current sourced by any I/O pin(3)...................................................................................................1 mA
Maximum current sunk by all ports combined ........................................................................................................10 mA
Maximum current sourced by all ports combined(2) ................................................................................................10 mA
Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions
above those indicated in the operation listings of this specification is not implied. Exposure to maximum
rating conditions for extended periods can affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 31-2).
3: Unlike devices at 125°C and below, the specifications in this section also apply to the CLKOUT, VREF+,
VREF-, SCLx, SDAx, PGCx, and PGDx pins.
4: AEC-Q100 reliability testing for devices intended to operate at 150°C is 1,000 hours. Any design in which
the total operating time from 125°C to 150°C will be greater than 1,000 hours is not warranted without prior
written approval from Microchip Technology Inc.
5: Refer to the “Pin Diagrams” section for 5V tolerant pins.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 367
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
31.1 High Temperature DC Characteristics
TABLE 31-1: OPERATING MIPS VS. VOLTAGE
Max MIPS
VDD Range
(in Volts)
Temperature Range
(in °C)
dsPIC33FJ32GP302/304,
dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04
Characteristic
3.0V to 3.6V
-40°C to +140°C
20
TABLE 31-2: THERMAL OPERATING CONDITIONS
Rating
Symbol
Min
Typ
Max
Unit
High Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range
TJ
TA
-40
-40
—
—
+145
+140
°C
°C
Power Dissipation:
Internal chip power dissipation:
PINT = VDD x (IDD - IOH)
PD
PINT + PI/O
W
W
I/O Pin Power Dissipation:
I/O = ({VDD - VOH} x IOH) + (VOL x IOL)
Maximum Allowed Power Dissipation
PDMAX
(TJ - TA)/JA
TABLE 31-3: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
DC CHARACTERISTICS
Parameter
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
Operating Voltage
HDC10
Supply Voltage
VDD
—
3.0
3.3
3.6
V
-40°C to +140°C
TABLE 31-4: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
Parameter
Typical
No.
Max
Units
Conditions
Power-Down Current (IPD)
HDC60e
HDC61c
250
3
2000
5
A
A
+140°C
+140°C
3.3V
3.3V
Base Power-Down Current(1,3)
(2,4)
Watchdog Timer Current: IWDT
Note 1: Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and
pulled to VSS. WDT, etc., are all switched off, and VREGS (RCON<8>) = 1.
2: The current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
3: These currents are measured on the device containing the most memory in this family.
4: These parameters are characterized, but are not tested in manufacturing.
DS70292D-page 368
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 31-5: DC CHARACTERISTICS: DOZE CURRENT (IDOZE)
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
Parameter
Typical(1)
No.
Doze
Ratio
Max
Units
Conditions
HDC72a
HDC72f
HDC72g
39
18
18
45
25
25
1:2
1:64
1:128
mA
mA
mA
+140°C
3.3V
20 MIPS
Note 1: Parameters with Doze ratios of 1:2 and 1:64 are characterized, but are not tested in manufacturing.
TABLE 31-6: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V
DC CHARACTERISTICS
(unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
VOL
Output Low Voltage
I/O ports
HDO10
HDO16
—
—
—
—
0.4
0.4
V
V
IOL = 1 mA, VDD = 3.3V
IOL = 1 mA, VDD = 3.3V
OSC2/CLKO
VOH
Output High Voltage
I/O ports
HDO20
HDO26
2.40
2.41
—
—
—
—
V
V
IOH = -1 mA, VDD = 3.3V
IOH = -1 mA, VDD = 3.3V
OSC2/CLKO
TABLE 31-7: DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C TA +140°C for High Temperature
Param
No.
Symbol
Characteristic(1)
Min
Typ
Max
Units
Conditions
Program Flash Memory
Cell Endurance
HD130 EP
10,000
20
—
—
—
—
E/W -40C to +140C(2)
HD134 TRETD
Characteristic Retention
Year 1000 E/W cycles or less and no
other specifications are violated
Note 1: These parameters are assured by design, but are not characterized or tested in manufacturing.
2: Programming of the Flash memory is not allowed above 125°C.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 369
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
31.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 AC characteristics and
timing parameters for high temperature devices.
However, all AC timing specifications in this section are
the same as those in Section 30.2 “AC
Characteristics and Timing Parameters”, with the
exception of the parameters listed in this section.
Parameters in this section begin with an H, which
denotes High temperature. For example, parameter
OS53 in Section 30.2 “AC Characteristics and
Timing Parameters” is the Industrial and Extended
temperature equivalent of HOS53.
TABLE 31-8: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
Standard Operating Conditions: 3.0V to 3.6V
(unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC CHARACTERISTICS
Operating voltage VDD range as described in Table 31-1.
FIGURE 31-1:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 1 – for all pins except OSC2
VDD/2
Load Condition 2 – for OSC2
CL
RL
Pin
VSS
CL
Pin
RL = 464
CL = 50 pF for all pins except OSC2
15 pF for OSC2 output
VSS
TABLE 31-9: PLL CLOCK TIMING SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
HOS53
DCLK
CLKO Stability (Jitter)(1)
-5
0.5
5
%
Measured over 100 ms
period
Note 1: These parameters are characterized, but are not tested in manufacturing.
DS70292D-page 370
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 31-10: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
HSP35
HSP40
HSP41
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
10
25
ns
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
28
35
—
—
—
—
ns
ns
—
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 31-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
HSP35 TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
10
25
ns
—
HSP36 TdoV2sc, SDOx Data Output Setup to
TdoV2scL First SCKx Edge
35
28
35
—
—
—
—
—
—
ns
ns
ns
—
—
—
HSP40 TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
HSP41 TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
Note 1: These parameters are characterized but not tested in manufacturing.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 371
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 31-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max Units
Conditions
HSP35 TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
HSP40 TdiV2scH, Setup Time of SDIx Data Input
—
—
35
—
—
55
ns
ns
ns
ns
—
25
25
15
—
—
—
—
—
TdiV2scL
to SCKx Edge
HSP41 TscH2diL,
TscL2diL
Hold Time of SDIx Data Input to
SCKx Edge
See Note 2
HSP51 TssH2doZ SSx to SDOx Output
High-Impedance
Note 1: These parameters are characterized but not tested in manufacturing.
2: Assumes 50 pF load on all SPIx pins.
TABLE 31-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic(1)
Min
Typ
Max
Units
Conditions
HSP35
HSP40
HSP41
HSP51
HSP60
TscH2doV, SDOx Data Output Valid after
TscL2doV SCKx Edge
—
—
35
ns
—
TdiV2scH, Setup Time of SDIx Data Input
TdiV2scL to SCKx Edge
25
25
15
—
—
—
—
—
—
—
55
55
ns
ns
ns
ns
—
—
TscH2diL, Hold Time of SDIx Data Input
TscL2diL
to SCKx Edge
See Note 2
TssH2doZ SSx to SDOX Output
High-Impedance
TssL2doV SDOx Data Output Valid after
SSx Edge
—
Note 1: These parameters are characterized but not tested in manufacturing.
2: Assumes 50 pF load on all SPIx pins.
DS70292D-page 372
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 31-14: ADC MODULE SPECIFICATIONS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max Units
Conditions
Reference Inputs
HAD08
IREF
Current Drain
—
—
250
—
600
50
A ADC operating, See Note 1
A ADC off, See Note 1
Note 1: These parameters are not characterized or tested in manufacturing.
2: These parameters are characterized, but are not tested in manufacturing.
TABLE 31-15: ADC MODULE SPECIFICATIONS (12-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
ADC Accuracy (12-bit Mode) – Measurements with External VREF+/VREF-(1)
HAD20a Nr
HAD21a INL
Resolution
12 data bits
—
bits
—
Integral Nonlinearity
-2
> -1
-2
+2
< 1
10
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22a DNL
HAD23a GERR
HAD24a EOFF
Differential Nonlinearity
Gain Error
—
—
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
-3
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
ADC Accuracy (12-bit Mode) – Measurements with Internal VREF+/VREF-(1)
HAD20a Nr
Resolution
12 data bits
bits
—
HAD21a INL
HAD22a DNL
HAD23a GERR
HAD24a EOFF
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
> -1
2
—
—
—
—
+2
< 1
20
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
Offset Error
2
10
Dynamic Performance (12-bit Mode)(2)
HAD33a FNYQ
Input Signal Bandwidth 200 kHz
—
—
—
Note 1: These parameters are characterized, but are tested at 20 ksps only.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 373
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 31-16: ADC MODULE SPECIFICATIONS (10-BIT MODE)
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
ADC Accuracy (10-bit Mode) – Measurements with External VREF+/VREF-(1)
HAD20b Nr
HAD21b INL
Resolution
10 data bits
—
bits
—
Integral Nonlinearity
-3
> -1
-5
3
< 1
6
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
HAD22b DNL
HAD23b GERR
HAD24b EOFF
Differential Nonlinearity
Gain Error
—
—
—
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
Offset Error
-1
5
LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.6V
ADC Accuracy (10-bit Mode) – Measurements with Internal VREF+/VREF-(1)
HAD20b Nr
Resolution
10 data bits
bits
—
HAD21b INL
HAD22b DNL
HAD23b GERR
HAD24b EOFF
Integral Nonlinearity
Differential Nonlinearity
Gain Error
-2
> -1
-5
—
—
—
—
2
< 1
15
7
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
LSb VINL = AVSS = 0V, AVDD = 3.6V
Offset Error
-1.5
Dynamic Performance (10-bit Mode)(2)
HAD33b FNYQ
Input Signal Bandwidth 400 kHz
—
—
—
Note 1: These parameters are characterized, but are tested at 20 ksps only.
2: These parameters are characterized by similarity, but are not tested in manufacturing.
DS70292D-page 374
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE 31-17: ADC CONVERSION (12-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
Clock Parameters
HAD50 TAD
ADC Clock Period(1)
Throughput Rate(1)
147
Conversion Rate
—
—
—
ns
—
—
HAD56 FCNV
—
400
Ksps
Note 1: These parameters are characterized but not tested in manufacturing.
TABLE 31-18: ADC CONVERSION (10-BIT MODE) TIMING REQUIREMENTS
Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated)
Operating temperature -40°C TA +140°C for High Temperature
AC
CHARACTERISTICS
Param
Symbol
No.
Characteristic
Min
Typ
Max
Units
Conditions
Clock Parameters
HAD50
HAD56
TAD
ADC Clock Period(1)
Throughput Rate(1)
104
—
—
ns
—
—
Conversion Rate
FCNV
—
—
800
Ksps
Note 1: These parameters are characterized but not tested in manufacturing.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 375
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 376
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
32.0 PACKAGING INFORMATION
28-Lead SPDIP
Example
dsPIC33FJ32GP
302-E/SP
0730235
XXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXX
YYWWNNN
e
3
28-Lead SOIC (.300”)
Example
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
XXXXXXXXXXXXXXXXXXXX
dsPIC33FJ32GP
302-E/SO
e
3
0730235
YYWWNNN
28-Lead QFN-S
Example
XXXXXXXX
XXXXXXXX
YYWWNNN
33FJ32GP
3
e
302EMM
0730235
44-Lead QFN
Example
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
dsPIC
33FJ32GP304
-E/ML
0730235
e
3
Example
44-Lead TQFP
dsPIC
XXXXXXXXXX
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
33FJ32GP304
-I/PT
e3
0730235
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: If the full Microchip part number cannot be marked on one line, it is carried over to the next
line, thus limiting the number of available characters for customer-specific information.
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 377
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
32.1 Package Details
28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
N
NOTE 1
E1
1
2 3
D
E
A2
A
L
c
b1
A1
b
e
eB
Units
Dimension Limits
INCHES
NOM
28
.100 BSC
–
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
–
.200
.150
–
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.120
.015
.290
.240
1.345
.110
.008
.040
.014
–
.135
–
.310
.285
1.365
.130
.010
.050
.018
–
.335
.295
1.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing §
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-070B
DS70292D-page 378
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
N
E
E1
NOTE 1
1
2
3
e
b
h
α
h
c
φ
A2
A
L
A1
L1
β
Units
MILLMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
28
1.27 BSC
Overall Height
Molded Package Thickness
Standoff §
A
–
2.05
0.10
–
–
–
2.65
–
0.30
A2
A1
E
Overall Width
10.30 BSC
Molded Package Width
Overall Length
Chamfer (optional)
Foot Length
E1
D
h
7.50 BSC
17.90 BSC
0.25
0.40
–
–
0.75
1.27
L
Footprint
L1
φ
c
b
α
1.40 REF
Foot Angle Top
Lead Thickness
Lead Width
Mold Draft Angle Top
Mold Draft Angle Bottom
0°
0.18
0.31
5°
–
–
–
–
–
8°
0.33
0.51
15°
β
5°
15°
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-052B
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 379
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
28-Lead Plastic Quad Flat, No Lead Package (MM) – 6x6x0.9 mm Body [QFN-S]
with 0.40 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
E2
E
b
2
1
2
1
K
N
N
L
NOTE 1
BOTTOM VIEW
TOP VIEW
A
A3
A1
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
N
e
A
A1
A3
E
E2
D
28
0.65 BSC
0.90
0.80
0.00
1.00
0.05
0.02
0.20 REF
6.00 BSC
3.70
6.00 BSC
3.70
0.38
0.40
–
3.65
4.70
D2
b
L
3.65
0.23
0.30
0.20
4.70
0.43
0.50
–
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-124B
DS70292D-page 380
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
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'ꢌꢋ(ꢇꢛꢜ)ꢛꢇ!!ꢇ*ꢓ+ꢋꢅꢍꢋꢇꢃꢄ+ꢕꢋ(
ꢒꢓꢋꢄ, ꢀꢁꢂꢃ ꢄꢅꢃ!ꢁ" ꢃꢆ#ꢂꢂꢅꢇ ꢃꢈꢉꢆ$ꢉꢊꢅꢃ%ꢂꢉ&ꢋꢇꢊ"'ꢃꢈꢌꢅꢉ"ꢅꢃ"ꢅꢅꢃ ꢄꢅꢃꢍꢋꢆꢂꢁꢆꢄꢋꢈꢃ(ꢉꢆ$ꢉꢊꢋꢇꢊꢃꢎꢈꢅꢆꢋ)ꢋꢆꢉ ꢋꢁꢇꢃꢌꢁꢆꢉ ꢅ%ꢃꢉ ꢃ
ꢄ ꢈ*++&&&ꢏ!ꢋꢆꢂꢁꢆꢄꢋꢈꢏꢆꢁ!+ꢈꢉꢆ$ꢉꢊꢋꢇꢊ
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 381
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D2
D
EXPOSED
PAD
e
b
K
E
E2
2
1
2
1
N
N
NOTE 1
L
TOP VIEW
BOTTOM VIEW
A
A3
A1
Units
MILLIMETERS
Dimension Limits
MIN
NOM
44
0.65 BSC
0.90
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Width
N
e
A
A1
A3
E
E2
D
0.80
0.00
1.00
0.05
0.02
0.20 REF
8.00 BSC
6.45
8.00 BSC
6.45
0.30
0.40
–
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
6.30
6.80
D2
b
L
6.30
0.25
0.30
0.20
6.80
0.38
0.50
–
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-103B
DS70292D-page 382
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
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ꢒꢓꢋꢄ, ꢀꢁꢂꢃ ꢄꢅꢃ!ꢁ" ꢃꢆ#ꢂꢂꢅꢇ ꢃꢈꢉꢆ$ꢉꢊꢅꢃ%ꢂꢉ&ꢋꢇꢊ"'ꢃꢈꢌꢅꢉ"ꢅꢃ"ꢅꢅꢃ ꢄꢅꢃꢍꢋꢆꢂꢁꢆꢄꢋꢈꢃ(ꢉꢆ$ꢉꢊꢋꢇꢊꢃꢎꢈꢅꢆꢋ)ꢋꢆꢉ ꢋꢁꢇꢃꢌꢁꢆꢉ ꢅ%ꢃꢉ ꢃ
ꢄ ꢈ*++&&&ꢏ!ꢋꢆꢂꢁꢆꢄꢋꢈꢏꢆꢁ!+ꢈꢉꢆ$ꢉꢊꢋꢇꢊ
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 383
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
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D1
E
e
E1
N
b
NOTE 1
1 2 3
NOTE 2
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A
c
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A2
β
A1
L
L1
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DS70292D-page 384
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
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2009 Microchip Technology Inc.
Preliminary
DS70292D-page 385
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 386
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
APPENDIX A: REVISION HISTORY
Revision A (September 2007)
Initial release of this document.
Revision B (March 2008)
This revision includes minor typographical and
formatting changes throughout the data sheet text. In
addition, redundant information was removed that is
now available in the respective chapters of the
dsPIC33F/PIC24H Family Reference Manual, which
can be obtained from the Microchip website
(www.microchip.com).
The major changes are referenced by their respective
section in the following table.
TABLE A-1:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit Digital Signal
Controllers”
Note 1 added to all pin diagrams (see “Pin Diagrams”).
Add External Interrupts column and Note 3 to the
“dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, and
dsPIC33FJ128GPX02/X04 Controller Families” table.
Section 1.0 “Device Overview”
Section 6.0 “Interrupt Controller”
Updated parameters PMA0, PMA1, and PMD0 through PMPD7
(Table 1-1).
IFS0-IFSO4 changed to IFSX (see Section 6.3.2 “IFSx”).
IEC0-IEC4 changed to IECX (see Section 6.3.3 “IECx”).
IPC0-IPC19 changed to IPCx (see Section 6.3.4 “IPCx”).
Section 7.0 “Direct Memory Access (DMA)” Updated parameter PMP (see Table 7-1).
Section 8.0 “Oscillator Configuration”
Updated the third clock source item (External Clock) in
Section 8.1.1 “System Clock Sources”.
Updated TUN<5:0> (OSCTUN<5:0>) bit description (see
Register 8-4).
Section 20.0 “10-Bit/12-Bit Analog-to-Digital Added Note 2 to Figure 20-3.
Converter (ADC1)”
Section 26.0 “Special Features”
Added Note 2 to Figure 26-1.
Added Note after second paragraph in Section 26.2 “On-Chip
Voltage Regulator”.
Section 29.0 “Electrical Characteristics”
Updated Max MIPS for temperature range of -40ºC to +125ºC in
Table 29-1.
Updated typical values in Thermal Packaging Characteristics in
Table 29-3.
Added parameters DI11 and DI12 to Table 29-9.
Updated minimum values for parameters D136 (TRW) and D137
(TPE) and removed typical values in Table 29-12.
Added Extended temperature range to Table 29-13.
Updated parameter AD63 and added Note 3 to Table 29-40 and
Table 29-41.
2009 Microchip Technology Inc.
Preliminary
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Revision C (May 2009)
This revision includes minor typographical and
formatting changes throughout the data sheet text.
Global changes include:
• Changed all instances of OSCI to OSC1 and
OSCO to OSC2
• Changed all instances of VDDCORE and VDDCORE/
VCAP to VCAP/VDDCORE
The other changes are referenced by their respective
section in the following table.
TABLE A-2:
MAJOR SECTION UPDATES
Section Name
Update Description
High-Performance, 16-Bit Digital
Signal Controllers
Updated all pin diagrams to denote the pin voltage tolerance (see “Pin
Diagrams”).
Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which
references pin connections to VSS.
Section 1.0 “Device Overview”
Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1).
Added Peripheral Pin Select (PPS) capability column to Pinout I/O
Descriptions (see Table 1-1).
Section 2.0 “Guidelines for Getting Added new section to the data sheet that provides guidelines on getting
Started with 16-Bit Digital Signal
Controllers”
started with 16-bit Digital Signal Controllers.
Section 3.0 “CPU”
Updated CPU Core Block Diagram with a connection from the DSP Engine
to the Y Data Bus (see Figure 3-1).
Vertically extended the X and Y Data Bus lines in the DSP Engine Block
Diagram (see Figure 3-3).
Section 4.0 “Memory Organization” Updated Reset value for CORCON in the CPU Core Register Map (see
Table 4-1).
Updated the Reset values for IPC14 and IPC15 and removed the FLTA1IE
bit (IEC3) from the Interrupt Controller Register Map (see Table 4-4).
Updated bit locations for RPINR25 in the Peripheral Pin Select Input
Register Map (see Table 4-21).
Updated the Reset value for CLKDIV in the System Control Register Map
(see Table 4-33).
Section 5.0 “Flash Program
Memory”
Updated Section 5.3 “Programming Operations” with programming time
formula.
Section 9.0 “Oscillator
Configuration”
Updated the Oscillator System Diagram and added Note 2 (see Figure 9-1).
Added Note 1 and Note 2 to the OSCON register (see Register 9-1).
Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock
Divisor (CLKDIV) Register (see Register 9-2).
Added a paragraph regarding FRC accuracy at the end of Section 9.1.1
“System Clock Sources”.
Added Note 3 to Section 9.2.2 “Oscillator Switching Sequence”.
Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see
Register 9-4).
DS70292D-page 388
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2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE A-2:
MAJOR SECTION UPDATES (CONTINUED)
Update Description
Added the following registers:
Section Name
Section 10.0 “Power-Saving
Features”
• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)
• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)
• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)
Section 11.0 “I/O Ports”
Removed Table 11-1 and added reference to pin diagrams for I/O pin
availability and functionality.
Added paragraph on ADPCFG register default values to Section 11.3
“Configuring Analog Port Pins”.
Added Note box regarding PPS functionality with input mapping to
Section 11.6.2.1 “Input Mapping”.
Section 16.0 “Serial Peripheral
Interface (SPI)”
Added Note 2 and 3 to the SPIxCON1 register (see Register 16-2).
Updated the Notes in the UxMode register (see Register 18-1).
Section 18.0 “Universal
Asynchronous Receiver Transmitter
(UART)”
Updated the UTXINV bit settings in the UxSTA register and added Note 1
(see Register 18-2).
Section 19.0 “Enhanced CAN
(ECAN™) Module”
Changed bit 11 in the ECAN Control Register 1 (CiCTRL1) to Reserved (see
Register 19-1).
Section 21.0 “10-Bit/12-Bit Analog- Replaced the ADC1 Module Block Diagrams with new diagrams (see
to-Digital Converter (ADC)”
Figure 21-1 and Figure 21-2).
Updated bit values for ADCS<7:0> and added Notes 1 and 2 to the ADC1
Control Register 3 (AD1CON3) (see Register 21-3).
Added Note 2 to the ADC1 Input Scan Select Register Low (AD1CSSL) (see
Register 21-7).
Added Note 2 to the ADC1 Port Configuration Register Low (AD1PCFGL)
(see Register 21-8).
Section 22.0 “Audio Digital-to-
Analog Converter (DAC)”
Updated the midpoint voltage in the last sentence of the first paragraph.
Updated the voltage swing values in the last sentence of the last paragraph
in Section 22.3 “DAC Output Format”.
Section 23.0 “Comparator Module” Updated the Comparator Voltage Reference Block Diagram
(see Figure 23-2).
Section 24.0 “Real-Time Clock and Updated the minimum positive adjust value for CAL<7:0> in the RTCC
Calendar (RTCC)”
Calibration and Configuration (RCFGCAL) Register (see Register 24-1).
Section 27.0 “Special Features”
Added Note 1 to the Device Configuration Register Map (see Table 27-1).
Updated Note 1 in the dsPIC33F Configuration Bits Description (see
Table 27-2).
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 389
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
TABLE A-2:
MAJOR SECTION UPDATES (CONTINUED)
Section Name
Update Description
Section 30.0 “Electrical
Characteristics”
Updated Typical values for Thermal Packaging Characteristics (see
Table 30-3).
Updated Min and Max values for parameter DC12 (RAM Data Retention
Voltage) and added Note 4 (see Table 30-4).
Updated Power-Down Current Max values for parameters DC60b and
DC60c (see Table 30-7).
Updated Characteristics for I/O Pin Input Specifications and added
parameter DI21 (see Table 30-9).
Updated Program Memory values for parameters 136, 137, and 138
(renamed to 136a, 137a, and 138a), added parameters 136b, 137b, and
138b, and added Note 2 (see Table 30-12).
Added parameter OS42 (GM) to the External Clock Timing Requirements
(see Table 30-16).
Updated Watchdog Timer Time-out Period parameter SY20 (see
Table 30-21).
Updated the IREF Current Drain parameter AD08 (see Table 30-37).
Updated parameters AD30a, AD31a, AD32a, AD33a, and AD34a (see
Table 30-38)
Updated parameters AD30b, AD31b, AD32b, AD33b, and AD34b (see
Table 30-39)
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Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Revision D (November 2009)
The revision includes the following global update:
• Added Note 2 to the shaded table that appears at
the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits
This revision also includes minor typographical and
formatting changes throughout the data sheet text.
All other major changes are referenced by their
respective section in the following table.
TABLE A-3:
MAJOR SECTION UPDATES
Section Name
Update Description
“High-Performance, 16-Bit Digital Signal
Controllers”
Added information on high temperature operation (see “Operating
Range:”).
Section 11.0 “I/O Ports”
Changed the reference to digital-only pins to 5V tolerant pins in the
second paragraph of Section 11.2 “Open-Drain Configuration”.
Section 18.0 “Universal Asynchronous
Receiver Transmitter (UART)”
Updated the two baud rate range features to: 10 Mbps to 38 bps at
40 MIPS.
Section 21.0 “10-Bit/12-Bit Analog-to-
Digital Converter (ADC)”
Updated the ADC block diagrams (see Figure 21-1 and Figure 21-2).
Section 22.0 “Audio Digital-to-Analog
Converter (DAC)”
Removed last sentence of the first paragraph in the section.
Added a shaded note to Section 22.2 “DAC Module Operation”.
Updated Figure 22-2: “Audio DAC Output for Ramp Input
(Unsigned)”.
Section 27.0 “Special Features”
Updated the second paragraph and removed the fourth paragraph in
Section 27.1 “Configuration Bits”.
Updated the Device Configuration Register Map (see Table 27-1).
Section 30.0 “Electrical Characteristics”
Updated the Absolute Maximum Ratings for high temperature and
added Note 4.
Removed parameters DI26, DI28, and DI29 from the I/O Pin Input
Specifications (see Table 30-9).
Updated the SPIx Module Slave Mode (CKE = 1) Timing
Characteristics (see Figure 30-12).
Removed Table 30-43: Audio DAC Module Specifications. Original
contents were updated and combined with Table 30-42 of the same
name.
Section 31.0 “High Temperature Electrical Added new chapter with high temperature specifications.
Characteristics”
“Product Identification System”
Added the “H” definition for high temperature.
2009 Microchip Technology Inc.
Preliminary
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NOTES:
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Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
INDEX
CPU
A
Control Register.......................................................... 28
A/D Converter ................................................................... 253
CPU Clocking System ...................................................... 142
DMA.......................................................................... 253
PLL Configuration..................................................... 143
Initialization ............................................................... 253
Selection................................................................... 142
Key Features............................................................. 253
Sources .................................................................... 142
AC Characteristics .................................................... 332, 372
Customer Change Notification Service............................. 401
ADC Module.............................................................. 375
Customer Notification Service .......................................... 401
ADC Module (10-bit Mode) ....................................... 376
Customer Support............................................................. 401
ADC Module (12-bit Mode) ....................................... 375
Internal RC Accuracy................................................ 334
D
Load Conditions................................................ 332, 372
Data Accumulators and Adder/Subtracter .......................... 34
ADC Module
Data Space Write Saturation...................................... 36
ADC11 Register Map.................................................. 51
Overflow and Saturation............................................. 34
Alternate Interrupt Vector Table (AIVT) .............................. 87
Round Logic ............................................................... 35
Arithmetic Logic Unit (ALU)................................................. 32
Write Back .................................................................. 35
Assembler
Data Address Space........................................................... 39
MPASM Assembler................................................... 320
Alignment.................................................................... 39
Memory Map for dsPIC33FJ128GP202/204 and
B
dsPIC33FJ64GP202/204 Devices
with 8 KB RAM ................................................... 41
Memory Map for dsPIC33FJ128GP802/804 and
Barrel Shifter ....................................................................... 36
Bit-Reversed Addressing .................................................... 66
Example...................................................................... 67
Implementation ........................................................... 66
Sequence Table (16-Entry)......................................... 67
dsPIC33FJ64GP802/804 Devices
with 16 KB RAM ................................................. 42
Memory Map for dsPIC33FJ32GP302/304
Block Diagrams
Devices with 4 KB RAM...................................... 40
16-bit Timer1 Module................................................ 187
A/D Module ....................................................... 254, 255
Near Data Space........................................................ 39
Software Stack ........................................................... 63
Connections for On-Chip Voltage Regulator............. 305
Width .......................................................................... 39
DCI Module............................................................... 247
Data Converter Interface (DCI) Module............................ 247
Device Clock..................................................... 141, 143
DC Characteristics............................................................ 324
DSP Engine ................................................................ 33
Doze Current (IDOZE)................................................ 371
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
High Temperature..................................................... 370
and dsPIC33FJ128GPX02/X04......................... 16
I/O Pin Input Specifications ...................................... 329
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
I/O Pin Output........................................................... 371
and dsPIC33FJ128GPX02/X04 CPU Core........ 26
I/O Pin Output Specifications.................................... 330
ECAN Module ........................................................... 222
Idle Current (IDOZE) .................................................. 328
Input Capture ............................................................ 195
Idle Current (IIDLE).................................................... 327
Output Compare ....................................................... 197
Operating Current (IDD) ............................................ 326
PLL............................................................................ 143
Operating MIPS vs. Voltage ..................................... 370
Reset System.............................................................. 79
Power-Down Current (IPD)........................................ 328
Shared Port Structure ............................................... 159
Power-down Current (IPD) ........................................ 370
SPI ............................................................................ 201
Program Memory.............................................. 331, 371
Timer2 (16-bit) .......................................................... 189
Temperature and Voltage......................................... 370
Timer2/3 (32-bit) ....................................................... 191
Temperature and Voltage Specifications.................. 325
UART ........................................................................ 215
Thermal Operating Conditions.................................. 370
Watchdog Timer (WDT)............................................ 306
DCI
Introduction............................................................... 247
DCI Module
C
C Compilers
Register Map .............................................................. 56
Demonstration/Development Boards, Evaluation Kits,
and Starter Kits......................................................... 322
Development Support....................................................... 319
DMA Module
DMA Register Map ..................................................... 52
DMAC Registers............................................................... 131
DMAxCNT ................................................................ 131
DMAxCON................................................................ 131
DMAxPAD ................................................................ 131
DMAxREQ................................................................ 131
DMAxSTA................................................................. 131
DMAxSTB................................................................. 131
Doze Mode ....................................................................... 154
DSP Engine ........................................................................ 32
Multiplier ..................................................................... 34
Hi-Tech C.................................................................. 320
MPLAB C .................................................................. 320
Clock Switching................................................................. 151
Enabling.................................................................... 151
Sequence.................................................................. 151
Code Examples
Erasing a Program Memory Page............................... 77
Initiating a Programming Sequence............................ 78
Loading Write Buffers ................................................. 78
Port Write/Read ........................................................ 160
PWRSAV Instruction Syntax..................................... 153
Code Protection ........................................................ 301, 307
Comparator Module .......................................................... 265
Configuration Bits.............................................................. 301
Configuration Register Map .............................................. 301
Configuring Analog Port Pins............................................ 160
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
ECAN TX/RX Buffer m Control Register (CiTRmnCON).. 242
Electrical Characteristics .................................................. 323
E
ECAN Module
AC..................................................................... 332, 372
CiBUFPNT1 register .................................................233
Enhanced CAN Module .................................................... 221
CiBUFPNT2 register .................................................234
CiBUFPNT3 register .................................................234
Equations
Device Operating Frequency.................................... 142
CiBUFPNT4 register .................................................235
Errata.................................................................................. 14
CiCFG1 register ........................................................231
CiCFG2 register ........................................................232
F
CiCTRL1 register ......................................................224
Flash Program Memory ...................................................... 73
CiCTRL2 register ......................................................225
Control Registers........................................................ 74
CiEC register.............................................................231
Operations .................................................................. 74
CiFCTRL register......................................................227
Programming Algorithm.............................................. 77
CiFEN1 register ........................................................233
RTSP Operation ......................................................... 74
CiFIFO register .........................................................228
Table Instructions ....................................................... 73
CiFMSKSEL1 register...............................................237
Flexible Configuration....................................................... 301
CiFMSKSEL2 register...............................................238
CiINTE register .........................................................230
CiINTF register..........................................................229
H
High Temperature Electrical Characteristics .................... 369
CiRXFnEID register ..................................................237
CiRXFnSID register ..................................................236
CiRXFUL1 register....................................................240
CiRXFUL2 register....................................................240
CiRXMnEID register..................................................239
CiRXMnSID register..................................................239
CiRXOVF1 register ...................................................241
CiRXOVF2 register ...................................................241
CiTRmnCON register................................................242
CiVEC register ..........................................................226
ECAN1 Register Map (C1CTRL1.WIN = 0 or 1).........54
ECAN1 Register Map (C1CTRL1.WIN = 0) ................54
ECAN1 Register Map (C1CTRL1.WIN = 1) ................55
Frame Types.............................................................221
Modes of Operation ..................................................223
Overview ...................................................................221
I
I/O Ports............................................................................ 159
Parallel I/O (PIO) ...................................................... 159
Write/Read Timing.................................................... 160
2
I C
Operating Modes...................................................... 207
Registers .................................................................. 207
In-Circuit Debugger........................................................... 307
In-Circuit Emulation .......................................................... 301
In-Circuit Serial Programming (ICSP)....................... 301, 307
Input Capture.................................................................... 195
Registers .................................................................. 196
Input Change Notification ................................................. 160
Instruction Addressing Modes ............................................ 63
File Register Instructions ............................................ 63
Fundamental Modes Supported ................................. 64
MAC Instructions ........................................................ 64
MCU Instructions ........................................................ 63
Move and Accumulator Instructions............................ 64
Other Instructions ....................................................... 64
Instruction Set
ECAN Registers
Acceptance Filter Enable Register (CiFEN1)............233
Acceptance Filter Extended Identifier Register n
(CiRXFnEID).....................................................237
Acceptance Filter Mask Extended Identifier Register n
(CiRXMnEID) ....................................................239
Acceptance Filter Mask Standard Identifier Register n
(CiRXMnSID) ....................................................239
Acceptance Filter Standard Identifier Register n (CiRXF-
nSID).................................................................236
Baud Rate Configuration Register 1 (CiCFG1).........231
Baud Rate Configuration Register 2 (CiCFG2).........232
Control Register 1 (CiCTRL1)...................................224
Control Register 2 (CiCTRL2)...................................225
FIFO Control Register (CiFCTRL) ............................227
FIFO Status Register (CiFIFO) .................................228
Filter 0-3 Buffer Pointer Register (CiBUFPNT1) .......233
Filter 12-15 Buffer Pointer Register (CiBUFPNT4) ...235
Filter 15-8 Mask Selection Register (CiFMSKSEL2).238
Filter 4-7 Buffer Pointer Register (CiBUFPNT2) .......234
Filter 7-0 Mask Selection Register (CiFMSKSEL1)...237
Filter 8-11 Buffer Pointer Register (CiBUFPNT3) .....234
Interrupt Code Register (CiVEC) ..............................226
Interrupt Enable Register (CiINTE) ...........................230
Interrupt Flag Register (CiINTF) ...............................229
Receive Buffer Full Register 1 (CiRXFUL1)..............240
Receive Buffer Full Register 2 (CiRXFUL2)..............240
Receive Buffer Overflow Register 2 (CiRXOVF2).....241
Receive Overflow Register (CiRXOVF1) ..................241
ECAN Transmit/Receive Error Count Register (CiEC) .....231
Overview................................................................... 314
Summary .................................................................. 311
Instruction-Based Power-Saving Modes........................... 153
Idle............................................................................ 154
Sleep ........................................................................ 153
Internal RC Oscillator
Use with WDT........................................................... 306
Internet Address ............................................................... 401
Interrupt Control and Status Registers ............................... 91
IECx............................................................................ 91
IFSx ............................................................................ 91
INTCON1.................................................................... 91
INTCON2.................................................................... 91
IPCx............................................................................ 91
Interrupt Setup Procedures............................................... 128
Initialization............................................................... 128
Interrupt Disable ....................................................... 128
Interrupt Service Routine.......................................... 128
Trap Service Routine................................................ 128
Interrupt Vector Table (IVT)................................................ 87
Interrupts Coincident with Power Save Instructions ......... 154
J
JTAG Boundary Scan Interface........................................ 301
JTAG Interface.................................................................. 307
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Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
M
R
Memory Organization.......................................................... 37
Microchip Internet Web Site.............................................. 401
Modes of Operation
Reader Response............................................................. 402
Register Map
CRC............................................................................ 60
Dual Comparator ........................................................ 60
Parallel Master/Slave Port.......................................... 59
Real-Time Clock and Calendar .................................. 60
Registers
Disable...................................................................... 223
Initialization ............................................................... 223
Listen All Messages.................................................. 223
Listen Only................................................................ 223
Loopback .................................................................. 223
Normal Operation...................................................... 223
Modulo Addressing ............................................................. 65
Applicability................................................................. 66
Operation Example ..................................................... 65
Start and End Address................................................ 65
W Address Register Selection .................................... 65
MPLAB ASM30 Assembler, Linker, Librarian ................... 320
MPLAB ICD 3 In-Circuit Debugger System ...................... 321
MPLAB Integrated Development Environment Software .. 319
MPLAB PM3 Device Programmer .................................... 322
MPLAB REAL ICE In-Circuit Emulator System................. 321
MPLINK Object Linker/MPLIB Object Librarian ................ 320
AD1CHS0 (ADC1 Input Channel 0 Select................ 263
AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 262
AD1CON1 (ADC1 Control 1).................................... 257
AD1CON2 (ADC1 Control 2).................................... 259
AD1CON3 (ADC1 Control 3).................................... 260
AD1CON4 (ADC1 Control 4).................................... 261
AD1CSSL (ADC1 Input Scan Select Low) ............... 264
AD1PCFGL (ADC1 Port Configuration Low)............ 264
CiBUFPNT1 (ECAN Filter 0-3 Buffer Pointer) .......... 233
CiBUFPNT2 (ECAN Filter 4-7 Buffer Pointer) .......... 234
CiBUFPNT3 (ECAN Filter 8-11 Buffer Pointer) ........ 234
CiBUFPNT4 (ECAN Filter 12-15 Buffer Pointer) ...... 235
CiCFG1 (ECAN Baud Rate Configuration 1)............ 231
CiCFG2 (ECAN Baud Rate Configuration 2)............ 232
CiCTRL1 (ECAN Control 1)...................................... 224
CiCTRL2 (ECAN Control 2)...................................... 225
CiEC (ECAN Transmit/Receive Error Count) ........... 231
CiFCTRL (ECAN FIFO Control) ............................... 227
CiFEN1 (ECAN Acceptance Filter Enable)............... 233
CiFIFO (ECAN FIFO Status) .................................... 228
CiFMSKSEL1 (ECAN Filter 7-0 Mask Selection) .... 237,
238
CiINTE (ECAN Interrupt Enable).............................. 230
CiINTF (ECAN Interrupt Flag) .................................. 229
CiRXFnEID (ECAN Acceptance Filter n
Extended Identifier) .......................................... 237
CiRXFnSID (ECAN Acceptance Filter n
Standard Identifier)........................................... 236
CiRXFUL1 (ECAN Receive Buffer Full 1)................. 240
CiRXFUL2 (ECAN Receive Buffer Full 2)................. 240
CiRXMnEID (ECAN Acceptance Filter Mask n
Extended Identifier) .......................................... 239
CiRXMnSID (ECAN Acceptance Filter Mask n
N
NVM Module
Register Map............................................................... 62
O
Open-Drain Configuration ................................................. 160
Output Compare ............................................................... 197
P
Packaging ......................................................................... 379
Details....................................................................... 380
Marking ..................................................................... 379
Peripheral Module Disable (PMD) .................................... 154
PICkit 2 Development Programmer/Debugger and
PICkit 2 Debug Express............................................ 322
PICkit 3 In-Circuit Debugger/Programmer and
PICkit 3 Debug Express............................................ 321
Pinout I/O Descriptions (table)............................................ 17
PMD Module
Register Map............................................................... 62
PORTA
Register Map......................................................... 60, 61
PORTB
Register Map............................................................... 61
Power-on Reset (POR) ....................................................... 84
Power-Saving Features .................................................... 153
Clock Frequency and Switching................................ 153
Program Address Space..................................................... 37
Construction................................................................ 68
Data Access from Program Memory
Standard Identifier)........................................... 239
CiRXOVF1 (ECAN Receive Buffer Overflow 1)........ 241
CiRXOVF2 (ECAN Receive Buffer Overflow 2)........ 241
CiTRBnSID (ECAN Buffer n Standard Identifier)..... 243,
244, 246
CiTRmnCON (ECAN TX/RX Buffer m Control) ........ 242
CiVEC (ECAN Interrupt Code) ................................. 226
CLKDIV (Clock Divisor) ............................................ 147
CORCON (Core Control)...................................... 30, 93
DCICON1 (DCI Control 1) ........................................ 248
DCICON2 (DCI Control 2) ........................................ 249
DCICON3 (DCI Control 3) ........................................ 250
DCISTAT (DCI Status) ............................................. 251
DMACS0 (DMA Controller Status 0) ........................ 136
DMACS1 (DMA Controller Status 1) ........................ 138
DMAxCNT (DMA Channel x Transfer Count)........... 135
DMAxCON (DMA Channel x Control)....................... 132
DMAxPAD (DMA Channel x Peripheral Address) .... 135
DMAxREQ (DMA Channel x IRQ Select)................. 133
DMAxSTA (DMA Channel x RAM Start Address A). 134
DMAxSTB (DMA Channel x RAM Start Address B). 134
DSADR (Most Recent DMA RAM Address) ............. 139
I2CxCON (I2Cx Control)........................................... 209
I2CxMSK (I2Cx Slave Mode Address Mask)............ 213
I2CxSTAT (I2Cx Status)........................................... 211
Using Program Space Visibility........................... 71
Data Access from Program Memory
Using Table Instructions ..................................... 70
Data Access from, Address Generation...................... 69
Memory Map............................................................... 37
Table Read Instructions
TBLRDH ............................................................. 70
TBLRDL .............................................................. 70
Visibility Operation ...................................................... 71
Program Memory
Interrupt Vector ........................................................... 38
Organization................................................................ 38
Reset Vector ............................................................... 38
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 395
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
IFS0 (Interrupt Flag Status 0) ............................. 97, 104
IFS1 (Interrupt Flag Status 1) ............................. 99, 106
IFS2 (Interrupt Flag Status 2) ........................... 101, 108
IFS3 (Interrupt Flag Status 3) ........................... 102, 109
IFS4 (Interrupt Flag Status 4) ........................... 103, 110
INTCON1 (Interrupt Control 1)....................................94
INTCON2 (Interrupt Control 2)....................................96
INTTREG Interrupt Control and Status Register.......127
IPC0 (Interrupt Priority Control 0) .............................111
IPC1 (Interrupt Priority Control 1) .............................112
IPC11 (Interrupt Priority Control 11) .........................121
IPC14 (Interrupt Priority Control 14) .........................122
IPC15 (Interrupt Priority Control 15) .........................123
IPC16 (Interrupt Priority Control 16) .........................124
IPC17 (Interrupt Priority Control 17) .........................125
IPC18 (Interrupt Priority Control 18) .........................126
IPC2 (Interrupt Priority Control 2) .............................113
IPC3 (Interrupt Priority Control 3) .............................114
IPC4 (Interrupt Priority Control 4) .............................115
IPC5 (Interrupt Priority Control 5) .............................116
IPC6 (Interrupt Priority Control 6) .............................117
IPC7 (Interrupt Priority Control 7) .............................118
IPC8 (Interrupt Priority Control 8) .............................119
IPC9 (Interrupt Priority Control 9) .............................120
NVMCON (Flash Memory Control) .............................75
NVMKEY (Nonvolatile Memory Key) ..........................76
OCxCON (Output Compare x Control) .....................199
OSCCON (Oscillator Control) ...................................145
OSCTUN (FRC Oscillator Tuning) ............................149
PLLFBD (PLL Feedback Divisor)..............................148
PMD1 (Peripheral Module Disable
System Control
Register Map .............................................................. 62
T
Temperature and Voltage Specifications
AC..................................................................... 332, 372
Timer1............................................................................... 187
Timer2/3............................................................................ 189
Timing Characteristics
CLKO and I/O ........................................................... 335
Timing Diagrams
10-bit A/D Conversion (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 0, SSRC<2:0> = 000)... 361
10-bit A/D Conversion (CHPS<1:0> = 01,
SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111,
SAMC<4:0> = 00001)...................................... 361
12-bit A/D Conversion
(ASAM = 0, SSRC<2:0> = 000)........................ 359
Brown-out Situations................................................... 85
DCI AC-Link Mode.................................................... 353
2
DCI Multi -Channel, I S Modes................................. 351
ECAN I/O.................................................................. 355
External Clock........................................................... 333
I2Cx Bus Data (Master Mode) .................................. 347
I2Cx Bus Data (Slave Mode) .................................... 349
I2Cx Bus Start/Stop Bits (Master Mode)................... 347
I2Cx Bus Start/Stop Bits (Slave Mode)..................... 349
Input Capture (CAPx) ............................................... 340
OC/PWM................................................................... 341
Output Compare (OCx)............................................. 340
Reset, Watchdog Timer, Oscillator Start-up Timer
and Power-up Timer......................................... 336
SPIx Master Mode (CKE = 0) ................................... 342
SPIx Master Mode (CKE = 1) ................................... 343
SPIx Slave Mode (CKE = 0) ..................................... 344
SPIx Slave Mode (CKE = 1) ..................................... 345
Timer1, 2 and 3 External Clock ................................ 338
Timing Requirements
Control Register 1)............................................155
PMD2 (Peripheral Module Disable
Control Register 2)............................................156
PMD3 (Peripheral Module Disable
Control Register 3)............................................157
PxTCON (PWM Time Base Control).........267, 268, 269
RCON (Reset Control)................................................80
RSCON (DCI Receive Slot Control)..........................252
SPIxCON1 (SPIx Control 1)......................................203
SPIxCON2 (SPIx Control 2)......................................205
SPIxSTAT (SPIx Status and Control) .......................202
SR (CPU Status)................................................... 28, 92
T1CON (Timer1 Control)...........................................188
TCxCON (Input Capture x Control)...........................196
TSCON (DCI Transmit Slot Control) .........................252
TxCON (Type B Time Base Control) ........................192
TyCON (Type C Time Base Control) ........................193
UxMODE (UARTx Mode)..........................................216
UxSTA (UARTx Status and Control).........................218
ADC Conversion (10-bit mode)................................. 377
ADC Conversion (12-bit Mode)................................. 377
CLKO and I/O ........................................................... 335
DCI AC-Link Mode.................................................... 354
2
DCI Multi-Channel, I S Modes.................................. 352
External Clock........................................................... 333
Input Capture............................................................ 340
SPIx Master Mode (CKE = 0) ................................... 373
SPIx Module Master Mode (CKE = 1) ...................... 373
SPIx Module Slave Mode (CKE = 0) ........................ 374
SPIx Module Slave Mode (CKE = 1) ........................ 374
Timing Specifications
10-bit A/D Conversion Requirements ....................... 362
12-bit A/D Conversion Requirements ....................... 360
CAN I/O Requirements............................................. 355
I2Cx Bus Data Requirements (Master Mode)........... 348
I2Cx Bus Data Requirements (Slave Mode)............. 350
Output Compare Requirements................................ 340
PLL Clock ......................................................... 334, 372
QEI External Clock Requirements............................ 339
QEI Index Pulse Requirements ................................ 342
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out Reset
Requirements ................................................... 337
Simple OC/PWM Mode Requirements ..................... 341
SPIx Master Mode (CKE = 0) Requirements............ 342
SPIx Master Mode (CKE = 1) Requirements............ 343
SPIx Slave Mode (CKE = 0) Requirements.............. 344
SPIx Slave Mode (CKE = 1) Requirements.............. 346
Reset
Illegal Opcode....................................................... 79, 86
Trap Conflict.......................................................... 85, 86
Uninitialized W Register........................................ 79, 86
Reset Sequence..................................................................87
Resets.................................................................................79
S
Serial Peripheral Interface (SPI) .......................................201
Software Reset Instruction (SWR) ......................................85
Software Simulator (MPLAB SIM).....................................321
Software Stack Pointer, Frame Pointer
CALL Stack Frame......................................................63
Special Features of the CPU.............................................301
SPI Module
SPI1 Register Map......................................................50
Symbols Used in Opcode Descriptions.............................312
DS70292D-page 396
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
Timer1 External Clock Requirements ....................... 338
Timer2 External Clock Requirements ....................... 339
Timer3 External Clock Requirements ....................... 339
U
UART Module
UART1 Register Map............................................ 49, 50
Universal Asynchronous Receiver Transmitter (UART).... 215
Using the RCON Status Bits............................................... 86
V
Voltage Regulator (On-Chip) ............................................ 305
W
Watchdog Time-out Reset (WDTR) .................................... 85
Watchdog Timer (WDT) ............................................ 301, 306
Programming Considerations ................................... 306
WWW Address.................................................................. 401
WWW, On-Line Support ..................................................... 14
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 397
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
NOTES:
DS70292D-page 398
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
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2009 Microchip Technology Inc.
Preliminary
DS70292D-page 399
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
READER RESPONSE
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dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04,
and dsPIC33FJ128GPX02/X04 Data Sheet
DS70292D
Literature Number:
Device:
Questions:
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DS70292D-page 400
Preliminary
2009 Microchip Technology Inc.
dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
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dsPIC 33 FJ 32 GP3 02 T E / SP - XXX
a) dsPIC33FJ32GP302-E/SP:
General Purpose dsPIC33, 32 KB program
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Microchip Trademark
Architecture
Flash Memory Family
Program Memory Size (KB)
Product Group
Pin Count
Tape and Reel Flag (if applicable)
Temperature Range
Package
Pattern
Architecture:
33
=
=
16-bit Digital Signal Controller
Flash program memory, 3.3V
Flash Memory Family: FJ
Product Group:
GP2
GP3
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=
=
=
General Purpose family
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Pin Count:
02
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=
=
28-pin
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Temperature Range:
I
E
H
=
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=
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-40C to+140C (High)
Package:
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SO
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MM
PT
=
=
=
=
=
Skinny Plastic Dual In-Line - 300 mil body (SPDIP)
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Plastic Quad, No Lead Package - 8x8 mm body (QFN)
Plastic Quad, No Lead Package - 6x6x0.9 mm body (QFN-S)
Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP)
2009 Microchip Technology Inc.
Preliminary
DS70292D-page 401
Worldwide Sales and Service
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03/26/09
DS70292D-page 402
Preliminary
2009 Microchip Technology Inc.
Mouser Electronics
Authorized Distributor
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dsPIC33FJ128GP202-E/MM dsPIC33FJ128GP202-I/MM dsPIC33FJ128GP202T-I/MM dsPIC33FJ128GP206-E/PT
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dsPIC33FJ128GP802-E/MM dsPIC33FJ128GP802-I/MM dsPIC33FJ128GP802T-I/MM dsPIC33FJ32GP302-E/MM
dsPIC33FJ64GP802T-I/MM dsPIC33FJ32GP302-I/MM dsPIC33FJ64GP802-I/MM dsPIC33FJ64GP802-E/MM
dsPIC33FJ32GP302T-I/MM dsPIC33FJ64GP202T-I/MM dsPIC33FJ64GP202-I/MM dsPIC33FJ128GP310-E/PF
dsPIC33FJ64GP202-E/MM dsPIC33FJ128GP202-E/SO dsPIC33FJ128GP202-E/SP dsPIC33FJ128GP202-I/SO
dsPIC33FJ128GP202-I/SP dsPIC33FJ128GP202T-I/SO dsPIC33FJ128GP204-E/ML dsPIC33FJ128GP204-E/PT
dsPIC33FJ128GP204-I/ML dsPIC33FJ128GP204-I/PT dsPIC33FJ128GP204T-I/ML dsPIC33FJ128GP204T-I/PT
dsPIC33FJ128GP802-E/SO dsPIC33FJ128GP802-E/SP dsPIC33FJ128GP802-I/SO dsPIC33FJ128GP802-I/SP
dsPIC33FJ128GP802T-I/SO dsPIC33FJ128GP804-E/ML dsPIC33FJ128GP804-E/PT dsPIC33FJ128GP804-I/ML
dsPIC33FJ128GP804-I/PT dsPIC33FJ128GP804T-I/ML dsPIC33FJ128GP804T-I/PT dsPIC33FJ32GP302-E/SO
dsPIC33FJ32GP302-E/SP dsPIC33FJ32GP302-I/SO dsPIC33FJ32GP302-I/SP dsPIC33FJ32GP302T-I/SO
dsPIC33FJ32GP304-E/ML dsPIC33FJ32GP304-E/PT dsPIC33FJ32GP304-I/ML dsPIC33FJ32GP304-I/PT
dsPIC33FJ32GP304T-I/ML dsPIC33FJ32GP304T-I/PT dsPIC33FJ64GP202-E/SO dsPIC33FJ64GP202-E/SP
dsPIC33FJ64GP202-I/SO dsPIC33FJ64GP202-I/SP dsPIC33FJ64GP202T-I/SO dsPIC33FJ64GP204-E/ML
dsPIC33FJ64GP204-E/PT dsPIC33FJ64GP204-I/ML dsPIC33FJ64GP204-I/PT dsPIC33FJ64GP204T-I/ML
dsPIC33FJ64GP204T-I/PT dsPIC33FJ64GP802-E/SO dsPIC33FJ64GP802-E/SP dsPIC33FJ64GP802-I/SO
dsPIC33FJ64GP802-I/SP dsPIC33FJ64GP802T-I/SO dsPIC33FJ64GP804-E/ML dsPIC33FJ64GP804-E/PT
dsPIC33FJ64GP804-I/ML dsPIC33FJ64GP804-I/PT dsPIC33FJ64GP804T-I/ML dsPIC33FJ64GP804T-I/PT
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