EEC1005-H-B-IWC-TR [MICROCHIP]
Enterprise Storage Backplane Management Processor;
| 型号： | EEC1005-H-B-IWC-TR |
| 厂家： | 
MICROCHIP |
| 描述： | Enterprise Storage Backplane Management Processor |
| 文件： | 总56页 (文件大小：820K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EEC1005
Enterprise Storage Backplane Management Processor
• Complete Universal Storage Backplane Manage-
ment Processor
• Integrated NV Memory for:
- UBM FRU (Field Replaceable Unit) for every
HFC
- SFF-TA-1005 Universal Backplane Manage-
ment (UBM) over I2C
- General Purpose FRU
- Provides SFF-8654 compliant Host Facing
Connector (HFC) communication support
over I2C
- NV Configuration Memory
• Configurable Interfaces using a single analog
configuration pin
- HFC connection responds to all standard
UBM commands from the host
- Host interface (SGPIO vs UBM)
- Number of HFCs and Drive Facing Connec-
tors (DFCs)
- Integrates the UBM FRU non-volatile mem-
ory on the UBM FRU I2C Address
- Other supported features
• Monitors system PERST
- Provides SFF-8639 compliant U.2 Drive Fac-
ing Connector (DFC) Support
- One pin per DFC for PERST support
- Provides SFF-TA-1001 compliant U.3 Drive
Facing Connector (DFC) Support
• Monitors for drive insertion from IFDET and
PRSNT signals
- Support for SES over UBM
- IFDET2 support (for SFF-TA-1001)
• Package Options
• Supports I2C communication to Baseboard Man-
agement Controller
- 144 pin WFBGA RoHS Compliant package
- 84 pin WFBGA RoHS Compliant package
• Up to 8 I2C ports for UBM and BMC host inter-
faces
• SFF-8485 Support
- Implements up to 4 Hardware Accelerated
SGPIO Legacy Interfaces for SAS/SATA
backplane implementations
• Secure Boot
- EEC1005 code is authenticated by a secure
boot loader prior to loading from internal flash
- Hardware accelerated crypto blocks provide
fast secure boot
- Secure Firmware update
- Key revocation
• Supports Storage LED Management as per SFF-
8489 IBPI specifications by default
• Custom LED patterns can be configured
• Scalable Solution for up to 16 Hard Drives on a
Single Device
- SGPIO Host Interfaces support up to 16
drives (SAS/SATA drive types)
- UBM Host Interfaces support up to 12 drives
(NVMe drive types)
- Up to 6 HFCs
• Supports multiple backplanes on a single chassis
• Support for NVME Hot plug and Power Disable for
drives
2020 Microchip Technology Inc.
DS00003392B-page 1
EEC1005
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DS00003392B-page 2
2020 Microchip Technology Inc.
EEC1005
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 UBM Backplane Architecture .......................................................................................................................................................... 5
3.0 Configurations ................................................................................................................................................................................. 8
4.0 Configuration FRU ........................................................................................................................................................................ 11
5.0 Generic FRU ................................................................................................................................................................................. 19
6.0 UBM FRU ...................................................................................................................................................................................... 20
7.0 UBM Controller Commands .......................................................................................................................................................... 22
8.0 LED Specifications ........................................................................................................................................................................ 25
9.0 Multiple Chassis Configuration ..................................................................................................................................................... 26
10.0 Pin Configuration ........................................................................................................................................................................ 28
11.0 Electrical Specifications .............................................................................................................................................................. 43
12.0 Package Information ................................................................................................................................................................... 48
2020 Microchip Technology Inc.
DS00003392B-page 3
EEC1005
1.0
GENERAL DESCRIPTION
EEC1005 is a generic, easily configurable, True Universal Backplane Management (UBM) device that can be used on
hard drive backplanes to provide complete storage enclosure management and reporting to computing host systems
using industry standard communication protocols.
EEC1005 supports a variety of host interfaces to accommodate SAS/SATS/NVMe backplane. The SFF-8654 slimline
connector (Host facing Connector) can be used to route SAS signals in which case the HBA will manage SAS/SATA
drives, the same connector protocol (physically a different connector) can be used to route PCIe signals in which case
the HBA will manage NVME drives. In both cases UBM will be used as management protocol with support of SGPIO
as well on SAS Slimline (Configuration dependent).The device supports using U.2 and U.3 Drive facing Connectors.
EEC1005 also supports Multiple Backplanes on a single chassis.
EEC1005 supports 2 or 3 LED IBPI blinking patterns for up to 16 drives. Customized LED blink pattern can also be pro-
grammed through the FRU.
The EEC1005 has a secure boot loader that authenticates and decrypts the Flash boot image (UBM application) using
the AES-256, ECDSA P-256, SHA-256 cryptographic hardware accelerators. EEC1005 hardware accelerators support
128-bit and 256-bit AES encryption, ECDSA and EC_KCDSA signing algorithms, 1024-bits to 4096-bits RSA and
Elliptic asymmetric public key algorithms, and a True Random Number Generator (TRNG). Additionally, the device
offers lockable OTP storage for private keys and IDs.
EEC1005 is available in 84 pin and 144 pin WFBGA packages.
1.1
References
1. SFF-TA-1005 Universal Backplane Management Specification
2. SFF-8485 Serial General-Purpose Input/output (SGPIO) Specification
3. SFF-8448 SAS Sideband Signal Assignment
4. SFF-8489 Serial GPIO (International Blinking Pattern Interpretation)
5. Enterprise SSD Form Factor Version 1.0a
6. SFF-TA-1001 (U.3 Drive Connector) Specification
7. SFF-8639 (U.2 Drive Connector) Specification
8. SFF-9639 (U.2 Connector Pinout) Specification
9. SFF-8654 Slimline Connector Specification
10. SFF-9402 Multi-Protocol Internal Cables for SAS and/or PCIe (Slimline Connector Pinout) Specification
11. SCSI Enclosure Services -4 Specification
DS00003392B-page 4
2020 Microchip Technology Inc.
EEC1005
2.0
UBM BACKPLANE ARCHITECTURE
EEC1005 on the back plane communicates to the Host through SGPIO or I2C interface over the Host facing Connector
(Host attach configuration) or dedicated cable (Direct attach configuration). It detects hard drive being installed in the
backplane and notifies the host of the insertion/removal/failure of the drive. It also blinks Leds for each hard drive’s sta-
tus as explained in Section 8.0, "LED Specifications".
There are different types of Backplanes based on:
1. Number of drives the back plane supports
2. Type of host communication (For eg. I2C or SGPIO)
3. Type of Drive slots (For eg. U.2 or U.3)
The different configurations of the backplane that EEC1005 supports is covered in Section 3.0, "Configurations".
2.1
Direct Attach UBM Backplane
A direct attach configuration is enabled when user connects the backplane directly to mother board and the drives are
not managed by an HBA. In this case the drives are managed either by BMC or PCIe Switch/Expander for switch-based
configurations.EEC1005 can be used in Direct attach configurations using UBM as the management protocol from BMC
(BMC Emulation) or Switch/Expander.
EEC1005 based backplane architectures are capable of supporting Y-cable configurations where the PCIe lanes from
a single Host HFC will be split into 2x backplane HFC’s, this allows splitting on PCIe clocks using clock buffers as shown
in the following diagram.
2020 Microchip Technology Inc.
DS00003392B-page 5
EEC1005
FIGURE 2-1:
DIRECT ATTACH CONFIGURATION
PCIe
CPU
ChipSet
BMC
BMC
HFC(SFF‐8654)
Clock Buffer
EEC1005
IFDET,PRSNT,PERST
IFDET,PRSNT,PERST
SFF‐8639/9639 U.2
SFF‐8639/9639
U.2
2.2
Host Attach UBM Backplane
A Host attach configuration is enabled when user connects the backplane directly to SMARTROC/HBA and the drives
are managed by an HBA. EEC1005 can be used in Host attach configuration as in FIGURE 2-2: “Host Attach Configu-
ration”. Each HFC is connected to a Host through a cable to communicate with EEC1005.
EEC1005 based backplane architecture supports NVME PERST functionality by allowing the Host to directly control the
PERST signal. This allows the Host to directly control the reset behavior of NVME drive without adding any latency. The
PERST signal will be driven from HFC and then split into 2 signals to control 2 drives from a single signal.
Note:
The hardware bifurcation of the PCIe lanes is application dependent. Usually each HFC bifurcates x8 lanes
into two x4 connections.
DS00003392B-page 6
2020 Microchip Technology Inc.
EEC1005
FIGURE 2-2:
HOST ATTACH CONFIGURATION
C D F
C D F
C H F
C H F
2020 Microchip Technology Inc.
DS00003392B-page 7
EEC1005
3.0
CONFIGURATIONS
Multiple Backplane architectures are supported using EEC1005 that are configured by firmware based on an analog
value sampled at one of EEC1005 input ADC pin (Config Pin) at startup. Table 3-1, “EEC1005 Configuration Select”
provides the complete list of Configurations selectable based on the analog value on CONFIG_PIN. The analog value
can be set by a resistor divider network as in Figure 3-1, the values of the resistors are user defined.The configuration
is fixed for a Backplane and is not runtime modified. The recommendations on the resistor values are provided in
Table 3-2, “Recommended Resistor Values,” on page 9.
TABLE 3-1:
EEC1005 CONFIGURATION SELECT
DFC
SAS/
SATA
EEC1005
Configa
Pin
Count
Config
(V)
HFC HFC - HFC - DFC
Totalb SAS
PCIe Total
DFC
PCIe
ID
Pinout
4 Drive SGPIO 84
8 Drive SGPIO 84
12 Drive SPGIO 144
16 Drive SPGIO 144
01 0.1
02 0.2
03 0.3
04 0.4
05 0.5
06 0.6
07 0.7
Table 10-3, “SGPIO Con- 1
troller - 84 Pin Package”
1
1
2
2
1
1
1
0
4
4
8
0
Table 10-3, “SGPIO Con- 1
troller - 84 Pin Package”
0
0
0
2
4
4
8
0
0
0
4
8
8
Table 10-1, “SGPIO Con- 2
troller - 144 Pin Package”
12
16
4
12
16
4
Table 10-1, “SGPIO Con- 2
troller - 144 Pin Package”
4 Drive UBM
U.2
84
Table 10-4, “UBM Con-
troller - 84 Pin Package”
3
5
5
8 Drive UBM
U.2
84
Table 10-4, “UBM Con-
troller - 84 Pin Package”
8
8
8 Drive UBM
U.2 (Full Fea-
ture)
144
Table 10-2, “UBM Con-
troller - 144 Pin Package”
8
8
8 Drive UBM
U.3 (Minimum
Feature)
84
08 0.8
09 0.9
0A 1.0
0B 1.1
0D 1.3
Table 10-4, “UBM Con-
troller - 84 Pin Package”
4
4
6
6
5
4
4
0
0
1
4
4
6
6
4
8
8
8
0
0
8
8
8 Drive UBM
U.3 (Full Fea-
ture)
144
144
144
144
Table 10-2, “UBM Con-
troller - 144 Pin Package”
8
8
12 Drive UBM
U.2 PCIe Only
(Full Featured)
Table 10-2, “UBM Con-
troller - 144 Pin Package”
12
12
8
12
12
8
12 Drive UBM
U.3 PCIe Only
(Full Featured)
Table 10-2, “UBM Con-
troller - 144 Pin Package”
8 Drive
Table 10-5,
UBM+SGPIO
U.2
“UBM_SGPIO Controller
- 144 Pin Package”
a. Configurations not mentioned in the above table are not supported by EEC1005.
b. HFC Total is the number of host facing connectors required for a particular configuration.
DS00003392B-page 8
2020 Microchip Technology Inc.
EEC1005
FIGURE 3-1:
VOLTAGE DIVIDER AT ADC INPUT
VCC = 3.3V
R1 = 10K
To ADC input
(CFG Pin)
R2
C = 0.1uf
R3
TABLE 3-2:
RECOMMENDED RESISTOR VALUES
EEC1005 Config
Config (V)
Pinout
R2 (in Ohms)
R3(in Ohms)
4 Drive SGPIO
0.1
0.2
0.3
0.4
0.5
0.6
Table 10-3, “SGPIO
Controller - 84 Pin
Package”
301
11.5
8 Drive SGPIO
12 Drive SPGIO
16 Drive SPGIO
4 Drive UBM U.2
8 Drive UBM U.2
Table 10-3, “SGPIO
Controller - 84 Pin
Package”
634
11
Table 10-1, “SGPIO
Controller - 144 Pin
Package”
1000
1370
1780
2210
2670
0
Table 10-1, “SGPIO
Controller - 144 Pin
Package”
9.31
5.76
12.1
40.2
Table 10-4, “UBM
Controller - 84 Pin
Package”
Table 10-4, “UBM
Controller - 84 Pin
Package”
8 Drive UBM U.2 (Full 0.7
Feature)
Table 10-2, “UBM
Controller - 144 Pin
Package”
2020 Microchip Technology Inc.
DS00003392B-page 9
EEC1005
TABLE 3-2:
RECOMMENDED RESISTOR VALUES (CONTINUED)
EEC1005 Config
Config (V)
Pinout
R2 (in Ohms)
3160
R3(in Ohms)
8 Drive UBM U.3
(Minimum Feature)
0.8
Table 10-4, “UBM
Controller - 84 Pin
Package”
40.2
8 Drive UBM U.3 (Full 0.9
Feature)
Table 10-2, “UBM
Controller - 144 Pin
Package”
3740
4320
4990
5490
10
12 Drive UBM U.2
PCIe Only (Full Fea-
tured)
1.0
1.1
Table 10-2, “UBM
Controller - 144 Pin
Package”
28
12 Drive UBM U.3
PCIe Only (Full Fea-
tured)
Table 10-2, “UBM
Controller - 144 Pin
Package”
10
8 Drive UBM+SGPIO 1.3
U.2
Table 10-5,
1000
“UBM_SGPIO Con-
troller - 144 Pin Pack-
age”
Note 1: The resistor values suggested are based on the standard value resistors available @1% tolerance.
2: It is highly recommended to use 1% tolerant resistors at ADC input.
3: The ADC input capacitor should be 0.1uF.
4: The resistor R1 should be fixed at 10K.
5: The Config values not mentioned in the above table is not supported by EEC1005.
DS00003392B-page 10
2020 Microchip Technology Inc.
EEC1005
4.0
CONFIGURATION FRU
EEC1005 supports a 256-byte FRU (Field Replaceable Unit) that is used to initialize/input the parameters which are
client specific. These parameters are read on power up as well as run time to initialize the firmware accordingly. This
256-byte FRU is accessible over BMC I2C segment, if used in an architecture where BMC exists.
TABLE 4-1:
Address
CONFIGURATION FRU TABLE
Group
Global
Field Name
Pattern
LED Name
Parameters
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
ACTIVITY/2WIRE_RESET OPTION
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
Global
HFC0
HFC0
HFC0
HFC0
HFC0
IBPI PATTERN 2/3 LED
Backplane HFC Count
Backplane DFC Count
Backplane Physical Location
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CHECKSUM
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
SILICON VENDOR ID VENDOR SPECIFIC
0
0x1A
HFC0
SILICON VENDOR ID VENDOR SPECIFIC
1
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
HFC0
HFC0
HFC0
HFC0
HFC0
HFC0
HFC0
HFC0
HFC0
HFC0
HFC0
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
2020 Microchip Technology Inc.
DS00003392B-page 11
EEC1005
TABLE 4-1:
CONFIGURATION FRU TABLE (CONTINUED)
Group Field Name
HFC0
HFC0
Address
Pattern
LED Name
Parameters
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
RSVD
RSVD
HFC0
HFC0
HFC0
HFC0
HFC0
HFC1
HFC1
HFC1
HFC1
HFC1
RSVD
RSVD
RSVD
RSVD
CHECKSUM
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
SILICON VENDOR ID VENDOR SPECIFIC
0
0x32
HFC1
SILICON VENDOR ID VENDOR SPECIFIC
1
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
0x48
0x49
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC1
HFC2
HFC2
HFC2
HFC2
HFC2
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CHECKSUM
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
SILICON VENDOR ID VENDOR SPECIFIC
0
0x4A
HFC2
SILICON VENDOR ID VENDOR SPECIFIC
1
0x4B
0x4C
0x4D
0x4E
HFC2
HFC2
HFC2
HFC2
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
DS00003392B-page 12
2020 Microchip Technology Inc.
EEC1005
TABLE 4-1:
CONFIGURATION FRU TABLE (CONTINUED)
Group Field Name
HFC2
Address
Pattern
LED Name
Parameters
0x4F
0x50
0x51
0x52
0x53
0x54
0x55
0x56
0x57
0x58
0x59
0x5A
0x5B
0x5C
0x5D
0x5E
0x5F
0x60
0x61
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CHECKSUM
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC2
HFC3
HFC3
HFC3
HFC3
HFC3
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
SILICON VENDOR ID VENDOR SPECIFIC
0
0x62
HFC3
SILICON VENDOR ID VENDOR SPECIFIC
1
0x63
0x64
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
0x74
0x75
0x76
0x77
0x78
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC3
HFC4
HFC4
HFC4
HFC4
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CHECKSUM
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
2020 Microchip Technology Inc.
DS00003392B-page 13
EEC1005
TABLE 4-1:
Address
CONFIGURATION FRU TABLE (CONTINUED)
Group
HFC4
Field Name
Pattern
LED Name
Parameters
0x79
SILICON VENDOR ID VENDOR SPECIFIC
0
0x7A
HFC4
SILICON VENDOR ID VENDOR SPECIFIC
1
0x7B
0x7C
0x7D
0x7E
0x7F
0x80
0x81
0x82
0x83
0x84
0x85
0x86
0x87
0x88
0x89
0x8A
0x8B
0x8C
0x8D
0x8E
0x8F
0x90
0x91
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC4
HFC5
HFC5
HFC5
HFC5
HFC5
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CHECKSUM
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
SILICON VENDOR ID VENDOR SPECIFIC
0
0x92
HFC5
SILICON VENDOR ID VENDOR SPECIFIC
1
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
0x9C
0x9D
0x9E
0x9F
0xA0
0xA1
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC5
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
DS00003392B-page 14
2020 Microchip Technology Inc.
EEC1005
TABLE 4-1:
CONFIGURATION FRU TABLE (CONTINUED)
Group Field Name
HFC5
Address
Pattern
LED Name
Parameters
0xA2
0xA3
0xA4
0xA5
0xA6
0xA7
0xA8
0xA9
RSVD
HFC5
HFC5
HFC6
HFC6
HFC6
HFC6
HFC6
RSVD
CHECKSUM
UBM CONTROLLER DEVICE CODE MSB
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE
UBM CONTROLLER DEVICE CODE LSB
SILICON VENDOR ID VENDOR SPECIFIC
0
0xAA
HFC6
SILICON VENDOR ID VENDOR SPECIFIC
1
0xAB
0xAC
0xAD
0xAE
0xAF
0xB0
0xB1
0xB2
0xB3
0xB4
0xB5
0xB6
0xB7
0xB8
0xB9
0xBA
0xBB
0xBC
0xBD
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC6
HFC IDENTITY
CPRSNT# or CHANGE_DETECT#
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
CHECKSUM
LED PAT- NOT_PRES_LED_ACT_BLINKP_REP
TERN
NOT_PRES
NOT_PRES
NOT_PRES
NOT_PRES
NOT_PRES
NOT_PRES
LED_ACT
LED_ACT
BLINK-
P_REP
0xBE
0xBF
0xC0
0xC1
0xC2
0xC3
0xC4
0xC5
LED PAT- NOT_PRES_LED_ACT_PAT_PERIOD
TERN
PAT_PE-
RIOD
LED PAT- NOT_PRES_LED_STAorLOC_BLINK-
LED_STAor-
LOC
BLINK-
P_REP
TERN
LED PAT- NOT_PRES_LED_STAorLOC_PAT_PE-
TERN RIOD
P_REP
LED_STAor-
LOC
PAT_PE-
RIOD
LED PAT- NOT_PRES_LED_FAIL_BLINKP_REP
TERN
LED_FAIL
BLINK-
P_REP
LED PAT- NOT_PRES_LED_FAIL_PAT_PERIOD
TERN
LED_FAIL
PAT_PE-
RIOD
LED PAT- PRES_NO_ACT_LED_ACT_BLINKP_REP PRES_NO_AC LED_ACT
TERN
LED PAT- PRES_NO_ACT_LED_ACT_PAT_PERIOD PRES_NO_AC LED_ACT
TERN
LED PAT- PRES_NO_ACT_LED_STAorLOC_BLINK- PRES_NO_AC LED_STAor-
TERN P_REP LOC
BLINK-
P_REP
T
PAT_PE-
RIOD
T
BLINK-
P_REP
T
2020 Microchip Technology Inc.
DS00003392B-page 15
EEC1005
TABLE 4-1:
CONFIGURATION FRU TABLE (CONTINUED)
Group Field Name
LED PAT- PRES_NO_ACT_LED_STAor-
TERN LOC_PAT_PERIOD
LED PAT- PRES_NO_ACT_LED_FAIL_BLINKP_REP PRES_NO_AC LED_FAIL
Address
Pattern
PRES_NO_AC LED_STAor-
LOC
LED Name
Parameters
0xC6
0xC7
0xC8
0xC9
0xCA
0xCB
0xCC
0xCD
0xCE
0xCF
0xD0
0xD1
0xD2
0xD3
0xD4
0xD5
0xD6
0xD7
0xD8
0xD9
0xDA
0xDB
0xDC
0xDD
0xDE
PAT_PE-
RIOD
T
BLINK-
P_REP
TERN
T
LED PAT- PRES_NO_ACT_LED_FAIL_PAT_PE-
TERN
PRES_NO_AC LED_FAIL
T
PAT_PE-
RIOD
RIOD
LED PAT- PRES_ACT_LED_ACT_BLINKP_REP
TERN
PRES_ACT
PRES_ACT
PRES_ACT
PRES_ACT
PRES_ACT
PRES_ACT
LOCATE
LED_ACT
BLINK-
P_REP
LED PAT- PRES_ACT_LED_ACT_PAT_PERIOD
TERN
LED_ACT
PAT_PE-
RIOD
LED PAT- PRES_ACT_LED_STAorLOC_BLINK-
LED_STAor-
LOC
BLINK-
P_REP
TERN
LED PAT- PRES_ACT_LED_STAorLOC_PAT_PE-
TERN RIOD
P_REP
LED_STAor-
LOC
PAT_PE-
RIOD
LED PAT- PRES_ACT_LED_FAIL_BLINKP_REP
TERN
LED_FAIL
LED_FAIL
LED_ACT
LED_ACT
BLINK-
P_REP
LED PAT- PRES_ACT_LED_FAIL_PAT_PERIOD
TERN
PAT_PE-
RIOD
LED PAT- LOCATE_LED_ACT_BLINKP_REP
TERN
BLINK-
P_REP
LED PAT- LOCATE_LED_ACT_PAT_PERIOD
TERN
LOCATE
PAT_PE-
RIOD
LED PAT- LOCATE_LED_STAorLOC_BLINKP_REP LOCATE
TERN
LED_STAor-
LOC
BLINK-
P_REP
LED PAT- LOCATE_LED_STAorLOC_PAT_PERIOD LOCATE
TERN
LED_STAor-
LOC
PAT_PE-
RIOD
LED PAT- LOCATE_LED_FAIL_BLINKP_REP
TERN
LOCATE
LOCATE
FAIL
LED_FAIL
LED_FAIL
LED_ACT
LED_ACT
BLINK-
P_REP
LED PAT- LOCATE_LED_FAIL_PAT_PERIOD
TERN
PAT_PE-
RIOD
LED PAT- FAIL_LED_ACT_BLINKP_REP
TERN
BLINK-
P_REP
LED PAT- FAIL_LED_ACT_PAT_PERIOD
TERN
FAIL
PAT_PE-
RIOD
LED PAT- FAIL_LED_STAorLOC_BLINKP_REP
TERN
FAIL
LED_STAor-
LOC
BLINK-
P_REP
LED PAT- FAIL_LED_STAorLOC_PAT_PERIOD
TERN
FAIL
LED_STAor-
LOC
PAT_PE-
RIOD
LED PAT- FAIL_LED_FAIL_BLINKP_REP
TERN
FAIL
LED_FAIL
LED_FAIL
LED_ACT
LED_ACT
BLINK-
P_REP
LED PAT- FAIL_LED_FAIL_PAT_PERIOD
TERN
FAIL
PAT_PE-
RIOD
LED PAT- REBUILD_LED_ACT_BLINKP_REP
TERN
REBUILD
REBUILD
BLINK-
P_REP
LED PAT- REBUILD_LED_ACT_PAT_PERIOD
TERN
PAT_PE-
RIOD
LED PAT- REBUILD_LED_STAorLOC_BLINKP_REP REBUILD
TERN
LED_STAor-
LOC
BLINK-
P_REP
LED PAT- REBUILD_LED_STAorLOC_PAT_PERIOD REBUILD
TERN
LED_STAor-
LOC
PAT_PE-
RIOD
DS00003392B-page 16
2020 Microchip Technology Inc.
EEC1005
TABLE 4-1:
Address
CONFIGURATION FRU TABLE (CONTINUED)
Group Field Name
Pattern
LED Name
Parameters
0xDF
0xE0
0xE1
0xE2
0xE3
0xE4
0xE5
0xE6
0xE7
0xE8
0xE9
0xEA
0xEB
0xEC
0xED
0xEE
0xEF
0xF0
0xF1
0xF2
0xF3
0xF4
0xF5
0xF6
0xF7
LED PAT- REBUILD_LED_FAIL_BLINKP_REP
TERN
REBUILD
LED_FAIL
LED_FAIL
LED_ACT
LED_ACT
BLINK-
P_REP
LED PAT- REBUILD_LED_FAIL_PAT_PERIOD
TERN
REBUILD
PFA
PAT_PE-
RIOD
LED PAT- PFA_LED_ACT_BLINKP_REP
TERN
BLINK-
P_REP
LED PAT- PFA_LED_ACT_PAT_PERIOD
TERN
PFA
PAT_PE-
RIOD
LED PAT- PFA_LED_STAorLOC_BLINKP_REP
TERN
PFA
LED_STAor-
LOC
BLINK-
P_REP
LED PAT- PFA_LED_STAorLOC_PAT_PERIOD
TERN
PFA
LED_STAor-
LOC
PAT_PE-
RIOD
LED PAT- PFA_LED_FAIL_BLINKP_REP
TERN
PFA
LED_FAIL
BLINK-
P_REP
LED PAT- PFA_LED_FAIL_PAT_PERIOD
TERN
PFA
LED_FAIL
PAT_PE-
RIOD
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
2020 Microchip Technology Inc.
DS00003392B-page 17
EEC1005
TABLE 4-1:
Address
CONFIGURATION FRU TABLE (CONTINUED)
Group Field Name
Pattern
LED Name
Parameters
0xF8
0xF9
0xFA
0xFB
0xFC
0xFD
0xFE
0xFF
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- RSVD
TERN
LED PAT- CHECKSUM
TERN
DS00003392B-page 18
2020 Microchip Technology Inc.
EEC1005
5.0
GENERIC FRU
EEC1005 has a Generic FRU space which customer can use as non volatile storage. 256 bytes are allocated for this
Customer defined Generic FRU. This memory emulates AT24C02 256 byte I2C EEPROM.Read and write of data to this
FRU space can be done by host over the same physical I2C interface connected to BMC/Host at I2C slave address
0x54 (7-bit address).
2020 Microchip Technology Inc.
DS00003392B-page 19
EEC1005
6.0
UBM FRU
The SFF-TA-1005 (UBM) Specification calls out for an external Field Replaceable Unit (FRU) per every UBM Controller.
EEC1005 incorporates a UBM FRU for every UBM Controller as per the spec requirement within EEC1005 Memory
space. This saves board space and cost.
The UBM FRU on backplane is a 256 byte read-only NVRAM with IPMI FRU formatted content and is responsible for
reporting static backplane information.
FIGURE 6-1:
UBM FRU FORMAT
DS00003392B-page 20
2020 Microchip Technology Inc.
EEC1005
FIGURE 6-2:
UBM FRU
UBM FRU
Drive0
UBM I2C
HFC 0
UBM CONTROLLER 1
EEC1005
UBM FRU
UBM I2C
HFC 1
Drive4
UBM CONTROLLER 2
The UBM FRU is addressed as specified by SFF-TA-1005, over Slave Address (0xAE).
2020 Microchip Technology Inc.
DS00003392B-page 21
EEC1005
7.0
UBM CONTROLLER COMMANDS
The UBM Controller manages the Host facing Connector sideband I/O signaling, the Drive facing connector I/O signal-
ing and the LED states for the DFC. It provides backplane implementation features and options for the initialization of
the devices. These features are selected for the device through the CONFIG_PIN (Section 10.2, "Pin List") as explained
in Section 3.0, "Configurations".
The below are the supported UBM controller command set for EEC1005. There are variables in UBM that are client
specific for example “Vendor Specific” bytes of Silicon Identity and Revision Command. EEC 1005 allows clients to
initialize those variables from FRU, the UBM registers are initialized to these values on power up.
7.1
Silicon Identity and Revision (0x02)
Byte/Bit
7
6
5
4
3
2
1
0
0
1
2
3
UBM Spec Major Version = 1
UBM Spec Minor Version = 3
PCIE Vendor ID (LSB) = 0x54
PCIE Vendor ID (MSB) = 0x00
RESERVED = 0x00
4
5
6
7
8
9
UMB Controller Device Code (LSB) = Configuration FRU
UBM Controller Device Code = Configuration FRU
UBM Controller Device Code (MSB) = Configuration FRU
RESERVED = 0x0000
10
11
12
13
UBM Controller Image Version Minor = Backplane FW Minor Version
UBM Controller Image Version Major = Backplane FW Major Version
Vendor Specific = Configuration FRU
7.2
Programming Update Mode Capabilities (0x03)
Byte/Bit
7
6
5
4
3
2
1
0
0
RSVD
Update Mode = 0x01
Update Mode: The update mode will be set to 0x01 to indicate that update is supported while the device remains online.
In order to support the non-destructive status of NVME drives while the update is being performed the GPIOs status will
remain consistent across a firmware reset.
7.3
Host Facing Connector Info (0x30)
Byte/Bit
7
6
5
4
3
2
1
0
0
Port Type
= 1 (PCIe)
= 0 (SAS)
RSVD = 0x0
Host Facing Connector Identity = Configuration FRU
Host Facing Connector ID will start from 0 and will report SAS HFC first followed by NVME HFC
PORT TYPE: HFCs that are SAS/SATA shall report Port Type = 0. HFCs that are PCIe shall report Port Type = 1.
DS00003392B-page 22
2020 Microchip Technology Inc.
EEC1005
7.4
Backplane Info (0x31)
Byte/Bit
7
6
5
4
3
2
1
0
0
Backplane Type
RSVD = 0
Backplane Number = Configuration FRU
The Backplane Type will represent the Configuration selected from Config Pin.The Backplane Number will be read from
Configuration FRU or configured based on input voltage on CONFIG_BPNUM_PIN.
7.5
Starting Slot (0x32)
Byte/Bit
7
6
5
4
3
2
1
0
0
Starting Slot = 0x00
Starting Slot is fixed to 0x0.
7.6
Capabilities (0x33)
Byte/Bit
7
6
5
4
3
2
1
0
0
DFC
Change
Count = 1
Change
Detect Int
= 1
2-Wire Reset = 02h
Dual Port
= 0b
PCIe
Reset
Control
=0
Slot Power
Control = 1 ing = Configu-
ration FRU
Clock Rout-
1
RSVD = 00h
DFC
PERST#
Manage-
ment
IFDET2 = IFDET1 = 1
0 or 1* P4
PRSNT = 1
P10
Override
support =1
CLOCK ROUTING: Set to 0 for SAS HFCS. Set to 1 for PCIe HFCs.
SLOT POWER CONTROL: Set to 0. DFCs with SAS drives will support Slot Power Control if a backplane configuration
supports Power Disable Pin
PCIE RESET CONTROL: Set to 0.
DUAL PORT: Set to 0. Single ported only.
2WIRE RESET: Set to 0. 2-wire reset is not supported.
CHANGE DETECT: Set to 1. One Change Detect interrupt supported per backplane HFC.
DFC CHANGE COUNT : Set to 1. Indicates if a change count is maintained per an individual DFC Status and Control
Command Descriptor.
PRSNT: Set to 1. Indicates that the DFCs connected to this HFC support the PRSNT signal.
IFDET1: Set to 1. Indicates that the DFCs connected to this HFC support the IFDET1 signal.
*IFDET2: This bit will be set to 1 if it is a U.3 backplane and to 0 if it is a U.2 backplane
DFC PERST# MANAGEMENT OVERRIDE : Set to 1, Override supported
7.7
Features (0x34)
Byte/Bit
7
6
5
4
3
2
1
0
0
DFC PERST# Man-
agement Override
Operational
State Mask =
1b
Drive
Type
Change
Mask =
1b
PCIE
Reset
Change
Mask =
1b
CPRSTN = Write Check- Read Check-
Configura-
tion FRU
sum = 1b
sum = 1b
1
RSVD = 0x00
READ CHECKSUM: Set to 1.
2020 Microchip Technology Inc.
DS00003392B-page 23
EEC1005
WRITE CHECKSUM CHECKING: Set to 1.
CPRSNT LEGACY MODE: Set to 0.
PCIE RESET CHANGE MASK: Set to 1.
DRIVE TYPE INSTALLED CHANGE COUNT MASK: Set to 1
OPERATIONAL STATE CHANGE COUNT MASK: Set to 1.
DFC PERST# MANAGEMENT OVERRIDE : Indicates the DFC_PERST# behaviour when a drive has been installed
0 = No override
1 = DFC PERST# Managed upon install
2 = DFC PERST# Automatically released upon install
3 = Reserved
DS00003392B-page 24
2020 Microchip Technology Inc.
EEC1005
8.0
LED SPECIFICATIONS
EEC1005 supports three LED’s per every DFC ( Activity, Fail, Locate ).The Drive Activity LED can be controlled directly
from Host or from EEC1005 which is selected using Configuration FRU (Configuration address 0x01), the Fail (Amber)
and Locate (Green) are supported as a bi color LED on backplane and controlled by EEC1005.
In order to prevent any current leakage, the LED pins will remain tri-stated till the backplane is initialized and the default
state for all the LED’s will be off on power up after initialization is complete.
The table below summarizes the LED patterns as per International Blinking Pattern Interpretation defined in SFF-8489.
TABLE 8-1:
IBPI LED BLINK PATTERN
Locate/Identify LED (Green)
Drive State
Fail LED (Amber)
Drive Not Present
Drive Present, No Activity
Drive Present, Activity
Locate (Identify)
Fail
OFF
OFF
OFF
OFF
OFF
ON
ON
ON
4Hz
OFF
Rebuild
OFF
1Hz
1Hz
Rebuild Abort
OFF
Predicted Failure (PFA)
Hot spare
OFF
2 Blinks at 4Hz & Pause for 0.5sec
Not Supported
Not Supported
Not Supported
Not Supported
In A Critical Array
In a Failed Array
Not Supported
Not Supported
If a Host sets multiple drive states at the same time, then backplane controller will follow a priority as defined in the
below. Configurable LED blink frequency/duty cycle are also supported via FRU in order to support blink patterns that
are not IBPI complaint.
TABLE 8-2:
LED PRIORITY
Drive State
Priority
Locate (Identify)
Fault
1
2
3
4
5
6
Predicted Failure
Rebuild Abort
Drive Present, Activity
Drive Present, No Activity
2020 Microchip Technology Inc.
DS00003392B-page 25
EEC1005
9.0
MULTIPLE CHASSIS CONFIGURATION
When multiple Backplanes are used in a single system, the Backplane Number in the Backplane Info (0x31) UBM reg-
ister is used by host to determine the physical backplane location of a given backplane.
The Backplane Number is populates with the values of Table 9-1, “ Backplane number vs Resistor select” as a function
of the voltage on pin CONFIG_BPNUM_PIN. This voltage can be provided by a fixed voltage divider on the backplane
or by mating with the backplane power cable. Alternatively, the Configuration FRU can be used to overwrite the Back-
plane Number value. This is done by writing a value different than 0xFF to offset 0x04 of the Configuration FRU, Back-
plane Physical Location.
FIGURE 9-1:
MULTIPLE CHASSIS CONFIGURATION
CPU
PCIe
PCIe
HBA1
HBA2
UBM I2C
UBM I2C
Rear x4
Backplane 1
Front x8
Backplane 1
BMC I2C
BMC I2C
BMC
DS00003392B-page 26
2020 Microchip Technology Inc.
EEC1005
FIGURE 9-2:
BACKPLANE NUMBER SELECT ADC INPUT
VCC = 3.3V
R1 = 10K
To ADC input
(Config_BPNUM_Pin)
C = 0.1uf
R2
TABLE 9-1:
BACKPLANE NUMBER VS RESISTOR SELECT
Pull Down Resistor (R2)
Backplane Number
Voltage at the Config_BPNUM_Pin
in Ohms
0
0
0.000
0.148
0.250
0.354
0.503
0.702
0.874
1.055
1.185
1.336
1.487
1.650
1.800
1.980
2.121
2.269
1
470
2
820
3
1200
1800
2700
3600
4700
5600
6800
8200
10000
12000
15000
18000
22000
4
5
6
7
8
9
10
11
12
13
14
15
Note 1: The resistor values suggested are based on the standard value resistors available @1% tolerance
2: It is highly recommended to use 1% tolerant resistors at ADC input
3: The ADC input capacitor should be 0.1uF
4: The resistor R1 should be fixed at 10K
5: The Backplane Number values not mentioned in the above table is not supported by EEC1005
2020 Microchip Technology Inc.
DS00003392B-page 27
EEC1005
10.0 PIN CONFIGURATION
10.1 Description
Section 10.0 “Pin Configuration” consists of the Pin Lists and Package Drawings.
10.2 Pin List
TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE
Ball Number
Function
A1
A2
DFC_00_PWR_DISABLE
BMC_I2C_SDA
A3
BMC_I2C_SCL
A4
DFC_14_IFDET_N
DFC_13_IFDET_N
RSVD
A5
A6
A7
NC
A8
SGPIO_03_DATAOUT
DFC_07_IFDET_N
DFC_13_ACTIVITY_N
DFC_08_PWR_DISABLE
DFC_02_LED_STA_N
DFC_06_ACTIVITY_N
SGPIO_00_CLOCK
DFC_05_LED_STA_N
DFC_01_IFDET_N
DFC_12_IFDET_N
NC
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
B7
DFC_09_PRSNT_N
DFC_03_PWR_DISABLE
DFC_05_PWR_DISABLE
DFC_04_PWR_DISABLE
DFC_14_ACTIVITY_N
SGPIO_03_CTRL_TYPE
DFC_01_PWR_DISABLE
SGPIO_03_CLOCK
SGPIO_01_CLOCK
SGPIO_02_CLOCK
DFC_13_PRSNT_N
RSVD
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
DFC_10_PRSNT_N
DFC_07_LED_STA_N
DFC_02_ACTIVITY_N
DFC_10_ACTIVITY_N
DFC_07_PWR_DISABLE
DFC_03_ACTIVITY_N
VCC
DS00003392B-page 28
2020 Microchip Technology Inc.
EEC1005
TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
E1
DFC_07_ACTIVITY_N
DFC_02_IFDET_N
nRESET_IN
SGPIO_02_LOAD
DFC_12_PWR_DISABLE
NC
DFC_11_PWR_DISABLE
DFC_08_IFDET_N
DFC_11_ACTIVITY_N
DFC_14_PWR_DISABLE
DFC_13_PWR_DISABLE
BMC_2WIRE_RESET
DFC_15_ACTIVITY_N
DFC_02_PWR_DISABLE
SGPIO_00_DATAOUT
VCC
E2
E3
E4
E5
E6
VSS
E7
VCC
E8
VSS
E9
SGPIO_01_DATAOUT
DFC_09_ACTIVITY_N
DFC_00_LED_ACT_N
SGPIO_02_CTRL_TYPE
VR_CAP
E10
E11
E12
F1
F2
DFC_06_PWR_DISABLE
SGPIO_03_DATAIN
SGPIO_01_LOAD
VCC
F3
F4
F5
F6
DFC_06_IFDET_N
DFC_04_LED_STA_N
VSS
F7
F8
F9
DFC_07_PRSNT_N
nSTRAP_IN
F10
F11
F12
G1
G2
G3
G4
G5
G6
G7
G8
DFC_08_ACTIVITY_N
DFC_06_LED_STA_N
DFC_15_PWR_DISABLE
VREF_ADC
SGPIO_03_LOAD
DFC_12_ACTIVITY_N
VSS
VSS
DFC_04_ACTIVITY_N
VCC
2020 Microchip Technology Inc.
DS00003392B-page 29
EEC1005
TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
HEARTBEAT_PIN
DFC_08_LED_STA_N
DFC_03_LED_STA_N
DFC_05_ACTIVITY_N
CONFIG_PIN
DFC_05_IFDET_N
DFC_09_PWR_DISABLE
DFC_01_LED_ACT_N
DFC_10_PWR_DISABLE
VCC
VCC
DFC_00_ACTIVITY_N
DFC_09_LED_STA_N
DFC_10_LED_STA_N
DFC_11_LED_STA_N
DFC_11_LED_ACT_N
DFC_04_IFDET_N
DFC_00_IFDET_N
DFC_03_IFDET_N
DFC_10_IFDET_N
DFC_03_LED_ACT_N
DFC_15_LED_ACT_N
DFC_12_LED_ACT_N
SGPIO_02_DATAIN
NC
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
K1
DFC_12_PRSNT_N
DFC_11_PRSNT_N
SGPIO_00_CTRL_TYPE
CONFIG_BPNUM_PIN
DFC_00_PRSNT_N
DFC_15_PRSNT_N
DFC_02_LED_ACT_N
DFC_13_LED_ACT_N
DFC_12_LED_STA_N
DFC_06_LED_ACT_N
DFC_07_LED_ACT_N
DFC_09_LED_ACT_N
DFC_08_LED_ACT_N
SGPIO_00_DATAIN
DFC_15_IFDET_N
DFC_01_PRSNT_N
SGPIO_00_LOAD
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
L2
L3
DFC_14_PRSNT_N
DS00003392B-page 30
2020 Microchip Technology Inc.
EEC1005
TABLE 10-1: SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
L4
L5
SGPIO_01_DATAIN
DFC_14_LED_ACT_N
DFC_14_LED_STA_N
DFC_05_LED_ACT_N
DFC_04_PRSNT_N
DFC_01_LED_STA_N
SGPIO_01_CTRL_TYPE
DFC_05_PRSNT_N
DFC_10_LED_ACT_N
DFC_09_IFDET_N
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
DFC_02_PRSNT_N
DFC_11_IFDET_N
DFC_03_PRSNT_N
DFC_08_PRSNT_N
DFC_04_LED_ACT_N
DFC_13_LED_STA_N
DFC_00_LED_STA_N
DFC_15_LED_STA_N
DFC_01_ACTIVITY_N
SGPIO_02_DATAOUT
DFC_06_PRSNT_N
TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE
Ball Number
Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
B1
B2
B3
B4
B5
B6
DFC_02_IFDET2_N
BMC_I2C_SDA
BMC_I2C_SCL
HFC_04_SCL
HFC_04_SDA
RSVD
HFC_01_SDA
DFC_06_ACTIVITY_N
DFC_07_IFDET_N
DFC_10_IFDET2_N
DFC_09_IFDET2_N
DFC_02_LED_STA_N
DFC_01_IFDET2_N
HFC_00_SCL
DFC_05_LED_STA_N
DFC_01_IFDET_N
HFC_02_SCL
HFC_02_SDA
2020 Microchip Technology Inc.
DS00003392B-page 31
EEC1005
TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
B7
B8
DFC_09_PRSNT_N
DFC_04_PERST_N
DFC_06_IFDET2_N
DFC_05_IFDET2_N
DFC_11_IFDET2_N
DFC_11_PWR_DISABLE
DFC_03_IFDET2_N
DFC_09_PERST_N
DFC_05_PERST_N
DFC_08_PERST_N
DFC_10_PERST_N
RSVD
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
DFC_10_PRSNT_N
DFC_07_LED_STA_N
DFC_02_ACTIVITY_N
DFC_10_ACTIVITY_N
DFC_08_IFDET2_N
DFC_08_PWR_DISABLE
VCC
C8
C9
C10
C11
C12
D1
D2
DFC_00_PERST_N
DFC_02_IFDET_N
nRESET_IN
D3
D4
D5
DFC_00_IFDET2_N
HFC_03_CHNG_DET_N
HFC_01_SCL
D6
D7
D8
HFC_01_CHNG_DET_N
DFC_08_IFDET_N
DFC_11_ACTIVITY_N
HFC_05_2WIRE_RESET
HFC_04_2WIRE_RESET
BMC_2WIRE_RESET
DFC_11_PERST_N
DFC_04_IFDET2_N
DFC_03_ACTIVITY_N
VCC
D9
D10
D11
D12
E1
E2
E3
E4
E5
E6
VSS
E7
VCC
E8
VSS
E9
DFC_02_PERST_N
DFC_09_ACTIVITY_N
DFC_00_LED_ACT_N
DFC_10_PWR_DISABLE
VR_CAP
E10
E11
E12
F1
DS00003392B-page 32
2020 Microchip Technology Inc.
EEC1005
TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
F2
F3
DFC_07_IFDET2_N
DFC_07_ACTIVITY_N
DFC_03_PERST_N
VCC
F4
F5
F6
DFC_06_IFDET_N
DFC_04_LED_STA_N
VSS
F7
F8
F9
DFC_07_PRSNT_N
nSTRAP_IN
F10
F11
F12
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
DFC_01_PERST_N
DFC_06_LED_STA_N
HFC_05_CHNG_DET_N
VREF_ADC
DFC_08_ACTIVITY_N
DFC_09_PWR_DISABLE
VSS
VSS
DFC_04_ACTIVITY_N
VCC
HEARTBEAT_PIN
DFC_08_LED_STA_N
DFC_03_LED_STA_N
DFC_05_ACTIVITY_N
CONFIG_PIN
DFC_05_IFDET_N
HFC_00_2WIRE_RESET
DFC_01_LED_ACT_N
HFC_01_2WIRE_RESET
VCC
VCC
DFC_00_ACTIVITY_N
DFC_09_LED_STA_N
DFC_10_LED_STA_N
DFC_11_LED_STA_N
DFC_11_LED_ACT_N
DFC_04_IFDET_N
DFC_00_IFDET_N
DFC_03_IFDET_N
DFC_10_IFDET_N
DFC_03_LED_ACT_N
DFC_01_PWR_DISABLE
HFC_02_2WIRE_RESET
DFC_06_PWR_DISABLE
J2
J3
J4
J5
J6
J7
J8
2020 Microchip Technology Inc.
DS00003392B-page 33
EEC1005
TABLE 10-2: UBM CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
J9
J10
J11
J12
K1
HFC_03_SCL
HFC_05_SCL
DFC_11_PRSNT_N
HFC_03_SDA
CONFIG_BPNUM_PIN
DFC_00_PRSNT_N
DFC_07_PERST_N
DFC_02_LED_ACT_N
HFC_03_2WIRE_RESET
DFC_02_PWR_DISABLE
DFC_06_LED_ACT_N
DFC_07_LED_ACT_N
DFC_09_LED_ACT_N
DFC_08_LED_ACT_N
HFC_00_CHNG_DET_N
HFC_05_SDA
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
DFC_01_PRSNT_N
HFC_00_SDA
L2
L3
DFC_06_PERST_N
HFC_04_CHNG_DET_N
DFC_00_PWR_DISABLE
DFC_04_PWR_DISABLE
DFC_05_LED_ACT_N
DFC_04_PRSNT_N
DFC_01_LED_STA_N
HFC_02_CHNG_DET_N
DFC_05_PRSNT_N
DFC_10_LED_ACT_N
DFC_09_IFDET_N
L4
L5
L6
L7
L8
L9
L10
L11
L12
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
DFC_02_PRSNT_N
DFC_11_IFDET_N
DFC_03_PRSNT_N
DFC_08_PRSNT_N
DFC_04_LED_ACT_N
DFC_03_PWR_DISABLE
DFC_00_LED_STA_N
DFC_07_PWR_DISABLE
DFC_01_ACTIVITY_N
DFC_05_PWR_DISABLE
DFC_06_PRSNT_N
DS00003392B-page 34
2020 Microchip Technology Inc.
EEC1005
TABLE 10-3: SGPIO CONTROLLER - 84 PIN PACKAGE
Ball Number
Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C5
C6
C9
C10
D1
D2
D4
D5
D6
D7
D9
D10
E1
E2
E3
E4
E7
E8
E9
E10
F1
DFC_07_ACTIVITY_N
DFC_00_IFDET_N
DFC_05_LED_STA_N
BMC_I2C_SDA
BMC_I2C_SCL
DFC_03_ACTIVITY_N
DFC_00_PRSNT_N
RSVD
DFC_06_PWR_DISABLE
DFC_05_PWR_DISABLE
VCC
nRESET_IN
SGPIO_01_CLOCK
SGPIO_00_CLOCK
DFC_01_IFDET_N
DFC_02_ACTIVITY_N
NC
DFC_07_LED_STA_N
DFC_03_PWR_DISABLE
DFC_07_IFDET_N
SGPIO_00_LOAD
SGPIO_00_DATAOUT
DFC_02_PWR_DISABLE
RSVD
DFC_01_PWR_DISABLE
DFC_02_IFDET_N
VR_CAP
SGPIO_01_LOAD
VCC
VCC
VSS
VSS
DFC_06_LED_STA_N
DFC_02_LED_STA_N
CONFIG_PIN
DFC_04_PWR_DISABLE
BMC_2WIRE_RESET
VCC
VSS
SGPIO_01_DATAOUT
DFC_00_LED_ACT_N
nSTRAP_IN
VREF_ADC
2020 Microchip Technology Inc.
DS00003392B-page 35
EEC1005
TABLE 10-3: SGPIO CONTROLLER - 84 PIN PACKAGE (CONTINUED)
Ball Number
Function
F2
F3
F4
F7
F8
F9
F10
G1
G2
G4
G5
G6
G7
G9
G10
H1
H2
H5
H6
H9
H10
J1
DFC_01_LED_ACT_N
DFC_06_IFDET_N
VSS
VSS
DFC_07_PRSNT_N
DFC_00_PWR_DISABLE
DFC_04_ACTIVITY_N
DFC_04_IFDET_N
DFC_05_ACTIVITY_N
RSVD
VCC
VCC
VCC
DFC_04_LED_STA_N
DFC_03_LED_STA_N
DFC_05_IFDET_N
SPARE
DFC_03_LED_ACT_N
DFC_01_ACTIVITY_N
DFC_00_ACTIVITY_N
DFC_07_PWR_DISABLE
DFC_03_IFDET_N
CONFIG_BPNUM_PIN
SGPIO_01_DATAIN
DFC_02_PRSNT_N
DFC_04_LED_ACT_N
DFC_04_PRSNT_N
DFC_00_LED_STA_N
DFC_06_PRSNT_N
SGPIO_00_DATAIN
SGPIO_00_CTRL_TYPE
DFC_06_ACTIVITY_N
DFC_01_PRSNT_N
DFC_02_LED_ACT_N
DFC_03_PRSNT_N
DFC_06_LED_ACT_N
DFC_07_LED_ACT_N
DFC_05_LED_ACT_N
DFC_01_LED_STA_N
SGPIO_01_CTRL_TYPE
DFC_05_PRSNT_N
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DS00003392B-page 36
2020 Microchip Technology Inc.
EEC1005
TABLE 10-4: UBM CONTROLLER - 84 PIN PACKAGE
Ball Number
Function
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
DFC_00_PERST_N
DFC_02_IFDET_N
DFC_05_LED_STA_N
BMC_I2C_SDA
BMC_I2C_SCL
HFC_04_SCL
HFC_02_SCL
DFC_05_ACTIVITY_N
HFC_01_SDA
HFC_01_SCL
VCC
nRESET_IN
DFC_05_PERST_N
HFC_00_SCL
DFC_01_IFDET_N
HFC_04_SDA
HFC_02_SDA
DFC_07_LED_STA_N
DFC_04_PERST_N
DFC_07_IFDET_N
HFC_00_SDA
C2
C5
C6
C9
C10
D1
D2
D4
D5
D6
D7
D9
D10
E1
E2
E3
E4
E7
E8
E9
E10
F1
DFC_03_ACTIVITY_N/HFC_03_2WIRE_RESET
HFC_03_CHNG_DET_N
DFC_06_ACTIVITY_N
HFC_01_CHNG_DET_N
DFC_02_ACTIVITY_N/HFC_02_2WIRE_RESET
VR_CAP
DFC_03_PERST_N
VCC
VCC
VSS
VSS
DFC_06_LED_STA_N
DFC_02_LED_STA_N
CONFIG_PIN
DFC_07_ACTIVITY_N
BMC_2WIRE_RESET
VCC
VSS
DFC_02_PERST_N
DFC_00_LED_ACT_N
nSTRAP_IN
VREF_ADC
2020 Microchip Technology Inc.
DS00003392B-page 37
EEC1005
TABLE 10-4: UBM CONTROLLER - 84 PIN PACKAGE (CONTINUED)
Ball Number
Function
F2
F3
F4
F7
F8
F9
F10
G1
G2
G4
G5
G6
G7
G9
G10
H1
H2
H5
H6
H9
H10
J1
DFC_01_LED_ACT_N
DFC_06_IFDET_N
VSS
VSS
DFC_07_PRSNT_N
DFC_01_PERST_N
DFC_04_ACTIVITY_N/HFC_04_2WIRE_RESET
DFC_04_IFDET_N
DFC_07_PERST_N
DFC_07_PRSNT_N
VCC
VCC
VCC
DFC_04_LED_STA_N
DFC_03_LED_STA_N
DFC_05_IFDET_N
DFC_00_IFDET_N
DFC_03_LED_ACT_N
DFC_01_ACTIVITY_N/HFC_01_2WIRE_RESET
DFC_00_ACTIVITY_N/HFC_00_2WIRE_RESET
HFC_03_SCL
DFC_03_IFDET_N
J2
CONFIG_BPNUM_PIN
HFC_04_CHNG_DET_N
DFC_02_PRSNT_N
DFC_04_LED_ACT_N
DFC_04_PRSNT_N
DFC_00_LED_STA_N
DFC_06_PRSNT_N
HFC_00_CHNG_DET_N
HFC_03_SDA
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
DFC_06_PERST_N
DFC_01_PRSNT_N
DFC_02_LED_ACT_N
DFC_03_PRSNT_N
DFC_06_LED_ACT_N
DFC_07_LED_ACT_N
DFC_05_LED_ACT_N
DFC_01_LED_STA_N
HFC_02_CHNG_DET_N
DFC_05_PRSNT_N
DS00003392B-page 38
2020 Microchip Technology Inc.
EEC1005
TABLE 10-5: UBM_SGPIO CONTROLLER - 144 PIN PACKAGE
Ball Number
Function
A1
A2
DFC_02_IFDET2_N
BMC_I2C_SDA
BMC_I2C_SCL
NC
A3
A4
A5
NC
A6
RSVD
A7
HFC_02_SDA
DFC_06_ACTIVITY_N
DFC_07_IFDET_N
NC
A8
A9
A10
A11
A12
B1
DFC_05_PERST_N
DFC_02_LED_STA_N
DFC_01_IFDET2_N
B2
SGPIO_00_CLOCK/HFC_00_SCL
DFC_05_LED_STA_N
DFC_01_IFDET_N
HFC_03_SCL
B3
B4
B5
B6
HFC_03_SDA
B7
DFC_03_PERST_N
DFC_04_PERST_N
DFC_06_IFDET2_N
DFC_05_IFDET2_N
HFC_04_SDA
B8
B9
B10
B11
B12
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
D1
D2
D3
D4
D5
D6
D7
HFC_00_CHNG_DET_N
DFC_03_IFDET2_N
NC
SGPIO_01_CLOCK
NC
NC
RSVD
NC
DFC_07_LED_STA_N
DFC_02_ACTIVITY_N
HFC_01_SCL
DFC_03_ACTIVITY_N
HFC_01_CHNG_DET_N
VCC
DFC_00_PERST_N
DFC_02_IFDET_N
nRESET_IN
DFC_00_IFDET2_N
HFC_04_CHNG_DET_N
HFC_02_SCL
2020 Microchip Technology Inc.
DS00003392B-page 39
EEC1005
TABLE 10-5: UBM_SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
D8
D9
D10
D11
D12
E1
HFC_02_CHNG_DET_N
HFC_04_SCL
HFC_01_SDA
NC
HFC_00_2WIRE_RESET
BMC_2WIRE_RESET
NC
E2
E3
DFC_04_IFDET2_N
SGPIO_00_DATAOUT
VCC
E4
E5
E6
VSS
E7
VCC
E8
VSS
E9
SGPIO_01_DATAOUT
HFC_03_CHNG_DET_N
DFC_00_LED_ACT_N
NC
E10
E11
E12
F1
VR_CAP
F2
DFC_07_IFDET2_N
DFC_07_ACTIVITY_N
SGPIO_01_LOAD
VCC
F3
F4
F5
F6
DFC_06_IFDET_N
DFC_04_LED_STA_N
VSS
F7
F8
F9
DFC_07_PRSNT_N
nSTRAP_IN
F10
F11
F12
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
G11
G12
H1
H2
DFC_01_PERST_N
DFC_06_LED_STA_N
NC
VREF_ADC
NC
NC
VSS
VSS
DFC_04_ACTIVITY_N
VCC
HEARTBEAT_PIN
NC
DFC_03_LED_STA_N
DFC_05_ACTIVITY_N
CONFIG_PIN
DFC_05_IFDET_N
DS00003392B-page 40
2020 Microchip Technology Inc.
EEC1005
TABLE 10-5: UBM_SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
H3
H4
H5
H6
H7
H8
H9
H10
H11
H12
J1
HFC_01_2WIRE_RESET
DFC_01_LED_ACT_N
HFC_02_2WIRE_RESET
VCC
VCC
DFC_00_ACTIVITY_N
NC
NC
NC
NC
DFC_04_IFDET_N
DFC_00_IFDET_N
DFC_03_IFDET_N
NC
J2
J3
J4
J5
DFC_03_LED_ACT_N
DFC_01_PWR_DISABLE
HFC_03_2WIRE_RESET
DFC_06_PWR_DISABLE
NC
J6
J7
J8
J9
J10
J11
J12
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
K11
K12
L1
NC
NC
SGPIO_00_CTRL_TYPE
CONFIG_BPNUM_PIN
DFC_00_PRSNT_N
DFC_07_PERST_N
DFC_02_LED_ACT_N
HFC_04_2WIRE_RESET
DFC_02_PWR_DISABLE
DFC_06_LED_ACT_N
DFC_07_LED_ACT_N
NC
NC
SGPIO_00_DATAIN
NC
DFC_01_PRSNT_N
L2
SGPIO_00_LOAD/HFC_00_SDA
DFC_06_PERST_N
L3
L4
SGPIO_01_DATAIN
L5
DFC_00_PWR_DISABLE
DFC_04_PWR_DISABLE
DFC_05_LED_ACT_N
DFC_04_PRSNT_N
L6
L7
L8
L9
DFC_01_LED_STA_N
2020 Microchip Technology Inc.
DS00003392B-page 41
EEC1005
TABLE 10-5: UBM_SGPIO CONTROLLER - 144 PIN PACKAGE (CONTINUED)
Ball Number
Function
L10
L11
L12
M1
SGPIO_01_CTRL_TYPE
DFC_05_PRSNT_N
NC
DFC_02_PERST_N
DFC_02_PRSNT_N
NC
M2
M3
M4
DFC_03_PRSNT_N
NC
M5
M6
DFC_04_LED_ACT_N
DFC_03_PWR_DISABLE
DFC_00_LED_STA_N
DFC_07_PWR_DISABLE
DFC_01_ACTIVITY_N
DFC_05_PWR_DISABLE
DFC_06_PRSNT_N
M7
M8
M9
M10
M11
M12
DS00003392B-page 42
2020 Microchip Technology Inc.
EEC1005
11.0 ELECTRICAL SPECIFICATIONS
11.1 Maximum Ratings*
*Stresses exceeding those listed could cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at any other condition above those indicated in the operation sections of this specification
is not implied.
Note:
When powering this device from laboratory or system power supplies, it is important that the Absolute Max-
imum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on
their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line
may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used.
11.1.1
ABSOLUTE MAXIMUM THERMAL RATINGS
Parameter
Maximum Limits
-40oC to +85oC Industrial
-55o to +150oC
Operating Temperature Range
Storage Temperature Range
Lead Temperature Range
Refer to JEDEC Spec J-STD-020B
11.1.2
ABSOLUTE MAXIMUM SUPPLY VOLTAGE RATINGS
Symbol
Parameter
3.3V Power Supply with respect to ground
Maximum Limits
VCC
-0.3V to +3.63V
11.1.3
ABSOLUTE MAXIMUM I/O VOLTAGE RATINGS
Parameter
Maximum Limits
Determined by Power Supply of I/O Buffer and Pad Type
Voltage on any Digital Pin with respect to ground
11.2 Operational Specifications
11.2.1
POWER SUPPLY OPERATIONAL CHARACTERISTICS
TABLE 11-1: POWER SUPPLY OPERATING CONDITIONS
Symbol
Parameter
MIN
TYP
MAX
Units
VCC
3.3V Power Supply
3.135
3.3
3.465
V
11.2.2
CAPACITIVE LOADING SPECIFICATIONS
The following table defines the maximum capacitive load validated for the buffer characteristics listed in Table 11-4, "DC
Electrical Characteristics".
CAPACITANCE TA = 25°C; fc = 1MHz; Vcc = 3.3 VDC
Note:
All output pins, except pin under test, tied to AC ground.
2020 Microchip Technology Inc.
DOS-00000
DS00003392B-page 43
EEC1005
TABLE 11-2: MAXIMUM CAPACITIVE LOADING
Limits
TYP
Parameter
Symbol
Unit
Notes
MIN
MAX
Input Capacitance
Output Capacitance
CIN
COUT
10
20
pF
pF
Note 1
Note 2
Note 1: All input buffers can be characterized by this capacitance unless otherwise specified.
2: All output buffers can be characterized by this capacitance unless otherwise specified.
11.2.3
DC ELECTRICAL CHARACTERISTICS FOR I/O BUFFERS
TABLE 11-3: BUFFER TYPE
Signal Name
Buffer Type
DFC_xx_ACTIVITY_N
DFC_xx_IFDET_N
I
I
I
DFC_xx_IFDET2_N
DFC_xx_PRSNT_N
I
HFC_xx_2WIRE_RESET
DFC_xx_LED_ACT_N
DFC_xx_LED_STA_N
DFC_xx_PERST_N
I
OD-2mA
OD-2mA
OD-2mA
OD-2mA
PIO
DFC_xx_CHNG_DET_N
DFC_xx_PWR_DISABLE_N
CONFIG_PIN
I_AN
I_AN
CONFIG_BPNUM_PIN
xx is the instance/port number
Note:
DS00003392B-page 44
DOS-00000
2020 Microchip Technology Inc.
EEC1005
TABLE 11-4: DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
MIN
TYP
MAX
Units
Comments
PIO Type Buffer
All PIO Buffers
Internal PU selected via the
GPIO Pin Control Register.
Pull-up Resistor @3.3V
All PIO Buffers
RPU
34
52
63
95
KΩ
Internal PD selected via the
GPIO Pin Control Register.
Pull-down Resistor @3.3V
PIO
RPD
VOL
38
127
0.4
KΩ
V
IOL = 4 mA (min)
VOH
VCC-
0.4
V
IOH = -4 mA (min)
OD-2mA
Low Output Level
I Type Input Buffer
Low Input Level
High Input Level
Schmitt Trigger Hysteresis
VOL
0.4
V
IOL = 2mA (min)
TTL Compatible Schmitt Trigger
Input
VILI
0.3x
VCC
V
VIHI
0.7x
VCC
V
VHYS
400
mV
I_AN Type Buffer
I_AN Type Buffer
(Analog Input Buffer)
I_AN
Voltage range on pins:
-0.3V to +3.63V
These buffers are not 5V tolerant
buffers and they are not back-
drive protected
ADC Reference Pins
VREF_ADC
Voltage (Option A)
V
VCC
V
Connect to same power supply
as VCC
Voltage (Option B)
Input Impedance
Input Low Current
V
2.97
3.0
75
3.03
V
RREF
ILEAK
KΩ
µA
-0.05
+0.05
This buffer is not 5V tolerant
This buffer is not backdrive pro-
tected.
2020 Microchip Technology Inc.
DOS-00000
DS00003392B-page 45
EEC1005
11.2.3.1
Pin Leakage
Leakage characteristics for all digital I/O pins is shown in the following Pin Leakage table, unless otherwise specified.
Two exceptions are pins with Over-voltage protection and Backdrive protection (10.2 “Pin List”). Leakage character-
istics for Over-Voltage protected pins and Backdrive protected pins are shown in the two sub-sections following the Pin
Leakage table.
TABLE 11-5: PIN LEAKAGE (VCC=3.3V + 5%; VCC = 1.8V +5%)
(TA = -40oC to +85oC)
Leakage Current
IIL
+/-2
µA
VIN=0V to VCC
11.2.4 ADC ELECTRICAL CHARACTERISTICS
TABLE 11-6: ADC CHARACTERISTICS
Symbol
VCC
Parameter
MIN
TYP
MAX
Units
Comments
Analog Supply Voltage
Input Voltage Range
3.135
0
3.3
3.465
V
V
VRNG
VREF
_ADC
Range of VREF_ADC
input to ADC ground
RES
ACC
DNL
INL
Resolution
–
–
–
10/12
4
Bits
LSB
Guaranteed Monotonic
Absolute Accuracy
Differential Non Linearity, DNL
Integral Non Linearity, INL
Gain Error, EGAIN
2
–
-1
+1
+3
2
LSB
Guaranteed Monotonic
Guaranteed Monotonic
-3.0
-2
–
LSB
EGAIN
EOFFSET
CONV
II
–
LSB
Offset Error, EOFFSET
Conversion Time
-2
–
2
LSB
1.125
4.5
S/channel
M
Input Impedance
4
5.3
11.2.5
THERMAL CHARACTERISTICS
TABLE 11-7: THERMAL OPERATING CONDITIONS
Rating
Symbol
MIN
TYP
MAX
Unit
Consumer Temperature Devices
Operating Junction Temperature Range
Operating Ambient Temperature Range - Industrial
TJ
0
—
—
125
+85
°C
°C
TA
-40
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH)
69.3
(PINT + PI/O)
PD
mW
W
I/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
a
Maximum Allowed Power Dissipation
PDMAX
(TJ – TA)/JA
o
a.Tj Max value is at ambient of 70 C
DS00003392B-page 46
DOS-00000
2020 Microchip Technology Inc.
EEC1005
11.3 Power Consumption
TABLE 11-9: VCC SUPPLY CURRENT, I_VCC
Typical(3.3V, Max (3.45V,
25C) 70C)
Max (3.45V,
85C)
48 MHz Clock
Unit
Comments
48MHz
9.41
13.79
15.8
mA
Full On
2020 Microchip Technology Inc.
DOS-00000
DS00003392B-page 47
EEC1005
12.0 PACKAGE INFORMATION
12.1 144 Pin WFBGA/WC Package
Note:
For the most current package drawings, see the Microchip Packaging Specification at http://www.micro-
chip.com/packaging.
144-Ball Very, Very Thin Fine Pitch Ball Grid Array (WCX) - 10x10 mm Bodyꢀ[WFBGA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
(A1)
144X
D
A
0.08
C
B
E
NOTE 1
0.10
C
1
2
3
4
5
6
7
8
9
10 11 12
A
B
C
D
E
F
G
H
J
(DATUM B)
(DATUM A)
K
L
2X
M
0.15
C
2X
A2
0.15
C
TOP VIEW
A
SEATING
PLANE
D1
1
2
3
4
5
6
7
8
9
10 11
12
SIDE VIEW
M
L
K
J
H
G
e
E2
F
E
D
C
B
A
e
2
144X Øb
0.15
e
C
C
A B
0.08
BOTTOM VIEW
Microchip Technology Drawing C04-416A Sheet 1 of 2
DS00003392B-page 48
2020 Microchip Technology Inc.
EEC1005
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2020 Microchip Technology Inc.
DS00003392B-page 49
EEC1005
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DS00003392B-page 50
2020 Microchip Technology Inc.
EEC1005
12.2 84 Pin WFBGA/SX1 Package
Note:
For the most current package drawings, see the Microchip Packaging Specification at http://www.micro-
chip.com/packaging.
2020 Microchip Technology Inc.
DS00003392B-page 51
EEC1005
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision
Section/Figure/Entry
Correction
DS00003392B (05-06-20)
DS00003392A (02-26-20)
Section 7.6, "Capabilities
(0x33)"
Register bits "2-Wire Reset” updated to 02h.
Section 11.0, "Electrical Spec- Chapter added
ifications"
Initial document
DS00003392B-page 52
2020 Microchip Technology Inc.
EEC1005
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://www.microchip.com/support
2020 Microchip Technology Inc.
DS00003392B-page 53
EEC1005
PRODUCT IDENTIFICATION SYSTEM
Not all of the possible combinations of Device, Temperature Range and Package may be offered for sale. To order or
obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](3)
Temp Range/ Tape and Reel
X/XXX(2)
-
PART NO.(1)
Device
-
X
-
XX
-
Example:
Total Version/
SRAM
a)
EEC1005-I/WC = EEC1005 with 12-drive UBM
solution provided with FW
Revision
Package
Option
(1)
Device:
EEC1005
UBM Controller
256KB
Total SRAM:
H
Version/
Revision:
B#
B = Version, # = Version Revision Number
o
Note 1:
2:
These products meet the halogen maximum
concentration values per IEC61249-2-21.
All package options are RoHS compliant.
For RoHS compliance and environmental
information, please visit http://www.micro-
chip.com/pagehandler/en-
o
TemperatureRange: I/
= -40 C to +85 C (Industrial)
Package:
WC
144 pin WFBGA 10x10mm body,
us/aboutus/ehs.html
0.80mm pitch
3:
Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option
SX1
84 pin WFBGA 7x7mm body,
0.65mm pitch
Tape and Reel
Option:
Blank
TR
=
=
Tray packaging
Tape and Reel
(3)
DS00003392B-page 54
2020 Microchip Technology Inc.
EEC1005
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522458968
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2020 Microchip Technology Inc.
<Redtext>
DS00003392B-page 55
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DS00003392B-page 56
2020 Microchip Technology Inc.
05/14/19
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