HV512X_技术文档

HV512

64-Channel Serial To Parallel Converter

With Temperature Sense

and High Voltage Push-Pull Outputs

Ordering Information

Package Option

Micro-BGA

HV512GA

Device

Die

HV512

HV512X

Features

General Description

The HV512 is a low voltage serial to high voltage parallel

converter with push-pull outputs. The device allows switching of

the outputs between V_PPand HVGND.

❏ High voltage HVCMOS^®output

❏ Output voltages from 0V to 50V-200V

❏ Low power level shifting

Data is loaded into the 64-bit shift register using the data input

signal, D_IOAor D_IOB, and clock, CLK. Control of the data direction

is by the use of the DIR pin. Data is shifted out through the data

output signals, D_IOBor D_IOA. The data is controlled through the

device using the latch enable, LE, and blank, BLE_X, control

signals. The output drivers are further controlled by a polarity,

POL, and high-Z, HI-Z, control lines.

❏ Shift register speed 12.5MHz double clocked

for 25MHz data rate

❏ Logic control includes Direction, Blank, Polarity,

Latch and High-Z

❏ CMOS compatible inputs

❏ Internal pull-up or pull-down on logic inputs

❏ Continuously monitored temperature sense

❏ Quad 16-bit output latch control

Die temperature sensing is provided to inform the user when the

die temperature reaches the limit of the operating temperature.

Absolute Maximum Ratings

Logic supply voltage, V_DD

7.5V

Driver supply voltage, V_PP

220V

Output voltage

220V

Input voltage¹

-2.0V to V_DD+2.0V

Thermal Resistance

Junction to Case, R_JC

1 °C/W

Operating Temperature Range

-0°C to +150°C

All voltages are referenced to GND.

1

Minimum of -2.0V for 20 nsec. Maximum of V_DD+2.0V for 20 nsec. allowable.

10/17/01

Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability

indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to

workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the

Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

1

HV512

Electrical Characteristics

DC Characteristics (Over recommended Operating Conditions unless otherwise noted)

Symbol

V_OH

Parameter

Min

Typ

Max

Units

Conditions

High-level output voltage

HV outputs

Serial output

HV outputs

Serial output

V_PP-2.0

V_DD-0.75

V

I_OH=-1mA

V_DOH

V_OL

V_DD=4.5V, I_OH=-100 µA

I_OL=1mA

Low-level output voltage

High level input voltage

2.0

0.75

V_DOL

V_IH

V_DD=4.5V, I_OL=100 µA

0.8 V_DD

-0.5

V_DD+ 0.5

Standard CMOS levels, with

respect to ground

V_IL

Low level input voltage

AV_DDcurrent

0.2 V_DD

V

I_AVDD

I_DD

0.2

25

1

mA

V_DDcurrent

inputs high, f_CLK= 12.5MHz ¹

I_DDQ

V_DDquiescent current

all inputs = floating; D_IOA, D_IOB

CLK = LOW

,

I_PP

V_PPcurrent

mA

C_L=10pF

C_L=30pF

30

25

f_OUT= 300Kcycles, V_PP= 220V

f_OUT= 100Kcycles, V_PP= 220V

Outputs H or L.

I_PPQ

I_O(OFF)

I_H

V_PPquiescent current

0.5

TBD

10

ma

µA

High-Z state output current

High-level input current ²

For inputs with 20k pull-up resistor

275

For inputs with 20k pull-down

resistor

I_L

Low-level Input current ²

10

µA

For inputs with 20k pull-down

resistor

275

120

25

For inputs with 20k pull-up resistor

T_TRIP

T_HYS

Over temperature trip level

Temperature hysteresis

110

115

°C

Required cooling to reset /OT

output

Internal Capacitance

Symbol Parameter

Max

10

5

Unit

Condition

f = 1 MHZ

f = f_Omax

f = 1 MHZ

C_IN

Input Capacitance

pF

C_HVout

C_OUTL

HV Output Capacitance

Output Logic Capacitance

10

2

HV512

Electrical Characteristics, continued:

AC Characteristics (Over recommended Operating Conditions unless otherwise noted)

Symbol

f_CLK

Parameter

Min

Typ

Max

12.5

25

Units Conditions

Clock frequency

MHZ

nsec

to 140°C T_J

f_DATA

t_WL, t_WH

t_SU

Data rate

Clock width low / high

Data setup to before clock rise/fall

Data hold after clock rise/fall

Delay clock to logic output rise/fall

Clock rise/fall to latch enable fall

Latch enable width

30

15

t_H

t_LL, t_LH

t_DLE

t_WLE

t_SLE

200

250

Not compatible for cascading at 12.5MHz

Min. time to allow S/R to settle before LE

Min. LE pulse width to latch data

25

40

80

60

0

Latch enable fall to clock rise/fall

Setup time from LE to BLE_X

Input rise time

Delay before restarting clock

t_LBH

t_R

10

All input signals

t_F

Input fall time

0

t_ON, t_OFF

BLE_Xor POL to HV output rise/fall

500

100

nsec

10pF external load, to start (10%) of output

rise or start (90%) of output fall

∆t_ON, ∆t_OFFVariation on single IC

t_OT

f_D

Over temp sense

250

300

nsec

kHz

From over temp sense to output state ³

10pF external load

HV output switching rate

0

100

550

30pF external load

10pF external load ⁴

t_DR90

t_DR95

t_DF10

t_DF5

HV output 90% rise time

HV output 95% rise time

HV output 10% fall time

HV output 5%Fall Time

HV output to high-Z State

nsec

900

600

30pF external load ⁴

10pF external load ⁴

1000

550

30pF external load ⁴

10pF external load ⁴

900

600

30pF external load ⁴

10pF external load ⁴

1000

500

30pF external load ⁴

t_HI-Z

Input to high-Z state on outputs

Recommended Operating Conditions

Symbol

V_PP

Parameter

Min

50

Typ Max Units

Conditions

High voltage supply

Logic supply voltage

Over-temp circuit supply

Shift clock frequency

Junction temperature

200

5.25

V

V_DD

4.75

5.0

AV_DD

f_SC

12.5 MHZ

140 °C

T_J

10

3

HV512

Electrical Characteristics, continued:

Absolute Maximum Ratings

Symbol

V_DD

Parameter

Min

-0.5

-2.0

-65

0

Max

7.5

Units

V

Conditions

with respect to ground ⁵

Logic Supply Voltage

Analog Supply Voltage

High Supply Voltage

Logic Inputs

AV_DD

V_PP

7.5

V

with respect to ground ⁵

No bias

220

V

V_IN

V_DD+2.0 ⁶

150

V

T_STG

T_J

Storage Temperature

Junction Temperature

°C

µsec

150

Max DC voltages applied, all inputs GND ⁷

T_SHORTOutput Short Duration

2

Any high output to any output at any levels, or

any output to ground, V_PP; with V_PPat max

voltage; no IC damage (need characterization)

Notes:

1

Outputs switching V_PP= 200V to GND, 300,000 times per second, 10pf external load on each output. Or, outputs switching V_PP= 200V to GND

100,000 times per second, 30pF external load on each output.

2

3

4

Inputs include nominal 20k ±25% value bias resistor to V_DDor GND to prevent damage from a floating input.

Need to respond, typically setting Hi-Z to LOW, to over-temperature (/OT) signal within 1ms to prevent die damage.

Rise and fall times are currently based on simulation of S-4 process. This is a new process and distribution of variance is not completely modeled.

Thus, these numbers are goals and not a guarantee of production performance. (DELETE THIS NOTE ON FINAL SPEC)

5

6

7

All grounds must be at the same potential.

Minimum of -2.0V for 20 nsec. Maximum of V_DD+2.0V for 20 nsec. allowable.

Power dissipation assumes a package with a thermal resistance = 7.5 °C / Watt in 50 °C ambient. Duty cycle is limited by total power dissipation of

the carrier.

Power sequence should be the following:

1. Connect ground.

2. Apply V_DD, AV_DD, and V_PPbias (≥V_DD-1V).

3. Set all inputs (Data, CLK, Enable, etc.) to a known state.

4. Apply full V_PP. Power down sequence should be the reverse of the above.

Input and Output Equivalent Circuit

V

DD

V

DD

V

PP

*

Data Out

HV

OUT

Input

*

GND

HV

GND

Logic Inputs

Pull-up or pull-down resistor

Logic Data Output

4

High Voltage Outputs

*

HV512

Pad/Ball Definitions

Pad

13

12

5

Ball #

A6

A7

B1

A2

B4

A3

B6

B7

B10

A9

A8

F5

Name

AGND

AV_DD

BLE_A

BLE_B

BLE_C

BLE_D

CLK

I/O

Function

-

Analog ground for over-temp circuit

Over-temp circuit supply voltage

Transfers data from 64-bit latches to output latches when low

Clock shift register data on rise/fall edge

Shift register input data when DIR=L

Shift register input data when DIR=H

Controls the data shift directions

Logic ground

-

I

6

I

7

I

8

I

15

18

19

14

11

2

I

D_IOA

I/O

D_IOB

O/I

I

DIR

GND

HVGND

LE

-

V_PPground

22

66

9

F6

-

V_PPground

L5

-

V_PPground

A4

B3

B9

B2

N/C

A5

E5

E6

L6

I

Transfers data from shift register to 64-bit latches when high

Set all HV outputs to high-Z state when low

Logic supply voltage

3

HI-Z

I

20

4

V_DD

-

POL

N/C

I

Output polarity control

21

10

1

-

not used, leave open

V_DD

-

Logic supply voltage

V_PP

-

High voltage source supply

23

47

16

17

V_PP

-

High voltage source supply

V_PP

-

High voltage source supply

B8

A10

TEST

OT

-

Not used, leave open

O

Signal for die over temperature detection

High Voltage Outputs

Pad

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

74

Ball #

D2

C2

E2

D1

E1

F2

Name

Pad

73

72

71

70

69

68

67

65

64

63

62

61

60

59

58

57

Ball #

Name

HV17

HV18

HV19

HV20

HV21

HV22

HV23

HV24

HV25

HV26

HV27

HV28

HV29

HV30

HV31

HV32

Pad

56

55

54

53

52

51

50

49

48

46

45

44

43

42

41

40

Ball #

Q6

Name

HV33

HV34

HV35

HV36

HV37

HV38

HV39

HV40

HV41

HV42

HV43

HV44

HV45

HV46

HV47

HV48

Pad

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

Ball #

K10

J9

Name

HV49

HV50

HV51

HV52

HV53

HV54

HV55

HV56

HV57

HV58

HV59

HV60

HV61

HV62

HV63

HV64

HV1

L1

HV2

M1

K2

P6

HV3

Q7

N10

J10

H9

HV4

P1

Q9

HV5

N2

L2

P7

HV6

Q8

H10

G10

F10

G9

C1

F1

HV7

M2

P2

Q10

P8

HV8

G2

G1

H1

H2

J1

HV9

P3

P9

HV10

HV11

HV12

HV13

HV14

HV15

HV16

Q1

Q3

P4

M9

L9

C10

E10

F9

N9

Q2

Q4

P5

P10

K9

D10

C9

N1

J2

M10

L10

E9

K1

Q5

D9

5

HV512

Switching Waveforms

Input Timing Diagram

t_SU

t_H

t_SU

t_H

V_IH

V_IL

Data Input

(D_IOAor D_IOB

DATA VALID #1

DATA VALID #2

)

t_WH

t_WL

V_IH

V_IL

Clock

t_LL

t_LH

V_DOH

Data Output

VALID OUTPUT

(D_IOBor D_IOA

)

V_DOL

t_DLE

t_SLE

V_IH

V_IL

LE

t_WLE

NOTE: First input data is loaded on rising clock edge.

Output Timing Diagram

V_IH

V_IL

LE

t_LBH

V_IH

V_IL

BLE

X

POL

V_IH

V_IL

t_ON

V_OH

V_OL

HV w/ LO Low

90%

10%

t_ON

t_OFF

t_ON

t_OFF

90%

V_OH

HV w/ LO High

10%

V_OL

t_DR90

t_DF90

6

HV512

Functional Block Diagram

* POL

** BLE_A

** BLE_B

* LE

V_PP

Output Latches

16-bit Latch

(L01...L016)

to ouputs 1-16

D_IOB

SR1

LI1

HV_OUT1

HV_OUT

2

❏

16-bit Latch

(L017...L032)

to ouputs 17-32

Clock

64 bit

Static Shift

Register

60 Additional

Outputs

64-bit

Latch

* DIR

❏

16-bit Latch

(L033...L048)

to ouputs 33-48

to ouputs 49-64

D_IOA

HV_OUT63

HV_OUT64

16-bit Latch

(L049...L064)

SR64

LI64

** BLE_C

** BLE_D

HV_GND

* HI-Z

*

Inputs have internal 20k-ohm pull-up resistor to V

DD

Over Temp Sense

OT

** Inputs have internal 20k-ohm pull-down resitor to GND

Functional Table

Function

Data In CLK DIR LE BLE_XPOL Hi-Z Data Out

Action

I/O Relation to Shift

Register

SR1 →

D_IOB

Shift even registers;

D_IOA→ SR64 → SR62 ...

↑

D_IOA

L

SR2 →

D_IOB

Shift odd registers;

D_IOA→ SR63 → SR61 ...

↓

↑

↓

SR64 → Shift odd registers;

D_IOAD_IOB→ SR1→ SR3 ...

D_IOB

H

SR63 → Shift even registers;

D_IOA

N/A

D_IOB→ SR2 → SR4 ...

64-bit Latch transparent

64-bit Latch held

X

H

L

SR_NLI_N

LI_Nheld to previous value

HV outputs OFF

X

L

H

LI_N→ LO_N; HV outputs High

LI_N→ LO_N; HV outputs Low

L

X

H

N/A

HV outputs ON

LO_Nheld to previous value;

HV_OUTN=LO_N

L

H

LO_Nheld to previous value;

HV_OUTN=LO_N

X

H

N/A

High-Z

X

L

N/A

Outputs have high impedance

Outputs operational

Outputs functioning

H

7

HV512

Typical Operation

(refer to the Functional Block Diagram and Function Table)

Die Temperature Sensing

Data is first loaded into the 64-bit shift register using the clock,

CLK, and data input lines, D_IOAor D_IOB. If the direction pin, DIR,

is high, then data is shifted into D_IOBand out D_IOA; SR1 to SR64.

If DIR is low, then data is shifted into D_IOAand out D_IOB; SR64 to

SR1. The data rate is twice the CLK frequency. The first data bit

is loaded on the rising clock edge and the next data is loaded on

the falling edge; 32 complete clock cycles are required to load

the 64-bit shift register. Data is transferred from 64-bit shift

register to the 64-bit latch when the latch enable, LE, is high.

When LE is set low, data is retained in the 64-bit latch.

A signal is provided for die over-temp sensing, OT. A CMOS

digital LOW signal will be provided when the center of the die

temperature exceeds T_TRIP. This will be a non-synchronized,

non-latched, continuously monitored output that will contain

hysteresis to prevent oscillation at the threshold temperature.

This circuit is driven by the analog supply, AV_DDand AGND.

OT Level

The blanking signals, BLE_A, BLE_B, BLE_C, and BLE_D, do two

functions: blanking and data transfer from the 64-bit latch to the

four 16-bit output latches. BLE_Acontrols HV outputs 1 through

16, BLE_Bcontrols HV outputs 17 through 32, etc. When BLE_Xis

low, the high voltage, HV, outputs are blanked and data transfers

from the 64-bit latch to the output latch. When BLE_Xis high, the

HV outputs are enabled and data in the output latch is retained.

A blanked HV output combined with a high polarity signal, POL,

sets the HV output low. If POLis low, the blanked HV output is set

high.

T

HYS

H

L

OT

Temperature

If BLE_Xis high, the data in the 16-bit output latch are sent to the

HV outputs. If POL is high the HV output is not inverted; a high

data yields a high HV output. If POL is low, the HV output is

inverted.

Figure 2: Over-temp/Hysteresis Performance

The control signal High-Z, HI-Z, sets the HV outputs to a high

impedance state. If HI-Z is high, the outputs can be set to either

high or low. If HI-Z is low, the outputs are set to a high impedance

state, both output transistors are turned off.

V_PP

C1

V_DD

V_PP

V_DD

C3

HV_OUT

HV512

GND

HV_GND

Figure 1: Typical Connection

8

HV512

µBGA^®PACKAGE, 91 BALL, 15x10 ARRAY ASSEMBLY DRAWING

(Unless Otherwise Specified, Dimensions are in Millimeters)

Bump View

NOTES:

1.

2.

3.

4.

5.

6.

Dimensioning and tolerancing per ASME Y14.5M-1994.

Do not subject part to ultrasonic cleaning or intense UV.

Mark back of die with laser.

Contact ball position designation per JESD 95-1, SOO-010.

Die P/N HV512.

Elastomer

106000200108 (Dow Corning 6811 Encapsulant).

1030001000108 (Dow Corning 6910 Space Adhesive).

Make from Eutectic Solder Ball (ø0.3mm). Dimensions apply after solder ball reflow.

Datum Z established by high points of solder bumps.

Elastomer shall not extend beyond Datum A.

Max. vertical load allowed per ball of 40 grams.

7.

8.

9.

10.

9

HV512

µBGA^®PACKAGE, 91 BALL, 15x10 ARRAY ASSEMBLY DRAWING,

Continued

(Unless Otherwise Specified, Dimensions are in Millimeters)

Back View

Side View

(Not to Scale)

10

HV512

µBGA^®PACKAGE, 91 BALL, 15x10 ARRAY ASSEMBLY DRAWING,

Continued

(Unless Otherwise Specified, Dimensions are in Millimeters)

GENERAL ASSEMBLY SECTION

(NOT TO SCALE)

10/17/01

1235 Bordeaux Drive, Sunnyvale, CA 94089

TEL: (408) 744-0100 • FAX: (408) 222-4895

www.supertex.com

11


型号：	HV512X
厂家：	MICROCHIP
描述：	SIPO Based Peripheral Driver, CMOS, DIE 驱动接口集成电路
文件：	总11页 (文件大小：100K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

HV512X [MICROCHIP]

相关型号：

HV513

HV513K7-G

HV513K7-GM935

HV513WG

HV513WG-G

HV513_13

HV514

HV514WG

HV514WG-G

HV518

HV518P

HV518P-G