HV53001 [MICROCHIP]
16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter;
| 型号： | HV53001 |
| 厂家： | 
MICROCHIP |
| 描述： | 16-Channel, ±135V Push-Pull Driver with RTZ, Current Sensor and Built-in Boost Converter |
| 文件： | 总40页 (文件大小：1904K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HV53001
16-Channel, ±135V Push-Pull Driver with RTZ,
Current Sensor and Built-in Boost Converter
Features
General Description
• 16-Channel Push-Pull Output
The HV53001 device is an integrated driver solution
for various applications, which consists of three main
functional blocks (1) high-voltage driver, (2) SPI inter-
face and (3) DC/DC boost controller with power
MOSFET.
• Return-To-Zero (RTZ) and High-Impedance (Hi-Z)
Function
• Up to ±135V Output Voltage
• 24 mA Minimum Source Sink Output Current
• 250 pF Maximum Output Load
• Current Sensor Output
The high-voltage driver block includes 16 push-pull
drivers capable of ±135V output swing with Return-To-
Zero (RTZ) function. Each output driver is capable of
sourcing and sinking at least 24 mA. Each high-volt-
age output is capable of driving up to 250 pF capaci-
tive load. A global current sensor function is also
integrated into this device to monitor the charge and
discharge currents. The measured current is mapped
to a low-voltage analog output with a scale factor of
3.1 V/V via a current sensing resistor.
• SPI Interface with Quad-Latched 2-bit per Chan-
nel Architecture
• Power-on Reset Function
• DC/DC Boost Converter with Power MOSFET
• 2.7 to 5.5V Converter Input Voltage
• Short Circuit Protection
• Overtemperature Monitor
The SPI interface is used to communicate between the
host processor and the high-voltage drivers. This inter-
face accepts a 3.3V logic I/O signal up to clock speed
of 32 MHz. Five digital LATCH control signals manage
the data flow and the firing pattern. It establishes the
output to one of four possible states: VPP, VNN, 0V or
high impedance.
• Power ON/OFF Sequence Control
• Shutdown Function
• 105-ball 9 x 9 mm TFBGA Package
Application
• Surface Haptic Application
• MEMS Driver
This IC also includes an integrated DC/DC controller
with power MOSFET. The controller is used in a fly-
back configuration to generate four high-voltage rails,
±135V and ±123V, for the high-voltage driver block.
The ±123V rails are created from two 12V floating sup-
plies referenced to the ±135V supply rails.
• Piezo Driver
The converter accepts input voltage from a single
2.7V-5.5V input voltage rail. A built-in positive charge
pump and a simple external negative charge pump
convert the input supply to +6.5V and -6.0V supplies to
power the high-voltage driver block.
Aproper power on and off sequence is critical to ensure
the operation of the high-voltage driver. A power
sequence control circuit is included for the user to con-
trol the power supplies to power up or down the high-
voltage driver. It is used in conjunction with the external
high-voltage FET transistors.
Safety features are added to the DC/DC converter. The
overvoltage protection monitors both high-voltage rails
to protect the driver against an overvoltage condition.
Short circuit protection detects any short circuit event at
the high-voltage rails by monitoring the current flow
2021 Microchip Technology Inc.
DS20006518A-page 1
HV53001
through the power FET transistor. When a short circuit
is detected, the DC/DC controller will shut down the
converter and send a fault signal at the SHORT pin.
The HV53001 device is packaged in a 9x9mm 105 ball
TFBGA package. All high-voltage I/Os are arranged to
have sufficient clearance for safety.
An overtemperature monitor function is also added in
the converter IC. It sends a fault signal at the TEMP pin
when it detects a temperature over the threshold
temperature.
Typical Application Diagram
2.7 to 12V
-VE LDO
LVGND
HVGND
+VE LDO
VBOVP
VBFB
RSHT
2.7V to 5.5V
Logic voltage
supply
VPF
VNF
VPP VNN VNNO VPPO
Sensor Circuit
POR
FILN FILP
VLL
FBP FBN
VDD
VCC
VIN
S
D
OVPP
OVPN
SHTN SHTP
CCP2
POWER
VNNSENSE
VPPSENSE
Power On
MOSFET
Sequence
Control
GATE
actuator
CHARGE
PUMP
DRIVER
CCP1
High Voltage
REGULATOR
Overvoltage
Protection
LATCHIN
LATCHA
LATCHB
LATCHC
LATCHD
HVOUT
0
DC/DC
VSSPUL
VSS
VBFB
VBOVP
REF
EN
CONTROLLER
Control
Logic
Short Circuit
Protection
Low Voltage
VSSPUL
Driver
HVOUT15
HV53001
TON
SPI
Temp
VREF
Interface
Sensor
STDBY
VLDO
AGND
SHTEN RT TEMP
SDI SDO SCK SS
SHORT
TRIG
SEQ[0:3]
HVGND
SHDN
PGND
DATA FROM MCU
CONTROL FROM MCU
DS20006518A-page 2
2021 Microchip Technology Inc.
HV53001
Package Types (Top View)
HV53001
9 x 9 TFBGA*
9
1
2
3
4
5
6
7
8
10
11
12
13
HV
1
HV
5
6
HV
4
HV
3
HV
2
HV 0
OUT
FILP
A
B
OUT
A
B
OUT
OUT
OUT
OUT
VPP
SENSE
HV
V
PPO
OUT
LATCHD
SS
SHDN
V
V
AGND
FBP
V
SS
VSSPUL
VBFB
LL
CC
C
D
E
C
D
E
HVGND LATCHC
HVGND LATCHB
SDI
Reserved OVPP
OVPN
NC
FBN
SDO
SCK
HVGND Reserved
HVGND STDBY
VBOVP
VLDO
TEMP
REF
HV
7
V
PP
OUT
VNN
LATCHA
SENSE
SHTEN SHORT
AGND
F
F
NC
NC
LATCHIN HVGND HVGND
HVGND HVGND HVGND
SEQ3
SHTN
SEQ2
SEQ1
SEQ0
TRIG
CSEQ
HV
HV
HV
8
9
V
G
G
OUT
PF
NF
NN
V
T
CCP1N
IN
ON
H
J
H
J
S
S
S
S
D
D
D
D
SHTP
D
V
EN
D
RT
CCP1P
CCP2N
V
OUT
DD
D
D
PGND
K
L
K
L
10
S
S
D
D
D
D
PGND
CCP2P
V
OUT
M
N
M
N
HV
11
HV
12
HV
13
HV
14
HV
15
FILN
V
NNO
OUT
OUT
OUT
OUT
OUT
1
2
3
4
5
6
7
8
9
10
11
12
13
* see Table 2-1.
2021 Microchip Technology Inc.
DS20006518A-page 3
HV53001
Block Diagram
SHDN
LATCHA,B,C,D
LATCHIN
4
GPIOs
32
32
32
32
32
32
32
32
Surface
Haptics
Element
4
2
2
HVOUT
HVOUT
0
1
SS
SCK
SDI
SPI
32
MCU
SDO
2
2
HVOUT14
HVOUT15
VPPSENSE
VNNSENSE
Analog
Inputs
IPP and INN
Current Sensors
DC/DC convrter
HV53001
VPP, VNN, VPF, VNF
DS20006518A-page 4
2021 Microchip Technology Inc.
HV53001
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
Converter Input Supply Voltage (VIN).........................................................................................................-0.3V to +6.0V
Enable Pin Input Voltage (EN) ....................................................................................................................... -0.3V to VIN
Power FET Drain-Source Voltage (VDS) .....................................................................................................-0.3V to +80V
Low Positive Voltage Supply (VDD) ............................................................................................................-0.3V to +8.0V
High Positive Supply Voltage (VPP)...........................................................................................................-0.3V to +140V
High Negative Supply Voltage (VNN).........................................................................................................-140V to +0.3V
High Positive Floating Supply Voltage (VPF)..........................................................................................VPP - 14V to VPP
High Negative Floating Supply Voltage (VNF) ...................................................................................... VNN to VNN + 14V
Analog Low Positive Voltage Supply (VCC)................................................................................................-0.3V to +8.0V
Analog Low Negative Voltage Supply (VSS).............................................................................................. -8.0V to +0.3V
Logic Voltage Supply (VLL).........................................................................................................................-0.3V to +4.0V
Logic Input Levels (Hi-V Driver, SPI Interface, LATCHX and SHDN).................................................. -0.3V to VLL +0.3V
Logic Input Levels (DC/DC Converter Controls) ...............................................................................-0.3V to VLDO +0.3V
Maximum Junction Temperature (TJ(MAX)) ...........................................................................................................+125°C
Storage Temperature...............................................................................................................................-65°C to +150°C
ESD Rating on Low-Voltage Pins (Human Body Model)............................................................................................2 kV
ESD Rating on Low-Voltage Pins (Charged Device Model).....................................................................................500 V
ESD Rating on High-Voltage Pins (Human Body Model).........................................................................................500 V
ESD Rating on High-Voltage Pins (Charged Device Model)....................................................................................500 V
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not intended. Exposure to maximum rating conditions for extended periods
may affect device reliability.
TABLE 1-1:
OPERATING SUPPLY VOLTAGES
Electrical Specifications: Unless otherwise specified: TA = TJ = +25°C. Boldface specifications apply over the TA=
TJ = range of -40°C to +125°C.
Parameter
Sym.
Min.
Typ.
-
Max.
Units
Conditions
Note 1
Input Supply Voltage
VIN
VPP
VNN
2.7
48
5.5
135
-48
V
V
V
High Positive Supply Voltage
High Negative Supply Voltage
-135
Low Positive Supply Voltage
(High-Voltage Driver)
VCC
VSS
6.0
6.5
7.0
V
V
Low Negative Supply Voltage
(High-Voltage Driver)
-6.5
-6.0
-5.5
Logic Input Supply Voltage (SPI
Interface)
VLL
VNF
VPF
3.0
3.3
3.6
V
V
V
Negative Floating Supply Voltage
Positive Floating Supply Voltage
VNN + 9V
VPP-13.2V
-
-
VNN+13.2V
VPP - 9V
High-Level Input Logic Voltage
(DC/DC Controls)
2.0
VIH
V
V
High-Level Input Logic Voltage
(High-Voltage Driver Controls)
0.8VLL
Low-Level Input Logic Voltage
(DC/DC Controls)
0
0
0.8
VIL
Low-Level Input Logic Voltage
(High-Voltage Driver Controls)
0.2VLL
Note 1: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006518A-page 5
HV53001
TABLE 1-2:
ELECTRICAL CHARACTERISTICS
Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k,
EN = 3.3V, VPP= +135V, VNN= -135V, VPF= +123V, VNF= -123V, VCC= +6.5V, VSS= -6.0V, VLL= +3.3V, VIN = +3.3V
unless otherwise specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Low Current Standby Mode
Low Threshold for EN Pin
High Threshold for EN Pin
Pull Down Resistor at EN Pin
Quiescent Current Draw from
VIL
VIH
0
0.8
VIN
V
V
2.0
500
k
A
EN = 3.3V
IINQ
5
EN = open
VIN Pin
Charge Pump Converter
Output Voltage
VDD
6.0
6.5
6.75
V
2.7V ≤ VIN ≤ 5.5V
Io = 10mA
Output IDD Load Current
Output Ripple Voltage
IDD
10
mA
mV
VRIPPLE
150
VIN = 3.3V, Io = 10mA,
CVDD = 10F (Note 3)
V
DD Under Voltage Lockout
VDDUVLO
4.25
4.75
V
V
(Note 2)
(Note 2)
(Rising Edge)
VDD Hysteresis (Falling)
Low Dropout Linear Regulator
Internal LDO Output Voltage
Clock Generation
0.25
VLDO
5.0
5.25
5.5
V
Minimum Switching Frequency
fs,min
fs,max
160
320
200
400
240
480
kHz
kHz
RT = 400k
RT = 200k
Maximum Switching
Frequency
Clock Ramp Maximum
Clock Ramp Minimum
Output Voltage Reference
Internally Set Reference
VTS
3.75
0.2
V
V
(Note 2)
(Note 2)
VRST
VREFINT
REFS
-3%
1.19
0.6
+3%
V
V
(Note 2) VIN = 3.7V
Internal Reference to Select
External Reference
-5.5%
+5.5%
External Reference Range
Output Current Feedback
OCP Threshold
REF
0.6
2.4
V
(Note 2)
(Note 2)
VREF2
40
60
mV
Ton Generation
T
T
T
ON Voltage Range
ON Ceiling Voltage
ON Floor Range
VTON
LIMITCL
LIMITFL
TON(min)
KTON
0
3
3
3
V
V
0.8VTS
0.25VTS
40
V
Minimum TON Time
250
ns
(Note 2)
Internal Gain in TON
Generation
s/V (Note 2)
Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all
input pins =0V unless noted. TJ=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
DS20006518A-page 6
2021 Microchip Technology Inc.
HV53001
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k,
EN = 3.3V, VPP= +135V, VNN= -135V, VPF= +123V, VNF= -123V, VCC= +6.5V, VSS= -6.0V, VLL= +3.3V, VIN = +3.3V
unless otherwise specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Over Voltage Protection
OVPP Set Point
OVPPR
OVPNR
OVPHYS
OVPDLY
-3%
-3%
1.19
1.07
0.12
50
+3%
+3%
V
V
VIN = 3.7V
OVPN Set Point
VIN = 3.7V
OVP Hysteresis
V
OVP Comparator Delay Time
ns
100 mV overdrive
(Note 2)
VSSPUL DRIVER
VSSPUL Switching Frequency
VSSPUL High Level Output
VSSPUL Low Level Output
Pull Up Resistance
fPUL
VOH
VOL
500
kHz
V
5.75
VDD = 6.5V, IO = 5 mA
VDD = 6.5V, IO = 5 mA
0.25
10
V
VDD = 5.75V
RON(UP)
RON(DN)
IPUL
(Note 2)
Pull Down Resistance
VDD = 5.75V
(Note 2)
5
Source and Sink Current
IL = 5mA at -6.0V out-
put (Note 2)
11
135
80
mA
Temp Sensor
Threshold Temperature
Power FET
TTH
°C
V
Note 2
Drain to Source Breakdown
voltage
VGS = 0V, ID = 250 .
BVDSS
Drain to Source ON-Resis-
tance
V
GS = 5V, VDS=12V.
RDS(ON)
60
m
(Note 2)
High-Voltage Driver
Quiescent VPP Supply Current
(Sum of Current at VPP and
VPPO Pins)
IPP
Q
3.7
5.6
mA
mA
Quiescent VNN Supply Current
(Sum of Current at VNN and
VNNO Pins)
INN
Q
-5.8
-5.2
-3.8
Quiescent VPF Supply Current
(Source)
IPF
Q
Q
-3.6
3.7
mA
mA
Quiescent VNF Supply Cur-
rent (Source)
INF
5.4
0.4
Quiescent High-Voltage Posi-
tive Supply Resultant Cur-
I
PPRQ
mA
mA
rent, IPPQ + IPF
Q
Quiescent High-Voltage Nega-
tive Supply Resultant Cur-
I
NNRQ
-0.4
rent, INNQ + INF
Q
Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all
input pins =0V unless noted. TJ=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006518A-page 7
HV53001
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k,
EN = 3.3V, VPP= +135V, VNN= -135V, VPF= +123V, VNF= -123V, VCC= +6.5V, VSS= -6.0V, VLL= +3.3V, VIN = +3.3V
unless otherwise specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
VPP Supply Current (Sum of
current at VPP and VPPO
pins)
V
PP=+90V, VNN=-90V,
IPP
7.5
mA
VPF=+78V, VNF=-78V,
HVOUT = 20kHz,CL=
f
250 pF, Running two
channels. Test pattern
= Figure 1-3 with
VNN Supply Current (Sum of
current at VNN and VNNO
pins)
INN
-7.5
mA
mA
12.5s pulse width
V
V
PP=+90V, VNN=-90V,
PF=+78V, VNF=-78V,
High-Voltage Positive Supply
Resultant Current, IPP + IPF
IPPR
2
fHVOUT = 20kHz,CL=
250 pF, Running two
channels. Test pattern
= Figure 1-3 with
High-Voltage Negative Supply
Resultant Current, INN + INF
INNR
-2
mA
mA
12.5s pulse width
VPP=+90V, VNN=-90V,
VCC Operating Supply Current
ICC
0.2
VPF=+78V, VNF=-78V,
Test pattern =
Figure 1-3 with 12.5s
pulse width
VSS Operating Supply Current
VLL Operating Supply Current
ISS
-0.2
-5.5
mA
mA
VLL = +3.3V
ILL
25
SCK = 32MHz, SDI =
16 MHz pulse train
VPP=+90V, VNN=-90V,
VPF Operating Supply Current
VNF Operating Supply Current
IPF
mA
mA
VPF=+78V, VNF=-78V,
fHVOUT = 20kHz,CL=
250 pF, Running two
channels. Test pattern
= Figure 1-3 with
INF
5.5
12.5 s pulse width
VNF Negative Floating Supply
Voltage
VNN+9V
VNN+13.2V
VPP-9V
VNF
-
-
V
V
VPF Positive Floating Supply
Voltage
VPP-13.2V
VPF
Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all
input pins =0V unless noted. TJ=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
DS20006518A-page 8
2021 Microchip Technology Inc.
HV53001
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k,
EN = 3.3V, VPP= +135V, VNN= -135V, VPF= +123V, VNF= -123V, VCC= +6.5V, VSS= -6.0V, VLL= +3.3V, VIN = +3.3V
unless otherwise specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
VPP=+90V, VNN=-90V,
VPF=+78V, VNF=-78V,
CL=250pF, Test pat-
tern = Figure 1-3 with
12.5s pulse width
HVOUT Switching Frequency
fHVOUT
0
25
kHz
HVOUT Output Source and
Sink urrent
VPP=+90V, VNN=-90V,
VPF=+78V, VNF=-78V
IHVOUT
24
40
mA
Return-To-Zero Slew Rate
90% to 10%
(i) from VPP to 0V
(ii) from VNN to 0V
VPP=+90V,VNN=-90V,
VPF=+78V,VNF=-78V,
VCC=+6.5V,VSS=-6.0V
CL = 250 pF
SR
100
200
V/s
Delay time for output to start
rise/fall
(from LATCHA, B, C, D to 1V
VPP = +135 V, VNN = -
135 V, VCC= 6.5V, VSS
= -6.0V No load. (Note
3)
td(ON/OFF)
100
40
ns
of HVOUT
)
Variation of delay time
(channel to channel)
td
ns
V
(Note 3)
Shutdown pin input enable
voltage
VIH(SHDN)
2.5
VPPSENSE and VNNSENSE Current Sensor
Vout
VPP = +135V, VNN = -
135V, VCC = +6.5V,
VSS = -6.0V
VPPSENSE/VNNSENSE Out-
put Voltage
0
3.6
V
(VPPSENSE/
VNNSENSE)
VPP = +135V, VNN = -
135V, VCC = +6.5V,
VSS = -6.0V, VPP-VPPO
and VNNO-VNN: from
0.1V to 1.0V
AVSENSE
(-40°C to
125°C)
Voltage Gain of Current Sen-
sor
-14%
-280
3.1
+14%
V/V
VPP = +135V, VNN = -
135V, VCC = +6.5V,
VSS = -6.0V, VPP-VPPO
and VNNO-VNN: from
0.1V to 1.0V
Sensing Amplifier Output
Offset
VOS
+280
mV
Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all
input pins =0V unless noted. TJ=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006518A-page 9
HV53001
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k,
EN = 3.3V, VPP= +135V, VNN= -135V, VPF= +123V, VNF= -123V, VCC= +6.5V, VSS= -6.0V, VLL= +3.3V, VIN = +3.3V
unless otherwise specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
(Note 3)
VPP = +90V, VNN = -
90V, VCC = +6.5V, VSS
= -6.0V, CL=3pF, Test
pulse: 1V, 1s pulse
width
Rise Time
(Time from 10% to 90% of
targeted value)
tR
300
ns
1. VPP and VPPO
2. VNN and VNNO
VPP = +90V, VNN = -
90V, VCC = +6.5V, VSS
= -6.0V, CL=20pF, Test
pulse: 1V, 1s pulse
width
Rise Time
(Time from 10% to 90% of
targeted value)
tR
740
ns
1. VPP and VPPO
2. VNN and VNNO
RLOAD
CLOAD
10
M
(Note 2)
(Note 2)
VPPSENSE/VNNSENSE
Output Load
3
pF
SPI Interface
Digital Input Clock frequency
High-level input logic voltage
Low-level input logic voltage
Logic I/O pin rise and fall time
fCLK
VIH
32
MHz Note: 3.3V logic input
0.8VLL
0
V
V
VIL
0.2VLL
tR, tF
5
ns
(Note 3) CL=15pF
(Note 2)
Sourced by any standard I/O
pin
Isource
Isink
10
10
mA
mA
Sunk by any standard I/O pin
(Note 2)
SPI Quiescent current of low-
voltage supplies with Shut-
down asserted
In shutdown mode.
All logic input = 0V.
V(SHDN) = VLL
ILL
Q
100
A
Time to enter and exit shut-
down
SCK=32MHz and SDI
= 16MHz pulse train.
tSHDN
tWAIT
tPKT
1
-
ms
ns
s
ns
Time from chip select and SPI
data
Refer to Figure 1-1
(Note 2)
20
4
50
-
Time to transfer 128-bits of
data
Refer to Figure 1-1
(Note 2)
-
Time from last clock pulse to
LATCHIN
Refer to Figure 1-1
(Note 2)
tH(LAT)
20
50
-
Digital Interface
Refer to Figure 1-2
(Note 2)
Time SPI latch held low
tab
tac
20
10
50
12
-
-
ns
Refer to Figure 1-2
(Note 2)
Time between SPI latches
s
Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all
input pins =0V unless noted. TJ=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
DS20006518A-page 10
2021 Microchip Technology Inc.
HV53001
TABLE 1-2:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: unless otherwise specified, all limits apply for TA = TJ = 25°C; Boldface specifications
apply over the full operating temperature range of TA= TJ = -40°C to 125°C. Typical values are at +25°C. RT = 200k,
EN = 3.3V, VPP= +135V, VNN= -135V, VPF= +123V, VNF= -123V, VCC= +6.5V, VSS= -6.0V, VLL= +3.3V, VIN = +3.3V
unless otherwise specified.
Parameter
Sym.
Min.
Typ.
Max.
Units
Conditions
Time from SPI latch assert to
data valid
Refer to Figure 1-2
(Note 2)
tae
-
10
20
ns
Time from SPI latch to data
latch
Refer to Figure 1-2
(Note 2)
tak
tgk
tmn
trs
20
20
20
80
-
50
50
-
-
ns
ns
ns
ns
ns
Refer to Figure 1-2
(Note 2)
Time latch signal held high
Time latch signal held low
Refer to Figure 1-2
(Note 2)
50
-
Time between two data latch
events
Refer to Figure 1-2
(Note 2)
100
10
-
Propagation delay from data
register to output register
Refer to Figure 1-2
(Note 2)
tkv
20
Note 1: Recommended Operating Conditions: VIN=3.3V, VCC=+6.5V, VSS=-6.0V, VPP=+135V, VNN= -135V all
input pins =0V unless noted. TJ=25°C
2: Design guidance only.
3: Specification is obtained by characterization and is not 100% tested.
2021 Microchip Technology Inc.
DS20006518A-page 11
HV53001
TEMPERATURE SPECIFICATIONS
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Junction Temperature Range
Storage Temperature Range
TJ
-40
-65
—
—
+125
+150
°C
°C
TA
Package Thermal Resistance
Thermal Resistance, 105B-9x9 TFBGA
JA
—
38.1
—
°C/W
1.1
Timing Diagrams
FIGURE 1-1:
SPI and LATCHIN Timing Diagram
DS20006518A-page 12
2021 Microchip Technology Inc.
HV53001
tac
tab
LATCHIN
Register D
Register C
Register B
Register A
LATCHA
c
a
b
SPI buffer bit 127:96
SPI buffer bit 95:64
SPI buffer bit 63:32
SPI buffer bit 31:0
e
tae
g
k
tak
tgk
tmn
LATCHB
m
n
LATCHC
s
trs
LATCHD
r
Output
v
Reg A
Reg D
Reg D
Reg C
Reg C
Reg B
Reg B
tkv
Register
w
HV Output
Reg A
tkw
FIGURE 1-2:
LATCHA, B, C, D and High-Voltage Output Timing Diagram
FIGURE 1-3:
High-Voltage Output Test Pattern
2021 Microchip Technology Inc.
DS20006518A-page 13
HV53001
1.2
Typical Performance Curves
Note:
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 1-4:
Typical HV
output
FIGURE 1-7:
Typical HV
from 0V to
OUT
OUT
waveform V =135V V =-135V, Load = 100pF
135V, Load = 100pF
PP
NN
FIGURE 1-5:
Typical HV
from 135V to
FIGURE 1-8:
Typical HV
from 0V to
OUT
-
OUT
0V, Load = 100pF
135V, Load = 100pF
FIGURE 1-6:
Typical HV
from -135V
FIGURE 1-9:
Typ. HV
Rise Time
OUT
OUT
to 0V, Load = 100pF
Distribution, HV
from 0V to 90V, Load =
OUT
250pF
DS20006518A-page 14
2021 Microchip Technology Inc.
HV53001
Note:
The graphs and tables provided below are a statistical summary based on a limited number of samples and
are provided for informational purposes only. The performance characteristics listed herein are not tested
or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range
(e.g. outside specified power supply range) and therefore outside the warranted range.
FIGURE 1-10:
Typ. HV
Fall Time
FIGURE 1-13:
Typ. HV
Fall Time
OUT
OUT
Distribution, from 90V to 0V, Load = 250pF
Distribution, from 0V to -90V, Load = 250pF
FIGURE 1-11:
Typ. HV
Rise Time
FIGURE 1-14:
Typical VPPSENSE
OUT
Distribution, from -90V to 0V, Load = 250pF
Buffered Output, V =135V, V =-135V,
PP
NN
Load=100pF, 6.04ohm Sense Resistor, Four
Channels Active
FIGURE 1-12:
Typical VNNSENSE
buffered output, V =135V, V =-135V,
PP
NN
Load=100pF, 6.04ohm sense resistor, four
channels active
FIGURE 1-15:
Channel Delay
Typical HV
Channel-to-
OUT
2021 Microchip Technology Inc.
DS20006518A-page 15
HV53001
FIGURE 1-16:
Propagation Delay.
Typical LATCHA to HV
FIGURE 1-19:
Propagation Delay.
Typical LATCHB to HV
Typical LATCHD to HV
Typical Charge Pump
OUT
OUT
FIGURE 1-17:
Propagation Delay.
Typical LATCHC to HV
FIGURE 1-20:
Propagation Delay.
OUT
OUT
FIGURE 1-18:
Typical SDO output Rise
FIGURE 1-21:
Time and Fall Time.
Output Noise Ripple.
DS20006518A-page 16
2021 Microchip Technology Inc.
HV53001
FIGURE 1-22:
Typical Charge Pump
FIGURE 1-23:
Typical VSSPUL output
Output Voltage vs Output current V =3.3V.
waveform Io = -5mA.
IN
2021 Microchip Technology Inc.
DS20006518A-page 17
HV53001
2.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
Pin
PIN FUNCTION TABLE
Symbol
Description
E13
C13
L13
N13
C8
VPP
VPPO
VNN
Positive High-Voltage Supply
Positive High-Voltage Current Sense
Negative High-Voltage Supply
Negative High-Voltage Current Sense
Positive Low-Voltage Supply
Negative Low-Voltage Supply
VLL Logic Voltage
VNNO
VCC
C10
C7
VSS
VLL
D3, E3, H4-6,
HVGND
High-Voltage Ground
G5-6.E6, F6
G13
J13
N11
A13
C3
VPF
VNF
Positive floating voltage supply reference to VPP level
Negative floating voltage supply reference to VNN level
0.1uF cap across FILN and VNNO
FILN
FILP
0.1uF cap across FILP and VPPO
VPPSENSE Positive High-Voltage Sense Analog Output
VNNSENSE Negative High-Voltage Sense Analog Output
F3
E10
G3
VLDO
NC
LDO output pin
No Connection. (Do not connect. Keep the pin floating)
No Connection. (Do not connect. Keep the pin floating)
High-Voltage Output 0
H3
NC
A11
A9
HVOUT0
HVOUT
1
2
High-Voltage Output 1
A7
HVOUT
High-Voltage Output 2
A5
HVOUT3
High-Voltage Output 3
A3
HVOUT
4
5
High-Voltage Output 4
A1
HVOUT
High-Voltage Output 5
C1
HVOUT6
High-Voltage Output 6
E1
HVOUT
7
8
High-Voltage Output 7
G1
HVOUT
High-Voltage Output 8
J1
HVOUT9
High-Voltage Output 9
L1
HVOUT10 High-Voltage Output 10
HVOUT11 High-Voltage Output 11
HVOUT12 High-Voltage Output 12
HVOUT13 High-Voltage Output 13
HVOUT14 High-Voltage Output 14
HVOUT15 High-Voltage Output 15
N1
N3
N5
N7
N9
C5
SS
SPI Chip Select
SPI Data In
D5
SDI
DS20006518A-page 18
2021 Microchip Technology Inc.
HV53001
TABLE 2-1:
Pin
PIN FUNCTION TABLE (CONTINUED)
Symbol
Description
E5
F5
G4
F4
E4
D4
C4
H8
J8
SDO
SCK
SPI Data Out (for daisy chain)
SPI Clock
LATCHIN Latch SPI Data (SPI -> Latch A, B, C, D)
LATCHA
LATCHB
LATCHC
LATCHD
VIN
Latch A -> Output Register
Latch B -> Output Register
Latch C -> Output Register
Latch D -> Output Register
Input Voltage
VDD
Positive Low-Voltage Supply
Power Ground
K10,L10
PGND
AGND
CCP2N
CCP2P
CCP1N
CCP1P
TON
C9,F11
K11
L11
H11
J11
Analog Ground
Charge Pump 2 NEG
Charge Pump 2 POS
Charge Pump 1 NEG
Charge Pump 1 POS
TON pin
H9
J10
D11
E9
RT
RT pin
VBFB
VBOVP
REF
FB Bias
OVP Bias
E11
C11
F10
F9
Controller Voltage Reference
VSS Pulse Train
VSSPUL
TEMP
SHORT
SHTEN
SHDN
STDBY
EN
Temp Sensor Output
Short circuit indicator
Short circuit protection enable
Shutdown Mode
F8
C6
F7
Standby Mode
J9
DC/DC Enable
G7
G8
G9
G10
H10
G11
J7
SEQ3
SEQ2
SEQ1
SEQ0
TRIG
Power Sequence Channel 3
Power Sequence Channel 2
Power Sequence Channel 1
Power Sequence Channel 0
Power ON/OFF Sequence Trigger
Sequence timer. External capacitor to ground
Short Sense POS
CSEQ
SHTP
SHTN
OVPP
OVPN
FBP
H7
Short Sense NEG
D7
Over-voltage POS
D8
Over-voltage NEG
D9
Feedback POS
D10
FBN
Feedback NEG
2021 Microchip Technology Inc.
DS20006518A-page 19
HV53001
TABLE 2-1:
Pin
PIN FUNCTION TABLE (CONTINUED)
Symbol
Description
E8
E7
D6
NC
No Connection (Do not connect. Keep the pin floating)
Reserved Reserved pin. Connect to Ground.
Reserved Reserved pin. Connect to Ground.
J3-4, K3-4,L3-4
S
D
Source of Power FET
Drain of Power FET
J5-6, K5-9,L5-9
DS20006518A-page 20
2021 Microchip Technology Inc.
HV53001
The SS pin is a chip select function which is similar to
the enable function to guard the clock and data input
signal. The SCK contains the bus clock signal from the
host processor. The SDI and SDO are the data input
and data output pins of the SPI shift register buffer.
3.0
3.1
DEVICE DESCRIPTION
Serial Peripheral Interface
The SPI interface is used to transfer data of the chan-
nel settings from the host controller to the high-voltage
driver. The HV53001 operates as an SPI slave device
and receives 128 bits of data from the master device
(host controller). The HV53001 SPI interface is
designed to be compatible with all Microchip 8-bit, 16-
bit and 32-bit SPI data transmission formats. This SPI
interface has a 128-bit shift register buffer to store 128
bits of data.
SDI and SDO can be used to cascade multiple
HV53001 or HV53011 drivers together if only a single
SPI port is available. This SPI interface is compatible
with 3.3V logic input voltage with its maximum clock
frequency of 32 MHz.
The SPI shift register captures the data at the SDI
input in the rising edge of the SCK clock and pushes
out the data from the buffer to the SDO output in the
falling edge of the SCK clock. When the SPI bus is at
idle status, the SS pin stays in logic “1” and the SCK
clock is expected to stay at “0”.
FIGURE 3-1:
SPI Signal Diagram.
The bit order of the SDI data input is defined in the
following. The first and second data bits represent bit 1
and bit 0 of channel 15 in register D, respectively. The
third and fourth bits represent bit 1 and bit 0 of channel
14 in register D. This pattern is extended all the way to
channel 0. Hence, there are 32 data bits to control
register D to cover all sixteen channels.
The next 32 data bits are arranged in the same fashion
for register C. Similarly, the exact pattern repeats itself
for register B and A. Since each register (A, B, C and
D) contains 32 bits of data, the SPI shift register buffer
is 128 bits long.
Bit 1 of channel 15 in register D is defined as the MSb
(Most Significant bit) and bit 0 of channel 0 in register
A as the LSb (Least Significant bit) in this SPI shift
register buffer definition.
128 clock cycle
SCK
SDI
* * * * * * * * * * * * * * * * * *
MSb… Data < D_CH15[1], D_CH15[0], D_CH14[1], ……. A_CH0[1], A_CH0[0] > … LSb
For example, D_CH15[1] = Setting of Register D, Channel 15, Bit 1
FIGURE 3-2:
SPI Bit Pattern Diagram.
2021 Microchip Technology Inc.
DS20006518A-page 21
HV53001
The following table shows the summary of the SPI shift register buffer.
TABLE 3-1:
Sym
REGISTER LEGEND
Description
Sym
Description
Cleared by Hardware only
R
W
U
P
Readable bit
Writable bit
HC
HS
1
Set by Hardware only
Bit is set at Reset
Unimplemented bit, read as ‘0’
Programmable bit
Settable bit
0
Bit is cleared at Reset
Bit is unknown at Reset
S
x
C
Clearable bit
Example: R/W - 0 indicates the bit is both readable or writable, and reads ‘0’ after a Reset.
TABLE 3-2: SPI_SR 128-BIT BUFFER SUMMARY
Register
Name
Bit Range
Bit
Bit
Bit
101
Bit
Bit
99
Bit
Bit
97
Bit
127/119/111/ 126/118/110/ 125/117/109/ 124/116/108/ 123/115/107/ 122/114/106/ 121/113/105/ 120/112/104/
103
102
100
98
96
LATCHD
<127:120>
<119:112>
<111:104>
<103:96>
Bit Range
CH15<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH14<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH13<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH12<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
Register
Name
Bit
95/87/79/71
Bit
Bit
93/85/77/69
Bit
Bit
91/83/75/67
Bit
Bit
89/81/73/65
Bit
94/86/78/70
92/84/76/68
90/82/74/66
88/80/72/64
LATCHC
<95:88>
<87:80>
<79:72>
<71:64>
Bit Range
CH15<1:0>
CH14<1:0>
CH13<1:0>
CH12<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
Register
Name
Bit
63/55/47/39
Bit
Bit
61/53/45/37
Bit
Bit
59/51/43/35
Bit
Bit
57/49/41/33
Bit
62/54/46/38
60/52/44/36
58/50/42/34
56/48/40/32
LATCHB
<63:56>
<55:48>
<47:40>
<39:32>
Bit Range
CH15<1:0>
CH14<1:0>
CH13<1:0>
CH12<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
Register
Name
Bit
31/23/15/7
Bit
Bit
29/21/13/5
Bit
Bit
27/19/11/3
Bit
Bit
25/17/9/1
Bit
30/22/14/6
28/20/12/4
26/18/10/2
24/16/8/0
LATCHA
<31:24>
<23:16>
<15:8>
<7:0>
CH15<1:0>
CH14<1:0>
CH13<1:0>
CH12<1:0>
CH11<1:0>
CH7<1:0>
CH3<1:0>
CH10<1:0>
CH6<1:0>
CH2<1:0>
CH9<1:0>
CH5<1:0>
CH1<1:0>
CH8<1:0>
CH4<1:0>
CH0<1:0>
updated using one of the latch signals, the output will
go to a not driven state temporarily to avoid shoot-
through.
3.2
Quad-Latched Two-Bit per
Channel Architecture
In the Quad-Latched 2-bit per channel architecture,
each channel is controlled by a 2-bit encoding for each
of the four possible states: “00” = (Hi-Z) high imped-
The data in these four latched arrays can be updated
by the SPI shift register buffer. The 128 bits of data is
first transmitted from the host process to this device
via the SPI interface. The data format has been dis-
cussed in the previous section. After the 128 bits
transaction completes, the data will stay in the SPI
shift register buffer. The user then sends an activation
signal at the LATCHIN pin to initiate the transfer of the
data from the SPI shift register to the four 32-bit
registers (A, B, C and D).
ance, “01” = pull-down to VNN, “10” = pull-up to VPP
,
“11” = driven to ground. Since there are 16 channels
on each HV53001 device, a 32-bit output control
register is required.
Four separate latched arrays (A, B, C and D) hold four
possible 32-bit output configurations. The data is
loaded from the arrays into the output control register
by four separate external control signals (LATCHA, B,
C, D). When the output control register is being
DS20006518A-page 22
2021 Microchip Technology Inc.
HV53001
When the application requires more output channels,
the user can cascade more driver devices in a daisy
chain configuration. The SDO pin is used to pass the
data from the SPI shift register buffer to the cascaded
driver.
TABLE 3-1:
2-BIT CONTROL AND
OUTPUT VOLTAGE LOGIC
TABLE
CONTROL BITS
HVOUT OUTPUT
The SPI signal pins (SCK, SS, SDI and SDO) are used
to control the data flow of the SPI shift register buffer.
The five latch control signals (LATCHIN, LATCHA,
LATCHB, LATCHC and LATCHD) are used to control
the data selection of the high-voltage output from the
four 32-bit registers. The SPI interface and latch
functions are two independent operation blocks.
Bit 1
Bit 0
0
0
1
1
0
1
0
1
High impedance (Hi-Z)
Driven Low (VNN
)
Driven High (VPP
)
Driven to Ground (0V)
To achieve some power savings when idling for a
period of time, a shutdown pin is available to reduce the
quiescent current draw as much as possible.
SS
SCK
Clock Control
SDO
SDI
SPI 128 bits shift register buffer
32
32
32
32
LATCHIN
32-bit LATCHA
32
32-bit LATCHB
32
32-bit LATCHC
32
32-bit LATCHD
32
LATCHA,B,C,D
SWITCHES
4
32-bit OUTPUT CONTROL REGISTER
SHDN
FIGURE 3-3:
Quad-Latched Two-Bit per Channel Architecture.
TABLE 3-3:
LATCHIN
↓
QUAD-LATCHED TWO-BIT LOGIC STATE TABLE
LATCHA
LATCHB
LATCHC
LATCHD
Description
X
X
X
X
SPI bit[127:96] into Latch Register D
SPI bit[95:64] into Latch Register C
SPI bit[63:32] into Latch Register B
SPI bit[31:0] into Latch Register A
X*
X*
X*
X*
↓
X
↓
X
X
↓
X
X
X
↓
Register A to output
Register B to output
Register C to output
Register D to output
X
X
X
X
X
X
Note:
* = LATCHX should be delayed appropriately if a register update from LATCHIN is still in progress.
↓ = Negative edge-triggered
X = Don’t care
2021 Microchip Technology Inc.
DS20006518A-page 23
HV53001
3.3
Driver Shutdown Mode
3.6
Negative Charge Pump
When the shutdown (SHDN) pin is at logic “1”, any
unnecessary circuit in the line driver is disabled to min-
imize the power consumption. It includes the level
translator, bias current, voltage reference, driver out-
put, SPI interface and combinational logic. During
shutdown, the ILL quiescent current is less than
100 A. The system response time is less than 1 ms to
switch between shutdown and active states when a
new signal is asserted at the shutdown pin.
A continuous pulse train is created at the VSSPUL
output and is used in conjunction with a few external
components to create a negative charge pump circuit.
The pulse train is a 0 to 6.5V square wave with a fixed
oscillation frequency. This -6.0V negative low supply
voltage is generated at the output of the external circu-
ity and is capable of supplying a minimum of 5 mA.
This negative supply provides enough power to
operate the high-voltage driver device.
It is recommended to use 10 F 25V X5R 0805
ceramic capacitors and B0530WS 400 mV 500 mA
30V Schottky diodes for this circuit.
3.4
Driver Power On Reset
The Power-on Reset function resets all high-voltage
HVOUT output to high impedance when the device is
initially powered on. It also resets and clears the SPI
buffer registers, registers A, B, C and D, to logic “0”.
Note:
Please consider the operating temperature
for component selection.
3.5
Positive Charge Pump Regulator
The device is targeted to operate with a standard bat-
tery voltage range of 2.7V to 5.5V. An internal 3X
charge pump converter is integrated to generate a reg-
ulated output at high-voltage level. This regulated out-
put supply rail powers the gate driver to drive the
power MOSFET transistor.
It is recommended to use 1 F 16V X7R 0603 ceramic
capacitors for the two CCP capacitors and a 10 F
25V X5R 0805 ceramic capacitor for the output
storage capacitor.
FIGURE 3-6:
Converter
Negative Charge Pump
Note:
Please consider the operating temperature
for component selection.
3.7
Standby Mode
Standby mode is used to guard the PWM pulses from
the DC/DC controller to the power FET. It momentarily
disables the gate driver of the power FET to minimize
the noise level so that the output current sensor can
measure the output current precisely. While the device
is in Standby mode, all other circuits are expected to
be in their operating condition.
3.8
Enable Function
FIGURE 3-4:
Positive Charge Pump
Converter Conceptual Diagram
The enable function is used to switch the DC/DC con-
troller on/off completely. When it is set to Off mode, all
internal circuits of the DC/DC converter are turned off
and minimum current is drawn. When the DC/DC con-
verter is disabled, the boost converter, charge pump
converter and linear regulator shut off.
+6.5V to high voltage driver
2.7 to
5.5V
VDD
CCP1+/-
CCP2+/-
VIN
The SHDN and EN are two separate controls. SHDN
is for the high-voltage driver, and EN is for the DC/DC
converter.
HV53001
Positive Charge Pump Converter
FIGURE 3-5:
HV53001 Positive Charge
Pump Connections
DS20006518A-page 24
2021 Microchip Technology Inc.
HV53001
3.9
Power-On/Off Sequence Control
The HV53001 DC/DC converter generates multiple
rails to power the high-voltage driver IC. The power-on
sequence is important to the high-voltage IC because
any incorrect power-on/off sequence may cause
damage to the high-voltage driver IC.
A sequence control block is included in this device to
avoid an incorrect sequence caused by user error
which could damage the driver IC.
When a single pulse is asserted at the TRIG pin, the
four sequence control outputs generate a logic “1” in
sequential order. First, a logic “1” will appear in SEQ0,
and then in SEQ1, SEQ2 and SEQ3. When a second
pulse is asserted at the TRIG pin, a logic “0” appears
in SEQ3, SEQ2, SEQ1 and SEQ0 sequentially in
reverse order. The timing between each is controlled
by an external capacitor connected at the CSEQ pin.
The sequence switch time period is calculated in the
following equation.
FIGURE 3-8:
State Diagram.
Sequence On/Off Control
+135V
Logic voltage supply
VPP
SEQY
Tseq = 2 x ln(2) x R x CSEQ where R = 100 k
The four sequence logic output signals, SEQ[3:0], can
be used to control the enable function of the power
module or external analog power switches to control
the supply voltage rails.
SEQX
VNN
-135V
.
FIGURE 3-9:
Example of Power Switch
Circuit
FIGURE 3-7:
Power-On/Off Sequence
Control
TABLE 3-2:
Steps
ACCEPTABLE POWER-ON SEQUENCES
Description
1
2
3
4
5
6
Connect ground.
Keep shutdown pin to low.
Set all driver inputs to low.
Apply VIN.
Set all converter inputs to a known state.
The power-on sequence will enable supplies in this sequence: VLL, VNN, VNF, VSS, VCC, VPF and
VPP
Set all inputs to a known state.
.
7
2021 Microchip Technology Inc.
DS20006518A-page 25
HV53001
TABLE 3-3:
Steps
ACCEPTABLE POWER-OFF SEQUENCES
Description
1
2
Set all inputs and shutdown pin to low.
The power-off sequence will disable supplies in this sequence: VPP, VPF, VCC, VSS, VNF, VNN and
VLL
.
3
4
Disconnect VIN.
Disconnect ground
The following schematic diagram shows how this
DC/DC converter can be configured. VPP, VPF, VNN and
VNF represent all output rails. VIN is the main supply rail
to the DC/DC converter.
3.10 Built-in DC/DC Converter
A hysteretic step-up DC/DC converter is integrated in
this driver IC to generate two high-voltage rails, one
positive and one negative. In normal operation, this
converter operates at a fixed duty cycle and frequency.
The controller monitors both positive and negative
voltage rails alternately to regulate the output voltage.
The positive supply feedback input is a typical DC/DC
feedback which monitors the feedback voltage from a
resistor divider referenced to ground. When the sens-
ing voltage is higher than the internal reference volt-
age, it deactivates the pulse in the next cycle. When the
sensing voltage is lower, it activates the pulse.
For the negative supply feedback input, the controller
provides a low DC bias voltage to map the feedback
voltage above ground because the controller is pow-
ered by a low-voltage positive power rail. Hence, the
negative supply feedback voltage is referenced to the
bias voltage VBFB pin via the resistor divider network.
The negative supply feedback path works differently
from the positive supply feedback path since it senses
the negative voltage. When the sensing voltage is
higher than the internal reference voltage, it activates
the pulse in the next cycle. When the sensing voltage
is lower, it deactivates the pulse.
Based on the operation described above, the controller
basically regulates the mid-point of the VPP and VNN
voltage rails. As long as the two transformers are
closely matched, the two high-voltage outputs can be
coupled within a few percentage of each other. For
matching the transformers, their absolute values are
not important. The important factor is the difference
between the two transformers. Since both transformers
are built the same way, their secondary effects are very
similar. The major factor is their primary parameter,
magnetizing inductance.
In addition to the two extreme high-voltage rails, the
driver requires two floating voltage rails. Both floating
supplies are referenced to one of the extreme high-volt-
age outputs. These two floating supply rails are created
using the multi-winding transformer and two 12V regu-
lators. The positive voltage rail requires a negative 12V
regulator referenced to VPP. The negative voltage rail
uses a positive 12V regulator reference to VNN
.
DS20006518A-page 26
2021 Microchip Technology Inc.
HV53001
Coilcraft
VIN
WA8775-BE
4.49
1
VPP
VPF
0.58
GND
Vi
Vo
Neg LDO
4.49
0.58
POWER
MOSFET
D
VIN
1
VNN
VNF
S
GND
SHTP
Vi
Vo
Pos LDO
HV53001
Coilcraft
WA8775-BE
SHTN
DC/DC
converter
FBP
FBN
VPP
VNN
VBFB
FIGURE 3-10:
3.10.1
HV53001 DC-DC converter configuration
SETTING
fSW = 1/ (C * RT) where C = 12pF
OVERVOLTAGE PROTECTION
T
ON
The TON pin is used to set the duty cycle of the DC-DC
converter. An internal ramp generator in the DC-DC
converter creates a ramp between 0 and 3.75V. A low-
to-high transition starts at 0V. When this ramp voltage
reaches the same voltage level presented at the TON
pin, it triggers the internal comparator and sets the
pulse high-to-low transition. The voltage present at the
TON pin sets the duty cycle of the pulses.
3.10.3
Overvoltage protection is to monitor the output voltage
of the boost converter. If the output voltage of the
DC/DC converter reaches above the threshold volt-
age, it will pause the DC/DC converter operation for
safety purpose.
An internal lower bound and upper bound of the duty
cycle are set to avoid any malfunction. The user can
select any TON voltage between 0 and 3V.
The DC/DC stays in Standby mode until the monitored
voltage drops below the threshold. Then, the DC/DC
controller exits Standby mode and resumes normal
operation.
For example, the duty cycle is set to 80% for
VTON = 3V.
The overvoltage protection is intended to guard any
momentarily overvoltage condition for a short period of
time and does not require any user interaction. The
threshold voltage can be set by the external resistor
network.
VTON
DutyCycle = -------------
3.75
The OVPP and OVPN pins are used to monitor the
feedback voltage from the VPP and VNN supplies via
two sets of voltage divider networks. The sampled
voltage from VPP and VNN are compared with the inter-
3.10.2
CONVERTER SWITCHING
FREQUENCY
The converter switching frequency is set by an external
resistor RT. The frequency is set by the following equa-
tion.
2021 Microchip Technology Inc.
DS20006518A-page 27
HV53001
nal reference voltage. If the sampled VPP or VNN volt-
age is above the threshold, the controller will turn off
the pulses until VPP and VNN drop below the threshold.
The amplifier output accuracy is less important. Both
VPPSENSE and VNNSENSE outputs have a tolerance
of ±14%.
3.10.4
SHORT CIRCUIT PROTECTION
Sense
A short circuit at the flyback transformer output may
cause damage to the power supply circuit and gener-
ate a lot of heat. This may create a hazardous situa-
tion for the end user. A short circuit protection scheme
is implemented in the DC/DC controller by monitoring
the current of the power FET transistor.
Resistor
+135V
VPPO
VPP
V+
V-
Av
HVOUT
HVOUT
0
1
Difference
Amplifier
x3.1
This DC/DC controller is running in Discontinuous
Conduction mode (DCM). When a short circuit situa-
tion happens, the converter goes into Continuous
Conduction mode (CCM). This causes the FET current
at turn on to be non-zero. The controller detects this
and shuts down the pulse to the power FET and sets a
logic '1' at the SHORT pin. The user toggles the EN
signal to restart the converter.
VPPSENSE
(Reference to GND)
HVOUT14
HVOUT15
The short circuit protection function can be bypassed
by inserting a logic “0” to the short circuit enable pin
(SHTEN).
FIGURE 3-11:
Current Sensing Topology.
3.11 Driver Output Current Sensing
Some system designs require a load sensing function
to determine the size or change of the capacitive load.
One simple scheme is to place a series current sensing
resistor on the power supply rail and measure the volt-
age drop across this resistor. This solution is very effec-
tive if the voltage drop is small enough not to affect the
operation of the system.
The HV53001 driver IC provides this function and the
user can monitor the supply current flowing through
both high-voltage positive and negative supplies. Two
external current sensing resistors are connected to the
VPP and VNN supply rails, respectively, as high side
current sensing. The voltage drop across these resis-
tors are connected to two pin pairs, VPP-VPPO and VNN
-
VNNO. Since these voltage drops are referenced to VPP
and VNN supply rails, it is not practical for a low-voltage
ADC to measure these voltages. Hence, two internal
difference amplifiers in the driver IC convert these volt-
age drops to near ground potential.
The difference amplifier accepts a maximum input volt-
age of 1V. The amplifier gain of 3.1 amplifies this input
and sends the output to the VPPSENSE and VNN-
SENSE pins. These amplifiers are designed using
high-voltage and high value resistors to minimize its
power consumption. These amplifier outputs are high
impedance in nature, so an external high bandwidth
(200MHz) unity gain buffer is highly recommended.
The high bandwidth is needed to capture the fast
current pulse during the transition.
The user selects the value of the sensing resistor to fit
the system requirement. The speed of difference ampli-
fier is a high priority parameter because the charge or
discharge current appears for a short period of time.
DS20006518A-page 28
2021 Microchip Technology Inc.
HV53001
4.0
4.1
PACKAGING INFORMATION
Package Marking Information
105-Ball TFBGA(9x9x1.2 mm)
Example
HV53001
1508256
Legend: XX...X Product Code or Customer-specific information
Y
YY
WW
NNN
e8
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e8
)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
2021 Microchip Technology Inc.
DS20006518A-page 29
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2021 Microchip Technology Inc.
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2021 Microchip Technology Inc.
DS20006518A-page 31
HV53001
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DS20006518A-page 32
2021 Microchip Technology Inc.
HV53001
NOTES:
2021 Microchip Technology Inc.
DS20006518A-page 33
HV53001
DS20006518A-page 34
2021 Microchip Technology Inc.
HV53001
APPENDIX A: REVISION HISTORY
Revision A (March 2021)
• Original Release of this Document.
2021 Microchip Technology Inc.
DS20006518A-page 35
HV53001
NOTES:
DS20006518A-page 36
2021 Microchip Technology Inc.
HV53001
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
X-
X
/XXX
a)
HV53001-E/KWX:16-Channel, ±135V Push-Pull
Driver with RTZ, Current Sensor
and Built-in Boost Converter. Thin
Fine Pitch Ball Grid Array, 105-Ball
TFBGA (9 x 9 x 1.2mm) Package,
260/Tray
Media Type Temperature
Tape and Reel Range
Package
Device:
HV53001: 16-Channel, +/-135V Push-Pull Driver with RTZ,
Current Sensor and Built-in Boost Converter
b)
HV53001T-E/KWX:16-Channel, ±135V Push-Pull
Driver with RTZ, Current Sensor
and Built-in Boost Converter.
Thin Fine Pitch Ball Grid Array,
105-Ball TFBGA (9 x 9 x 1.2mm)
Package, 1000/Tape & Reel
Media Type:
blank = 260/Tray for KWX Package
T
= 1000/Reel for KWX Package
Temperature
Range:
E
=-40°C to +125°C (Extended) RoHS Compliant
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This identifier
is used for ordering purposes and is not
printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
Package:
KWX =Thin Fine Pitch Ball Grid Array
105-Ball TFBGA (9 x 9 x 1.2 mm)
2021 Microchip Technology Inc.
DS20006518A-page 37
HV53001
NOTES:
DS20006518A-page 38
2021 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip
devices. We believe that these methods require using the Microchip products in a manner outside the operating specifications
contained in Microchip's Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished
without violating Microchip's intellectual property rights.
•
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole
purpose of designing with and using Microchip products. Infor-
mation regarding device applications and the like is provided
only for your convenience and may be superseded by updates.
It is your responsibility to ensure that your application meets
with your specifications.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A. and
other countries.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WAR-
RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NON-
INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
PARTICULAR PURPOSE OR WARRANTIES RELATED TO
ITS CONDITION, QUALITY, OR PERFORMANCE.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions
Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight
Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-
Wire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDI-
RECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUEN-
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WHATSOEVER RELATED TO THE INFORMATION OR ITS
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OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF
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the buyer agrees to defend, indemnify and hold harmless
Microchip from any and all damages, claims, suits, or expenses
resulting from such use. No licenses are conveyed, implicitly or
otherwise, under any Microchip intellectual property rights
unless otherwise stated.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,
BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive,
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, Espresso T1S,
EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP,
INICnet, Intelligent Paralleling, Inter-Chip Connectivity,
JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi,
MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE,
Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O,
simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI,
SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total
Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY,
ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2021, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-7936-9
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2021 Microchip Technology Inc.
DS20006518A-page 39
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
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Tel: 61-2-9868-6733
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Tel: 91-80-3090-4444
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Web Address:
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Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
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Tel: 408-735-9110
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UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006518A-page 40
2021 Microchip Technology Inc.
02/28/20
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