IS2023S-203-TRAY [MICROCHIP]
Telecom Circuit, 1-Func, CMOS;
| 型号： | IS2023S-203-TRAY |
| 厂家： | 
MICROCHIP |
| 描述： | Telecom Circuit, 1-Func, CMOS 电信 电信集成电路 |
| 文件： | 总57页 (文件大小：2730K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IS2020/21/23/25 SoC
®
Bluetooth 4.1 Stereo Audio SOC
Packet loss concealment
Features
Build-in four languages (Chinese/ English/
System Specification
Compliant with Bluetooth Specification v.4.1
(EDR) in 2.4 GHz ISM band
It supports following profiles :
- HFP 1.6
Spanish/ French) voice prompts and 20 events
for each one (This function can be set up in
“IS20XXS_UI” tool.)
Support SCMS-T
- HSP 1.1
Audio Codec
- A2DP 1.2
- AVRCP 1.5
- SPP 1.0
- PBAP 1.0
20 bit DAC and 16 bit ADC codec
98dB SNR DAC playback
Built-in 2 channel 2.3W class-D amplifier for a
4Ω speaker (for IS2025S only)
Baseband Hardware
16MHz main clock input
Peripherals
Built-in internal ROM for program memory
Built-in Lithium-ion battery charger (up to
350mA)
Support to connect to two hosts ( phones,
tablets…) with HFP or A2DP profiles
simultaneously
Integrate 3V, 1.8V configurable switching
regulator and LDO
Adaptive Frequency Hopping (AFH) avoids
occupied RF channels
Built-in ADC for battery monitor and voltage
sense.
Fast Connection supported
A line-in port for external audio input
Two LED drivers
RF Hardware
Fully Bluetooth 4.1 (EDR) system in 2.4 GHz
ISM band.
Flexible HCI interface
High speed HCI-UART (Universal
Asynchronous Receiver Transmitter) interface
(up to 921600bps)
Combined TX/RX RF terminal simplifies
external matching and reduces external
antenna switches.
Max. +4dBm output power with 20 dB level
control from register control.
Package
5x6.5mm2 48QFN package (IS2021S)
7x7mm2 56QFN package (IS2020S, IS2023S)
8x8mm2 68QFN package (IS2025S)
Built-in T/R switch for Class 2/3 application
To avoid temperature variation, temperature
sensor with temperature calibration is utilized
into bias current and gain control.
Fully integrated synthesizer has been created.
There requires no external VCO, varactor
diode, resonator and loop filter.
Crystal oscillation with built-in digital trimming
for temperature/process variations.
Description
Stereo Audio Chip is a compact, highly
integrated, CMOS single-chip RF and
baseband IC for Bluetooth v4.1 with Enhanced
Data Rate 2.4GHz applications. This chip is
fully compliant with Bluetooth specification and
completely backward-compatible with Bluetooth
3.0, 2.0 or 1.2 systems.
Audio processor
Support 64 kb/s A-Law or -Law PCM format,
or CVSD (Continuous Variable Slope Delta
Modulation) for SCO channel operation.
It incorporates Bluetooth 1M/2M/3Mbps RF,
single-cycle 8bit MCU, TX/RX modem, 5-port
memory controller, task/hopping controller,
Noise suppression
Echo suppression
SBC and optional AAC decoding
Page 1
Stereo Audio SoC
components required for portable devices, a
battery voltage sensor, battery charger, a
switching regulator and LDO are integrated to
reduce system BOM cost for various Bluetooth
applications.
UART interface, and MICROCHIP’s own
Bluetooth software stack to achieve the
required BT v4.1 with EDR functions.
To provide the superior audio and voice
quality, it also integrates a DSP co-processor, a
PLL, and a CODEC dedicated for voice and
audio applications.
As the market of portable/wireless speakers
demand is increasing, a stereo 2 channels
2.3W class-D amplifier which provides up to
100dB SNR is also built-in to reduce BOM cost
and PCB area.
For voice, not only basic CVSD encoding and
decoding but also enhanced noise reduction
and echo cancellation are implemented by the
built-in DSP to achieve better quality in both
sending and receiving sides. For the enhanced
audio applications, SBC/AAC_LC decoding
functions can be also carried out by DSP to
satisfy Bluetooth A2DP requirements.
Applications
Stereo headsets
Portable speakerphones
In addition, to minimize the external
Page 2
Stereo Audio SoC
Table of Contents
1.0 DEVICE OVERVIEW ...................................................................................................................................4
2.0 KEY FEATURES TABLE..............................................................................................................................5
3.0 PIN DESCRIPTION AND POWER SUPPLY ...............................................................................................6
4.0 TRANSCEIVER..........................................................................................................................................19
5.0 MICROPROCESSOR ................................................................................................................................20
6.0 AUDIO ........................................................................................................................................................21
7.0 POWER MANAGEMENT UNIT..................................................................................................................23
8.0 GENERAL PURPOSE IOs.........................................................................................................................25
9.0 OPERATION WITH EXTERNAL MCU.......................................................................................................26
10.0 I2S APPLICATION....................................................................................................................................31
11.0 ANTENNA PLACEMENT RULE ..............................................................................................................33
12.0 SPECIFICATIONS ...................................................................................................................................34
13.0 REFERENCE CIRCUIT............................................................................................................................41
14.0 PACKAGE INFORMATION......................................................................................................................46
15.0 REFLOW PROFILE AND STORAGE CINDITION...................................................................................54
Abbreviations List:
HFP: Hands-free Profile
AVRCP: Audio Video Remote Control Profile
A2DP: Advanced Audio Distribution Profile
PBAP: Phone Book Access Profile
HSP: Headset Profile
SPP: Serial Port Profile
NFC: Near Field Communication
CDA: Class D Amplifier
SCMS-T: Serial Copy Management System
Page 3
Stereo Audio SoC
1.0 DEVICE OVERVIEW
The stereo audio chip series include IS2020S, IS2021S, IS2023S, and IS2025S chip. The chip integrates
Bluetooth 4.1 radio transceiver, PMU, DSP and 2-channel CDA (Class D Amplifier). Figure 1-1 shows the
application block diagram.
FIGURE 1-1: APPLICATION BLOCK DIAGRAM
Antenna
IS20XX
2W
Stereo Class-D
AMP
BTv4.1+EDR
Transceiver
DSP
Speaker
24-bit DSP Core
16 M Hz
Crystal
Classic RF
158KB ROM
88KB RAM
I2S
EXT DSP
Audio Codec
Digital Core
(Digital signal for IS2023S only)
RF Controller
MAC
MODEM
Speaker
MCU
8051
PMU
2-Channel DAC
2-Channel ADC
Li-Ion
BAT
MIC1
BAT Charger
44KB RAM
448KB ROM
16KB patch RAM
Power Switch
1.8V BUCK
MIC2
(For IS2020/2025 only)
3.0V LDO*2
LED Driver *2
AUX_IN
(analog signal)
I2C
IO Port 0~3
(GPIOs or H/W)
LED
EEPROM
FIGURE 1-2: INTERFACE BETWEEN MCU AND IS20XX CHIP
MCU_
WAKEUP
P0_0
UART_RX
HCI_TXD
MCU
IS20XXS
UART_TX
HCI_RXD
BT_
WAKEUP
PWR
Page 4
Stereo Audio SoC
2.0 KEY FEATURES TABLE
Feature
Chip
IS2020S
IS2021S
Headset
IS2023S
IS2025S
Speaker
Headset /
Speaker
I2S Speaker
Application
Stereo
56
Stereo
48
Stereo
56
Stereo
68
Stereo/Mono
Pin count
Dimension (mm2)
7X7
5X6.5
7X7
8X8
2-ch
-98
2-ch
-98
X
X
2-ch
-98
Audio DAC output
DAC (single-end) SNR@2.8V (dB)
DAC (cap-less) SNR@2.8V (dB)
ADC SNR @2.8V (dB)
I2S digital interface
Analog Aux- in
X
-90
-96
-96
-96
-90
-90
-90
X
X
X
X
1
2
1
2
Mono MIC
X
X
2
X
X
2
Support external audio AMP
Build-in Class-D amplifier
UART
X
2
2-ch
2
LED Driver
Internal DC-DC step-down
regulator
DC 5V Adaptor Input
9
8
X
6
Battery Charger (350mA max)
10
IO Pin for Application
6
6
6
Button support
Support NFC application
X
Voice prompt
Multi-tone
Internal DSP sound effect
Profile
HFP
1.6
1.5
1.2
1.0
1.1
1.0
X
1.6
1.5
1.6
1.5
1.2
1.0
1.1
1.0
X
1.6
1.5
1.2
1.0
1.1
1.0
X
AVRCP
A2DP
PBAP
HSP
1.2
1.0
1.1
1.0
SPP
Build-in EEPROM
Note: “” means support the feature.
(128k)
Page 5
Stereo Audio SoC
“X” means no support the feature.
3.0 PIN DESCRIPTION AND POWER SUPPLY
3.1PIN ASSIGNMENT
TABLE 3-1: IS2020S PIN DESCRIPTION
Pin No.
Pin type
Name
VCOM
MICN2
MICP2
MICN1
MICP1
MIC_BIAS
AIR
Description
1
2
3
4
5
6
7
8
9
P
I
Internal biasing voltage for CODEC
Mic 2 mono differential analog negative input
Mic 2 mono differential analog positive input
Mic 1 mono differential analog negative input
Mic 1 mono differential analog positive input
Electric microphone biasing voltage
I
I
I
P
I
R-channel single-ended analog inputs
I
AIL
L-channel single-ended analog inputs
P
VDD_CORE
Core 1.2V power input; Connect to CLDO_O pin
IO pin, default pull-high input
EEPROM clock SCL
IO pin, default pull-high input
EEPROM data SDA
10
11
O
P1_2
P1_3
I/O
12
13
I
RST_N
System Reset Pin, active when rising edge.
P
VDD_IO
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
IO pin, default pull-high input (Note 1)
1. FWD key when class 2 RF (default), active low.
2. Class1 TX Control signal of external RF T/R switch, active high.
IO pin, default pull-high input
14
15
I/O
I
P0_1
P2_4
System Configuration,
Page 6
Stereo Audio SoC
Pin No.
Pin type
Name
Description
L: Boot Mode with P2_0 low combination
Pin No.
Pin type
Name
Description
IO pin, default pull-high input. (Note 1)
16
I/O
P0_4
1. NFC detection pin, active low.
2. Out_Ind_0
IO pin, default pull-high input (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
17
I/O
P1_5
3. Slide Switch Detector, active low.
4. Buzzer Signal Output
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
I
HCI_RXD
HCI_TXD
HCI-UART RX data
HCI-UART TX data
O
P
CODEC_VO 3.1V LDO output for CODEC power
P
P
LDO31_VIN 3.1V LDO input; Connect to SYS_PWR pin
LDO31_VO
ADAP_IN
BAT_IN
NC
3.1V LDO output
P
5V power adaptor input
P
-
3.3V~4.2V Li-Ion battery input
No Connection
P
P
P
P
P
I
SAR_VDD
SYS_PWR
BK_VDD
BK_LX
SAR 1.8V input; Connect to BK_O pin
Power Output which come from BAT_IN or ADAP_IN
1.8V buck VDD Power Input; Connect to SYS_PWR pin
1.8V buck pin for switch
BK_O
1.8V buck feedback input
PWR
Multi-Function Push Button and power on key
LED Driver 2
I
LED2
I
LED1
LED Driver 1
IO pin, default pull-high input (Note 1)
1. Slide Switch Detector, active low.
2. UART TX_IND, active low.
34
I/O
P0_0
IO pin, default pull-high input (Note 1)
1. REV key (default), active low.
2. Buzzer Signal Output
35
36
I/O
I
P0_3
EAN
3. Out_Ind_1
4. Class1 RX Control signal of external RF T/R switch, active high.
Embedded ROM/External Flash enable
H: Embedded; L: External Flash
37
38
39
40
41
P
P
P
P
P
CLDO_O
PMIC_IN
RFLDO_O
VBG
1.2V core LDO output
PMU blocks power input; Connect to BK_O pin
1.28V RF LDO output
Bandgap output reference for decoupling interference
ULPC_VSUS ULPC 1.2V output power.
Page 7
Stereo Audio SoC
Pin No.
42
Pin type
Name
XO_N
Description
I
I
16MHz Crystal input negative
16MHz Crystal input positive
43
XO_P
44
P
VCC_RF
RF power input (1.28V) for both synthesizer and TX/RX block
Pin No.
Pin type
Name
Description
45
I/O
RTX
RF RTX path
IO pin, default pull-high input (Note 1)
Play/Pause key (default), active low.
IO pin, default pull-high input
46
I
P0_2
47
I
P2_0
System Configuration,
H: Application L: Baseband(IBDK Mode)
IO pin, default pull-high input (Note 1)
Volume up key (default), active low.
IO pin, default pull-high input (Note 1)
Line-in Detector (default), active low.
IO pin, default pull-high input (Note 1)
Volume down (default), active low.
48
49
50
I
I
I
P2_7
P3_0
P0_5
51
52
P
VDD_IO
AOHPR
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
R-channel analog headphone output
O
Positive power supply dedicated to CODEC output amplifiers; Connect to
CODEC_VO pin
53
P
VDDAO
54
55
O
O
AOHPM
AOHPL
Headphone common mode output/sense input.
L-channel analog headphone output
Positive power supply/reference voltage for CODEC; Connect to
CODEC_VO pin
56
57
P
P
VDDA
EP
Exposed pad as ground
* I: signal input pin
* O: signal output pin
* I/O: signal input/output pin
* P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
Page 8
Stereo Audio SoC
TABLE 3-2: IS2021S PIN DESCRIPTION
Pin No.
Pin type
Name
AOHPM
AOHPL
Description
1
2
O
O
Headphone common mode output/sense input.
L-channel analog headphone output
Positive power supply/reference voltage for CODEC; Connect to
CODEC_VO pin
3
P
VDDA
4
5
6
7
P
I
VCOM
MICN1
Internal biasing voltage for CODEC
Mic 1 mono differential analog negative input
Mic 1 mono differential analog positive input
Electric microphone biasing voltage
I
MICP1
P
MIC_BIAS
IO pin, default pull-high input
EEPROM data SDA
8
9
I/O
I
P1_3
RST_N
System Reset Pin, active when rising edge.
IO pin, default pull-high input (Note 1)
10
11
12
I/O
P
P0_1
VDD_IO
P0_4
1. FWD key when class 2 RF, active low.
2. Class1 TX Control signal of external RF T/R switch, active high.
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
IO pin, default pull-high input. (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
I/O
IO pin, default pull-high input (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
13
I/O
P1_5
Page 9
Stereo Audio SoC
Pin No.
Pin type
Name
Description
3. Slide Switch Detector, active low.
4. Buzzer Signal Output
14
15
I
HCI_RXD
HCI_TXD
HCI-UART RX data
O
HCI-UART TX data
Pin No.
16
Pin type
Name
Description
P
P
P
P
P
-
CODEC_VO 3.1V LDO output for CODEC power
17
LDO31_VIN 3.1V LDO input; Connect to SYS_PWR pin
18
LDO31_VO
ADAP_IN
BAT_IN
NC
3.1V LDO output
19
5V power adaptor input
20
3.3~4.2V Li-Ion battery input
No Connection
21
22
P
P
P
P
P
I
SAR_VDD
SYS_PWR
BK_VDD
BK_LX
BK_O
SAR 1.8V input; Connect to BK_O pin
Power Output which come from BAT_IN or ADAP_IN
1.8V buck VDD Power Input; Connect to SYS_PWR pin
1.8V buck pin for switch
23
24
25
26
1.8V buck feedback input
Multi-Function Push Button and power on key
No Connection
27
PWR
28
-
NC
29
I
LED2
LED Driver 2
30
I
LED1
LED Driver 1
IO pin, default pull-high input (Note 1)
1. Slide Switch Detector, active low.
2. UART TX_IND, active low.
IO pin, default pull-high input (Note 1)
1. REV key (default), active low.
2. Buzzer Signal Output
31
32
I/O
I/O
P0_0
P0_3
3. Out_Ind_1
4. Class1 RX Control signal of external RF T/R switch, active high.
33
34
35
36
37
38
39
P
P
P
P
P
I
CLDO_O
PMIC_IN
RFLDO_O
VBG
1.2V core LDO output
PMU blocks power input; Connect to BK_O pin
1.28V RF LDO output
Bandgap output reference for decoupling interference
ULPC_VSUS ULPC 1.2V output power.
XO_N
XO_P
16MHz Crystal input negative
16MHz Crystal input positive
I
RF power input (1.28V) for both synthesizer and TX/RX block; Connect to
RFLDO_O pin
40
41
42
P
I/O
I
VCC_RF
RTX
RF RTX path
IO pin, default pull-high input (Note 1)
Play/Pause key (default), active low.
P0_2
Page 10
Stereo Audio SoC
Pin No.
Pin type
Name
Description
IO pin, default pull-high input (Note 1)
43
I
P2_0
System Configuration,
H: Application L: Baseband(IBDK Mode)
IO pin, default pull-high input (Note 1)
Volume up key (default), active low.
IO pin, default pull-high input (Note 1)
Volume down (default), active low.
44
45
I
I
P2_7
P0_5
Pin No.
46
Pin type
Name
VDD_IO
NC
Description
P
-
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
No Connection.
47
48
O
P
AOHPR
EP
R-channel analog headphone output
Exposed pad as ground
49
* I: signal input pin
* O: signal output pin
* I/O: signal input/output pin
* P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
Page 11
Stereo Audio SoC
TABLE 3-3: IS2023S PIN DESCRIPTION
Pin No.
Pin type
Name
Description
Positive power supply dedicated to CODEC output amplifiers; Connect to
CODEC_VO pin
1
P
VDDAO
Positive power supply/reference voltage for CODEC; Connect to
CODEC_VO pin
2
P
VDDA
3
4
5
6
7
8
9
P
I
VCOM
MICN1
MICP1
MIC_BIAS
AIR
Internal biasing voltage for CODEC
Mic 1 mono differential analog negative input
Mic 1 mono differential analog positive input
Electric microphone biasing voltage
I
P
I
R-channel single-ended analog inputs
L-channel single-ended analog inputs
Core 1.2V power input; Connect to CLDO_O pin
I
AIL
P
VDD_CORE
IO pin, default pull-high input
EEPROM clock SCL
IO pin, default pull-high input
EEPROM data SDA
10
11
O
P1_2
P1_3
I/O
12
13
14
I
RST_N
VDD_IO
P0_1
System Reset Pin, active when rising edge.
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
IO pin, default pull-high input
P
I/O
Page 12
Stereo Audio SoC
Pin No.
Pin type
Name
Description
IO pin, default pull-high input
System Configuration,
15
I
P2_4
L: Boot Mode with P2_0 low combination
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
I/O
I/O
I
P0_4
P1_5
IO pin, default pull-high input.
IO pin, default pull-high input
HCI-UART RX data
HCI_RXD
HCI_TXD
O
P
HCI-UART TX data
CODEC_VO 3.1V LDO output for CODEC power
P
LDO31_VIN 3.1V LDO input; Connect to SYS_PWR pin
P
LDO31_VO
ADAP_IN
BAT_IN
NC
3.1V LDO output
P
5V power adaptor input
P
3.3~4.2V Li-ion battery input
No Connection
-
P
SAR_VDD
SYS_PWR
BK_VDD
BK_LX
SAR 1.8V input; Connect to BK_O pin
Power Output which come from BAT_IN or ADAP_IN
1.8V buck VDD Power Input; Connect to SYS_PWR pin
1.8V buck pin for switch
P
P
P
P
BK_O
1.8V buck feedback input
1. Multi-Function Push Button and power on key
2. UART RX_IND
31
I
PWR
32
33
I
I
LED2
LED1
LED Driver 2
LED Driver 1
IO pin, default pull-high input (Note 1)
UART TX_IND
34
35
36
I/O
I/O
I
P0_0
P0_3
EAN
IO pin, default pull-high input
Embedded ROM/External Flash enable
H: Embedded; L: External Flash
37
38
39
40
41
42
43
P
P
P
P
P
I
CLDO_O
PMIC_IN
RFLDO_O
VBG
1.2V core LDO output
PMU blocks power input; Connect to BK_O pin
1.28V RF LDO output
Bandgap output reference for decoupling interference
ULPC_VSUS ULPC 1.2V output power.
XO_N
XO_P
16MHz Crystal input negative
16MHz Crystal input positive
I
RF power input (1.28V) for both synthesizer and TX/RX block; Connect to
RFLDO_O pin
44
P
VCC_RF
45
46
I/O
I/O
RTX
RF RTX path
P0_2
IO pin, default pull-high input
IO pin, default pull-high input
System Configuration,
47
I
P2_0
H: Application L: Baseband(IBDK Mode)
Page 13
Stereo Audio SoC
Pin No.
48
Pin type
I/O
I/O
I/O
I/O
P
Name
P2_7
P3_0
TFS0
P0_5
VDD_IO
DR0
Description
IO pin, default pull-high input
IO pin, default pull-high input
49
I2S interface: ADC Left/Right Clock
50
51
IO pin, default pull-high input
52
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
I2S interface: DAC Digital Left/Right Data
I2S interface: DAC Left/Right Clock
I2S interface: Bit Clock
53
I/O
I/O
I/O
I/O
P
54
RFS0
SCLK0
DT0
55
I2S interface: ADC Digital Left/Right Data
56
57
EP
Exposed pad as ground
* I: signal input pin
* O: signal output pin
* I/O: signal input/output pin
* P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
Page 14
Stereo Audio SoC
TABLE 3-4: IS2025S PIN DESCRIPTION
Pin No.
Pin type
Name
Description
Positive power supply dedicated to CODEC output amplifiers; Connect to
CODEC_VO pin
1
P
VDDAO
2
3
O
O
AOHPM
AOHPL
Headphone common mode output/sense input.
L-channel analog headphone output
Positive power supply/reference voltage for CODEC; Connect to
CODEC_VO pin
4
P
VDDA
5
6
P
I
VCOM
MICN2
MICP2
Internal biasing voltage for CODEC
Mic 2 mono differential analog negative input
Mic 2 mono differential analog positive input
Mic 1 mono differential analog negative input
Mic 1 mono differential analog positive input
Electric microphone biasing voltage
7
I
8
I
MICN1
MICP1
9
I
10
P
MIC_BIAS
Page 15
Stereo Audio SoC
Pin No.
11
Pin type
Name
AIR
Description
I
I
R-channel single-ended analog inputs
12
AIL
L-channel single-ended analog inputs
13
P
VDD_CORE
Core 1.2V power input; Connect to CLDO_O pin
IO pin, default pull-high input
EEPROM clock SCL
IO pin, default pull-high input
EEPROM data SDA
14
15
O
P1_2
P1_3
I/O
Pin No.
16
Pin type
Name
RST_N
Description
I
System Reset Pin, active when rising edge.
17
P
VDD_IO
I/O power supply input (2.7~3.3V); Connect to LDO31_VO pin
IO pin, default pull-high input (Note 1)
1. FWD key when class 2 RF, active low.
2. Class1 TX Control signal of external RF T/R switch, active high.
IO pin, default pull-high input
18
19
20
I/O
I
P0_1
P2_4
P0_4
System Configuration,
L: Boot Mode with P2_0 low combination
IO pin, default pull-high input. (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
I/O
IO pin, default pull-high input (Note 1)
1. NFC detection pin, active low.
2. Out_Ind_0
21
I/O
P1_5
3. Slide Switch Detector, active low.
4. Buzzer Signal Output
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
I
O
I
HCI_RXD
HCI_TXD
TEST_EN
HCI-UART RX data
HCI-UART TX data
Scan chain test enable pin, active high.
P
P
P
P
P
-
CODEC_VO 3.1V LDO output for CODEC power
LDO31_VIN 3.1V LDO input; Connect to SYS_PWR pin
LDO31_VO
ADAP_IN
BAT_IN
NC
3.1V LDO output
5V power adaptor input
3.3~4.2V Li-Ion battery input
No Connection
P
P
P
P
P
I
SAR_VDD
SYS_PWR
BK_VDD
BK_LX
SAR 1.8V input; Connect to BK_O pin
Power Output which come from BAT_IN or ADAP_IN
1.8V buck VDD Power Input; Connect to SYS_PWR pin
1.8V buck pin for switch
BK_O
1.8V buck feedback input
PWR
Multi-Function Push Button and power on key
No Connection
-
NC
Page 16
Stereo Audio SoC
Pin No.
38
Pin type
Name
LED2
LED1
P3_5
Description
I
I
LED Driver 2
39
LED Driver 1
40
I/O
IO pin, default pull-high input
IO pin, default pull-high input (Note 1)
1. Slide Switch Detector, active low.
2. UART TX_IND, active low.
IO pin, default pull-high input (Note 1)
1. REV key (default), active low.
2. Buzzer Signal Output
41
42
I/O
I/O
P0_0
P0_3
3. Out_Ind_1
4. Class1 RX Control signal of external RF T/R switch, active high.
Pin No.
Pin type
Name
Description
Embedded ROM/External Flash enable
H: Embedded; L: External Flash
43
I
EAN
44
45
46
47
48
49
50
51
52
53
P
P
P
P
P
-
CLDO_O
PMIC_IN
RFLDO_O
VBG
1.2V core LDO output
PMU blocks power input.
1.28V RF LDO output
Bandgap output reference for decoupling interference
ULPC_VSUS ULPC 1.2V output power, maximum loading 1mA.
NC
XO_N
XO_P
VCC_RF
RTX
No Connection.
I
16MHz Crystal input negative
16MHz Crystal input positive
RF power input for both synthesizer and TX/RX block
RF RTX path
I
P
I/O
GPIO, default pull-high input (Note 1)
Play/Pause key as the default setting
GPIO, default pull-high input (Note 1)
1. KEY PIN for FT Test
2. System Configuration, H: Application L: Baseband(IBDK Mode)
3. Buzzer Signal Output
54
I/O
P0_2
55
I/O
P2_0
GPIO, default pull-high input (Note 1)
Volume up key (default)
GPIO, default pull-high input (Note 1)
Line-in Detector
GPIO, default pull-high input (Note 1)
Volume down (default)
56
57
58
I/O
I/O
I/O
P2_7
P3_0
P0_5
59
60
61
62
63
64
65
P
P
VDD_IO
I/O power supply input
PVDD2_CDA Supply voltage of power stage ch-2 .
HPOP2_CDA Positive BTL output of channel-2
HPON2_CDA Negative BTL output of channel-2
AVDD_CDA Supply voltage of audio amplifier.
O
O
P
P
VBP_CDA
Reference voltage output.
O
HPON_CDA Negative BTL output of channel-1
Page 17
Stereo Audio SoC
Pin No.
66
Pin type
Name
Description
O
P
HPOP_CDA Positive BTL output of channel-1
PVDD_CDA Supply voltage of power stage ch-1
67
68
O
AOHPR
EP
R-channel analog headphone output
Exposed pad as ground
69
P
* I: signal input pin
* O: signal output pin
* I/O: signal input/output pin
* P: power pin
Note 1: These button or functions can be setup by “IS20XXS_UI” tool.
3.2 POWER SUPPLY
The device is powered via BAT pin input. If a battery is not connected, an external power supply needs to
provide to this input. Figure 3-1 shows the PCB connections from BAT pin to other voltage supply pins of the
chip.
FIGURE 3-1: POWER TREE DIAGRAM
(Use PCB trace link these pins)
(3.0~2.7V)
VDDA /
VDDAO
CODEC_VO
LDO31_VO
PVDD_CDA
(4.2~3.0V)
LDO31_VIN
3V LDO
VDD_IO
BAT_IN
ADAP_IN
Power
Switch
(3.3~2.7V)
SYS_PWR
(4.2~3.0V)
(4.5~5.5V)
BK_O
(1.2V)
BK_VDD
1.8V Buck
CLDO_O
5V
Adapter
VDD_CORE
VCC_RF
(1.8V)
BK_LX
PMIC_IN
1.2V LDO
(1.28V)
RFLDO_O
SAR_VDD
Page 18
Stereo Audio SoC
4.0 TRANSCEIVER
The stereo audio chip is designed and optimized for Bluetooth 2.4 GHz system. It contains a complete
radio frequency transmitter/receiver section. An internal synthesizer generates a stable clock for
synchronize with another device.
4.1 TRANSMITTER
The internal PA has a maximum output power of +4dBm with 20dB power level control. This is applied
into Class2/3 radios without external RF PA.
The transmitter directly performs IQ conversion to minimize the frequency drift, and it can excess 20dB
power range with temperature compensation mechanism.
4.2 RECEVIER
The LNA operates with TR-combined mode for single port application. It can save a pin on package and
without an external TX/RX switch.
The ADC is utilized to sample the input analog wave and convert into digital signal for de-modulator
analysis. A channel filter has been integrated into receiver channel before the ADC, which to reduce the
external component count and increase the anti-interference capability.
The image rejection filter is used to reject image frequency for low-IF architecture. This filter for low-IF
architecture is intent to reduce external BPF component for super heterodyne architecture.
RSSI signal is feedback to the processor to control the RF output power to make a good tradeoff for
effective distance and current consumption.
4.3 SYNTHESIZER
A synthesizer generates a clock for radio transceiver operation. There is a VCO inside with tunable
internal LC tank. It can reduce variation for components. A crystal oscillation with internal digital trimming
circuit provides a stable clock for synthesizer.
4.4 MODEM
For Bluetooth v1.2 specification and below, 1 Mbps was the standard data rate based on Gaussian
Frequency Shift Keying (GFSK) modulation scheme. This basic rate modem meets BDR requirements of
Bluetooth v2.0 with EDR specification.
For Bluetooth v2.0 with EDR specification, Enhanced Data Rate (EDR) has been introduced to provide 2
and 3 Mbps data rates as well as 1 Mbps. This enhanced data rate modem meets EDR requirements of
Bluetooth v2.0 with EDR specification. For the viewpoint of baseband, both BDR and EDR utilize the same
1MHz symbol rate and 1.6 KHz slot rate. For BDR, 1 symbol represents 1 bit. However each symbol in the
payload part of EDR packets represents 2 or 3 bits. This is achieved by using two different modulations, π/4
DQPSK and 8DPSK.
4.5 AFH (Adaptive Frequency Hopping)
Stereo audio chip have AFH function to avoid RF interference. It has an algorithm to check the
interference nearby and choice clear channel to transceiver Bluetooth signal.
Page 19
Stereo Audio SoC
5.0 MICROPROCESSOR
A single-cycle 8-bit MCU is built into the stereo audio chip to execute the Bluetooth protocols. It operates
from 16MHz to higher frequency where the firmware can dynamically adjust the tradeoff between the
computing power and the power consumption. The MCU firmware is hard-wired in ROM to minimize the
firmware execution power consumption and to save the external flash cost.
5.1 MEMORY
A synchronous single port RAM interface is used. There are sufficient ROM and RAM to fulfill the
requirement of processor. A register bank, a dedicated single port memory and a flash memory are
connected to the processor bus. The processor coordinates all the link control procedures and data
movement using a set of pointers registers.
5.2 EXTERNAL RESET
The chip provides a watchdog timer to reset the chip. It has an integrated Power-On Reset (POR) circuit
that resets all circuits to a known power-on state. This action can also be driven by an external reset signal
that can be used to externally control the device, forcing it into a power-on reset state. The RST signal input
is active low and no connection is required in most applications.
5.3 REFERENCE CLOCK
Stereo audio chip is composed of an integrated crystal oscillation function. It uses a 16 MHz external
crystal and two specified loading capacitors to provide a high quality system reference timer source. This
feature is typically used to remove the initial tolerance frequency errors associated with the crystal and its
equivalent loading capacitance in mass production. Frequency trim is achieved by adjusting the crystal
loading capacitance through the on-chip trim capacitors Ctrim..
The value of trimming capacitance is around 200fF (200x10-15 F) per LSB at 5 bits word, therefore the
overall adjustable clock frequency is around 40 KHz.
FIGURE 5-1: CRYSTAL CONNECTION
IS20XXS
XO_N
XO_P
CL2
CL1
Ctrim
=200fF * (1~31) ; Cint 3pF
CL=[(CL1*CL2)/(CL1+CL2)]+(Ctrim/2)+Cint
(e.g. Set trim value as 16, then C trim= 3.2pF.
For a 16M Hz crystal which C =9pF, we can get CL1 = CL2 = 9.1pF in this case.)
L
For CL selection, please refer to the datasheet of crystal vendor
Page 20
Stereo Audio SoC
6.0 AUDIO
There are a few stages for input audio and output audio. Each stage can be programmed to vary the gain
response characteristics. For microphone input, both single-end input and differential input are supported.
One of the important points in maintaining a high quality signal is to provide a stable bias voltage source to
the condenser microphone’s FET. DC blocking capacitors may be used at both positive and negative sides
of input. Internally, this analog signal is converted to 16-bit 8 kHz linear PCM data.
6.1 DIGITAL SIGNAL PROCESSOR
A digital signal processor (DSP) cooperates with MCU to perform digital audio processing with some
advanced features such as noise cancellation, audio output level suppression and etc. It provides audio
processing with some advanced features. The DSP cancels the acoustic echo that may present in headset
or speaker. All the audio processing is performed by the DSP with low power consumption. This technique
effectively cancels the incoming echo signal without impact to the desired voice signal. An outgoing signal
to the speaker which level exceeds the threshold (and therefore deemed likely to create echo) will be result
in suppression of the signal along the input path from the microphone. Filtering is also applied to provide a
smoother transition for more natural user experience.
FIGURE 6-1: BLOCK DIAGRAM OF DSP
BT Chip
DSP
CVSD/A-
Law/u-Law
Decoders
Antenna
Audio
Amp
Far- End
NR
IIR/EQ
HPF
DAC
ADC
BT
Speaker
Digital Mic
Gain
RF/Base-
band
Processor
CVSD/A-
Law/u-Law
Encoders
Near-End
NR/AES
HPF
IIR/EQ
AEC
MIC
Additive
Background Noise
(a)
BT Chip
DSP
Antenna
8051
Processor/
BT
RF/Base-
band
Processor
Audio
Amp
Audio
Effect
SBC/AAC
Decoders
DAC
IIR/EQ
Speaker
(b)
Processing flow of speakerphone applications for (a) speech and (b) audio signal processing.
There is a “DSPTool_IS20XX” can support user to set up these DSP parameter. For more detail
information, please reference “BT5502_DSP_APP” document.
Page 21
Stereo Audio SoC
6.2 CLASS-D AUDIO AMPLIFIER
The class D amplifier has significant advantage in many applications because of its lower power
dissipation which produces less heat. IS2025S chip has built-in a class D amplifier that reduces circuit
board space and system cost. The efficiency of the amplifier extends the battery life in portable systems.
The class D amplifier is implemented by using a full-bridge output stage. A full bridge uses two half-bridge
stages to drive the load differentially. It provides a good signal to noise ratio (SNR) and enough drive
capability for a 4 Ohm speaker driver.
6.3 CODEC
The built-in codec has a high Signal to Noise ratio performance. This built-in codec consist of an analog
to digital converter (ADC), a digital to analog converter (DAC) and additional analog circuitry.
6.4 LINE IN (Aux In)
The chip supports one analog line in from external audio source. The analog line in signal can be
processed by the DSP to generate different sound effect (Multi-band Dynamic Range Compression, Audio
Widening). The sound effect can be set up by DSP tool.
Page 22
Stereo Audio SoC
7.0 POWER MANAGEMENT UNIT
The on-chip Power management Unit (PMU) has two main feature; Lithium Ion battery charging and
voltage regulation. A power switch is used to switch over the power source between battery and adaptor
automatically. The PMU also provides driving current for 2 LEDs.
7.1 CHARGING A BATTERY
Stereo audio chip has a built-in battery charger which is optimized for lithium polymer batteries. The
charger includes a current sensor for charging control, user programmable current regulation and high
accuracy voltage regulation.
The charging current parameters are configured by “IS20XXS_UI” tool. Whenever the adaptor is plug-in,
the charging circuit will be activated. Reviving, Pre-charging, Constant Current and Constant Voltage
modes are implemented and re-charging function is also included. The maximum charging current is
350mA.
FIGURE 7-1: CHARGING CURVE
Recharge
Mode
Reviving
Mode
Pre charge
Mode
CV Voltage 4.2v
Constant Current Mode
Constant Voltage Mode
Recharge Voltage
4.1v
CC current 0.5c
CC Voltage 3.0v
Recharge current
0.25c
Precharge Voltage
2.5v
Precharge Current
0.1c
Reviving Current
2mA
7.2 VOLTAGE MONITORING
A 10-bit Successive-Approximation-Register analog to digital converter (SAR ADC) provides one
dedicated channel for battery voltage level detection. The warning level is programmable by “IS20XXS_UI”
tool. This ADC provides a good resolution that MCU can control the charging process.
7.3 LDO
The built-in LDO is used to convert the battery or adaptor power for power supply. It also integrates
hardware architecture to control power on/off procedure. The built-in programmable LDOs provide power for
codec and digital IO pads. It is used to buffer the high input voltage from battery or adapter. This LDO needs
1uF bypass capacitor.
7.4 SWITCHING REGULATOR
The built-in programmable output voltage regulator can convert battery voltage for RF and baseband core
power supply. This converter has high conversion efficiency and fast transient response.
Page 23
Stereo Audio SoC
7.5 LED DRIVER
There are two dedicate LED drivers to control the LEDs. They provide enough sink current (16 step control
and 0.35mA for each step) that LED can be connected directly with IS20XXS. LED setting can be set up by
“IS20XXS_UI” tool.
SYS_PWR
LED1
IS20XXS
LED2
Page 24
Stereo Audio SoC
8.0 GENERAL PURPOSE IOs
Stereo audio chip provides six IOs for key functions. The corresponding key functions can be set up by
“IS20XXS_UI” tool. The first button (Button 0) must be power key. The power on/off functions only can be set
on PWR pin. There are four different operations (short click, long click, double click and combinations) for
every button can be defined as different functions. All these function can be set up by “IS20XXS_UI” tool.
IO Pin for Buttons
Button Name
Button 0
Button 1
Button 2
Button 3
Button 4
Button 5
Default Functions
Power / MFB
PLAY/PAUSE
Volume UP
Volume DOWN
FWD
IO pin name
PWR
P0_2
P2_7
P0_5
P0_1
P0_3
REV
Note: All these function can be set up by “IS20XXS_UI” tool.
Some signals were generated to indicate or control outside devices. The most popular applications are NFC
for easy pairing, external audio amplifier for louder speaker and buzzer for indication.
IOs pin for added functions
Functions
Slide switch
Buzzer
IO configurable features
P0_0 / P1_5
P0_3
NFC detect
External AMP enable
P0_4 / P1_5
P1_5
Note: All these function can be set up by “IS20XXS_UI” tool.
Page 25
Stereo Audio SoC
9.0 OPERATION WITH EXTERNAL MCU
IS20XXS support UART command set to make an external MCU to control IS20XXS chip.
Here is the connection interface between IS20XXS and MCU.
FIGURE 9-1: INTERFACE BETWEEN MCU AND IS20XX CHIP
MCU_
WAKEUP
P0_0
UART interface
UART_RX
UART_TX
HCI_TXD
MCU
IS20XXS
UART interface
HCI_RXD
PWR
BT_
WAKEUP
MCU can control IS20XXS chip by UART interface and wakeup IS20XXS by PWR pin. IS20XXS provide
wakeup MCU function by connect to P0_0 pin of IS20XX.
“UART_CommandSet_v154” document provide all UART command which IS20XX support and
“IS20XXS_UI” tool will help you to set up your system support UART command.
For more detail description, please reference “UART_CommandSet_v154” document and “IS20XXS_UI”
tool.
Page 26
Stereo Audio SoC
9.1 T
F
FIGU
N
Page 27
Stereo Audio SoC
FIGURE 9-4: TIMING SEQUENCE OF POWER OFF
Page 28
Stereo Audio SoC
FIGURE 9-5: TIMING SEQUENCE OF POWER ON (NACK)
FIGURE 9-6: RESET TIMING SEQUENCE IF MODULE HANGS UP
Page 29
Stereo Audio SoC
FIGURE 9-7: TIMING SEQUENCE OF POWER DROP PROTECTION
BAT_IN +4V
RST_N from Reset IC
If BT’s BAT use adaptor translates voltage by LDO, we recommend use “Reset IC” to avoid power
off suddenly. Rest IC spec output pin must be “Open Drain”、delay time ≦ 10ms
Recommend part: TCM809SVNB713 or G691L263T73
Page 30
Stereo Audio SoC
10.0 I2S APPLICATION
IS2023S support I2S digital audio signal output. It provide 8k Hz, 44.1k Hz and 48k Hz sampling rate; it also
support 16 bits and 24bits data format. The I2S setting can be set up by “IS20XXS_UI” tool and DSP tool.
.
The I2S signal connection between IS2023S and external DSP as below:
FIGURE 10-1: MASTER MODE REFERENCE CONNECTION
BCLK
SCLK0
RFS0
TFS0
DR0
DACLRC
EXTERNAL
DSP/CODEC
IS2023S
ADCDAT
DACDAT
DT0
FIGURE 10-2: SLAVE MODE REFERENCE CONNECTION
BCLK
SCLK0
RFS0
TFS0
DR0
DACLRC
(*1)
EXTERNAL
DSP/CODEC
IS2023S
(*2)
ADCDAT
DACDAT
DT0
Note 1: For 002 version chip or module, system should connect line 1 in slave mode figure.
And, system not support ADC signal from external DSP/CODEC.
Note 2: For other version chip or module, system should connect line 2 in slave mode figure.
About “Mast” or “Slave” mode setting, you can use “DSP Configuration Tool” to set up system.
Page 31
Stereo Audio SoC
10.1 CLOCK AND DATA TIMING SEQUENCE
FIGURE 10-3: TIMING FOR I2S MODES (both master and slave)
1/fs
SCLKn
Left Channel
RFSn/TFSn
Right Channel
DRn/DTn
B
n-1
Bn-2
B1
B
0
Bn-1
B
n-2
B
1
B0
Word Length
FIGURE 10-4: TIMING FOR PCM MODES (both master and slave)
1/fs
SCLK0
RFS0/TFS0
Left Channel
Right Channel
DR0/DT0
B
n-1
Bn-2
B
1
B
0
B
n-1
Bn-2
B
1
B
0
Word Length
Page 32
Stereo Audio SoC
11.0 ANTENNA PLACEMENT RULE
For Bluetooth product, antenna placement will affect whole system performance.
Antenna need free space to transmit RF signal, it can’t be surround by GND plane.
Here are some examples of good and poor placement on a Main Application board with GND plane.
FIGURE 11-1: ANTENNA PLACEMENT EXAMPLES
Antenna
Good Case
Antenna
Acceptable Case
Antenna
Poor Case
Antenna
Worse Case
System GND Plane
FIGURE 11-2: KEEP OUT AREA SUGGESTION FOR ANTENNA
For more detail free space of antenna placement design, you can reference the design rule of antenna
produce vendor.
Page 33
Stereo Audio SoC
12.0 SPECIFICATIONS
Table 12-1: ABSOLUTE MAXIMUM SPECIFICATION
Symbol
VDD_CORE
VCC_RF
Parameter
Digital core supply voltage
RF supply voltage
Min
0
0
Max
1.35
1.35
2.1
Unit
V
V
SAR_VDD
SAR ADC supply voltage
0
V
VDDA/VDDAO CODEC supply voltage
0
3.3
V
VDD_IO
BK_VDD
LDO31_VIN
BAT_IN
ADAP_IN
TSTORE
I/O supply voltage
BUCK supply voltage
Supply voltage
Input voltage for battery
Input voltage for adaptor
Storage temperature
Operation temperature
0
0
0
0
0
-65
-20
3.6
4.3
4.3
4.3
7.0
+150
+70
V
V
V
V
V
ºC
ºC
TOPERATION
Table 12-2: RECOMMENDED OPERATING CONDITION
Symbol
VDD_CORE
VCC_RF
SAR_VDD
VDDA/VDDAO CODEC supply voltage
Parameter
Digital core supply voltage
RF supply voltage
Min
Typical
Max
1.26
1.34
1.98
3.0
Unit
1.14
1.22
1.62
2.7
2.7
3
3
3
4.5
-20
1.2
1.28
1.8
2.8
3.0
3.7
3.7
3.7
5
V
V
V
V
V
V
V
V
V
ºC
SAR ADC supply voltage
VDD_IO
I/O supply voltage
BUCK supply voltage
Supply voltage
Input voltage for battery
Input voltage for adaptor
Operation temperature
3.3
BK_VDD
LDO31_VIN
BAT_IN
ADAP_IN
TOPERATION
Note:
4.25
4.25
4.25
5.5
+25
+70
All these supply voltage are programmable by EEPROM parameters.
Page 34
Stereo Audio SoC
Table 12-3: BUCK SWITCHING REGULATOR
Min
3.0
1.7
Typical
3.7
Max
4.25
2.05
Unit
V
Parameter
Input Voltage
Output Voltage (Iload=70mA, Vin=4V)
Output Voltage Accuracy
1.8
V
±5
%
mV
/Step
V
Output Voltage Adjustable Step
Output Adjustment Range
50
88
-0.1
120
+0.25
Average Load Current (ILOAD
)
mA
%
Conversion efficiency (BAT=3.8V, Iload = 50mA)
Quiescent Current (PFM)
μA
40
<1
Output Current (peak)
Shutdown Current
200
mA
μA
Note:
(1) Test condition: SAR_VDD=1.8V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
Table 12-4: LOW DROP REGULATOR
Min
3.0
Typical
Max
Unit
Parameter
Input Voltage
3.7
4.25
V
VOUT CODEC
VOUT IO
2.8
Output Voltage
V
2.8
±5
Output Accuracy (VIN=3.7V, ILOAD=100mA, 27’C)
%
Output current (average)
Drop-out voltage
(Iload = maximum output current)
100
300
mA
mV
Quiescent Current
(excluding load, Iload < 1mA)
Shutdown Current
μA
μA
45
<1
Note:
(1) Test condition: SAR_VDD=1.8V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
Page 35
Stereo Audio SoC
Table 12-5: BATTERY CHARGER
Min
Typical
Max
5.5
Unit
V
Parameter
Input Voltage
4.5
5.0
3
Supply current to charger only
4.5
mA
Headroom > 0.7V
(ADAP_IN=5V)
170
160
330
180
200
180
350
240
240
420
270
mA
mA
mA
Maximum Battery
Fast Charge Current
Note: ENX2=0
Headroom = 0.3V
(ADAP_IN=4.5V)
Headroom > 0.7V
(ADAP_IN=5V)
Headroom = 0.3V
(ADAP_IN=4.5V)
Maximum Battery
Fast Charge Current
Note: ENX2=1
220
3
mA
V
Trickle Charge Voltage Threshold
Battery Charge Termination Current,
(% of Fast Charge Current)
10
%
Note:
(1) Headroom = VADAP_IN – VBAT
(2) ENX2 is not allowed to be enabled when VADAP_IN – VBAT > 2V
(3) These parameters are characterized but not tested in manufacturing.
Table 12-6: LED DRIVER
Min
Typical
Max
3.6
Unit
Parameter
Open-drain Voltage
Programmable Current Range
Intensity Control
V
0
5.25
mA
step
mA
μA
μA
16
Current Step
0.35
Power Down Open-drain Current
1
1
Shutdown Current
Note:
(1) Test condition: SAR_VDD=1.8V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
Page 36
Stereo Audio SoC
Table 12-7: AUDIO CODEC DIGITAL TO ANALOGUE CONVERTER
T= 25oC, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20Hz~20KHz
Parameter (Condition)
Min.
Typ.
Max.
Unit
Over-sampling rate
128
fs
Resolution
Output Sample Rate
16
8
20
48
Bits
KHz
Signal to Noise Ratio Note: 1
(SNR @cap-less mode) for 48kHz
Signal to Noise Ratio Note: 1
(SNR @single-end mode) for 48kHz
Digital Gain
96
98
dB
dB
dB
dB
-54
-28
495
4.85
3
Digital Gain Resolution
2~6
Analog Gain
dB
dB
Analog Gain Resolution
1
mV rms
mW
Output Voltage Full-scale Swing (AVDD=2.8V)
Maximum Output Power (16Ω load)
742.5
34.5
Maximum Output Power (32Ω load)
mW
17.2
16
Ω
pF
%
Resistive
Capacitive
8
O.C.
500
Allowed Load
THD+N (16Ω load)
0.05
Signal to Noise Ratio (SNR @ 16Ωload)
96
dB
Note:
(1) fin=1KHz, B/W=20~20KHz, A-weighted, THD+N < 0.01%, 0dBFS signal, Load=100KΩ
(2) These parameters are characterized but not tested in manufacturing.
Page 37
Stereo Audio SoC
Table 12-8: AUDIO CODEC ANALOGUE TO DIGITAL CONVERTER
T= 25oC, Vdd=3.0V, 1KHz sine wave input, Bandwidth = 20Hz~20KHz
Parameter (Condition)
Min.
Typ.
Max.
Unit
Resolution
16
48
Bits
KHz
Output Sample Rate
Signal to Noise Ratio Note: 1
(SNR @MIC or Line-in mode)
Digital Gain
8
90
dB
-54
4.85
60
dB
dB
Digital Gain Resolution
2~6
20
MIC Boost Gain
Analog Gain
dB
dB
Analog Gain Resolution
2.0
4
800
20
24
0.02
dB
mV rms
Input full-scale at maximum gain (differential)
Input full-scale at minimum gain (differential)
3dB bandwidth
mV rms
KHz
KΩ
%
Microphone mode (input impedance)
THD+N (microphone input) @30mVrms input
Note:
(1) fin=1KHz, B/W=20~20KHz, A-weighted, THD+N < 1%, 150mVpp input
(2) These parameters are characterized but not tested in manufacturing.
Page 38
Stereo Audio SoC
Table 12-9: DUAL-CHANNEL CLASS-D AMPLIFIER
Parameter (Condition)
Min.
Typ.
Max.
Unit
Standalone SNR (A-weighting)
Gain
100
12
dB
dB
dB
%
PSRR (217Hz, 200mV on PVDD)
70
4ohm
Efficiency
80
85
85
90
8ohm
%
Supply Voltage
Load
3.0
3.7
4
4.5
V
ohm
mA
Quiescent current (1 channel)
2
Sample frequency
Over current limits
Shutdown current
250
2.3
1.0
KHz
A
uA
Note:
(1) Test condition: PVDD_CDA=4.2V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
Table 12-10: SYSTEM CURRENT CONSUMPTION
System Status
Typ.
Max.
Unit
System Off Mode
Standby Mode
Linked Mode
SCO Link
2
5
uA
mA
mA
mA
mA
0.8
0.4
7.8
10.7
A2DP Link (V p-p=200mV; 1k tone signal)
Note: Use IS2020 EVB as test platform.
Test condition: BAT_IN= 3.8V, link with HTC EYE cell phone; distance between cell phone and EVB: 30cm.
Table 12-11: SYSTEM CURRENT CONSUMPTION OF DIGITAL AUDIO OUTPUT(I2S)
System Status
Typ.
Max.
Unit
System Off Mode
Standby Mode
Linked Mode
SCO Link
2
5
uA
mA
mA
mA
mA
0.4
0.4
9.3
A2DP Link (1k tone signal)
11.7
Note: Use IS2023 EVB as test platform
Test condition: BAT_IN= 3.8V, link with HTC M8 cell phone; distance between cell phone and EVB: 30cm;
I2S signal link with YAMAHA YDA174 EVB
Page 39
Stereo Audio SoC
Table 12-12: TRANSMITTER SECTION FOR BDR AND EDR
Bluetooth
specification
Parameter
Min
Typ
Max
Unit
Maximum RF transmit power
Relative transmit power
3.0
4.0
1
-6 to 4
dBm
dB
-4
-1.2
-4 to 1
Note:
The RF Transmit power is calibrated during production using MP Tool software and MT8852 Bluetooth Test equipment.
Test condition: VCC_RF= 1.28V, temperature=25 ºC.
Table 12-13: RECEIVER SECTION FOR BDR AND EDR
Bluetooth
specification
Modulation
Min
Typ
Max
Unit
Sensitivity at
0.1% BER
GFSK
π/4 DQPSK
8DPSK
-90
-91
-82
≤-70
dBm
dBm
dBm
≤-70
≤-70
Sensitivity at
0.01% BER
Note:
(1) Test condition: VCC_RF= 1.28V, temperature=25 ºC.
(2) These parameters are characterized but not tested in manufacturing.
Page 40
Stereo Audio SoC
13.0 REFERENCE CIRCUIT
FIGURE 13-1: IS2020S REFERENCE CIRCUIT
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
2
1
1
2
3
2
1
2
2
3
1
4
1
2
1
1
1
2
1
2
X O _ P
D
B K _ V D
S Y S _ P W
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
2 8
F
_ R C V C
R T X
P 0 2
P 2 0
P 2 7
P 3 0
P 0 5
O _ I D V D
P R A O H
A O D V D
P M A O H
P L A O H
A D V D
R
D
2 7
2 6
2 5
2 4
_ V D S A R
N C
P 0 _ 2
P 2 _ 0
P 2 _ 7
P 3 _ 0
P 0 _ 5
N _ I B A T
N A P _ A I D
N
A P _ A I D
2 3
O 3 L 1 D _ V O
2 2
O 3 L 1 D _ V I
N
2 1
2 0
1 9
1 8
1 7
1 6
1 5
_ V O E C O C D
X D _ I T C H
X D _ I R C H
P R A O H
P 1 5
P 0 4
P 2 4
P M A O H
P L A O H
P 0 _ 4
P 2 _ 4
E P
5 7
2
1
3
1
2
1
2
3
1
2
1
2
4
2
3
1
2
1
2
1
2
1
2
1
2
1
2
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
Page 41
Stereo Audio SoC
FIGURE 13-2: IS2021S REFERENCE CIRCUIT
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
2
3
2
1
2
1
1
2
3
1
4
1
2
1
2
1
2
X O _ P
_ R C V C
R T X
P 0 2
P 2 0
P 2 7
P 0 5
O _ I D V D
N C
P R A O H
D
B K _ V D
2 4
3 9
4 0
4 1
4 2
4 3
4 4
4 5
4 6
4 7
4 8
F
R
D
S Y S _ P W
2 3
2 2
2 1
2 0
_ V D S A R
N C
P 0 _ 2
P 2 _ 0
P 2 _ 7
P 0 _ 5
N _ I B A T
N A P _ A I D
N
A P _ A I D
1 9
1 8
1 7
1 6
1 5
O 3 L 1 D _ V O
O 3 L 1 D _ V I
N
_ V O E C O C D
X D _ I T C H
P R A O H
E P
4 9
2
1
3
1
2
1
2
3
1
2
1
2
4
2
3
1
2
1
2
1
1
2
2
2
2
1
1
1
1
1
1
1
1
1
Page 42
Stereo Audio SoC
FIGURE 13-3: IS2023S REFERENCE CIRCUIT
1
2
1
2
2
1
2
1
2
1
2
3
1
4
1
2
1
2
X O _ P
D D _ V B K
R P W S _ S Y
D D _ V R S A
N C
4 3
4 4
4 5
4 6
4 7
4 8
4 9
5 0
5 1
5 2
5 3
5 4
5 5
5 6
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1 7
1 6
1 5
F
_ R C V C
R T X
P 0 2
P 2 0
P 2 7
P 3 0
S F 0 T
P 0 5
O _ I D V D
D R 0
S F 0 R
1
2
N _ I T B A
P 2 _ 0
P 3 _ 0
N _ I A P A D
V O 1 _ O 3 L D
N V I 1 _ O 3 L D
O
_ V E C O C D
X D _ I T C H
X D _ I R C H
P 1 5
P 0 4
P 2 4
0
L K S C
D T 0
E P
5 7
Page 43
Stereo Audio SoC
FIGURE 13-4: IS2025S REFERENCE CIRCUIT (FOR HEADSET APPLICATION)
1
2
1
2
1
2 3
1
2
4
2
3
1
1
2
1
2
1
2
D
T
G / N J A D
O U
1
2
3
I N
1
2
2
3
1
4
1
2
1
1
2
3
F
_ R C V C
R T X
P 0 2
P 2 0
P 2 7
P 3 0
P 0 5
B K _ L X
5 2
5 3
5 4
3 4
D
B K _ V D
3 3
1
2
2
R
D
S Y S _ P W
P 0 _ 2
3 2
3 1
3 0
2 9
_ V D S A R
E T B _ D A M
N _ I B A T
P 2 _ 0
5 5
P 2 _ 7
5 6
P 3 _ 0
5 7
N
A P _ A I D
O 3 L 1 D _ V O
2 7
P 0 _ 5
N
A P _ A I D
5 8
5 9
6 0
6 1
6 2
6 3
6 4
6 5
6 6
6 7
2 8
O _ I D V D
A D 2 _ D
A D
A D 2 _ C P O H N
A D _ C D A V D
C
P V D
N
O 3 L 1 D _ V I
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
1
2
P O H P 2 _ C
_ V O E C O C D
_ E N E T S T
X D _ I T C H
X D _ I R C H
X D _ I T C H
X D _ I R C H
A D
V B P _ C
A D _ C P O H N
A D
A D _ C D P V D
P R A O H
P 1 5
P O H P _ C
P 0 4
P 2 4
P 0 1
P 0 _ 4
P 2 _ 4
P 0 _ 1
P R A O H
6 8
E P
6 9
2
1
3
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
Page 44
Stereo Audio SoC
FIGURE 13-5: IS2025S REFERENCE CIRCUIT (FOR SPEAKER APPLICATION)
1
2
1
2
1
2
1
2
1
2
1
2
1
2
D
T
G / N J A D
O U
1
2
3
I N
1
2
2
3
1
4
1
1
2
3
2
1
2
1
2
F
_ R
C
V C
B K _ L X
5 2
5 3
5 4
3 4
R T X
P 0 2
P 2 0
P 2 7
P 3 0
P 0 5
D
B K _ V D
3 3
1
2
R
D
S Y S _ P W
P 0 _ 2
3 2
3 1
3 0
2 9
_ V D S A R
N C
N _ I B A T
A P _ A I D
P 2 _ 0
5 5
P 2 _ 7
5 6
P 3 _ 0
5 7
N
P 0 _ 5
N
A P _ A I D
5 8
5 9
6 0
2 8
O _ I D V D
A D 2 _
A D
A D 2 _ C P O H N
A D _ C
O 3 L 1 D _ V O
2 7
O 3 L 1 D _ V I
D C
P V D
N
2 6
2 5
2 4
2 3
2 2
2 1
2 0
1 9
1 8
P O H P 2 _ C
_ V O E C O C D
_ E N E T S T
X D _ I T C H
X D _ I R C H
P O H P 2
6 1
6 2
6 3
6 4
6 5
6 6
6 7
6 8
2
P O H N
D
A V D
X D _ I T C H
X D _ I R C H
A D
V B P _ C
A D _ C P O H N
A D P O H P _ C
A D _ C P V D
P 1 5
P O H N
P O H P
P 0 4
P 2 4
P 0 1
P 0 _ 4
P 2 _ 4
P 0 _ 1
D
P R A O H
E P
6 9
1
2
1
2
1
2 3
1
2
1
2
2
1
3
1
2
4
2
3
1
1
2
2
2
1
1
2
2
1
1
2
1
2
1
2
1
2
1
2
1
2
1
Page 45
Stereo Audio SoC
14.0 PACKAGE INFORMATION
14.1 CHIP IDENTIFICATION SYSTEM
PART NO.
(Chip Name)
X
-Y
(Version)
(Package Type)
Chip name:
IS2020
IS2021
IS2023
IS2025
Package Type:
Version:
S = QFN (Saw Type) Package
e.g. “-203” is means the chip version is 203.
Examples:
a) IS2020S-002:
b) IS2025S-203:
002 version ROM code IS2020 chip in QFN type package.
203 version ROM code IS2025 chip in QFN type package.
Page 46
Stereo Audio SoC
14.2 PACKAGE MARKING INFORMATION
48 Lead QFN (5x6.5x0.9 mm)
Example
56 Lead QFN (7x7x0.9 mm)
Example
68 Lead QFN (8x8x0.9 mm)
Example
Legend:
XXX: Chip serial number version and e3 Pb-free JEDEC designator for Matte Tin (Sn)
○
YY: Year code (last 2 digits of calendar year)
WW: Week code (week of January 1 is week “1”)
NNN: Alphanumeric traceability code
Page 47
Stereo Audio SoC
14.3 PACKAGE DETAIL
QFN48 5x6.5 Chip Outline (IS2021S)
Page 48
Stereo Audio SoC
QFN48 5x6.5 PCB Footprint (IS2021S)
Page 49
Stereo Audio SoC
QFN56 7x7 Chip Outline (IS2020S / IS2023S)
Page 50
Stereo Audio SoC
QFN56 7x7 PCB Footprint (IS2020S / IS2023S)
Page 51
Stereo Audio SoC
QFN68 8x8 Chip Outline (IS2025S)
Page 52
Stereo Audio SoC
QFN68 8x8 PCB Footprint (IS2025S)
Page 53
Stereo Audio SoC
15.0 REFLOW PROFILE AND STORAGE CONDITION
15.1 STENCIL OF SMT ASSEMBLY SUGGESTION
15.1.1 STENCIL TYPE & THICKNESS
Laser cutting
Stainless steel
Thickened
0.5 mm Pitch: thickness < 0.15 mm
15.1.2 APERTURE SIZE AND SHAPE FOR TERMINAL PAD
Aspect ratio (width/thickness) > 1.5
Aperture shape
The stencil aperture is typically designed to match the pad size on the PCB.
Oval-shaped opening should be used to get the optimum paste release.
Rounded corners to minimize clogging.
Positive taper walls (5o tapering) with bottom opening larger than the top.
15.1.3 APERTURE DESIGN FOR THERMAL PAD
The small multiple openings should be used in steady of one big opening.
60~80% solder paste coverage
Rounded corners to minimize clogging
Positive taper walls (5° tapering) with bottom opening larger than the top
Don’t recommend
Recommend
Recommend
Coverage 91%
Coverage 77%
Coverage 65%
Stencil
PCB
Page 54
Stereo Audio SoC
15.2 REFLOW CONDITION
1.) Follow : IPC/JEDEC J-STD-020
2.) Condition :
Average ramp-up rate (217℃ to peak): 1~2℃/sec max.
Preheat：150~200C、60~180 seconds
Temperature maintained above 217℃ : 60~150 seconds
Time within 5℃ of actual peak temperature: 20 ~ 40 sec.
Peak temperature：260 +5/-0 ℃
Ramp-down rate : 3℃/sec. max.
Time 25℃ to peak temperature : 8 minutes max.
Cycle interval：5 minus
FIGURE 15-1: REFLOW PROFILE
peak: 260 +5/-0℃
Slope: 1~2℃/sec max.
(217℃ to peak)
Ramp down rate :
Max. 3℃/sec.
217℃
Preheat: 150~200℃
20~40 sec.
60 ~150sec
60 ~ 180 sec.
25℃
Time (sec)
Page 55
Stereo Audio SoC
15.3 STORAGE CONDITION
1. Calculated shelf life in sealed bag: 24 months at < 40 ℃ and <90% relative humidity (RH)
2. After bag is opened, devices that will be subjected to reflow solder or other high temperature process
must be Mounted within 168 hours of factory conditions <30℃/60% RH
FIGURE 15-2: LABEL OF CHIP BAG
(Please notice the baking requirement)
Page 56
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