KSZ8081RNA_技术文档

KSZ8081RNA/RND

10BASE-T/100BASE-TX PHY with RMII

Support

Features

Target Applications

• Single-Chip 10BASE-T/100BASE-TX IEEE 802.3

Compliant Ethernet Transceiver

• Game Consoles

• IP Phones

• IP Set-Top Boxes

• IP TVs

• RMII v1.2 Interface Support with a 50 MHz Refer-

ence Clock Output to MAC, and an Option to

Input a 50 MHz Reference Clock

• LOM

• RMII Back-to-Back Mode Support for a 100 Mbps

Copper Repeater

• Printers

• MDC/MDIO Management Interface for PHY Reg-

ister Configuration

• Programmable Interrupt Output

• LED Outputs for Link and Activity Status Indica-

tion

• On-Chip Termination Resistors for the Differential

Pairs

• Baseline Wander Correction

• HP Auto MDI/MDI-X to Reliably Detect and Cor-

rect Straight-Through and Crossover Cable Con-

nections with Disable and Enable Option

• Auto-Negotiation to Automatically Select the

Highest Link-Up Speed (10/100 Mbps) and

Duplex (Half/Full)

• Power-Down and Power-Saving Modes

• LinkMD^®TDR-Based Cable Diagnostics to Iden-

tify Faulty Copper Cabling

• Parametric NAND Tree Support for Fault Detec-

tion Between Chip I/Os and the Board

• HBM ESD Rating (6 kV)

• Loopback Modes for Diagnostics

• Single 3.3V Power Supply with V_DDI/O Options

for 1.8V, 2.5V, or 3.3V

• Built-In 1.2V Regulator for Core

• Available in 24-pin 4 mm x 4 mm QFN Package

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DS00002199A-page 1

KSZ8081RNA/RND

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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).

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DS00002199A-page 2

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

Table of Contents

1.0 Introduction ..................................................................................................................................................................................... 4

2.0 Pin Description and Configuration .................................................................................................................................................. 5

3.0 Functional Description .................................................................................................................................................................. 10

4.0 Register Descriptions .................................................................................................................................................................... 26

5.0 Operational Characteristics ........................................................................................................................................................... 35

6.0 Electrical Characteristics ............................................................................................................................................................... 36

7.0 Timing Diagrams............................................................................................................................................................................ 38

8.0 Reset Circuit .................................................................................................................................................................................. 42

9.0 Reference Circuits - LED Strap-In Pins ......................................................................................................................................... 43

10.0 Reference Clock - Connection and Selection .............................................................................................................................. 44

11.0 Magnetic - Connection and Selection .......................................................................................................................................... 45

12.0 Package Outlines......................................................................................................................................................................... 47

Appendix A: Data Sheet Revision History ........................................................................................................................................... 48

The Microchip Web Site ...................................................................................................................................................................... 49

Customer Change Notification Service ............................................................................................................................................... 49

Customer Support ............................................................................................................................................................................... 49

Product Identification System ............................................................................................................................................................. 50

 2016 Microchip Technology Inc.

DS00002199A-page 3

KSZ8081RNA/RND

1.0

1.1

INTRODUCTION

General Description

The KSZ8081RNA/RND is a single-supply 10BASE-T/100BASE-TX Ethernet physical-layer transceiver for transmis-

sion and reception of data over standard CAT-5 unshielded twisted pair (UTP) cable.

The KSZ8081RNA/RND is a highly-integrated PHY solution. It reduces board cost and simplifies board layout by using

on-chip termination resistors for the differential pairs and by integrating a low-noise regulator to supply the 1.2V core,

and by offering 1.8/2.5/3.3V digital I/O interface support.

The KSZ8081RNA/RND offers the Reduced Media Independent Interface (RMII) for direct connection to RMII-compliant

MACs in Ethernet processors and switches.

As the power-up default, the KSZ8081RNA/RND uses a 25 MHz crystal to generate all required clocks, including the

50 MHz RMII reference clock output for the MAC. The KSZ8081RND is the version that takes in the 50 MHz RMII ref-

erence clock as the power-up default.

To facilitate system bring-up and debugging in production testing and in product deployment, parametric NAND tree sup-

port enables fault detection between KSZ8081RNA/RND I/Os and the board. LinkMD^®TDR-based cable diagnostics

identify faulty copper cabling.

The KSZ8081RNA and KSZ8081RND are available in 24-pin, lead-free QFN packages.

FIGURE 1-1:

SYSTEM BLOCK DIAGRAM

MDC/MDIO

MANAGEMENT

MEDIA TYPES:

10BASE-T

100BASE-TX

RMII

RJ-45

CONNECTOR

10/100Mbps

RMII MAC

KSZ8081RNA

50MHz

REF_CLK

XO

XI

25MHz

XTAL

22pF

DS00002199A-page 4

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KSZ8081RNA/RND

2.0

PIN DESCRIPTION AND CONFIGURATION

FIGURE 2-1:

24-QFN PIN ASSIGNMENT (TOP VIEW)

22

19

24

23

21

20

INTRP

RXER

VDD_1.2

1

2

3

4

18

17

16

15

VDDA_3.3

RXM

REF_CLK

PADDLE GROUND

(ON BOTTOM OF CHIP)

CRS_DV/

PHYAD[1:0]

RXP

TXM

TXP

VDDIO

RXD0

5

6

14

13

9

10

11

12

7

8

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KSZ8081RNA/RND

TABLE 2-1:

SIGNALS - KSZ8081RNA/RND

Type

Number

Note

Name

2-1

Description

1.2V Core V_DD(power supplied by KSZ8081RNA/KSZ8081RND). Decouple

with 2.2 µF and 0.1 µF capacitors to ground.

1

VDD_1.2

P

2

3

4

5

6

VDDA_3.3

RXM

P

3.3V Analog V_DD.

I/O

Physical Receive or Transmit Signal (– differential).

Physical Receive or Transmit Signal (+ differential).

Physical Transmit or Receive Signal (– differential).

Physical Transmit or Receive Signal (+ differential).

RXP

TXM

TXP

Crystal Feedback for 25 MHz Crystal. This pin is a no connect if an oscillator

or external clock source is used.

7

XO

O

RMII – 25 MHz Mode: 25 MHz ±50 ppm Crystal/Oscillator/External Clock

Input

RMII – 50 MHz Mode: 50 MHz ±50 ppm Oscillator/External Clock Input

For unmanaged mode (power-up default setting):

– KSZ8081RNA takes in the 25 MHz crystal/clock on this pin.

– KSZ8081RND takes in the 50 MHz clock on this pin.

8

XI

I

After power-up, both the KSZ8081RNA and KSZ8081RND can be pro-

grammed to either the 25 MHz mode or 50 MHz mode using PHY Register

1Fh Bit [7].

See also XI (Pin 8).

RMII Receive Error Output.

At the de-assertion of reset, this pin needs to latch in a pull-down value for

normal operation. If MAC side pulls this pin high, see Register 16h, Bit [15] for

solution. It is better having an external pull-down resistor to avoid MAC side

pulls this pin high.

17

18

RXER

INTRP

Ipd/O

Ipu/

Opu

Interrupt Output: Programmable interrupt output. This pin has a weak pull-up,

is open drain, and requires an external 1.0 kꢀ pull-up resistor.

19

20

TXEN

TXD0

I

RMII Transmit Enable Input.

RMII Transmit Data Input [0] (Note 2-3).

RMII Transmit Data Input [1] (Note 2-3).

NAND Tree Mode: NAND Tree output pin.

21

22

TXD1

GND

I/O

GND

Ground.

LED Output: Programmable LED0 Output.

Config. Mode: Latched as auto-negotiation enable (Register 0h, Bit [12]) and

Speed (Register 0h, Bit [13]) at the de-assertion of reset. See the Strapping

Options section for details.

The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined

as follows:

LED Mode = [00]

Link/Activity

Pin State

High

LED Definition

OFF

No Link

LED0/

ANEN_SPEED

23

Ipu/O

Link

Low

ON

Activity

Toggle

Blinking

LED Mode = [01]

Link

Pin State

High

LED Definition

No Link

OFF

ON

Link

Low

LED Mode = [10], [11]: Reserved

Chip Reset (active-low).

24

RST#

Ipu

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KSZ8081RNA/RND

TABLE 2-1:

SIGNALS - KSZ8081RNA/RND (CONTINUED)

Type

Note

2-1

Number

Name

Description

Paddle

GND

Ground.

Note 2-1

P = power supply

GND = ground

I = input

O = output

I/O = bi-directional

Ipu = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value).

Ipu/O = Input with internal pull-up (see Section 6.0, "Electrical Characteristics" for value) during

power-up/reset; output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

Ipu/Opu = Input with internal pull-up (see Electrical Characteristics for value) and output with internal

pull-up (see Electrical Characteristics for value).

Note 2-2

Note 2-3

RMII RX Mode: The RXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each

clock period in which CRS_DV is asserted, two bits of recovered data are sent by the PHY to the

MAC.

RMII TX Mode: The TXD[1:0] bits are synchronous with the 50 MHz RMII Reference Clock. For each

clock period in which TXEN is asserted, two bits of data are received by the PHY from the MAC.

DS00002199A-page 8

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KSZ8081RNA/RND

The PHYAD[1:0] strap-in pin is latched at the de-assertion of reset. In some systems, the RMII MAC receive input pins

may drive high/low during power-up or reset, and consequently cause the PHYAD[1:0] strap-in pin, a shared pin with

the RMII CRS_DV signal, to be latched to the unintended high/low state. In this case an external pull-up (4.7 kꢀ) or pull-

down (1.0 kꢀ) should be added on the PHYAD[1:0] strap-in pin to ensure that the intended value is strapped-in correctly.

TABLE 2-2:

Pin Number

STRAP-IN OPTIONS - KSZ8081RNA/RND

Type

Pin Name

Description

Note 2-4

The PHY Address is latched at the de-assertion of reset and is con-

figurable to either one of the following two values:

Pull-up = PHY Address is set to 00011b (0x3h)

Pull-down (default) = PHY Address is set to 00000b (0x0h)

15

PHYAD[1:0]

Ipd/O

Ipu/O

PHY Address Bits [4:2] are set to 000 by default.

Auto-Negotiation Enable and SPEED Mode

Pull-up (default) = Enable Auto-Negotiation and set 100 Mbps Speed

Pull-down = Disable Auto-Negotiation and set 10 Mbps Speed

23

ANEN_SPEED

At the de-assertion of reset, this pin value is latched into Register 0h

Bit [12] for Auto-negotiation enable/disable, Register 0h Bit [13] for

the speed select, and Register 4h (Auto-Negotiation Advertisement)

for the speed capability support.

Note 2-4

Ipu/O = Input with internal pull-up (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

Ipd/O = Input with internal pull-down (see Electrical Characteristics for value) during power-up/reset;

output pin otherwise.

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KSZ8081RNA/RND

3.0

FUNCTIONAL DESCRIPTION

The KSZ8081RNA is an integrated, single 3.3V supply, fast Ethernet transceiver. It is fully compliant with the IEEE 802.3

Specification, and reduces board cost and simplifies board layout by using on-chip termination resistors for the two dif-

ferential pairs and by integrating the regulator to supply the 1.2V core.

On the copper media side, the KSZ8081RNA supports 10BASE-T and 100BASE-TX for transmission and reception of

data over a standard CAT-5 unshielded twisted pair (UTP) cable, and HP Auto MDI/MDI-X for reliable detection of and

correction for straight-through and crossover cables.

On the MAC processor side, the KSZ8081RNA offers the Reduced Media Independent Interface (RMII) for direct con-

nection with RMII-compliant Ethernet MAC processors and switches

The MII management bus option gives the MAC processor complete access to the KSZ8081RNA control and status

registers. Additionally, an interrupt pin eliminates the need for the processor to poll for PHY status change.

As the power-up default, the KSZ8081RNA uses a 25 MHz crystal to generate all required clocks, including the 50 MHz

RMII reference clock output for the MAC. The KSZ8081RND version uses the 50 MHz RMII reference clock as the

power-up default.

The KSZ8081RNA/RND is used to refer to both KSZ8081RNA and KSZ8081RND versions in this data sheet.

3.1

10BASE-T/100BASE-TX Transceiver

3.1.1

100BASE-TX TRANSMIT

The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B encoding, scrambling, NRZ-to-NRZI

conversion, and MLT3 encoding and transmission.

The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial

bit stream. The data and control stream is then converted into 4B/5B coding and followed by a scrambler. The serialized

data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is

set by an external 6.49 kꢀ 1% resistor for the 1:1 transformer ratio.

The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude

balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX

transmitter.

3.1.2

100BASE-TX RECEIVE

The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and

clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.

The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted

pair cable. Because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust

its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on

comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.

This is an ongoing process and self-adjusts against environmental changes such as temperature variations.

Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-

pensates for the effect of baseline wander and improves the dynamic range. The differential data-conversion circuit con-

verts MLT3 format back to NRZI. The slicing threshold is also adaptive.

The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then

used to convert the NRZI signal to NRZ format. This signal is sent through the de-scrambler, then the 4B/5B decoder.

Finally, the NRZ serial data is converted to MII format and provided as the input data to the MAC.

3.1.3

SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)

The scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic interference (EMI) and

baseline wander. The de-scrambler recovers the scrambled signal.

3.1.4

10BASE-T TRANSMIT

The 10BASE-T drivers are incorporated with the 100BASE-TX drivers to allow for transmission using the same mag-

netic. The drivers perform internal wave-shaping and pre-emphasis, and output 10BASE-T signals with typical ampli-

tude of 2.5V peak. The 10BASE-T signals have harmonic contents that are at least 27 dB below the fundamental

frequency when driven by an all-ones Manchester-encoded signal.

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KSZ8081RNA/RND

3.1.5

10BASE-T RECEIVE

On the receive side, input buffer and level detecting squelch circuits are used. A differential input receiver circuit and a

phase-locked loop (PLL) performs the decoding function. The Manchester-encoded data stream is separated into clock

signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV, or with short pulse widths, to prevent

noise at the RXP and RXM inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL

locks onto the incoming signal and the KSZ8081RNA/RND decodes a data frame. The receive clock is kept active

during idle periods between data receptions.

3.1.6

PLL CLOCK SYNTHESIZER

The KSZ8081RNA/RND in RMII – 25 MHz Clock mode generates all internal clocks and all external clocks for system

timing from an external 25 MHz crystal, oscillator, or reference clock. For the KSZ8081RNA/RND in RMII – 50 MHz

clock mode, these clocks are generated from an external 50 MHz oscillator or system clock.

3.1.7

AUTO-NEGOTIATION

The KSZ8081RNA/RND conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specifica-

tion.

Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the highest common mode of operation.

During auto-negotiation, link partners advertise capabilities across the UTP link to each other and then compare their

own capabilities with those they received from their link partners. The highest speed and duplex setting that is common

to the two link partners is selected as the mode of operation.

The following list shows the speed and duplex operation mode from highest to lowest priority.

• Priority 1: 100BASE-TX, full-duplex

• Priority 2: 100BASE-TX, half-duplex

• Priority 3: 10BASE-T, full-duplex

• Priority 4: 10BASE-T, half-duplex

If auto-negotiation is not supported or the KSZ8081RNA/RND link partner is forced to bypass auto-negotiation, then the

KSZ8081RNA/RND sets its operating mode by observing the signal at its receiver. This is known as parallel detection,

which allows the KSZ8081RNA/RND to establish a link by listening for a fixed signal protocol in the absence of the auto-

negotiation advertisement protocol.

Auto-negotiation is enabled by either hardware pin strapping (ANEN_SPEED, Pin 23) or software (Register 0h, Bit [12]).

By default, auto-negotiation is enabled after power-up or hardware reset. After that, auto-negotiation can be enabled or

disabled by Register 0h, Bit [12]. If auto-negotiation is disabled, the speed is set by Register 0h, Bit [13], and the duplex

is set by Register 0h, Bit [8].

The auto-negotiation link-up process is shown in Figure 3-1.

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DS00002199A-page 11

KSZ8081RNA/RND

FIGURE 3-1:

AUTO-NEGOTIATION FLOW CHART

START AUTO-NEGOTIATION

PARALLEL

OPERATION

FORCE LINK SETTING

YES

NO

ATTEMPT AUTO-

NEGOTIATION

LISTEN FOR 100BASE-TX

IDLES

LISTEN FOR 10BASE-T

LINK PULSES

BYPASS AUTO-NEGOTIATION

AND SET LINK MODE

NO

JOIN FLOW

LINK MODE SET?

YES

LINK MODE SET

3.2

RMII Interface

The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). It pro-

vides a common interface between physical layer and MAC layer devices, and has the following key characteristics:

• Pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50 MHz reference

clock).

• 10 Mbps and 100 Mbps data rates are supported at both half- and full-duplex.

• Data transmission and reception are independent and belong to separate signal groups.

• Transmit data and receive data are each 2 bits wide, a dibit.

3.2.1

RMII SIGNAL DEFINITION

Table 3-1 describes the RMII signals. Refer to RMII Specification v1.2 for detailed information.

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KSZ8081RNA/RND

TABLE 3-1:

RMII SIGNAL DEFINITION

Direction with

RMII Signal

Name

Direction with

Respect to PHY,

KSZ8081 Signal

Description

Respect to MAC

Output (25 MHz

Clock Mode)/

Input/

Synchronous 50 MHz reference clock for receive, trans-

REF_CLK

No Connect (50 MHz Input or No Connect mit, and control interface

Clock Mode)

TXEN

Input

Output

Input

Transmit Enable

TXD[1:0]

CRS_DV

RXD[1:0]

Transmit Data[1:0]

Output

Carrier Sense/Receive Data Valid

Receive Data[1:0]

Input

Input or

Not Required

RXER

Output

Receive Error

3.2.1.1

Reference Clock (REF_CLK)

REF_CLK is a continuous 50 MHz clock that provides the timing reference for TXEN, TXD[1:0], CRS_DV, RXD[1:0],

and RX_ER.

For RMII – 25 MHz Clock Mode, the KSZ8081RNA/RND generates and outputs the 50 MHz RMII REF_CLK to the MAC

at REF_CLK (Pin 16).

For RMII – 50 MHz Clock Mode, the KSZ8081RNA/RND takes in the 50 MHz RMII REF_CLK from the MAC or system

board at XI (Pin 8) and leaves the REF_CLK (Pin 16) as no connect.

3.2.1.2

Transmit Enable (TXEN)

TXEN indicates that the MAC is presenting dibits on TXD[1:0] for transmission. It is asserted synchronously with the first

dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the RMII. It is negated

before the first REF_CLK following the final dibit of a frame.

TXEN transitions synchronously with respect to REF_CLK.

3.2.1.3

Transmit Data[1:0] (TXD[1:0])

TXD[1:0] transitions synchronously with respect to REF_CLK. When TXEN is asserted, the PHY accepts TXD[1:0] for

transmission.

TXD[1:0] is 00 to indicate idle when TXEN is de-asserted. The PHY ignores values other than 00 on TXD[1:0] while

TXEN is de-asserted.

3.2.1.4

Carrier Sense/Receive Data Valid (CRS_DV)

The PHY asserts CRS_DV when the receive medium is non-idle. It is asserted asynchronously when a carrier is

detected. This happens when squelch is passed in 10 Mbps mode, and when two non-contiguous 0s in 10 bits are

detected in 100 Mbps mode. Loss of carrier results in the de-assertion of CRS_DV.

While carrier detection criteria are met, CRS_DV remains asserted continuously from the first recovered dibit of the

frame through the final recovered dibit. It is negated before the first REF_CLK that follows the final dibit. The data on

RXD[1:0] is considered valid after CRS_DV is asserted. However, because the assertion of CRS_DV is asynchronous

relative to REF_CLK, the data on RXD[1:0] is 00 until receive signals are properly decoded.

3.2.1.5

Receive Data[1:0] (RXD[1:0])

RXD[1:0] transitions synchronously with respect to REF_CLK. For each clock period in which CRS_DV is asserted,

RXD[1:0] transfers two bits of recovered data from the PHY.

RXD[1:0] is 00 to indicate idle when CRS_DV is de-asserted. The MAC ignores values other than 00 on RXD[1:0] while

CRS_DV is de-asserted.

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DS00002199A-page 13

KSZ8081RNA/RND

3.2.1.6

Receive Error (RXER)

RXER is asserted for one or more REF_CLK periods to indicate that a symbol error (for example, a coding error that a

PHY can detect that may otherwise be undetectable by the MAC sub-layer) was detected somewhere in the frame being

transferred from the PHY.

RXER transitions synchronously with respect to REF_CLK. While CRS_DV is de-asserted, RXER has no effect on the

MAC.

3.2.1.7

Collision Detection (COL)

The MAC regenerates the COL signal of the MII from TXEN and CRS_DV.

3.2.2

RMII SIGNAL DIAGRAM – 25/50 MHZ CLOCK MODE

The KSZ8081RNA/RND RMII pin connections to the MAC for 25 MHz clock mode are shown in Figure 3-2. The con-

nections for 50 MHz clock mode are shown in Figure 3-3.

3.2.2.1

RMII – 25 MHz Clock Mode

The KSZ8081RNA is configured to RMII – 25 MHz clock mode after it is powered up or hardware reset with the following:

• A 25 MHz crystal connected to XI, XO (Pins 8, 7), or an external 25 MHz clock source (oscillator) connected to XI

The KSZ8081RND can optionally be configured to RMII – 25 MHz clock mode after it is powered up or hardware reset

and software programmed with the following:

• A 25 MHz crystal connected to XI, XO (Pins 8, 7), or an external 25 MHz clock source (oscillator) connected to XI

• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 25 MHz clock mode

FIGURE 3-2:

KSZ8081RNA/RND RMII INTERFACE (RMII - 25 MHZ CLOCK MODE)

'

RMII MAC

KSZ8081RNA/RND

CRS_DV

RXD[1:0]

RXER

CRS_DV

RXD[1:0]

RX_ER

TXEN

TX_EN

TXD[1:0]

REF_CLK

XO

XI

25MHz

XTAL

22pF

DS00002199A-page 14

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KSZ8081RNA/RND

3.2.2.2

RMII – 50 MHz Clock Mode

The KSZ8081RND is configured to RMII – 50 MHz clock mode after it is powered up or hardware reset with the follow-

ing:

• An external 50 MHz clock source (oscillator) connected to XI (Pin 8)

The KSZ8081RNA can optionally be configured to RMII – 50 MHz clock mode after it is powered up or hardware reset

and software programmed with the following:

• An external 50 MHz clock source (oscillator) connected to XI (Pin 8)

• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50 MHz clock mode

FIGURE 3-3:

KSZ8081RNA/RND RMII INTERFACE (RMII - 50 MHZ CLOCK MODE)

RMII MAC

KSZ8081RNA/RND

CRS_DV

RXD[1:0]

RXER

CRS_DV

RXD[1:0]

RX_ER

TXEN

TX_EN

TXD[1:0]

REF_CLK

XI

50MHz

OSC

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DS00002199A-page 15

KSZ8081RNA/RND

3.3

Back-to-Back Mode – 100 Mbps Copper Repeater

Two KSZ8081RNA/RND devices can be connected back-to-back to form a managed 100BASE-TX copper repeater.

FIGURE 3-4:

KSZ8081RNA/RND AND KSZ8081RNA/RND RMII BACK-TO-BACK COPPER

REPEATER

RxD

RXP/RXM

TXP/TXM

KSZ8081RNA/RND

(COPPER MODE)

TxD

XI

50MHz

OSC

XI

KSZ8081RNA/RND

(COPPER MODE)

TXP/TXM

RXP/RXM

TxD

RxD

3.3.1

RMII BACK-TO-BACK MODE

In RMII back-to-back mode, a KSZ8081RNA/RND interfaces with another KSZ8081RNA/RND to provide a 100 Mbps

copper repeater solution.

The KSZ8081RNA/RND devices are configured to RMII back-to-back mode after power-up or reset, and software pro-

gramming, with the following:

• A common 50 MHz reference clock connected to XI (Pin 8)

• Register 1Fh, Bit [7] programmed to ‘1’ to select RMII – 50 MHz clock mode for KSZ8081RNA

KSZ8081RND is set to RMII – 50 MHz clock mode as the default after power up or hardware reset.

• Register 16h, Bits [6] and [1] programmed to ‘1’ and ‘1’, respectively, to enable RMII back-to-back mode.

• RMII signals connected as shown in Table 3-2.

TABLE 3-2:

RMII SIGNAL CONNECTION FOR RMII BACK-TO-BACK MODE (100BASE-TX

COPPER REPEATER)

KSZ8081RNA/RND (100BASE-TX Copper)

[Device 2]

[Device 1]

Pin Name

Pin Number

Pin Type

Pin Name

Pin Number

Pin Type

CRS_DV

RXD1

RXD0

TXEN

TXD1

15

12

13

19

21

20

Output

Input

TXEN

TXD1

19

21

20

15

12

13

Input

TXD0

Input

CRS_DV

RXD1

Output

Input

TXD0

Input

RXD0

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KSZ8081RNA/RND

3.4

MII Management (MIIM) Interface

The KSZ8081RNA/RND supports the IEEE 802.3 MII management interface, also known as the Management Data

Input/Output (MDIO) interface. This interface allows an upper-layer device, such as a MAC processor, to monitor and

control the state of the KSZ8081RNA/RND. An external device with MIIM capability is used to read the PHY status and/

or configure the PHY settings. More details about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3

Specification.

The MIIM interface consists of the following:

• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).

• A specific protocol that operates across the physical connection mentioned earlier, which allows the external con-

troller to communicate with one or more PHY devices.

• A set of 16-bit MDIO registers. Registers [0:8] are standard registers, and their functions are defined in the IEEE

802.3 Specification. The additional registers are provided for expanded functionality. See the Register Map section

for details.

The KSZ8081RNA/RND supports only two unique PHY addresses. The PHYAD[1:0] strapping pin is used to select

either 0h or 3h as the unique PHY address for the KSZ8081RNA/RND device.

PHY address 0h is defined as the broadcast PHY address according to the IEEE 802.3 Specification, and can be used

to read/write to a single PHY device, or write to multiple PHY devices simultaneously. For the KSZ8081RNA/RND, PHY

address 0h defaults to the broadcast PHY address after power-up, but PHY address 0h can be disabled as the broad-

cast PHY address using software to assign it as a unique PHY address.

For applications that require two KSZ8081RNA/RND PHYs to share the same MDIO interface with one PHY set to

address 0h and the other PHY set to address 3h, use PHY address 0h (defaults to broadcast after power-up) to set both

PHYs’ Register 16h, Bit [9] to ‘1’ to assign PHY address 0h as a unique (non-broadcast) PHY address.

Table 3-3 shows the MII management frame format for the KSZ8081RNA/RND.

TABLE 3-3:

MII MANAGEMENT FRAME FORMAT FOR THE KSZ8081RNA/RND

Read/

PHY

REG

Start of

Frame

Preamble

Write OP Address Address TA

Code

Data Bits[15:0]

Idle

Bits[4:0] Bits[4:0]

Read

Write

32 1’s

01

10

01

000AA

RRRRR Z0

RRRRR 10

DDDDDDDD_DDDDDDDD

Z

3.5

Interrupt (INTRP)

INTRP (Pin 18) is an optional interrupt signal that is used to inform the external controller that there has been a status

update to the KSZ8081RNA/RND PHY register. Bits [15:8] of Register 1Bh are the interrupt control bits to enable and

disable the conditions for asserting the INTRP signal. Bits [7:0] of Register 1Bh are the interrupt status bits to indicate

which interrupt conditions have occurred. The interrupt status bits are cleared after reading Register 1Bh.

Bit [9] of Register 1Fh sets the interrupt level to active high or active low. The default is active low.

The MII management bus option gives the MAC processor complete access to the KSZ8081RNA/RND control and sta-

tus registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.

3.6

HP Auto MDI/MDI-X

HP Auto MDI/MDI-X configuration eliminates the need to decide whether to use a straight cable or a crossover cable

between the KSZ8081RNA/RND and its link partner. This feature allows the KSZ8081RNA/RND to use either type of

cable to connect with a link partner that is in either MDI or MDI-X mode. The auto-sense function detects transmit and

receive pairs from the link partner and assigns transmit and receive pairs to the KSZ8081RNA/RND accordingly.

HP Auto MDI/MDI-X is enabled by default. It is disabled by writing a ‘1’ to Register 1Fh, Bit [13]. MDI and MDI-X mode

is selected by Register 1Fh, Bit [14] if HP Auto MDI/MDI-X is disabled.

An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.

Table 3-4 shows how the IEEE 802.3 Standard defines MDI and MDI-X.

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KSZ8081RNA/RND

TABLE 3-4:

MDI/MDI-X PIN DESCRIPTION

MDI

MDI-X

RJ-45 Pin

Signal

RJ-45 Pin

Signal

1

2

3

6

TX+

TX–

RX+

RX–

1

2

3

6

RX+

RX–

TX+

TX–

3.6.1

STRAIGHT CABLE

A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-5 shows

a typical straight cable connection between a NIC card (MDI device) and a switch or hub (MDI-X device).

FIGURE 3-5:

TYPICAL STRAIGHT CABLE CONNECTION

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

1

TRANSMIT PAIR

RECEIVE PAIR

2

3

STRAIGHT

CABLE

3

4

RECEIVE PAIR

5

TRANSMIT PAIR

5

6

7

8

6

7

8

MODULAR CONNECTOR

(RJ-45)

MODULAR CONNECTOR

(RJ-45)

NIC

HUB

(REPEATER OR SWITCH)

3.6.2

CROSSOVER CABLE

A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.

Figure 3-6 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).

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KSZ8081RNA/RND

FIGURE 3-6:

TYPICAL CROSSOVER CABLE CONNECTION

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

10/100 ETHERNET

MEDIA DEPENDENT INTERFACE

1

CROSSOVER

CABLE

RECEIVE PAIR

2

RECEIVE PAIR

2

3

4

TRANSMIT PAIR

5

TRANSMIT PAIR

5

6

7

8

6

7

8

MODULAR CONNECTOR

(RJ-45)

HUB

(RJ-45)

HUB

(REPEATER OR SWITCH)

3.7

Loopback Mode

The KSZ8081RNA/RND supports the following loopback operations to verify analog and/or digital data paths.

• Local (digital) loopback

• Remote (analog) loopback

3.7.1

LOCAL (DIGITAL) LOOPBACK

This loopback mode checks the RMII transmit and receive data paths between the KSZ8081RNA/RND and the external

MAC, and is supported for both speeds (10/100 Mbps) at full-duplex.

The loopback data path is shown in Figure 3-7.

1. The RMII MAC transmits frames to the KSZ8081RNA/RND.

2. Frames are wrapped around inside the KSZ8081RNA/RND.

3. The KSZ8081RNA/RND transmits frames back to the RMII MAC.

4. Except the frames back to the RMII MAC, the transmit frames also go out from the copper port.

FIGURE 3-7:

LOCAL (DIGITAL) LOOPBACK

KSZ8081RNA/RND

AFE

PCS

RMII

MAC

RMII

(ANALOG)

(DIGITAL)

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KSZ8081RNA/RND

The following programming action and register settings are used for local loopback mode:

For 10/100 Mbps loopback:

Set Register 0h,

Bit [14] = 1

// Enable local loopback mode

Bit [13] = 0/1 // Select 10 Mbps/100 Mbps speed

Bit [12] = 0

Bit [8] = 1

// Disable auto-negotiation

// Select full-duplex mode

Follow the steps below if you don’t want the frames go out from the copper port in the local loopback.

1. Set register 1Fh bit [3] to ‘1’ to disable the transmitter.

2. Run local loopback test as above.

3. Set register 1Fh bit [3] to ‘0’ to enable the transmitter.

3.7.2

REMOTE (ANALOG) LOOPBACK

This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and

receive data paths between the KSZ8081RNA/RND and its link partner, and is supported for 100BASE-TX full-duplex

mode only.

The loopback data path is shown in Figure 3-8.

1. The Fast Ethernet (100BASE-TX) PHY link partner transmits frames to the KSZ8081RNA/RND.

2. Frames are wrapped around inside the KSZ8081RNA/RND.

3. The KSZ8081RNA/RND transmits frames back to the Fast Ethernet (100BASE-TX) PHY link partner.

FIGURE 3-8:

REMOTE (ANALOG) LOOPBACK

KSZ8081RNA/RND

AFE

(ANALOG)

PCS

(DIGITAL)

RMII

RJ-45

CAT-5

(UTP)

100BASE-TX

LINK PARTNER

RJ-45

The following programming steps and register settings are used for remote loopback mode:

1. Set Register 0h,

Bits [13] = 1 // Select 100Mbps speed

Bit [12] = 0 // Disable auto-negotiation

Bit [8] = 1

// Select full-duplex mode

Or just auto-negotiate and link up at 100BASE-TX full-duplex mode with the link partner.

2. Set Register 1Fh,

Bit [2] = 1

// Enable remote loopback mode

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KSZ8081RNA/RND

3.8

LinkMD^®Cable Diagnostic

The LinkMD function uses time-domain reflectometry (TDR) to analyze the cabling plant for common cabling problems.

These include open circuits, short circuits, and impedance mismatches.

LinkMD works by sending a pulse of known amplitude and duration down the MDI or MDI-X pair, then analyzing the

shape of the reflected signal to determine the type of fault. The time duration for the reflected signal to return provides

the approximate distance to the cabling fault. The LinkMD function processes this TDR information and presents it as

a numerical value that can be translated to a cable distance.

LinkMD is initiated by accessing Register 1Dh, the LinkMD Control/Status register, in conjunction with Register 1Fh, the

PHY Control 2 register. The latter register is used to disable Auto MDI/MDI-X and to select either MDI or MDI-X as the

cable differential pair for testing.

3.8.1

USAGE

The following is a sample procedure for using LinkMD with Registers 1Dh and 1Fh:

1. Disable auto MDI/MDI-X by writing a ‘1’ to Register 1Fh, bit [13].

2. Start cable diagnostic test by writing a ‘1’ to Register 1Dh, bit [15]. This enable bit is self-clearing.

3. Wait (poll) for Register 1Dh, bit [15] to return a ‘0’, and indicating cable diagnostic test is completed.

4. Read cable diagnostic test results in Register 1Dh, bits [14:13]. The results are as follows:

00 = normal condition (valid test)

01 = open condition detected in cable (valid test)

10 = short condition detected in cable (valid test)

11 = cable diagnostic test failed (invalid test)

The ‘11’ case, invalid test, occurs when the device is unable to shut down the link partner. In this instance, the test is

not run, since it would be impossible for the device to determine if the detected signal is a reflection of the signal gen-

erated or a signal from another source.

5. Get distance to fault by concatenating Register 1Dh, bits [8:0] and multiplying the result by a constant of 0.38.

The distance to the cable fault can be determined by the following formula:

EQUATION 3-1:

·

DDistance to cable fault in meters = 0.38  Register 1Dh, bits[8:0]

Concatenated value of Registers 1Dh bits [8:0] should be converted to decimal before multiplying by 0.38.

The constant (0.38) may be calibrated for different cabling conditions, including cables with a velocity of propagation

that varies significantly from the norm.

3.9

NAND Tree Support

The KSZ8081RNA/RND provides parametric NAND tree support for fault detection between chip I/Os and board. The

NAND tree is a chain of nested NAND gates in which each KSZ8081RNA/RND digital I/O (NAND tree input) pin is an

input to one NAND gate along the chain. At the end of the chain, the TXD1 pin provides the output for the nested NAND

gates.

The NAND tree test process includes:

• Enabling NAND tree mode

• Pulling all NAND tree input pins high

• Driving each NAND tree input pin low, sequentially, according to the NAND tree pin order

• Checking the NAND tree output to make sure there is a toggle high-to-low or low-to-high for each NAND tree input

driven low

Table 3-5 lists the NAND tree pin order.

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DS00002199A-page 21

KSZ8081RNA/RND

TABLE 3-5:

NAND TREE TEST PIN ORDER FOR KSZ8081RNA/RND

Pin Number

Pin Name

NAND Tree Description

10

11

12

13

15

16

18

19

23

20

21

MDIO

MDC

Input

Output

RXD1

RXD0

CRS_DV

REF_CLK

INTRP

TXEN

LED0

TXD0

TXD1

3.9.1

NAND TREE I/O TESTING

Use the following procedure to check for faults on the KSZ8081RNA/RND digital I/O pin connections to the board:

1. Enable NAND tree mode by setting Register 16h, Bit [5] to ‘1’.

2. Use board logic to drive all KSZ8081RNA/RND NAND tree input pins high.

3. Use board logic to drive each NAND tree input pin, in KSZ8081RNA/RND tree pin order, as follows:

a) Toggle the first pin (MDIO) from high to low, and verify that the TDX1 pin switches from high to low to indicate

that the first pin is connected properly.

b) Leave the first pin (MDIO) low.

c) Toggle the second pin (MDC) from high to low, and verify that the TXD1 pin switches from low to high to

indicate that the second pin is connected properly.

d) Leave the first pin (MDIO) and the second pin (MDC) low.

e) Toggle the third pin from high to low, and verify that the TXD1 pin switches from high-to-low to indicate that

the third pin is connected properly.

f) Continue with this sequence until all KSZ8081RNA/RND NAND tree input pins have been toggled.

Each KSZ8081RNA/RND NAND tree input pin must cause the TXD1 output pin to toggle high-to-low or low-to-high to

indicate a good connection. If the TXD1 pin fails to toggle when the KSZ8081RNA/RND input pin toggles from high to

low, the input pin has a fault.

3.10 Power Management

The KSZ8081RNA/RND incorporates a number of power-management modes and features that provide methods to

consume less energy. These are discussed in the following sections.

3.10.1

POWER-SAVING MODE

Power-saving mode is used to reduce the transceiver power consumption when the cable is unplugged. It is enabled

by writing a ‘1’ to Register 1Fh, Bit [10], and is in effect when auto-negotiation mode is enabled and the cable is discon-

nected (no link).

In this mode, the KSZ8081RNA/RND shuts down all transceiver blocks except the transmitter, energy detect, and PLL

circuits.

By default, power-saving mode is disabled after power-up.

3.10.2

ENERGY-DETECT POWER-DOWN MODE

Energy-detect power-down (EDPD) mode is used to further reduce transceiver power consumption when the cable is

unplugged. It is enabled by writing a ‘0’ to Register 18h, Bit [11], and is in effect when auto-negotiation mode is enabled

and the cable is disconnected (no link).

EDPD mode works with the PLL off (set by writing a ‘1’ to Register 10h, Bit [4] to automatically turn the PLL off in EDPD

mode) to turn off all KSZ8081RNA/RND transceiver blocks except the transmitter and energy-detect circuits.

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KSZ8081RNA/RND

Power can be reduced further by extending the time interval between transmissions of link pulses to check for the pres-

ence of a link partner. The periodic transmission of link pulses is needed to ensure two link partners in the same low

power state and with auto MDI/MDI-X disabled can wake up when the cable is connected between them.

By default, energy-detect power-down mode is disabled after power-up.

3.10.3

POWER-DOWN MODE

Power-down mode is used to power down the KSZ8081RNA/RND device when it is not in use after power-up. It is

enabled by writing a ‘1’ to Register 0h, Bit [11].

In this mode, the KSZ8081RNA/RND disables all internal functions except the MII management interface. The

KSZ8081RNA/RND exits (disables) power-down mode after Register 0h, Bit [11] is set back to ‘0’.

3.10.4

SLOW-OSCILLATOR MODE

Slow-oscillator mode is used to disconnect the input reference crystal/clock on XI (Pin 8) and select the on-chip slow

oscillator when the KSZ8081RNA/RND device is not in use after power-up. It is enabled by writing a ‘1’ to Register 11h,

Bit[5].

Slow-oscillator mode works in conjunction with power-down mode to put the KSZ8081RNA/RND device in the lowest

power state, with all internal functions disabled except the MII management interface. To properly exit this mode and

return to normal PHY operation, use the following programming sequence:

1. Disable slow-oscillator mode by writing a ‘0’ to Register 11h, Bit [5].

2. Disable power-down mode by writing a ‘0’ to Register 0h, Bit [11].

3. Initiate software reset by writing a ‘1’ to Register 0h, Bit [15].

3.11 Reference Circuit for Power and Ground Connections

The KSZ8081RNA/RND is a single 3.3V supply device with a built-in regulator to supply the 1.2V core. The power and

ground connections are shown in Figure 3-9 and Table 3-6 for 3.3V VDDIO.

FIGURE 3-9:

KSZ8081RNA/RND POWER AND GROUND CONNECTIONS

FERRITE

BEAD

1

2.2μF

0.1μF

VDD_1.2

2

VDDA_3.3

22μF

0.1μF

KSZ8081RNA/RND

3.3V

VDDIO

14

22μF

0.1μF

GND

22 PADDLE

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KSZ8081RNA/RND

TABLE 3-6:

Power Pin

KSZ8081RNA/RND POWER PIN DESCRIPTION

Pin Number

Description

VDD_1.2

1

2

Decouple with 2.2 µF and 0.1 µF capacitors to ground.

VDDA_3.3

Connect to board’s 3.3V supply through a ferrite bead. Decouple with

22 µF and 0.1 µF capacitors to ground.

VDDIO

14

Connect to board’s 3.3V supply for 3.3V VDDIO. Decouple with 22 µF

and 0.1 µF capacitors to ground.

3.12 Typical Current/Power Consumption

Table 3-7, Table 3-8, and Table 3-9 show typical values for current consumption by the transceiver (VDDA_3.3) and dig-

ital I/O (VDDIO) power pins and typical values for power consumption by the KSZ8081RNA/RND device for the indi-

cated nominal operating voltage combinations. These current and power consumption values include the transmit driver

current and on-chip regulator current for the 1.2V core.

TABLE 3-7:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 3.3V)

3.3V Transceiver

(VDDA_3.3)

3.3V Digital I/Os

(VDDIO)

Condition

Total Chip Power

100BASE-TX Link-up (no traffic)

100BASE-TX Full-duplex @ 100% utilization

10BASE-T Link-up (no traffic)

34 mA

14 mA

30 mA

14 mA

10 mA

3.77 mA

12 mA

13 mA

11 mA

10 mA

1.54 mA

152 mW

155 mW

82.5 mW

135 mW

79.2 mW

66 mW

10BASE-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, Bit [10] = 1)

EDPD mode (Reg. 18h, Bit [11] = 0)

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1)

1.75 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

2.59 mA

1.36 mA

1.51 mA

0.45 mA

13.5 mW

5.97 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

and slow-oscillator mode (Reg. 11h, Bit [5] =1)

TABLE 3-8:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 2.5V)

3.3V Transceiver

(VDDA_3.3)

2.5V Digital I/Os

(VDDIO)

Condition

Total Chip Power

100BASE-TX Link-up (no traffic)

100BASE-TX Full-duplex @ 100% utilization

10BASE-T Link-up (no traffic)

34 mA

15 mA

27 mA

15 mA

11 mA

3.55 mA

12 mA

13 mA

11 mA

10 mA

1.35 mA

142 mW

145 mW

77 mW

10BASE-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, Bit [10] = 1)

EDPD mode (Reg. 18h, Bit [11] = 0)

117 mW

74.5 mW

61.3 mW

15.1 mW

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1)

Software power-down mode (Reg. 0h, Bit [11] =1)

2.29 mA

1.15 mA

1.34 mA

0.29 mA

10.9 mW

4.52 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

and slow-oscillator mode (Reg. 11h, Bit [5] =1)

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KSZ8081RNA/RND

TABLE 3-9:

TYPICAL CURRENT/POWER CONSUMPTION (VDDA_3.3 = 3.3V, VDDIO = 1.8V)

3.3V Transceiver

(VDDA_3.3)

1.8V Digital I/Os

(VDDIO)

Condition

Total Chip Power

100BASE-TX Link-up (no traffic)

100BASE-TX Full-duplex @ 100% utilization

10BASE-T Link-up (no traffic)

34 mA

15 mA

27 mA

15 mA

11 mA

4.05 mA

11 mA

12 mA

10 mA

9 mA

132 mW

134 mW

67.5 mW

107 mW

65.7 mW

52.5 mW

15.5 mW

10BASE-T Full-duplex @ 100% utilization

Power-saving mode (Reg. 1Fh, Bit [10] = 1)

EDPD mode (Reg. 18h, Bit [11] = 0)

9 mA

EDPD mode (Reg. 18h, Bit [11] = 0) and

PLL off (Reg. 10h, Bit [4] = 1)

1.21 mA

Software power-down mode (Reg. 0h, Bit [11] =1)

2.79 mA

1.65 mA

1.21 mA

0.19 mA

11.4 mW

5.79 mW

Software power-down mode (Reg. 0h, Bit [11] =1)

and slow-oscillator mode (Reg. 11h, Bit [5] =1)

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KSZ8081RNA/RND

4.0

REGISTER DESCRIPTIONS

This chapter describes the various control and status registers (CSRs).

4.1

Register Map

TABLE 4-1:

REGISTERS SUPPORTED BY KSZ8081RNA/RND

Register Number (hex)

Description

0h

1h

Basic Control

Basic Status

2h

PHY Identifier 1

3h

PHY Identifier 2

4h

Auto-Negotiation Advertisement

Auto-Negotiation Link Partner Ability

Auto-Negotiation Expansion

Auto-Negotiation Next Page

Link Partner Next Page Ability

Reserved

5h

6h

7h

8h

9h

10h

11h

12h - 14h

15h

16h

17h

18h

19h - 1Ah

1Bh

1Ch

1Dh

1Eh

1Fh

Digital Reserved Control

AFE Control 1

Reserved

RXER Counter

Operation Mode Strap Override

Operation Mode Strap Status

Expanded Control

Reserved

Interrupt Control/Status

Reserved

LinkMD Control/Status

PHY Control 1

PHY Control 2

4.2

Register Descriptions

TABLE 4-2:

REGISTER DESCRIPTIONS

Mode

Note 4-1

Address Name

Description

Default

Register 0h – Basic Control

0.15

Reset

1 = Software reset

0 = Normal operation

This bit is self-cleared after a ‘1’ is written to it.

RW/SC

0

0.14

0.13

Loopback

1 = Loopback mode

0 = Normal operation

RW

Speed Select 1 = 100Mbps

0 = 10Mbps

Set by the ANEN_-

SPEED strapping pin.

See the Strap-In

Options -

This bit is ignored if auto-negotiation is enabled

(Register 0.12 = 1).

KSZ8081RNA/RND

section for details.

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KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Description

Mode

Default

Note 4-1

Address Name

0.12

0.11

Auto-Negoti- 1 = Enable auto-negotiation process

ation Enable 0 = Disable auto-negotiation process

RW

Set by the ANEN_-

SPEED strapping pin.

See the Strap-In

Options -

KSZ8081RNA/RND

section for details.

If enabled, the auto-negotiation result overrides the

settings in Registers 0.13 and 0.8.

Power-Down 1 = Power-down mode

RW

0

0 = Normal operation

If software reset (Register 0.15) is used to exit

power-down mode (Register 0.11 = 1), two soft-

ware reset writes (Register 0.15 = 1) are required.

The first write clears power-down mode; the sec-

ond write resets the chip and re-latches the pin

strapping pin values.

0.10

0.9

Isolate

1 = Electrical isolation of PHY from MII

0 = Normal operation

RW

0

Restart Auto- 1 = Restart auto-negotiation process

RW/SC

Negotiation

0 = Normal operation.

This bit is self-cleared after a ‘1’ is written to it.

0.8

Duplex Mode 1 = Full-duplex

0 = Half-duplex

RW

RO

1

0.7

Collision Test 1 = Enable COL test

0 = Disable COL test

0

0.6:0

Reserved

000_0000

Register 1h - Basic Status

1.15

1.14

1.13

1.12

1.11

100Base-T4 1 = T4 capable

0 = Not T4 capable

RO

0

1

100Base-TX 1 = Capable of 100Mbps full-duplex

Full-Duplex

0 = Not capable of 100Mbps full-duplex

100Base-TX 1 = Capable of 100Mbps half-duplex

Half-Duplex 0 = Not capable of 100Mbps half-duplex

10Base-T

1 = Capable of 10Mbps full-duplex

Full-Duplex

0 = Not capable of 10Mbps full-duplex

10Base-T

1 = Capable of 10Mbps half-duplex

Half-Duplex 0 = Not capable of 10Mbps half-duplex

1.10:7

1.6

Reserved Reserved

RO

000_0

1

No Preamble 1 = Preamble suppression

0 = Normal preamble

1.5

Auto-Negoti- 1 = Auto-negotiation process completed

RO

0

ation Com-

plete

0 = Auto-negotiation process not completed

1.4

1.3

1.2

1.1

Remote Fault 1 = Remote fault

0 = No remote fault

RO/LH

RO

0

1

0

Auto-Negoti- 1 = Can perform auto-negotiation

ation Ability

0 = Cannot perform auto-negotiation

Link Status

1 = Link is up

RO/LL

RO/LH

0 = Link is down

Jabber

Detect

1 = Jabber detected

0 = Jabber not detected (default is low)

 2016 Microchip Technology Inc.

DS00002199A-page 27

KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

1.0

Extended

Capability

Register 2h - PHY Identifier 1

1 = Supports extended capability registers

RO

1

2.15:0

PHY ID

Number

Assigned to the 3rd through 18th bits of the Organi- RO

zationally Unique Identifier (OUI). KENDIN Com-

munication’s OUI is 0010A1 (hex).

0022h

Register 3h - PHY Identifier 2

3.15:10

PHY ID Num- Assigned to the 19th through 24th bits of the Orga- RO

0001_01

01_0110

ber

nizationally Unique Identifier (OUI). KENDIN Com-

munication’s OUI is 0010A1 (hex).

3.9:4

3.3:0

Model Num- Six-bit manufacturer’s model number

ber

RO

Revision

Number

Four-bit manufacturer’s revision number

Indicates silicon revi-

sion to Rev. A; A2 =

0x0, A3 = 0x1.

Register 4h - Auto-Negotiation Advertisement

4.15

RW

1

0 = No next page capability

Note: Recommend to set this bit to ‘0’.

4.14

4.13

Reserved

RO

RW

0

Remote Fault 1 = Remote fault supported

0 = No remote fault

4.12

Reserved

Pause

Reserved

RO

RW

0

4.11:10

[00] = No pause

00

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

4.9

4.8

100BASE-T4 1 = T4 capable

0 = No T4 capability

100BASE-TX 1 = 100Mbps full-duplex capable

Full-Duplex 0 = No 100Mbps full-duplex capability

RO

RW

0

Set by the ANEN_-

SPEED strapping pin.

See the Strap-In

Options -

KSZ8081RNA/RND

section for details.

4.7

100BASE-TX 1 = 100Mbps half-duplex capable

Half-Duplex 0 = No 100Mbps half-duplex capability

RW

Set by the ANEN_-

SPEED strapping pin.

See the Strap-In

Options -

KSZ8081RNA/RND

section for details.

4.6

10BASE-T

Full-Duplex

1 = 10Mbps full-duplex capable

0 = No 10Mbps full-duplex capability

RW

1

4.5

10BASE-T

1 = 10Mbps half-duplex capable

1

Half-Duplex 0 = No 10Mbps half-duplex capability

4.4:0

Selector

Field

[00001] = IEEE 802.3

0_0001

Register 5h - Auto-Negotiation Link Partner Ability

5.15

RO

0

0 = No next page capability

DS00002199A-page 28

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Description

Mode

Default

Note 4-1

Address Name

5.14

5.13

Acknowledge 1 = Link code word received from partner

0 = Link code word not yet received

RO

0

Remote Fault 1 = Remote fault detected

0 = No remote fault

RO

0

5.12

Reserved

Pause

Reserved

RO

0

5.11:10

[00] = No pause

00

[10] = Asymmetric pause

[01] = Symmetric pause

[11] = Asymmetric and symmetric pause

5.9

100Base-T4 1 = T4 capable

0 = No T4 capability

100Base-TX 1 = 100Mbps full-duplex capable

Full-Duplex 0 = No 100Mbps full-duplex capability

RO

0

5.8

0

5.7

100Base-TX 1 = 100Mbps half-duplex capable

Half-Duplex 0 = No 100Mbps half-duplex capability

0

5.6

5.5

5.4:0

10Base-T

1 = 10Mbps full-duplex capable

0

Full-Duplex

0 = No 10Mbps full-duplex capability

10Base-T

1 = 10Mbps half-duplex capable

0

Half-Duplex 0 = No 10Mbps half-duplex capability

Selector

Field

[00001] = IEEE 802.3

0_0001

Register 6h - Auto-Negotiation Expansion

6.15:5

6.4

Reserved

RO

0000_0000_000

0

Parallel

Detection

Fault

1 = Fault detected by parallel detection

0 = No fault detected by parallel detection

RO/LH

6.3

6.2

Link Partner 1 = Link partner has next page capability

RO

0

1

0 = Link partner does not have next page capability

1 = Local device has next page capability

0 = Local device does not have next page capabil-

ity

6.1

6.0

Page

Received

1 = New page received

0 = New page not received yet

RO/LH

RO

0

Link Partner 1 = Link partner has auto-negotiation capability

Auto-Negoti- 0 = Link partner does not have auto-negotiation

ation Able

capability

Register 7h - Auto-Negotiation Next Page

7.15

1 = Additional next pages will follow

0 = Last page

RW

0

7.14

7.13

Reserved

RO

RW

0

1

Message

Page

1 = Message page

0 = Unformatted page

7.12

7.11

Acknowl-

edge2

1 = Will comply with message

0 = Cannot comply with message

RW

RO

0

Toggle

1 = Previous value of the transmitted link code

word equaled logic 1

0 = Logic 0

 2016 Microchip Technology Inc.

DS00002199A-page 29

KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

7.10:0

Message

Field

Register 8h - Link Partner Next Page Ability

11-bit wide field to encode 2048 messages

RW

000_0000_0001

8.15

8.14

8.13

8.12

8.11

0 = Last page

RO

0

Acknowledge 1 = Successful receipt of link word

0 = No successful receipt of link word

Message

Page

1 = Message page

0 = Unformatted page

Acknowl-

edge2

1 = Can act on the information

0 = Cannot act on the information

Toggle

1 = Previous value of transmitted link code word

equal to logic 0

0 = Previous value of transmitted link code word

equal to logic 1

8.10:0

Message

Field

11-bit wide field to encode 2048 messages

RO

000_0000_0000

Register 10h – Digital Reserved Control

10.15:5

10.4

Reserved

PLL Off

Reserved

RW

0000_0000_000

0

1 = Turn PLL off automatically in EDPD mode

0 = Keep PLL on in EDPD mode.

See also Register 18h, Bit [11] for EDPD mode

10.3:0

Reserved

RW

0000

Register 11h – AFE Control 1

11.15:6

11.5

Reserved

RW

0000_0000_00

0

Slow-Oscilla- Slow-oscillator mode is used to disconnect the

tor Mode

Enable

input reference crystal/clock on the XI pin and

select the on-chip slow oscillator when the

KSZ8081RNA/RND device is not in use after

power-up.

1 = Enable

0 = Disable

This bit automatically sets software power-down to

the analog side when enabled.

11.4:0

Reserved

RW

0_0000

0000h

Register 15h – RXER Counter

15.15:0

RXER

Receive error counter for symbol error frames

RO/SC

Counter

Register 16h – Operation Mode Strap Override

16.15

Reserved

Factory

Mode

0 = Normal operation

1 = Factory test mode

If RXER (Pin 17) latches in a pull-up value at the

de-assertion of reset, write a ‘0’ to this bit to clear

Reserved Factory Mode.

RW

0

Set by the pull-up /

pull-down value of

RXER (Pin 17).

16.14:11

16.10

Reserved

B-

Reserved

RW

RO

RW

000_0

Reserved

0

16.9

1 = Override strap-in for B-CAST_OFF

CAST_OFF If bit is ‘1’, PHY Address 0 is non-broadcast.

Override

DS00002199A-page 30

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Note 4-1

Address Name

Description

16.8:7

16.6

Reserved

RW

0_0

0

RMII B-to-B 1 = Override strap-in for RMII back-to-back mode RW

Override

(also set Bit 1 of this register to ‘1’)

16.5

NAND Tree

Override

1 = Override strap-in for NAND tree mode

RW

0

16.4:2

16.1

Reserved

RW

0_00

1

RMII Over-

ride

1 = Override strap-in for RMII mode

16.0

Reserved

RW

RO

0

Register 17h - Operation Mode Strap Status

17.15:13

PHYAD[2:0] [000] = Strap to PHY Address 0

Strap-In Sta- [011] = Strap to PHY Address 3

tus

The KSZ8081RNA/RND supports only PHY

addresses 0h and 3h.

17.12:2

17.1

Reserved

RO

RMII Strap-In 1 = Strap to RMII mode

Status

17.0

Reserved

RO

Register 18h - Expanded Control

18.15:12

18.11

Reserved

RW

0000

1

EDPD Dis-

abled

Energy-detect power-down mode

1 = Disable

0 = Enable

See also Register 10h, Bit [4] for PLL off.

18.10:0

Reserved

RW

000_0000_0000

Register 1Bh – Interrupt Control/Status

1B.15

Jabber Inter- 1 = Enable jabber interrupt

RW

0

rupt Enable

0 = Disable jabber interrupt

1B.14

Receive

Error Inter-

rupt Enable

1 = Enable receive error interrupt

0 = Disable receive error interrupt

1B.13

1B.12

1B.11

Page

1 = Enable page received interrupt

0 = Disable page received interrupt

RW

0

Received

Interrupt

Enable

Parallel

1 = Enable parallel detect fault interrupt

Detect Fault 0 = Disable parallel detect fault interrupt

Interrupt

Enable

Link Partner 1 = Enable link partner acknowledge interrupt

Acknowl-

0 = Disable link partner acknowledge interrupt

edge Inter-

rupt Enable

1B.10

1B.9

Link-Down

Interrupt

Enable

1= Enable link-down interrupt

0 = Disable link-down interrupt

RW

0

RemoteFault 1 = Enable remote fault interrupt

Interrupt

Enable

0 = Disable remote fault interrupt

 2016 Microchip Technology Inc.

DS00002199A-page 31

KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

1B.8

Link-Up

Interrupt

Enable

1 = Enable link-up interrupt

0 = Disable link-up interrupt

RW

0

1B.7

1B.6

Jabber Inter- 1 = Jabber occurred

RO/SC

0

rupt

0 = Jabber did not occur

Receive

Error Inter-

rupt

1 = Receive error occurred

0 = Receive error did not occur

1B.5

1B.4

1B.3

Page

Receive

Interrupt

1 = Page receive occurred

0 = Page receive did not occur

RO/SC

0

Parallel

1 = Parallel detect fault occurred

Detect Fault 0 = Parallel detect fault did not occur

Interrupt

Link Partner 1 = Link partner acknowledge occurred

Acknowl-

edge Inter-

rupt

0 = Link partner acknowledge did not occur

1B.2

1B.1

1B.0

Link-Down

Interrupt

1 = Link-down occurred

0 = Link-down did not occur

RO/SC

0

RemoteFault 1 = Remote fault occurred

Interrupt

0 = Remote fault did not occur

Link-Up

Interrupt

1 = Link-up occurred

0 = Link-up did not occur

Register 1Dh – LinkMD Control/Status

1D.15

Cable Diag- 1 = Enable cable diagnostic test. After test has

RW/SC

RO

0

nostic Test

Enable

completed, this bit is self-cleared.

0 = Indicates cable diagnostic test (if enabled) has

completed and the status information is valid for

read.

1D.14:13

1D.12

Cable Diag- [00] = Normal condition

00

nostic Test

Result

[01] = Open condition has been detected in cable

[10] = Short condition has been detected in cable

[11] = Cable diagnostic test has failed

Short Cable 1 = Short cable (<10 meter) has been detected by RO

0

Indicator

LinkMD

1D.11:9

1D.8:0

Reserved

RW

RO

000

Cable Fault

Counter

Distance to fault

0_0000_0000

Register 1Eh – PHY Control 1

1E.15:10

1E.9

Reserved

Enable

Reserved

RO

0000_00

0

1 = Flow control capable

Pause (Flow 0 = No flow control capability

Control)

1E.8

1E.7

1E.6

Link Status

1 = Link is up

0 = Link is down

RO

0

Polarity Sta- 1 = Polarity is reversed

tus

0 = Polarity is not reversed

Reserved

0

DS00002199A-page 32

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

TABLE 4-2:

Address Name

1E.5 MDI/MDI-X

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Default

Note 4-1

Description

1 = MDI-X

0 = MDI

RO

State

1E.4

Energy

Detect

1 = Signal present on receive differential pair

0 = No signal detected on receive differential pair

RO

RW

RO

0

1E.3

PHY Isolate 1 = PHY in isolate mode

0 = PHY in normal operation

0

1E.2:0

Operation

[000] = Still in auto-negotiation

000

Mode Indica- [001] = 10Base-T half-duplex

tion

[010] = 100Base-TX half-duplex

[011] = Reserved

[100] = Reserved

[101] = 10Base-T full-duplex

[110] = 100Base-TX full-duplex

[111] = Reserved

Register 1Fh – PHY Control 2

1F.15

HP_MDIX

1 = HP Auto MDI/MDI-X mode

0 = Microchip Auto MDI/MDI-X mode

RW

1

0

1F.14

MDI/MDI-X

Select

When Auto MDI/MDI-X is disabled,

1 = MDI-X mode

Transmit on RXP,RXM (Pins 4, 3) and Receive on

TXP,TXM (Pins 6, 5)

0 = MDI mode

Transmit on TXP,TXM (Pins 6, 5) and Receive on

RXP,RXM (Pins 4, 3)

1F.13

Pair Swap

Disable

1 = Disable Auto MDI/MDI-X

0 = Enable Auto MDI/MDI-X

RW

0

1F.12

1F.11

Reserved

Force Link

Reserved

RW

0

1 = Force link pass

0 = Normal link operation

This bit bypasses the control logic and allows the

transmitter to send a pattern even if there is no link.

1F.10

1F.9

1F.8

1F.7

Power Sav-

ing

1 = Enable power saving

0 = Disable power saving

RW

0

1

0

Interrupt

Level

1 = Interrupt pin active high

0 = Interrupt pin active low

Enable Jab- 1 = Enable jabber counter

ber

0 = Disable jabber counter

RMII Refer-

ence Clock

Select

1 = For KSZ8081RNA, clock input to XI (Pin 8) is

50MHz for RMII – 50MHz clock mode.

For KSZ8081RND, clock input to XI (Pin 8) is

25MHz for RMII – 25MHz clock code.

0 = For KSZ8081RNA, clock input to XI (Pin 8) is

25MHz for RMII – 25MHz clock code.

For KSZ8081RND, clock input to XI (Pin 8) is

50MHz for RMII – 50MHz clock mode.

1F.6

Reserved

RW

0

1F.5:4

LED Mode

[00] = LED0: Link/Activity

[01] = LED0: Link

00

[10], [11] = Reserved

1F.3

Disable

Transmitter

1 = Disable transmitter

0 = Enable transmitter

RW

0

 2016 Microchip Technology Inc.

DS00002199A-page 33

KSZ8081RNA/RND

TABLE 4-2:

REGISTER DESCRIPTIONS (CONTINUED)

Mode

Note 4-1

Address Name

Description

Default

1F.2

Remote

Loopback

1 = Remote (analog) loopback is enabled

0 = Normal mode

RW

0

1F.1

1F.0

Reserved

RW

0

Disable Data 1 = Disable scrambler

Scrambling 0 = Enable scrambler

RW = Read/Write; RO = Read Only; SC = Self-Cleared; LH = Latch High; LL = Latch Low.

Note 4-1

DS00002199A-page 34

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

5.0

5.1

OPERATIONAL CHARACTERISTICS

Absolute Maximum Ratings*

Supply Voltage (V_IN)

(V_{DD_1.2}).................................................................................................................................................... –0.5V to +1.8V

(V_DDIO, V_{DDA_3.3})...................................................................................................................................... –0.5V to +5.0V

Input Voltage (all inputs)............................................................................................................................ –0.5V to +5.0V

Output Voltage (all outputs)....................................................................................................................... –0.5V to +5.0V

Lead Temperature (soldering, 10s)....................................................................................................................... +260°C

Storage Temperature (T_S)...................................................................................................................... –55°C to +150°C

*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating

may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-

ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect

reliability.

5.2

Operating Ratings**

Supply Voltage

(V_{DDIO_3.3}, V_{DDA_3.3}) ........................................................................................................................ +3.135V to +3.465V

(V_{DDIO_2.5}) ........................................................................................................................................ +2.375V to +2.625V

(V_{DDIO_1.8}) ........................................................................................................................................ +1.710V to +1.890V

Ambient Temperature

(T_ACommercial)...........................................................................................................................................0°C to +70°C

(T_AIndustrial) ...........................................................................................................................................–40°C to +85°C

Maximum Junction Temperature (T_Jmax.)........................................................................................................... +125°C

Thermal Resistance (Θ_JA)..............................................................................................................................+47.84°C/W

Thermal Resistance (Θ_JC) .............................................................................................................................+14.71°C/W

**The device is not guaranteed to function outside its operating ratings.

Note:

Do not drive input signals without power supplied to the device.

 2016 Microchip Technology Inc.

DS00002199A-page 35

KSZ8081RNA/RND

6.0

ELECTRICAL CHARACTERISTICS

T_A= 25°C. Specification is for packaged product only.

TABLE 6-1: ELECTRICAL CHARACTERISTICS

Parameters

Supply Current (V_DDIO, V_{DDA_3.3}= 3.3V), Note 6-1

Symbol

Min.

Typ.

Max.

Units

Note

10BASE-T

I_{DD1_3.3V}

I_{DD2_3.3V}

—

41

47

—

mA

Full-duplex traffic @ 100% utilization

100BASE-TX

Ethernet cable disconnected

(Reg. 18h.11 = 0)

EDPD Mode

I_{DD3_3.3V}

I_{DD4_3.3V}

—

20

4

—

mA

Software power-down

(Reg. 0h.11 = 1)

Power-Down Mode

CMOS Level Inputs

2.4

2.0

1.5

—

V

V_DDIO= 3.3V

Output High Voltage

Output Low Voltage

V_OH

V

_DDIO= 2.5V

_DDIO= 1.8V

—

V

0.4

0.3

10

V

V_DDIO= 3.3V

V_OL

|I_OZ

I_LED

—

V

_DDIO= 2.5V

_DDIO= 1.8V

—

V

Output Tri-State Leakage

LED Output

|

—

µA

Output Drive Current

—

8

—

mA

LED0 pin

All Pull-Up/Pull-Down Pins (including Strapping Pins)

30

39

48

26

34

53

45

61

99

43

59

99

73

102

178

79

kꢀ

V_DDIO= 3.3V

V_DDIO= 2.5V

Internal Pull-Up Resistance

pu

pd

V_DDIO= 1.8V

V_DDIO= 3.3V

Internal Pull-Down

Resistance

113

200

V_DDIO= 2.5V

V_DDIO= 1.8V

100BASE-TX Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

100ꢀ termination across differential

V_O

0.95

—

1.05

2

V

Voltage

output

100ꢀ termination across differential

Output Voltage Imbalance

V_IMB

%

output

Rise/Fall Time

Rise/Fall Time Imbalance

Duty Cycle Distortion

Overshoot

t_r/t_f

—

3

—

5

0.5

±0.25

5

ns

%

—

0

—

Output Jitter

0.7

—

ns

Peak-to-peak

10BASE-T Transmit (measured differentially after 1:1 transformer)

Peak Differential Output

100ꢀ termination across differential

V_P

2.2

—

2.8

V

Voltage

output

Jitter Added

—

3.5

—

ns

Peak-to-peak

—

Rise/Fall Time

t_r/t_f

25

10BASE-T Receive

Squelch Threshold

Transmitter - Drive Setting

Reference Voltage of I_SET

V_SQ

—

400

—

mV

V

5 MHz square wave

V_SET

0.65

R(I_SET) = 6.49 kꢀ

DS00002199A-page 36

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

TABLE 6-1:

ELECTRICAL CHARACTERISTICS (CONTINUED)

Parameters

Symbol

Min.

Typ.

Max.

Units

Note

REF_CLK Output

50 MHz RMII Clock Output

Jitter

Peak-to-peak. Applies only to RMII -

25 MHz Clock Mode.

—

300

—

ps

100 Mbps Mode - Industrial Applications Parameters

Link loss detected at receive

differential inputs to PHY signal

indication time for each of the

following:

Link Loss Reaction

(Indication) Time

t_llr

—

4.4

—

µs

1. For LED mode 01, Link LED output

changes from low (link-up) to high

(link-down).

2. INTRP pin asserts for link-down

status change.

Note 6-1

Current consumption is for the single 3.3V supply KSZ8081RNA/RND device only, and includes the

transmit driver current and the 1.2V supply voltage (V_{DD_1.2}) that are supplied by the KSZ8081RNA/

RND.

 2016 Microchip Technology Inc.

DS00002199A-page 37

KSZ8081RNA/RND

7.0

7.1

TIMING DIAGRAMS

RMII Timing

FIGURE 7-1:

RMII TIMING - DATA RECEIVED FROM RMII

t_CYC

TRANSMIT TIMING

REF_CLK

t₁

t₂

TXEN

TXD[1:0]

FIGURE 7-2:

RMII TIMING - DATA INPUT TO RMII

t_CYC

RECEIVE TIMING

REF_CLK

CRS_DV

RXD[1:0]

RXER

t_OD

TABLE 7-1:

Parameter

RMII TIMING PARAMETERS (25 MHZ INPUT TO XI PIN, 50 MHZ OUTPUT FROM

REF_CLK PIN)

Description

Min.

Typ.

Max.

Units

t_CYC

t₁

Clock cycle

Setup time

Hold time

—

4

20

—

10

—

13

ns

t₂

2

t_OD

Output delay

7

TABLE 7-2:

Parameter

RMII TIMING PARAMETERS (50 MHZ INPUT TO XI PIN)

Description

Min.

Typ.

Max.

Units

t_CYC

t₁

Clock cycle

Setup time

Hold time

—

4

20

—

11

—

13

ns

t₂

2

t_OD

Output delay

8

DS00002199A-page 38

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

7.2

Auto-Negotiation Timing

FIGURE 7-3:

AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING

AUTO -NEGOTIATION

FAST LINK PULSE (FLP) TIMING

FLP

BURST

FLP

BURST

TX+/TX-

t_FLPW

t_BTB

CLOCK

PULSE

DATA

PULSE

CLOCK

PULSE

DATA

PULSE

TX+/TX-

t_PW

t_CTD

t_CTC

TABLE 7-3:

Parameter

AUTO-NEGOTIATION FAST LINK PULSE TIMING PARAMETERS

Description

Min.

Typ.

Max.

Units

t_BTB

t_FLPW

t_PW

FLP burst to FLP burst

8

—

16

2

24

—

ms

ns

µs

—

FLP burst width

Clock/Data pulse width

—

100

64

—

t_CTD

t_CTC

—

Clock pulse to data pulse

Clock pulse to clock pulse

Number of clock/data pulses per FLP burst

55.5

111

17

69.5

139

33

128

—

 2016 Microchip Technology Inc.

DS00002199A-page 39

KSZ8081RNA/RND

7.3

MDC/MDIO Timing

FIGURE 7-4:

MDC/MDIO TIMING

t_P

MDC

t_MD1

t_MD2

MDIO

(PHY INPUT)

VALID

DATA

VALID

DATA

t_MD3

MDIO

(PHY OUTPUT)

VALID

DATA

TABLE 7-4:

Parameter

MDC/MDIO TIMING PARAMETERS

Description

Min.

Typ.

Max.

Units

fc

MDC Clock Frequency

MDC period

—

10

4

2.5

400

—

10

—

MHz

ns

t_P

t_MD1

t_MD2

t_MD3

MDIO (PHY input) setup to rising edge of MDC

ns

MDIO (PHY input) hold from rising edge of MDC

MDIO (PHY output) delay from rising edge of MDC

—

ns

5

222

ns

DS00002199A-page 40

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

7.4

Power-Up/Reset Timing

The KSZ8081RNA/RND reset timing requirement is summarized in Figure 7-5 and Table 7-5.

FIGURE 7-5:

POWER-UP/RESET TIMING

SUPPLY

VOLTAGES

t_SR

t_VR

RST#

t_CS

t_CH

STRAP-IN

VALUE

t_RC

STRAP-IN /

OUTPUT PIN

TABLE 7-5:

POWER-UP/RESET TIMING PARAMETERS

Description

Parameter

Min.

Typ.

Max.

Units

t_VR

t_SR

Supply voltage (V_DDIO, V_{DDA_3.3}) rise time

300

10

—

µs

Stable supply voltage (V_DDIO, V_{DDA_3.3}) to reset

high

ms

t_CS

t_CH

t_RC

Configuration setup time

Configuration hold time

Reset to strap-in pin output

5

6

—

ns

The supply voltage (V_DDIOand V_{DDA_3.3}) power-up waveform should be monotonic. The 300 µs minimum rise time is

from 10% to 90%.

For warm reset, the reset (RST#) pin should be asserted low for a minimum of 500 µs. The strap-in pin values are read

and updated at the de-assertion of reset.

After the de-assertion of reset, wait a minimum of 100 µs before starting programming on the MIIM (MDC/MDIO) inter-

face.

 2016 Microchip Technology Inc.

DS00002199A-page 41

KSZ8081RNA/RND

8.0

RESET CIRCUIT

Figure 8-1 shows a reset circuit recommended for powering up the KSZ8081RNA/RND if reset is triggered by the power

supply.

FIGURE 8-1:

RECOMMENDED RESET CIRCUIT

VDDIO

D1: 1N4148

D1

R 10K

KSZ8081RNA/RND

RST#

C 10μF

Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example,

the CPU or an FPGA). The reset out RST_OUT_n from CPU/FPGA provides the warm reset after power up reset. D2

is used if using different V_DDIObetween the switch and CPU/FPGA, otherwise, the different V_DDIOwill fight each other.

If different V_DDIOhave to use in a special case, a low V_F(<0.3V) diode is required (for example, Vishay’s BAT54,

MSS1P2L and so on), or a level shifter device can be used too. If Ethernet device and CPU/FPGA use same V_DDIO

voltage, D2 can be removed to connect both devices directly. Usually, Ethernet device and CPU/FPGA should use same

V_DDIOvoltage.

FIGURE 8-2:

RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT

VDDIO

R 10K

D1

KSZ8081RNA/RND

RST#

CPU/FPGA

RST_OUT_n

D2

C 10μF

D1, D2: 1N4148

DS00002199A-page 42

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

9.0

REFERENCE CIRCUITS — LED STRAP-IN PINS

The pull-up, float, and pull-down reference circuits for the LED0/ANEN_SPEED strapping pin are shown in Figure 9-1

for 3.3V and 2.5V V_DDIO

.

FIGURE 9-1:

REFERENCE CIRCUITS FOR LED STRAPPING PINS

VDDIO = 3.3V, 2.5V

PULL-UP

4.7k

220

KSZ8081RNA/RND

LED0 PIN

VDDIO = 3.3V, 2.5V

FLOAT

220

KSZ8081RNA/RND

LED0 PIN

VDDIO = 3.3V, 2.5V

PULL-DOWN

220

KSZ8081RNA/RND

LED0 PIN

1k

For 1.8V V_DDIO, LED indication support is not recommended due to the low voltage. Without the LED indicator, the

ANEN_SPEED strapping pin is functional with a 4.7 kꢀ pull-up to 1.8V V_DDIOor float for a value of ‘1’, and with a 1.0 kꢀ

pull-down to ground for a value of ‘0’.

If using RJ45 jacks with integrated LEDs and 1.8V V_DDIO, a level shifting is required from LED 3.3V to 1.8V. For example,

use a bipolar transistor or a level shift device.

 2016 Microchip Technology Inc.

DS00002199A-page 43

KSZ8081RNA/RND

10.0 REFERENCE CLOCK - CONNECTION AND SELECTION

A crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ8081RNA/

RND. For the KSZ8081RNA/RND in RMII – 25 MHz clock mode, the reference clock is 25 MHz. The reference clock

connections to XI (Pin 8) and XO (Pin 7), and the reference clock selection criteria, are provided in Figure 10-1 and

Table 10-1.

FIGURE 10-1:

25 MHZ CRYSTAL/OSCILLATOR REFERENCE CLOCK CONNECTION

22pF

XI

25MHz OSC

50ppꢀ

NC

XO

25MHz XTAL

50ppꢀ

TABLE 10-1: 25 MHZ CRYSTAL/REFERENCE CLOCK SELECTION CRITERIA

Characteristics

Value

Frequency

25 MHz

±50 ppm

40ꢀ

Frequency Tolerance (max.); Note 10-1

Crystal Series Resistance (typ.)

Crystal Load Capacitance (typ.)

16 pF

Note 10-1

±60 ppm for overtemperature crystal.

For the KSZ8081RNA/RND in RMII – 50 MHz clock mode, the reference clock is 50 MHz. The reference clock connec-

tion to XI (Pin 8), and the reference clock selection criteria are provided in Figure 10-2 and Table 10-2.

FIGURE 10-2:

50 MHZ OSCILLATOR/REFERENCE CLOCK CONNECTION

XI

50MHz OSC

50ppꢀ

NC

XO

TABLE 10-2: 50 MHZ OSCILLATOR/REFERENCE CLOCK SELECTION CRITERIA

Characteristics

Value

Frequency

50 MHz

Frequency Tolerance (max.)

±50 ppm

DS00002199A-page 44

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

11.0 MAGNETIC - CONNECTION AND SELECTION

A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs

exceeding FCC requirements.

The KSZ8081RNA/RND design incorporates voltage-mode transmit drivers and on-chip terminations.

With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the two differential

pairs. Therefore, the two transformer center tap pins on the KSZ8081RNA/RND side should not be connected to any

power supply source on the board; instead, the center tap pins should be separated from one another and connected

through separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode volt-

age is different between transmitting and receiving differential pairs.

Figure 11-1 shows the typical magnetic interface circuit for the KSZ8081RNA/RND.

FIGURE 11-1:

TYPICAL MAGNETIC INTERFACE CIRCUIT

1

TXP

2

3

TXM

RXP

RXM

4

5

6

7

8

4 x 75

1000pF/2kV

(2 x 0.1μF)

SIGNAL GROUND

CHASSIS GROUND

Table 11-1 lists recommended magnetic characteristics.

TABLE 11-1: MAGNETICS SELECTION CRITERIA

Parameter

Value

Test Conditions

Turns Ratio

Open-Circuit Inductance (min.)

Insertion Loss (max.)

HIPOT (min.)

1 CT : 1 CT

350 µH

—

100 mV, 100 kHz, 8 mA

100 kHz to 100 MHz

—

–1.1 dB

1500 V_RMS

Table 11-2 is a list of compatible single-port magnetics with separated transformer center tap pins on the PHY chip side

that can be used with the KSZ8081RNA/RND.

 2016 Microchip Technology Inc.

DS00002199A-page 45

KSZ8081RNA/RND

TABLE 11-2: COMPATIBLE SINGLE-PORT 10/100 MAGNETICS

Manufacturer

Part Number

Temperature Range

Magnetic + RJ-45

Bel Fuse

Delta

S558-5999-U7

SI-46001-F

SI-50170-F

LF8505

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

No

Yes

No

HALO

HFJ11-2450E

TG110-E055N5

LF-H41S-1

H1102

Yes

No

HALO

LANKom

Pulse

No

Pulse

H1260

No

Pulse

HX1188

No

Pulse

J00-0014

Yes

No

Pulse

JX0011D21NL

TLA-6T718A

HB726

TDK

Transpower

Wurth/Midcom

000-7090-37R-LF1

No

DS00002199A-page 46

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

12.0 PACKAGE OUTLINE

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

FIGURE 12-1:

24-LEAD QFN 4 MM X 4 MM PACKAGE

 2016 Microchip Technology Inc.

DS00002199A-page 47

KSZ8081RNA/RND

APPENDIX A: DATA SHEET REVISION HISTORY

TABLE A-1:

REVISION HISTORY

Section/Figure/Entry

Revision

Correction

Converted Micrel data sheet KSZ8081RNA/RND to

Microchip DS00002199A. Minor text changes

throughout.

DS00002199A (06-14-16)

—

DS00002199A-page 48

 2016 Microchip Technology Inc.

KSZ8081RNA/RND

THE MICROCHIP WEB SITE

Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make

files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-

tains the following information:

• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s

guides and hardware support documents, latest software releases and archived software

• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion

groups, Microchip consultant program member listing

• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-

nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive

e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or

development tool of interest.

To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-

cation” and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales

offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-

ment.

Technical support is available through the web site at: http://microchip.com/support

 2016 Microchip Technology Inc.

DS00002199A-page 49

KSZ8081RNA/RND

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

Examples:

X

a)

b)

c)

d)

KSZ8081RNACA

RMII Interface

24-pin QFN

25 MHz Input/50 MHz Output

Commercial Temperature

KSZ8081RNAIA

RMII Interface

Interface Package

Temperature

Special

Attribute

Device:

KSZ8081

24-pin QFN

Interface:

R = RMII

25 MHz Input/50 MHz Output

Industrial Temperature

KSZ8081RNDCA

RMII Interface

24-pin QFN

50 MHz Input

Commercial Temperature

KSZ8081RNDIA

RMII Interface

Package:

N = 24-pin QFN

Special Attribute:

A = 25 MHz Input/50 MHz Output Clocks

D = 50 MHz Input Clock

24-pin QFN

50 MHz Input

Industrial Temperature

Temperature:

CA = 0C to +70C (Commercial)

IA = –40C to +85C (Industrial)

DS00002199A-page 50

 2016 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be

superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO

REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-

chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold

harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or

otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, AnyRate, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, KeeLoq logo,

Kleer, LANCheck, LINK MD, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC,

SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other

countries.

ClockWorks, The Embedded Control Solutions Company, ETHERSYNCH, Hyper Speed Control, HyperLight Load, IntelliMOS,

mTouch, Precision Edge, and QUIET-WIRE are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,

Dynamic Average Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, RightTouch logo, REAL ICE, Ripple Blocker, Serial

Quad I/O, SQI, SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless

DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.

GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their respective companies.

ISBN: 978-1-5224-0855-0

Microchip received ISO/TS-16949:2009 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ

and India. The Company’s quality system processes and procedures

CERTIFIEDꢀBYꢀDNVꢀ

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

== ISO/TSꢀ16949ꢀ==ꢀ

 2016 Microchip Technology Inc.

DS00002199A-page 51

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Asia Pacific Office

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

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Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

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Tel: 86-756-3210040

Fax: 86-756-3210049

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

Hong Kong

Tel: 852-2943-5100

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-3090-4444

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Tel: 81-3-6880- 3770

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China - Dongguan

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Itasca, IL

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Addison, TX

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Fax: 972-818-2924

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Fax: 86-25-8473-2470

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Fax: 60-4-227-4068

Detroit

Novi, MI

Tel: 248-848-4000

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Houston, TX

Tel: 281-894-5983

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-5778-366

Fax: 886-3-5770-955

Los Angeles

China - Shenzhen

Tel: 86-755-8864-2200

Fax: 86-755-8203-1760

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Taiwan - Kaohsiung

Tel: 886-7-213-7828

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2508-8600

Fax: 886-2-2508-0102

New York, NY

Tel: 631-435-6000

San Jose, CA

Tel: 408-735-9110

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

06/23/16

DS00002199A-page 52

 2016 Microchip Technology Inc.


型号：	KSZ8081RNA
厂家：	MICROCHIP
描述：	10BASE-T/100BASE-TX PHY with RMII Support
文件：	总52页 (文件大小：454K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

KSZ8081RNA [MICROCHIP]

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KSZ8081RNB-EVAL

KSZ8081RNBCA

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