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KSZ8721SLI-TR [MICROCHIP]

3.3V Single Power Supply 10/100 Base-TX/FX MII Physical Layer Transceiver;
KSZ8721SLI-TR
型号： KSZ8721SLI-TR
厂家： MICROCHIP    MICROCHIP
描述：

3.3V Single Power Supply 10/100 Base-TX/FX MII Physical Layer Transceiver

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KSZ8721BL/SL  
3.3V Single Power Supply 10/100 Base-TX/FX MII Physical Layer  
Transceiver  
Features  
• Single Chip 100BASE-TX/100BASE-FX/  
10BASE-T Physical Layer Solution  
• On-Chip, Built-In, Analog Front-End Filtering for  
Both 100BASE-TX and 10BASE-T  
• 2.5V CMOS Design; 2.5/3.3V Tolerance on I/O  
• LED Outputs for Link, Activity, Full-Duplex/Half-  
Duplex, Collision, and Speed  
• 3.3V Single Power Supply with Built-In Voltage  
Regulator; Power Consumption <340 mW  
(Including Output Driver Current)  
• Supports Back-to-Back, FX to TX for Media  
Converter Applications  
• Fully Compliant to IEEE 802.3u Standard  
• Supports MII and Reduced MII (RMII)  
• Supports MDI/MDI-X Auto-Crossover  
• KSZ8721BL is a Drop-In Replacement for the  
KSZ8721BT in the Same Footprint  
• Supports 10BASE-T, 100BASE-TX, and  
100BASE-FX with Far-End Fault Detection  
• KSZ8721SL is a Drop-In Replacement for the  
KSZ8721B in the Same Footprint  
• Supports Power Down and Power Saving Modes  
• Commercial Temperature Range: 0°C to +70°C  
• Industrial Temperature Range: –40°C to +85°C  
• Available in 48-pin SSOP and LQFP Packages  
• Configurable Through MII Serial Management  
Ports or via External Control Pin  
• Supports Auto-Negotiation and Manual Selection  
for 10/100 Mbps Speed and Full-Duplex/Half-  
Duplex Modes  
2018 Microchip Technology Inc.  
DS00002813A-page 1  
KSZ8721BL/SL  
TO OUR VALUED CUSTOMERS  
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip  
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and  
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Most Current Data Sheet  
To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:  
http://www.microchip.com  
You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.  
The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).  
Errata  
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for cur-  
rent devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the  
revision of silicon and revision of document to which it applies.  
To determine if an errata sheet exists for a particular device, please check with one of the following:  
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Microchip’s Worldwide Web site; http://www.microchip.com  
Your local Microchip sales office (see last page)  
When contacting a sales office, please specify which device, revision of silicon and data sheet (include -literature number) you are  
using.  
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Register on our web site at www.microchip.com to receive the most current information on all of our products.  
DS00002813A-page 2  
2018 Microchip Technology Inc.  
KS8721BL/SL  
Table of Contents  
1.0 Introduction ..................................................................................................................................................................................... 4  
2.0 Pin Description and Configuration .................................................................................................................................................. 5  
3.0 Functional Description .................................................................................................................................................................. 10  
4.0 Register Map ................................................................................................................................................................................. 19  
5.0 Operational Characteristics ........................................................................................................................................................... 25  
6.0 Electrical Characteristics ............................................................................................................................................................... 26  
7.0 Timing Specifications .................................................................................................................................................................... 28  
8.0 Packaging Information .................................................................................................................................................................. 36  
Appendix A: Data Sheet Revision History ........................................................................................................................................... 39  
The Microchip Web Site ...................................................................................................................................................................... 40  
Customer Change Notification Service ............................................................................................................................................... 40  
Customer Support ............................................................................................................................................................................... 40  
Product Identification System ............................................................................................................................................................. 41  
2018 Microchip Technology Inc.  
DS00002813A-page 3  
KSZ8721BL/SL  
1.0  
1.1  
INTRODUCTION  
General Description  
Operating with a 2.5V core to meet low-voltage and low-power requirements, the KSZ8721BL and KSZ8721SL are  
10BASE-T/100BASE-TX/FX Physical Layer Transceivers that use MII and RMII interfaces to transmit and receive data.  
They contain 10BASE-T Physical Medium Attachment (PMA), Physical Medium Dependent (PMD), and Physical  
Coding Sub-layer (PCS) functions. The KSZ8721BL/SL also have on-chip 10BASE-T output filtering. This eliminates  
the need for external filters and allows a single set of line magnetics to be used to meet requirements for both  
100BASE-TX and 10BASE-T.  
The KSZ8721BL/SL automatically configure themselves for 100 or 10Mbps and full-duplex or half-duplex operation,  
using an on-chip auto-negotiation algorithm. They are the ideal physical layer transceiver for 100BASE-TX/10BASE-T  
applications.  
FIGURE 1-1:  
KSZ8721BL/SL FUNCTIONAL DIAGRAM  
4B/5B Encoder  
Scrambler  
Parallel/Serial  
NRZ/NRZI  
MLT3 Encoder  
TXD3  
TXD2  
TXD1  
TXD0  
TXER  
TXC  
TXEN  
CRS  
COL  
10/100  
Pulse  
Shaper  
TX+  
Transmitter  
TX-  
Parallel/Serial  
Manchester Encoder  
MII/RMII  
Registers  
and  
Controller  
Interface  
Adaptive EQ  
Base Line  
Wander Correction  
MLT3 Decoder  
NRZI/NRZ  
RX+  
RX-  
4B/5B Decoder  
Descrambler  
Serial/Parallel  
Clock  
Recovery  
MDIO  
MDC  
RXD3  
RXD2  
RXD1  
RXD0  
RXER  
RXDV  
RXC  
Auto  
Negotiation  
Manchester Decoder  
Serial/Parallel  
10BASE-T  
Receiver  
Power  
Down or  
Saving  
LINK  
COL  
FDX  
SPD  
LED  
Driver  
XI  
PLL  
XO  
PWRDWN  
DS00002813A-page 4  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
2.0  
PIN DESCRIPTION AND CONFIGURATION  
FIGURE 2-1:  
48-PIN SSOP (SM) AND 48-PIN LQFP (LQ) (TOP VIEW)  
48-Pin SSOP (SM)  
MDIO  
MDC  
1
48 RST#  
2
3
4
5
6
7
8
9
47 VDDPLL  
46 XI  
48-Pin LQFP (LQ)  
R3D3/PHYAD1  
RXD2/PHYAD2  
RXD1/PHYAD3  
RXD0/PHYAD4  
VDDIO  
45 XO  
44 GND  
43 GND  
48 47 46 45 44 43 42 4140 39 38 37  
42 VDDTX  
41 TX+  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
GND  
GND  
MDIO  
1
2
3
MDC  
RXD1/PHYAD1  
RXD2/PHYAD2  
RXD1/PHYAD3  
RXD0/PHYAD4  
VDDIO  
GND  
FXSD/FXEN  
RX+  
4
RXDV/PCS_LPBK  
40 TX-  
5
RX–  
6
VDDRX  
RXC 10  
RXER/ISO 11  
GND 12  
39 GND  
PD#  
7
38 VDDRCV  
37 REXT  
8
LED3/NWAYEN  
LED2/DUPLEX  
LED1/SPD100  
LED0/TEST  
GND  
RXDV/PCS_LPBK  
RXC  
9
10  
RXER/ISO  
11  
12  
26  
25  
VDDC 13  
36 GND  
GND  
INT#/PHYAD0  
13 14 15 16 17 18 19 20 21 22 23 24  
TXER 14  
35 GND  
TXC/REF_CLK 15  
TXEN 16  
34 FXSD/FXEN  
33 RX+  
TXD0 17  
32 RX-  
TXD1 18  
31 VDDRX  
30 PD#  
TXD2 19  
TXD3 20  
29 LED3/NWAYEN  
28 LED2/DUPLEX  
27 LED1/SPD100  
26 LED0/TEST  
25 INT#/PHYAD0  
COL/RMII 21  
CRS/RMII_BTB 22  
GND 23  
VDDIO 24  
2018 Microchip Technology Inc.  
DS00002813A-page 5  
KSZ8721BL/SL  
TABLE 2-1:  
PIN DESCRIPTION  
Pin  
Number  
Type  
(Note 2-1)  
Pin Name  
Description  
Management Independent Interface (MII) Data I/O. This pin  
requires an external 4.7 kΩ pull-up resistor.  
1
2
MDIO  
MDC  
I/O  
I
MII Clock Input. This pin is synchronous to the MDIO.  
MII Receive Data Output. RXD [3..0], these bits are synchronous  
with RXCLK. When RXDV is asserted, RXD [3..0] presents valid  
data to MAC through the MII. RXD [3..0] is invalid when RXDV is  
de-asserted.  
RXD3/PHYAD  
3
IPD/O  
During reset, the pull-up/pull-down value is latched as PHYADDR  
[1]. See Table 2-2 for details.  
MII Receive Data Output.  
4
5
6
RXD2/PHYAD2  
RXD1/PHYAD1  
RXD0/PHYAD4  
IPD/O  
IPD/O  
IPD/O  
During reset, the pull-up/pull-down value is latched as PHY-  
ADDR[2]. See Table 2-2 for details.  
MII Receive Data Output.  
During reset, the pull-up/pull-down value is latched as PHY-  
ADDR[3]. See Table 2-2 for details.  
MII Receive Data Output.  
During reset, the pull-up/pull-down value is latched as PHY-  
ADDR[4]. See Table 2-2 for details.  
Digital IO 2.5 /3.3V tolerant power supply. 3.3V power Input of  
voltage regulator. See Section 3.23 “Circuit Design Reference  
for Power Supply” for details.  
7
8
9
VDDIO  
GND  
P
GND  
IPD/O  
Ground.  
MII Receive Data Valid Output.  
During reset, the pull-up/pull-down value is latched as  
PCS_LPBK. See Table 2-2 for details.  
RXDV/CRSDV/  
PCS_LPBK  
MII Receive Clock Output. Operating at 25 MHz = 100 Mbps,  
2.5 MHz = 10 Mbps.  
10  
11  
RXC  
O
MII Receive Error Output.  
During reset, the pull-up/pull-down value is latched as ISOLATE  
during reset. See Table 2-2 for details.  
RXER/ISO  
IPD/O  
12  
13  
14  
GND  
VDDC  
TXER  
GND  
P
Ground.  
Digital core 2.5V only power supply. See Section 3.23 “Circuit  
Design Reference for Power Supply” for details.  
IPD  
MII Transmit Error Input.  
MII Transmit Clock Output.  
Input for crystal or an external 50 MHz clock. When REFCLK pin  
is used for REF clock interface, pull up XI to VDDPLL 2.5V via  
10 kΩ resistor and leave XO pin unconnected.  
15  
TXC/REFCLK  
I/O  
16  
17  
18  
TXEN  
TXD0  
TXD1  
IPD  
IPD  
IPD  
MII Transmit Enable Input.  
MII Transmit Data Input.  
MII Transmit Data Input.  
DS00002813A-page 6  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
TABLE 2-1:  
PIN DESCRIPTION (CONTINUED)  
Type  
Pin  
Number  
Pin Name  
Description  
(Note 2-1)  
19  
20  
TXD2  
TXD3  
IPD  
IPD  
MII Transmit Data Input.  
MII Transmit Data Input.  
MII Collision Detect Output.  
21  
22  
COL/RMII  
IPD/O  
IPD/O  
During reset, the pull-up/pull-down value is latched as RMII select.  
See Table 2-2 for details.  
MII Carrier Sense Output.  
During reset, the pull-up/pull-down value is latched as RMII back-  
to-back mode when RMII mode is selected. See Table 2-2 for  
details.  
CRS/RMII_BTB  
23  
24  
GND  
GND  
P
Ground.  
Digital IO 2.5/3.3V tolerant power supply. 3.3V power input of volt-  
age regulator. See  
Power Supply  
VDDIO  
Section 3.23, Circuit Design Reference for  
for details.  
Management Interface (MII) Interrupt Out. Interrupt level set by  
Register 1f, bit 9. During reset, latched as PHYAD[0]. See Table 2-  
2 for details.  
25  
INT#/PHYAD0  
LED0/TEST  
IPU/O  
IPU/O  
Link/Activity LED Output. The external pull-down enable test  
mode and only used for the factory test. Active low.  
Link/Act  
No Link  
Link  
Pin State  
LED Definition PHYAD0  
26  
H
L
Off  
On  
Act  
—
Toggle  
Speed LED Output. Latched as SPEED (Register 0, bit 13) during  
power-up/ reset. See Table 2-2 for details. Active low.  
LED1/SPD100/  
nFEF  
Speed  
10BT  
Pin State  
LED Definition  
27  
28  
29  
IPU/O  
IPU/O  
IPU/O  
H
L
Off  
On  
100BT  
Full-duplex LED Output. Latched as DUPLEX (register 0h, bit 8)  
during power-up/ reset. See “Table 2-2 for details. Active low.  
Duplex  
Half  
Pin State  
LED Definition  
LED2  
H
L
Off  
On  
Full  
Collision LED Output. Latched as ANEG_EN (register 0h, bit 12)  
during power-up/ reset. See Table 2-2 for details.  
Collision  
No Collision  
Collision  
Pin State  
LED Definition  
LED3/NWAYEN  
H
L
Off  
On  
2018 Microchip Technology Inc.  
DS00002813A-page 7  
KSZ8721BL/SL  
TABLE 2-1:  
PIN DESCRIPTION (CONTINUED)  
Pin  
Number  
Type  
(Note 2-1)  
Pin Name  
Description  
30  
31  
PD#  
IPU  
P
Power Down. 1 = Normal operation, 0 = Power-down. Active low.  
Analog 2.5V power supply. See Section 3.23 “Circuit Design  
Reference for Power Supply” section for details.  
VDDRX  
Receive Input. Differential receive input pins for 100FX,  
100BASE-TX, or 10BASE-T.  
32  
33  
RX–  
RX+  
I
I
Receive Input: Differential receive input pin for 100FX, 100BASE-  
TX, or 10BASE-T.  
Fiber Mode Enable/Signal Detect in Fiber Mode. If FXEN = 0, FX  
mode is disable. The default is “0”. See Section 3.21 “100BT FX  
Mode” for more details.  
FXSD/  
FXEN  
34  
IPD/O  
35  
36  
37  
GND  
GND  
REXT  
GND  
GND  
I
Ground.  
Ground.  
External resistor (6.49 kW) connects to REXT and GND.  
Analog 2.5V power supply. 2.5V power output of voltage regulator.  
See Section 3.23 “Circuit Design Reference for Power Sup-  
ply” for details.  
38  
VDDRCV  
P
39  
40  
GND  
TX–  
GND  
O
Ground.  
Transmit Outputs: Differential transmit output for 100FX,  
100BASE-TX, or 10BASE-T.  
Transmit Outputs: Differential transmit output for 100FX,  
100BASE-TX, or 10BASE-T.  
41  
42  
TX+  
O
P
Transmitter 2.5V power supply. See Section 3.23 “Circuit  
Design Reference for Power Supply” for details.  
VDDTX  
43  
44  
45  
GND  
GND  
XO  
GND  
GND  
O
Ground.  
Ground.  
XTAL feedback: Used with XI for Xtal application.  
Crystal Oscillator Input: Input for a crystal or an external 25 MHz  
clock. If an oscillator is used, XI connects to a 3.3V tolerant oscil-  
lator, and X2 is a no-connect.  
46  
47  
XI  
I
Analog PLL 2.5V power supply. See Section 3.23 “Circuit  
Design Reference for Power Supply” for details.  
VDDPLL  
RST#  
P
48  
IPU  
Chip Reset. Active low, minimum of 50 µs pulse is required.  
Note 2-1  
P = Power supply;  
GND = Ground;  
I = Input; O = Output; I/O = Bi-directional;  
IPU/O = Input with internal pull-up during power-up/reset; output pin otherwise.  
IPU = Input with internal pull-up.  
IPD = Input with internal pull-down.  
IPD/O = Input with internal pull-down during reset; output pin otherwise.  
IPU/O = Input with internal pull-up during reset; output pin otherwise.  
DS00002813A-page 8  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
Note 2-2  
Speed: Low (100BASE-TX), High (10BASE-T)  
Full-Duplex: Low (full-duplex), High (half-duplex)  
Act: Toggle (transmit / receive activity)  
Link: Low (link), High (no link)  
TABLE 2-2:  
Pin Number  
STRAPPING OPTIONS (Note 2-1)  
Pin Name  
Type (Note 2-2) Pin Function  
PHYAD[4:1]/  
RXD[0:3]  
PHY Address latched at power-up/reset. The default  
PHY address is 00001.  
6, 5, 4, 3  
25  
IPD/O  
IPU/O  
IPD/O  
IPD/O  
PHYAD0/  
INT#  
Enables PCS_LPBK mode at power-up/reset. PD  
(default) = Disable, PU = Enable.  
PCS_LPBK/  
RXDV  
Enables ISOLATE mode at power-up/reset. PD  
(default) = Disable, PU = Enable.  
9 (Note 2-3)  
11 (Note 2-3)  
Enables RMII mode at power-up/reset. PD (default) =  
Disable, PU = Enable.  
ISO/RXER  
Enable RMII back-to-back mode at power-up/reset. PD  
(default) = Disable,  
PU = Enable.  
21 (Note 2-3)  
22 (Note 2-3)  
RMII/COL  
IPD/O  
IPD/O  
Enable RMII back-to-back mode at power-up/reset. PD  
(default) = Disable,  
PU = Enable.  
RMII_BTB  
CRS  
Latched into Register 0h bit 13 during power-up/reset.  
PD = 10Mbps, PU (default) = 100Mbps. If SPD100 is  
asserted during power-up/reset, this pin is also latched  
as LED1 the Speed Support in register 4h. (If FXEN is  
pulled up, the latched value 0 means no Far_End  
_Fault.)  
SPD100/  
No FEF/  
27  
28  
IPU/O  
IPU/O  
Latched into Register 0h bit 8 during power-up/reset.  
PD = Half-duplex, PU (default) = Full-duplex. If Duplex  
is pulled up during reset, this pin is also latched as the  
Duplex support in register 4h.  
DUPLEX/  
LED2  
Nway (auto-negotiation) Enable. Latched into Register  
0h bit 12 during power-up/reset. PD = Disable Auto-  
Negotiation, PU (default) = Enable Auto-Negotiation.  
NWAYEN/  
LED3  
29  
30  
IPU/O  
IPU  
Power-Down Enable. PU (default) = Normal operation,  
PD = Power-Down mode.  
PD#  
Note 2-1  
Note 2-2  
Strap-in is latched during power-up or reset.  
IPU = Input with internal pull-up.  
IPD/O = Input with internal pull-down during reset; output pin otherwise.  
IPU/O = Input with internal pull-up during reset; output pin otherwise.  
See “Reference Circuit” section for pull-up/pull-down and float information.  
Note 2-3  
Some devices may drive MII pins that are designated as output (PHY) on power-up, resulting in  
incorrect strapping values latched at reset. It is recommended that an external pull-down via 1 kΩ  
resistor be used in these applications to augment the KSZ8721’s internal pull-down  
2018 Microchip Technology Inc.  
DS00002813A-page 9  
KSZ8721BL/SL  
3.0  
3.1  
FUNCTIONAL DESCRIPTION  
100BASE-TX transmit  
The 100BASE-TX transmit function performs parallel to serial conversion, NRZ-to-NRZI conversion, and MLT-3 encod-  
ing and transmission. The circuitry starts with a parallel to serial conversion that converts the 25 MHz, 4-bit nibbles into  
a 125 MHz serial bit stream. The incoming data is clocked in at the positive edge of the TXC signal. The serialized data  
is further converted from NRZ to NRZI format, and then transmitted in MLT3 current output. The output current is set by  
an external 1% 6.49 kΩ resistor for the 1:1 transformer ratio. Its typical rise/fall time of 4 ns complies with the ANSI  
TP-PMD standard regarding amplitude balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver  
is also incorporated into the 100BASE-TX driver.  
3.2  
100BASE-TX Receive  
The 100BASE-TX receive function performs adaptive equalization, DC restoration, MLT-3 to NRZI conversion, data and  
clock recovery, NRZI-to-NRZ conversion, and serial-to-parallel conversion. The receiving side starts with the equaliza-  
tion filter to compensate inter-symbol interference (ISI) over the twisted pair cable. Because the amplitude loss and  
phase distortion are a function of the length of the cable, the equalizer has to adjust its characteristic to optimize perfor-  
mance. In this design, the variable equalizer will make an initial estimation based on comparisons of incoming signal  
strength against some known cable characteristics, then tunes itself for optimization. This is an ongoing process and  
can self-adjust for environmental changes such as temperature variations.  
The equalized signal then goes through a DC restoration and data conversion block. The DC restoration circuit is used  
to compensate for the effects of base line wander and improve dynamic range. The differential data conversion circuit  
converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.  
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then  
used to convert the NRZI signal into the NRZ format. Finally, the NRZ serial data is converted to 4-bit parallel 4B nibbles.  
A synchronized 25 MHz RXC is generated so that the 4B nibbles are clocked out at the negative edge of RCK25 and  
is valid for the receiver at the positive edge. When no valid data is present, the clock recovery circuit is locked to the  
25 MHz reference clock and both TXC and RXC clocks continue to run.  
3.3  
PLL Clock Synthesizer  
The KSZ8721BL/SL generates 125 MHz, 25 MHz, and 20 MHz clocks for system timing. An internal crystal oscillator  
circuit provides the reference clock for the synthesizer.  
3.4  
Scrambler/De-scrambler (100BASE-TX Only)  
The purpose of the scrambler is to spread the power spectrum of the signal in order to reduce electromagnetic interfer-  
ence (EMI) and baseline wander.  
3.5  
10BASE-T Transmit  
When TXEN (transmit enable) goes high, data encoding and transmission begins. The KSZ8721BL/SL continues to  
encode and transmit data as long as TXEN remains high. The data transmission ends when TXEN goes low. The last  
transition occurs at the boundary of the bit cell if the last bit is zero, or at the center of the bit cell if the last bit is one.  
The output driver is incorporated into the 100BASE-T driver to allow transmission with the same magnetics. They are  
internally wave-shaped and pre-emphasized into outputs with typical 2.5V amplitude. The harmonic contents are at least  
27dB below the fundamental when driven by all-ones, Manchester-encoded signal.  
3.6  
10BASE-T Receive  
On the receive side, input buffer and level detecting squelch circuits are employed. A differential input receiver circuit  
and a PLL performs the decoding function. The Manchester-encoded data stream is separated into clock signal and  
NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths in order to prevent  
noise at the RX+ or RX– input from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL  
locks onto the incoming signal and the KSZ8721BL/SL decodes a data frame. This activates the carrier sense (CRS)  
and RXDV signals and makes the receive data (RXD) available. The receive clock is maintained active during idle peri-  
ods in between data reception.  
DS00002813A-page 10  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
3.7  
SQE and Jabber Function (10BASE-T Only)  
In 10BASE-T operation, a short pulse is put out on the COL pin after each packet is transmitted. This is required as a  
test of the 10BASE-T transmit/receive path and is called an SQE test. The 10BASE-T transmitter is disabled and COL  
goes high if TXEN is high for more than 20 ms (jabbering). If TXEN then goes low for more than 250 ms, the  
10BASE-T transmitter is re-enabled and COL goes low.  
3.8  
Auto-Negotiation  
The KSZ8721BL/SL performs auto-negotiation by hardware strapping option (pin 29) or software (Register 0.12). It  
automatically chooses its mode of operation by advertising its abilities and comparing them with those received from its  
link partner whenever auto-negotiation is enabled. It can also be configured to advertise 100BASE-TX or 10BASE-T in  
either full-duplex or half-duplex mode (please refer to ). Auto-negotiation is disabled in the FX mode.  
During auto-negotiation, the contents of Register 4, coded in fast link pulse (FLP), are sent to its link partner under the  
conditions of power-on, link-loss, or restart. At the same time, the KSZ8721BL/SL monitors incoming data to determine  
its mode of operation. The parallel detection circuit is enabled as soon as either 10BASE-T normal link pulse (NLP) or  
100BASE-TX idle is detected. The operation mode is configured based on the following priority:  
• Priority 1: 100BASE-TX, full-duplex  
• Priority 2: 100BASE-TX, full-duplex  
• Priority 3: 100BASE-TX, full-duplex  
• Priority 4: 10BASE-T, half-duplex  
When the KSZ8721BL/SL receives a burst of FLP from its link partner with three identical link code words (ignoring  
acknowledge bit), it will store these code words in Register 5 and wait for the next three identical code words. Once the  
KSZ8721BL/SL detects the second code words, it then configures itself according to the above-mentioned priority. In  
addition, the KSZ8721BL/SL also checks for 100BASE-TX idle or 10BASE-T NLP symbols. If either is detected, the  
KSZ8721BL/SL automatically configures to match the detected operating speed.  
• A physical connection including a data line (MDIO), a clock line (MDC), and an optional interrupt line (INTRPT).  
• A specific protocol that runs across the above mentioned physical connection that allows one controller to commu-  
nicate with multiple KSZ8721BL/SL devices. Each KSZ8721BL/SL is assigned an MII address between 0 and 31  
by the PHYAD inputs.  
• An internal addressable set of fourteen 16-bit MDIO registers. Registers [0:6] are required and their functions are  
specified by the IEEE 802.3 specifications. Additional registers are provided for expanded functionality.  
The INTPRT pin functions as a management data interrupt in the MII. An active low or high in this pin indicates a status  
change on the KSZ8721BL/SL based on 1fh.9 level control. Register bits at 1bh[15:8] are the interrupt enable bits. Reg-  
ister bits at 1bh[7:0] are the interrupt condition bits. This interrupt is cleared by reading Register 1bh.  
3.9  
MII Data Interface  
The data interface consists of separate channels for transmitting data from a 10/100 802.3-compliant Media Access  
Controller (MAC) to the KSZ8721BL/SL, and for receiving data from the line. Normal data transmission is implemented  
in 4B nibble mode (4-bit wide nibbles).  
3.9.1  
TRANSMIT CLOCK (TXC)  
The transmit clock is normally generated by the KSZ8721BL/SL from an external 25 MHz reference source at the X1  
input. The transmit data and control signals must always be synchronized to the TXC by the MAC. The KSZ8721BL/SL  
normally samples these signals on the rising edge of the TXC.  
3.9.2  
RECEIVE CLOCK (RXC)  
For 100BASE-TX links, the receive clock is continuously recovered from the line. If the link goes down, and auto-nego-  
tiation is disabled, the receive clock operates off the master input clock (X1 or TXC). For 10BASE-T links, the receive  
clock is recovered from the line while carrier is active, and operates from the master input clock when the line is idle.  
The KSZ8721BL/SL synchronizes the receive data and control signals on the falling edge of RXC in order to stabilize  
the signals at the rising edge of the clock with 10 ns setup and hold times.  
3.9.3  
TRANSMIT ENABLE  
The MAC must assert TXEN at the same time as the first nibble of the preamble, and deassert TXEN after the last bit  
of the packet.  
2018 Microchip Technology Inc.  
DS00002813A-page 11  
KSZ8721BL/SL  
3.9.4  
RECEIVE DATA VALID  
The KSZ8721BL/SL asserts RXDV when it receives a valid packet. Line operating speed and MII mode will determine  
timing changes in the following way:  
• For 100BASE-TX links with the MII in 4B mode, RXDV is asserted from the first nibble of the preamble to the last  
nibble of the data packet.  
• For 10BASE-T links, the entire preamble is truncated. RXDV is asserted with the first nibble of the SFD “5D” and  
remains asserted until the end of the packet.  
3.9.5  
ERROR SIGNALS  
Whenever the KSZ8721BL/SL receives an error symbol from the network, it asserts RXER and drives “1110” (4B) on  
the RXD pins. When the MAC asserts TXER, the KSZ8721BL/SL will drive “H” symbols (a Transmit Error defined in the  
IEEE 802.3 4B/5B code group) out on the line to force signaling errors.  
3.9.6  
CARRIER SENSE (CRS)  
For 100BASE-TX links, a start-of-stream delimiter, or /J/K symbol pair causes assertion of Carrier Sense (CRS). An end-  
of-stream delimiter, or /T/R symbol pair, causes deassertion of CRS. The PMA layer will also de-assert CRS if IDLE  
symbols are received without /T/R, yet in this case RXER will be asserted for one clock cycle when CRS is deasserted.  
For 10BASE-T links, CRS assertion is based on reception of valid preamble, and deassertion on reception of an end-  
of-frame (EOF) marker.  
3.9.7  
COLLISION  
Whenever the line state is half-duplex and the transmitter and receiver are active at the same time, the KSZ8721BL/SL  
asserts its collision signal, which is asynchronous to any clock.  
3.10 RMII (Reduced MII) Data Interface  
RMII interface specifies a low pin count, Reduced Media Independent Interface (RMII) intended for use between  
Ethernet PHYs and Switch or Repeater ASICs. It is fully compliant with IEEE 802.3u [2].  
This interface has the following characteristics:  
• It is capable of supporting 10 Mbps and 100 Mbps data rates.  
• A single clock reference is sourced from the MAC to PHY (or from an external source).  
• It provides independent 2-bit wide (di-bit) transmit and receive data paths.  
• It uses TTL signal levels compatible with common digital CMOS ASIC processes.  
TABLE 3-1:  
RMII SIGNAL DEFINITION  
Direction  
Direction  
(w/respect to the MAC)  
Signal Name  
Use  
(w/respect to the PHY)  
Synchronous clock reference  
for receive, transmit and con-  
trol interface  
REF_CLK  
Input  
Input or Output  
Carrier Sense/Receive Data  
Valid  
CRS_DV  
Output  
Input  
RXD[1:0]  
TX_EN  
Output  
Input  
Input  
Output  
Output  
Input  
Receive Data  
Transmit Enable  
Transmit Data  
Receive Error  
TXD[1:0]  
RX_ER  
Input  
Output  
3.11 Reference Clock (REF_CLK)  
REF_CLK is a continuous 50 MHz clock that provides the timing reference for CRS_DV, RXD[1:0], TX_EN, TXD[1:0],  
and RX_E. REF_CLK is sourced by the MAC or an external source. Switch implementations may choose to provide  
REF_CLK as an input or an output depending on whether they provide a REF_CLK output or rely on an external clock  
distribution device. Each PHY device must have an input corresponding to this clock but may use a single clock input  
for multiple PHYs implemented on a single IC.  
DS00002813A-page 12  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
3.12 Carrier Sense/Receive Data Valid (CRS_DV)  
CRS_DV is asserted asynchronously on detection of carrier due to the criteria relevant to the operating mode. That is,  
in 10BASE-T mode, when squelch is passed or in 100BASE-X mode when two noncontiguous zeroes in 10 bits are  
detected, the carrier is detected.  
Loss-of-carrier results in the deassertion of CRS_DV synchronous to REF_CLK. As carrier criteria are met, CRS_DV  
remains continuously asserted from the first recovered di-bit of the frame through the final recovered di-bit and is  
negated prior to the first REF_CLK that follows the final di-bit.  
The data on RXD[1:0] is considered valid once CRS_DV is asserted. However, because the assertion of CRS_DV is  
asynchronous relative to REF_CLK, the data on RXD[1:0] remains as “00” until proper receive signal decoding takes  
place (see Section 3.13, Receive Data [1:0] (RXD[1:0])).  
3.13 Receive Data [1:0] (RXD[1:0])  
RXD[1:0] transitions synchronously to REF_CLK. For each clock period in which CRS_DV is asserted, RXD[1:0] trans-  
fers two bits of recovered data from the PHY. In some cases (e.g., before data recovery or during error conditions), a  
predetermined value for RXD[1:0] is transferred instead of recovered data. RXD[1:0] remains as “00” to indicate idle  
when CRS_DV is deasserted. Values of RXD[1:0] other than “00” when CRS_DV is deasserted are reserved for out-of-  
band signaling (to be defined). Values other than “00” on RXD[1:0] while CRS_DV is deasserted are ignored by the  
MAC/repeater. Upon assertion of CRS_DV, the PHY ensures that RXD[1:0]=00 until proper receive decoding takes  
place.  
3.14 Transmit Enable (TX_EN)  
Transmit Enable TX_EN indicates that the MAC is presenting di-bits on TXD[1:0] on the RMII for transmission. TX_EN  
is asserted synchronously with the first nibble of the preamble and remains asserted while all transmitted di-bits are  
presented to the RMII. TX_EN is negated prior to the first REF_CLK following the final di-bit of a frame. TX_EN transi-  
tions synchronously with respect to REF_CLK.  
3.15 Transmit Data [1:0] (TXD[1:0])  
Transmit Data TXD[1:0] transitions synchronously with respect to REF_CLK. When TX_EN is asserted, TXD[1:0] are  
accepted for transmission by the PHY. TXD[1:0] remains as “00” to indicate idle when TX_EN is deasserted. Values of  
TXD[1:0] other than “00” when TX_EN is deasserted are reserved for out-of-band signaling (to be defined). Values other  
than “00” on TXD[1:0] while TX_EN is deasserted are ignored by the PHY.  
3.16 Collision Detection  
Because the definition of CRS_DV and TX_EN both contain an accurate indication of the start of frame, the MAC reliably  
regenerates the COL signal of the MII by ANDing TX_EN and CRS_DV.  
During the IPG time following the successful transmission of a frame, the COL signal is asserted by some transceivers  
as a self-test. The Signal Quality Error (SQE) function is not supported by the reduced MII due to the lack of the COL  
signal. Historically, SQE was present to indicate that a transceiver located physically remote from the MAC was func-  
tioning. Because the reduced MII only supports chip-to-chip connections on a PCB, SQE functionality is not required.  
3.17 RX_ER  
The PHY provides RX_ER as an output according to the rules specified in IEEE 802.3u [2] (see Clause 24, Figure 24-  
11– Receive State Diagram). RX_ER is asserted for one or more REF_CLK periods to indicate that an error (e.g., a  
coding error or any error that a PHY is capable of detecting, and that may otherwise be undetectable by the MAC sub-  
layer) is detected somewhere in the frame presently being transferred from the PHY. RX_ER transitions synchronously  
with respect to REF_CLK. While CRS_DV is deasserted, RX_ER has no effect on the MAC.  
TABLE 3-2:  
Symbol  
RMII AC CHARACTERISTICS  
Parameter  
Min.  
Typ.  
Max.  
Units  
—
—
REF_CLK Frequency  
REF_CLK Duty Cycle  
—
50  
—
—
MHz  
%
35  
65  
2018 Microchip Technology Inc.  
DS00002813A-page 13  
KSZ8721BL/SL  
TABLE 3-2:  
Symbol  
tSU  
RMII AC CHARACTERISTICS  
Parameter  
Min.  
Typ.  
Max.  
Units  
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER  
4
—
—
ns  
TXD[1:0], TX_EN, RXD[1:0], CRS_DV, RXER  
Data Hold from REF_CLKRising Edge  
tH  
2
—
—
ns  
3.18 Unused RMII Pins  
Input Pins  
TXD[2:3] and TXER are pull-down to GND  
Output Pins RXD[2:3] and RXC are no connect.  
Note that the RMII pin needs to be pulled up to enable RMII mode.  
3.19 Auto-Crossover (Auto-MDI/MDI-X)  
Automatic MDI/MDI-X configuration is intended to eliminate the need for crossover cables between similar devices. The  
assignment of pinouts for a 10/100 BASE-T crossover function cable is shown below.  
This feature eliminates the confusion in applications by allowing the use of both straight and crossover cables. This fea-  
ture is controlled by register 1f:13. See Table 4-13 for details.  
FIGURE 3-1:  
STRAIGHT THROUGH CABLE  
10/100 Ethernet  
Media Dependent Interface  
10/100 Ethernet  
Media Dependent Interface  
1
1
Transmit Pair  
2
Receive Pair  
2
Straight  
Cable  
3
4
5
6
7
8
3
4
Receive Pair  
Transmit Pair  
5
6
7
8
Modular Connector  
(RJ-45)  
Modular Connector  
(RJ-45)  
NIC  
HUB  
(Repeater or Switch)  
DS00002813A-page 14  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
FIGURE 3-2:  
CROSSOVER CABLE  
10/100 Ethernet  
Media Dependent Interface  
10/100 Ethernet  
Media Dependent Interface  
1
1
Crossover  
Cable  
Receive Pair  
2
Receive Pair  
2
3
3
4
4
Transmit Pair  
5
Transmit Pair  
5
6
7
8
6
7
8
Modular Connector (RJ-45)  
HUB  
Modular Connector (RJ-45)  
HUB  
(Repeater or Switch)  
(Repeater or Switch)  
3.20 Power Management  
The KSZ8721BL/SL offers the following modes for power management:  
• Power-Down Mode: This mode can be achieved by writing to Register 0.11 or pulling pin 30 PD# low.  
• Power-Saving Mode: This mode can be disabled by writing to Register 1fh.10. The KSZ8721BL/SL turns off  
everything except for the Energy Detect and PLL circuits when the cable is not installed. In other words, the  
KSZ8721BL/SL shuts down most of the internal circuits to save power if there is no link. Power-saving mode is in  
the most effective state when auto-negotiation mode is enabled.  
3.21 100BT FX Mode  
Please contact your local field application engineer (FAE) for a reference schematic on fiber connection.  
100BT FX mode is activated when FXSD/FXEN is higher than 0.6V (this pin has a default pull down). Under this mode,  
the auto-negotiation and auto-MDI-X features are disabled.  
In fiber operation, the FXSD pin should connect to the signal detect (SD) output of the fiber module. The internal thresh-  
old of FXSD is around 1/2 VDD ±50 mV (1.25V ±0.05V). Above this level, the fiber signal is considered detected.  
The operation is summarized in Table 3-3:  
2018 Microchip Technology Inc.  
DS00002813A-page 15  
KSZ8721BL/SL  
TABLE 3-3:  
100BT FX MODE  
FXSD/FXEN  
Condition  
Less than 0.6V  
100TX mode  
FX mode  
No signal detected  
FEF generated  
Less than 1.25V,  
but greater than 0.6V  
FX mode  
Signal detected  
Greater than 1.25  
To ensure proper operation, the swing of fiber module SD should cover the threshold variation. Aresistive voltage divider  
is recommended to adjust the SD voltage range.  
Far End Fault (FEF), repetition of a special pattern which consists of 84-one and 1-zero, is generated under “FX mode  
with no signal detected.” The purpose of FEF is to notify the sender of a faulty link. When receiving an FEF, the LINK  
will go down to indicate a fault, even with fiber signal detected. The transmitter is not affected by receiving an FEF and  
still sends out its normal transmit pattern from MAC. FEF can be disabled by strapping pin 27 low. Refer to Table 2-2.  
3.22 Media Converter Operation  
The KSZ8721BL/SL is capable of performing media conversion with two parts in a back-to-back RMII loop-back mode  
as indicated in the diagram. Both parts are in RMII mode and with RMII BTB asserted (pins 21 and 22 strapped high).  
One part is operating in TX mode and the other is operating in FX mode. Both parts can share a common 50 MHz oscil-  
lator.  
Under this operation, auto-negotiation on the TX side prohibits 10BASE-T link-up. Additional options can be  
implemented under this operation. Disable the transmitter and set it at tri-state by controlling the high TXD2 pin. In order  
to do this, RXD2 and TXD2 pins need to be connected via inverter. When TXD2 pin is high in both the copper and fiber  
operation, it is disabled transmit. Meanwhile, the RXD2 pin on the copper side serves as the energy detect and can  
indicate if a line signal is detected. TXD3 should be tied low and RXD3 let float.  
FIGURE 3-3:  
FIBER MODULE  
VCC  
21 22  
Pin  
+/-  
Rx  
RxD  
KS8721BL/SL  
TxD  
Tx +/-  
FTx  
TxC/  
Ref_CLK  
OSC  
50MHz  
TxC/  
Ref_CLK  
TxD  
RxD  
KS8721BL/SL  
(Fiber Mode)  
FR  
x
Pin  
34  
Pin  
21 22  
To the SD pin of the  
Fiber Module  
VCC  
DS00002813A-page 16  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
3.23 Circuit Design Reference for Power Supply  
Microchip’s integrated built-in, voltage regulator technology and thoughtful implementation allows the user to save BOM  
cost on both existing and future designs with the use of the new KSZ8721BL/SL single supply, single port 10/100 Ether-  
net PHY.  
FIGURE 3-4:  
CIRCUIT DESIGN  
The circuit design in Figure 7-1 shows the power connections for the power supply: the 3.3V to VDDI/O is the only input  
power source and the 2.5V at VDDRCV, pin 38, is the output of the voltage regulator that needs to supply through the  
rest of the 2.5V VDD pins via the 2.5V power plane.  
The 2.5V VDD pins make the drop-in replacement with the existing KSZ8721B/BT part. Table 3-4 shows the drop-in  
replacement from the existing KSZ8721B/BT to the KSZ8721SL/BL. Please contact your local Microchip FAE for  
Application Note AN-117, “Drop-in Replacement with KSZ8721BT.”  
TABLE 3-4:  
DROP-IN REPLACEMENT  
2.5V/3.3V Supply  
3.3V Supply with Built-in Regulator  
Part Number  
KSZ8721B  
Package  
Part Number  
Package  
48-SSOP  
48-TQFP  
48-SSOP  
KSZ8721SL  
KSZ8721BL  
KSZ8721SLI  
48-SSOP  
48-LQFP  
48-SSOP  
KSZ8721BT  
KSZ8721BI  
2018 Microchip Technology Inc.  
DS00002813A-page 17  
KSZ8721BL/SL  
Notes:  
DS00002813A-page 18  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
4.0  
REGISTER MAP  
TABLE 4-1:  
REGISTER DESCRIPTION  
Register Number  
Description  
0h  
1h  
Basic Control Register  
Basic Status Register  
2h  
PHY Identifier I  
3h  
PHY Identifier II  
4h  
Auto-Negotiation Advertisement Register  
Auto-Negotiation Link Partner Ability Register  
Auto-Negotiation Expansion Register  
Auto-Negotiation Next Page Register  
Link Partner Next Page Ability  
RXER Counter Register  
5h  
6h  
7h  
8h  
15h  
1 bh  
1 fh  
Interrupt Control/Status Register  
100BASE-TX PHY Control Register  
TABLE 4-2:  
REGISTER 0H - BASIC CONTROL  
Bit  
Name  
Description  
Default  
Reference  
0.15  
Reset  
1 = Software reset. Bit is self-clearing  
RW/SC  
0
1 = Loop-back mode  
0 = Normal operation  
0.14  
Loop-Back  
RW  
0
1 = 100 Mbps  
0 = 10 Mbps  
Ignored if Auto-Negotiation is enabled (0.12 = 1)  
Set by  
SPD100  
0.13  
Speed Select (LSB)  
RW  
1 = Enable auto-negotiation process  
(override 0.13 and 0.8)  
0 = Disable auto-negotiation process  
Set by  
NWAYEN  
0.12  
0.11  
0.10  
Auto-Negotiation Enable  
Power Down  
RW  
RW  
RW  
1 = Power-down mode  
0 = Normal operation  
0
1 = Electrical isolation of PHY from MII and TX+/  
TX–  
Isolate  
Set by ISO  
0 = Normal operation  
1 = Restart auto-negotiation process  
0 = Normal operation. Bit is self-clearing  
0.9  
0.8  
Restart Auto-Negotiation  
Duplex Mode  
RW/SC  
RW  
0
1 = Full-duplex  
0 = Half-duplex  
Set by  
DUPLEX  
1 = Enable COL test  
0 = Disable COL test  
0.7  
0.6:1  
0.0  
Collision Test  
Reserved  
RW  
RO  
RW  
0
0
0
—
Disable  
Transmitter  
0 = Enable transmitter  
1 = Disable transmitter  
2018 Microchip Technology Inc.  
DS00002813A-page 19  
KSZ8721BL/SL  
TABLE 4-3:  
REGISTER 1H - BASIC STATUS  
Bit  
Name  
100BASE-T4  
Description  
Default  
Reference  
1 = T4 capable  
0 = Not T4 capable  
1.15  
RO  
0
100BASE-TX Full-Duplex 1 = Capable of 100BASE-X full-duplex  
0 = Not capable of 100BASE-X full-duplex  
1.14  
1.13  
1.12  
1.11  
RO  
RO  
RO  
RO  
1
1
1
1
100BASE-TX Half-Duplex 1 = Capable of 100BASE-X half-duplex  
0 = Not capable of 100BASE-X half-duplex  
10BASE-T Full-Duplex  
1 = 10 Mbps with full-duplex  
0 = No 10 Mbps with full-duplex capability  
10BASE-T Half-Duplex  
1 = 10 Mbps with half-duplex  
0 = No 10 Mbps with half-duplex capability  
1.10:7 Reserved  
—
RO  
RO  
0
1
1.6  
1.5  
1.4  
1.3  
1.2  
1.1  
1.0  
No Preamble  
1 = Preamble suppression  
0 = Normal preamble  
Auto-Negotiation Complete 1 = Auto-negotiation process completed  
0 = Auto-negotiation process not completed  
RO  
0
Remote Fault  
1 = Remote fault  
0 = No remote fault  
RO/LH  
RO  
0
1
Auto-Negotiation Ability  
Link Status  
1 = Capable to perform auto-negotiation  
0 = Unable to perform auto-negotiation  
1 = Link is up  
0 = Link is down  
RO/LL  
RO/LH  
RO  
0
0
1
Jabber Detect  
1 = Jabber detected  
0 = Jabber not detected. Default is low  
Extended Capability  
1 = Supports extended capabilities registers  
TABLE 4-4:  
REGISTER 2H - PHY IDENTIFIER 1  
Bit  
Name  
Description  
Default  
Reference  
Assigned to the 3rd through 18th bits of the organi-  
2.15:0 PHY ID Number  
zationally unique identifier (OUI). Microchip’s OUI RO  
is 0010A1 (hex).  
0022h  
TABLE 4-5:  
REGISTER 3H - PHY IDENTIFIER 2  
Bit  
Name  
Description  
Default  
Reference  
Assigned to the 19th through 24th bits of the orga-  
nizationally unique identifier (OUI). Microchip’s  
OUI is 0010A1 (hex).  
3.15:0 PHY ID Number  
RO  
000101  
3.9:4  
3.3:0  
Model Number  
Six bit manufacturer’s model number  
Four bit manufacturer’s model number  
RO  
RO  
100001  
1001  
Revision Number  
TABLE 4-6:  
REGISTER 4H - AUTO-NEGOTIATION ADVERTISEMENT  
Bit  
Name  
Description  
Default  
Reference  
1 = Next page capable  
0 = No next page capability  
4.15  
4.14  
4.13  
Next page  
RW  
RO  
RW  
RO  
0
0
0
0
Reserved  
—
1 = Remote fault supported  
0 = No remote fault  
Remote Fault  
4.12:11 Reserved  
—
DS00002813A-page 20  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
TABLE 4-6:  
REGISTER 4H - AUTO-NEGOTIATION ADVERTISEMENT (CONTINUED)  
Bit  
Name  
Description  
Default  
Reference  
1 = Pause function supported  
0 = No pause function  
4.10  
Pause  
RW  
0
1 = T4 capable  
0 = No T4 capability  
4.9  
4.8  
100BASE-T4  
RO  
0
Set by  
SPD100 &  
DUPLEX  
1 = TX with full-duplex  
0 = No TX full-duplex capability  
100BASE-TX Full-Duplex  
RW  
1 = TX capable  
0 = No TX capability  
Set by  
SPD100  
4.7  
4.6  
100BASE-TX  
RW  
RW  
RW  
RW  
1 = 10 Mbps with full-duplex  
0 = No 10 Mbps full-duplex capability  
Set by  
DUPLEX  
10BASE-T Full-Duplex  
10BASE-T  
1 = 10 Mbps capable  
0 = No 10 Mbps capability  
4.5  
1
1 = 10 Mbps capable  
0 = No 10 Mbps capability  
4.4:0  
Selector Field  
00001  
TABLE 4-7:  
REGISTER 5H - AUTO-NEGOTIATION LINK PARTNER ABILITY  
Bit  
Name  
Description  
Default  
Reference  
1 = Next page capable  
0 = No next page capability  
5.15  
Next page  
RO  
0
1 = Link code word received from partner  
0 = Link code word not yet received  
5.14  
Acknowledge  
RO  
0
5.13  
5.12  
Remote Fault  
Reserved  
1 = Remote fault detected; 0 = no remote fault  
RO  
RO  
0
0
—
5.10 5.11  
0
0
No PAUSE  
0
1
5.11:10 Pause  
Asymmetric PAUSE (link partner)  
RO  
0
1
0
Symmetric PAUSE  
1
1
Symmetric & Asymmetric PAUSE (local device)  
1 = T4 capable  
0 = No T4 capability  
5.9  
5.8  
5.7  
5.6  
100 BASE-T4  
RO  
RO  
RO  
RO  
0
0
0
0
1 = TX with full-duplex  
0 = No TX full-duplex capability  
100BASE-TX Full-Duplex  
100BASE-TX  
1 = TX capable  
0 = No TX capability  
1 = 10 Mbps with full-duplex  
0 = No 10 Mbps full-duplex capability  
10BASE-T Full-Duplex  
1 = 10 Mbps capable  
0 = No 10 Mbps capability  
5.5  
10BASE-T  
RO  
RO  
0
5.4:0  
Selector Field  
[00001] = IEEE 802.3  
00001  
2018 Microchip Technology Inc.  
DS00002813A-page 21  
KSZ8721BL/SL  
TABLE 4-8:  
REGISTER 6H - AUTO-NEGOTIATION EXPANSION  
Bit  
Name  
Description  
Default  
Reference  
6.15:5 Reserved  
—
RO  
0
1 = Fault detected by parallel detection  
0 = No fault detected by parallel detection  
6.4  
6.3  
6.2  
6.1  
Parallel Detection Fault  
RO/LH  
RO  
0
0
1
0
Link Partner Next Page  
Able  
1 = Link partner has next page capability  
0 = Link partner does not have next page capability  
1 = Local device has next page capability  
0 = Local device does not have next page capability  
Next Page Able  
Page Received  
RO  
1 = New page received  
0 = New page not yet received  
RO/LH  
1 = Link partner has auto-negotiation capability  
0 = Link partner does not have auto-negotiation  
capability  
Link Partner  
Auto-Negotiation Able  
6.0  
RO  
0
TABLE 4-9:  
REGISTER 7H - AUTO-NEGOTIATION NEXT PAGE  
Bit  
Name  
Description  
Default  
Reference  
1 = Additional next page(s) will follow  
0 = Last page  
7.15  
7.14  
7.13  
Next Page  
RW  
RP  
0
0
1
Reserved  
—
1 = Message page  
0 = Unformatted page  
Message Page  
RW  
1 = Will comply with message  
0 = Cannot comply with message  
7.12  
7.11  
Acknowledge 2  
Toggle  
RW  
0
1 = Previous value of the transmitted link code  
word equaled logic One  
RO  
0
0 = Logic Zero  
7.10:0 Message Field  
11-bit wide field to encode 2048 messages  
RW  
001  
TABLE 4-10: REGISTER 8H - LINK PARTNER NEXT PAGE ABILITY  
Bit  
Name  
Description  
Default  
Reference  
1 = Additional next page(s) will follow  
0 = Last page  
8.15  
Next Page  
RO  
0
1 = Successful receipt of link word  
0 = No successful receipt of link word  
8.14  
8.13  
8.12  
Acknowledge  
Message Page  
Acknowledge 2  
RO  
RO  
RO  
0
0
0
1 = Message Page  
0 = Unformatted page  
1 = Able to act on the information  
0 = Not able to act on the information  
1 = Previous value of transmitted link code word  
equal to logic zero  
0 = Previous value of transmitted link code word  
equal to logic one  
8.11  
Toggle  
RO  
RO  
0
0
8.10:0 Message Field  
—
TABLE 4-11: REGISTER 15H - RXER COUNTER  
Bit Name Description  
Default  
Reference  
15.15:0 RXER Counter  
RX Error counter for the RX_ER in each package RO  
000  
DS00002813A-page 22  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
TABLE 4-12: REGISTER 1BH - INTERRUPT CONTROL/STATUS REGISTER  
Bit  
Name  
Description  
Default  
Reference  
1 = Enable jabber interrupt  
0 = Disable jabber interrupt  
1b.15  
Jabber Interrupt Enable  
RW  
0
Receive Error  
Interrupt Enable  
1 = Enable receive error interrupt  
0 = Disable receive error interrupt  
1b.14  
1b.13  
1b.12  
1b.11  
1b.10  
1b.9  
1b.8  
1b.7  
1b.6  
1b.5  
1b.4  
1b.3  
1b.2  
1b.1  
1b.0  
RW  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Page Received  
Interrupt Enable  
1 = Enable page received interrupt  
0 = Disable page received interrupt  
RW  
Parallel Detect Fault  
Interrupt Enable  
1 = Enable parallel detect fault interrupt  
0 = Disable parallel detect fault interrupt  
RW  
Link Partner Acknowledge 1 = Enable link partner acknowledge interrupt  
Interrupt Enable  
RW  
0 = Disable link partner acknowledge interrupt  
Link Down  
Interrupt Enable  
1 = Enable link down interrupt  
0 = Disable link down interrupt  
RW  
Remote Fault  
Interrupt Enable  
1 = Enable remote fault interrupt  
0 = Disable remote fault interrupt  
RW  
1 = Enable link up interrupt  
0 = Disable link up interrupt  
Link Up Interrupt Enable  
Jabber Interrupt  
RW  
1 = Jabber interrupt occurred  
0 = Jabber interrupt has not occurred  
RO/SC  
RO/SC  
RO/SC  
RO/SC  
RO/SC  
RO/SC  
RO/SC  
RO/SC  
1 = Receive error occurred  
0 = Receive error has not occurred  
Receive Error Interrupt  
Page Receive Interrupt  
1 = Page receive occurred  
0 = Page receive has not occurred  
Parallel Detect  
Fault Interrupt  
1 = Parallel detect fault occurred  
0 = Parallel detect fault has not occurred  
Link Partner  
Acknowledge Interrupt  
1 = Link partner acknowledge occurred  
0 = Link partner acknowledge has not occurred  
1 = Link down occurred  
0 = Link down has not occurred  
Link Down Interrupt  
Remote Fault Interrupt  
Link Up Interrupt  
1 = Remote fault occurred  
0 = Remote fault has not occurred  
1 = Link up interrupt occurred  
0 = Link up interrupt has not occurred  
2018 Microchip Technology Inc.  
DS00002813A-page 23  
KSZ8721BL/SL  
TABLE 4-13: REGISTER 1FH - 100BASE-TX PHY CONTROLLER  
Bit  
Name  
Description  
Default  
Reference  
1f.15:14 Reserved  
—
RO  
0
1 = Disable MDI/MDI-X  
0 = Enable MDI/MDI-X  
1f.13  
1f.12  
Pairswap Disable  
RW  
RO  
0
0
1 = Presence of signal on RX+/RX– analog wire pair  
0 = No signal detected on RX+/RX–  
Energy Detect  
Force Link  
1 = Force link pass  
0 = Normal link operation  
This bit bypasses the control logic and allow trans-  
mitter to send pattern even if there is no link.  
1f.11  
RW  
0
1 = Enable power-saving  
0 = Disable  
1f.10  
1f.9  
1f.8  
1f.7  
1f.6  
1f.5  
Power Saving  
Interrupt Level  
Enable Jabber  
RW  
RW  
RW  
RW  
RO  
RO  
1
0
1
0
0
0
1 = Interrupt pin active high  
0 = Active low  
1 = Enable jabber counter  
0 = Disable  
Auto-Negotiation  
Complete  
1 = Auto-negotiation complete  
0 = Not complete  
Enable Pause  
(Flow-Control Result)  
1 = Flow control capable  
0 = No flow control  
1 = PHY in isolate mode  
0 = Not isolated  
PHY Isolate  
[000] = Still in auto-negotiation  
[001] = 10BASE-T half-duplex  
[010] = 100BASE-TX half-duplex  
[011] = Reserved  
[101] = 10BASE-T full-duplex  
[110] = 100BASE-TX full-duplex  
[111] = PHY/MII isolate  
Operation Mode  
Indication  
1f.4:2  
RO  
0
1 = Enable SQE test  
0 = Disable  
1f.1  
1f.0  
Enable SQE Test  
RW  
RW  
0
0
1 = Disable scrambler  
0 = Enable  
Disable Data Scrambling  
Note 4-1  
RW = Read/Write  
RO = Read Only  
SC = Self Clear  
LH = Latch High  
LL = Latch Low  
Some of the default values are set by strap-in. See Table 2-2.  
DS00002813A-page 24  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
5.0  
5.1  
OPERATIONAL CHARACTERISTICS  
Absolute Maximum Ratings*  
Storage Temperature (TS)...................................................................................................................... –55°C to +150°C  
Supply Referenced to GND ...................................................................................................................... –0.5V to +4.0V  
All Pins ...................................................................................................................................................... –0.5V to +4.0V  
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating  
may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-  
ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect  
reliability.  
5.2  
Operating Ratings**  
Supply Voltage  
(VDD_PLL, VDD_TX, VDD_RXC, VDD_RCV, VDDC).........................................................................................................+2.5V  
(VDDIO).....................................................................................................................................................................+3.3V  
Ambient Temperature (TA)  
Commercial..................................................................................................................................................0°C to +70°C  
Industrial .................................................................................................................................................. –40°C to +85°C  
Package Thermal Resistance (Note 5-1)  
LQFP (θJA) No Airflow....................................................................................................................................+83.56°C/W  
SSOP (θJA) No Airflow ...................................................................................................................................+75.19°C/W  
**The device is not guaranteed to function outside its operating ratings. Unused inputs must always be tied to an appro-  
priate logic voltage level (GROUND to VDD_IO).  
Note 5-1  
No (HS) heat spreader in this package.  
2018 Microchip Technology Inc.  
DS00002813A-page 25  
KSZ8721BL/SL  
6.0  
ELECTRICAL CHARACTERISTICS  
TABLE 6-1:  
ELECTRICAL CHARACTERISTICS (Note 6-1)  
VDD = 3.3V ±10%  
Parameters  
Symbol  
Min.  
Typ.  
Max.  
Units Conditions  
Total Supply Current (Including TX Output Driver Current) (Note 6-2)  
Normal 100BASE-TX  
IDD1  
IDD2  
—
—
116  
151  
—
—
mA Including 43 mA output current  
Normal 100BASE-TX  
(Independent of utilization)  
Including 103 mA output  
mA  
current  
Power Saving Mode 1  
Power Down Mode  
TTL Inputs  
IDD3  
IDD5  
—
—
47  
4
—
—
mA Auto-negotiation is enable  
mA  
—
1/2VDD(I/O)  
+0.2  
Input High Voltage  
VIH  
—
—
V
—
Input Low Voltage  
Input Current  
VIL  
IIN  
—
—
—
0.8  
10  
V
—
–10  
µA  
VIN = GND ~ VDDIO  
TTL Outputs  
1/2VDD(I/O)  
+0.6  
Output High Voltage  
VOH  
—
—
V
IOH = –4mA  
Output Low Voltage  
VOL  
IOZ  
—
—
—
—
0.4  
10  
V
IOL = 4mA  
—
Output Tri-state Leakage  
100Base-TX Receive  
µA  
RX+/RX– Differential Input  
Resistance  
—
—
8
—
kΩ  
ns  
—
RIN  
Propagation Delay  
50  
110  
From magnetics to RDTX  
10Base-TX Transmit (Measured Differentially After 1:1 Transformer)  
Peak Differential Output  
Voltage  
VO  
0.95  
—
1.05  
V
50Ω from each output to VDD  
Output Voltage Imbalance  
Rise/Fall Time  
VIMB  
—
3
—
—
2
5
%
ns  
50Ω from each output to VDD  
—
Rise/Fall Time Imbalance  
Duty Cycle Distortion  
Overshoot  
0
—
0.5  
±0.5  
5
ns  
—
tr, tf  
—
—
—
—
—
—
ns  
—
—
%
—
Reference Voltage of ISET  
Propagation Delay  
Jitters  
0.75  
45  
—
V
—
VSET  
60  
1.4  
ns  
From TDTX to magentics  
—
0.7  
ns(PP)  
10Base-TX Receive  
RX+/RX– Differential Input  
Resistance  
RIN  
—
—
8
—
—
kW  
—
Squelch Threshold  
VSQ  
400  
mV 5 MHz square wave  
100Base-TX Transmit (Measured Differentially After 1:1 Transformer)  
Peak Differential Output  
Voltage  
2.2  
—
2.8  
V
50Ω from each output to VDD  
VP  
Jitters Added  
—
—
—
±3.5  
—
ns  
ns  
50Ω from each output to VDD  
—
Rise/Fall Time  
Clock Outputs  
Crystal Oscillator  
Receive Clock, 100TX  
tr, tf  
25  
X1, X2  
—
—
25  
25  
—
—
MHz  
MHz  
—
—
RXC100  
DS00002813A-page 26  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
TABLE 6-1:  
ELECTRICAL CHARACTERISTICS (Note 6-1) (CONTINUED)  
VDD = 3.3V ±10%  
Parameters  
Symbol  
Min.  
Typ.  
Max.  
Units Conditions  
MHz  
ns(pp) —  
Receive Clock, 10T  
Receive Clock Jitters  
Transmit Clock, 100TX  
Transmit Clock, 10T  
Transmit Clock Jitters  
—
—
—
—
—
2.5  
3.0  
25  
—
—
—
—
—
—
RXC10  
TXC100  
TXC10  
MHz  
MHz  
—
—
2.5  
1.8  
ns(pp) —  
Note 6-1  
Note 6-2  
TA = 25°C. Specification for packaged product only.  
There is 100% data transmission in full-duplex mode and a minimum IPG with a 130 meter cable.  
2018 Microchip Technology Inc.  
DS00002813A-page 27  
KSZ8721BL/SL  
7.0  
7.1  
TIMING SPECIFICATIONS  
10BASE-T MII Transmit Timing  
FIGURE 7-1:  
10BASE-T MII TRANSMIT TIMING  
TXC  
tHD2  
tHD1  
tSU2  
TXEN  
TXD[3:0]  
CRS  
tSU1  
tCRS1  
tCRS2  
Valid  
Data  
TXP/TXM  
tLAT  
SQE Timing  
TXC  
TXEN  
COL  
tSQE  
tSQEP  
TABLE 7-1:  
Parameter  
10BASE-T MII TRANSMIT TIMING PARAMETERS  
Symbol  
Min.  
Typ.  
Max.  
Units  
TXD [3:0] Set-Up to TXC High  
tSU1  
tSU2  
10  
10  
0
—
—
—
—
4
—
—
—
—
—
—
—
—
—
ns  
TXEN Set-Up to TXC High  
ns  
TXD [3:0] Hold After TXC High  
tHD1  
ns  
TXEN Hold After TXC High  
tHD2  
0
ns  
TXEN High to CRS Asserted Latency  
TXEN Low to CRS De-Asserted Latency  
TXEN High to TXP/TXM Output (TX Latency)  
COL (SQE) Delay After TXEN De-Asserted  
COL (SQE) Pulse Duration  
tCRS1  
tCRS2  
tLAT  
—
—
—
—
—
BT (Note 7-1)  
8
BT  
BT  
µs  
µs  
4
tSQE  
tSQEP  
2.5  
1.0  
Note 7-1  
1BT = 10 ns at 10BASE-TX.  
DS00002813A-page 28  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
7.2  
100BASE-T MII Transmit Timing  
FIGURE 7-2:  
100BASE-T MII TRANSMIT TIMING  
TXC  
tHD2  
tSU2  
TXEN  
tHD1  
tSU1  
TXD[3:0],  
TXER  
Data  
In  
tCRS2  
tCRS1  
tLAT  
CRS  
Symbol  
Out  
TX+/TX-  
TABLE 7-2:  
Parameter  
100BASE-T MII TRANSMIT TIMING PARAMETERS  
Symbol  
Min.  
Typ.  
Max.  
Units  
TXD [3:0] Set-Up to TXC High  
TXEN Set-Up to TXC High  
tSU1  
tSU2  
tHD1  
tHD2  
tHD3  
tCRS1  
tCRS2  
tLAT  
10  
10  
0
—
—
—
—
—
4
—
—
—
—
—
—
—
—
ns  
ns  
TXD [3:0] Hold After TXC High  
TXER Hold After TXC High  
ns  
0
ns  
TXEN Hold After TXC High  
0
ns  
BT (Note 7-1)  
BT  
TXEN High to CRS Asserted Latency  
TXEN Low to CRS De-Asserted Latency  
TXEN High to TXP/TXM Output (TX Latency)  
—
—
—
4
9
BT  
Note 7-1  
1BT = 10 ns at 100BASE-TX  
2018 Microchip Technology Inc.  
DS00002813A-page 29  
KSZ8721BL/SL  
7.3  
100BASE-T MII Receive Timing  
FIGURE 7-3:  
100BASE-T MII RECEIVE TIMING  
Start of  
Stream  
End of  
Stream  
RX+/RX-  
tCRS1  
CRS  
tCRS2  
RXDV  
tRLAT  
tHD  
RXD[3:0]  
RXER  
tSU  
tWH  
RXC  
tWL  
tP  
TABLE 7-3:  
Parameter  
100BASE-T MII RECEIVE TIMING PARAMETERS  
Symbol  
Min.  
Typ.  
Max.  
Units  
RXC Period  
tP  
—
20  
40  
—
—
20  
20  
6
—
—
ns  
ns  
ns  
ns  
ns  
BT  
ns  
ns  
RXC Pulse Width  
RXC Pulse Width  
tWL  
tWH  
tSU  
tHD  
20  
—
RXD [3:0], RXER, RXDV Set-Up to Rising Edge of RXC  
RXD [3:0], RXER, RXDV Hold from Rising Edge of RXC  
CRS to RXD Latency, 4B or 5B Aligned  
—
—
—
—
tRLAT  
tCRS1  
tCRS2  
—
—
“Start of Stream” to CSR Asserted  
106  
154  
—
—
138  
186  
“End of Stream” to CSR De-Asserted  
DS00002813A-page 30  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
7.4  
Auto-Negotiation  
FIGURE 7-4:  
AUTO-NEGOTIATION/FAST LINK PULSE TIMING  
FLP  
Burst  
FLP  
Burst  
TX+/TX-  
tFLPW  
tBTB  
Clock  
Pulse  
Data  
Pulse  
Clock  
Pulse  
Data  
Pulse  
TX+/TX-  
tPW  
tPW  
tCTD  
tCTC  
TABLE 7-4:  
Parameter  
AUTO-NEGOTIATION/FAST LINK PULSE TIMING PARAMETERS  
Symbol  
Min.  
Typ.  
Max.  
Units  
FLP Burst to FLP Burst  
tBTB  
tFLPW  
tPW  
8
16  
2
24  
—
—
—
—
33  
ms  
ms  
ns  
FLP Burst Width  
—
—
—
—
17  
Clock/Data Pulse Width  
Clock Pulse to Data Pulse  
Clock Pulse to Clock Pulse  
Number of Clock/Data Pulses per Burst  
100  
69  
tCTD  
µs  
136  
—
tCTC  
µs  
2018 Microchip Technology Inc.  
DS00002813A-page 31  
KSZ8721BL/SL  
7.5  
SMI Timing  
FIGURE 7-5:  
SERIAL MANAGEMENT INTERFACE TIMING  
tP  
MDC  
tMD1  
tMD2  
MDIO  
(Into Chip)  
Valid  
Data  
Valid  
Data  
tMD3  
MDIO  
(Out of Chip)  
Valid  
Data  
TABLE 7-5:  
SERIAL MANAGEMENT INTERFACE TIMING PARAMETERS  
Parameter  
Symbol  
Min.  
Typ.  
Max.  
Units  
MDC Period  
tP  
—
10  
10  
—
400  
—
—
—
—
—
ns  
ns  
ns  
ns  
MDIO Set-Up to MDC (MDIO as Input)  
MDIO Hold After MDC (MDIO as Input)  
MDC to MDIO Valid (MDIO as Output)  
tMD1  
tMD2  
tMD3  
—
222  
DS00002813A-page 32  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
7.6  
Reset Timing  
FIGURE 7-6:  
RESET TIMING  
Supply  
Voltage  
tsr  
RST_N  
Strap-In  
Value  
TABLE 7-6:  
Parameter  
RESET TIMING PARAMETERS  
Symbol  
Min.  
Typ.  
Max.  
Units  
Stable Supply Voltages to Reset High  
fSR  
50  
—
—
µs  
7.6.1  
RESET CIRCUIT DIAGRAM  
The following discrete reset circuit as shown in Figure 7-7 is recommended when powering up the KSZ8721BL/SL  
device. For the application where the reset circuit signal comes from another device (e.g., CPU, FPGA, etc), please  
refer to the reset circuit as shown in Figure 7-8.  
FIGURE 7-7:  
RECOMMENDED RESET CIRCUIT  
2018 Microchip Technology Inc.  
DS00002813A-page 33  
KSZ8721BL/SL  
FIGURE 7-8:  
RECOMMENDED CIRCUIT FOR INTERFACING WITH CPU/FPGA RESET  
VCC  
R
D1  
ꢀꢁNȍ  
KS8721BL/SL  
RST  
CPU/FPGA  
RST_OUT_n  
D2  
C
10μF  
D1, D2: 1N4148  
At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the device. The reset out from CPU/  
FPGA provides warm reset after power up. It is also recommended to power up the VDD core voltage earlier than VDDIO  
voltage. At worst case, the both VDD core and VDDIO voltages should come up at the same time.  
7.6.2  
REFERENCE CIRCUIT FOR STRAPPING OPTION CONFIGURATION  
Figure 7-9 shows the reference circuit for strapping option pins.  
FIGURE 7-9:  
REFERENCE CIRCUIT, STRAPPING OPTION PINS  
2.5V  
220:  
Pull-Up  
10k:  
LED pin  
KS8721BL/SL  
2.5V  
220:  
Pull-down  
LED pin  
KS8721BL/SL  
1k:  
Reference circuits for unmanaged programming through LED ports.  
DS00002813A-page 34  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
7.7  
Selection of Isolation Transformers  
One simple 1:1 isolation transformer is needed at the line interface. An isolation transformer with integrated common-  
mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer  
characteristics.  
TABLE 7-7:  
Parameter  
Turns ratio  
SELECTION OF ISOLATION TRANSFORMERS (Note 7-1)  
Value  
Test Condition  
1 CT : 1 CT  
350 µH  
0.4 µH  
—
Open-circuit inductance (min)  
Leakage inductance (max)  
Inter-winding capacitance (max)  
D.C. resistance (max)  
Insertion loss (max)  
100 mV, 100 kHz, 8 mA  
1 MHz (min)  
12 pF  
—
0.9Ω  
—
0 MHz - 65 MHz  
—
1.0 dB  
HIPOT (min)  
1500Vrms  
Note 7-1  
The IEEE 802.3u standard for 100BASE-TX assumes a transformer loss of 0.5dB. For the transmit  
line transformer, insertion loss of up to 1.3 dB can be compensated or by increasing the line drive  
current by means of reducing the ISET resistor value. Please select the transformer that supports  
auto-MDI/MDI-X.  
7.8  
Selection of Reference Crystal  
An oscillator or crystal with the following typical characteristics is recommended.  
TABLE 7-8:  
SELECTION OF ISOLATION TRANSFORMERS  
Characteristics  
Value  
Frequency  
25 MHz  
±100 ppm  
20 pF  
Frequency tolerance (max)  
Load capacitance (max)  
Series resistance (max)  
40Ω  
TABLE 7-9:  
QUALIFIED SINGLE PORT TRANSFORMER LISTS  
Single Port Magnetic Manufacturer  
Part Number  
Auto MDIX  
Pulse  
H1102  
S558-5999-U7  
PT163020  
HB726  
Yes  
Yes  
Yes  
Yes  
Yes  
Yes  
Bel Fuse  
YCL  
Transpower  
Delta  
LF8505  
LanKom  
LF-H41S  
Integrated Transformers  
Pulse  
Pulse  
J0011D21  
J00-0061  
Yes  
Yes  
2018 Microchip Technology Inc.  
DS00002813A-page 35  
KSZ8721BL/SL  
8.0  
8.1  
PACKAGING INFORMATION  
Package Marking Information  
48-Lead SSOP*  
Example  
MICREL  
MICREL  
XXXXXXXXX  
KSZ8721SL  
1736A4G000001736200  
YYWWA4GXXXXXYYWWNNN  
Example  
48-Lead LQFP*  
MICREL  
MICREL  
KSZ8721BL  
1641A4O  
XXXXXXXXX  
YYWWA4O  
GXXXXXYYWWNNN  
G000001641230  
Legend: XX...X Product code or customer-specific information  
Y
Year code (last digit of calendar year)  
YY  
WW  
NNN  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)  
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
*
e
3
)
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle  
mark).  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information. Package may or may not include  
the corporate logo.  
Underbar (_) and/or Overbar (‾) symbol may not be to scale.  
DS00002813A-page 36  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
FIGURE 8-1:  
48-LEAD LQFP 7 MM X 7 MM PACKAGE OUTLINE & RECOMMENDED LAND  
PATTERN  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging.  
2018 Microchip Technology Inc.  
DS00002813A-page 37  
KSZ8721BL/SL  
FIGURE 8-2:  
48-LEAD SSOP 7 MM X 7 MM PACKAGE OUTLINE & RECOMMENDED LAND  
PATTERN  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging.  
DS00002813A-page 38  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
APPENDIX A: DATA SHEET REVISION HISTORY  
TABLE A-1:  
REVISION HISTORY  
Revision  
Section/Figure/Entry  
Correction  
Converted Micrel data sheet KSZ8721BL/SL to  
Microchip DS00002813A. Minor text changes  
throughout.  
DS00002813A (10-30-18)  
—
2018 Microchip Technology Inc.  
DS00002813A-page 39  
KSZ8721BL/SL  
THE MICROCHIP WEB SITE  
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make  
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-  
tains the following information:  
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s  
guides and hardware support documents, latest software releases and archived software  
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion  
groups, Microchip consultant program member listing  
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-  
nars and events, listings of Microchip sales offices, distributors and factory representatives  
CUSTOMER CHANGE NOTIFICATION SERVICE  
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive  
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or  
development tool of interest.  
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-  
cation” and follow the registration instructions.  
CUSTOMER SUPPORT  
Users of Microchip products can receive assistance through several channels:  
• Distributor or Representative  
• Local Sales Office  
• Field Application Engineer (FAE)  
• Technical Support  
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales  
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-  
ment.  
Technical support is available through the web site at: http://microchip.com/support  
DS00002813A-page 40  
2018 Microchip Technology Inc.  
KSZ8721BL/SL  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Example:  
X
-XX  
PART NO.  
Device  
X
X
Supply  
Voltage  
Media  
Type  
Package  
Temperature  
a) KSZ8721-BL:  
b) KSZ8721-SL:  
c) KSZ8721-BLI:  
d) KSZ8721-SLI:  
10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
LQFP, Single 3.3V Supply,  
0C to +70C,250/Tray  
Device:  
KSZ8721  
10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
SSOP, Single 3.3V Supply,  
0C to +70C,30/Tube  
B = 48-Lead LQFP  
S = 48-Lead SSOP  
Package:  
10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
LQFP, Single 3.3V Supply,  
–40°C to +85°C,250/Tray  
Supply Voltage:  
Temperature:  
L = Single 3.3V Supply  
<blank> = 0C to +70C  
I = –40°C to +85°C  
10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
SSOP, Single 3.3V Supply,  
–40°C to +85°C,30/Tube  
Media Type:  
<blank> = 30/Tube (SSOP Package Only)  
<blank> = 250/Tray (LQFP package Only)  
<TR> = 1000/Reel  
e) KSZ8721-BL-TR: 10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
LQFP, Single 3.3V Supply,  
0C to +70C,1000/Reel  
f) KSZ8721-SL-TR:  
10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
SSOP, Single 3.3V Supply,  
0C to +70C, 1000/Tray  
g) KSZ8721-BLI-TR: 10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
LQFP, Single 3.3V Supply,  
–40°C to +85°C,1000/Reel  
d) KSZ8721-SLI-TR: 10/100 Base-TX/FX MII Physical  
Layer Transceiver, 48-Lead  
SSOP, Single 3.3V Supply,  
–40°C to +85°C,1000/Reel  
Note 1:  
Tape and Reel identifier only appears in the  
catalog part number description. This  
identifier is used for ordering purposes and  
is not printed on the device package. Check  
with your Microchip Sales Office for  
package availability with the Tape and Reel  
option.  
2018 Microchip Technology Inc.  
DS00002813A-page 41  
KSZ8721BL/SL  
NOTES:  
DS00002813A-page 42  
2018 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be  
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO  
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,  
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Micro-  
chip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold  
harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or  
otherwise, under any Microchip intellectual property rights unless otherwise stated.  
Trademarks  
The Microchip name and logo, the Microchip logo, AnyRate, AVR, AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo, CryptoMemory,  
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus, maXTouch, MediaLB, megaAVR,  
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch, SAM-BA, SpyNIC, SST, SST  
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other  
countries.  
ClockWorks, The Embedded Control Solutions Company, EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS, mTouch, Precision  
Edge, and Quiet-Wire are registered trademarks of Microchip Technology Incorporated in the U.S.A.  
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard, CryptoAuthentication,  
CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, EtherGREEN,  
In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,  
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM,  
PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,  
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are  
trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.  
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.  
Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries.  
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other  
countries.  
All other trademarks mentioned herein are property of their respective companies.  
© 2018, Microchip Technology Incorporated, All Rights Reserved.  
ISBN: 978-1-5224-3789-5  
Microchip received ISO/TS-16949:2009 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
QUALITYꢀMANAGEMENTꢀꢀSYSTEMꢀ  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
CERTIFIEDꢀBYꢀDNVꢀ  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
== ISO/TSꢀ16949ꢀ==ꢀ  
2018 Microchip Technology Inc.  
DS00002813A-page 43  
Worldwide Sales and Service  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://www.microchip.com/  
support  
Australia - Sydney  
Tel: 61-2-9868-6733  
India - Bangalore  
Tel: 91-80-3090-4444  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
China - Beijing  
Tel: 86-10-8569-7000  
India - New Delhi  
Tel: 91-11-4160-8631  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
China - Chengdu  
Tel: 86-28-8665-5511  
India - Pune  
Tel: 91-20-4121-0141  
Finland - Espoo  
Tel: 358-9-4520-820  
China - Chongqing  
Tel: 86-23-8980-9588  
Japan - Osaka  
Tel: 81-6-6152-7160  
Web Address:  
www.microchip.com  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
China - Dongguan  
Tel: 86-769-8702-9880  
Japan - Tokyo  
Tel: 81-3-6880- 3770  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
China - Guangzhou  
Tel: 86-20-8755-8029  
Korea - Daegu  
Tel: 82-53-744-4301  
Germany - Garching  
Tel: 49-8931-9700  
China - Hangzhou  
Tel: 86-571-8792-8115  
Korea - Seoul  
Tel: 82-2-554-7200  
Germany - Haan  
Tel: 49-2129-3766400  
Austin, TX  
Tel: 512-257-3370  
China - Hong Kong SAR  
Tel: 852-2943-5100  
Malaysia - Kuala Lumpur  
Tel: 60-3-7651-7906  
Germany - Heilbronn  
Tel: 49-7131-67-3636  
Boston  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
China - Nanjing  
Tel: 86-25-8473-2460  
Malaysia - Penang  
Tel: 60-4-227-8870  
Germany - Karlsruhe  
Tel: 49-721-625370  
China - Qingdao  
Philippines - Manila  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Tel: 86-532-8502-7355  
Tel: 63-2-634-9065  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
China - Shanghai  
Tel: 86-21-3326-8000  
Singapore  
Tel: 65-6334-8870  
Germany - Rosenheim  
Tel: 49-8031-354-560  
China - Shenyang  
Tel: 86-24-2334-2829  
Taiwan - Hsin Chu  
Tel: 886-3-577-8366  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
Israel - Ra’anana  
Tel: 972-9-744-7705  
China - Shenzhen  
Tel: 86-755-8864-2200  
Taiwan - Kaohsiung  
Tel: 886-7-213-7830  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
China - Suzhou  
Tel: 86-186-6233-1526  
Taiwan - Taipei  
Tel: 886-2-2508-8600  
Detroit  
Novi, MI  
Tel: 248-848-4000  
China - Wuhan  
Tel: 86-27-5980-5300  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Italy - Padova  
Tel: 39-049-7625286  
Houston, TX  
Tel: 281-894-5983  
China - Xian  
Tel: 86-29-8833-7252  
Vietnam - Ho Chi Minh  
Tel: 84-28-5448-2100  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Indianapolis  
Noblesville, IN  
Tel: 317-773-8323  
Fax: 317-773-5453  
Tel: 317-536-2380  
China - Xiamen  
Tel: 86-592-2388138  
Norway - Trondheim  
Tel: 47-7288-4388  
China - Zhuhai  
Tel: 86-756-3210040  
Poland - Warsaw  
Tel: 48-22-3325737  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
Tel: 951-273-7800  
Romania - Bucharest  
Tel: 40-21-407-87-50  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
Raleigh, NC  
Tel: 919-844-7510  
Sweden - Gothenberg  
Tel: 46-31-704-60-40  
New York, NY  
Tel: 631-435-6000  
Sweden - Stockholm  
Tel: 46-8-5090-4654  
San Jose, CA  
Tel: 408-735-9110  
Tel: 408-436-4270  
UK - Wokingham  
Tel: 44-118-921-5800  
Fax: 44-118-921-5820  
Canada - Toronto  
Tel: 905-695-1980  
Fax: 905-695-2078  
DS00002813A-page 44  
2018 Microchip Technology Inc.  
08/15/18  

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