KSZ8841-32MVLI-TR [MICROCHIP]
Single-Port Ethernet MAC Controller with Non-PCI Interface;
| 型号： | KSZ8841-32MVLI-TR |
| 厂家： | 
MICROCHIP |
| 描述： | Single-Port Ethernet MAC Controller with Non-PCI Interface 以太网：16GBASE-T PC 电信 电信集成电路 |
| 文件： | 总98页 (文件大小：2167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ8841-16M/-32M
Single-Port Ethernet MAC Controller
with Non-PCI Interface
Features
Additional Features
• Single Chip Ethernet Controller with IEEE 802.3u
Support
In addition to offering all of the features of a Layer 2
controller, the KSZ8841-16M/-32M offers:
• Supports 10BASE-T/100BASE-TX
• Dynamic Buffer Memory Scheme
• Supports IEEE 802.3x Full-Duplex Flow Control
and Half-Duplex Backpressure Collision Flow
Control
- Essential for Applications such as Video over
IP where Image Jitter is Unacceptable
• Flexible 8-bit, 16-bit, and 32-bit Generic Host Pro-
cessor Interfaces
• Microchip LinkMD® Cable Diagnostic Capabilities
to Determine Cable Length, Diagnose Faulty
Cables, and Determine Distance to Fault
• Supports Burst Data Transfers
• 8 KB Internal Memory for RX/TX FIFO Buffers
• Early TX/RX Functions to Minimize Latency
Through the Device
• Optional to Use External Serial EEPROM Config-
uration for Both KSZ8841-16MQL and KSZ8841-
32MQL
• Wake-on-LAN Functionality
- Incorporates Magic Packet™, Network Link
State, and Wake-Up Frame Technology
• Single 25 MHz Reference Clock for Both PHY
and MAC
• HP Auto MDI-X™ Crossover with Disable/Enable
Option
Network Features
• Ability to Transmit and Receive Frames up to
1916 bytes
• Fully Integrated to Comply with IEEE 802.3u
Standards
Applications
• 10BASE-T and 100BASE-TX Physical Layer Sup-
port
• Video Distribution Systems
• High-End Cable, Satellite, and IP Set-Top Boxes
• Video over IP
• Auto-Negotiation: 10/100 Mbps Full- and Half-
Duplex
• Adaptive Equalizer
• Voice over IP (VoIP) and Analog Telephone
Adapters (ATA)
• Baseline Wander Correction
• Industrial Control in Latency-Critical Applications
• Motion Control
Power Modes, Power Supplies, and Packaging
• Single Power Supply (3.3V) with 5V Tolerant I/O
Buffers
• Industrial Control Sensor Devices (Temperature,
Pressure, Levels, and Valves)
• Enhanced Power Management Feature with
Power-Down Feature to Ensure Low Power Dissi-
pation During Device Idle Periods
• Security and Surveillance Cameras
Markets
• Comprehensive LED Indicator Support for Link,
Activity, Full-/Half-Duplex, and 10/100 Speed (4
LEDs)
• Fast Ethernet
• Embedded Ethernet
• Industrial Ethernet
- User Programmable
• Low-Power CMOS Design
• Commercial Temperature Range: 0°C to +70°C
• Industrial Temperature Range: –40°C to +85°C
• Available in 128-Pin PQFP and 100-Ball LFBGA
(128-Pin LQFP Optional)
2019 Microchip Technology Inc.
DS00003147A-page 1
KSZ8841-16M/-32M
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00003147A-page 2
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration ................................................................................................................................................... 5
3.0 Functional Description .................................................................................................................................................................. 22
4.0 Register Descriptions .................................................................................................................................................................... 37
5.0 Operational Characteristics ........................................................................................................................................................... 75
6.0 Electrical Characteristics ............................................................................................................................................................... 76
7.0 Timing Specifications .................................................................................................................................................................... 77
8.0 Selection of Isolation Transformers ............................................................................................................................................... 88
9.0 Package Outline ............................................................................................................................................................................ 89
Appendix A: Data Sheet Revision History ........................................................................................................................................... 93
The Microchip Web Site ...................................................................................................................................................................... 94
Customer Change Notification Service ............................................................................................................................................... 94
Customer Support ............................................................................................................................................................................... 94
Product Identification System ............................................................................................................................................................. 95
2019 Microchip Technology Inc.
DS00003147A-page 3
KSZ8841-16M/-32M
1.0
1.1
INTRODUCTION
General Description
The KSZ8841-series single-port chip includes PCI and non-PCI CPU interfaces, and are available in 8-bit, 16-bit, and
32-bit bus designs. This data sheet describes the KSZ8841M-series of non-PCI CPU interface chips. For information
on the KSZ8841 PCI CPU interface chips, refer to the KSZ8841P data sheet.
The KSZ8841M is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing
Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, an 8-bit, 16-bit, and 32-bit generic host pro-
cessor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable
8 KB for both TX and RX directions in host buffer interface.
The KSZ8841M is designed to be fully compliant with the appropriate IEEE 802.3 standards. An industrial temperature
grade version of the KSZ8841M, the KSZ8841MVLI, also can be ordered.
Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more
efficient and allowing for lower power consumption. The KSZ8841M is designed using a low-power CMOS process that
features a single 3.3V power supply with 5V tolerant I/O. It has an extensive feature set that offers management infor-
mation base (MIB) counters and CPU control/data interfaces.
The KSZ8841M includes a unique cable diagnostics feature called LinkMD®. This feature determines the length of the
cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the
cable length and cable conditions to be conveniently displayed. In addition, the KSZ8841M supports Hewlett Packard
(HP) Auto-MDIX, thereby eliminating the need to differentiate between straight or crossover cables in applications.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
1 0 /1 0 0
B a s e -T /T X
P H Y
P 1 H P A u to
M D I/M D I-X
H o s t M A C
R X Q
4 K B
Q M U
D M A
N o n -P C I
C P U
B u s
In te rfa c e
U n it
T X Q
4 K B
C h a n n e l
E m b e d d e d P ro c e s s o r
In te rfa c e
C o n tro l
R e g is te rs
8 ,1 6 , o r 3 2 -b it G e n e ric
H o s t In te rfa c e
M IB
C o u n te rs
L E D
D riv e r
P 1 L E D [3 :0 ]
E E P R O M I/F
E E P R O M
In te rfa c e
DS00003147A-page 4
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
PIN CONFIGURATION FOR KSZ8841-16 CHIP (8-/16-BIT)
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
AG ND
VDDAP
AG ND
ISET
NC
NC
NC
NC
NC
DG ND
VDDIO
NC
AG ND
VDDA
NC
NC
D15
D14
D13
D12
D11
D10
D9
NC
AG ND
NC
NC
VDDARX
VDDATX
TXM 1
TXP1
AG ND
RXM 1
RXP1
NC
KSZ8841-16MQL
(Top View)
D8
D7
D6
D5
D4
D3
DGND
DGND
VDDIO
D2
VDDA
AG ND
NC
D 1
D0
NC
AG ND
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
97
98
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AGND
VDDAP
AGND
ISET
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
NC
AGND
VDDA
NC
NC
DGND
VDDIO
NC
AGND
NC
NC
D15
D14
D13
D12
D11
D10
D9
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
NC
KSZ8841-16MVL
(Top View)
D8
D7
VDDA
AGND
NC
D6
D5
D4
NC
D3
AGND
VDDA
AGND
PWRDN
ADSN
DGND
WRN
DGND
DGND
VDDIO
38
37
36
35
D2
D1
D0
34
33
2019 Microchip Technology Inc.
DS00003147A-page 5
KSZ8841-16M/-32M
TABLE 2-1:
SIGNALS
Pin Name
Pin
Number
Type
Description
Test Enable
1
2
TEST_EN
SCAN_EN
I
I
For normal operation, pull-down this pin to ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this pin to ground.
Port 1 LED Indicators, defined as follows
Chip Global Control Register: CGCR bit
[15,9]
[0, 0] Default
—
[0, 1]
P1LED3
P1LED2
P1LED1
P1LED0
—
Link/Activity
Full-Duplex/Col
Speed
100Link/Activity
10Link/Activity
Full-Duplex
3
4
5
P1LED2
P1LED1
P1LED0
OPU
Reg. CGCR bit [15,9]
[1, 0]
[1, 1]
—
P1LED3
P1LED2
P1LED1
P1LED0
Note:
Activity
Link
—
Full-Duplex/Col
Speed
—
—
Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/
Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half-
duplex); Speed = On (100BASE-T); Off (10BASE-T)
Note:
P1LED3 is pin 27.
6
7
8
9
NC
NC
OPU
OPU
OPU
GND
No connect.
No connect.
No connect.
Digital ground.
NC
DGND
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
10
VDDIO
P
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous
read cycles. If the host doesn’t connect to this pin, assert this pin.
For burst mode (32-bit interface only): Host drives this pin low to signal
waiting states.
11
RDYRTNN
IPD
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is
12
BCLK
IPD
50 MHz.
This pin should be tied Low or unconnected if it is in asynchronous
mode.
13
14
NC
IPU
No connect.
Power Management Event Not
When asserted (Low), this signal indicates that a power management
event has occurred in the system when a wake-up signal is detected by
KSZ8841M.
PMEN
OPU
DS00003147A-page 6
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin Name
Type
Description
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and
VLBus-like extend accesses.
15
SRDYN
OPU
For VLBus-like mode, the falling edge of this signal indicates ready. This
signal is synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8841M drives this pin low
to signal wait states.
Interrupt
16
17
INTRN
LDEVN
OPD
OPD
Active Low signal to host CPU to indicate an interrupt status bit is set,
this pin need an external 4.7 kΩ pull-up resistor.
Local Device Not
Active Low output signal, asserted when AEN is Low and A15-A4
decode to the KSZ8841M address programmed into the high byte of the
base address register. LDEVN is a combinational decode of the Address
and AEN signal.
Read Strobe Not
Asynchronous read strobe, active-low.
18
19
RDN
IPD
EEPROM Chip Select
This signal is used to select an external EEPROM device.
EECS
OPU
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus
access cycles. It is asynchronous to the host CPU or bus clock. this pin
need an external 4.7 kΩ pull-up resistor.
20
21
ARDY
OPD
IPD
Cycle Not
For VLBus-like mode cycle signal; this pin follows the addressing cycle
to signal the command cycle.
CYCLEN
For burst mode (32-bit interface only), this pin stays High for read cycles
and Low for write cycles.
22
23
NC
OPD
GND
No connect.
DGND
Digital IO ground.
1.2V digital core voltage output (internal 1.2V LDO power supply output),
this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. It
is recommended this pin should be connected to 3.3V power rail by a
100Ω resistor for the internal LDO application
24
VDDCO
P
Note: Internally generated power voltage. Do not connect an external
power supply to this pin. This pin is used for connecting external filter
(Ferrite bead and capacitors).
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous
mode or EISA-like burst mode.
25
26
VLBUSN
EEEN
IPD
IPD
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
Port 1 LED indicator
See the description in pins 3, 4, and 5.
27
28
P1LED3
EEDO
OPD
OPD
EEPROM Data Out
This pin is connected to DI input of the serial EEPROM.
EEPROM Serial Clock
A 4 μs (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns
(OBCR[1:0]=00 on-chip bus speed @ 125 MHz) serial output clock cycle
to load configuration data from the serial EEPROM.
29
EESK
OPD
2019 Microchip Technology Inc.
DS00003147A-page 7
KSZ8841-16M/-32M
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin Name
Type
Description
EEPROM Data In
This pin is connected to DO output of the serial EEPROM when EEEN is
pull-up.
30
EEDI
IPD
This pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode
or don’t care for 32-bit bus mode when EEEN is pull-down (without
EEPROM).
Synchronous Write/Read
31
32
SWR
AEN
IPD
IPU
Write/Read signal for synchronous bus accesses. Write cycles when
high and Read cycles when low.
Address Enable
Address qualifier for the address decoding, active-low.
Write Strobe Not
Asynchronous write strobe, active-low.
33
34
WRN
IPD
DGND
GND
Digital IO ground
Address Strobe Not
35
ADSN
IPD
For systems that require address latching, the rising edge of ADSN indi-
cates the latching moment of A15-A1 and AEN.
Full-chip power-down. Active-Low
(Low = Power down; High or floating = Normal operation).
36
37
38
PWRDN
AGND
VDDA
IPU
GND
P
Analog ground
1.2V analog VDD input power supply from VDDCO (pin 24) through
external Ferrite bead and capacitor.
39
40
41
42
AGND
NC
GND
—
Analog ground
No Connect
NC
—
No Connect
AGND
GND
Analog ground
1.2V analog VDD input power supply from VDDCO (pin 24) through
external Ferrite bead and capacitor.
43
VDDA
P
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
RXP1
RXM1
AGND
TXP1
TXM1
VDDATX
VDDARX
NC
—
I/O
I/O
GND
I/O
I/O
P
No Connect
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
Analog ground
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
3.3V analog VDD input power supply with well decoupling capacitors.
P
3.3V analog VDD input power supply with well decoupling capacitors.
—
No Connect
No Connect
Analog ground
No Connect
No Connect
NC
—
AGND
NC
GND
—
NC
—
1.2 analog VDD input power supply from VDDCO (pin 24) through exter-
nal Ferrite bead and capacitor.
57
VDDA
P
58
59
60
AGND
NC
GND
IPU
Analog ground
No connect
No connect
NC
IPU
DS00003147A-page 8
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin Name
Type
Description
Set physical transmits output current.
Pull-down this pin with a 3.01 kΩ 1% resistor to ground.
61
62
63
ISET
AGND
VDDAP
O
GND
P
Analog ground
1.2V analog VDD for PLL input power supply from VDDCO (pin 24)
through external Ferrite bead and capacitor.
64
65
AGND
X1
GND
I
Analog ground
25 MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to
a 3.3V tolerant oscillator and X2 is a no connect.
Note: Clock requirement is ±50 ppm for either crystal or oscillator.
66
67
X2
O
Reset Not
RSTN
IPU
Hardware reset pin (active-low). This reset input is required minimum of
10 ms low after stable supply voltage 3.3V.
68
69
70
71
72
73
74
75
76
77
78
A15
A14
A13
A12
A11
A10
A9
I
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
I
I
I
I
I
I
A8
I
Address 8
A7
I
I
Address 7
A6
Address 6
DGND
GND
Digital IO ground
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
79
VDDIO
P
80
81
82
83
84
85
86
A5
A4
A3
A2
A1
NC
NC
I
I
I
I
I
I
I
Address 5
Address 4
Address 3
Address 2
Address 1
No Connect
No Connect
Byte Enable 1 Not, Active-low for Data byte 1 enable (don’t care in 8-bit
bus mode).
87
88
BE1N
BE0N
I
I
Byte Enable 0 Not, Active-low for Data byte 0 enable (there is an internal
inverter enabled and connected to the BE1N for 8-bit bus mode).
89
90
NC
I
No Connect
DGND
GND
Digital core ground
1.2V digital core V
external Ferrite bead and capacitor.
input power supply from VDDCO (pin 24) through
DD
91
92
VDDC
P
P
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
VDDIO
93
94
95
NC
NC
NC
I
I
I
No Connect
No Connect
No Connect
2019 Microchip Technology Inc.
DS00003147A-page 9
KSZ8841-16M/-32M
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin Name
Type
Description
96
97
NC
NC
I
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
No Connect
Digital IO ground
I
98
NC
I
99
NC
I
100
101
102
103
104
105
106
107
NC
I
NC
I
NC
I
NC
I
NC
I
NC
I
I
NC
DGND
GND
3.3V digital V
itors.
input power supply for IO with well decoupling capac-
DDIO
108
VDDIO
P
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
NC
D15
D14
D13
D12
D11
D10
D9
I
No Connect
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
GND
D8
Data 8
D7
Data 7
D6
Data 6
D5
Data 5
D4
Data 4
D3
Data 3
DGND
DGND
Digital IO ground
Digital core ground
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
125
VDDIO
P
126
127
D2
D1
D0
I/O
I/O
I/O
Data 2
Data 1
Data 0
128
Note 2-1
P = power supply; GND = ground; I = input; O = output
I/O = bi-directional
IPU/O = Input with internal pull-up during reset; output pin otherwise.
IPU = Input with internal pull-up.
IPD = Input with internal pull-down.
OPU = Output with internal pull-up.
OPD = Output with internal pull-down.
DS00003147A-page 10
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
FIGURE 2-2:
BALL CONFIGURATION FOR KSZ8841-16 CHIP (8/16-BIT)
TABLE 2-2:
BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT)
Ball
Number
Ball Name
Type
Description
Test Enable
E8
TEST_EN
SCAN_EN
I
I
For normal operation, pull-down this ball to ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this ball to ground.
D10
2019 Microchip Technology Inc.
DS00003147A-page 11
KSZ8841-16M/-32M
TABLE 2-2:
BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED)
Ball
Number
Ball Name
Type
Description
Port 1 LED Indicators, defined as follows
Switch Global Control Register 5:
SGCR bit [15,9]
[0, 0] Default
—
[0, 1]
P1LED3
P1LED2
P1LED1
P1LED0
—
Link/Activity
Full-Duplex/Col
Speed
100Link/Activity
10Link/Activity
Full-Duplex
A10
B10
C10
P1LED2
P1LED1
P1LED0
OPU
Reg. SGCR bit [15,9]
[1, 0]
[1, 1]
—
P1LED3
P1LED2
P1LED1
P1LED0
Note:
Activity
Link
—
Full-Duplex/Col
Speed
—
—
Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/
Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half-
duplex); Speed = On (100BASE-T); Off (10BASE-T)
Note:
P1LED3 is ball A4.
Ready Return Not:
D9
A8
RDYRTNN
BCLK
IPD
IPD
For VLBus-like mode: Asserted by the host to complete synchronous
read cycles. If the host doesn’t connect to this ball, assert this ball.
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is
50 MHz.
This ball should be tied Low or unconnected if it is in asynchronous
mode.
Power Management Event Not
When asserted (Low), this signal indicates that a power management
event has occurred in the system when a wake-up signal is detected by
KSZ8841M.
D8
PMEN
OPU
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and
VLBus-like extend accesses.
For VLBus-like mode, the falling edge of this signal indicates ready. This
signal is synchronous to the bus clock signal BCLK.
B8
C8
A7
SRDYN
INTRN
LDEVN
OPU
OPD
OPD
Interrupt
Active-low signal to host CPU to indicate an interrupt status bit is set,
this ball need an external 4.7 kΩ pull-up resistor.
Local Device Not
Active-low output signal, asserted when AEN is Low and A15-A4 decode
to the KSZ8841M address programmed into the high byte of the base
address register. LDEVN is a combinational decode of the Address and
AEN signal.
Read Strobe Not
Asynchronous read strobe, active-low.
B7
C7
RDN
IPD
EECS
OPU
EEPROM Chip Select
DS00003147A-page 12
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-2:
BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED)
Ball
Number
Ball Name
Type
Description
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus
access cycles. It is asynchronous to the host CPU or bus clock. This ball
needs an external 4.7 kΩ pull-up resistor.
A6
B6
ARDY
OPD
Cycle Not
For VLBus-like mode cycle signal; this ball follows the addressing cycle
to signal the command cycle.
CYCLEN
IPD
For burst mode (32-bit interface only), this ball stays High for read cycles
and Low for write cycles.
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 8-bit or 16-bit asynchronous
mode or EISA-like burst mode.
A5
B5
VLBUSN
EEEN
IPD
IPD
EEPROM Enable
EEPROM is enabled and connected when this ball is pull-up.
EEPROM is disabled when this ball is pull-down or no connect.
Port 1 LED indicator
See the description in balls A10, B10, and C10.
A4
B4
P1LED3
EEDO
OPD
OPD
EEPROM Data Out
This ball is connected to DI input of the serial EEPROM.
EEPROM Serial Clock
A 4 μs (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns
(OBCR[1:0]=00 on-chip bus speed @ 125 MHz) serial output clock cycle
to load configuration data from the serial EEPROM.
A3
EESK
OPD
EEPROM Data In
This ball is connected to DO output of the serial EEPROM when EEEN
is pull-up.
This ball can be pull-down for 8-bit bus mode, pull-up for 16-bit bus
mode or don’t care for 32-bit bus mode when EEEN is pull-down (with-
out EEPROM).
B3
C3
EEDI
SWR
IPD
IPD
Synchronous Write/Read
Write/Read signal for synchronous bus accesses. Write cycles when
high and Read cycles when low.
Address Enable
Address qualifier for the address decoding, active-low.
A2
B2
AEN
IPU
IPD
Write Strobe Not
Asynchronous write strobe, active-low.
WRN
Address Strobe Not
A1
B1
ADSN
IPD
IPU
For systems that require address latching, the rising edge of ADSN indi-
cates the latching moment of A15-A1 and AEN.
Full-chip power-down. Low = Power down; High or floating = Normal
operation.
PWRDN
C1
C2
D1
D2
RXP1
RXM1
TXP1
TXM1
I/O
I/O
I/O
I/O
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
Test input 2
For normal operation, left this ball open.
H2
G3
TEST2
ISET
IPU
O
Set physical transmits output current.
Pull-down this ball with a 3.01 kΩ 1% resistor to ground.
2019 Microchip Technology Inc.
DS00003147A-page 13
KSZ8841-16M/-32M
TABLE 2-2:
BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED)
Ball
Number
Ball Name
Type
Description
J1
X1
I
25 MHz crystal or oscillator clock connection.
Balls (X1, X2) connect to a crystal. If an oscillator is used, X1 connects
to a 3.3V tolerant oscillator and X2 is a no connect.
Note: Clock requirement is 50 ppm for either crystal or oscillator.
K1
X2
O
Hardware reset ball (active Low). This reset input is required minimum of
10 ms low after stable supply voltage 3.3V.
J2
RSTN
IPU
K2
K3
J3
A15
A14
A13
A12
A11
A10
A9
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
Address 8
Address 7
Address 6
Address 5
Address 4
Address 3
Address 2
Address 1
H3
K4
J4
H4
K5
J5
A8
A7
H5
K6
J6
A6
A5
A4
H6
K7
J7
A3
A2
A1
Byte Enable 1 Not, Active-low for Data byte 1 enable (don’t care in 8-bit
bus mode).
H7
K8
BE1N
BE0N
I
I
Byte Enable 0 Not, Active-low for Data byte 0 enable (there is an internal
inverter enabled and connected to the BE1N for 8-bit bus mode).
K9
K10
J9
D15
D14
D13
D12
D11
D10
D9
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
Data 7
Data 6
Data 5
Data 4
Data 3
Data 2
Data 1
Data 0
J10
J8
H9
H10
H8
D8
G9
G10
G8
F9
D7
D6
D5
D4
F10
F8
D3
D2
E9
D1
E10
D0
DS00003147A-page 14
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-2:
BALL DESCRIPTION FOR KSZ8841-16 CHIP (8/16-BIT) (CONTINUED)
Ball
Number
Ball Name
Type
Description
1.2V digital core voltage output (internal 1.2V LDO power supply output),
this 1.2V output ball provides power to all VDDC/VDDA balls. It is rec-
ommended this ball should be connected to 3.3V power rail by a 100Ω
resistor for the internal LDO application.
C4
VDDCO
P
Note: Internally generated power voltage. Do not connect an external
power supply to this ball. This ball is used for connecting external filter
(Ferrite bead and capacitors).
1.2V digital core V
external Ferrite bead and capacitor.
input power supply from VDDCO (ball C4) through
DD
C5
VDDC
VDDA
P
P
1.2V analog VDD input power supply from VDDCO (ball C4) through
external Ferrite bead and capacitor.
D3, E3, F3
E1
E2
VDDATX
VDDARX
P
P
3.3V analog VDD input power supply with well decoupling capacitors.
3.3V analog VDD input power supply with well decoupling capacitors.
D7, E7, F7,
G4, G5,
G6, G7
3.3V digital V
itors.
input power supply for IO with well decoupling capac-
DDIO
VDDIO
GND
NC
P
D4, D5, D6,
E4, E5, E6,
F4, F5, F6
GND
I/O
All digital and analog grounds
No Connect
H1, A9, B9,
C9, C6, F2,
F1, G2, G1
2019 Microchip Technology Inc.
DS00003147A-page 15
KSZ8841-16M/-32M
FIGURE 2-3:
PIN CONFIGURATION FOR KSZ8841-32 CHIP (32-BIT)
AGND
VDDAP
AGND
ISET
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
D20
D19
D18
D17
DGND
VDDIO
D16
NC
AGND
VDDA
NC
D15
D14
NC
D13
AGND
NC
D12
D11
NC
KSZ8841-32MQL
(Top View)
D10
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
NC
D9
D8
D7
D6
D5
D4
D3
DGND
DGND
VDDIO
D2
D1
D0
VDDA
AGND
NC
NC
AGND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
AGND
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
97
98
VDDAP
AGND
ISET
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
NC
NC
AGND
VDDA
NC
NC
AGND
NC
DGND
VDDIO
D16
D15
D14
D13
D12
D11
D10
D9
NC
VDDARX
VDDATX
TXM1
TXP1
AGND
RXM1
RXP1
NC
KSZ8841-32MVL
(Top View)
D8
D7
VDDA
AGND
NC
D6
D5
D4
NC
D3
AGND
VDDA
AGND
PWRDN
ADSN
DGND
WRN
DGND
DGND
VDDIO
D2
38
37
36
35
D1
34
D0
33
DS00003147A-page 16
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-3:
PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT)
Pin
Number
Pin Name
Type
Description
Test Enable
1
2
TEST_EN
SCAN_EN
I
I
For normal operation, pull-down this pin to ground.
Scan Test Scan Mux Enable
For normal operation, pull-down this pin to ground.
Port 1 LED Indicators, defined as follows
Chip Global Control Register:
CGCR bit [15,9]
[0, 0] Default
—
[0, 1]
P1LED3
P1LED2
P1LED1
P1LED0
—
Link/Activity
Full-Duplex/Col
Speed
100Link/Activity
10Link/Activity
Full-Duplex
3
4
5
P1LED2
P1LED1
P1LED0
OPU
Reg. CGCR bit [15,9]
[1, 0]
[1, 1]
—
P1LED3
P1LED2
P1LED1
P1LED0
Note:
Activity
Link
—
Full-Duplex/Col
Speed
—
—
Link = On; Activity = Blink; Link/Act = On/Blink; Full-Duplex/
Col = On/Blink; Full-Duplex = On (Full-duplex); Off (Half-
duplex); Speed = On (100BASE-T); Off (10BASE-T)
Note:
P1LED3 is pin 27.
6
7
8
9
NC
NC
OPU
OPU
OPU
GND
No connect.
No connect.
No connect.
Digital ground.
NC
DGND
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
10
VDDIO
P
Ready Return Not:
For VLBus-like mode: Asserted by the host to complete synchronous
read cycles. If the host doesn’t connect to this pin, assert this pin.
For burst mode (32-bit interface only): Host drives this pin low to signal
waiting states.
11
RDYRTNN
IPD
Bus Interface Clock
Local bus clock for synchronous bus systems. Maximum frequency is
12
BCLK
IPD
50 MHz.
This pin should be tied Low or unconnected if it is in asynchronous
mode.
DATA Chip Select Not (For KSZ8841-32 Mode only)
Chip select signal for QMU data register (QDRH, QDRL), active Low.
13
14
DATACSN
PMEN
IPU
When DATACSN is Low, the data path can be accessed regardless of
the value of AEN, A15-A1, and the content of the BANK select register.
Power Management Event Not
When asserted (Low), this signal indicates that a power management
event has occurred in the system when a wake-up signal is detected by
KSZ8841M.
OPU
2019 Microchip Technology Inc.
DS00003147A-page 17
KSZ8841-16M/-32M
TABLE 2-3:
PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED)
Pin
Number
Pin Name
Type
Description
Synchronous Ready Not
Ready signal to interface with synchronous bus for both EISA-like and
VLBus-like extend accesses.
15
SRDYN
OPU
For VLBus-like mode, the falling edge of this signal indicates ready. This
signal is synchronous to the bus clock signal BCLK.
For burst mode (32-bit interface only), the KSZ8841M drives this pin low
to signal wait states.
Interrupt
16
17
INTRN
LDEVN
OPD
OPD
Active-low signal to host CPU to indicate an interrupt status bit is set,
this pin need an external 4.7 kΩ pull-up resistor
Local Device Not
Active-low output signal, asserted when AEN is Low and A15-A4 decode
to the KSZ8841M address programmed into the high byte of the base
address register. LDEVN is a combinational decode of the Address and
AEN signal.
Read Strobe Not
Asynchronous read strobe, active-low.
18
19
RDN
IPD
EEPROM Chip Select
This signal is used to select an external EEPROM device.
EECS
OPU
Asynchronous Ready
ARDY may be used when interfacing asynchronous buses to extend bus
access cycles. It is asynchronous to the host CPU or bus clock. this pin
need an external 4.7 kΩ pull-up resistor.
20
21
ARDY
OPD
IPD
Cycle Not
For VLBus-like mode cycle signal; this pin follows the addressing cycle
to signal the command cycle.
CYCLEN
For burst mode (32-bit interface only), this pin stays High for read cycles
and Low for write cycles.
22
23
NC
OPD
GND
No Connect
DGND
Digital IO ground
1.2V digital core voltage output (internal 1.2V LDO power supply output),
this 1.2V output pin provides power to VDDC, VDDA and VDDAP pins. It
is recommended this ball should be connected to 3.3V power rail by a
100Ω resistor for the internal LDO application.
24
VDDCO
P
Note: Internally generated power voltage. Do not connect an external
power supply to this pin. This pin is used for connecting external filter
(Ferrite bead and capacitors).
VLBus-like Mode
Pull-down or float: Bus interface is configured for synchronous mode.
Pull-up: Bus interface is configured for 32-bit asynchronous mode or
EISA-like burst mode.
25
26
VLBUSN
EEEN
IPD
IPD
EEPROM Enable
EEPROM is enabled and connected when this pin is pull-up.
EEPROM is disabled when this pin is pull-down or no connect.
Port 1 LED indicator
See the description in pins 3, 4, and 5.
27
28
P1LED3
EEDO
OPD
OPD
EEPROM Data Out
This pin is connected to DI input of the serial EEPROM.
EEPROM Serial Clock
A 4 μs (OBCR[1:0]=11 on-chip bus speed @ 25 MHz) or 800 ns
(OBCR[1:0]=00 on-chip bus speed @ 125 MHz) serial output clock cycle
to load configuration data from the serial EEPROM.
29
EESK
OPD
DS00003147A-page 18
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-3:
PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED)
Pin
Number
Pin Name
Type
Description
EEPROM Data In
This pin is connected to DO output of the serial EEPROM when EEEN is
pull-up.
30
EEDI
IPD
This pin can be pull-down for 8-bit bus mode, pull-up for 16-bit bus mode
or don’t care for 32-bit bus mode when EEEN is pull-down (without
EEPROM).
Synchronous Write/Read
31
32
SWR
AEN
IPD
IPU
Write/Read signal for synchronous bus accesses. Write cycles when
high and Read cycles when low.
Address Enable
Address qualifier for the address decoding, active-low.
Write Strobe Not
Asynchronous write strobe, active-low.
33
34
WRN
IPD
DGND
GND
Digital IO ground
Address Strobe Not
35
ADSN
IPD
For systems that require address latching, the rising edge of ADSN indi-
cates the latching moment of A15-A1 and AEN.
Full-chip power-down. Active-low
(Low = Power down; High or floating = Normal operation).
36
37
38
PWRDN
AGND
VDDA
IPU
GND
P
Analog ground
1.2V analog VDD input power supply from VDDCO (pin 24) through
external Ferrite bead and capacitor.
39
40
41
42
AGND
NC
GND
—
Analog ground
No Connect
NC
—
No Connect
AGND
GND
Analog ground
1.2V analog VDD input power supply from VDDCO (pin 24) through
external Ferrite bead and capacitor.
43
VDDA
P
44
45
46
47
48
49
50
51
52
53
54
55
56
NC
RXP1
RXM1
AGND
TXP1
TXM1
VDDATX
VDDARX
NC
—
I/O
I/O
GND
I/O
I/O
P
No Connect
Port 1 physical receive (MDI) or transmit (MDIX) signal (+ differential)
Port 1 physical receive (MDI) or transmit (MDIX) signal (– differential)
Analog ground
Port 1 physical transmit (MDI) or receive (MDIX) signal (+ differential)
Port 1 physical transmit (MDI) or receive (MDIX) signal (– differential)
3.3V analog VDD input power supply with well decoupling capacitors.
P
3.3V analog VDD input power supply with well decoupling capacitors.
—
No Connect
No Connect
Analog ground
No Connect
No Connect
NC
—
AGND
NC
GND
—
NC
—
1.2 analog VDD input power supply from VDDCO (pin 24) through exter-
nal Ferrite bead and capacitor.
57
VDDA
P
58
59
60
AGND
NC
GND
IPU
Analog ground
No connect
No connect
NC
IPU
2019 Microchip Technology Inc.
DS00003147A-page 19
KSZ8841-16M/-32M
TABLE 2-3:
PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED)
Pin
Number
Pin Name
Type
Description
Set physical transmits output current.
Pull-down this pin with a 3.01 kΩ 1% resistor to ground.
Analog ground
61
62
63
ISET
AGND
VDDAP
O
GND
P
1.2V analog VDD for PLL input power supply from VDDCO (pin 24)
through external Ferrite bead and capacitor.
64
65
AGND
X1
GND
I
Analog ground
25 MHz crystal or oscillator clock connection.
Pins (X1, X2) connect to a crystal. If an oscillator is used, X1 connects to
a 3.3V tolerant oscillator and X2 is a no connect.
Note: Clock requirement is ±50 ppm for either crystal or oscillator.
66
67
X2
O
Reset Not
RSTN
IPU
Hardware reset pin (active-low). This reset input is required minimum of
10 ms low after stable supply voltage 3.3V.
68
69
70
71
72
73
74
75
76
77
78
A15
A14
A13
A12
A11
A10
A9
I
Address 15
Address 14
Address 13
Address 12
Address 11
Address 10
Address 9
I
I
I
I
I
I
A8
I
Address 8
A7
I
I
Address 7
A6
Address 6
DGND
GND
Digital IO ground
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
79
VDDIO
P
80
81
82
83
84
85
86
87
88
89
90
A5
A4
I
Address 5
I
Address 4
A3
I
Address 3
A2
I
Address 2
A1
I
Address 1
BE3N
BE2N
BE1N
BE0N
D31
I
Byte Enable 3 Not, Active-low for Data byte 3 enable
Byte Enable 2 Not, Active-low for Data byte 2 enable
Byte Enable 1 Not, Active-low for Data byte 1 enable
Byte Enable 0 Not, Active-low for Data byte 0 enable
Data 31
I
I
I
I/O
GND
DGND
Digital core ground
1.2V digital core V
external Ferrite bead and capacitor.
input power supply from VDDCO (pin 24) through
DD
91
92
VDDC
P
P
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
VDDIO
93
94
95
96
97
D30
D29
D28
D27
D26
I/O
I/O
I/O
I/O
I/O
Data 30
Data 29
Data 28
Data 27
Data 26
DS00003147A-page 20
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
TABLE 2-3:
PIN DESCRIPTION FOR KSZ8841-32 CHIP (32-BIT) (CONTINUED)
Pin
Number
Pin Name
Type
Description
98
D25
D24
D23
D22
D21
D20
D19
D18
D17
DGND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
Data 25
99
Data 24
100
101
102
103
104
105
106
107
Data 23
Data 22
Data 21
Data 20
Data 19
Data 18
Data 17
Digital IO ground
3.3V digital V
itors.
input power supply for IO with well decoupling capac-
DDIO
108
VDDIO
P
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
D16
D15
D14
D13
D12
D11
D10
D9
I/O
I/O
Data 16
Data 15
Data 14
Data 13
Data 12
Data 11
Data 10
Data 9
Data 8
Data 7
Data 6
Data 5
Data 4
Data 3
I/O
I/O
I/O
I/O
I/O
I/O
D8
I/O
D7
I/O
D6
I/O
D5
I/O
D4
I/O
D3
I/O
DGND
DGND
GND
GND
Digital IO ground
Digital core ground
3.3V digital VDDIO input power supply for IO with well decoupling capaci-
tors.
125
VDDIO
P
126
127
D2
D1
D0
I/O
I/O
I/O
Data 2
Data 1
Data 0
128
Legend:
P = Power supply, GND = Ground
I/O = Bi-directional, I = Input, O = Output.
IPD = Input with internal pull-down.
IPU = Input with internal pull-up.
OPD = Output with internal pull-down.
OPU = Output with internal pull-up.
2019 Microchip Technology Inc.
DS00003147A-page 21
KSZ8841-16M/-32M
3.0
FUNCTIONAL DESCRIPTION
The KSZ8841M is a single-chip Fast Ethernet MAC controller consisting of a 10/100 physical layer transceiver (PHY),
a MAC, and a Bus Interface Unit (BIU) that controls the KSZ8841M via an 8-bit, 16-bit, or 32-bit host bus interface.
The KSZ8841M is fully compliant to IEEE802.3u standards.
3.1
Power Management
3.1.1
POWER DOWN
The KSZ8841M features a port power-down mode. To save power, the user can power-down the port that is not in use
by setting bit 11 in either P1CR4 or P1MBCR register for this port. To bring the port back up, reset bit 11 in these regis-
ters.
In addition, there is a full chip power-down mode PWRDN (pin 36). When this pin is pulled-down, the entire chip powers
down. Transitioning this pin from pull-down to pull-up results in a power up and chip reset.
3.1.2
WAKE-ON-LAN
Wake-up frame events are used to wake the system whenever meaningful data is presented to the system over the
network. Examples of meaningful data include the reception of a Magic Packet, a management request from a remote
administrator, or simply network traffic directly targeted to the local system. In all of these instances, the network device
is pre-programmed by the policy owner or other software with information on how to identify wake frames from other
network traffic.
A wake-up event is a request for hardware and/or software external to the network device to put the system into a pow-
ered state (working).
A wake-up signal is caused by:
• Detection of a change in the network link state
• Receipt of a network wake-up frame
• Receipt of a Magic Packet
There are also other types of wake-up events that are not listed here as manufacturers may choose to implement these
in their own way.
3.1.3
LINK CHANGE
Link status wake events are useful to indicate a change in the network’s availability, especially when this change may
impact the level at which the system should re-enter the sleeping state. For example, a change from link off to link on
may trigger the system to re-enter sleep at a higher level (D2 versus D3) so that wake frames can be detected. Con-
versely, a transition from link on to link off may trigger the system to re-enter sleep at a deeper level (D3 versus D2)
since the network is not currently available.
References to D0, D1, D2, and D3 are power management states defined in a similar fashion to the way they are defined
for PCI. For more information, refer to the PCI specification.
3.1.4
WAKE-UP PACKET
Wake-up packets are certain types of packets with specific CRC values that a system recognizes as a ‘wake up’ frame.
The KSZ8841M supports up to four users defined wake-up frames as below:
1. Wake-up frame 0 is defined in registers 0x00 - 0x0A of Bank 4 and is enabled by bit 0 in wakeup frame control
register.
2. Wake-up frame 1 is defined in registers 0x00 - 0x0A of Bank 5 and is enabled by bit 1 in wakeup frame control
register.
3. Wake-up frame 2 is defined in registers 0x00 - 0x0A of Bank 6 and is enabled by bit 2 in wakeup frame control
register.
4. Wake-up frame 4 is defined in registers 0x00 - 0x0A of Bank 7 and is enabled by bit 3 in wakeup frame control
register.
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3.1.5
MAGIC PACKET
Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a LAN. This is accomplished by
sending a specific packet of information, called a Magic Packet frame, to a node on the network. When a PC capable
of receiving the specific frame goes to sleep, it enables the Magic Packet RX mode in the LAN controller, and when the
LAN controller receives a Magic Packet frame, it will alert the system to wake up.
Magic Packet is a standard feature integrated into the KSZ8841M. The controller implements multiple advanced power-
down modes including Magic Packet to conserve power and operate more efficiently.
Once the KSZ8841M has been put into Magic Packet Enable mode (WFCR[7]=1), it scans all incoming frames
addressed to the node for a specific data sequence, which indicates to the controller this is a Magic Packet (MP) frame.
A Magic Packet frame must also meet the basic requirements for the LAN technology chosen, such as Source Address
(SA), Destination Address (DA), which may be the receiving station’s IEEE address or a multicast or broadcast address
and CRC.
The specific sequence consists of 16 duplications of the IEEE address of this node, with no breaks or interruptions. This
sequence can be located anywhere within the packet, but must be preceded by a synchronization stream. The synchro-
nization stream allows the scanning state machine to be much simpler. The synchronization stream is defined as 6 bytes
of FFh. The device will also accept a broadcast frame, as long as the 16 duplications of the IEEE address match the
address of the machine to be awakened.
Example:
If the IEEE address for a particular node on a network is 11h 22h, 33h, 44h, 55h, 66h, the LAN controller would be scan-
ning for the data sequence (assuming an Ethernet frame):
DESTINATION SOURCE – MISC - FF FF FF FF FF FF - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 -
11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66
-11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66 - 11 22 33 44 55 66
- 11 22 33 44 55 66 - MISC - CRC.
There are no further restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet or
an IPX packet. The frame may be bridged or routed across the network without affecting its ability to wake-up a node
at the frame’s destination.
If the LAN controller scans a frame and does not find the specific sequence shown above, it discards the frame and
takes no further action. If the KSZ8841M controller detects the data sequence, however, it then alerts the PC’s power
management circuitry (assert the PMEN pin) to wake up the system.
3.2
Physical Layer Transceiver
3.2.1
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI
conversion, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. An external 1%
3.01 kΩ resistor for the 1:1 transformer ratio sets the output current.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output driver is also incorporated into the 100BASE-
TX driver.
3.2.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer has to adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on com-
parisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
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Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to an MII format and provided as the input data to the MAC.
3.2.3
PLL CLOCK SYNTHESIZER (RECOVERY)
The internal PLL clock synthesizer generates 125 MHz, 62.5 MHz, 41.66 MHz, and 25 MHz clocks by setting the on-
chip bus speed control register for KSZ8841M system timing. These internal clocks are generated from an external
25 MHz crystal or oscillator.
3.2.4
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander.
Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (LFSR). The scrambler
generates a 2047-bit non-repetitive sequence. Then the receiver de-scrambles the incoming data stream using the
same sequence as at the transmitter.
3.2.5
10BASE-T TRANSMIT
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.4V amplitude. The harmonic contents
are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
3.2.6
10BASE-T RECEIVE
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function.
The Manchester-encoded data stream is separated into clock signal and NRZ data. A squelch circuit rejects signals with
levels less than 400 mV or with short pulse widths to prevent noise at the RXP-or-RXM input from falsely triggering the
decoder. When the input exceeds the squelch limit, the PLL locks onto the incoming signal and the KSZ8841M decodes
a data frame.
The receiver clock is maintained active during idle periods in between data reception.
3.2.7
MDI/MDI-X AUTO CROSSOVER
To eliminate the need for crossover cables between similar devices, the KSZ8841M supports HP-Auto MDI/MDI-X and
IEEE 802.3u standard MDI/MDI-X auto crossover. HP-Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns the transmit and receive pairs
for the KSZ8841M device. This feature is extremely useful when end users are unaware of cable types in addition to
saving on an additional uplink configuration connection. The auto-crossover feature can be disabled through the port
control registers.
The IEEE 802.3u standard MDI and MDI-X definitions are illustrated in Table 3-1.
TABLE 3-1:
MDI/MDI-X PIN DEFINITIONS
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
2
3
6
TD+
TD–
RD+
RD–
1
2
3
6
RD+
RD–
TD+
TD–
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3.2.7.1
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-1 depicts
a typical straight cable connection between a NIC card (MDI) and a switch or hub (MDI-X).
FIGURE 3-1:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
Transmit Pair
2
Receive Pair
2
Straight
Cable
3
3
4
4
Receive Pair
5
Transmit Pair
5
6
7
8
6
7
8
Modular Connector
(RJ-45)
Modular Connector
(RJ-45)
NIC
HUB
(Repeater or Switch)
3.2.7.2
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-2 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-2:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
Crossover
Cable
Receive Pair
2
Receive Pair
2
3
3
4
4
Transmit Pair
5
Transmit Pair
5
6
7
8
6
7
8
Modular Connector (RJ-45)
HUB
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
(Repeater or Switch)
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3.2.8
AUTO-NEGOTIATION
The KSZ8841M conforms to the auto negotiation protocol as described by the 802.3 committee to allow the port to oper-
ate at either 10BASE-T or 100BASE-TX.
Auto negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In
auto negotiation, the link partners advertise capabilities across the link to each other. If auto negotiation is not supported
or the link partner to the KSZ8841M is forced to bypass auto negotiation, the mode is set by observing the signal at the
receiver. This is known as parallel mode because while the transmitter is sending auto negotiation advertisements, the
receiver is listening for advertisements or a fixed signal protocol.
The link up process is shown in Figure 3-3.
FIGURE 3-3:
AUTO-NEGOTIATION AND PARALLEL OPERATION
START AUTO-NEGOTIATION
PARALLEL
FORCE LINK SETTING
NO
OPERATION
YES
ATTEMPT AUTO-
NEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
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®
3.2.9
LINKMD CABLE DIAGNOSTICS
The KSZ8841M LinkMD® uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling prob-
lems such as open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault with
a maximum distance of 200m and an accuracy of ±2m. Internal circuitry displays the TDR information in a user-readable
digital format in register P1VCT[8:0].
Note that cable diagnostics are only valid for copper connections. Fiber-optic operation is not supported.
3.2.9.1
Access
LinkMD is initiated by accessing register P1VCT, the LinkMD Control/Status register, in conjunction with register P1CR4,
the 100BASE-TX PHY Controller register.
3.2.9.2
Usage
LinkMD can be run at any time by ensuring that Auto-MDIX has been disabled. To disable Auto-MDIX, write a ‘1’ to
P1CR4[10] to enable manual control over the pair used to transmit the LinkMD pulse. The self-clearing cable diagnostic
test enable bit, P1VCT[15], is set to ‘1’ to start the test on this pair.
When bit P1VCT[15] returns to ‘0’, the test is complete. The test result is returned in bits P1VCT[14:13] and the distance
is returned in bits P1VCT[8:0]. The cable diagnostic test results are as follows:
00 = Valid test, normal condition
01 = Valid test, open circuit in cable
10 = Valid test, short circuit in cable
11 = Invalid test, LinkMD failed
If P1VCT[14:13]=11, this indicates an invalid test, and occurs when the KSZ8841M is unable to shut down the link part-
ner. In this instance, the test is not run, as it is not possible for the KSZ8841M to determine if the detected signal is a
reflection of the signal generated or a signal from another source.
Cable distance can be approximated by the following formula:
P1VCT[8:0] x 0.4m for port 1 cable distance
This constant may be calibrated for different cabling conditions, including cables with a velocity of propagation that var-
ies significantly from the norm.
3.2.10
MEDIA ACCESS CONTROL (MAC) OPERATION
The KSZ8841M strictly abides by IEEE 802.3 standards to maximize compatibility.
3.2.10.1
Inter Packet Gap (IPG)
If a frame is successfully transmitted, then the minimum 96-bit time for IPG is measured between two consecutive pack-
ets. If the current packet is experiencing collisions, the minimum 96-bit time for IPG is measured from carrier sense
(CRS) to the next transmit packet.
3.2.10.2
Back-Off Algorithm
The KSZ8841M implements the IEEE standard 802.3 binary exponential back-off algorithm in half-duplex mode. After
16 collisions, the packet is dropped.
3.2.10.3
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
3.2.10.4
Flow Control
The KSZ8841M supports standard 802.3x flow control frames on both transmit and receive sides.
On the receive side, if the KSZ8841M receives a pause control frame, the KSZ8841M will not transmit the next normal
frame until the timer, specified in the pause control frame, expires. If another pause frame is received before the current
timer expires, the timer will be updated with the new value in the second pause frame. During this period (while it is flow
controlled), only flow control packets from the KSZ8841M are transmitted.
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On the transmit side, the KSZ8841M has intelligent and efficient ways to determine when to invoke flow control. The
flow control is based on availability of the system resources.
The KSZ8841M issues a flow control frame (Xoff, or transmitter off), containing the maximum pause time defined in
IEEE standard 802.3x. Once the resource is freed up, the KSZ8841M sends out the another flow control frame (Xon, or
transmitter on) with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is
provided to prevent the flow control mechanism from being constantly activated and deactivated.
3.2.10.5
Half-Duplex Backpressure
A half-duplex backpressure option (non-IEEE 802.3 standards) is also provided. The activation and deactivation condi-
tions are the same as in full-duplex mode. If backpressure is required, the KSZ8841M sends preambles to defer the
other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the 802.3 standard), after a certain time, the KSZ8841M dis-
continues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents other sta-
tions from sending out packets thus keeping other stations in a carrier sense deferred state. If the port has packets to
send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets are trans-
mitted instead. If there are no additional packets to send, carrier sense type backpressure is reactivated again until chip
resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense is gener-
ated immediately, thus reducing the chance of further collision and carrier sense is maintained to prevent packet recep-
tion.
3.2.10.6
Clock Generator
The X1 and X2 pins are connected to a 25 MHz crystal. X1 can also serve as the connector to a 3.3V, 25 MHz oscillator
(as described in the pin description).
The bus interface unit (BIU) uses BCLK (Bus Clock) for synchronous accesses. The maximum frequency is 50 MHz for
VLBus-like and EISA-like slave direct memory access (DMA).
3.2.11
BUSINESS INTERFACE UNIT (BIU)
The BIU host interface is a generic bus interface, designed to communicate with embedded processors. The use of glue
logic may be required when it talks to various standard buses and processors.
3.2.11.1
Supported Transfers
In terms of transfer type, the BIU can support two transfers: asynchronous transfer and synchronous transfer. To support
these transfers (asynchronous and synchronous), the BIU provides three groups of signals:
• Synchronous signals
• Asynchronous signals
• Common signals are used for both synchronous and asynchronous transfers.
Because both synchronous and asynchronous signals are independent of each other, synchronous transfer and asyn-
chronous transfer can be mixed or interleaved but cannot be overlapped (due to the sharing of common signals).
3.2.11.2
Physical Data Bus Size
The BIU supports an 8-bit, 16-bit, or 32-bit host standard data bus. Depending on the size of the physical data bus, the
KSZ8841M supports 8-bit, 16-bit, or 32-bit data transfers
For example,
For a 32-bit system/host data bus, the KSZ8841M allows an 8-bit, 16-bit, and 32-bit data transfer (KSZ8841-32MQL).
For a 16-bit system/host data bus, the KSZ8841M allows an 8-bit and 16-bit data transfer (KSZ8841-16MQL).
For an 8-bit system/host data bus, the KSZ8841M only allows an 8-bit data transfer (KSZ8841-16MQL).
The KSZ8841M does not support internal data byte-swap but it does support internal data word-swap. This means that
the system/host data bus HD[7:0] must connect to both D[7:0] and D[15:8] for an 8-bit data bus interface. For a 16-bit
data bus, the system/host data bus HD[15:8] and HD[7:0] only need to connect to D[15:8] and D[7:0] respectively, and
there is no need to connect HD[15:8] and HD[7:0] to D[31:24] and D[23:16].
Table 3-2 describes the BIU signal grouping.
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TABLE 3-2:
Signal
BUS INTERFACE UNIT SIGNAL GROUPING
Type
Function
Common Signals
A[15:1]
I
Address
Address Enable
AEN
I
Address Enable asserted indicates memory address on the bus for DMA access and because
the device is an I/O device, address decoding is only enabled when AEN is Low.
Byte Enable
BE0N
BE1N
BE2N
BE3N
Description
32-bit access
0
0
1
0
1
1
1
0
0
1
1
0
1
1
0
1
0
1
1
0
1
0
1
0
1
1
1
0
Lower 16-bit (D[15:0]) access
Higher 16-bit (D[31:16]) access
Byte 0 (D[7:0]) access
BE3N,
BE2N,
BE1N,
BE0N
I
Byte 1 (D[15:8]) access
Byte 2 (D[23:16]) access
Byte 3 (D[31:24]) access
Note 1: BE3N, BE2N, BE1N, and BE0N are ignored when DATACSN is low because 32-bit
transfers are assumed.
Note 2: BE2N and BE3N are valid only for the KSZ8841-32 mode, and are No Connect for the
KSZ8841-16 mode.
Data
D[31:16]
D[15:0]
ADSN
I/O
I/O
I
For KSZ8841M-32 mode only.
Data
For both KSZ8841-32 and KSZ8841-16 modes
Address Strobe
The rising edge of ADSN is used to latch A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N.
Local Device
LDEVN
O
This signal is a combinatorial decode of AEN and A[15:4]. This A[15:4] is used to compare
against the Base Address Register.
Data Register Chip Select (For KSZ8841-32MQL Mode only)
This signal is used for central decoding architecture (mostly for embedded application). When
asserted, the device’s local decoding logic is ignored and the 32-bit access to QMU Data
Register is assumed.
DATACSN
INTR
I
O
Interrupt
Synchronous Transfer Signals
VLBUS
VLBUSN
CYCLEN
SWR
I
I
I
VLBUSN = 0, VLBus-like cycle.
VLBUSN = 1, burst cycle (both host/system and KSZ8841M can insert wait state)
CYCLEN
For VLBus-like access: used to sample SWR when asserted.
For burst access: used to connect to IOWC# bus signal to indicate burst write.
Write/Read
For VLBus-like access: used to indicate write (High) or read (Low) transfer.
For burst access: used to connect to IORC# bus signal to indicate burst read.
Synchronous Ready
For VLBus-like access: exactly the same signal definition of nSRDY in VLBus.
For burst access: insert wait state by KSZ8841M whenever necessary during the Data Regis-
ter access.
SRDYN
O
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TABLE 3-2:
Signal
BUS INTERFACE UNIT SIGNAL GROUPING (CONTINUED)
Type
Function
Ready Return
For VLBus-like access: exactly like RDYRTNN signal in VLBus to end the cycle.
For burst access: exactly like EXRDY signal in EISA to insert wait states. Note that the wait
states are inserted by system logic (memory) not by KSZ8841M.
RDYRTNN
BCLK
I
I
Bus Clock
Asynchronous Transfer Signals
RDN
I
I
Asynchronous Read
Asynchronous Write
WRN
Asynchronous Ready
This signal is asserted (Low) to insert wait states.
ARDY
O
Note 3-1
I = Input. O = Output. I/O = Bi-directional.
Regardless of whether the transfer is synchronous or asynchronous, if the address latch is required, use the rising edge
of ADSN to latch the incoming signals A[15:1], AEN, BE3N, BE2N, BE1N, and BE0N.
Note that if the local device decoder is used in either synchronous or asynchronous transfers, LDEVN will be asserted
to indicate that the KSZ8841M is successfully targeted. The signal LDEVN is a combinatorial decode of AEN and
A[15:4].
3.2.11.3
Asynchronous Interface
For asynchronous transfers, the asynchronous dedicated signals RDN (for read) or WRN (for write) toggle, but the syn-
chronous dedicated signals CYCLEN, SWR, and RDYRTNN are de-asserted and stay at the same logic level through-
out the entire asynchronous transfer.
There is no data burst support for asynchronous transfer. All asynchronous transfers are single-data transfers. The BIU,
however, provides flexible asynchronous interfacing to communicate with various applications and architectures. Three
major ways of interfacing with the system (host) are.
• Interfacing with the system/host relying on local device decoding and having stable address throughout the whole
transfer: The typical example for this application is ISA-like bus interface using latched address signals as shown
in Figure 13. No additional address latch is required, therefore ADSN should be connected Low. The BIU decodes
A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. The
host utilizes the rising edge of RDN to latch read data and the BIU will use rising edge of WRN to latch write data.
• Interfacing with the system/host relying on local device decoding but not having stable address throughout the
entire transfer: The typical example for this application is EISA-like bus (non-burst) interface as shown in Figure
14. This type of interface requires ADSN to latch the address on the rising edge. The BIU decodes latched A[15:4]
and qualifies with AEN to determine if the KSZ8841M device is the intended target. The data transfer is the same
as the first case.
• Interfacing with the system/host relying on central decoding (KSZ8841-32MQL only): The typical example for this
application is for an embedded processor having a central decoder on the system board or within the processor.
Connecting the chip select (CS) from system/host to DATACSN bypasses the local device decoder. When the
DATACSN is asserted, it only allows access to the Data Register in 32 bits and BE3N, BE2N, BE1N, and BE0N
are ignored as shown in Figure 15. No other registers can be accessed by asserting DATACSN. The data transfer
is the same as in the first case. Independent of the type of asynchronous interface used. To insert a wait state, the
BIU will assert ARDY to prolong the cycle.
3.2.11.4
Synchronous Interface
For synchronous transfers, the synchronous dedicated signals CYCLEN, SWR, and RDYRTNN will toggle but the asyn-
chronous dedicated signals RDN and WRN are de-asserted and stay at the same logic level throughout the entire syn-
chronous transfer.
The synchronous interface mainly supports two applications, one for VLBus-like and the other for EISA-like (DMA type
C) burst transfers. The VLBus-like interface supports only single-data transfer. The pin option VLBUSN determines if it
is a VLBus-like or EISA-like burst transfer. If VLBUSN = 0, the interface is for VLBus-like transfer; if VLBUSN = 1, the
interface is for EISA-like burst transfer.
For VLBus-like transfer interface (VLBUSN = 0):
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This interface is used in an architecture in which the device’s local decoder is utilized; that is, the BIU decodes latched
A[15:4] and qualifies with AEN (Address Enable) to determine if the KSZ8841M device is the intended target. No burst
is supported in this application. The M/nIO signal connection in VLBus is routed to AEN. The CYCLEN in this application
is used to sample the SWR signal when it is asserted. Usually, CYCLEN is one clock delay of ADSN. There is a hand-
shaking process to end the cycle of VLBus-like transfers. When the KSZ8841M is ready to finish the cycle, it asserts
SRDYN. The system/host acknowledges SRDYN by asserting RDYRTNN after the system/host has latched the read
data. The KSZ8841M holds the read data until RDYRTNN is asserted. The timing waveform is shown in Figures 19 and
20.
For EISA-like burst transfer interface (VLBUSN = 1):
The SWR is connected to IORC# in EISA to indicate the burst read and CYCLEN is connected to IOWC# in EISA to
indicate the burst write. Note that in this application, both the system/host/memory and KSZ8841M are capable of insert-
ing wait states. For system/host/memory to insert a wait state, assert the RDYRTNN signal; for the KSZ8841M to insert
the wait state, assert the SRDYN signal. The timing waveform is shown in Figures 17 and 18.
3.2.11.5
BIU Summation
Figure 3-4 shows the mapping from ISA-like, EISA-like and VLBus-like transactions to the chip’s BIU.
Figure 3-5 shows the connection for different data bus sizes.
Note: For the 8-bit data bus mode, the internal inverter is enabled and connected between BE0N and BE1N, so an even
address will enable the BE0N and an odd address will enable the BE1N.
FIGURE 3-4:
MAPPING FROM THE ISA, EISA, AND VLBUS TO THE KSZ8841M BUS
INTERFACE
KSZ8841M BIU
ISA
Host Interface
Host Interface
No Addr Latch
(ADSN = 0)
Local
decode
Asynchronous
Interface
Address Latch
Central decode
Non-burst
EISA
Central decode
(VLBUSN = 1)
Host Interface
Host Interface
Burst
Synchronous
Interface
Local
VLBus
Address Latch
decode
(VLBUSN = 0)
Note: To use DATACSN & 32-bit only for Central decode
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FIGURE 3-5:
KSZ8841M 8-BIT, 16-BIT, AND 32-BIT DATA BUS CONNECTIONS
KSZ8841-16
KSZ8841-16
KSZ8841-32
HA[1]
HA[1]
A[1]
GND
A[1]
A[1]
HA[15:2]
A[15:2]
HA[15:2]
A[15:2]
HA[15:2]
A[15:2]
D[7:0]
HD[7:0]
HD[15:8]
HD[23:16]
HD[31:24]
HD[7:0]
HD[15:8]
D[7:0]
D[15:8]
HD[7:0]
D[7:0]
D[15:8]
D[15:8]
D[23:16]
D[31:24]
HA[0]
BE0N
BE1N
HA[0]
VDD
BE0N
BE1N
BE0N
BE1N
BE2N
BE3N
nHBE[0]
nHBE[1]
nHBE[2]
nHBE[3]
nSBHE
16-bit Data Bus
(for example: ISA-like)
8-bit Data Bus
32-bit Data Bus
(for example: EISA-like)
3.2.11.6
BIU Implementation Principles
Because KSZ8841M is an I/O device with 16 addressable locations, address decoding is based on the values of A15-
A4 and AEN. Whenever DATACSN is asserted, the address decoder is disabled and a 32-bit transfer to Data Register
is assumed (BE3N – BE0N are ignored).
If address latching is required, the address is latched on the rising edge of ADSN and is transparent when ADSN = 0.
• Byte, word, and double word data buses and accesses (transfers) are supported.
• Internal byte swapping is not implemented and word swapping is supported internally. Refer to Figure 11 for the
appropriate 8-bit, 16-bit, and 32-bit data bus connection.
• Because independent sets of synchronous and asynchronous signals are provided, synchronous and asynchro-
nous cycles can be mixed or interleaved as long as they are not active simultaneously.
• The asynchronous interface uses RDN and WRN signal strobes for data latching. If necessary, ARDY is de-
asserted on the leading edge of the strobe.
• The VLBUS-like synchronous interface uses BCLK, ADSN, and SWR and CYCLEN to control read and write
operations and generate SRDYN to insert the wait state, if necessary, when VLBUSN = 0. For read, the data must
be held until RDYRTNN is asserted.
The EISA-like burst transfer is supported using synchronous interface signals and DATACSN when I/O signal VLBUSN
= 1. Both the system/host/memory and KSZ8841M are capable of inserting wait states. To set the system/host/memory
to insert a wait state, assert RDYRTNN signal. To set the KSZ8841M to insert a wait state, assert SRDYN signal.
3.2.12
QUEUE MANAGEMENT UNIT (QMU)
The Queue Management Unit (QMU) manages packet traffic between the MAC/PHY interface and the system host. It
has built-in packet memory for receive and transmit functions called TXQ (Transmit Queue) and RXQ (Receive Queue).
Each queue contains 4 KB of memory for back-to-back, non-blocking frame transfer performance. It provides a group
of control registers for system control, frame status registers for current packet transmit/receive status, and interrupts
to inform the host of the real time TX/RX status.
3.2.12.1
Transmit Queue (TXQ) Frame Format
The frame format for the transmit queue is shown in Table 3-3. The first word contains the control information for the
frame to transmit. The second word is used to specify the total number of bytes of the frame. The packet data follows.
The packet data area holds the frame itself. It may or may not include the CRC checksum depending upon whether
hardware CRC checksum generation is enabled.
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Multiple frames can be pipelined in both the transmit queue and receive queue as long as there is enough queue mem-
ory, thus avoiding overrun. For each transmitted frame, the transmit status information for the frame is located in the
TXSR register.
TABLE 3-3:
FRAME FORMAT FOR TRANSMIT QUEUE
Bit 15
2nd Byte
Bit 0
1st Byte
Packet Memory Address Offset
0
2
Control Word
Byte Count
Transmit Packet Data
(maximum size is 1916)
4 and up
Because multiple packets can be pipelined into the TX packet memory for transmit, the transmit status reflects the status
of the packet that is currently being transferred on the MAC interface, which may or may not be the last queued packet
in the TX queue.
The transmit control word is the first 16-bit word in the TX packet memory, followed by a 16-bit byte count. It must be
word aligned. Each control word corresponds to one TX packet. Table 3-4 gives the transmit control word bit fields.
TABLE 3-4:
TRANSMIT CONTROL WORD BIT FIELDS
Bit
Description
15
TXIC Transmit Interrupt on Completion
When this bit is set, the KSZ8841M sets the transmit interrupt after the present frame has been
transmitted.
14 - 6
5 - 0
Reserved.
TXFID Transmit Frame ID
This field specifies the frame ID that is used to identify the frame and its associated status infor-
mation in the transmit status register.
TABLE 3-5:
Bit
TRANSMIT BYTE COUNT FORMAT
Description
15 - 11
10 - 0
Reserved.
TXBC Transmit Byte Count
Transmit Byte Count. Hardware uses the byte count information to conserve the TX buffer mem-
ory for better utilization of the packet memory.
Note: The hardware behavior is unknown if an incorrect byte count information is written to this
field. Writing a 0 value to this field is not permitted.
The data area contains six bytes of Destination Address (DA) followed by six bytes of Source Address (SA), followed
by a variable-length number of bytes. On transmit, all bytes are provided by the CPU, including the source address. The
KSZ8841M does not insert its own SA. The 802.3 Frame Length word (Frame Type in Ethernet) is not interpreted by
the KSZ8841M. It is treated transparently as data both for transmit operations.
3.2.12.2
Receive Queue (RXQ) Frame Format
The frame format for the receive queue is shown in Table 3-6. The first word contains the status information for the
frame received. The second word is the total number of bytes of the RX frame. Following that is the packet data area.
The packet data area holds the frame itself. It may or may not include the CRC checksum depending on whether hard-
ware CRC stripping is enabled.
TABLE 3-6:
FRAME FORMAT FOR RECEIVE QUEUE
Packet Memory
Address Offset
Bit 15
2nd Byte
Bit 0
1st Byte
0
2
Status Word
Byte Count
4 and up
Receive Packet Data
(maximum size is 1916)
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For receive, the packet receive status always reflects the receive status of the packet received in the current RX packet
memory (see Table 3-7). The RXSR register indicates the status of the current received frame.
TABLE 3-7:
Bit
RXQ RECEIVE PACKET STATUS WORD
Description
RXFV Receive Frame Valid
When set, this field indicates that the present frame in the receive packet memory is valid. The
status information currently in this location is also valid.
15
When clear, it indicates that there is either no pending receive frame or that the current frame is
still in the process of receiving.
14 - 8
7
Reserved.
RXBF Receive Broadcast Frame
When set, it indicates that this frame has a broadcast address.
RXMF Receive Multicast Frame
When set, it indicates that this frame has a multicast address (including the broadcast address).
6
RXUF Receive Unicast Frame
When set, it indicates that this frame has a unicast address.
5
4
Reserved.
RXFT Receive Frame Type
When set, it indicates that the frame is an Ethernet-type frame (frame length is greater than 1500
bytes). When clear, it indicates that the frame is an IEEE 802.3 frame.
This bit is not valid for runt frames.
3
2
RXTL Receive Frame Too Long
When set, it indicates that the frame length exceeds the maximum size of 1518 bytes. Frames that
are too long are passed to the host only if the pass bad frame bit is set.
Note: Frame too long is only a frame length indication and does not cause any frame truncation.
RXRF Receive Runt Frame
When set, it indicates that a frame was damaged by a collision or had a premature termination
before the collision window passed.
Runt frames are passed to the host only if the pass bad frame bit is set.
1
0
RXCE Receive CRC Error
When set, it indicates that a CRC error has occurred on the current received frame.
CRC error frames are passed to the host only if the pass bad frame bit is set.
Table 3-8 gives the format of the RX byte count field.
TABLE 3-8:
Bit
RXQ RECEIVE PACKET BYTE COUNT WORD
Description
15 - 11
Reserved.
RXBC Receive Byte Count
Receive Byte Count up to 1916 bytes
10 - 0
3.2.13
EEPROM INTERFACE
It is optional in the KSZ8841M to use an external EEPROM. In the case that an EEPROM is not used, the EEEN pin
must be tied Low or floating.
An external serial EEPROM with a standard microwire bus interface is used for non-volatile storage of information such
as the host MAC address, base address, and default configuration settings. The KSZ8841M can detect if the EEPROM
is a 1 KB (93C46) or 4 KB (93C66) EEPROM device (the 93C46 and the 93C66 are typical EEPROM devices). The
EEPROM is organized as 16-bit mode.
If the EEEN pin is pulled high, then the KSZ8841M performs an automatic read of the external EEPROM words 0H to
6H after the deassertion of Reset. The EEPROM values are placed in certain host-accessible registers. EEPROM read/
write functions can also be performed by software read/writes to the EEPCR registers.
The KSZ8841M EEPROM format is given in Table 3-9.
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TABLE 3-9:
Word
KSZ8841M EEPROM FORMAT
15 - 8
7 - 0
0H
1H
Base Address
Host MAC Address Byte 2
Host MAC Address Byte 4
Host MAC Address Byte 6
Reserved
Host MAC Address Byte 1
Host MAC Address Byte 3
Host MAC Address Byte 5
2H
3H
4H
5H
Reserved
6H
ConfigParam (see Table 3-10)
7H - 3FH
Not used for KSZ8841M (available for user to use)
The format for ConfigParam is shown in Table 3-10.
TABLE 3-10: CONFIGPARAM WORD IN EEPROM FORMAT
Bit
Bit Name
Description
15
Reserved
Reserved.
No Soft Reset
When this bit is set, indicates that KSZ8841M transitioning from D3_hot to D0
because of PowerState commands do not perform an internal reset. Configura-
tion Context is preserved. Upon transition from the D3_hot to the D0 Initialized
state, no additional operating system intervention is required to preserve Con-
figuration Context beyond writing the PowerState bits.
When this bit is clear, KSZ8841M performs an internal reset upon transitioning
from D3_hot to D0 via software control of the PowerState bits. Configuration
Context is lost when performing the soft reset. Upon transition from the D3_hot
to the D0 state, full reinitialization sequence is needed to return the device to
D0 Initialized.
14
NO_SRST
Regardless of this bit, devices that transition from D3_hot to D0 by a system or
bus segment reset will return to the device state D0 Uninitialized with only PME
context preserved if PME is supported and enabled.
This bit is loaded to bit 3 of PMCS register
13
12
Reserved
PME_D2
Reserved.
PME Support D2
When this bit is set, the KSZ8841M asserts PME event (pin 14) when the
KSZ8841M is in D2 state and PME_EN is set. Otherwise, the KSZ8841M does
not assert PME event when the KSZ8841M is in D2 state.
This bit is loaded to bit 13 of PMCR register
PME Support D1
When this bit is set, the KSZ8841M asserts PME event (pin 14) when the
KSZ8841M is in D1 state and PME_EN is set. Otherwise, the KSZ8841M does
not assert PME event when the KSZ8841M is in D1 state.
This bit is loaded to bit 12 of PMCR register.
11
10
PME_D1
D2_SUP
D2 Support
When this bit is set, the KSZ8841M supports D2 power state. This bit is loaded
to bit 10 of PMCR register.
D1 Support
9
D1_SUP
When this bit is set, the KSZ8841M supports D1 power state. This bit is loaded
to bit 9 of PMCR register.
8 - 2
Reserved
Reserved.
Internal clock rate selection
0 = 125 MHz
1
Clock_Rate
1 = 25 MHz
Note: At power up, this chip operates on 125 MHz clock. The internal fre-
quency can be dropped to 25 MHz via the external EEPROM.
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TABLE 3-10: CONFIGPARAM WORD IN EEPROM FORMAT (CONTINUED)
Bit
Bit Name
Description
Async 8-bit bus select
1 = Bus is configured for 16-bit width
0
ASYN_8bit
0 = Bus is configured for 8-bit width
This bit is loaded to bit 0 of PMCR register
(32-bit width, KSZ8841-32MQL, don’t care this bit setting)
3.2.14
LOOPBACK SUPPORT
The KSZ8841M provides Near-end (Remote) loopback support for remote diagnostic of failure. In loopback mode, the
speed at the PHY port will be set to 100BASE-TX full-duplex mode.
3.2.14.1
Near-End (Remote) Loopback
Near-end (Remote) loopback is conducted at PHY port 1of the KSZ8841M. The loopback path starts at the PHY port’s
receive inputs (RXP1/RXM1), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit
outputs (TXP1/TXM1).
Bit [1] of register P1PHYCTRL is used to enable near-end loopback for port 1. Alternatively, Bit [9] of register
P1SCSLMD can also be used to enable near-end loopback. The ports 1 near-end loopback path is illustrated in
Figure 3-6.
FIGURE 3-6:
PHY PORT 1 NEAR-END (REMOTE) LOOPBACK PATH
RXP1 /
RXM1
TXP1 /
TXM1
PHY Port 1
Near-end (remote)
Loopback
PMD1/PMA1
PCS1
MAC1
RXQ/TXQ
QMU/DMA
Bus I/F Unit
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4.0
4.1
REGISTER DESCRIPTIONS
CPU Interface I/O Registers
The KSZ8841M provides an EISA-like, ISA-like, or VLBUS-like bus interface for the CPU to access its internal I/O reg-
isters. I/O registers serve as the address that the microprocessor uses when communicating with the device. This is
used for configuring operational settings, reading or writing control, status information, and transferring packets by read-
ing and writing through the packet data registers.
4.1.1
I/O REGISTERS
Input/Output (I/O) registers are limited to 16 locations as required by most ISA bus-based systems; therefore, registers
are assigned to different banks. The last word of the I/O register locations (0xE - 0xF) is shared by all banks and can
be used to change the bank in use.
The following I/O Space Mapping Tables apply to 8-, 16-, or 32-bit bus products. Depending upon the bus interface used
and byte enable signals (BE[3:0]N control byte access), each I/O access can be performed as an 8-bit, 16-bit, or 32-bit
operation. The KSZ8841M is not limited to 8/16-bit performance and 32-bit read/write are also supported.
TABLE 4-1:
INTERNAL I/O SPACE MAPPING - BANK 0 TO BANK 7
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Base
Address
[7:0]
Host MAC
Address
Low [7:0]
On-Chip
Bus Control Frame0
[7:0]
Wakeup
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
0x0
CRC0 [7:0] CRC0 [7:0] CRC0 [7:0] CRC0 [7:0]
0x0 to 0x1
Reserved
Reserved
Wakeup
Frame0
CRC0
Wakeup
Frame1
CRC0
Wakeup
Frame2
CRC0
Wakeup
Frame3
CRC0
Base
Address
[15:8]
Host MAC
Address
Low [15:8] [15:8]
On-Chip
Bus Control
0x1
0x2
0x3
[15:8]
[15:8]
[15:8]
[15:8]
0x0 to 0x3
Host MAC
Address
Mid [7:0]
EEPROM
Control
[7:0]
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
CRC1 [7:0] CRC1 [7:0] CRC1 [7:0] CRC1 [7:0]
0x2 to 0x3
Reserved
Wakeup
Frame0
CRC1
Wakeup
Frame1
CRC1
Wakeup
Frame2
CRC1
Wakeup
Frame3
CRC1
Host MAC
Address
Mid [15:8]
EEPROM
Control
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
QMU RX
Flow Con-
trol Water-
mark
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
Host MAC
Address
High [7:0]
Memory
BIST Info
[7:0]
0x4
0x5
ByteMask0 ByteMask0 ByteMask0 ByteMask0
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
0x4 to 0x5
Reserved
QMU RX
Flow Con-
trol Water-
mark
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
Host MAC
Address
High [15:8] [15:8]
Memory
BIST Info
ByteMask0 ByteMask0 ByteMask0 ByteMask0
[15:8]
[15:8]
[15:8]
[15:8]
0x4 to 0x7
[15:8]
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
Bus Error
Status
[7:0]
Global
Reset
[7:0]
0x6
0x7
ByteMask1 ByteMask1 ByteMask1 ByteMask1
[7:0]
[7:0]
[7:0]
[7:0]
0x6 to 0x7
Reserved
Reserved
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
Bus Error
Status
[15:8]
Global
Reset
[15:8]
ByteMask1 ByteMask1 ByteMask1 ByteMask1
[15:8] [15:8] [15:8] [15:8]
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TABLE 4-1:
INTERNAL I/O SPACE MAPPING - BANK 0 TO BANK 7 (CONTINUED)
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 0 Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7
Power
Manage-
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
Bus Burst
Length
[7:0]
0x8
ment Capa- ByteMask2 ByteMask2 ByteMask2 ByteMask2
bilities [7:0] [7:0]
[7:0]
[7:0]
[7:0]
0x8 to 0x9
Reserved
Reserved
Power
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
Bus Burst
Length
[15:8]
Manage-
ment Capa-
bilities
0x9
ByteMask2 ByteMask2 ByteMask2 ByteMask2
[15:8]
[15:8]
[15:8]
[15:8]
[15:8]
0x8 to 0xB
Wakeup
Frame
Control
[7:0]
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
0xA
0xB
ByteMask3 ByteMask3 ByteMask3 ByteMask3
[7:0]
[7:0]
[7:0]
[7:0]
0xA to 0xB
Reserved
Wakeup
Frame
Control
[15:8]
Wakeup
Frame0
Wakeup
Frame1
Wakeup
Frame2
Wakeup
Frame3
ByteMask3 ByteMask3 ByteMask3 ByteMask3
[15:8] [15:8] [15:8] [15:8]
0xC
0xD
0xE
0xF
0xC to 0xD
0xE to 0xF
Reserved
0xC to 0xF
Bank Select [7:0]
Bank Select [15:8]
TABLE 4-2:
INTERNAL I/O SPACE MAPPING - BANK 8 TO BANK 15
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 Bank 13 Bank 14 Bank 15
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0 to 0x1
0x2 to 0x3
0x4 to 0x5
0x6 to 0x7
0x8 to 0x9
0xA to 0xB
0xC to 0xD
0xE to 0xF
Reserved
0x0 to 0x3
Reserved
Reserved
0x4 to 0x7
0x8 to 0xB
0xC to 0xF
Reserved
Reserved
Reserved
Bank Select [7:0]
Bank Select [15:8]
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TABLE 4-3:
INTERNAL I/O SPACE MAPPING - BANK 16 TO BANK 23
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 16 Bank 17 Bank 18 Bank 19 Bank 20 Bank 21 Bank 22 Bank 23
Transmit
Control
[7:0]
Interrupt
Enable
[7:0]
Multicast
Table 0
[7:0]
TXQ Com-
mand [7:0]
0x0
0x0 to 0x1
Reserved
Reserved
Transmit
Control
[15:8]
TXQ Com- Interrupt
Multicast
Table 0
[15:8]
0x1
0x2
0x3
mand
[15:8]
Enable
[15:8]
0x0 to 0x3
Transmit
Status
[7:0]
Interrupt
Status
[7:0]
Multicast
Table 1
[7:0]
RXQ Com-
mand [7:0]
0x2 to 0x3
Transmit
Status
[15:8]
RXQ Com- Interrupt
Multicast
Table 1
[15:8]
mand
[15:8]
Status
[15:8]
TX Frame
Data
Pointer
[7:0]
Receive
Control
[7:0]
Receive
Status
[7:0]
Multicast
Table 2
[7:0]
0x4
0x5
0x6
0x7
0x4 to 0x5
Reserved
TX Frame
Data
Pointer
[15:8]
Receive
Control
[15:8]
Receive
Status
[15:8]
Multicast
Table 2
[15:8]
0x4 to 0x7
RX Frame
Data
Pointer
[7:0]
Receive
Byte
Counter
[7:0]
Multicast
Table 3
[7:0]
0x6 to 0x7
Reserved
Reserved
RX Frame
Data
Pointer
[15:8]
Receive
Byte
Counter
[15:8]
Multicast
Table 3
[15:8]
Power
TXQ Mem-
ory Infor-
mation
QMU Data Early
Manage-
ment Con-
trol/Status
[7:0]
0x8
0x9
Low
[7:0]
Transmit
[7:0]
[7:0]
0x8 to 0x9
Reserved
Power
TXQ Mem-
ory Infor-
mation
QMU Data Early
Manage-
ment Con-
trol/Status
[15:8]
Low
Transmit
[15:8]
[15:8]
0x8 to 0xB
[15:8]
RXQ Mem- QMU Data Early
0xA
0xB
ory Infor-
mation [7:0] [7:0]
High
Receive
[7:0]
0xA to 0xB
Reserved
RXQ Mem-
QMU Data Early
High
[15:8]
ory Infor-
mation
[15:8]
Receive
[15:8]
0xC
0xD
0xE
0xF
0xC to 0xD
0xE to 0xF
Reserved
0xC to 0xF
Bank Select [7:0]
Bank Select [15:8]
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TABLE 4-4:
INTERNAL I/O SPACE MAPPING - BANK 24 TO BANK 31
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 24 Bank 25 Bank 26 Bank 27 Bank 28 Bank 29 Bank 30 Bank 31
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0 to 0x1
Reserved
Reserved
0x0 to 0x3
0x2 to 0x3
0x4 to 0x5
0x6 to 0x7
0x8 to 0x9
0xA to 0xB
0xC to 0xD
0xE to 0xF
Reserved
0x4 to 0x7
0x8 to 0xB
Reserved
Reserved
Reserved
Bank Select [7:0]
Bank Select [15:8]
0xC to 0xF
TABLE 4-5:
INTERNAL I/O SPACE MAPPING - BANK 32 TO BANK 39
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 32 Bank 33 Bank 34 Bank 35 Bank 36 Bank 37 Bank 38 Bank 39
Chip ID
0x0
and Enable
[7:0]
0x0 to 0x1
Reserved
Chip ID
0x0 to 0x3
0x1
and Enable
[15:8]
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0x2 to 0x3
0x4 to 0x5
0x6 to 0x7
0x8 to 0x9
Reserved
Reserved
Reserved
Reserved
0x4 to 0x7
0x8 to 0xB
0xC to 0xF
ChipGlobal
Control
[7:0]
0xA
0xB
0xA to 0xB
Reserved
ChipGlobal
Control
[15:8]
0xC
0xD
0xE
0xF
0xC to 0xD
0xE to 0xF
Reserved
Bank Select [7:0]
Bank Select [15:8]
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KSZ8841-16M/-32M
TABLE 4-6:
INTERNAL I/O SPACE MAPPING - BANK 40 TO BANK 47
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 40 Bank 41 Bank 42 Bank 43 Bank 44 Bank 45 Bank 46 Bank 47
PHY1 MII-
Register
Basic Con-
trol
PHY1
LinkMD
Control/
Status
[7:0]
Indirect
Access
Control.
[7:0]
0x0
[7:0]
0x0 to 0x1
Reserved
Reserved
Reserved
PHY1
Indirect
Access
Control.
[15:8]
PHY1 MII-
Register
Basic Con-
trol [15:8]
LinkMD
Control/
Status
[15:8]
0x1
0x2
0x3
0x0 to 0x3
PHY1 MII-
Register
Basic Sta-
tus
PHY1
Special
Control/
Status
[7:0]
Indirect
Access
Data 1
[7:0]
[7:0]
0x2 to 0x3
Reserved
Reserved
Reserved
PHY1
Indirect
Access
Data 1
[15:8]
PHY1 MII-
Register
Basic Sta-
tus [15:8]
Special
Control/
Status
[15:8]
Indirect
PHY1
0x4
0x5
Access
Data 2 [7:0]
PHYID Low
[7:0]
0x4 to 0x5
Reserved
Reserved
Reserved
Reserved
Reserved
Indirect
Access
Data 2
[15:8]
PHY1
PHYID Low
[15:8]
0x4 to 0x7
PHY1
PHYID
High
Indirect
Access
Data 3 [7:0]
0x6
0x7
0x8
0x9
0xA
0xB
[7:0]
0x6 to 0x7
Reserved
Reserved
Reserved
Indirect
Access
Data 3
[15:8]
PHY1
PHYID
High
[15:8]
PHY1 A.N.
Advertise-
ment
Indirect
Access
Data 4 [7:0]
[7:0]
0x8 to 0x9
Reserved
Reserved
Indirect
Access
Data 4
[15:8]
PHY1 A.N.
Advertise-
ment
[15:8]
0x8 to 0xB
PHY1 A.N.
Link Part-
ner Ability
[7:0]
Indirect
Access
Data 5 [7:0]
0xA to 0xB
Reserved
Reserved
Reserved
Indirect
Access
Data 5
[15:8]
PHY1 A.N.
Link Part-
ner Ability
[15:8]
0xC
0xD
0xE
0xF
0xC to 0xD
0xE to 0xF
0xC to 0xF
Bank Select [7:0]
Bank Select [15:8]
2019 Microchip Technology Inc.
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KSZ8841-16M/-32M
TABLE 4-7:
INTERNAL I/O SPACE MAPPING - BANK 48 TO BANK 55
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 48 Bank 49 Bank 50 Bank 51 Bank 52 Bank 53 Bank 54 Bank 55
Port 1 PHY
Special
Control/
Status,
LinkMD
[7:0]
0x0
0x0 to 0x1
Reserved
Reserved
Port 1 PHY
Special
Control/
Status,
0x1
0x0 to 0x3
LinkMD
[15:8]
Port 1
Control 4
[7:0]
0x2
0x3
0x4
0x5
0x2 to 0x3
0x4 to 0x5
Reserved
Reserved
Reserved
Reserved
Port 1
Control 4
[15:8]
Port 1
Status
[7:0]
Port 1
Status
[15:8]
0x4 to 0x7
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x6 to 0x7
0x8 to 0x9
0xA to 0xB
0xC to 0xD
0xE to 0xF
Reserved
Reserved
Reserved
Reserved
0x8 to 0xB
0xC to 0xF
Bank Select [7:0]
Bank Select [15:8]
TABLE 4-8:
INTERNAL I/O SPACE MAPPING - BANK 56 TO BANK 63
I/O Register Location
Bank Location
32-Bit
16-Bit
8-Bit
Bank 56 Bank 57 Bank 58 Bank 59 Bank 60 Bank 61 Bank 62 Bank 63
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
0x8
0x9
0xA
0xB
0xC
0xD
0xE
0xF
0x0 to 0x1
0x2 to 0x3
0x4 to 0x5
0x6 to 0x7
0x8 to 0x9
0xA to 0xB
0xC to 0xD
0xE to 0xF
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0x0 to 0x3
0x4 to 0x7
0x8 to 0xB
0xC to 0xF
Bank Select [7:0]
Bank Select [15:8]
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KSZ8841-16M/-32M
4.2
Register Map: MAC and PHY
Do not write to bit values or to registers defined as Reserved. Manipulating reserved bits or registers causes unpredict-
able and often fatal results. If the user wants to write to these reserved bits, the user has to read back these reserved
bits (RO or RW) first, then “OR” with the read value of the reserved bits and write back to these reserved bits.
Bit Type Definitions
• RO = Read only.
• RW = Read/Write.
• W1C = Write 1 to Clear (writing a one to this bit clears it).
Bank 0-63 Bank Select Register (0x0E): BSR (same location in all Banks)
The bank select register is used to select or to switch between different sets of register banks for I/O access. There are
a total of 64 banks available to select, including the built-in switch engine registers.
TABLE 4-9:
Bit
BANK 0-63 BANK SELECT REGISTER (0X0E)
Default Value
R/W
Description
15 - 6 0x000
RO
Reserved
BSA Bank Select Address Bits
BSA bits select the I/O register bank in use.
This register is always accessible regardless of the register bank
currently selected.
Notes:
5 - 0
0x00
R/W
The bank select register can be accessed as a doubleword (32-bit)
at offset 0xC, as a word (16-bit) at offset 0xE, or as a byte (8-bit) at
offset 0xE.
A doubleword write to offset 0xC writes to the BANK Select Regis-
ter but does not write to registers 0xC and 0xD; it only writes to reg-
ister 0xE.
Bank 0 Base Address Register (0x00): BAR
This register holds the base address for decoding a device access. Its value is loaded from the external EEPROM
(0x0H) upon a power-on reset if the EEPROM Enable (EEEN) pin is tied to High. Its value can also be modified after
reset. Writing to this register does not store the value into the EEPROM. When the EEEN pin is tied to Low, the default
base address is 0x300.
TABLE 4-10: BANK 0 BASE ADDRESS REGISTER (0X00)
Bit
Default Value
R/W
Description
0x03 if EEEN is Low or
BARH Base Address High
15 - 8 the value from EEPROM
if EEEN is High
R/W
These bits are compared against the address on the bus
ADDR[15:8] to determine the BASE for the KSZ8841M registers.
0x00 if EEEN is Low or
BARL Base Address Low
7 - 5
4 - 0
the value from EEPROM
if EEEN is High
R/W
RO
These bits are compared against the address on the bus
ADDR[7:5] to determine the BASE for the KSZ8841M registers.
0x00
Reserved
Bank 0 QMU RX Flow Control High Watermark Configuration Register (0x04): QRFCR
This register contains the user defined QMU RX Queue high watermark configuration bit as below.
TABLE 4-11:
Bit
Default Value
R/W
Description
15 - 13 0x0
RO
Reserved
12
0
R/W
QMU RX Flow Control High Watermark Configuration
0 = 3 KBytes
1 = 2 KBytes
11 - 0 0x000
RO
Reserved
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Bank 0 Bus Error Status Register (0x06): BESR
This register flags the different kinds of errors on the host bus.
TABLE 4-12: BANK 0 BUS ERROR STATUS REGISTER (0X06)
Bit
Default Value
R/W
Description
15
0
RO
IBEC Illegal Byte Enable Combination
1 = Illegal byte enable combination occurs. The illegal combination
value can be found from bit 14 to bit 11.
0 = Legal byte enable combination.
Write 1 to clear.
14 - 11
—
RO
RO
RO
IBECV Illegal Byte Enable Combination Value
Bit 14 = Byte enable 3.
Bit 13 = Byte enable 2.
Bit 12 = Byte enable 1.
Bit 11 = Byte enable 0.
This value is valid only when bit 15 is set to 1.
10
0
SSAXFER Simultaneous Synchronous and Asnychronous Trans-
fers
1 = Synchronous and Asnychronous Transfers occur simultane-
ously.
0 = Normal.
Write 1 to clear.
9 - 0
0x000
Reserved
Bank 0 Bus Burst Length Register (0x08): BBLR
Before the burst can be sent, the burst length needs to be programmed.
TABLE 4-13: BANK 0 BUS BURST LENGTH REGISTER (0X08)
Bit
Default Value
R/W
Description
15
0
RO
Reserved
BRL Burst Length (for burst read and write)
000: single.
14 - 12 0x0
R/W
RO
011: fixed burst read length of 4.
101: fixed burst read length of 8.
111: fixed burst read length of 16.
11 - 0 0x000
Reserved
Bank 1: Reserved
Except Bank Select Register (0xE).
Bank 2 Host MAC Address Register Low (0x00): MARL
This register along with the other two Host MAC address registers are loaded starting at word location 0x1 of the
EEPROM upon hardware reset. The software driver can modify the register, but it will not modify the original Host MAC
address value in the EEPROM. These six bytes of Host MAC address in external EEPROM are loaded to these three
registers as mapping below:
• MARL[15:0] = EEPROM 0x1(MAC Byte 2 and 1)
• MARM[15:0] = EEPROM 0x2(MAC Byte 4 and 3)
• MARH[15:0] = EEPROM 0x3(MAC Byte 6 and 5)
The Host MAC address is used to define the individual destination address that the KSZ8841M responds to when
receiving frames. Network addresses are generally expressed in the form of 01:23:45:67:89:AB, where the bytes are
received from left to right, and the bits within each byte are received from right to left (LSB to MSB). For example, the
actual transmitted and received bits are on the order of 10000000 11000100 10100010 11100110 10010001 11010101.
These three registers value for Host MAC address 01:23:45:67:89:AB will be held as below:
• MARL[15:0] = 0x89AB
• MARM[15:0] = 0x4567
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• MARH[15:0] = 0x0123
The following table shows the register bit fields for Low word of Host MAC address.
TABLE 4-14: BANK 2 HOST MAC ADDRESS REGISTER LOW (0X00)
Bit
Default Value
R/W
Description
MARL MAC Address Low
The least significant word of the MAC address.
15 - 0
—
R/W
Bank 2 Host MAC Address Register Middle (0x02): MARM
The following table shows the register bit fields for middle word of Host MAC address.
TABLE 4-15: BANK 2 HOST MAC ADDRESS REGISTER MIDDLE (0X02)
Bit
Default Value
R/W
Description
MARM MAC Address Middle
The middle word of the MAC address.
15 - 0
—
R/W
Bank 2 Host MAC Address Register High (0x04): MARH
The following table shows the register bit fields for high word of Host MAC address.
TABLE 4-16: BANK 2 HOST MAC ADDRESS REGISTER HIGH (0X04)
Bit
Default Value
R/W
Description
MARH MAC Address High
The Most significant word of the MAC address.
15 - 0
—
R/W
Bank 3 On-Chip Bus Control Register (0x00): OBCR
This register controls the on-chip bus speed for the KSZ8841M. It is used for power management when the external
host CPU is running at a slow frequency. The default of the on-chip bus speed is 125 MHz without EEPROM. When the
external host CPU is running at a higher clock rate, the on-chip bus should be adjusted for the best performance.
TABLE 4-17: BANK 3 ON-CHIP BUS CONTROL REGISTER (0X00)
Bit
Default Value
R/W
Description
15 - 2
—
RO
Reserved
OBSC On-Chip Bus Speed Control
00 = 125 MHz.
01 = 62.5 MHz.
10 = 41.66 MHz.
11 = 25 MHz.
1 - 0
0x0
R/W
Note: When external EEPROM is enabled, the bit 1 in Configparm
word (0x6H) is used to control this speed as below:
Bit 1 = 0, this value will be 00 for 125 MHz.
Bit 1 = 1, this value will be 11 for 25 MHz.
(User still can write these two bits to change speed after EEPROM
data loaded)
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Bank 3 EEPROM Control Register (0x02): EEPCR
To support an external EEPROM, tie the EEPROM Enable (EEEN) pin to High; otherwise, tie it to Low. If an external
EEPROM is not used, the default chip Base Address (0x300), and the software programs the host MAC address. If an
EEPROM is used in the design (EEPROM Enable pin to High), the chip Base Address and host MAC address are
loaded from the EEPROM immediately after reset. The KSZ8841M allows the software to access (read and write) the
EEPROM directly; that is, the EEPROM access timing can be fully controlled by the software if the EEPROM Software
Access bit is set.
TABLE 4-18: BANK 3 EEPROM CONTROL REGISTER (0X02)
Bit
Default Value
R/W
Description
15 - 5
—
0
RO
Reserved
EESA EEPROM Software Access
1 = Enable software to access EEPROM through bit 3 to bit 0.
0 = Disable software to access EEPROM.
4
3
R/W
RO
EECB EEPROM Status Bit
Data Receive from EEPROM. This bit directly reads the EEDI pin.
—
EECB EEPROM Control Bits
Bit 2 = Data Transmit to EEPROM. This bit directly controls the
device’s EEDO pin.
Bit 1 = Serial Clock. This bit directly controls the device’s EESK pin.
Bit 0 = Chip Select for EEPROM. This bit directly controls the
device’s EECS pin.
2 - 0
0x0
R/W
Bank 3 Memory BIST Info Register (0x04): MBIR
TABLE 4-19: BANK 3 MEMORY BIST INFO REGISTER (0X04)
Bit
Default Value
R/W
Description
15 - 13 0x0
RO
Reserved
TXMBF TX Memory BIST Finish
12
—
RO
When set, it indicates the Memory Built In Self Test completion for
the TX Memory.
TXMBFA TX Memory BIST Fail
When set, it indicates the Memory Built In Self Test has failed.
11
—
—
RO
RO
10 - 5
Reserved
RXMBF RX Memory BIST Finish
4
—
RO
When set, it indicates the Memory Built In Self Test completion for
the RX Memory.
RXMBFA RX Memory BIST Fail
When set, it indicates the Memory Built In Self Test has failed.
3
—
—
RO
RO
2 - 0
Reserved
Bank 3 Global Reset Register (0x06): GRR
This register controls the global reset function with information programmed by the CPU.
TABLE 4-20: BANK 3 GLOBAL RESET REGISTER (0X06)
Bit
Default Value
R/W
Description
15 - 1 0x0000
RO
Reserved
Global Soft Reset
1 = Software reset is active.
0 = Software reset is inactive.
0
0
R/W
Software reset will affect PHY, MAC, QMU, DMA, and the switch
core, only the BIU (base address registers) remains unaffected by a
software reset.
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KSZ8841-16M/-32M
Bank 3 Power Management Capabilities Register (0x08): PMCR
This register is a read-only register that provides information on the K8841M power management capabilities. These
bits are automatically downloaded from Configparam word of EEPROM if pin EEEN is high (enabled EEPROM).
TABLE 4-21: BANK 3 POWER MANAGEMENT CAPABILITIES REGISTER (0X08)
Bit
Default Value
R/W
Description
PME Support D3 (cold)
This bit defaults to 0, so the KSZ8841M does not support D3(cold)
15
0
1
RO
PME Support D3 (hot)
This bit is 1 only. It indicates that the KSZ8841M can assert PME
event (PMEN pin 14) in D3(hot) power state.(see bit1:0 in PMCS
register)
14
13
RO
RO
PME Support D2
If this bit is set, the wake-up signals will assert PME event (PMEN
pin 14) when the KSZ8841M is in D2 power state and PME_EN
(see bit8 in PMCS register) is set. Otherwise, the KSZ8841M does
not assert PME event (PMEN pin 14) when the KSZ8841M is in D2
power state.
0
The value of this bit is loaded from the PME_D2 bit of 0x6 in the
serial EEPROM (without an EEPROM, this bit defaults to 0).
PME Support D1
If this bit is set, the wake-up signals will assert PME event (PMEN
pin 14) when the KSZ8841M is in D1 power state and PME_EN
(see bit8 in PMCS register) is set. Otherwise, the KSZ8841M does
not assert PME event (PMEN pin 14) when the KSZ8841M is in D1
power state.
12
0
RO
The value of this bit loaded from the PME_D1 bit of 0x6 in the serial
EEPROM (without an EEPROM, this bit defaults to 0).
PME Support D0
11
10
0
0
RO
RO
This bit defaults to 0, it is indicating that the KSZ8841M does not
assert PME event (PMEN pin 14) in D0 power state.
D2 Support
If this bit is set, it indicates that the KSZ8841M support D2 power
state. The value of this bit is loaded from the D2_SUP bit of 0x6 in
the serial EEPROM (without an EEPROM, this bit defaults to 0).
D1 Support
If this bit is set, it indicates that the KSZ8841M support D1 power
state. The value of this bit is loaded from the D1_SUP bit of 0x6 in
the serial EEPROM (without an EEPROM, this bit defaults to 0).
9
8 - 1
0
0
RO
RO
RO
—
—
Reserved
Bus Configuration (only for KSZ8841-16MQL device)
1 = Bus width is 16 bits.
0 = Bus width is 8 bits.
(this bit, ASYN_8bit, is only available when EEPROM is enabled)
Bank 3 Wakeup Frame Control Register (0x0A): WFCR
This register holds control information programmed by the CPU to control the wake up frame function.
TABLE 4-22: BANK 3 WAKEUP FRAME CONTROL REGISTER (0X0A)
Bit
Default Value
R/W
Description
15 - 8 0x00
RO
Reserved
MPRXE
Magic Packet RX Enable
When set, it enables the magic packet pattern detection.
When reset, the magic packet pattern detection is disabled.
7
0
R/W
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TABLE 4-22: BANK 3 WAKEUP FRAME CONTROL REGISTER (0X0A) (CONTINUED)
Bit
Default Value
R/W
Description
6 - 4
0x0
0
RO
Reserved
WF3E
Wake up Frame 3 Enable
When set, it enables the Wake up frame 3 pattern detection.
When reset, the Wake up frame 3 pattern detection is disabled.
3
2
1
0
R/W
R/W
R/W
R/W
WF2E
Wake up Frame 2 Enable
When set, it enables the Wake up frame 2 pattern detection.
When reset, the Wake up frame 2 pattern detection is disabled.
0
0
0
WF1E
Wake up Frame 1 Enable
When set, it enables the Wake up frame 1 pattern detection.
When reset, the Wake up frame 1 pattern detection is disabled.
WF0E
Wake up Frame 0 Enable
When set, it enables the Wake up frame 0 pattern detection.
When reset, the Wake up frame 0 pattern detection is disabled.
Bank 4 Wakeup Frame 0 CRC0 Register (0x00): WF0CRC0
This register contains the expected CRC values of the Wake up frame 0 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-23: BANK 4 WAKEUP FRAME 0 CRC0 REGISTER (0X00)
Bit
Default Value
R/W
Description
WF0CRC0
15 - 0 0x0000
R/W
Wake up Frame 0 CRC (lower 16 bits)
The expected CRC value of a Wake up frame 0 pattern.
Bank 4 Wakeup Frame 0 CRC1 Register (0x02): WF0CRC1
This register contains the expected CRC values of the Wake up frame 0 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-24: BANK 4 WAKEUP FRAME 0 CRC1 REGISTER (0X02)
Bit
Default Value
R/W
Description
WF0CRC1
15 - 0
0
R/W
Wake up Frame 0 CRC (upper 16 bits).
The expected CRC value of a Wake up frame 0 pattern.
Bank 4 Wakeup Frame 0 Byte Mask 0 Register (0x04): WF0BM0
This register contains the first 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the first byte
of the Wake up frame 0, setting bit 15 selects the 16th byte of the Wake up frame 0.
TABLE 4-25: BANK 4 WAKEUP FRAME 0 BYTE MASK 0 REGISTER (0X04)
Bit
Default Value
R/W
Description
WF0BM0
15 - 0
0
R/W
Wake up Frame 0 Byte Mask 0
The first 16 bytes mask of a Wake up frame 0 pattern.
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KSZ8841-16M/-32M
Bank 4 Wakeup Frame 0 Byte Mask 1 Register (0x06): WF0BM1
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 0. Setting bit 15 selects the 32nd byte of the Wake up frame 0.
TABLE 4-26: BANK 4 WAKEUP FRAME 0 BYTE MASK 1 REGISTER (0X06)
Bit
Default Value
R/W
Description
WF0BM1
Wake up Frame 0 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake up
frame 0 pattern.
15 - 0
0
R/W
Bank 4 Wakeup Frame 0 Byte Mask 2 Register (0x08): WF0BM2
This register contains the next 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 0. Setting bit 15 selects the 48th byte of the Wake up frame 0.
TABLE 4-27: BANK 4 WAKEUP FRAME 0 BYTE MASK 2 REGISTER (0X08)
Bit
Default Value
R/W
Description
WF0BM2
Wake-up Frame 0 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up
frame 0 pattern.
15 - 0
0
R/W
Bank 4 Wakeup Frame 0 Byte Mask 3 Register (0x0A): WF0BM3
This register contains the last 16 bytes mask values of the Wake up frame 0 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 0. Setting bit 15 selects the 64th byte of the Wake up frame 0.
TABLE 4-28: BANK 4 WAKEUP FRAME 0 BYTE MASK 3 REGISTER (0X0A)
Bit
Default Value
R/W
Description
WF0BM3
Wake-up Frame 0 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame
0 pattern.
15 - 0
0
R/W
Bank 5 Wakeup Frame 1 CRC0 Register (0x00): WF1CRC0
This register contains the expected CRC values of the Wake up frame 1 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard; it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-29: BANK 5 WAKEUP FRAME 1 CRC0 REGISTER (0X00)
Bit
Default Value
R/W
Description
WF1CRC0
15 - 0
0
R/W
Wake-up frame 1 CRC (lower 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
Bank 5 Wakeup Frame 1 CRC1 Register (0x02): WF1CRC1
This register contains the expected CRC values of the Wake up frame 1 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-30: BANK 5 WAKEUP FRAME 1 CRC1 REGISTER (0X02)
Bit
Default Value
R/W
Description
WF1CRC1
15 - 0
0
R/W
Wake-up frame 1 CRC (upper 16 bits).
The expected CRC value of a Wake-up frame 1 pattern.
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Bank 5 Wakeup Frame 1 Byte Mask 0 Register (0x04): WF1BM0
This register contains the first 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the first byte
of the Wake up frame 1, setting bit 15 selects the 16th byte of the Wake up frame 1.
TABLE 4-31: BANK 5 WAKEUP FRAME 1 BYTE MASK 0 REGISTER (0X04)
Bit
Default Value
R/W
Description
WF1BM0
15 - 0
0
R/W
Wake-up frame 1 Byte Mask 0.
The first 16 bytes mask of a Wake-up frame 1 pattern.
Bank 5 Wakeup Frame 1 Byte Mask 1 Register (0x06): WF1BM1
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 1. Setting bit 15 selects the 32nd byte of the Wake up frame 1.
TABLE 4-32: BANK 5 WAKEUP FRAME 1 BYTE MASK 1 REGISTER (0X06)
Bit
Default Value
R/W
Description
WF1BM1
Wake-up frame 1 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake-up
frame 1 pattern.
15 - 0
0
R/W
Bank 5 Wakeup Frame 1 Byte Mask 2 Register (0x08): WF1BM2
This register contains the next 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 1. Setting bit 15 selects the 48th byte of the Wake up frame 1.
TABLE 4-33: BANK 5 WAKEUP FRAME 1 BYTE MASK 2 REGISTER (0X08)
Bit
Default Value
R/W
Description
WF1BM2
Wake-up frame 1 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up
frame 1 pattern.
15 - 0
0
R/W
Bank 5 Wakeup Frame 1 Byte Mask 3 Register (0x0A): WF1BM3
This register contains the last 16 bytes mask values of the Wake up frame 1 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 1. Setting bit 15 selects the 64th byte of the Wake up frame 1.
TABLE 4-34: BANK 5 WAKEUP FRAME 1 BYTE MASK 3 REGISTER (0X0A)
Bit
Default Value
R/W
Description
WF1BM3
Wake-up frame 1 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame
1 pattern.
15 - 0
0
R/W
Bank 6 Wakeup Frame 2 CRC0 Register (0x00): WF2CRC0
This register contains the expected CRC values of the Wake up frame 2 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-35: BANK 6 WAKEUP FRAME 2 CRC0 REGISTER (0X00)
Bit
Default Value
R/W
Description
WF2CRC0
15 - 0
0
R/W
Wake-up frame 2 CRC (lower 16 bits).
The expected CRC value of a Wake-up frame 2 pattern.
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KSZ8841-16M/-32M
Bank 6 Wakeup Frame 2 CRC1 Register (0x02): WF2CRC1
This register contains the expected CRC values of the wake-up frame 2 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-36: BANK 6 WAKEUP FRAME 2 CRC1 REGISTER (0X02)
Bit
Default Value
R/W
Description
WF2CRC1
15 - 0
0
R/W
Wake-up frame 2 CRC (upper 16 bits).
The expected CRC value of a Wake-up frame 2 pattern.
Bank 6 Wakeup Frame 2 Byte Mask 0 Register (0x04): WF2BM0
This register contains the first 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the first byte
of the Wake up frame 2, setting bit 15 selects the 16th byte of the Wake up frame 2.
TABLE 4-37: BANK 6 WAKEUP FRAME 2 BYTE MASK 0 REGISTER (0X04)
Bit
Default Value
R/W
Description
WF2BM0
15 - 0
0
R/W
Wake-up frame 2 Byte Mask 0.
The first 16 bytes mask of a Wake-up frame 2 pattern.
Bank 6 Wakeup Frame 2 Byte Mask 1 Register (0x06): WF2BM1
This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 2. Setting bit 15 selects the 32nd byte of the Wake up frame 2.
TABLE 4-38: BANK 6 WAKEUP FRAME 2 BYTE MASK 1 REGISTER (0X06)
Bit
Default Value
R/W
Description
WF2BM1
Wake-up frame 2 Byte Mask 1.
The next 16 bytes mask covering bytes 17 to 32 of a Wake-up
frame 2 pattern.
15 - 0
0
R/W
Bank 6 Wakeup Frame 2 Byte Mask 2 Register (0x08): WF2BM2
This register contains the next 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 2. Setting bit 15 selects the 48th byte of the Wake up frame 2.
TABLE 4-39: BANK 6 WAKEUP FRAME 2 BYTE MASK 2 REGISTER (0X08)
Bit
Default Value
R/W
Description
WF2BM2
Wake-up frame 2 Byte Mask 2.
The next 16 bytes mask covering bytes 33 to 48 of a Wake-up
frame 2 pattern.
15 - 0
0
R/W
Bank 6 Wakeup Frame 2 Byte Mask 3 Register (0x0A): WF2BM3
This register contains the last 16 bytes mask values of the Wake up frame 2 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 2. Setting bit 15 selects the 64th byte of the Wake up frame 2.
TABLE 4-40: BANK 6 WAKEUP FRAME 2 BYTE MASK 3 REGISTER (0X0A)
Bit
Default Value
R/W
Description
WF2BM3
Wake-up frame 2 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake-up frame
2 pattern.
15 - 0
0
R/W
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Bank 7 Wakeup Frame 3 CRC0 Register (0x00): WF3CRC0
This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake-up byte mask registers.
TABLE 4-41: BANK 7 WAKEUP FRAME 3 CRC0 REGISTER (0X00)
Bit
Default Value
R/W
Description
WF3CRC0
15 - 0
0
R/W
Wake-up frame 3 CRC (lower 16 bits).
The expected CRC value of a Wake up frame 3 pattern.
Bank 7 Wakeup Frame 3 CRC1 Register (0x02): WF3CRC1
This register contains the expected CRC values of the Wake up frame 3 pattern. The value of the CRC calculated is
based on the IEEE 802.3 Ethernet standard, it is taken over the bytes specified in the wake up byte mask registers.
TABLE 4-42: BANK 7 WAKEUP FRAME 3 CRC1 REGISTER (0X02)
Bit
Default Value
R/W
Description
WF3CRC1
15 - 0
0
R/W
Wake-up frame 3 CRC (upper 16 bits).
The expected CRC value of a Wake up frame 3 pattern.
Bank 7 Wakeup Frame 3 Byte Mask 0 Register (0x04): WF3BM0
This register contains the first 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the first byte
of the Wake up frame 3, setting bit 15 selects the 16th byte of the Wake up frame 3.
TABLE 4-43: BANK 7 WAKEUP FRAME 3 BYTE MASK 0 REGISTER (0X04)
Bit
Default Value
R/W
Description
WF3BM0
15 - 0
0
R/W
Wake up Frame 3 Byte Mask 0
The first 16 byte mask of a Wake up frame 3 pattern.
Bank 7 Wakeup Frame 3 Byte Mask 1 Register (0x06): WF3BM1
This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 17th byte
of the Wake up frame 3. Setting bit 15 selects the 32nd byte of the Wake up frame 3.
TABLE 4-44: BANK 7 WAKEUP FRAME 3 BYTE MASK 1 REGISTER (0X06)
Bit
Default Value
R/W
Description
WF3BM1
Wake up Frame 3 Byte Mask 1
The next 16 bytes mask covering bytes 17 to 32 of a Wake up
frame 3 pattern.
15 - 0
0
R/W
Bank 7 Wakeup Frame 3 Byte Mask 2 Register (0x08): WF3BM2
This register contains the next 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 33rd byte
of the Wake up frame 3. Setting bit 15 selects the 48th byte of the Wake up frame 3.
TABLE 4-45: BANK 7 WAKEUP FRAME 3 BYTE MASK 2 REGISTER (0X08)
Bit
Default Value
R/W
Description
WF3BM2
Wake up Frame 3 Byte Mask 2
The next 16 bytes mask covering bytes 33 to 48 of a Wake up
frame 3 pattern.
15 - 0
0
R/W
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Bank 7 Wakeup Frame 3 Byte Mask 3 Register (0x0A): WF3BM3
This register contains the last 16 bytes mask values of the Wake up frame 3 pattern. Setting bit 0 selects the 49th byte
of the Wake up frame 3. Setting bit 15 selects the 64th byte of the Wake up frame 3.
TABLE 4-46: BANK 7 WAKEUP FRAME 3 BYTE MASK 3 REGISTER (0X0A)
Bit
Default Value
R/W
Description
WF3BM3
Wake up Frame 3 Byte Mask 3.
The last 16 bytes mask covering bytes 49 to 64 of a Wake up frame
3 pattern.
15 - 0
0
R/W
Bank 8 - 15: Reserved
Except Bank Select Register (0xE).
Bank 16 Transmit Control Register (0x00): TXCR
This register holds control information programmed by the CPU to control the QMU transmit module function.
TABLE 4-47: BANK 16 TRANSMIT CONTROL REGISTER (0X00)
Bit
Default Value
R/W
Description
15
—
RO
R/W
RO
Reserved
Reserved
Reserved
14 - 13 0x0
12 - 4
—
TXFCE Transmit Flow Control Enable
When this bit is set and the KSZ8841M is in full-duplex mode, flow
control is enabled. The KSZ8841M transmits a PAUSE frame when
the Receive Buffer capacity reaches a threshold level that will
cause the buffer to overflow.
3
0x0
R/W
When this bit is set and the KSZ8841M is in half-duplex mode,
back-pressure flow control is enabled. When this bit is cleared, no
transmit flow control is enabled.
TXPE Transmit Padding Enable
When this bit is set, the KSZ8841M automatically adds a padding
field to a packet shorter than 64 bytes.
Note: Setting this bit requires enabling the add CRC feature to
avoid CRC errors for the transmit packet.
2
1
0
0x0
0x0
0x0
R/W
R/W
R/W
TXCE Transmit CRC Enable
When this bit is set, the KSZ8841M automatically adds a CRC
checksum field to the end of a transmit frame.
TXE Transmit Enable
When this bit is set, the transmit module is enabled and placed in a
running state. When reset, the transmit process is placed in the
stopped state after the transmission of the current frame is com-
pleted.
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Bank 16 Transmit Status Register (0x02): TXSR
This register keeps the status of the last transmitted frame.
TABLE 4-48: BANK 16 TRANSMIT STATUS REGISTER (0X02)
Bit
Default Value
R/W
Description
15
0x0
0x0
RO
Reserved
TXUR Transmit Underrun
This bit is set when underrun occurs.
Note: This is a fatal status. Software should guarantee that no
underrun condition occurred when enabling the early transmit func-
tion. The system or the QMU requires a reset or restart to recover
from an underrun condition.
14
RO
To aviod transmit underun condition, the user has to make sure that
the host interface speed (bandwidth) is faster than the ethernet
port.
TXLC Transmit Late Collision
This bit is set when a transmit Late Collision occurs.
13
0x0
RO
TXMC Transmit Maximum Collision
This bit is set when a transmit Maximum Collision is reached.
12
0x0
—
RO
RO
11 - 6
Reserved
TXFID Transmit Frame ID
5 - 0
—
RO
This field identifies the transmitted frame. All of the transmit status
information in this register belongs to the frame with this ID.
Bank 16 Receive Control Register (0x04): RXCR
This register holds control information programmed by the CPU to control the receive function.
TABLE 4-49: BANK 16 RECEIVE CONTROL REGISTER (0X04)
Bit
Default Value
R/W
Description
15 - 11
—
RO
Reserved
RXFCE Receive Flow Control Enable
When this bit is set and the KSZ8841M is in full-duplex mode, flow
control is enabled, and the KSZ8841M will acknowledge a PAUSE
frame from the receive interface; i.e., the outgoing packets are
pending in the transmit buffer until the PAUSE frame control timer
expires. This field has no meaning in half-duplex mode and should
be programmed to 0.
10
0x0
R/W
R/W
When this bit is cleared, flow control is not enabled.
RXEFE Receive Error Frame Enable
When this bit is set, CRC error frames are allowed to be received
into the RX queue.
9
0x0
When this bit is cleared, all CRC error frames are discarded.
8
7
—
RO
Reserved
RXBE Receive Broadcast Enable
When this bit is set, the RX module receives all the broadcast
frames.
0x0
R/W
RXME Receive Multicast Enable
6
5
0x0
0x0
R/W
R/W
When this bit is set, the RX module receives all the multicast
frames (including broadcast frames).
RXUE Receive Unicast
When this bit is set, the RX module receives unicast frames that
match the 48-bit Station MAC address of the module.
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TABLE 4-49: BANK 16 RECEIVE CONTROL REGISTER (0X04) (CONTINUED)
Bit
Default Value
R/W
Description
RXRA Receive All
4
0x0
0x0
R/W
When this bit is set, the KSZ8841M receives all incoming frames,
regardless of the frame’s destination address.
RXSCE Receive Strip CRC
When this bit is set, the KSZ8841M strips the CRC on the received
frames. Once cleared, the CRC is stored in memory following the
packet.
3
R/W
QMU Receive Multicast Hash-Table Enable
2
1
0x0
—
R/W
RO
When this bit is set, this bit enables the RX function to receive mul-
ticast frames that pass the CRC Hash filtering mechanism.
Reserved
RXE Receive Enable
When this bit is set, the RX block is enabled and placed in a run-
ning state.
0
0x0
R/W
When this bit is cleared, the receive process is placed in the
stopped state upon completing reception of the current frame.
Bank 16 TXQ Memory Information Register (0x08): TXMIR
This register indicates the amount of free memory available in the TXQ of the QMU module.
TABLE 4-50: BANK 16 TXQ MEMORY INFORMATION REGISTER (0X08)
Bit
Default Value
R/W
Description
15 - 13
—
—
RO
Reserved
TXMA Transmit Memory Available
The amount of memory available is represented in units of byte.
The TXQ memory is used for both frame payload, control word.
Note: Software must be written to ensure that there is enough
memory for the next transmit frame including control information
before transmit data is written to the TXQ.
12 - 0
RO
Bank 16 RXQ Memory Information Register (0x0A): RXMIR
This register indicates the amount of receive data available in the RXQ of the QMU module.
TABLE 4-51: BANK 16 RXQ MEMORY INFORMATION REGISTER (0X0A)
Bit
Default Value
R/W
Description
15 - 13
—
—
RO
Reserved
RXMA Receive Packet Data Available
The amount of Receive packet data available is represented in
units of byte. The RXQ memory is used for both frame payload, sta-
tus word. There is total 4096 bytes in RXQ. This counter will update
after a complete packet is received and also issues an interrupt
when receive interrupt enable IER[13] in Bank 18 is set.
Note: Software must be written to empty the RXQ memory to allow
for the new RX frame. If this is not done, the frame may be dis-
carded as a result of insufficient RXQ memory.
12 - 0
RO
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Bank 17 TXQ Command Register (0x00): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in
the TXQ memory is queued for transmit.
TABLE 4-52: BANK 17 TXQ COMMAND REGISTER (0X00)
Bit
Default Value
R/W
Description
15 - 1
—
RO
Reserved
TXETF Enqueue TX Frame
When this bit is written as 1, the current TX frame prepared in the
TX buffer is queued for transmit.
Note: This bit is self-clearing after the frame is finished transmitting.
The software should wait for the bit to be cleared before setting up
another new TX frame.
0
0x0
R/W
Bank 17 RXQ Command Register (0x02): RXQCR
This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ
frame buffer is read only by the host and the memory space is released.
TABLE 4-53: BANK 17 RXQ COMMAND REGISTER (0X02)
Bit
Default Value
R/W
Description
15 - 1
—
RO
Reserved
RXRRF Release RX Frame
When this bit is written as 1, the current RX frame buffer is
released.
Note: This bit is self-clearing after the frame memory is released.
The software should wait for the bit to be cleared before processing
new RX frame.
0
0x0
R/W
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO incre-
ment is set, It will automatically increment the pointer value on Write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
TABLE 4-54: BANK 17 TX FRAME DATA POINTER REGISTER (0X04)
Bit
Default Value
R/W
Description
15
—
RO
Reserved
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments
automatically on accesses to the data register. The increment is by
one for every byte access, by two for every word access, and by
four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually con-
trolled by user to access the TX frame location.
14
0x0
—
R/W
13 - 11
RO
Reserved
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX
Frame Data has been enqueued through the TXQ command regis-
ter.
10 - 0 0x000
R/W
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Bank 17 RX Frame Data Pointer Register (0x06): RXFDPR
The value of this register determines the address to be accessed within the RXQ frame buffer. When the Auto Increment
is set, it will automatically increment the RXQ Pointer on read accesses to the data register.
The counter is incremented is by one for every byte access, by two for every word access, and by four for every double
word access.
TABLE 4-55: BANK 17 RX FRAME DATA POINTER REGISTER (0X06)
Bit
Default Value
R/W
Description
15
—
RO
Reserved
RXFPAI RX Frame Pointer Auto Increment
When this bit is set, the RXQ Address register increments automat-
ically on accesses to the data register. The increment is by one for
every byte access, by two for every word access, and by four for
every double word access.
When this bit is reset, the RX frame data pointer is manually con-
trolled by user to access the RX frame location.
14
0x0
—
R/W
13 - 11
RO
Reserved
RXFP RX Frame Pointer
RX Frame data pointer index to the Data register for access.
This field reset to next available RX frame location when RX Frame
release command is issued (through the RXQ command register).
10 - 0 0x000
R/W
Bank 17 QMU Data Register Low (0x08): QDRL
This register QDRL(0x08-0x09) contains the Low data word presently addressed by the pointer register. Reading maps
from the RXQ, and writing maps to the TXQ.
TABLE 4-56: BANK 17 QMU DATA REGISTER LOW (0X08)
Bit
Default Value
R/W
Description
QDRL Queue Data Register Low
This register is mapped into two uni-directional buffers for 16-bit
buses, and one uni-directional buffer for 32-bit buses, (TXQ when
Write, RXQ when Read) that allow moving words to and from the
KSZ8841M regardless of whether the pointer is even, odd, or
Dword aligned. Byte, word, and Dword access can be mixed on the
fly in any order. This register along with DQRH is mapped into two
consecutive word locations for 16-bit buses, or one word location
for 32-bit buses, to facilitate Dword move operations.
15 - 0
—
R/W
Bank 17 QMU Data Register High (0x0A): QDRH
This register QDRH(0x0A-0x0B) contains the High data word presently addressed by the pointer register. Reading
maps from the RXQ, and writing maps to the TXQ.
TABLE 4-57: BANK 17 QMU DATA REGISTER HIGH (0X0A)
Bit
Default Value
R/W
Description
QDRL Queue Data Register High
This register is mapped into two uni-directional buffers for 16-bit
buses, and one uni-directional buffer for 32-bit buses, (TXQ when
Write, RXQ when Read) that allow moving words to and from the
KSZ8841M regardless of whether the pointer is even, odd, or
Dword aligned. Byte, word, and Dword access can be mixed on the
fly in any order. This register along with DQRL is mapped into two
consecutive word locations for 16-bit buses, or one word location
for 32-bit buses, to facilitate Dword move operations.
15 - 0
—
R/W
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Bank 18 Interrupt Enable Register (0x00): IER
This register enables the interrupts from the QMU and other sources.
TABLE 4-58: BANK 18 INTERRUPT ENABLE REGISTER (0X00)
Bit
Default Value
R/W
Description
LCIE Link Change Interrupt Enable
15
0x0
0x0
0x0
0x0
0x0
0x0
R/W
When this bit is set, the link change interrupt is enabled.
When this bit is reset, the link change interrupt is disabled.
TXIE Transmit Interrupt Enable
When this bit is set, the transmit interrupt is enabled.
When this bit is reset, the transmit interrupt is disabled.
14
13
12
11
10
R/W
R/W
R/W
R/W
R/W
RXIE Receive Interrupt Enable
When this bit is set, the receive interrupt is enabled.
When this bit is reset, the receive interrupt is disabled.
TXUIE Transmit Underrun Interrupt Enable
When this bit is set, the transmit underrun interrupt is enabled.
When this bit is reset, the transmit underrun interrupt is disabled.
RXOIE Receive Overrun Interrupt Enable
When this bit is set, the Receive Overrun interrupt is enabled.
When this bit is reset, the Receive Overrun interrupt is disabled.
RXEIE Receive Early Receive Interrupt Enable
When this bit is set, the Early Receive interrupt is enabled.
When this bit is reset, the Early Receive interrupt is disabled.
TXPSIE Transmit Process Stopped Interrupt Enable
When this bit is set, the Transmit Process Stopped interrupt is
enabled.
When this bit is reset, the Transmit Process Stopped interrupt is
disabled.
9
8
0x0
0x0
R/W
R/W
RXPSIE Receive Process Stopped Interrupt Enable
When this bit is set, the Receive Process Stopped interrupt is
enabled.
When this bit is reset, the Receive Process Stopped interrupt is dis-
abled.
RXEFIE Receive Error Frame Interrupt Enable
7
0x0
—
R/W
RO
When this bit is set, the Receive error frame interrupt is enabled.
When this bit is reset, the Receive error frame interrupt is disabled.
6 - 0
Reserved
Bank 18 Interrupt Status Register (0x02): ISR
This register contains the status bits for all QMU and other interrupt sources.
When the corresponding enable bit is set, it causes the interrupt pin to be asserted.
This register is usually read by the host CPU and device drivers during interrupt service routine or polling. The register
bits are not cleared when read. The user has to write “1” to clear.
TABLE 4-59: BANK 18 INTERRUPT STATUS REGISTER (0X02)
Bit
Default Value
R/W
Description
LCIS Link Change Interrupt Status
When this bit is set, it indicates that the link status has changed
RO
15
0x0
(W1C) from link up to link down, or link down to link up.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
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TABLE 4-59: BANK 18 INTERRUPT STATUS REGISTER (0X02) (CONTINUED)
Bit
Default Value
R/W
Description
TXIS Transmit Status
When this bit is set, it indicates that the TXQ MAC has transmitted
at least a frame on the MAC interface and the QMU TXQ is ready
for new frames from the host.
RO
(W1C)
14
0x0
0x0
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXIS Receive Interrupt Status
When this bit is set, it indicates that the QMU RXQ has received a
frame from the MAC interface and the frame is ready for the host
CPU to process.
RO
(W1C)
13
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXUIS Transmit Underrun Interrupt Status
RO
When this bit is set, it indicates that the transmit underrun condition
12
11
10
9
0x0
0x0
0x0
0x0
0x0
(W1C) has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXOIS Receive Overrun Interrupt Status
When this bit is set, it indicates that the Receive Overrun status has
RO
(W1C) occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXEIS Receive Early Receive Interrupt Status
When this bit is set, it indicates that the Early Receive status has
RO
(W1C) occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
TXPSIE Transmit Process Stopped Status
When this bit is set, it indicates that the Transmit Process has
RO
(W1C) stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXPSIE Receive Process Stopped Status
When this bit is set, it indicates that the Receive Process has
RO
8
(W1C) stopped.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
RXEFIE Receive Error Frame Interrupt Status
RO
When this bit is set, it indicates that the Receive error frame status
7
0x0
—
(W1C) has occurred.
This edge-triggered interrupt status is cleared by writing 1 to this bit.
Reserved
6 - 0
RO
Bank 18 Receive Status Register (0x04): RXSR
This register indicates the status of the current received frame and mirrors the Receive Status word of the Receive
Frame in the RXQ.
TABLE 4-60: BANK 18 RECEIVE STATUS REGISTER (0X04)
Bit
Default Value
R/W
Description
RXFV Receive Frame Valid
When set, it indicates that the present frame in the receive packet
memory is valid. The status information currently in this location is
also valid.
15
—
RO
When clear, it indicates that there is either no pending receive
frame or that the current frame is still in the process of receiving.
14 - 8
7
—
—
RO
RO
Reserved
RXBF Receive Broadcast Frame
When set, it indicates that this frame has a broadcast address.
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TABLE 4-60: BANK 18 RECEIVE STATUS REGISTER (0X04) (CONTINUED)
Bit
Default Value
R/W
Description
RXMF Receive Multicast Frame
6
—
—
—
RO
When set, it indicates that this frame has a multicast address
(including the broadcast address).
RXUF Receive Unicast Frame
When set, it indicates that this frame has a unicast address.
5
4
RO
RO
RXMR Receive MII Error
When set, it indicates that there is an MII symbol error on the
received frame.
RXFT Receive Frame Type
When set, it indicates that the frame is an Ethernet-type frame
(frame length is greater than 1500 bytes).
When clear, it indicate that the frame is an IEEE 802.3 frame.
This bit is not valid for runt frames.
3
2
—
—
RO
RO
RXTL Receive Frame Too Long
When set, it indicates that the frame length exceeds the maximum
size of 1916 bytes. Frames that are too long are passed to the host
only if the pass bad frame bit is set (bit 9 in RXCR register).
Note: Frame too long is only a frame length indication and does not
cause any frame truncation.
RXRF Receive Runt Frame
When set, it indicates that a frame was damaged by a collision or
premature termination before the collision window has passed.
Runt frames are passed to the host only if the pass bad frame bit is
set (bit 9 in RXCR register).
1
0
—
—
RO
RO
RXCE Receive CRC Error
When set, it indicates that a CRC error has occurred on the current
received frame. A CRC error frame is passed to the host only if the
pass bad frame bit is set (bit 9 in RXCR register)
Bank 18 Receive Byte Count Register (0x06): RXBC
This register indicates the status of the current received frame and mirrors the Receive Byte Count word of the Receive
Frame in the RXQ.
TABLE 4-61: BANK 18 RECEIVE BYTE COUNT REGISTER (0X06)
Bit
Default Value
R/W
Description
15 - 11
—
—
RO
Reserved
RXBX Receive Byte Count
Receive byte count.
10 - 0
RO
Bank 18 Early Transmit Register (0x08): ETXR
This register specifies the threshold for the early transmit.
TABLE 4-62: BANK 18 EARLY TRANSMIT REGISTER (0X08): ETXR
Bit
Default Value
R/W
Description
15 - 8
—
RO
Reserved
TXEE Early Transmit Enable
7
0x0
—
R/W
RO
When this bit is set, the Early Transmit function is enabled.
When this bit is cleared, normal operation is assumed.
6- 5
Reserved
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TABLE 4-62: BANK 18 EARLY TRANSMIT REGISTER (0X08): ETXR (CONTINUED)
Bit
Default Value
R/W
Description
ETXTH Early Transmit Threshold
The threshold for Early Transmit. Specified in unit of 64-byte.
Whenever the number of bytes written in memory for the presently
transmitting packet exceeds the threshold, Early Transmit will be
started on the network interface.
4 - 0
0x00
R/W
When early transmit is enabled, setting this field to 0 is invalid, and
the hardware behavior is unknown.
Bank 18 Early Receive Register (0x0A): ERXR
This register specify the threshold for early receive and interrupt condition.
TABLE 4-63: BANK 18 EARLY RECEIVE REGISTER (0X0A)
Bit
Default Value
R/W
Description
15 - 8
—
RO
Reserved
RXEE Early Receive Enable
7
0x0
—
R/W
RO
When this bit is set, the Early Receive function is enabled.
When this bit is cleared, normal operation is assumed.
6 - 5
Reserved
ERXTH Early Receive Threshold
The threshold for Early Receive and Interrupt. Specified in unit of
64-byte. Whenever the number of bytes written in memory for the
presently received packet exceeds the threshold, early receive sta-
tus will be set, and Early Receive interrupt will be asserted if its
interrupt is enabled.
4 - 0
0x1F
R/W
When early receive is enabled, setting this field to 0 is invalid, and
the hardware behavior is unknown.
Bank 19 Multicast Table Register 0 (0x00): MTR0
The 64-bit multicast table is used for group address filtering. This value is defined as the six most significant bits from
CRC circuit calculation result that is based on 48-bit of DA input. The two most significant bits select one of the four
registers to be used, while the others determine which bit within the register.
TABLE 4-64: BANK 19 MULTICAST TABLE REGISTER 0 (0X00)
Bit
Default Value
R/W
Description
MTR0 Multicast Table 0
When the appropriate bit is set, if the packet received with DA
matches the CRC, the hashing function is received without being fil-
tered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit
is set in the RXCR, all multicast addresses are received regardless
of the multicast table value.
15 - 0 0x0
R/W
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Bank 19 Multicast Table Register 1 (0x02): MTR1
TABLE 4-65: BANK 19 MULTICAST TABLE REGISTER 1 (0X02)
Bit
Default Value
R/W
Description
MTR0 Multicast Table 1
When the appropriate bit is set, if the packet received with DA
matches the CRC, the hashing function is received without being fil-
tered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit
is set in the RXCR, all multicast addresses are received regardless
of the multicast table value.
15 - 0 0x0
R/W
Bank 19 Multicast Table Register 2 (0x04): MTR2
TABLE 4-66: BANK 19 MULTICAST TABLE REGISTER 2 (0X04)
Bit
Default Value
R/W
Description
MTR0 Multicast Table 2
When the appropriate bit is set, if the packet received with DA
matches the CRC, the hashing function is received without being fil-
tered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit
is set in the RXCR, all multicast addresses are received regardless
of the multicast table value.
15 - 0 0x0
R/W
Bank 19 Multicast Table Register 3 (0x06): MTR3
TABLE 4-67: BANK 19 MULTICAST TABLE REGISTER 3 (0X06)
Bit
Default Value
R/W
Description
MTR0 Multicast Table 3
When the appropriate bit is set, if the packet received with DA
matches the CRC, the hashing function is received without being fil-
tered.
When the appropriate bit is cleared, the packet will drop.
Note: When the receive all (RXRA) or receive multicast (RXRM) bit
is set in the RXCR, all multicast addresses are received regardless
of the multicast table value.
15 - 0 0x0
R/W
Bank 19 Power Management Control and Status Register (0x08): PMCS
The following control and status register provides information on the KSZ8841M power management capabilities. The
following table shows the register bit fields.
TABLE 4-68: BANK 19 POWER MANAGEMENT CONTROL AND STATUS REGISTER (0X08)
Bit
Default Value
R/W
Description
PME_Status
This bit indicates that the KSZ8841M has detected a power-man-
agement event. If bit PME_Enable is set, the KSZ8841M also
(W1C) asserts the PMEN pin. This bit is cleared on power-up reset or by
write 1. It is not modified by either hardware or software reset.
When this bit is cleared, the KSZ8841M deasserts the PMEN pin.
RO
15
0
14 - 9 0x00
RO
Reserved
PME_Enable
If this bit is set, the KSZ8841M can assert the PMEN pin. Other-
wise, assertion of the PMEN pin is disabled.
This bit is cleared on power-up reset and will be not modified by
software reset.
8
0
R/W
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TABLE 4-68: BANK 19 POWER MANAGEMENT CONTROL AND STATUS REGISTER (0X08)
Bit
Default Value
R/W
Description
7 - 4
0x0
RO
Reserved
No Soft Reset
If this bit is set (“1”), the KSZ8841M does not perform an internal
reset when transitioning from D3_hot to D0 because of PowerState
commands. Configuration context is preserved. Upon transition
from D3_hot to the D0 Initialized state, no additional operating sys-
tem intervention is required to preserve configuration context
beyond writing the PowerState bits.
If this bit is cleared (“0”), the KSZ8841M does perform an internal
reset when transitioning from D3_hot to D0 via software control of
the PowerState bits. Configuration context is lost when performing
the soft reset. Upon transition from D3_hot to the D0 state, full reini-
tialization sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3_hot to D0 by
a system or bus segment reset will return to the device state D0
Uninitialized with only PME context preserved if PME is supported
and enabled.
3
0
RO
The value of this bit is loaded from the NO_SRST bit in the serial
EEPROM.
2
0
RO
Reserved
Power State
This field is used to set the new power state of the KSZ8841M as
well as to determine its current power state. The definitions of the
field values are:
00 = D0 -> System is on and running
01 = D1 -> Low-power state
1 - 0
0x0
R/W
10 = D2 -> Low-power state
11 = D3 (hot) -> System is off and not running
Banks 20 – 31: Reserved
Except Bank Select Register (0xE).
Bank 32 Chip ID and Enable Register (0x00): CIDER
This register contains the chip ID and the chip enable bit.
TABLE 4-69: BANK 32 CHIP ID AND ENABLE REGISTER (0X00)
Bit
Default Value
R/W
Description
Family ID
Chip family ID
15 - 8 0x88
RO
Chip ID
0x1 is assigned to KSZ8841M
7 - 4
0x1
RO
3 - 1
0
0x1
0
RO
RO
Revision ID
Reserved
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Bank 32 Chip Global Control Register (0x0A): CGCR
This register contains the global control for the chip function.
TABLE 4-70: BANK 32 CHIP GLOBAL CONTROL REGISTER (0X0A)
Bit
Default Value
R/W
Description
LEDSEL1
See description for bit 9.
15
0
0
R/W
14 - 12
R/W
R/W
Reserved
Reserved
LEDSEL0
11 - 10 0x2
This register bit sets the LEDSEL0 selection only.
Port 1 LED indicators, defined as below:
[LEDSEL1, LEDSEL0]
[0, 0]
[0, 1]
P1LED3
P1LED2
P1LED1
P1LED0
—
—
Link/Activity
Full-Duplex/Col
Speed
100Link/Activity
10Link/Activity
Full-Duplex
9
0
R/W
[LEDSEL1, LEDSEL0]
[1, 0]
[1, 1]
—
P1LED3
P1LED2
P1LED1
P1LED0
Reserved
Reserved
Activity
Link
—
Full-Duplex/Col
Speed
—
—
8
0
R/W
R/W
7 - 0
0x35
Banks 33 – 41: Reserved
Except Bank Select Register (0xE)
Bank 42 Indirect Access Control Register (0x00): IACR
This register contains the indirect control for the MIB counter (Write IACR triggers a command. Read or write access is
determined by register bit 12).
TABLE 4-71: BANK 42 INDIRECT ACCESS CONTROL REGISTER (0X00)
Bit
Default Value
R/W
Description
15 - 13 0x0
R/W
R/W
Reserved
12
0
Read High. Write Low
1 = Read cycle.
0 = Write cycle.
11 - 10 0x0
R/W
R/W
Table Select
00 = Reserved.
01 = Reserved.
10 = Reserved.
11 = MIB counter selected.
9 - 0
0x000
Indirect Address
Bit 9-0 of indirect address.
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Bank 42 Indirect Access Data Register 1 (0x02): IADR1
This register contains the indirect data for the chip function.
TABLE 4-72: BANK 42 INDIRECT ACCESS DATA REGISTER 1 (0X02)
Bit
Default Value
R/W
Description
15 - 0 0x0000
RO
Reserved
Bank 42 Indirect Access Data Register 2 (0x04): IADR2
This register contains the indirect data for the chip function.
TABLE 4-73: BANK 42 INDIRECT ACCESS DATA REGISTER 2 (0X04)
Bit
Default Value
R/W
Description
15 - 0 0x0000
RO
Reserved
Bank 42 Indirect Access Data Register 3 (0x06): IADR3
This register contains the indirect data for the chip function.
TABLE 4-74: BANK 42 INDIRECT ACCESS DATA REGISTER 3 (0X06)
Bit
Default Value
R/W
Description
15 - 0 0x0000
RO
Reserved
Bank 42 Indirect Access Data Register 4 (0x08): IADR4
This register contains the indirect data for the chip function.
TABLE 4-75: BANK 42 INDIRECT ACCESS DATA REGISTER 4 (0X08)
Bit
Default Value
R/W
Description
Indirect Data
Bit 15-0 of indirect data.
15 - 0 0x0000
R/W
Bank 42 Indirect Access Data Register 5 (0x0A): IADR5
This register contains the indirect data for the chip function.
TABLE 4-76: BANK 42 INDIRECT ACCESS DATA REGISTER 5 (0X0A)
Bit
Default Value
R/W
Description
Indirect Data
Bit 31-16 of indirect data.
15 - 0 0x0000
R/W
Bank 43– 44: Reserved
Except Bank Select Register (0xE)
Bank 45 PHY 1 MII-Register Basic Control Register (0x00): P1MBCR
This register contains Media Independent Interface (MII) register for port 1 as defined in the IEEE 802.3 specification.
TABLE 4-77: BANK 45 PHY 1 MII-REGISTER BASIC CONTROL REGISTER (0X00)
Bit
Default Value
R/W
Description
Bit Same As
Soft reset
Not supported.
15
14
0
RO
—
—
0
0
R/W
Reserved
Force 100
13
12
R/W
R/W
1 = Force 100Mbps if AN is disabled (bit 12)
0 = Force 10Mbps if AN is disabled (bit 12)
Bank49 0x2 bit6
Bank49 0x2 bit7
AN Enable
1 = Auto-negotiation enabled.
0 = Auto-negotiation disabled.
1
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TABLE 4-77: BANK 45 PHY 1 MII-REGISTER BASIC CONTROL REGISTER (0X00) (CONTINUED)
Bit
Default Value
R/W
Description
Bit Same As
Power-Down
1 = Power-down.
0 = Normal operation.
Bank49 0x2
bit11
11
0
R/W
Isolate
Not supported.
10
9
0
0
RO
—
Restart AN
1 = Restart auto-negotiation.
0 = Normal operation.
Bank49 0x2
bit13
R/W
Force Full Duplex
1 = Force full-duplex
0 = Force half-duplex.
8
0
R/W
Bank49 0x2 bit5
If AN is disabled (bit 12) or AN is enabled but failed.
Collision test
Not supported.
7
6
0
0
RO
RO
—
—
Reserved
HP_mdix
1 = HP Auto MDI-X mode.
0 = Microchip Auto MDI-X mode.
Bank49 0x4
bit15
5
4
1
0
R/W
R/W
Force MDI-X
1 = Force MDI-X.
0 = Normal operation.
Bank49 0x2 bit9
Disable MDI-X
1 = Disable auto MDI-X.
0 = Normal operation.
Bank49 0x2
bit10
3
2
1
0
0
0
R/W
R/W
R/W
Bank49 0x2
bit12
Reserved
Disable Transmit
1 = Disable transmit.
0 = Normal operation.
Bank49 0x2
bit14
Disable LED
1 = Disable LED.
0 = Normal operation.
Bank49 0x2
bit15
0
0
R/W
Bank 45 PHY 1 MII-Register Basic Status Register (0x02): P1MBSR
This register contains the MII register status for the chip function.
TABLE 4-78: BANK 45 PHY 1 MII-REGISTER BASIC STATUS REGISTER (0X02)
Bit
Default Value
R/W
Description
Bit Same As
T4 Capable
15
0
RO
1 = 100BASE-T4 capable.
—
0 = not 100BASE-T4 capable.
100 Full Capable
14
13
12
1
1
1
RO
RO
RO
1 = 100BASE-TX full-duplex capable.
0 = Not 100BASE-TX full-duplex.capable.
—
—
—
100 Half Capable
1= 100BASE-TX half-duplex capable.
0= Not 100BASE-TX half-duplex capable.
10 Full Capable
1 = 10BASE-T full-duplex capable.
0 = Not 10BASE-T full-duplex capable.
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TABLE 4-78: BANK 45 PHY 1 MII-REGISTER BASIC STATUS REGISTER (0X02) (CONTINUED)
Bit
Default Value
R/W
Description
Bit Same As
10 Half Capable
11
1
RO
1 = 10BASE-T half-duplex capable.
—
0 = Not 10BASE-T half-duplex capable.
10 - 7
6
0
0
RO
RO
Reserved
—
—
Preamble suppressed
Not supported.
AN Complete
5
4
3
0
0
1
RO
RO
RO
1 = Auto-negotiation complete.
0 = Auto-negotiation not completed.
Bank49 0x4 bit6
Bank49 0x4 bit8
—
Reserved
AN Capable
1 = Auto-negotiation capable.
0 = Not auto-negotiation capable.
Link Status
2
1
0
0
0
0
RO
RO
RO
1 = Link is up.
0 = Link is down.
Bank49 0x4 bit5
Jabber test
Not supported.
—
—
Extended Capable
1 = Extended register capable.
0 = Not extended register capable.
Bank 45 PHY 1 PHYID Low Register (0x04): PHY1ILR
This register contains the PHY ID (low) for the chip.
TABLE 4-79: BANK 45 PHY 1 PHYID LOW REGISTER (0X04)
Bit
Default Value
R/W
Description
PHYID Low
Low order PHYID bits.
15 - 0 0x1430
RO
Bank 45 PHY 1 PHYID High Register (0x06): PHY1IHR
This register contains the PHY ID (high) for the chip.
TABLE 4-80: BANK 45 PHY 1 PHYID HIGH REGISTER (0X06)
Bit
Default Value
R/W
Description
PHYID High
High order PHYID bits.
15 - 0 0x0022
RO
Bank 45 PHY 1 Auto-Negotiation Advertisement Register (0x08): P1ANAR
This register contains the auto-negotiation advertisement for the PHY function.
TABLE 4-81: BANK 45 PHY 1 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (0X08)
Bit
Default Value
R/W
Description
Bit Same As
Next page
Not supported.
15
14
0
RO
RO
RO
RO
—
—
—
—
0
0
0
Reserved
Remote fault
Not supported.
13
12 - 11
Reserved
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TABLE 4-81: BANK 45 PHY 1 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (0X08)
Bit
Default Value
R/W
Description
Bit Same As
Pause (flow control capability)
10
9
1
R/W
R/W
R/W
1 = Advertise pause capability.
0 = Do not advertise pause capability.
Bank49 0x2 bit4
—
0
1
Reserved
Adv 100 Full
1 = Advertise 100 full-duplex capability.
0 = Do not advertise 100 full-duplex capability
8
Bank49 0x2 bit3
Adv 100 Half
7
6
1
1
R/W
R/W
1= Advertise 100 half-duplex capability.
0 = Do not advertise 100 half-duplex capability.
Bank49 0x2 bit2
Bank49 0x2 bit1
Adv 10 Full
1 = Advertise 10 full-duplex capability.
0 = Do not advertise 10 full-duplex capability.
Adv 10 Half
5
1
R/W
RO
1 = Advertise 10 half-duplex capability.
0 = Do not advertise 10 half-duplex capability.
Bank49 0x2 bit0
—
Selector Field
802.3
4 - 0
0x01
Bank 45 PHY 1 Auto-Negotiation Link Partner Ability Register (0x0A): P1ANLPR
This register contains the auto-negotiation link partner ability for the chip function.
TABLE 4-82: BANK 45 PHY 1 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (0X0A)
Bit
Default Value
R/W
Description
Bit Same As
Next page
Not supported.
15
0
RO
—
LP ACK
Not supported.
14
0
RO
—
Remote fault
Not supported.
13
0
0
0
0
0
RO
RO
RO
RO
RO
—
12 - 11
Reserved
Pause
Link partner pause capability.
—
10
9
Bank49 0x4 bit4
—
Reserved
Adv 100 Full
Link partner 100 full capability.
8
Bank49 0x4 bit3
Adv 100 Half
Link partner 100 half capability.
7
6
0
0
RO
RO
Bank49 0x4 bit2
Bank49 0x4 bit1
Adv 10 Full
Link partner 10 full capability.
Adv 10 Half
Link partner 10 half capability.
5
0
RO
RO
Bank49 0x4 bit0
—
4 - 0
0x01
Reserved
Bank 46: Reserved
Except Bank Select Register (0xE)
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Bank 47 PHY1 LinkMD Control/Status (0x00): P1VCT
This register contains the LinkMD control and status information of PHY 1.
TABLE 4-83: BANK 47 PHY1 LINKMD CONTROL/STATUS (0X00): P1VCT
Bit
Default Value
R/W
Description
Bit Same As
Vct_enable
R/W
(Self-
1 = Cable diagnostic test is enabled. It is self-cleared after
the VCT test is done.
Bank49 0x0
bit 12
15
0
Clear) 0 = Indicates that the cable diagnostic test is completed
and the status information is valid for read.
Vct_result
[00] = Normal condition.
Bank49 0x0
bit 14 - 13
14 - 13
12
0
RO
[01] = Open condition detected in the cable.
[10] = Short condition detected in the cable.
[11] = Cable diagnostic test failed.
Vct 10M Short
1 = Less than 10m short.
Bank49 0x0
bit 15
—
RO
RO
11 - 9 0x0
8 - 0 0x000
Reserved
—
Vct_fault_count
Distance to the fault. The distance is approximately
0.4m*vct_fault_count.
Bank49 0x0
bit 8 - 0
RO
Bank 47 PHY1 Special Control/Status Register (0x02): P1PHYCTRL
This register contains the control and status information of PHY1.
TABLE 4-84: BANK 47 PHY1 SPECIAL CONTROL/STATUS REGISTER (0X02): P1PHYCTRL
Bit
Default Value
R/W
Description
Bit Same As
15 - 6 0x000
RO
Reserved
—
Polarity Reverse (polrvs)
1 = Polarity is reversed.
0 = Polarity is not reversed.
Bank49 0x04
bit 13
5
4
3
2
0
0
0
1
RO
RO
MDIX Status (mdix_st)
1 = MDI
0 = MDIX
Bank49 0x04
bit 7
Force Link (force_lnk)
1 = Force link pass.
0 = Normal operation.
Bank49 0x00
bit 11
R/W
R/W
Power Saving (pwrsave)
1 = Disable power saving.
0 = Enable power saving.
Bank49 0x00
bit 10
Remote (Near-end) Loopback (rlb)
1 = Perform remote loopback at PHY (RXP1/RXM1 ->
TXP1/TXM1, see Figure 12)
Bank49 0x00
bit 9
1
0
0
0
R/W
R/W
0 = Normal operation
Reserved
—
Bank 48: Reserved
Except Bank Select Register (0xE)
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Bank 49 Port 1 PHY Special Control/Status, LinkMD (0x00): P1SCSLMD
TABLE 4-85: BANK 49 PORT 1 PHY SPECIAL CONTROL/STATUS, LINKMD (0X00)
Bit
Default Value
R/W
Description
Bit Same As
Vct_10m_short
1 = Less than 10 meter short.
Bank 47 0x00
bit 12
15
0
RO
Vct_result
VCT result.
[00] = Normal condition.
Bank 47 0x00
bit 14 - 13
14 - 13
0
0
RO
[01] = Open condition has been detected in cable.
[10] = Short condition has been detected in cable.
[11] = Cable diagnostic test is failed.
Vct_en
Vct enable.
R/W
(Self-
Clear)
1 = The cable diagnostic test is enabled. It is self-cleared
after the VCT test is done.
0 = Indicates the cable diagnostic test is completed and
the status information is valid for read.
Bank 47 0x00
bit 15
12
Force_lnk
Force link.
1 = Force link pass.
0 = Normal operation.
Bank 47 0x02
bit 3
11
10
0
R/W
R/W
R/W
RO
pwrsave
Power-saving.
1 = Disable power saving.
0 = Enable power saving.
Bank 47 0x02
bit 2
1
Remote (Near-end) loopback (rlb)
1 = Perform remote loopback at PHY
(RXP1/RXM1 -> TXP1/TXM1, see Figure 12)
0 = Normal operation
Bank 47 0x02
bit 1
9
0
Vct_fault_count
VCT fault count.
Distance to the fault. It’s approximately
0.4m*vct_fault_count.
Bank 47 0x00
bit 8 - 0
8 - 0
0x000
Bank 49 Port 1 Control Register 4 (0x02): P1CR4
This register contains the global per port control for the chip function.
TABLE 4-86: BANK 49 PORT 1 CONTROL REGISTER 4 (0X02)
Bit
Default Value
R/W
Description
Bit Same As
LED Off
1 = Turn off all of the port 1 LEDs (P1LED3, P1LED2,
P1LED1, P1LED0). These pins are driven high if this bit is
set to one.
Bank 45 0x00
bit 0
15
0
R/W
0 = Normal operation.
Txids
Bank 45 0x00
bit 1
14
0
R/W
1 = Disable the port’s transmitter.
0 = Normal operation.
Restart AN
1 = Restart auto-negotiation.
0 = Normal operation.
Bank 45 0x00
bit 9
13
12
0
0
R/W
R/W
Bank 45 0x00
bit 2
Reserved
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TABLE 4-86: BANK 49 PORT 1 CONTROL REGISTER 4 (0X02) (CONTINUED)
Bit
Default Value
R/W
Description
Bit Same As
Power Down
1 = Power down.
0 = Normal operation.
Bank 45 0x00
bit 11
11
0
R/W
Disable auto MDI/MDI-X
1 = Disable auto MDI/MDI-X function.
0 = Enable auto MDI/MDI-X function.
Bank 45 0x00
bit 3
10
0
R/W
Force MDI-X
1= If auto MDI/MDI-X is disabled, force PHY into MDI-X
mode.
0 = Do not force PHY into MDI-X mode.
Bank 45 0x00
bit 4
9
8
7
0
0
1
R/W
R/W
R/W
Reserved
—
Auto-Negotiation Enable
1 = Auto-negotiation is enabled.
0 = Disable auto negotiation, speed, and duplex are
decided by bits 6 and 5 of the same register.
Bank 45 0x00
bit 12
Force Speed
1 = Force 100BT if AN is disabled (bit 7).
0 = Force 10BT if AN is disabled (bit 7).
Bank 45 0x00
bit 13
6
5
0
0
R/W
R/W
Force Duplex
1 = Force full-duplex if (1) AN is disabled or (2) AN is
enabled but failed.
0 = Force half-duplex if (1) AN is disabled or (2) AN is
enabled but failed.
Bank 45 0x00
bit 8
Advertised flow control capability.
1 = Advertise flow control (pause) capability.
0 = Suppress flow control (pause) capability from trans-
mission to link partner.
Bank 45 0x08
bit 10
4
3
2
1
0
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
Advertised 100BT full-duplex capability.
1 = Advertise 100BT full-duplex capability.
0 = Suppress 100BT full-duplex capability from transmis-
sion to link partner.
Bank 45 0x08
bit 8
Advertised 100BT half-duplex capability.
1 = Advertise 100BT half-duplex capability.
0 = Suppress 100BT half-duplex capability from transmis-
sion to link partner.
Bank 45 0x08
bit 7
Advertised 10BT full-duplex capability.
1 = Advertise 10BT full-duplex capability.
0 = Suppress 10BT full-duplex capability from transmis-
sion to link partner.
Bank 45 0x08
bit 6
Advertised 10BT half-duplex capability.
1 = Advertise 10BT half-duplex capability.
0 = Suppress 10BT half-duplex capability from transmis-
sion to link partner.
Bank 45 0x08
bit 5
2019 Microchip Technology Inc.
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KSZ8841-16M/-32M
Bank 49 Port 1 Status Register (0x04): P1SR
This register contains the global per port status for the chip function.
TABLE 4-87: BANK 49 PORT 1 STATUS REGISTER (0X04)
Bit
Default Value
R/W
Description
Same Bit As
HP_mdix
1 = HP Auto MDI-X mode.
0 = Microchip Auto MDI-X mode.
Bank 45 0x00
bit 5
15
14
13
1
R/W
RO
RO
0
0
Reserved
—
Polarity Reverse
1 = Polarity is reversed.
0 = Polarity is not reversed.
Bank 47 0x02
bit 5
Receive Flow Control Enable
12
11
10
0
0
0
RO
RO
RO
1 = Receive flow control feature is active.
0 = Receive flow control feature is inactive.
—
—
—
—
Transmit Flow Control Enable
1 = Transmit flow control feature is active.
0 = Transmit flow control feature is inactive.
Operation Speed
1 = Link speed is 100 Mbps.
0 = Link speed is 10 Mbps.
Operation Duplex
1 = Link duplex is full.
0 = Link duplex is half.
9
8
7
0
0
0
RO
RO
RO
Bank 45 0x02
bit 4
Reserved
MDI-X status
1 = MDI.
0 = MDI-X.
Bank 47 0x02
bit 4
AN Done
1 = AN done.
0 = AN not done.
Bank 45 0x02
bit 5
6
5
4
3
2
1
0
0
0
0
0
0
0
0
RO
RO
RO
RO
RO
RO
RO
Link Good
1 = Link good.
0 = Link not good.
Bank 45 0x02
bit 2
Partner flow control capability.
1 = Link partner flow control (pause) capable.
0 = Link partner not flow control (pause) capable.
Bank 45 0x0A
bit 10
Partner 100BT full-duplex capability.
1 = Link partner 100BT full-duplex capable.
0 = Link partner not 100BT full-duplex capable.
Bank 45 0x0A
bit 8
Partner 100BT half-duplex capability.
1 = Link partner 100BT half-duplex capable.
0 = Link partner not 100BT half-duplex capable.
Bank 45 0x0A
bit 7
Partner 10BT full-duplex capability.
1 = Link partner 10BT full-duplex capable.
0 = Link partner not 10BT full-duplex capable.
Bank 45 0x0A
bit 6
Partner 10BT half-duplex capability.
1 = Link partner 10BT half-duplex capable.
0 = Link partner not 10BT half-duplex capable.
Bank 45 0x0A
bit 5
Banks 50 – 63: Reserved
Except Bank Select Register (0xE)
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KSZ8841-16M/-32M
4.3
Management Information Base (MIB) Counters
The KSZ8841M provides 32 MIB counters to monitor the port activity for network management. The MIB counters are
formatted as shown below.
TABLE 4-88: FORMAT OF MIB COUNTERS
Bit
Name
Overflow
R/W
Description
Default
31
RO
1 = Counter overflow.
0
0 = No counter overflow.
30
Count Valid
RO
RO
1 = Counter value is valid.
0 = Counter value is not valid.
0
29 - 0 Counter Values
Counter value (read clear)
0x00000000
Ethernet port MIB counters are read using indirect memory access. The address offset range is 0x00 to 0x1F.
TABLE 4-89: PORT 1 MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset
Counter Name
RxLoPriorityByte
Description
0x0
0x1
0x2
0x3
0x4
Rx lo-priority (default) octet count including bad packets
Reserved
Reserved
RxUndersizePkt
RxFragments
RxOversize
Rx undersize packets w/ good CRC
Rx fragment packets w/ bad CRC, symbol errors or alignment errors
Rx oversize packets w/ good CRC (max: 1536 bytes)
Rx packets longer than 1536 bytes w/ either CRC errors, alignment
errors, or symbol errors
0x5
0x6
0x7
RxJabbers
RxSymbolError
RxCRCError
Rx packets w/ invalid data symbol and legal packet size.
Rx packets within (64,1916) bytes w/ an integral number of bytes and
a bad CRC
Rx packets within (64,1916) bytes w/ a non-integral number of bytes
and a bad CRC
0x8
0x9
RxAlignmentError
RxControl8808Pkts
Number of MAC control frames received by a port with 88-08h in
EtherType field
Number of PAUSE frames received by a port. PAUSE frame is quali-
fied with EtherType (88-08h), DA, control opcode (00-01), data length
(64B min), and a valid CRC
0xA
RxPausePkts
Rx good broadcast packets (not including error broadcast packets or
valid multicast packets)
0xB
0xC
RxBroadcast
RxMulticast
Rx good multicast packets (not including MAC control frames, error
multicast packets or valid broadcast packets)
0xD
0xE
RxUnicast
Rx good unicast packets
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length
Total Rx packets (bad packets included) that are between 65 and 127
octets in length
0xF
0x10
0x11
0x12
0x13
Rx65to127Octets
Rx128to255Octets
Rx256to511Octets
Rx512to1023Octets
Rx1024to1522Octets
Total Rx packets (bad packets included) that are between 128 and
255 octets in length
Total Rx packets (bad packets included) that are between 256 and
511 octets in length
Total Rx packets (bad packets included) that are between 512 and
1023 octets in length
Total Rx packets (bad packets included) that are between 1024 and
1916 octets in length
0x14
0x15
TxLoPriorityByte
Reserved
Tx lo-priority good octet count, including PAUSE packets
Reserved
2019 Microchip Technology Inc.
DS00003147A-page 73
KSZ8841-16M/-32M
TABLE 4-89: PORT 1 MIB COUNTERS INDIRECT MEMORY OFFSETS (CONTINUED)
Offset
Counter Name
Description
The number of times a collision is detected later than 512 bit-times
into the Tx of a packet
0x16
0x17
0x18
TxLateCollision
TxPausePkts
Number of PAUSE frames transmitted by a port
Tx good broadcast packets (not including error broadcast or valid
multicast packets)
TxBroadcastPkts
Tx good multicast packets (not including error multicast packets or
valid broadcast packets)
0x19
0x1A
0x1B
TxMulticastPkts
TxUnicastPkts
TxDeferred
Tx good unicast packets
Tx packets by a port for which the 1st Tx attempt is delayed due to
the busy medium
0x1C
0x1D
TxTotalCollision
Tx total collision, half-duplex only
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
Successfully Tx frames on a port for which Tx is inhibited by exactly
one collision
0x1E
TxSingleCollision
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more
than one collision
0x1F
Example:
1. MIB Counter Read (read port 1 “Rx64Octets” counter at indirect address offset 0x0E)
Write to reg. IACR with 0x1C0E (set indirect address and trigger a read MIB counters operation)
Then
Read reg. IADR5 (MIB counter value 31-16) // If bit 31 = 1, there was a counter overflow
// If bit 30 = 0, restart (re-read) from this register
Read reg. IADR4 (MIB counter value 15-0)
4.3.1
ADDITIONAL MIB INFORMATION
In the heaviest condition, the byte counter will overflow in 2 minutes. It is recommended that the software read all the
counters at least every 30 seconds.
MIB counters are designed as “read clear”. That is, these counters will be cleared after they are read.
DS00003147A-page 74
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KSZ8841-16M/-32M
5.0
5.1
OPERATIONAL CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage
(VDDATX, VDDARX, VDDIO).......................................................................................................................... –0.5V to +4.0V
Input Voltage (all inputs)............................................................................................................................ –0.5V to +5.0V
Output Voltage (all outputs)....................................................................................................................... –0.5V to +4.0V
Lead Temperature (soldering, 10s) .......................................................................................................................+270°C
Storage Temperature (TS)......................................................................................................................–55°C to +150°C
*Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above
may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-
ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect
reliability. Unused inputs must always be tied to an appropriate logic voltage level.
5.2
Operating Ratings**
Supply Voltage
(VDDATX, VDDARX, VDDIO)..........................................................................................................................+3.1V to +3.5V
Ambient Operating Temperature for Commercial Options (TA)....................................................................0°C to +70°C
Ambient Operating Temperature for Industrial Options (TA) ....................................................................–40°C to +85°C
Maximum Junction Temperature (TJ)....................................................................................................................+125°C
Thermal Resistance (Note 5-1) (ΘJA) ........................................................................................................... +42.91°C/W
Thermal Resistance (Note 5-1) (ΘJC) ............................................................................................................. +19.6°C/W
**The device is not guaranteed to function outside its operating ratings. Unused inputs must always be tied to an appro-
priate logic voltage level (Ground to VDD).
Note 5-1
No heat spreader (HS) in this package. The ΘJC/ΘJA is under air velocity 0 m/s.
Note:
Do not drive input signals without power supplied to the device.
2019 Microchip Technology Inc.
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6.0
ELECTRICAL CHARACTERISTICS
TA = 25°C. Specification is for packaged product only. Single port’s transformer consumes an additional 45 mA @ 3.3V
for 100BASE-TX and 70 mA @ 3.3V for 10BASE-T.
TABLE 6-1:
ELECTRICAL CHARACTERISTICS
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
Supply Current for 100BASE-TX Operation (Single Port @ 100% Utilization)
100BASE-TX
(analog core + PLL +
digital core + transceiver +
digital I/O)
VDDATX, VDDARX, VDDIO = 3.3V;
Chip only (no transformer)
IDDXIO
—
100
—
mA
Supply Current for 10BASE-T Operation (Single Port @ 100% Utilization)
10BASE-T
(analog core + PLL +
digital core + transceiver +
digital I/O)
VDDATX, VDDARX, VDDIO = 3.3V;
Chip only (no transformer)
IDDXIO
—
85
—
mA
CMOS Inputs
Input High Voltage
Input Low Voltage
Input Current
VIH
VIL
IIN
2.0
—
—
—
—
—
0.8
10
V
V
—
—
–10
μA
VIN = GND ~ VDDIO
CMOS Outputs
Output High Voltage
Output Low Voltage
Output Tri-State Leakage
VOH
VOL
2.4
—
—
—
—
—
0.4
10
V
V
IOH = –8 mA
IOL = 8 mA
—
|IOZ
|
—
μA
100BASE-TX Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
100Ω termination across differential
output.
VO
±0.95
—
—
—
±1.05
2
V
Voltage
100Ω termination across differential
output.
Output Voltage Imbalance
VIMB
%
Rise/Fall Time
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
tr/tf
—
3
—
—
5
0.5
±0.25
5
ns
ns
ns
%
V
—
0
—
—
—
—
—
—
—
—
—
—
—
—
Reference Voltage of ISET
Output Jitter
VSET
—
0.5
0.7
—
1.4
ns
Peak-to-peak
10BASE-T Receive
Squelch Threshold
VSQ
—
400
—
mV
5 MHz square wave
10BASE-T Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
100Ω termination across differential
output.
VP
—
—
—
2.4
1.8
—
V
Voltage
Peak-to-peak, 100Ω termination
across differential output
Jitter Added
3.5
ns
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KSZ8841-16M/-32M
7.0
7.1
TIMING SPECIFICATIONS
Asynchronous Timing without using Address Strobe (ADSN = 0)
FIGURE 7-1:
ASYNCHRONOUS CYCLE – ADSN = 0
t2
valid
Addr, AEN, BExN
ADSN
t3
t4
Read Data
valid
t1
t5
RDN, WRN
Write Data
t6
valid
t7
ARDY
t9
(Read Cycle)
t8
ARDY
(Write Cycle)
t10
TABLE 7-1:
ASYNCHRONOUS CYCLE (ADSN = 0) TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
t1
t2
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
0
—
—
ns
A1-A15, AEN, BExN[3:0] hold after RDN inactive (assume ADSN tied
Low)
0
1
—
—
—
—
ns
A1-A15, AEN, BExN[3:0] hold after WRN inactive (assume ADSN
tied Low)
t3
t4
t5
t6
t7
t8
Read data valid to ARDY rising
Read data to hold RDN inactive
Write data setup to WRN inactive
Write data hold after WRN inactive
Read active to ARDY Low
—
4
—
—
—
—
—
—
0.8
—
—
—
8
ns
ns
ns
ns
ns
ns
4
2
—
—
Write inactive to ARDY Low
8
ARDY low (wait time) in read cycle (Note 7-1)
(It is 0 ns to read bank select register and 40 ns to read QMU data
register in turbo mode) (Note 7-2)
0
0
0
40
80
50
—
—
—
t9
ns
ARDY low (wait time) in read cycle (Note 7-1)
(It is 0 ns to read bank select register and 80 ns to read QMU data
register in normal mode)
ARDY low (wait time) in write cycle (Note 7-1)
(It is 0 ns to write bank select register)
(It is 36 ns to write QMU data register)
t10
ns
Note 7-1
When CPU finished current Read or Write operation, it can do next Read or Write operation even
the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/
WRN low until the ARDY returns to high.
Note 7-2
In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which
is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
2019 Microchip Technology Inc.
DS00003147A-page 77
KSZ8841-16M/-32M
7.2
Asynchronous Timing using Address Strobe (ADSN)
FIGURE 7-2:
ASYNCHRONOUS CYCLE – USING ADSN
t8
valid
t6
Addr, AEN, BExN
ADSN
valid
Read Data
t1
t4
t3
t5
RDN, WRN
Write Data
valid
t2
t7
ARDY
(Read Cycle)
t10
t9
ARDY
(Write Cycle)
t11
TABLE 7-2:
ASYNCHRONOUS CYCLE USING ADSN TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
t1
t2
t3
t4
t5
t6
t7
t8
t9
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
0
—
4
—
—
—
—
—
—
—
—
—
—
0.8
—
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read data valid to ARDY rising
Read data hold to RDN inactive
Write data setup to WRN inactive
Write data hold after WRN inactive
A1-A15, AEN, nBE[3:0] setup to ADSN rising
Read active to ARDY Low
4
2
4
—
2
A1-A15, AEN, BExN[3:0] hold after ADSN rising
Write inactive to ARDY Low
—
8
—
ARDY low (wait time) in read cycle (Note 7-1)
(It is 0 ns to read bank select register and 40 ns to read QMU data
register in turbo mode) (Note 7-2)
0
0
0
40
80
50
—
—
—
t10
ns
ARDY low (wait time) in read cycle (Note 7-1)
(It is 0 ns to read bank select register and 80 ns to read QMU data
register in normal mode)
ARDY low (wait time) in write cycle (Note 7-1)
(It is 0 ns to write bank select register)
(It is 36 ns to write QMU data register)
t11
ns
Note 7-1
When CPU finished current Read or Write operation, it can do next Read or Write operation even
the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/
WRN low until the ARDY returns to high.
Note 7-2
In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which
is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
DS00003147A-page 78
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KSZ8841-16M/-32M
7.3
Asynchronous Timing using DATACSN
FIGURE 7-3:
ASYNCHRONOUS CYCLE – USING DATACSN
t2
DATACSN
valid
Read Data
RDN, WRN
Write Data
t1
t5
t4
t6
valid
t7
t3
ARDY
t9
(Read Cycle)
t8
ARDY
(Write Cycle)
t10
TABLE 7-3:
ASYNCHRONOUS CYCLE USING DATACSN TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
t1
t2
t3
t4
t5
t6
t7
t8
DATACSN setup to RDN, WRN active
2
0
—
—
—
—
—
—
—
—
—
—
0.8
—
—
—
8
ns
ns
ns
ns
ns
ns
ns
ns
DATACSN hold after RDN, WRN inactive (assume ADSN tied Low)
Read data hold to ARDY rising
—
4
Read data to RDN hold
Write data setup to WRN inactive
Write data hold after WRN inactive
Read active to ARDY Low
4
2
—
—
Write inactive to ARDY Low
8
ARDY low (wait time) in read cycle (Note 7-1)
(It is 0 ns to read bank select register and 40 ns to read QMU data
register in turbo mode) (Note 7-2)
0
0
0
40
80
50
—
—
—
t9
ns
ARDY low (wait time) in read cycle (Note 7-1)
(It is 0 ns to read bank select register and 80 ns to read QMU data
register in normal mode)
ARDY low (wait time) in write cycle (Note 7-1)
(It is 0 ns to write bank select register)
(It is 36 ns to write QMU data register)
t10
ns
Note 7-1
When CPU finished current Read or Write operation, it can do next Read or Write operation even
the ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/
WRN low until the ARDY returns to high.
Note 7-2
In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which
is only supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
2019 Microchip Technology Inc.
DS00003147A-page 79
KSZ8841-16M/-32M
7.4
Address Latching Timing for All Modes
FIGURE 7-4:
ADDRESS LATCHING CYCLE FOR ALL MODES
t1
ADSN
t2
Address, AEN, BExN
t3
LDEVN
TABLE 7-4:
ADDRESS LATCHING TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
t1
t2
t3
A1-A15, AEN, BExN[3:0] setup to ADSN
4
2
—
—
—
—
—
5
ns
ns
ns
A1-A15, AEN, BExN[3:0] hold after ADSN rising
A4-A15, AEN to LDEVN delay
—
DS00003147A-page 80
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KSZ8841-16M/-32M
7.5
Synchronous Timing in Burst Write (VLBUSN = 1)
FIGURE 7-5:
SYNCHRONOUS BURST WRITE CYCLES – VLBUSN = 1
TABLE 7-5:
SYNCHRONOUS BURST WRITE TIMING PARAMETERS
Symbol Parameter
Min.
Max.
Units
t1
SWR setup to BCLK falling
4
4
4
6
2
5
3
4
3
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t2
DATDCSN setup to BCLK rising
CYCLEN setup to BCLK rising
Write data setup to BCLK rising
Write data hold to BCLK rising
RDYRTNN setup to BCLK falling
RDYRTNN hold to BCLK falling
SRDYN setup to BCLK rising
SRDYN hold to BCLK rising
DATACSN hold to BCLK rising
SWR hold to BCLK falling
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
CYCLEN hold to BCLK
2019 Microchip Technology Inc.
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KSZ8841-16M/-32M
7.6
Synchronous Timing in Burst Read (VLBUSN = 1)
FIGURE 7-6:
SYNCHRONOUS BURST READ CYCLES – VLBUSN = 1
BCLK
t10
t12
t2
t3
DATACSN
SWR
t11
t1
CYCLEN
t5
t4
data0
data1
data2
data3
Read Data
t7
t6
RDYRTNN
SRDYN
t8
t9
TABLE 7-6:
SYNCHRONOUS BURST READ TIMING PARAMETERS
Symbol Parameter
Min.
Max.
Units
t1
SWR setup to BCLK falling
4
4
4
6
2
5
3
4
3
2
2
2
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t2
DATDCSN setup to BCLK rising
CYCLEN setup to BCLK rising
Read data setup to BCLK rising
Read data hold to BCLK rising
RDYRTNN setup to BCLK falling
RDYRTNN hold to BCLK falling
SRDYN setup to BCLK rising
SRDYN hold to BCLK rising
DATACSN hold to BCLK rising
SWR hold to BCLK falling
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
CYCLEN hold to BCLK
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KSZ8841-16M/-32M
7.7
Synchronous Write Timing (VLBUSN = 0)
FIGURE 7-7:
SYNCHRONOUS WRITE CYCLE – VLBUSN = 0
BCLK
t2
valid
t1
Address, AEN, BExN
ADSN
SWR
t5
t6
t4
t3
CYCLEN
Write Data
SRDYN
t7
valid
t8
t9
t10
t11
t12
RDYRTNN
TABLE 7-7:
SYNCHRONOUS WRITE (VLBUSN = 0) TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
t1
A1-A15, AEN, BExN[3:0] setup to ADSN rising
A1-A15, AEN, BExN[3:0] hold after ADSN rising
CYCLEN setup to BCLK rising
4
2
4
2
4
0
5
1
8
1
4
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t2
t3
t4
CYCLEN hold after BCLK rising (non-burst mode)
SWR setup to BCLK
t5
t6
SWR hold after BCLK rising with SRDYN active
Write data setup to BCLK rising
Write data hold from BCLK rising
SRDYN setup to BCLK
t7
t8
t9
t10
t11
t12
SRDYN hold to BCLK
RDYRTNN setup to BCLK
RDYRTNN hold to BCLK
2019 Microchip Technology Inc.
DS00003147A-page 83
KSZ8841-16M/-32M
7.8
Synchronous Read Timing (VLBUSN = 0)
FIGURE 7-8:
SYNCHRONOUS READ CYCLE – VLBUSN = 0
BCLK
t2
valid
t1
Address, AEN, BExN
ADSN
SWR
t5
t4
t3
CYCLEN
Read Data
SRDYN
t7
valid
t6
t8
t9
t10
t11
RDYRTNN
TABLE 7-8:
SYNCHRONOUS READ (VLBUSN = 0) TIMING PARAMETERS
Symbol Parameter
t1
Min.
Typ.
Max.
Units
A1-A15, AEN, BExN[3:0] setup to ADSN rising
A1-A15, AEN, BExN[3:0] hold after ADSN rising
CYCLEN setup to BCLK rising
CYCLEN hold after BCLK rising (non-burst mode)
SWR setup to BCLK
4
2
4
2
4
1
8
8
1
4
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t2
t3
t4
t5
t6
Read data hold from BCLK rising
Read data setup to BCLK
t7
t8
SRDYN setup to BCLK
t9
SRDYN hold to BCLK
t10
t11
RDYRTNN setup to BCLK rising
RDYRTNN hold after BCLK rising
DS00003147A-page 84
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
7.9
Auto-Negotiation Timing
FIGURE 7-9:
AUTO-NEGOTIATION TIMING
TABLE 7-9:
AUTO-NEGOTIATION TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
tBTB
tFLPW
tPW
FLP burst to FLP burst
8
—
16
2
24
—
ms
ms
ns
μs
μs
—
FLP burst width
Clock/Data pulse width
—
100
64
—
tCTD
tCTC
—
Clock pulse to data pulse
Clock pulse to clock pulse
Number of Clock/Data pulses per burst
55.5
111
17
69.5
139
33
128
—
2019 Microchip Technology Inc.
DS00003147A-page 85
KSZ8841-16M/-32M
7.10 Reset Timing
As long as the stable supply voltages to reset High timing (minimum of 10 ms) are met, there is no power-sequencing
requirement for the KSZ8841M supply voltages (3.3V).
The reset timing requirement is summarized in Figure 7-10 and Table 7-10.
FIGURE 7-10:
RESET TIMING
Supply
Voltage
tsr
RST_N
TABLE 7-10: RESET TIMING PARAMETERS
Parameter
Description
Min.
Typ.
Max.
Units
tSR
Stable supply voltages to reset high
10
—
—
ms
DS00003147A-page 86
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
7.11 EEPROM Timing
FIGURE 7-11:
EEPROM READ CYCLE TIMING DIAGRAM
EECS
EESK
EEDO
EEDI
*1
1
tcyc
ts
11
0
An
A0
th
High-Z
D0
D1
D15
D13
D14
*1 Start bit
TABLE 7-11: EEPROM TIMING PARAMETERS
Symbol Parameter
Min.
Typ.
Max.
Units
4 (OBCR[1:0]=11 on-chip
bus speed @ 25 MHz)
or
0.8 (OBCR[1:0]=00
on-chip bus speed @
125 MHz)
tCYC
Clock cycle
—
—
μs
tS
th
Setup time
Hold time
20
20
—
—
—
—
ns
ns
2019 Microchip Technology Inc.
DS00003147A-page 87
KSZ8841-16M/-32M
8.0
SELECTION OF ISOLATION TRANSFORMERS
A1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common-mode choke
is recommended for exceeding FCC requirements.
Table 8-1 lists recommended transformer characteristics.
TABLE 8-1:
TRANSFORMER SELECTION CRITERIA
Parameter
Turns Ratio
Value
Test Conditions
1 CT : 1 CT
350 μH
0.4 μH
—
Open-Circuit Inductance (min.)
Leakage Inductance (max.)
Interwinding Capacitance (max.)
D.C. Resistance (max.)
Insertion Loss (max.)
100 mV, 100 kHz, 8 mA
1 MHz (min.)
12 pF
—
0.9Ω
—
0 MHz to 65 MHz
—
1.0 dB
HIPOT (min.)
1500 VRMS
TABLE 8-2:
QUALIFIED SINGLE-PORT MAGNETICS
Manufacturer
Part Number
Auto MDI-X
Bel Fuse
Delta
S558-5999-U7
LF8505
Yes
Yes
Yes
Yes
Yes
Yes
Yes
LanKom
Pulse
LF-H41S
H1102
Pulse (Low Cost)
Transpower
H1260
HB726
TDK (Mag Jack)
TLA-6T718
TABLE 8-3:
TYPICAL REFERENCE CRYSTAL CHARACTERISTICS
Characteristic
Value
Frequency
25 MHz
±50 ppm
20 pF
Frequency Tolerance (max.)
Load Capacitance (max.)
Series Resistance
25Ω
DS00003147A-page 88
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
9.0
9.1
PACKAGE OUTLINE
Package Marking Information
128-Lead PQFP*
128-Lead LQFP*
100-Lead LFBGA*
Example
MICREL
MICREL
XXXXXXX-XX
YYWWA7
KSZ8841-16
1912A5
XXXXXYYWWNNN
YYWWNNN
G00001912710
1912710
Legend: XX...X Product code or customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
*
e
3
)
●, ▲, ▼ Pin one index is identified by a dot, delta up, or delta down (triangle
mark).
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information. Package may or may not include
the corporate logo.
Underbar (_) and/or Overbar (‾) symbol may not be to scale.
2019 Microchip Technology Inc.
DS00003147A-page 89
KSZ8841-16M/-32M
FIGURE 9-1:
128-LEAD PQFP 14 MM X 20 MM PACKAGE OUTLINE AND RECOMMENDED
LAND PATTERN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS00003147A-page 90
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
FIGURE 9-2:
128-LEAD LQFP 14 MM X 14 MM PACKAGE OUTLINE AND RECOMMENDED
LAND PATTERN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
2019 Microchip Technology Inc.
DS00003147A-page 91
KSZ8841-16M/-32M
FIGURE 9-3:
100-LEAD LFBGA 10 MM X 10 MM PACKAGE OUTLINE AND RECOMMENDED
LAND PATTERN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS00003147A-page 92
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision
Section/Figure/Entry
Correction
Converted Micrel data sheet KSZ8841-16M/-32M to
Microchip DS00003147A. Minor text changes
throughout.
DS00003147A (07-22-19)
—
2019 Microchip Technology Inc.
DS00003147A-page 93
KSZ8841-16M/-32M
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
DS00003147A-page 94
2019 Microchip Technology Inc.
KSZ8841-16M/-32M
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
-XX
[-XX]
PART NO.
Device
X
X
X
[X]
a)
b)
c)
d)
e)
f)
KSZ8841-16MQL
8-Bit or 16-Bit Bus Design, Non-PCI Interface
128-lead PQFP, Single 3.3V Power Supply
Commercial Temperature Range
66/Tray
Bus
Design
Media
Type
Interface Package Supply Temperature
Voltage
KSZ8841-16MBL
Device:
KSZ8841: Single-Port Ethernet MAC Controller with Non-PCI
Interface
8-Bit or 16-Bit Bus Design, Non-PCI Interface
100-lead LFBGA, Single 3.3V Power Supply
Commercial Temperature Range
240/Tray
Bus Design:
-16 = 8-bit or 16-bit
-32 = 32-bit (Not available for LFBGA option)
KSZ8841-16MBLI
8-Bit or 16-Bit Bus Design, Non-PCI Interface
100-lead LFBGA, Single 3.3V Power Supply
Industrial Temperature Range
240/Tray
Interface:
Package:
M = Management Interface
KSZ8841-16MVL
8-Bit or 16-Bit Bus Design, Non-PCI Interface
128-lead LQFP, Single 3.3V Power Supply
Commercial Temperature Range
90/Tray
Q = 128-lead PQFP
B = 100-lead LFBGA
V = 128-lead LQFP
KSZ8841-16MVLI
8-Bit or 16-Bit Bus Design, Non-PCI Interface
128-lead LQFP, Single 3.3V Power Supply
Industrial Temperature Range
90/Tray
Supply Voltage:
Temperature:
Media Type:
L = Single 3.3V Power Supply Supported with Internal 1.8V
LDO
KSZ8841-16MVL-TR
<blank> = 0C to +70C (Commercial)
I = –40C to +85C (Industrial)
8-Bit or 16-Bit Bus Design, Non-PCI Interface
128-lead LQFP, Single 3.3V Power Supply
Commercial Temperature Range
1,000/Reel
<blank> = 66/Tray (PQFP option)
<blank> = 240/Tray (LFBGA option)
<blank> = 90/Tray (LQFP option)
TR = 1,000/Reel
g)
h)
i)
KSZ8841-16MVLI-TR
8-Bit or 16-Bit Bus Design, Non-PCI Interface
128-lead LQFP, Single 3.3V Power Supply
Industrial Temperature Range
1,000/Reel
KSZ8841-32MQL
32-Bit Bus Design, Non-PCI Interface
128-lead PQFP, Single 3.3V Power Supply
Commercial Temperature Range
66/Tray
KSZ8841-32MVL
32-Bit Bus Design, Non-PCI Interface
128-lead LQFP, Single 3.3V Power Supply
Commercial Temperature Range
90/Tray
j)
KSZ8841-32MVLI
32-Bit Bus Design, Non-PCI Interface
128-lead LQFP, Single 3.3V Power Supply
Industrial Temperature Range
90/Tray
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and is
not printed on the device package. Check with
your Microchip Sales Office for package
availability with the Tape and Reel option.
2019 Microchip Technology Inc.
DS00003147A-page 95
KSZ8841-16M/-32M
NOTES:
DS00003147A-page 96
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be
superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO
REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,
MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of
Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implic-
itly or otherwise, under any Microchip intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero,
motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion, SyncWorld, Temux,
TimeCesium, TimeHub, TimePictra, TimeProvider, Vite, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the
U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net,
PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI, SuperSwitcher,
SuperSwitcher II, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4832-7
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
DS00003147A-page 97
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-72400
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS00003147A-page 98
2019 Microchip Technology Inc.
05/14/19
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