KSZ8863MLLITR [MICROCHIP]
Integrated 3-Port 10/100 Managed Switch with PHYs;
| 型号： | KSZ8863MLLITR |
| 厂家： | 
MICROCHIP |
| 描述： | Integrated 3-Port 10/100 Managed Switch with PHYs 局域网 局域网（LAN）标准 外围集成电路 |
| 文件： | 总92页 (文件大小：2921K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ8863MLL/FLL/RLL
Integrated 3-Port 10/100 Managed Switch
with PHYs
- Non-Blocking Switch Fabric Ensures Fast
Packet Delivery by Utilizing a 1k MAC Address
Lookup Table and a Store-and-Forward Archi-
tecture
- Full-Duplex IEEE 802.3x Flow Control (PAUSE)
with Force Mode Option
- Half-Duplex Back Pressure Flow Control
- HP Auto MDI-X for Reliable Detection of and
Correction for Straight-Through and Crossover
Cables with Disable and Enable Option
- LinkMD® TDR-Based Cable Diagnostics Permit
Identification of Faulty Copper Cabling
- MII Interface Supports Both MAC Mode and
PHY Mode
Features
• Advanced Switch Features
- IEEE 802.1q VLAN Support for Up to 16 Groups
(Full Range of VLAN IDs)
- VLAN ID Tag/Untag Options, Per Port Basis
- IEEE 802.1p/q Tag Insertion or Removal on a
Per Port Basis (Egress)
- Programmable Rate Limiting at the Ingress and
Egress on a Per Port Basis
- Broadcast Storm Protection with Percent
Control (Global and Per Port Basis)
- IEEE 802.1d Rapid Spanning Tree Protocol
Support
- Tail Tag Mode (1 byte Added before FCS) Sup-
port at Port 3 to Inform the Processor which
Ingress Port Receives the Packet and its Prior-
ity
- Comprehensive LED Indicator Support for Link,
Activity, Full-/Half-Duplex and 10/100 Speed
- HBM ESD Rating 4 kV
• Switch Monitoring Features
- Bypass Feature that Automatically Sustains the
Switch Function between Port 1 and Port 2
when CPU (Port 3 Interface) Goes to the Sleep
Mode
- Port Mirroring/Monitoring/Sniffing: Ingress and/
or Egress Traffic to Any Port or MII
- MIB Counters for Fully Compliant Statistics
Gathering 34 MIB Counters Per Port
- Loopback Modes for Remote Diagnostic of Fail-
ure
• Low Power Dissipation
- Full-Chip Software Power-Down (Register Con-
figuration Not Saved)
- Self-Address Filtering
- Individual MAC Address for Port 1 and Port 2
- Supports RMII Interface and 50 MHz Reference
Clock Output
- IGMP Snooping (IPv4) Support for Multicast
Packet Filtering
- Energy-Detect Mode Support
- IPv4/IPv6 QoS Support
- Dynamic Clock Tree Shutdown Feature
- Per Port Based Software Power-Save on PHY
(Idle Link Detection, Register Configuration Pre-
served)
- Voltages: Single 3.3V Supply with Internal 1.8V
LDO for 3.3V VDDIO
- Optional 3.3V, 2.5V, and 1.8V for VDDIO
- Transceiver Power 3.3V for VDDA_3.3
• Industrial Temperature Range: –40°C to +85°C
• Available in a 48-Pin LQFP, Lead-Free Package
- MAC Filtering Function to Forward Unknown
Unicast Packets to Specified Port
• Comprehensive Configuration Register Access
- Serial Management Interface (SMI) to All Inter-
nal Registers
- MII Management (MIIM) Interface to PHY Reg-
isters
- High Speed SPI and I2C Interface to All Internal
Registers
- I/O Pins Strapping and EEPROM to Program
Selective Registers in Unmanaged Switch
Mode
Applications
- Control Registers Configurable on the Fly (Port-
Priority, 802.1p/d/q, AN…)
• VoIP Phone
• Set-Top/Game Box
• QoS/CoS Packet Prioritization Support
- Per Port, 802.1p and DiffServ-Based
- Re-Mapping of 802.1p Priority Field Per Port
basis, Four Priority Levels
• Proven Integrated 3-Port 10/100 Ethernet Switch
- 3rd Generation Switch with Three MACs and
Two PHYs Fully Compliant with IEEE 802.3u
Standard
• Automotive
• Industrial Control
• IPTV POF
• SOHO Residential Gateway
• Broadband Gateway/Firewall/VPN
• Integrated DSL/Cable Modem
• Wireless LAN Access Point + Gateway
• Standalone 10/100 Switch
2017-2021 Microchip Technology Inc.
DS00002335C-page 1
KSZ8863MLL/FLL/RLL
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00002335C-page 2
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
Table of Contents
1.0 Introduction ..................................................................................................................................................................................... 4
2.0 Pin Description and Configuration .................................................................................................................................................. 5
3.0 Functional Description .................................................................................................................................................................. 11
4.0 Register Descriptions .................................................................................................................................................................... 36
5.0 Operational Characteristics ........................................................................................................................................................... 72
6.0 Electrical Characteristics ............................................................................................................................................................... 73
7.0 Timing Specifications .................................................................................................................................................................... 75
8.0 Reset Circuit ................................................................................................................................................................................. 84
9.0 Selection of Isolation Transformers .............................................................................................................................................. 85
10.0 Package Outline .......................................................................................................................................................................... 86
Appendix A: Data Sheet Revision History ........................................................................................................................................... 87
The Microchip Web Site ...................................................................................................................................................................... 88
Customer Change Notification Service ............................................................................................................................................... 88
Customer Support ............................................................................................................................................................................... 88
Product Identification System ............................................................................................................................................................. 89
2017-2021 Microchip Technology Inc.
DS00002335C-page 3
KSZ8863MLL/FLL/RLL
1.0
1.1
INTRODUCTION
General Description
KSZ8863MLL, KSZ8863FLL, and KSZ8863RLL are highly integrated 3-port switch-on-a-chip ICs in the industry’s small-
est footprint. They are designed to enable a new generation of low port count, cost-sensitive, and power-efficient 10/
100 Mbps switch systems. Low power consumption, advanced power management, and sophisticated QoS features
(for example, IPv6 priority classification support) make these devices ideal for IPTV, IP-STB, VoIP, automotive, and
industrial applications.
The KSZ8863 family is designed to support the GREEN requirement in today’s switch systems. Advanced power man-
agement schemes include software power down, per port power down, and energy detect mode that shuts down the
transceiver when a port is idle.
KSZ8863MLL/FLL/RLL also offers a bypass mode that enables system-level power saving. In this mode, the processor
connected to the switch through the MII interface can be shut down without impacting the normal switch operation.
The configurations provided by the KSZ8863 family enable the flexibility to meet the requirements of different applica-
tions:
• KSZ8863MLL: Two 10/100BASE-T/TX transceivers and one MII interface
• KSZ8863RLL: Two 10/100BASE-T/TX transceivers and one RMII interface
• KSZ8863FLL: One 100BASE-FX, one 10/100BASE-T/TX transceivers, and one MII interface
The devices are available in RoHS-compliant 48-pin LQFP packages. Industrial-grade and automotive-grade are also
available.
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
1K LOOK-UP
ENGINE
10/100
T/TX/FX
PHY 1
HP AUTO
10/100
MAC 1
MDIX
QUEUE
MANAGEMENT
10/100
T/TX
PHY 2
HP AUTO
MDIX
10/100
MAC 2
BUFFER
MANAGEMENT
MII (for MLL, FLL)
RMII (for RLL)
10/100
MAC 3
FRAME
BUFFERS
MIB
COUNTERS
SPI
SPI
MIIM
CONTROL
REGISTERS
EEPROM
INTERFACE
SMI
I2C
P1 LED[1:0]
P2 LED[1:0]
LED
DRIVERS
STRAP IN
CONFIGURATION
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2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
2.0
PIN DESCRIPTION AND CONFIGURATION
FIGURE 2-1:
48-PIN 7 MM X 7 MM LQFP ASSIGNMENT (TOP VIEW)
48 47 46 45 44 43 42 4140 39 38 37
36
35
34
33
32
31
30
29
28
27
SCL_MDC
RXM1
1
2
3
RXP1
TXM1
TXP1
INTRN
SCRS3
4
SCOL3
5
VDDA_3.3
VDDC
ISET
6
48-pin
LQFP
GND
VDDA_1.8
7
SMRXC3
SMRXD30
SMRXD31
SMRXD32
SMRXD33/REFCLKO_3
8
RXM2
RXP2
AGND
TXM2 11
TXP2 12
9
10
26
25
SMRXDV3
13 14 15 16 17 18 19 20 21 22 23 24
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DS00002335C-page 5
KSZ8863MLL/FLL/RLL
TABLE 2-1:
SIGNALS
Pin
Number
Pin
Name
Type
Note 2-1
Description
1
2
3
4
5
RXM1
RXP1
I/O
I/O
I/O
I/O
P
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
Physical transmit or receive signal (– differential)
Physical transmit or receive signal (+ differential)
3.3V analog VDD
TXM1
TXP1
VDDA_3.3
Set physical transmit output current.
Pull down this pin with an 11.8 kΩ 1% resistor to ground.
6
ISET
O
7
8
VDDA_1.8
RXM2
RXP2
AGND
TXM2
TXP2
P
I/O
1.8V analog core power input from VDDCO (pin 42).
Physical receive or transmit signal (– differential)
Physical receive or transmit signal (+ differential)
Analog ground
9
I/O
10
11
12
13
GND
I/O
Physical transmit or receive signal (– differential)
Physical transmit or receive signal (+ differential)
No connection
I/O
NC
NC
25 MHz or 50 MHz crystal or oscillator clock connections.
Pins (X1 and X2) connect to a crystal. If an oscillator is used, X1 connects
to a 3.3V tolerant oscillator, and X2 is a NC.
14
X1
I
Note: The clock is ±50 ppm for both crystal and oscillator. The clock should
be applied to X1 pin before the reset voltage goes high.
15
16
X2
O
SMTXEN3
Ipu
Switch MII transmit enable
MLL/FLL: Switch MII transmit data bit 3
RLL: Strap option: RMII mode Clock selection
PU = Enable REFCLKO_3 output
SMTXD33/
EN_REFCLKO_3
17
Ipu
Ipu
PD = Disable REFCLKO_3 output
Switch MII transmit data bit 2
RLL: Strap option: X1 pin Clock selection (for Rev A3 and behind A3)
PU = 25 MHz to X1 pin as clock source (default)
PD = 50 MHz to X1 pin as clock source to provide or receive 50 MHz RMII
reference clock for RLL part
18
SMTXD32
19
20
21
SMTXD31
SMTXD30
GND
Ipu
Ipu
Switch MII/RMII transmit data bit 1
Switch MII/RMII transmit data bit 0
Digital ground
GND
3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well decou-
pling capacitors
22
VDDIO
P
MLL/FLL: Switch MII transmit clock (MII and SNI modes only)
Output in PHY MII mode and SNI mode
SMTXC3/
REFCLKI_3
Input in MAC MII and RMII mode
RLL: Reference clock input
23
I/O
Note: Pull-down by resistor is needed if the internal reference clock is used
in RLL by register 198 bit 3.
Switch port 3 MII transmit error in MII mode
0 = MII link indicator from host in MII PHY mode
1 = No link on port 3 MII PHY mode and enable bypass mode
SMTXER3/
MII_LINK_3
24
Ipd
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2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note 2-1
Description
Switch MII/RMII receive data valid
Strap option: Force Duplex mode (P1DPX)
PU = Port 1 default to Full-Duplex mode if P1ANEN = 1 and auto-negotia-
tion fails. Force port 1 in Full-Duplex mode if P1ANEN = 0.
PD = Port 1 default to Half-Duplex mode if P1ANEN = 1 and auto-negotia-
tion fails. Force port 1 in Half-Duplex mode if P1ANEN = 0.
25
SMRXDV3
Ipu/O
MLL/FLL: Switch MII receive data bit 3
RLL: Output reference clock in RMII mode.
Strap option: enable auto-negotiation on port 2 (P2ANEN)
PU = Enable
SMRXD33/
REFCLKO_3
26
27
Ipu/O
Ipu/O
PD = Disable
Switch MII receive data bit 2
Strap option: Force the speed on port 2 (P2SPD)
PU = Force port 2 to 100BT if P2ANEN = 0
PD = Force port 2 to 10BT if P2ANEN = 0
SMRXD32
SMRXD31
Switch MII/RMII receive data bit 1
Strap option: Force Duplex mode (P2DPX)
PU = Port 2 default to Full-Duplex mode if P2ANEN = 1 and auto-negotia-
tion fails. Force port 2 in Full-Duplex mode if P2ANEN = 0.
PD = Port 2 set to Half-Duplex mode if P2ANEN = 1 and auto-negotiation
fails. Force port 2 in Half-Duplex mode if P2ANEN = 0.
28
Ipu/O
Switch MII/RMII receive data bit 0
Strap option: Force flow control on port 2 (P2FFC)
PU = Always enable (force) port 2 flow control feature.
PD = Port 2 flow control feature enable is determined by auto-negotiation
result.
29
30
SMRXD30
SMRXC3
Ipu/O
I/O
Switch MII receive clock.
Output in PHY MII mode
Input in MAC MII mode
31
32
33
34
GND
GND
P
Digital ground
VDDC
SCOL3
SCRS3
1.8V digital core power input from VDDCO (pin 42)
Switch MII collision detect
Ipu/O
Ipu/O
Switch MII carrier sense
Interrupt
35
36
INTRN
Opu
I/O
Active-low signal to host CPU to indicate an interrupt status bit is set when
lost link. Refer to register 187 and 188.
SPI Client mode/I2C Client mode: clock input
I2C Host mode: clock output
MIIM clock input
SCL_MDC
SPI Client mode: serial data input
I2C Host/Client mode: serial data input/output
MIIM: Data input/output
Note: An external pull-up is needed on this pin when it is in use.
37
38
SDA_MDIO
SPIQ
Ipu/O
Ipd/O
SPI Client mode: serial data output
Note: An external pull-up is needed on this pin when it is in use.
Strap option: Force flow control on port 1 (P1FFC)
PU = Always enable (force) port 1 flow control feature
PD = Port 1 flow control feature enable is determined by auto-negotiation
result.
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DS00002335C-page 7
KSZ8863MLL/FLL/RLL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note 2-1
Description
SPI Client mode: chip select (active-low)
When SPISN is high, KSZ8863MLL/FLL/RLL is deselected and SPIQ is
held in a high impedance state.
A high-to-low transition is used to initiate SPI data transfer.
39
SPISN
Ipd
Note:
An external pull-up is needed on this pin when using SPI or
MDC/MDIO-MIIM/SMI mode.
3.3V, 2.5V, or 1.8V digital VDD input power supply for IO with well decou-
pling capacitors
40
41
VDDIO
GND
P
GND
Digital ground
1.8V core power voltage output (internal 1.8V LDO regulator output)
This 1.8V output pin provides power to both VDDA_1.8 and VDDC input
pins.
42
VDDCO
P
Note:
Internally, 1.8V LDO regulator input comes from VDDIO. Do not
connect an external power supply to VDDCO pin. The ferrite
bead is requested between analog and digital 1.8V core power.
Port 1 LED Indicators:
Default: Speed (refer to register 195 bit [5:4])
Strap option: Force the speed on port 1 (P1SPD)
PU = Force port 1 to 100BT if P1ANEN = 0
PD = Force port 1 to 10BT if P1ANEN = 0
43
44
P1LED1
P1LED0
Ipu/O
Ipd/O
Port 1 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4])
Strap option: Enable auto-negotiation on port 1 (P1ANEN)
PU = Enable (better to pull up in design)
PD = Disable (default)
DS00002335C-page 8
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KSZ8863MLL/FLL/RLL
TABLE 2-1:
SIGNALS (CONTINUED)
Pin
Number
Pin
Name
Type
Note 2-1
Description
Port 2 LED Indicators:
Default: Speed (refer to register 195 bit [5:4])
Strap option: Serial bus configuration
Port 2 LED Indicators:
Default: Link/Act. (refer to register 195 bit [5:4])
Strap option: Serial bus configuration
Serial bus configuration pins to select mode of access to KSZ8863MLL/
FLL/RLL internal registers.
[P2LED1, P2LED0] = [0, 0] — I2C Host (EEPROM) mode
(If EEPROM is not detected, the KSZ8863MLL/FLL/RLL is configured with
the default values of its internal registers and the values of its strap-in
pins.)
45
P2LED1
Ipu/O
Interface Signals
SPIQ
Type
Description
O
O
I/O
I
Not used (tri-stated)
I2C clock
I2C data I/O
SCL_MDC
SDA_MDIO
SPISN
Not used
[P2LED1, P2LED0] = [0, 1] — I2C Client mode
The external I2C Host drives the SCL_MDC clock.
The KSZ8863MLL/FLL/RLL device addresses are:
1011_1111 <read>
1011_1110 <write>
Interface Signals
SPIQ
Type
Description
O
Not used (tri-stated)
I2C clock
I2C data I/O
SCL_MDC
SDA_MDIO
SPISN
I
I/O
I
Not used
[P2LED1, P2LED0] = [1, 0] — SPI Client mode
46
P2LED0
Ipu/O
Interface Signals
SPIQ
Type
Description
O
I
SPI data out
SPI clock
SCL_MDC
SDA_MDIO
SPISN
I
SPI data in
SPI chip select
I
[P2LED1, P2LED0] = [1, 1] – SMI/MIIM mode
In SMI mode, KSZ8863MLL/FLL/RLL provides access to all its internal 8-
bit registers through its SCL_MDC and SDA_MDIO pins.
In MIIM mode, KSZ8863MLL/FLL/RLL provides access to its 16-bit MIIM
registers through its SDC_MDC and SDA_MDIO pins.
47
48
RSTN
Ipu
I
Hardware reset pin (active-low)
MLL/RLL: No connection or connect to analog ground by 1 kΩ pull-down
resistor.
FXSD1
FLL: Fiber signal detect
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DS00002335C-page 9
KSZ8863MLL/FLL/RLL
Note 2-1
P = power supply
GND = Ground
I = Input
O = Output
I/O = Bi-directional
Ipu/O = Input with internal pull-up during reset; output pin otherwise
Ipu = Input with internal pull-up
Ipd = Input with internal pull-down
Opu = Output with internal pull-up
Opd = Output with internal pull-down
Speed: Low (100BASE-TX), High (10BASE-T)
Full-Duplex: Low (full-duplex), High (half-duplex)
Activity: Toggle (transmit/receive activity)
Link: Low (link), High (no link)
DS00002335C-page 10
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
3.0
FUNCTIONAL DESCRIPTION
KSZ8863MLL/FLL/RLL contains two 10/100 physical layer transceivers and three MAC units with an integrated layer 2
managed switch.
KSZ8863MLL/FLL/RLL has the flexibility to reside in either a managed or unmanaged design. In a managed design, the
host processor has complete control of KSZ8863MLL/FLL/RLL via the SMI interface, MIIM interface, SPI bus, or I2C
bus. An unmanaged design is achieved through I/O strapping and/or EEPROM programming at system reset time.
On the media side, KSZ8863MLL/FLL/RLLsupports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports. Phys-
ical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design
more efficient and allow for lower power consumption and smaller chip die size.
3.1
Physical Layer Transceiver
3.1.1
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-
version, and MLT3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT3 current output. The output current is
set by an external 1% 11.8 kΩ resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, overshoot, and timing jitter. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX
transmitter.
3.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT3-to-NRZI conversion, data and
clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its
characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on com-
parisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC restoration and data conversion block. The DC restoration circuit is used
to compensate for the effect of baseline wander and to improve the dynamic range. The differential data conversion
circuit converts the MLT3 format back to NRZI. The slicing threshold is also adaptive.
The clock recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to the MII format and provided as the input data to the MAC.
3.1.3
PLL CLOCK SYNTHESIZER
KSZ8863MLL/FLL/RLL generates 125 MHz, 62.5 MHz, and 31.25 MHz clocks for system timing. Internal clocks are
generated from an external 25 MHz or 50 MHz crystal or oscillator. KSZ8863RLL can generate a 50 MHz reference
clock for the RMII interface.
3.1.4
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register
(LFSR). The scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming
data stream using the same sequence as at the transmitter.
3.1.5
100BASE-FX OPERATION
The 100BASE-FX operation is similar to the 100BASE-TX operation with the differences being that the scrambler/de-
scrambler and MLT3 encoder/decoder are bypassed on transmission and reception. In addition, auto-negotiation is
bypassed and auto MDI/MDI-X is disabled.
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DS00002335C-page 11
KSZ8863MLL/FLL/RLL
3.1.6
100BASE-FX SIGNAL DETECTION
In 100BASE-FX operation, FXSD (fiber signal detect), input pin 48, is usually connected to the fiber transceiver SD (sig-
nal detect) output pin. The fiber signal threshold can be selected by register 192 bit 6 for port 1. When FXSD is less than
the threshold, no fiber signal is detected and a far-end fault (FEF) is generated. When FXSD is over the threshold, the
fiber signal is detected.
Alternatively, the designer may choose not to implement the FEF feature. In this case, the FXSD input pin is tied high
to force 100BASE-FX mode.
100BASE-FX signal detection is summarized in Table 3-1:
TABLE 3-1:
FX SIGNAL THRESHOLD
Register 192 Bit 7, Bit 6 (Port 1)
Fiber Signal Threshold at FXSD
1
0
2.0V
1.2V
To ensure proper operation, a resistive voltage divider is recommended to adjust the fiber transceiver SD output voltage
swing to match the FXSD pin’s input voltage threshold.
3.1.7
100BASE-FX FAR-END FAULT
A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The
KSZ8863FLL detects a FEF when its FXSD input is below the Fiber Signal Threshold. When a FEF is detected,
KSZ8863FLL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period
between frames. By default, FEF is enabled.
3.1.8
10BASE-T TRANSMIT
The 10BASE-T driver is incorporated with the 100BASE-TX driver to allow for transmission using the same magnetics.
They are internally wave-shaped and pre-emphasized into outputs with a typical 2.3V amplitude. The harmonic contents
are at least 27 dB below the fundamental frequency when driven by an all-ones Manchester-encoded signal.
3.1.9
10BASE-T RECEIVE
On the receive side, input buffers and level detecting squelch circuits are employed. A differential input receiver circuit
and a phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into
clock signal and NRZ data. A squelch circuit rejects signals with levels less than 400 mV or with short pulse widths to
prevent noise at the RXP-or-RXM input from falsely triggering the decoder. When the input exceeds the squelch limit,
the PLL locks onto the incoming signal and KSZ8863MLL/FLL/RLL decodes a data frame. The receiver clock is main-
tained active during idle periods in between data reception.
3.1.10
MDI/MDI-X AUTO CROSSOVER
To eliminate the need for crossover cables between similar devices, KSZ8863MLL/FLL/RLL supports HP Auto MDI/
MDI-X and IEEE 802.3u standard MDI/MDI-X auto crossover. HP Auto MDI/MDI-X is the default.
The auto-sense function detects remote transmit and receive pairs and correctly assigns transmit and receive pairs for
the KSZ8863MLL/FLL/RLL device. This feature is extremely useful when end users are unaware of cable types, and
also, saves on an additional uplink configuration connection. The auto-crossover feature can be disabled through the
port control registers, or MIIM PHY registers.
The IEEE 802.3u standard MDI and MDI-X definitions are illustrated in Table 3-2.
TABLE 3-2:
MDI/MDI-X PIN DEFINITIONS
MDI
MDI-X
RJ-45 Pins
Signals
RJ-45 Pins
Signals
1
2
3
6
TD+
TD–
RD+
RD–
1
2
3
6
RD+
RD–
TD+
TD–
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KSZ8863MLL/FLL/RLL
3.1.10.1
Straight Cable
A straight cable connects an MDI device to an MDI-X device, or an MDI-X device to an MDI device. Figure 3-1 depicts
a typical straight cable connection between a NIC card (MDI) and a switch, or hub (MDI-X).
FIGURE 3-1:
TYPICAL STRAIGHT CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
Transmit Pair
2
Receive Pair
2
Straight
Cable
3
3
4
4
Receive Pair
5
Transmit Pair
5
6
7
8
6
7
8
Modular Connector
(RJ-45)
Modular Connector
(RJ-45)
NIC
HUB
(Repeater or Switch)
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KSZ8863MLL/FLL/RLL
3.1.10.2
Crossover Cable
A crossover cable connects an MDI device to another MDI device, or an MDI-X device to another MDI-X device.
Figure 3-2 shows a typical crossover cable connection between two switches or hubs (two MDI-X devices).
FIGURE 3-2:
TYPICAL CROSSOVER CABLE CONNECTION
10/100 Ethernet
Media Dependent Interface
10/100 Ethernet
Media Dependent Interface
1
1
Crossover
Cable
Receive Pair
2
Receive Pair
2
3
3
4
4
Transmit Pair
5
Transmit Pair
5
6
7
8
6
7
8
Modular Connector (RJ-45)
HUB
Modular Connector (RJ-45)
HUB
(Repeater or Switch)
(Repeater or Switch)
3.1.11
AUTO-NEGOTIATION
KSZ8863MLL/FLL/RLL conforms to the auto-negotiation protocol defined in Clause 28 of the IEEE 802.3u specification.
Auto-negotiation allows unshielded twisted pair (UTP) link partners to select the best common mode of operation. In
auto-negotiation, link partners advertise their capabilities across the link to each other. If auto-negotiation is not sup-
ported or the KSZ8863MLL/FLL/RLL link partner is forced to bypass auto-negotiation, KSZ8863MLL/FLL/RLL sets its
operating mode by observing the signal at its receiver. This is known as parallel detection, and allows KSZ8863MLL/
FLL/RLL to establish a link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement pro-
tocol.
The link up process is shown in Figure 3-3.
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KSZ8863MLL/FLL/RLL
FIGURE 3-3:
AUTO-NEGOTIATION AND PARALLEL OPERATION
START AUTO-NEGOTIATION
PARALLEL
FORCE LINK SETTING
YES
NO
OPERATION
ATTEMPT AUTO-
NEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
3.1.12
LINKMD® CABLE DIAGNOSTICS
KSZ8863MLL/FLL/RLL supports LinkMD. The LinkMD feature utilizes time domain reflectometry (TDR) to analyze the
cabling plant for common cabling problems such as open circuits, short circuits, and impedance mismatches.
LinkMD works by sending a pulse of known amplitude and duration down the MDI and MDI-X pairs and then analyzes
the shape of the reflected signal. Timing the pulse duration gives an indication of the distance to the cabling fault. Inter-
nal circuitry displays the TDR information in a user-readable digital format.
Cable diagnostics are only valid for copper connections and do not support fiber optic operation.
3.1.12.1
Access
LinkMD is initiated through accessing the PHY special control/status registers {26, 42} and the LinkMD result registers
{27, 43} for ports 1 and 2 respectively; and in conjunction with the port registers control 13 for ports 1 and 2 respectively
to disable Auto MDI/MDIX.
Alternatively, the MIIM PHY registers 0 and 29 can be used for LinkMD access.
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KSZ8863MLL/FLL/RLL
3.1.12.2
Usage
The following is a sample procedure for using LinkMD with registers {42, 43, 45} on port 2:
1. Disable auto MDI/MDI-X by writing a ‘1’ to register 45, bit [2] to enable manual control over the differential pair
used to transmit the LinkMD pulse.
2. Start cable diagnostic test by writing a ‘1’ to register 42, bit [4]. This enable bit is self-clearing.
3. Wait (poll) for register 42, bit [4] to return a ‘0’, indicating cable diagnostic test is complete.
4. Read cable diagnostic test results in register 42, bits [6:5]. The results are as follows:
00 = normal condition (valid test)
01 = open condition detected in cable (valid test)
10 = short condition detected in cable (valid test)
11 = cable diagnostic test failed (invalid test)
The ‘11’ case, invalid test, occurs when KSZ8863MLL/FLL/RLL is unable to shut down the link partner. In this instance,
the test is not run because it is impossible for KSZ8863MLL/FLL/RLL to determine if the detected signal is a reflection
of the signal generated or a signal from another source.
5. Get the distance to fault by concatenating register 42, bit [0] and register 43, bits [7:0]; and multiplying the result
by a constant of 0.4. The distance to the cable fault can be determined by the following formula:
EQUATION 3-1:
·
DDistance to cable fault in meters = 0.4 Register 26 bit [0] Register 27 bits [7:0]
Concatenated values of registers 42 and 43 are converted to decimal before multiplying by 0.4.
The constant (0.4) may be calibrated for different cabling conditions, including cables with a velocity of propagation that
varies significantly from the norm.
3.2
Power Management
KSZ8863MLL/FLL/RLL supports enhanced power management feature in low power state with energy detection to
ensure low-power dissipation during device idle periods. There are five operation modes under the power management
function, which is controlled by two bits in register 195 (0xC3) and one bit in register 29 (0x1D), 45(0x2D) as shown
below:
• Register 195 bit [1:0] = 00 Normal Operation mode
• Register 195 bit [1:0] = 01 Energy Detect mode
• Register 195 bit [1:0] = 10 Soft Power Down mode
• Register 195 bit [1:0] = 11 Power Saving mode
• Register 29, 45 bit 3 = 1 Port Based Power Down mode
Table 3-3 indicates all internal function blocks status under four different power management operation modes.
TABLE 3-3:
INTERNAL FUNCTION BLOCK STATUS
Power Management Operation Modes
KSZ8863MLL/FLL/RLL
Function Blocks
Power Saving
Mode
Energy Detect
Mode
Soft Power Down
Mode
Normal Mode
Internal PLL Clock
Tx/Rx PHY
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Rx unused block
disabled
Energy detect at Rx
MAC
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Disabled
Disabled
Host Interface
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KSZ8863MLL/FLL/RLL
3.2.1
NORMAL OPERATION MODE
This is the default setting bit [1:0] = 00 in register 195 after the chip power-up or hardware reset. When KSZ8863MLL/
FLL/RLL is in this Normal Operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface is
ready for CPU read or write.
During the Normal Operation mode, the host CPU can set the bit [1:0] in register 195 to transit the current Normal Oper-
ation mode to any one of the other three power management operation modes.
3.2.2
POWER SAVING MODE
The Power Saving mode is entered when Auto-Negotiation mode is enabled, cable is disconnected, and bit [1:0] = 11
in register 195 is set. When KSZ8863MLL/FLL/RLL is in this mode, all PLL clocks are enabled, MAC is on, all internal
register values are not changed, and the host interface is ready for CPU read or write. In this mode, it mainly controls
the PHY transceiver on or off based on line status to achieve power saving. The PHY remains transmitting and only
turns off the unused receiver block. Once the activity resumes due to plugging a cable or attempting by the far end to
establish a link, KSZ8863MLL/FLL/RLL can automatically enable the PHY power-up to normal power state from Power
Saving mode.
During the Power Saving mode, the host CPU can set bit [1:0] = 0 in register 195 to transit the current Power Saving
mode to any one of the other three power management operation modes.
3.2.3
ENERGY DETECT MODE
The Energy Detect mode provides a mechanism to save more power than in the Normal Operation mode when
KSZ8863MLL/FLL/RLL is not connected to an active link partner. In this mode, the device saves up to 87% of the power.
If the cable is not plugged, KSZ8863MLL/FLL/RLL can automatically enter a low-power state, that is, the Energy Detect
mode. In this mode, KSZ8863MLL/FLL/RLL keeps transmitting 120 ns width pulses at a rate of 1 pulse/second. Once
the activity resumes due to plugging a cable or attempting by the far end to establish a link, KSZ8863MLL/FLL/RLL can
automatically power up to normal power state in Energy Detect mode.
Energy Detect mode consists of two states: normal power state and low power state. In low power state, KSZ8863MLL/
FLL/RLL reduces the power consumption by disabling all circuitries except the energy detect circuitry of the receiver.
The Energy Detect mode is entered by setting bit [1:0] = 01 in register 195. When KSZ8863MLL/FLL/RLL is in this mode,
it monitors the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bit [7:0]
Go-Sleep time in register 196, KSZ8863MLL/FLL/RLL goes into a low power state. When KSZ8863MLL/FLL/RLL is in
low power state, it keeps monitoring the cable energy. Once the energy is detected from the cable, KSZ8863MLL/FLL/
RLL enters the normal power state. When KSZ8863MLL/FLL/RLL is in the normal power state, it can transmit or receive
packet from the cable.
It saves about 87% of the power when the MII interface is in PHY mode (register 53 bit 7 = 0), pin SMTXER3/MII_LINK_3
is connected to High, register 195 bit [1:0] = 01, bit 2 = 1(Disable PLL), and no cables are connected.
3.2.4
SOFT POWER DOWN MODE
The Soft Power Down mode is entered by setting bit [1:0] = 10 in register 195. When KSZ8863MLL/FLL/RLL is in this
mode, all PLL clocks are disabled, PHY and MAC are off, and all internal register values are not changed. When the
host set bit [1:0] = 00 in register 195, this device reverts from current Soft Power Down mode to Normal Operation mode.
3.2.5
PORT-BASED POWER DOWN MODE
In addition, KSZ8863MLL/FLL/RLL features a per-port power down mode. To save power, a PHY port that is not in use
can be powered down via the port control register 29 or 45 bit 3, or the MIIM PHY register. It saves about 15 mAper port.
3.3
MAC and Switch
3.3.1
ADDRESS LOOKUP
The internal lookup table stores MAC addresses and their associated information. It contains a 1K unicast address table
plus switching information.
KSZ8863MLL/FLL/RLL is guaranteed to learn 1K addresses and distinguishes itself from hash-based lookup tables,
which depending on the operating environment and probabilities, may not guarantee the absolute number of addresses
it can learn.
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KSZ8863MLL/FLL/RLL
3.3.2
LEARNING
The internal lookup engine updates its table with a new entry if the following conditions are met:
• The received packet's Source Address (SA) does not exist in the lookup table.
• The received packet is good; the packet has no receiving errors and is of legal length.
The lookup engine inserts the qualified SA into the table, along with the port number and time stamp. If the table is full,
the last entry of the table is deleted to make room for the new entry.
3.3.3
MIGRATION
The internal lookup engine also monitors whether a station has moved. If a station has moved, it updates the table
accordingly. Migration happens when the following conditions are met:
• The received packet’s SA is in the table, but the associated source port information is different.
• The received packet is good; the packet has no receiving errors and is of legal length.
The lookup engine updates the existing record in the table with the new source port information.
3.3.4
AGING
The lookup engine updates the time stamp information of a record whenever the corresponding SA appears. The time
stamp is used in the aging process. If a record is not updated for a period of time, the lookup engine removes the record
from the table. The lookup engine constantly performs the aging process and continuously removes aging records. The
aging period is about 200 seconds. This feature can be enabled or disabled through register 3 (0x03) bit [2].
3.3.5
FORWARDING
KSZ8863MLL/FLL/RLL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 3-4
shows stage one of the forwarding algorithm, where the search engine looks up the VLAN ID, static table, and dynamic
table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by span-
ning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “port to forward 2” (PTF2), as
shown in Figure 3-5. The packet is sent to PTF2.
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KSZ8863MLL/FLL/RLL
FIGURE 3-4:
DESTINATION ADDRESS LOOKUP FLOW CHART, STAGE 1
Start
- Search VLAN table
- Ingress VLAN filtering
- Discard NPVID check
NO
VLAN ID
Valid?
PTF1= NULL
YES
Search complete.
Get PTF1 from
Static MAC Table
FOUND
Search Static
Table
This search is based on
DA or DA+FID
NOT
FOUND
Search complete.
Get PTF1 from
Dynamic MAC
Table
FOUND
This search is based on
DA+FID
Dynamic Table
Search
NOT
FOUND
Search complete.
Get PTF1 from
VLAN Table
PTF1
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KSZ8863MLL/FLL/RLL
FIGURE 3-5:
DESTINATION ADDRESS RESOLUTION FLOW CHART, STAGE 2
PTF1
- Check receiving port's receive enable bit
- Check destination port's transmit enable bit
- Check whether packets are special (BPDU
or specified)
Spanning Tree
Process
- Applied to MAC #1 and MAC #2
- MAC #3 is reserved for
microprocessor
IGMP Process
- IGMP will be forwarded to port 3
- RX Mirror
- TX Mirror
- RX or TX Mirror
- RX and TX Mirror
Port Mirror
Process
Port VLAN
Membership
Check
PTF2
KSZ8863MLL/FLL/RLL does not forward the following packets:
1. Error packets: These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal
size packet errors.
2. IEEE802.3x PAUSE frames: KSZ8863MLL/FLL/RLL intercepts these packets and performs full duplex flow con-
trol accordingly.
3. “Local” packets: Based on destination address (DA) lookup. If the destination port from the lookup table matches
the port from which the packet originated, the packet is defined as local.
3.3.6
SWITCHING ENGINE
KSZ8863MLL/FLL/RLL features a high-performance switching engine to move data to and from the MAC’s packet buf-
fers. It operates in store and forward mode, while the efficient switching mechanism reduces overall latency.
The switching engine has a 32-kb internal frame buffer. This buffer pool is shared among all three ports. There are a
total of 256 buffers available. Each buffer is sized at 128 bytes.
3.3.7
MAC OPERATION
KSZ8863MLL/FLL/RLL strictly abides by IEEE 802.3 standards to maximize compatibility.
3.3.7.1
Inter Packet Gap (IPG)
If a frame is successfully transmitted, the 96 bits time IPG is measured between the two consecutive MTXEN. If the
current packet is experiencing collision, the 96 bits time IPG is measured from MCRS and the next MTXEN.
3.3.7.2
Back-Off Algorithm
KSZ8863MLL/FLL/RLL implements the IEEE 802.3 standard for the binary exponential back-off algorithm and the
optional “aggressive mode” back-off. After 16 collisions, the packet is optionally dropped depending on the switch con-
figuration for register 4 (0x04) bit [3].
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KSZ8863MLL/FLL/RLL
3.3.7.3
Late Collision
If a transmit packet experiences collisions after 512 bit times of the transmission, the packet is dropped.
3.3.7.4
Illegal Frames
KSZ8863MLL/FLL/RLL discards frames less than 64 bytes and can be programmed to accept frames up to 1518 bytes,
1536 bytes, or 1916 bytes. These maximum frame size settings are programmed in register 4 (0x04). Since
KSZ8863MLL/FLL/RLL supports VLAN tags, the maximum sizing is adjusted when these tags are present.
3.3.7.5
Full-Duplex Flow Control
KSZ8863MLL/FLL/RLL supports the standard IEEE 802.3x flow control frames on both transmit and receive sides.
On the receive side, if KSZ8863MLL/FLL/RLLreceives a pause control frame, KSZ8863MLL/FLL/RLL does not transmit
the next normal frame until the timer, specified in the pause control frame, expires. If another pause frame is received
before the current timer expires, the timer is updated with the new value in the second pause frame. During this period
(while it is flow controlled), only flow control packets from KSZ8863MLL/FLL/RLL are transmitted.
On the transmit side, KSZ8863MLL/FLL/RLL has intelligent and efficient ways to determine when to invoke flow control.
The flow control is based on availability of the system resources, including available buffers, available transmit queues
and available receive queues.
KSZ8863MLL/FLL/RLL will flow control a port that has just received a packet if the destination port resource is busy.
KSZ8863MLL/FLL/RLL issues a flow control frame (XOFF) containing the maximum pause time defined by the IEEE
802.3x standard. Once the resource is freed up, KSZ8863MLL/FLL/RLL sends out the other flow control frame (XON)
with zero pause time to turn off the flow control (turn on transmission to the port). A hysteresis feature is provided to
prevent the flow control mechanism from being constantly activated and deactivated.
KSZ8863MLL/FLL/RLL flow controls all ports if the receive queue becomes full.
3.3.7.6
Half-Duplex Backpressure
A half-duplex backpressure option (not in IEEE 802.3 standards) is also provided. The activation and deactivation con-
ditions are the same as a full-duplex flow control. If backpressure is required, KSZ8863MLL/FLL/RLL sends preambles
to defer the other stations' transmission (carrier sense deference).
To avoid jabber and excessive deference (as defined in the IEEE 802.3 standard), after a certain time, KSZ8863MLL/
FLL/RLL discontinues the carrier sense and then raises it again quickly. This short silent time (no carrier sense) prevents
other stations from sending out packets, thus keeping other stations in a carrier sense deferred state. If the port has
packets to send during a backpressure situation, the carrier sense type backpressure is interrupted and those packets
are transmitted instead. If there are no additional packets to send, carrier sense type backpressure is activated again
until switch resources free up. If a collision occurs, the binary exponential back-off algorithm is skipped and carrier sense
is generated immediately, thus reducing the chance of further collisions and maintaining carrier sense to prevent packet
reception.
To ensure that no packet is lost in 10BASE-T or 100BASE-TX half-duplex modes, the user must enable the following:
• Aggressive back-off (register 3 (0x03), bit [0])
• No excessive collision drop (register 4 (0x04), bit [3])
Note:
These bits are not set as defaults because it is not the IEEE standard.
3.3.7.7
Broadcast Storm Protection
KSZ8863MLL/FLL/RLL has an intelligent option to protect the switch system from receiving too many broadcast pack-
ets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch
resources (bandwidth and available space in transmit queues) may be utilized. KSZ8863MLL/FLL/RLL can opt to
include “multicast packets” for storm control. The broadcast storm rate parameters are programmed globally and can
be enabled or disabled on a per-port basis. The rate is based on a 67 ms interval for 100BT and a 500 ms interval for
10BT. At the beginning of each interval, the counter is cleared to zero, and the rate limit mechanism starts to count the
number of bytes during the interval. The rate definition is described in register 6 (0x06) and 7 (0x07). The default setting
is 0x63 (99 decimal). This is equal to a rate of 1%, calculated as follows:
148,800 frames/sec × 67 ms/interval × 1% = 99 frames/interval (approx.) = 0x63
Note:
The 148,800 frames/sec is based on 64-byte block of packets in 100BASE-TX with 12 bytes of IPG and 8
bytes of preamble between two packets.
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KSZ8863MLL/FLL/RLL
3.3.7.8
Port Individual MAC Address and Source Port Filtering
KSZ8863MLL/FLL/RLL provides individual MAC address for port 1 and port 2. They can be set at registers 142-147 and
148-153. The packet is filtered if its source address matches the MAC address of port 1 or port 2 when register 21 and
37 bit 6 is set to 1, respectively. For example, the packet is dropped after it completes the loop of a ring network.
3.3.8
MII INTERFACE OPERATION
The Media Independent Interface (MII) is specified in Clause 22 of the IEEE 802.3u standard. It provides a common
interface between physical layer and MAC layer devices. The MII provided by KSZ8863MLL/FLL is connected to the
device’s third MAC; the MII default is PHY mode and can be set to MAC mode with the register 53 bit 7. The interface
contains two distinct groups of signals: one for transmission and the other for reception. Table 3-4 describes the signals
used by the MII bus.
TABLE 3-4:
MII SIGNALS
PHY Mode Connections
MAC Mode Connections
Pin Description
External MAC
Controller Signals
KSZ8863MLL/FLL
PHY Signals
External PHY
KSZ8863MLL/FLL
MAC Signals
Signals
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
SMTXEN3
SMTXER3
SMTXD33
SMTXD32
SMTXD31
SMTXD30
SMTXC3
Transmit Enable
Transmit Error
MTXEN
MTXER
MTXD3
MTXD2
MTXD1
MTXD0
MTXC
SMRXDV3
(NOT USED)
SMRXD33
SMRXD32
SMRXD31
SMRXD30
SMRXC3
SCOL3
Transmit Data Bit 3
Transmit Data Bit 2
Transmit Data Bit 1
Transmit Data Bit 0
Transmit Clock
MCOL
SCOL3
Collision Detection
Carrier Sense
MCOL
MCRS
SCRS3
MCRS
SCRS3
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
SMRXDV3
(NOT USED)
SMRXD33
SMRXD32
SMRXD31
SMRXD30
SMRXC3
Receive Data Valid
Receive Error
MRXDV
MRXER
MRXD3
MRXD2
MRXD1
MRXD0
MRXC
SMTXEN3
SMTXER3
SMTXD33
SMTXD32
SMTXD31
SMTXD30
SMTXC3
Receive Data Bit 3
Receive Data Bit 2
Receive Data Bit 1
Receive Data Bit 0
Receive Clock
The MII operates in either PHY mode or MAC mode. The data interface is nibble-wide and runs at ¼ the network bit rate
(not encoded). Additional signals on the transmit side indicate when data is valid or when an error occurs during trans-
mission. Similarly, the receive side has signals that convey when the data is valid and without physical layer errors. For
half-duplex operation, the SCOL signal indicates if a collision has occurred during transmission.
KSZ8863MLL/FLL does not provide the MRXER signal for PHY mode operation, and the MTXER signal for MAC mode
operation. Normally, MRXER indicates a receive error coming from the physical layer device and MTXER indicates a
transmit error from the MAC device. Because the switch filters error frames, these MII error signals are not used by
KSZ8863MLL/FLL. So, for PHY mode operation, if the device interfacing with KSZ8863MLL/FLL has an MRXER input
pin, it needs to be tied low. And, for MAC mode operation, if the device interfacing with KSZ8863MLL/FLL has an
MTXER input pin, it also needs to be tied low.
KSZ8863MLL/FLL provides a bypass feature in the MII PHY mode. Pin SMTXER3/MII_LINK is used for MII link status.
If the host is powered down, pin MII_LINK goes to high. In this case, no new ingress frames from port 1 or port 2 are
sent out through port 3, and the frames for port 3 already in packet memory are flushed out.
3.3.9
RMII INTERFACE OPERATION
The Reduced Media Independent Interface (RMII) specifies a low pin count Media Independent Interface (MII). RMII
provides a common interface between physical layer and MAC layer devices, and has the following key characteristics:
• Ports 10 Mbps and 100 Mbps data rates
• Uses a single 50 MHz clock reference (provided internally or externally)
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KSZ8863MLL/FLL/RLL
• Provides independent 2-bit wide (di-bit) transmit and receive data paths
• Contains two distinct groups of signals: one for transmission and the other for reception
When EN_REFCLKO_3 is high, KSZ8863RLL outputs a 50 MHz in REFCLKO_3. Register 198 bit [3] is used to select
the internal or external reference clock. Internal reference clock means that the clock for the RMII of KSZ8863RLL is
provided by KSZ8863RLL internally and the REFCLKI_3 pin is unconnected. For the external reference clock, the clock
provides to KSZ8863RLL via REFCLKI_3.
If KSZ8863RLL does not provide the reference clock, this 50 MHz reference clock with divide-by-2 (25 MHz) has to be
used in X1 pin instead of the 25 MHz crystal, since the clock skew of these two clock sources impacts the RMII timing
before Rev A3 part. The Rev A3 part can connect the external 50 MHz reference clock to X1 pin and SMTXC3/REF-
CLKI_3 pins directly with strap pins of pin 17 SMTXD33/EN_REFCLKO_3 and pin 18 SMTXD32 to be pulled down.
TABLE 3-5:
RMII CLOCK SETTING
Reg.
198
Bit [3]
Pin 17 SMTXD33/
EN_REFCLKO_3
Internal pull-up
Pin 18 SMTXD32
Internal pull-up
(For Rev A3)
Clock Source
Note
External 50 MHz OSC input to EN_REFCLKO_3 = 0 to
SMTXC3 /REFCLKI_3 and X1 disable REFCLKO_3 for
0
0
0
0
(pull down by 1k)
(pull down by 1k)
pin directly
better EMI
50 MHz on X1 pin is as clock EN_REFCLKO_3 = 1 to
source. REFCLKO_3 Output enable REFCLKO_3
is Feedback to REFCLKI_3
0
1
1
(pull down by 1k)
externally
25 MHz on X1 pin is as clock EN_REFCLKO_3 = 1 to
source.
enable REFCLKO_3
0
1
1
1
0
1
REFCLKO_3 Output is
connected to REFCLKI_3
externally
50 MHz on X1 pin, 50 MHz
EN_REFCLKO_3 = 1 to
RMII Clock goes to SMTXC3/ enable REFCLKO_3 and no
1
1
REFCLKI_3 internally.
REFCLKI_3 can be pulled
down by a resistor.
feedback to REFCLKI_3
25 MHz on X1 pin, 50 MHz
EN_REFCLKO_3 = 1 to
RMII Clock goes to SMTXC3/ enable REFCLKO_3 and no
REFCLKI_3 internally.
REFCLKI_3 can be pulled
down by a resistor.
feedback to REFCLKI_3
The RMII provided by KSZ8863RLL is connected to the device’s third MAC and complies with the RMII Specification.
Table 3-6 describes the signals that the RMII bus is using. Refer to RMII Specification for full detail on the signal descrip-
tion.
TABLE 3-6:
RMII SIGNAL DESCRIPTION
Direction (with
Direction (with
RMII Signal
Description
KSZ8863RLL RMII
Signal Direction
RMII Signal Name
respect to PHY)
respect to MAC)
Synchronous 50 MHz
clock reference for
receive, transmit, and
control interface
REF_CLK
CRS_DV
Input
Input or Output
REFCLKI_3 (input)
Carrier sense/
Receive data valid
Output
Input
SMRXDV3 (output)
RXD1
RXD0
Output
Output
Input
Input
Receive data bit 1
Receive data bit 0
SMRXD31 (output)
SMRXD30 (output)
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KSZ8863MLL/FLL/RLL
TABLE 3-6:
RMII SIGNAL DESCRIPTION (CONTINUED)
Direction (with
respect to PHY)
Direction (with
respect to MAC)
RMII Signal
Description
KSZ8863RLL RMII
Signal Direction
RMII Signal Name
TX_EN
TXD1
Input
Input
Output
Output
Transmit enable
Transmit data bit 1
Transmit data bit 0
Receive error
SMTXEN3 (input)
SMTXD31 (input)
SMTXD30 (input)
(not used)
TXD0
Input
Output
RX_ER
Output
Input (not required)
SMTXER3 (input)
Connects to RX_ER
signal of RMII PHY
device
—
—
—
—
KSZ8863RLL filters error frames and, thus, does not implement the RX_ER output signal. To detect error frames from
RMII PHY devices, the SMTXER3 input signal of KSZ8863RLL is connected to the RXER output signal of the RMII PHY
device.
Collision detection is implemented in accordance with the RMII Specification.
In RMII mode, the MII signals (SMTXD3 [3:2] and SMTXER3) can be floating if they are used as default strap options.
The KSZ8863RLL RMII can interface with RMII PHY and RMII MAC devices. The latter allows two KSZ8863RLL
devices to be connected back-to-back. Table 3-7 shows the KSZ8863RLL RMII pin connections with an external RMII
PHY and an external RMII MAC, such as another KSZ8863RLL device.
TABLE 3-7:
RMII SIGNAL CONNECTIONS
KSZ8863RLL
KSZ8863RLL
PHY-MAC Connections
MAC-MAC Connections
Pin Descriptions
External PHY
KSZ8863RLL MAC
Signals
KSZ8863RLL MAC
External MAC
Signals
Signals
Signals
REF_CLK
REFCLKI_3
SMRXDV3
Reference Clock
REFCLKI_3
REF_CLK
CRS_DV
Carrier sense/
Receive data valid
TX_EN
SMRXDV3
TXD1
TXD0
SMRXD31
SMRXD30
SMTXEN3
SMTXD31
SMTXD30
SMTXER3
Receive data bit 1
Receive data bit 0
Transmit enable
Transmit data bit 1
Transmit data bit 0
Receive error
SMRXD31
SMRXD30
SMTXEN3
SMTXD31
SMTXD30
(not used)
RXD1
RXD0
CRS_DV
RXD1
TX_EN
TXD1
RXD0
TXD0
RX_ER
(not used)
3.3.10
MII MANAGEMENT (MIIM) INTERFACE
KSZ8863MLL/FLL/RLL supports the IEEE 802.3 MII Management Interface, also known as the Management Data
Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of
KSZ8863MLL/FLL/RLL. An external device with MDC/MDIO capability is used to read the PHY status or configure the
PHY settings. For further detail on the MIIM interface, see Clause 22.2.4.5 of the IEEE 802.3u Specification, and refer
to 802.3 section 22.3.4 for the timing.
The MIIM interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC)
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8863MLL/FLL/RLL device
• Access to a set of eight 16-bit registers, consisting of six standard MIIM registers [0:5] and two custom MIIM regis-
ters [29, 31]
The MIIM interface can operate up to a maximum clock speed of 5 MHz.
Table 3-8 depicts the MII Management Interface frame format.
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KSZ8863MLL/FLL/RLL
TABLE 3-8:
MII MANAGEMENT FRAME FORMAT
Read/
PHY
REG
Start of
Frame
Preamble
Write OP Address Address TA
Code
Data Bits[15:0]
Idle
Bits [4:0] Bits [4:0]
Read
Write
32 1’s
32 1’s
01
01
10
01
AAAAA
AAAAA
RRRRR Z0
RRRRR 10
DDDDDDDD_DDDDDDDD
DDDDDDDD_DDDDDDDD
Z
Z
3.3.11
SERIAL MANAGEMENT INTERFACE (SMI)
The SMI is the KSZ8863MLL/FLL/RLL non-standard MIIM interface that provides access to all KSZ8863MLL/FLL/RLL
configuration registers. This interface allows an external device to completely monitor and control the states of
KSZ8863MLL/FLL/RLL.
The SMI interface consists of the following:
• A physical connection that incorporates the data line (SDA_MDIO) and the clock line (SCL_MDC)
• A specific protocol that operates across the aforementioned physical connection that allows an external controller
to communicate with the KSZ8863MLL/FLL/RLL device
• Access to all KSZ8863MLL/FLL/RLL configuration registers. Register access includes the Global, Port, and
Advanced Control Registers 0-198 (0x00 – 0xC6), and indirect access to the standard MIIM registers [0:5] and
custom MIIM registers [29, 31]
Table 3-9 depicts the SMI frame format.
TABLE 3-9:
SERIAL MANAGEMENT INTERFACE (SMI) FRAME FORMAT
Read/
PHY
REG
Start of
Frame
Preamble
Write OP Address Address TA
Code
Data Bits [15:0]
Idle
Bits [4:0] Bits [4:0]
Read
Write
32 1’s
32 1’s
01
01
00
00
1xRRR
0xRRR
RRRRR Z0
RRRRR 10
0000_0000_DDDD_DDDD
xxxx_xxxx_DDDD_DDDD
Z
Z
SMI register read access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘1’. SMI register
write access is selected when OP Code is set to “00” and bit 4 of the PHY address is set to ‘0’. PHY address bit [3] is
undefined for SMI register access, and hence can be set to either ‘0’ or ‘1’ in read or write operations.
To access the KSZ8873MLL/FLL/RLL registers 0-196 (0x00 – 0xC6), the following applies:
• PHYAD[2:0] and REGAD[4:0] are concatenated to form the 8-bit address; that is, {PHYAD[2:0], REGAD[4:0]} =
bits [7:0] of the 8-bit address.
• TA bits [1:0] are ‘Z0’ that means the processor MDIO pin is changed to input Hi-Z from Output mode and the fol-
lowing ‘0’ is the read response from the device.
• TA bits [1:0] are set to ‘10’ when write registers.
• Registers are 8 data bits wide.
- For read operation, data bits [15:8] are read back as 0’s.
- For write operation, data bits [15:8] are not defined, and hence can be set to either ‘0’ or ‘1’.
The SMI register access is the same as the MIIM register access, except for the register access requirements presented
in this section.
3.4
Advanced Switch Functions
3.4.1
BYPASS MODE
KSZ8863MLL/FLL/RLL also offers a Bypass mode that enables system-level power saving. When the CPU (connected
to port 3) enters a Power Saving mode of power down or Sleeping mode, the CPU can control pin 24 SMTXER3/
MII_LINK_3, which can be tied high so that KSZ8863MLL/FLL/RLL detects this change and automatically switches to
the Bypass mode. In this mode, the switch function between port 1 and port 2 is sustained. The packets with DA to port
3 are dropped and bypass the internal buffer memory, making the buffer memory more efficient for data transfer between
port 1 and port 2.
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KSZ8863MLL/FLL/RLL
3.4.2
IEEE 802.1Q VLAN SUPPORT
KSZ8863MLL/FLL/RLL supports 16 active VLANs out of the 4096 possible VLANs specified in the IEEE 802.1Q spec-
ification. KSZ8863MLL/FLL/RLL provides a 16-entries VLAN table that converts the 12-bits VLAN ID (VID) to the 4-bits
Filter ID (FID) for address lookup. If a non-tagged or null-VID-tagged packet is received, the ingress port default VID is
used for lookup. In VLAN mode, the lookup process starts with VLAN Table lookup to determine whether the VID is valid.
If the VID is not valid, the packet is dropped and its address is not learned. If the VID is valid, the FID is retrieved for
further lookup. The FID and Destination Address (FID+DA) are used to determine the destination port. The FID and
Source Address (FID+SA) are used for address learning.
TABLE 3-10: FID+DA LOOKUP IN VLAN MODE
DA Found in
Static MAC
Table?
FID+DA Found
in Dynamic
MAC Table?
Use FID Flag?
FID Match?
Action
Broadcast to the membership ports defined
in the VLAN Table bits [18:16]
No
No
Don’t care
Don’t care
Don’t care
Don’t care
No
No
Yes
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
Don’t care
Send to the destination port(s) defined in
the Static MAC Address Table bits [50:48]
Yes
Yes
Yes
Yes
0
1
1
1
Don’t care
No
Broadcast to the membership ports defined
in the VLAN Table bits [18:16]
Send to the destination port defined in the
Dynamic MAC Address Table bits [53:52]
No
Yes
Send to the destination port(s) defined in
the Static MAC Address Table bits [50:48]
Yes
Don’t care
TABLE 3-11: FID+SA LOOKUP IN VLAN MODE
FID+SA Found in Dynamic MAC Table?
Action
No
Learn and add FID+SA to the Dynamic MAC Address Table
Update time stamp
Yes
Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets,” are also supported by
KSZ8863MLL/FLL/RLL. These features can be set on a per-port basis and are defined in register 18, 34, and 50 for
ports 1, 2, and 3, respectively.
3.4.3
QOS PRIORITY SUPPORT
KSZ8863MLL/FLL/RLL provides Quality of Service (QoS) for applications such as VoIP and video conferencing. Offer-
ing four priority queues per port, the per-port transmit queue can be split into four priority queues: Queue 3 is the highest
priority queue and Queue 0 is the lowest priority queue. Bit [0] of registers 16, 32, and 48 is used to enable split transmit
queues for ports 1, 2, and 3, respectively. If a port's transmit queue is not split, high priority and low priority packets have
equal priority in the transmit queue.
There is an additional option to either always deliver high priority packets first or use weighted fair queuing for the four
priority queues. This global option is set and explained in bit [3] of register 5.
3.4.4
PORT-BASED PRIORITY
With port-based priority, each ingress port is individually classified as a high priority receiving port. All packets received
at the high-priority receiving port are marked as high priority and are sent to the high-priority transmit queue if the cor-
responding transmit queue is split. Bits [4:3] of registers 16, 32, and 48 are used to enable port-based priority for ports
1, 2, and 3, respectively.
3.4.5
802.1P-BASED PRIORITY
For 802.1p-based priority, KSZ8863MLL/FLL/RLL examines the ingress (incoming) packets to determine whether they
are tagged. If tagged, the 3-bit priority field in the VLAN tag is retrieved and compared against the “priority mapping”
value, as specified by the registers 12 and 13. The “priority mapping” value is programmable.
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KSZ8863MLL/FLL/RLL
Figure 3-6 illustrates how the 802.1p priority field is embedded in the 802.1Q VLAN tag.
FIGURE 3-6:
802.1P PRIORITY FIELD FORMAT
Bytes
8
6
6
2
2
2
46-1500
Data
4
Preamble
DA
SA
VPID
TCI
length
LLC
FCS
Bits
16
3
1
12
VLAN ID
Tagged Packet Type
(8100 for Ethernet)
802.1p
802.1q VLAN Tag
The 802.1p-based priority is enabled with bit [5] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively.
KSZ8863MLL/FLL/RLL provides the option to insert or remove the header of the priority tagged frame at each individual
egress port. This header, consisting of the 2 bytes VLAN Protocol ID (VPID) and the 2-byte Tag Control Information field
(TCI), is also referred to as the IEEE 802.1Q VLAN tag.
Tag Insertion is enabled by bit [2] of the port registers control 0 and the register 194 to select which source port (ingress
port) PVID can be inserted on the egress port for ports 1, 2, and 3, respectively. At the egress port, untagged packets
are tagged with the ingress port’s default tag. The default tags are programmed in register sets {19,20}, {35,36}, and
{51,52} for ports 1, 2, and 3, respectively; and the source port VID has to be inserted at selected egress ports by bit [5:0]
of register 194. KSZ8863MLL/FLL/RLL does not add tags to already tagged packets.
Tag Removal is enabled by bit [1] of registers 16, 32, and 48 for ports 1, 2, and 3, respectively. At the egress port, tagged
packets will have their 802.1Q VLAN Tags removed. KSZ8863MLL/FLL/RLL does not modify untagged packets.
The CRC is recalculated for both tag insertion and tag removal.
The 802.1p Priority Field Re-mapping is a QoS feature that allows KSZ8863MLL/FLL/RLL to set the “User Priority Ceil-
ing” at any ingress port. If the ingress packet’s priority field has a higher priority value than the default tag’s priority field
of the ingress port, the packet’s priority field is replaced with the default tag’s priority field.
3.4.6
DIFFSERV-BASED PRIORITY
DiffServ-based priority uses the ToS registers (registers 96 to 111) in the Advanced Control Registers section. The ToS
priority control registers implement a fully decoded, 64-bit Differentiated Services Code Point (DSCP) register to deter-
mine packet priority from the 6-bit ToS field in the IP header. When the most significant 6 bits of the ToS field are fully
decoded, the resultant of the 64 possibilities is compared with the corresponding bits in the DSCP register to determine
priority.
3.5
Spanning Tree Support
To support spanning tree, port 3 is designated as the processor port.
The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable,” “receive
enable,” and “learning disable” register settings in registers 18 and 34 for ports 1 and 2, respectively. Table 3-12 shows
the port setting and software actions taken for each of the five spanning tree states.
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KSZ8863MLL/FLL/RLL
TABLE 3-12: SPANNING TREE STATES
State
Port Setting
Software Action
The processor should not send any packets to the port. The
switch may still send specific packets to the processor (pack-
ets that match some entries in the “static MAC table” with
“overriding bit” set) and the processor should discard those
packets. Address learning is disabled on the port in this state.
Disable State
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The port should not for-
ward or receive any pack-
ets. Learning is disabled.
The processor should not send any packets to the port(s) in
this state. The processor should program the “Static MAC
table” with the entries that it needs to receive (for example,
BPDU packets). The “overriding” bit should also be set so that
the switch will forward those specific packets to the processor.
Address learning is disabled on the port in this state.
Blocking State
“transmit enable = 0,
receive enable = 0,
learning disable =1”
Only packets to the pro-
cessor are forwarded.
Learning is disabled.
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets).
The “overriding” bit should be set so that the switch will for-
ward those specific packets to the processor. The processor
may send packets to the port(s) in this state. See Section 3.7,
"Tail Tagging Mode" for details. Address learning is disabled
on the port in this state.
Listening State
Only packets to and from
the processor are for-
warded. Learning is dis-
abled.
“transmit enable = 0,
receive enable = 0,
learning disable =1”
The processor should program the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets).
The “overriding” bit should be set so that the switch will for-
ward those specific packets to the processor. The processor
may send packets to the port(s) in this state. See Section 3.7,
"Tail Tagging Mode" for details. Address learning is enabled
on the port in this state.
Learning State
Only packets to and from
the processor are for-
warded. Learning is
enabled.
“transmit enable = 0,
receive enable = 0,
learning disable = 0”
The processor programs the “Static MAC table” with the
entries that it needs to receive (for example, BPDU packets).
The “overriding” bit is set so that the switch forwards those
specific packets to the processor. The processor can send
packets to the port(s) in this state. See Section 3.7, "Tail Tag-
ging Mode" for details. Address learning is enabled on the port
in this state.
Forwarding State
“transmit enable = 1,
receive enable = 1,
learning disable = 0”
Packets are forwarded
and received normally.
Learning is enabled.
3.6
Rapid Spanning Tree Support
There are three operational states of the Discarding, Learning, and Forwarding assigned to each port for RSTP:
• Discarding ports do not participate in the active topology and do not learn MAC addresses.
- Discarding state: The state includes three states of the disable, blocking, and listening of STP.
- Port setting: “transmit enable = 0, receive enable = 0, learning disable = 1"
- Software action: The processor should not send any packets to the port. The switch may still send specific
packets to the processor (packets that match some entries in the static table with “overriding bit” set), and the
processor should discard those packets. When disabling the port’s learning capability (learning disable=’1’),
set the register 2 bit 5 and bit 4 flushes rapidly the port related entries in the dynamic MAC table and static
MAC table.
Note:
The processor is connected to port 3 via the MII interface. Address learning is disabled on the port in this
state.
• Ports in Learning states learn MAC addresses, but do not forward user traffic.
- Learning state: Only packets to and from the processor are forwarded. Learning is enabled.
- Port setting: “transmit enable = 0, receive enable = 0, learning disable = 0”
- Software action: The processor should program the static MAC table with the entries that it needs to receive
(for example, BPDU packets). The “overriding” bit should be set so that the switch forwards those specific
packets to the processor. The processor may send packets to the port(s) in this state, see Section 3.7, "Tail
Tagging Mode" for details. Address learning is enabled on the port in this state.
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KSZ8863MLL/FLL/RLL
• Ports in Forwarding states fully participate in both data forwarding and MAC learning.
- Forwarding state: Packets are forwarded and received normally. Learning is enabled.
- Port setting: “transmit enable = 1, receive enable = 1, learning disable = 0”
- Software action: The processor should program the static MAC table with the entries that it needs to receive
(for example, BPDU packets). The “overriding” bit should be set so that the switch forwards those specific
packets to the processor. The processor may send packets to the port(s) in this state, see Section 3.7, "Tail
Tagging Mode" for details. Address learning is enabled on the port in this state.
RSTP uses only one type of BPDU called RSTP BPDUs, which are similar to STP Configuration BPDUs with the excep-
tion of a type field set to “version 2” for RSTP and “version 0” for STP, and a flag field carrying additional information.
3.7
Tail Tagging Mode
The Tail Tag is only seen and used by the port 3 interface, which should be connected to a processor. It is an effective
way to retrieve the ingress port information for spanning tree protocol IGMP snooping and other applications. Bit 1 and
bit 0 in the one byte tail tagging is used to indicate the source or destination port in port 3. Bit 3 and bit 2 are used for
the priority setting of the ingress frame in port 3. Other bits are not used. The Tail Tag feature is enabled by setting reg-
ister 3 bit 6.
FIGURE 3-7:
TAIL TAG FRAME FORMAT
Bytes
8
6
6
2
2
2
46-1500
Data
1
4
Preamble
DA
SA
VPID
TCI
length
LLC
Tail Tag
FCS
TABLE 3-13: TAIL TAG RULES
Ingress to Port 3 (Host to KSZ8863)
Bit [1,0]
0,0
Destination Port
Normal (address lookup)
Port 1
0,1
1,0
Port 2
1,1
Port 1 and 2
Frame Priority
Priority 0
Bit [3,2]
0,0
0,1
Priority 1
1,0
Priority 2
1,1
Priority 3
Egress from Port 3 (KSZ8863 to Host)
Bit [0]
Source Port
Port 1
0
1
Port 2
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KSZ8863MLL/FLL/RLL
3.8
IGMP Support
For Internet Group Management Protocol (IGMP) support in layer 2, KSZ8863MLL/FLL/RLL provides two components:
3.8.1
IGMP SNOOPING
KSZ8863MLL/FLL/RLL traps IGMP packets and forwards them only to the processor (port 3). The IGMP packets are
identified as IP packets (either Ethernet IP packets, or IEEE 802.3 SNAP IP packets) with IP version = 0x4 and protocol
version number = 0x2.
3.8.2
IGMP SEND BACK TO THE SUBSCRIBED PORT
Once the host responds to the received IGMP packet, the host should knows the original IGMP ingress port and send
back the IGMP packet to this port only. Otherwise this IGMP packet is broadcasted to all ports to downgrade the perfor-
mance.
Enabling the Tail Tag mode, the host will know the IGMP packet received port from tail tag bits [0] and can send back
the response IGMP packet to this subscribed port by setting the bits [1,0] in the tail tag. Enable “Tail Tag mode” by setting
register 3 bit 6. The tail tag is removed automatically when the IGMP packet is sent out from the subscribed port.
3.9
Port Mirroring Support
KSZ8863MLL/FLL/RLL supports “Port Mirroring” as follows:
• “Receive only” mirror on a port
- All packets received on the port are mirrored on the sniffer port. For example, port 1 is programmed as the
“receive sniff” and port 3 is programmed as the “sniffer port.” A packet received on port 1 is destined to port 2
after the internal lookup. KSZ8863MLL/FLL/RLL forwards the packet to both port 2 and port 3. KSZ8863MLL/
FLL/RLL can also optionally forward “bad” received packets to the “sniffer port.”
• “Transmit only” mirror on a port
- All packets transmitted on the port are mirrored on the sniffer port. For example, port 1 is programmed as the
“transmit sniff” and port 3 is programmed as the “sniffer port.” A packet received on port 2 is destined to port 1
after the internal lookup. KSZ8863MLL/FLL/RLL forwards the packet to both port 1 and port 3.
• “Receive and transmit” mirror on two ports
- All packets received on port A and transmitted on port B are mirrored on the sniffer port. To turn on the “AND”
feature, set register 5 bit [0] to ‘1’. For example, port 1 is programmed as the “receive sniff,” port 2 is pro-
grammed as the “transmit sniff,” and port 3 is programmed as the “sniffer port.” A packet received on port 1 is
destined to port 2 after the internal lookup. KSZ8863MLL/FLL/RLL forwards the packet to both port 2 and port
3.
Multiple ports can be selected as the “receive sniff” or the “transmit sniff.” In addition, any port can be selected as the
“sniffer port.” All these per-port features can be selected through registers 17, 33, and 49 for ports 1, 2, and 3, respec-
tively.
3.10 Rate Limiting Support
KSZ8863MLL/FLL/RLL provides a fine resolution hardware rate limiting from 64 kbps to 99 Mbps. The rate step is
64 kbps when the rate range is from 64 kbps to 960 kbps, and 1 Mbps for 1 Mbps to 100 Mbps (100BT) or to 10 Mbps
(10BT) (refer to Data Rate Limit Table). The rate limit is independent on the “receive side” and on the “transmit side” on
a per-port basis. For 10BASE-T, a rate setting above 10 Mbps means the rate is not limited. On the receive side, the
data receive rate for each priority at each port can be limited by setting up Ingress Rate Control Registers. On the trans-
mit side, the data transmit rate for each priority queue at each port can be limited by setting up Egress Rate Control
Registers. The size of each frame has options to include a minimum IFG (Inter Frame Gap) or a Preamble byte, in addi-
tion to the data field (from packet DA to FCS).
For ingress rate limiting, KSZ8863MLL/FLL/RLL provides options to selectively choose frames from all types, multicast,
broadcast, and flooded unicast frames. KSZ8863MLL/FLL/RLL counts the data rate from those selected type of frames.
Packets are dropped at the ingress port when the data rate exceeds the specified rate limit.
For egress rate limiting, the Leaky Bucket algorithm is applied to each output priority queue for shaping output traffic.
Inter frame gap is stretched on a per-frame base to generate smooth, non-burst egress traffic. The throughput of each
output priority queue is limited by the egress rate specified.
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KSZ8863MLL/FLL/RLL
If any egress queue receives more traffic than the specified egress rate throughput, packets may be accumulated in the
output queue and packet memory. After the memory of the queue or the port is used up, packet dropping or flow control
is triggered. As a result of congestion, the actual egress rate may be dominated by flow control or dropping at the ingress
end, and may be therefore slightly less than the specified egress rate.
To reduce congestion, it is a good practice to make sure the egress bandwidth exceeds the ingress bandwidth.
3.11 Unicast MAC Address Filtering
The unicast MAC address filtering function works in conjunction with the static MAC address table. First, the static MAC
address table is used to assign a dedicated MAC address to a specific port. If a unicast MAC address is not recorded
in the static table, it is also not learned in the dynamic MAC table. KSZ8863MLL/FLL/RLL is then configured with the
option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in
register 14.
This function is useful in preventing the broadcast of unicast packets that could degrade the quality of the port in appli-
cations such as voice over Internet Protocol (VoIP).
3.12 Configuration Interface
KSZ8863MLL/FLL/RLL can operate as both a managed switch and an unmanaged switch.
In Unmanaged mode, KSZ8863MLL/FLL/RLL is typically programmed using an EEPROM. If no EEPROM is present,
KSZ8863MLL/FLL/RLL is configured using its default register settings. Some default settings are configured via strap-
in pin options. The strap-in pins are indicated in the “Pin Description and I/O Assignment” table.
3.12.1
I2C HOST SERIAL BUS CONFIGURATION
With an additional I2C (“2-wire”) EEPROM, KSZ8863MLL/FLL/RLL can perform more advanced switch features like
“broadcast storm protection” and “rate control” without the need of an external processor.
For the KSZ8863MLL/FLL/RLL I2C Host configuration, the EEPROM stores the configuration data for register 0 to reg-
ister 198 (as defined in the KSZ8863MLL/FLL/RLL register map) with the exception of the “Read Only” status registers.
After the deassertion of reset, KSZ8863MLL/FLL/RLL sequentially reads in the configuration data for all 199 registers,
starting from register 0.
FIGURE 3-8:
EEPROM CONFIGURATION TIMING DIAGRAM
....
RST_N
....
....
SCL
SDA
tprgm<15 ms
The following is a sample procedure for programming KSZ8863MLL/FLL/RLL with a pre-configured EEPROM:
1. Connect KSZ8863MLL/FLL/RLL to the EEPROM by joining the SCL and SDA signals of the respective devices.
2. Enable I2C Host mode by setting the KSZ8863MLL/FLL/RLL strap-in pins, P2LED [1:0] to “00”.
3. Check to ensure that the KSZ8863MLL/FLL/RLL reset signal input (RSTN) is properly connected to the external
reset source at the board level.
4. Program the desired configuration data into the EEPROM.
5. Place the EEPROM on the board and power up the board.
6. Assert an active-low reset to the RSTN pin of KSZ8863MLL/FLL/RLL. After reset is deasserted, KSZ8863MLL/
FLL/RLL begins reading the configuration data from the EEPROM. KSZ8863MLL/FLL/RLL checks that the first
byte read from the EEPROM is “88”. If this value is correct, EEPROM configuration continues. If not, EEPROM
configuration access is denied and all other data sent from the EEPROM is ignored by KSZ8863MLL/FLL/RLL.
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KSZ8863MLL/FLL/RLL
3.12.2
I2C CLIENT SERIAL BUS CONFIGURATION
In Managed mode, KSZ8863MLL/FLL/RLL can be configured as an I2C Client device. In this mode, an I2C Host device
(external controller or CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers. Program-
ming access includes Global registers, Port registers, Advanced Control registers, and indirect access to the “Static
MAC Table,” “VLAN Table,” “Dynamic MAC Table,” and “MIB Counters.” The tables and counters are indirectly accessed
via registers 121 to 131.
In I2C Client mode, KSZ8863MLL/FLL/RLL operates like other I2C Client devices. Addressing the KSZ8863MLL/FLL/
RLL’s 8-bit registers is similar to addressing the Microchip AT24C02 EEPROM’s memory locations. Details of I2C read
or write operations and related timing information can be found in the AT24C02 data sheet.
Two fixed 8-bit device addresses are used to address KSZ8863MLL/FLL/RLL in I2C Client mode: one for read operation
and the other for write operation. The addresses are as follows:
• 1011_1111 <read>
• 1011_1110 <write>
The following is a sample procedure for programming KSZ8863MLL/FLL/RLL using the I2C Client serial bus:
1. Enable I2C Client mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED [1:0] to “01”.
2. Power up the board and assert reset to the KSZ8863MLL/FLL/RLL device. Configure the desired register settings
in KSZ8863MLL/FLL/RLL using the I2C write operation.
3. Read back and verify the register settings in KSZ8863MLL/FLL/RLL using the I2C read operation.
Some of the configuration settings, such as “Aging Enable,” “Auto Negotiation Enable,” “Force Speed,” and “Power
down,” can be programmed after the switch has been started.
3.12.3
SPI CLIENT SERIAL BUS CONFIGURATION
In Managed mode, KSZ8863MLL/FLL/RLL can be configured as an SPI Client device. In this mode, an SPI Host device
(external controller or CPU) has complete programming access to the KSZ8863MLL/FLL/RLL’s 198 registers. Program-
ming access includes Global registers, Port registers, Advanced Control registers, and indirect access to the “Static
MAC Table,” “VLAN Table,” “Dynamic MAC Table,” and “MIB Counters”. The tables and counters are indirectly accessed
via registers 121 to 131.
KSZ8863MLL/FLL/RLL supports two standard SPI commands: ‘0000_0011’ for data read and ‘0000_0010’ for data
write. KSZ8863MLL/FLL/RLL also supports SPI multiple read and multiple write to expedite register read back and reg-
ister configuration, respectively.
SPI multiple read is initiated when the Host device continues to drive the KSZ8863MLL/FLL/RLL SPISN input pin (SPI
Client Select signal) low after a byte (a register) is read. The KSZ8863MLL/FLL/RLL internal address counter incre-
ments automatically to the next byte (next register) after the read. The next byte at the next register address is shifted
out onto the KSZ8863MLL/FLL/RLL SPIQ output pin. SPI multiple read continues until the SPI Host device terminates
it by deasserting the SPISN signal to KSZ8863MLL/FLL/RLL.
Similarly, SPI multiple write is initiated when the Host device continues to drive the KSZ8863MLL/FLL/RLL SPISN input
pin low after a byte (a register) is written. The KSZ8863MLL/FLL/RLL internal address counter increments automatically
to the next byte (next register) after the write. The next byte that is sent from the Host device to the KSZ8863MLL/FLL/
RLL SDA input pin is written to the next register address. SPI multiple write continues until the SPI Host device termi-
nates it by deasserting the SPISN signal to KSZ8863MLL/FLL/RLL.
For both SPI multiple read and multiple write, the KSZ8863MLL/FLL/RLLinternal address counter wraps back to register
address zero once the highest register address is reached. This feature allows all 198 KSZ8863MLL/FLL/RLL registers
to be read, or written with a single SPI command from any initial register address.
KSZ8863MLL/FLL/RLL can support SPI bus up to a maximum of 25 MHz. A high performance SPI Host is recom-
mended to prevent internal counter overflow.
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KSZ8863MLL/FLL/RLL
The following is a sample procedure for programming KSZ8863MLL/FLL/RLL using the SPI bus:
1. At the board level, connect the KSZ8863MLL/FLL/RLL pins as follows (Table 3-14):
TABLE 3-14: SPI CONNECTIONS
External Processor Signal
Description
Pin Number
Signal Name
39
36
SPISN
SPI Client Select
SPI Clock
SCL (SPIC)
SPI Data
(Host output Client input)
37
38
SDA (SPID)
SPIQ
SPI Data
(Host input; Client output)
2. Enable SPI Client mode by setting the KSZ8863MLL/FLL/RLL strap-in pins P2LED [1:0] to “10”.
3. Power up the board and assert reset to KSZ8863MLL/FLL/RLL.
4. Configure the desired register settings in KSZ8863MLL/FLL/RLL using the SPI write or multiple write command.
5. Read back and verify the register settings in KSZ8863MLL/FLL/RLL using the SPI read or multiple read com-
mand.
Some of the configuration settings, such as “Aging Enable,” “Auto Negotiation Enable,” “Force Speed,” and “Power
Down,” can be programmed after the switch has been started.
Figure 3-9, Figure 3-10, Figure 3-11, and Figure 3-12 illustrate the SPI data cycles for “Write,” “Read,” “Multiple Write,”
and “Multiple Read.” The read data is registered out of SPIQ on the falling edge of SPIC, and the data input on SPID is
registered on the rising edge of SPIC.
FIGURE 3-9:
SPI WRITE DATA CYCLE
SPIS_N
SPIC
SPID
D7
D6
D5
D4
D3
D2
D1
D0
X
0
0
0
0
0
0
1
0
A7 A6 A5 A4 A3 A2 A1
A0
SPIQ
WRITE COMMAND
WRITE ADDRESS
WRITE DATA
FIGURE 3-10:
SPI READ DATA CYCLE
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
0
A7 A6 A5 A4 A3 A2 A1
A0
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
READ ADDRESS
READ DATA
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KSZ8863MLL/FLL/RLL
FIGURE 3-11:
SPI MULTIPLE WRITE
SPIS_N
SPIC
SPID
D7
D6
D5
D4
D3
D2
D1
D0
X
0
0
0
0
0
0
1
0
A7 A6 A5 A4 A3 A2 A1
A0
SPIQ
WRITE COMMAND
WRITE ADDRESS
Byte 1
SPIS_N
SPIC
SPID
D7
D6
D5
D4
D4
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
SPIQ
Byte 2
Byte 3 ...
Byte N
FIGURE 3-12:
SPI MULTIPLE READ
SPIS_N
SPIC
SPID
X
0
0
0
0
0
0
1
1
A7 A6 A5 A4 A3 A2 A1
A0
X
X
X
X
X
X
X
X
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
READ COMMAND
READ ADDRESS
Byte 1
SPIS_N
SPIC
SPID
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
SPIQ
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Byte 2
Byte 3
Byte N
3.13 Loopback Support
KSZ8863MLL/FLL/RLL provides loopback support for remote diagnostic of failure. In Loopback mode, the speed at both
PHY ports must be set to 100BASE-TX. Two types of loopback are supported: Far-end Loopback and Near-end
(Remote) Loopback.
3.13.1
FAR-END LOOPBACK
Far-end loopback is conducted between KSZ8863MLL/FLL/RLL’s two PHY ports. The loopback is limited to few pack-
ages a time for diagnostic purpose and cannot support large traffic. The loopback path starts at the “Originating” PHY
port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating”
PHY port’s transmit outputs (TXP/TXM).
Bit [0] of registers 29 and 45 is used to enable far-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 0, bit [14] can be used to enable far-end loopback.
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KSZ8863MLL/FLL/RLL
The far-end loopback path is illustrated in Figure 3-13.
FIGURE 3-13:
FAR-END LOOPBACK PATH
RXP /
RXM
TXP /
TXM
Originating
PHY Port
PMD/PMA
PCS
MAC
Switch
MAC
PCS
PMD/PMA
Loop Back
PHY Port
3.13.2
NEAR-END (REMOTE) LOOPBACK
Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2 of KSZ8863MLL/FLL/RLL. The loopback
path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends
at the PHY port’s transmit outputs (TXPx/TXMx).
Bit [1] of registers 26 and 42 is used to enable near-end loopback for ports 1 and 2, respectively. Alternatively, the MII
Management register 31, bit [1] can be used to enable near-end loopback.
The near-end loopback paths are illustrated in Figure 3-14.
FIGURE 3-14:
NEAR-END (REMOTE) LOOPBACK PATH
RXP1/
RXM1
TXP1/
TXM1
PHY
Port 1
PMD/PMA
PCS
MAC
Switch
MAC
PCS
PMD/PMA
PHY
Port 2
TXP2/
TXM2
RXP2/
RXM2
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KSZ8863MLL/FLL/RLL
4.0
REGISTER DESCRIPTIONS
4.1
MII Management (MIIM) Registers
The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I2C, and SMI interfaces can
also be used to access some of these registers. The latter three interfaces use a different mapping mechanism than the
MIIM interface.
The “PHYADs” by default are assigned “0x1” for PHY1 (port 1) and “0x2” for PHY2 (port 2). Additionally, these “PHYADs”
can be programmed to the PHY addresses specified in bits [7:3] of register 15 (0x0F): Global Control 13.
The “REGAD” supported are 0x0-0x5, 0x1D, and 0x1F.
TABLE 4-1:
MIIM REGISTERS FOR KSZ8863MLL/FLL/RLL
Register Number
Description
PHYAD = 0x1, REGAD = 0x0
PHYAD = 0x1, REGAD = 0x1
PHYAD = 0x1, REGAD = 0x2
PHYAD = 0x1, REGAD = 0x3
PHYAD = 0x1, REGAD = 0x4
PHYAD = 0x1, REGAD = 0x5
PHYAD = 0x1, 0x6 – 0x1C
PHYAD = 0x1, 0x1D
PHY1 Basic Control Register
PHY1 Basic Status Register
PHY1 Physical Identifier I
PHY1 Physical Identifier II
PHY1 Auto-Negotiation Advertisement Register
PHY1 Auto-Negotiation Link Partner Ability Register
PHY1 Not supported
PHY1 Not supported
PHYAD = 0x1, 0x1E
PHY1 Not supported
PHYAD = 0x1, 0x1F
PHY1 Special Control/Status
PHY2 Basic Control Register
PHY2 Basic Status Register
PHY2 Physical Identifier I
PHYAD = 0x2, REGAD = 0x0
PHYAD = 0x2, REGAD = 0x1
PHYAD = 0x2, REGAD = 0x2
PHYAD = 0x2, REGAD = 0x3
PHYAD = 0x2, REGAD = 0x4
PHYAD = 0x2, REGAD = 0x5
PHYAD = 0x2, 0x6 – 0x1C
PHYAD = 0x2, 0x1D
PHY2 Physical Identifier II
PHY2 Auto-Negotiation Advertisement Register
PHY2 Auto-Negotiation Link Partner Ability Register
PHY2 Not supported
PHY2 LinkMD Control/Status
PHY2 Not supported
PHYAD = 0x2, 0x1E
PHYAD = 0x2, 0x1F
PHY2 Special Control/Status
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KSZ8863MLL/FLL/RLL
4.2
Register Descriptions
TABLE 4-2:
Bit
REGISTER DESCRIPTIONS
Name
R/W
Description
Default
Reference
PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control
PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control
15
14
Soft Reset
Loopback
RO
Not Supported
0
—
1 = Perform loopback, as indicated:
Port 1 Loopback (reg. 29, bit 0 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
Reg. 29, bit 0
Reg. 45, bit 0
R/W
0
Port 2 Loopback (reg. 45, bit 0 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
0 = Normal operation
1 = 100 Mbps
0 = 10 Mbps
Reg. 28, bit 6
Reg. 44, bit 6
13
12
Force 100
AN Enable
R/W
R/W
0
1
1 = Auto-negotiation enabled
0 = Auto-negotiation disabled
Reg. 28, bit 7
Reg. 44, bit 7
1 = Power down
0 = Normal operation
Reg. 29, bit 3
Reg. 45, bit 3
11
10
9
Power Down
Isolate
R/W
RO
0
0
0
Not Supported
—
1 = Restart auto-negotiation
0 = Normal operation
Reg. 29, bit 5
Reg. 45, bit 5
Restart AN
R/W
Force Full-
Duplex
1 = Full-duplex
0 = Half-duplex
Reg. 28, bit 5
Reg. 44, bit 5
8
R/W
0
7
6
Collision Test
Reserved
RO
RO
Not Supported
—
0
0
—
—
1 = HP Auto MDI/MDI-X mode
0 = Microchip Auto MDI/MDI-X mode
Reg. 31, bit 7
Reg. 47, bit 7
5
Hp_mdix
R/W
1
1 = Force MDI (transmit on RXP/RXM pins)
R/W 0 = Normal operation (transmit on TXP/TXM
pins)
Reg. 29, bit 1
Reg. 45, bit 1
4
Force MDI
0
Disable
MDIX
1 = Disable auto MDI-X
R/W
Reg. 29, bit 2
Reg. 45, bit 2
3
2
1
0
0
0
0
0
0 = Enable auto MDI-X
Disable Far-
End Fault
1 = Disable far-end fault detection
0 = Normal operation
R/W
Reg. 29, bit 4
Disable
Transmit
1 = Disable transmit
R/W
Reg. 29, bit 6
Reg. 45, bit 6
0 = Normal operation
1 = Disable LED
R/W
Reg. 29, bit 7
Reg. 45, bit 7
Disable LED
0 = Normal operation
PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status
PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status
15
14
T4 Capable
RO
RO
0 = Not 100BASE-T4 capable
0
1
—
100 Full
Capable
1 = 100BASE-TX full-duplex capable
0 = Not capable of 100BASE-TX full-duplex
Always 1
100 Half
Capable
1 = 100BASE-TX half-duplex capable
0 = Not 100BASE-TX half-duplex capable
13
12
RO
RO
1
1
Always 1
Always 1
10 Full
Capable
1 = 10BASE-T full-duplex capable
0 = Not 10BASE-T full-duplex capable
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KSZ8863MLL/FLL/RLL
TABLE 4-2:
Bit
REGISTER DESCRIPTIONS (CONTINUED)
Name
R/W
Description
Default
Reference
10 Half
Capable
1 = 10BASE-T half-duplex capable
0 = Not 10BASE-T half-duplex capable
11
10-7
6
RO
RO
RO
1
0000
0
Always 1
Reserved
—
—
—
Preamble
Suppressed
Not Supported
1 = Auto-negotiation complete
0 = Auto-negotiation not completed
Reg. 30, bit 6
Reg. 46, bit 6
5
4
3
AN Complete
RO
RO
RO
0
0
1
Far-End
Fault
1 = Far-end fault detected
0 = No far-end fault detected
Reg. 31, bit 0
1 = Auto-negotiation capable
0 = Not auto-negotiation capable
Reg. 28, bit 7
Reg. 44, bit 7
AN Capable
1 = Link is up
0 = Link is down
Reg. 30, bit 5
Reg. 46, bit 5
2
1
0
Link Status
Jabber Test
RO
RO
RO
0
0
0
Not Supported
—
Extended
Capable
0 = Not extended register capable
—
PHY1 Register 2 (PHYAD = 0x1, REGAD = 0x2): PHYID High
PHY2 Register 2 (PHYAD = 0x2, REGAD = 0x2): PHYID High
15-0
15-0
PHYID High
PHYID Low
RO
High order PHYID bits
0x0022
—
—
PHY1 Register 3 (PHYAD = 0x1, REGAD = 0x3): PHYID Low
PHY2 Register 3 (PHYAD = 0x2, REGAD = 0x3): PHYID Low
RO
Low order PHYID bits
0x1430
PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability
PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability
15
14
Next Page
Reserved
RO
RO
RO
RO
Not Supported
0
0
—
—
—
—
—
13
Remote Fault
Reserved
Not Supported
—
0
12-11
00
1 = Advertise pause ability
0 = Do not advertise pause ability
Reg. 28, bit 4
Reg. 44, bit 4
10
9
Pause
R/W
R/W
R/W
1
0
1
Reserved
Adv 100 Full
—
—
1 = Advertise 100 full-duplex ability
0 = Do not advertise 100 full-duplex ability
Reg. 28, bit 3
Reg. 44, bit 3
8
1 = Advertise 100 half-duplex ability
0 = Do not advertise 100 half-duplex ability
Reg. 28, bit 2
Reg. 44, bit 2
7
6
Adv 100 Half
Adv 10 Full
Adv 10 Half
R/W
R/W
R/W
RO
1
1 = Advertise 10 full-duplex ability
0 = Do not advertise 10 full-duplex ability
Reg. 28, bit 1
Reg. 44, bit 1
1
1
1 = Advertise 10 half-duplex ability
0 = Do not advertise 10 half-duplex ability
Reg. 28, bit 0
Reg. 44, bit 0
5
Selector
Field
4-0
802.3
00001
—
PHY1 Register 5 (PHYAD = 0x1, REGAD = 0x5): Auto-Negotiation Link Partner Ability
PHY2 Register 5 (PHYAD = 0x2, REGAD = 0x5): Auto-Negotiation Link Partner Ability
15
14
Next Page
LP ACK
RO
RO
RO
RO
Not Supported
Not Supported
Not Supported
—
0
0
—
—
—
—
13
Remote Fault
Reserved
0
12-11
00
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KSZ8863MLL/FLL/RLL
TABLE 4-2:
Bit
REGISTER DESCRIPTIONS (CONTINUED)
Name
R/W
Description
Default
Reference
Reg. 30, bit 4
Reg. 46, bit 4
10
9
Pause
RO
RO
RO
Link partner pause capability
0
0
0
Reserved
—
—
Reg. 30, bit 3
Reg. 46, bit 3
8
Adv 100 Full
Link partner 100 full-duplex capability
Reg. 30, bit 2
Reg. 46, bit 2
7
6
Adv 100 Half
Adv 10 Full
RO
RO
Link partner 100 half-duplex capability
Link partner 10 full-duplex capability
0
0
Reg. 30, bit 1
Reg. 46, bit 1
Reg. 30, bit 0
Reg. 46, bit 0
5
Adv 10 Half
Reserved
RO
RO
Link partner 10 half-duplex capability
—
0
4-0
00000
—
PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status
PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status
1 = Enable cable diagnostic. After VCT test
has completed, this bit will be self-cleared.
R/W
15
Vct_enable
0 = Indicate cable diagnostic test (if enabled)
has completed and the status information is
valid for read.
0
Reg. 42, bit 4
(SC)
RO
00 = Normal condition
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failed
14-13
Vct_result
00
Reg 42, bit[6:5]
Vct 10M
Short
12
RO
RO
1 = Less than 10 meter short
Reserved
0
Reg. 42, bit 7
—
11-9
Reserved
000
{(Reg. 42, bit 0)
(Reg. 43,
Vct_-
fault_count
Distance to the fault.
It’s approximately 0.4m*vct_fault_count[8:0]
8-0
RO
{0, (0x00)}
bit[7:0])}
PHY1 Register 31 (PHYAD = 0x1, REGAD = 0x1F): PHY Special Control/Status
PHY2 Register 31 (PHYAD = 0x2, REGAD = 0x1F): PHY Special Control/Status
15-6
5
Reserved
RO
Reserved
{(0x00),00}
—
Reg. 31, bit 5
Reg. 47, bit 5
Note that this bit
is only valid for
10BT.
1 = polarity is reversed
0 = polarity is not reversed
Polrvs
RO
0
1 = MDI
0 = MDI-X
Reg. 30, bit 7
Reg. 46, bit 7
4
3
2
MDI-X status
Force_lnk
Pwrsave
RO
R/W
R/W
0
0
1
1 = Force link pass
0 = Normal Operation
Reg. 26, bit 3
Reg. 42, bit 3
0 = Enable power saving
1 = Disable power saving
Reg. 26, bit 2
Reg. 42, bit 2
2017-2021 Microchip Technology Inc.
DS00002335C-page 39
KSZ8863MLL/FLL/RLL
TABLE 4-2:
Bit
REGISTER DESCRIPTIONS (CONTINUED)
Name
R/W
Description
Default
Reference
1 = Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
Remote
Loopback
Reg. 26, bit 1
Reg. 42, bit 1
1
0
R/W
0
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
0 = Normal Operation
Reserved
Do not change the default value.
Reserved
R/W
0
—
4.3
Memory Map (8-Bit Registers)
TABLE 4-3:
GLOBAL REGISTERS
Register (Decimal)
Register (Hex)
Description
Description
0-1
0x00-0x01
0x02-0x0F
Chip ID Register
2-15
Global Control Register
TABLE 4-4:
PORT REGISTERS
Register (Decimal)
Register (Hex)
16-29
30-31
32-45
46-47
48-57
58-62
63
0x10-0x1D
0x1E-0x1F
0x20-0x2D
0x2E-0x2F
0x30-0x39
0x3A-0x3E
0x3F
Port 1 Control Registers, including MII PHY Registers
Port 1 Status Registers, including MII PHY Registers
Port 2 Control Registers, including MII PHY Registers
Port 2 Status Registers, including MII PHY Registers
Port 3 Control Registers
Reserved
Port 3 Status Register
64-95
0x40-0x5F
Reserved
TABLE 4-5:
ADVANCED CONTROL REGISTERS
Register (Decimal)
Register (Hex)
Description
TOS Priority Control Registers
96-111
112-117
118-120
121-122
123-131
142-153
154-165
166
0x60-0x6F
0x70-0x75
0x76-0x78
0x79-0x7A
0x7B-0x83
0x8E-0x99
0x9A-0xA5
0xA6
Switch Engine’s MAC Address Registers
User Defined Registers
Indirect Access Control Registers
Indirect Data Registers
Station Address
Egress Data Rate Limit
Device Mode Indicator
167-170
171-174
175-186
187-188
189
0xA7-0xAA
0xAB-0xAE
0xAF-0xBA
0xBB-0xBC
0xBD
High Priority Packet Buffer Reserved
PM Usage Flow Control Select Mode
TXQ Split
Link Change Interrupt Register
Force Pause Off Iteration Limit Enable
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2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
TABLE 4-5:
ADVANCED CONTROL REGISTERS (CONTINUED)
Register (Decimal)
Register (Hex)
Description
192
194
195
196
198
0xC0
0xC2
0xC3
0xC4
0xC6
Fiber Signal Threshold
Insert SRC PVID
Power Management and LED Mode
Sleep Mode
Forward Invalid VID Frame and Host Mode
4.4
Register Descriptions
TABLE 4-6:
Bit
GLOBAL REGISTERS (0-15)
Name
R/W
Description
Register 0 (0x00): Chip ID0
Chip family
Default
7-0
Family ID
RO
0x88
Register 1 (0x01): Chip ID1/Start Switch
7-4
3-1
Chip ID
RO
RO
0x3 is assigned to M series. (73M)
Revision ID
0x3
—
Revision ID
1 = start the switch (default)
0 = stop the switch
0
Start Switch
R/W
1
Register 2 (0x02): Global Control 0
New back-off algorithm designed for UNH
1 = Enable
0 = Disable
New Back-Off
Enable
7
6
5
R/W
0
0
0
Reserved
RO
Reserved
1 = enable flush dynamic MAC table for spanning tree
application
0 = disable
Flush Dynamic MAC
Table
R/W
1 = enable flush static MAC table for spanning tree
application
0 = disable
Flush Static MAC
Table
4
R/W
0
Pass Flow Control
Packet
1 = switch will pass 802.1x flow control packets
0 = switch will drop 802.1x flow control packets
3
2
R/W
R/W
0
0
Reserved
Do not change the default value.
Reserved
Reserved
Do not change the default value.
1
0
Reserved
Reserved
R/W
RO
0
0
Reserved
Register 3 (0x03): Global Control 1
1 = switch all packets including bad ones. Used solely
7
6
Pass All Frames
R/W
for debugging purposes. Works in conjunction with
Sniffer mode only.
0
0
Port 3 Tail Tag Mode
Enable
1 = Enable port 3 Tail Tag mode.
0 = Disable
R/W
R/W
1 = will enable transmit direction flow control feature.
0 = will not enable transmit direction flow control fea-
ture. Switch will not generate any flow control
(PAUSE) frame.
IEEE 802.3x
Transmit Direction
Flow Control Enable
5
1
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KSZ8863MLL/FLL/RLL
TABLE 4-6:
Bit
GLOBAL REGISTERS (0-15) (CONTINUED)
Name
R/W
Description
Default
1 = will enable receive direction flow control feature.
0 = will not enable receive direction flow control fea-
ture. Switch will not react to any flow control (PAUSE)
frame it receives.
IEEE 802.3x
Receive Direction
Flow Control Enable
4
3
R/W
1
1 = will check frame length field in the IEEE packets. If
the actual length does not match, the packet will be
dropped (for Length/Type field < 1500).
0 = will not check
Frame Length Field
Check
R/W
0
1 = enable age function in the chip
0 = disable age function in the chip
2
1
Aging Enable
R/W
R/W
1
0
Fast Age Enable
1 = turn on fast age (800 µs)
1 = enable more aggressive back off algorithm in Half-
Duplex mode to enhance performance. This is not an
IEEE standard.
Aggressive Back-Off
Enable
0
R/W
0
Register 4 (0x04): Global Control 2
This feature is used with port-VLAN (described in reg.
17, reg. 33, etc.)
1 = all packets can not cross VLAN boundary
0 = unicast packets (excluding unknown/multicast/
broadcast) can cross VLAN boundary
Unicast Port-VLAN
Mismatch Discard
7
R/W
1
Note:
Port mirroring is not supported if this bit is
set to “0”.
1 = Broadcast Storm Protection does not include
multicast packets. Only DA = FF-FF-FF-FF-FF-FF
packets will be regulated.
0 = Broadcast Storm Protection includes DA = FF-FF-
FF-FF-FF-FF and DA[40] = 1 packets.
Multicast Storm
Protection Disable
6
5
R/W
R/W
1
1
1 = carrier sense based back pressure is selected
0 = collision based back pressure is selected
Back Pressure Mode
1 = Fair mode is selected. In this mode, if a flow con-
trol port and a non-flow control port talk to the same
destination port, packets from the non-flow control
port may be dropped. This is to prevent the flow con-
trol port from being flow controlled for an extended
period of time.
0 = In this mode, if a flow control port and a non-flow
control port talk to the same destination port, the flow
control port will be flow controlled. This may not be
“fair” to the flow control port.
Flow Control and
Back Pressure Fair
Mode
4
R/W
1
1 = the switch will not drop packets when 16 or more
collisions occur.
0 = the switch will drop packets when 16 or more colli-
sions occur.
No Excessive
Collision Drop
3
2
R/W
R/W
0
0
1 = will accept packet sizes up to 1916 bytes (inclu-
sive). This bit setting will override setting from bit 1 of
this register.
0 = the max packet size will be determined by bit 1 of
this register.
Huge Packet
Support
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KSZ8863MLL/FLL/RLL
TABLE 4-6:
Bit
GLOBAL REGISTERS (0-15) (CONTINUED)
Name
R/W
Description
Default
0 = will accept packet sizes up to 1536 bytes (inclu-
sive).
1 = 1522 bytes for tagged packets, 1518 bytes for
untagged packets. Any packets larger than the speci-
fied value will be dropped.
Legal Maximum
Packet Size Check
Enable
1
0
R/W
0
Reserved
Do not change the default value.
Reserved
R/W
0
Register 5 (0x05): Global Control 3
1 = 802.1Q VLAN mode is turned on. VLAN table
needs to set up before the operation.
0 = 802.1Q VLAN is disabled.
802.1Q VLAN
Enable
7
6
R/W
0
0
IGMP Snoop Enable
on Switch MII
Interface
1 = IGMP snoop is enabled. All IGMP packets will be
forwarded to the Switch MII port.
0 = IGMP snoop is disabled.
R/w
Reserved
Do not change the default values.
5
4
Reserved
Reserved
RO
RO
0
0
Reserved
Do not change the default values.
0 = Priority method set by the registers 175-186 bit [7]
= 0 for port 1, port 2 and port 3.
1 = Weighted Fair Queuing enabled. When all four
queues have packets waiting to transmit, the band-
width allocation is q3:q2:q1:q0 = 8:4:2:1.
Weighted Fair
Queue Enable
3
R/W
0
If any queues are empty, the highest non-empty
queue gets one more weighting. For example, if q2 is
empty, q3:q2:q1:q0 becomes (8+1):0:2:1.
Reserved
Do not change the default values.
2
1
Reserved
Reserved
RO
RO
0
0
Reserved
Do not change the default values.
1 = will do RX AND TX sniff (both source port and
destination port need to match)
0
Sniff Mode Select
Reserved
R/W
0 = will do RX OR TX sniff (either source port or desti-
nation port needs to match). This is the mode used to
implement RX only sniff.
0
Register 6 (0x06): Global Control 4
Reserved
Do not change the default values.
7
6
RO
0
0
Switch MII Half-
Duplex Mode
1 = enable MII interface Half-Duplex mode.
0 = enable MII interface Full-Duplex mode.
R/W
R/W
1 = enable full-duplex flow control on Switch MII inter-
face.
0 = disable full-duplex flow control on Switch MII inter-
Switch MII Flow
Control Enable
5
1
face.
1 = the switch interface is in 10 Mbps mode
0 = the switch interface is in 100 Mbps mode
4
3
Switch MII 10BT
R/W
R/W
0
0
Null VID
Replacement
1 = will replace NULL VID with port VID (12 bits)
0 = no replacement for NULL VID
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DS00002335C-page 43
KSZ8863MLL/FLL/RLL
TABLE 4-6:
Bit
GLOBAL REGISTERS (0-15) (CONTINUED)
Name
R/W
Description
Default
This register along with the next register determines
how many “64 byte blocks” of packet data are allowed
on an input port in a preset period. The period is
67 ms for 100BT or 500 ms for 10BT. The default is
1%.
Broadcast Storm
Protection Rate
Bit [10:8]
2-0
R/W
000
Note:
100BT Rate: 148,800 frames/sec*67 ms/
interval*1% = 99 frames/interval (approx.)
= 0x63
Register 7 (0x07): Global Control 5
This register along with the previous register deter-
mines how many “64 byte blocks” of packet data are
allowed on an input port in a preset period. The period
is 67 ms for 100BT or 500 ms for 10BT. The default is
Broadcast Storm
Protection Rate
Bit [7:0]
7-0
R/W
0x63
1%.
Note:
100BT Rate: 148,800 frames/sec*67 ms/
interval*1% = 99 frames/interval (approx.)
= 0x63
Register 8 (0x08): Global Control 6
Reserved
7-0
7-0
7-0
Factory Testing
Factory Testing
Factory Testing
RO
0x00
0x24
0x35
Do not change the default values.
Register 9 (0x09): Global Control 7
Reserved
Do not change the default values.
Register 10 (0x0A): Global Control 8
Reserved
RO
RO
Do not change the default values.
Register 11 (0x0B): Global Control 9
00 = 31.25 MHz supports SPI speed below 6 MHz
01 = 62.5 MHz supports SPI speed between 6 MHz to
12.5 MHz
CPU interface Clock
Selection
10 = 125 MHz supports SPI speed above 12.5 MHz
7-6
R/W
10
Note:
Lower clock speed will save more power
consumption, It is better set to 31.25 MHz
if SPI does not request a high speed.
5-4
3-2
1
Reserved
Reserved
Reserved
Reserved
RO
RO
RO
RO
N/A Don’t Change
N/A Don’t Change
N/A Don’t Change
N/A Don’t Change
00
10
0
0
0
Register 12 (0x0C): Global Control 10
IEEE 802.1p mapping. The value in this field is used
7-6
5-4
3-2
Tag_0x3
Tag_0x2
Tag_0x1
R/W
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x3.
01
01
00
IEEE 802.1p mapping. The value in this field is used
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x2.
R/W
R/W
IEEE 802.1p mapping. The value in this field is used
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x1.
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KSZ8863MLL/FLL/RLL
TABLE 4-6:
Bit
GLOBAL REGISTERS (0-15) (CONTINUED)
Name
R/W
Description
Default
IEEE 802.1p mapping. The value in this field is used
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x0.
1-0
Tag_0x0
R/W
00
Register 13 (0x0D): Global Control 11
IEEE 802.1p mapping. The value in this field is used
7-6
5-4
3-2
1-0
Tag_0x7
R/W
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x7.
11
11
10
10
IEEE 802.1p mapping. The value in this field is used
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x6.
Tag_0x6
Tag_0x5
Tag_0x4
R/W
R/W
R/W
IEEE 802.1p mapping. The value in this field is used
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x5.
IEEE 802.1p mapping. The value in this field is used
as the frame’s priority when its IEEE 802.1p tag has a
value of 0x4.
Register 14 (0x0E): Global Control 12
Send packets with unknown destination MAC
addresses to specified port(s) in bits [2:0] of this regis-
ter.
0 = disable
1 = enable
Unknown Packet
Default Port Enable
7
R/W
0
Drive Strength of I/O
Pad
1: 16 mA
0: 8 mA
6
5
4
3
R/W
RO
RO
RO
1
0
0
0
Reserved
Do not change the default values.
Reserved
Reserved
Reserved
Reserved
Do not change the default values.
Reserved
Do not change the default values.
Specify which port(s) to send packets with unknown
destination MAC addresses. This feature is enabled
by bit [7] of this register.
Bit 2 stands for port 3.
Bit 1 stands for port 2.
Bit 0 stands for port 1.
Unknown Packet
Default Port
2-0
R/W
111
A ‘1’ includes a port.
A ‘0’ excludes a port.
Register 15 (0x0F): Global Control 13
00000: N/A
00001: Port 1 PHY address is 0x1
00010: Port 1 PHY address is 0x2
…
11101: Port 1 PHY address is 0x29
11110: N/A
11111: N/A
7-3
2-0
PHY Address
Reserved
R/W
RO
00001
Note:
Port 2 PHY address = (Port 1 PHY
address) + 1
Reserved
Do not change the default values.
000
2017-2021 Microchip Technology Inc.
DS00002335C-page 45
KSZ8863MLL/FLL/RLL
The following registers are used to enable features that are assigned on a per-port basis. The register bit assignments
are the same for all ports, but the address for each port is different, as indicated.
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95)
Name
R/W
Description
Default
Register 16 (0x10): Port 1 Control 0
Register 32 (0x20): Port 2 Control 0
Register 48 (0x30): Port 3 Control 0
1 = enable broadcast storm protection for ingress
packets on port
0 = disable broadcast storm protection
Broadcast Storm
Protection Enable
7
6
5
R/W
0
0
0
1 = enable DiffServ priority classification for ingress
packets (IPv4) on port
0 = disable DiffServ function
DiffServ Priority
Classification Enable
R/W
R/W
1 = enable 802.1p priority classification for ingress
packets on port
0 = disable 802.1p
802.1p Priority Clas-
sification Enable
00 = ingress packets on port will be
classified as priority 0 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
01 = ingress packets on port will be
classified as priority 1 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
10 = ingress packets on port will be
classified as priority 2 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
11 = ingress packets on port will be
Port-based Priority
Classification
4-3
R/W
00
classified as priority 3 queue if “Diffserv” or “802.1p”
classification is not enabled or fails to classify.
Note:
“DiffServ”, “802.1p” and port priority can
be enabled at the same time. The OR’ed
result of 802.1p and DSCP overwrites the
port priority.
1 = when packets are output on the port, the switch
will add 802.1p/q tags to packets without 802.1p/q
tags when received. The switch will not add tags to
packets already tagged. The tag inserted is the
ingress port’s “port VID”.
2
Tag Insertion
R/W
0
0 = disable tag insertion
Note:
For the tag insertion available, the register
194 bits [5:0] have to be set first.
1 = when packets are output on the port, the switch
will remove 802.1p/q tags from packets with 802.1p/q
tags when received. The switch will not modify pack-
ets received without tags.
1
0
Tag Removal
R/W
R/W
0
0
0 = disable tag removal
1 = split TXQ to 4 queue configuration. It cannot be
enable at the same time with split 2 queue at register
18, 34, 50 bit 7.
TXQ Split Enable
0 = no split, treated as 1 queue configuration
DS00002335C-page 46
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KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
Register 17 (0x11): Port 1 Control 1
Register 33 (0x21): Port 2 Control 1
Register 49 (0x31): Port 3 Control 1
1 = Port is designated as sniffer port and will transmit
7
6
Sniffer Port
R/W
packets that are monitored.
0 = Port is a normal port
0
0
1 = All packets received on the port will be marked as
“monitored packets” and forwarded to the designated
“sniffer port”
Receive Sniff
Transmit Sniff
Double Tag
R/W
R/W
R/W
0 = no receive monitoring
1 = All packets transmitted on the port will be marked
as “monitored packets” and forwarded to the desig-
nated “sniffer port”
5
4
0
0
0 = no transmit monitoring
1 = All packets will be tagged with port default tag of
ingress port regardless of the original packets are
tagged or not
0 = do not double tagged on all packets
1 = if the packet’s “user priority field” is greater than
the “user priority field” in the port default tag register,
replace the packet’s “user priority field” with the “user
priority field” in the port default tag register.
0 = do not compare and replace the packet’s ‘user pri-
ority field”
3
User Priority Ceiling
R/W
R/W
0
Define the port’s egress port VLAN membership. The
port can only communicate within the membership. Bit
2 stands for port 3, bit 1 stands for port 2, bit 0 stands
for port 1.
Port VLAN
Membership
2-0
111
An ‘1’ includes a port in the membership.
An ‘0’ excludes a port from membership.
Register 18 (0x12): Port 1 Control 2
Register 34 (0x22): Port 2 Control 2
Register 50 (0x32): Port 3 Control 2
1 = Enable
Enable2 Queue Split
of Tx Queue
It cannot be enable at the same time with split 4
queue at register 16, 32, and 48 bit 0.
0 = Disable
7
R/W
0
1 = the switch will discard packets whose VID port
membership in VLAN table bits [18:16] does not
include the ingress port.
Ingress VLAN
Filtering
6
5
R/W
R/W
0
0
0 = no ingress VLAN filtering.
1 = the switch will discard packets whose VID does
not match ingress port default VID.
0 = no packets will be discarded
Discard non-PVID
Packets
2017-2021 Microchip Technology Inc.
DS00002335C-page 47
KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
Pin value during
reset:
For port 1, SPIQ
pin (default is
PD)
1 = will always enable full-duplex flow control on the
port, regardless of AN result.
For port 2,
4
Force Flow Control
R/W
0 = full-duplex flow control is enabled based on AN
result.
SMRXD30 pin
For port 3, this
bit has no
meaning. Flow
Control is set by
Reg. 6, bit 5.
Back Pressure
Enable
1 = enable port’s half-duplex back pressure
0 = disable port’s half-duplex back pressure
3
2
R/W
R/W
0
1 = enable packet transmission on the port
0 = disable packet transmission on the port
Transmit Enable
Receive Enable
Learning Disable
1
Note:
This bit is used for spanning tree support.
1 = enable packet reception on the port
0 = disable packet reception on the port
1
0
R/W
R/W
1
0
Note:
This bit is used for spanning tree support.
1 = disable switch address learning capability
0 = enable switch address learning
Note:
This bit is used for spanning tree support.
Register 19 (0x13): Port 1 Control 3
Register 35 (0x23): Port 2 Control 3
Register 51 (0x33): Port 3 Control 3
Port’s default tag, containing
7-5 = User priority bits
4 = CFI bit
7-0
Default Tag [15:8]
Default Tag [7:0]
R/W
0x00
0x01
3-0 = VID[11:8]
Register 20 (0x14): Port 1 Control 4
Register 36 (0x24): Port 2 Control 4
Register 52 (0x34): Port 3 Control 4
7-0
R/W
Port’s default tag, containing 7-0: VID[7:0]
Note:
Registers 19 and 20 (and those corresponding to other ports) serve two purposes:
Associated with the ingress untagged packets, and used for egress tagging.
Default VID for the ingress untagged or null-VID-tagged packets, and used for address lookup.
Register 21 (0x15): Port 1 Control 5
Register 37 (0x25): Port 2 Control 5
Register 53 (0x35): Port 3 Control 5
1 = Port 3 MII MAC mode
0 = Port 3 MII PHY mode
Port 3 MII Mode
Selection
7
6
R/W
Note:
This bit should be set for port 1, Register
21 bit [7] = ‘1’ for normal operation.
0
0
This bit is reserved for port 2.
Self-Address Filter-
ing Enable MACA1
(not for 0x35)
1 = enable port 1 self-address filtering MACA1
0 = disable
R/W
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KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
Self-Address Filter-
ing Enable MACA2
(not for 0x35)
1 = enable port 2 self-address filtering MACA2
0 = disable
5
4
R/W
0
Drop Ingress Tagged
Frame
1 = Enable
0 = Disable
R/W
R/W
0
Ingress Limit Mode
These bits determine what kinds of frames are limited
and counted against ingress rate limiting.
00 = limit and count all frames
01 = limit and count Broadcast, Multicast, and flooded
unicast frames
3-2
Limit Mode
00
10 = limit and count Broadcast and Multicast frames
only
11 = limit and count Broadcast frames only
Count IFG bytes
1 = each frame’s minimum inter frame gap
(IFG) bytes (12 per frame) are included in Ingress and
Egress rate limiting calculations.
0 = IFG bytes are not counted.
1
0
Count IFG
Count Pre
R/W
R/W
0
0
Count Preamble bytes
1 = each frame’s preamble bytes (8 per frame) are
included in Ingress and Egress rate limiting calcula-
tions.
0 = preamble bytes are not counted.
Register 22 [6:0] (0x16): Port 1 Q0 Ingress Data Rate Limit
Register 38 [6:0] (0x26): Port 2 Q0 Ingress Data Rate Limit
Register 54 [6:0] (0x36): Port 3 Q0 Ingress Data Rate Limit
0
1: Port 3 inverted refclk selected
0: Port 3 original refclk selected
Note: Not
applied to
RMII REFCLK
INVERT
7
R/W
Reg.22 and 38
(Port 1, Port 2)
Note:
Bit 7 is reserved for port 1 and port 2
Ingress data rate limit for priority 0 frames
Ingress traffic from this priority queue is shaped
according to the ingress Data Rate Selected Table.
Q0 Ingress Data
Rate Limit
6-0
R/W
0
Register 23 [6:0] (0x17): Port 1 Q1 Ingress Data Rate Limit
Register 39 [6:0] (0x27): Port 2 Q1 Ingress Data Rate Limit
Register 55 [6:0] (0x37): Port 3 Q1 Ingress Data Rate Limit
Reserved
R/W
7
Reserved
0
0
Do not change the default values.
Ingress data rate limit for priority 1 frames
Q1 Ingress Data
Rate Limit
6-0
R/W
Ingress traffic from this priority queue is shaped
according to the ingress Data Rate Selected Table.
Register 24 [6:0] (0x18): Port 1 Q2 Ingress Data Rate Limit
Register 40 [6:0] (0x28): Port 2 Q2 Ingress Data Rate Limit
Register 56 [6:0] (0x38): Port 3 Q2 Ingress Data Rate Limit
Reserved
R/W
7
Reserved
0
0
Do not change the default values.
Ingress data rate limit for priority 2 frames
Q2 Ingress Data
Rate Limit
6-0
R/W
Ingress traffic from this priority queue is shaped
according to ingress Data Rate Selection Table.
2017-2021 Microchip Technology Inc.
DS00002335C-page 49
KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
Register 25 [6:0] (0x19): Port 1 Q3 Ingress Data Rate Limit
Register 41 [6:0] (0x29): Port 2 Q3 Ingress Data Rate Limit
Register 57 [6:0] (0x39): Port 3 Q3 Ingress Data Rate Limit
Reserved
Do not change the default values.
7
Reserved
RO
0
0
Ingress data rate limit for priority 3 frames
Ingress traffic from this priority queue is shaped
according to ingress Data Rate Selection Table.
Q3 Ingress Data
Rate Limit
6-0
R/W
Note:
Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be
accessed with the MIIM PHY registers.
Register 26 (0x1A): Port 1 PHY Special Control/Status
Register 42 (0x2A): Port 2 PHY Special Control/Status
Register 58 (0x3A): Reserved, Not Applicable to Port 3
7
Vct 10M Short
Vct_result
RO
1 = Less than 10 meter short
0
00 = Normal condition
01 = Open condition detected in cable
10 = Short condition detected in cable
11 = Cable diagnostic test has failed
6-5
RO
00
1 = Enable cable diagnostic test. After VCT test has
completed, this bit will be self-cleared.
0 = Indicate cable diagnostic test (if enabled) has
completed and the status information is valid for read.
R/W
(SC)
4
Vct_en
0
1 = Force link pass
0 = Normal Operation
3
2
Force_lnk
Reserved
R/W
RO
0
0
Reserved
Do not change the default value.
1 = Perform Remote loopback, as follows:
Port 1 (reg. 26, bit 1 = ‘1’)
Start: RXP1/RXM1 (port 1)
Loopback: PMD/PMA of port 1’s PHY
End: TXP1/TXM1 (port 1)
1
0
Remote Loopback
Vct_fault_count[8]
R/W
0
0
Port 2 (reg. 42, bit 1 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 2’s PHY
End: TXP2/TXM2 (port 2)
0 = Normal Operation
Bit[8] of VCT fault count
Distance to the fault.
RO
It is approximately 0.4m*vct_fault_count[8:0].
Register 27 (0x1B): Port 1 LinkMD Result
Register 43 (0x2B): Port 2 LinkMD Result
Register 59 (0x3B): Reserved, Not Applicable to Port 3
Bits[7:0] of VCT fault count
7-0
Vct_fault_count[7:0]
RO
Distance to the fault.
0x00
It is approximately 0.4m*Vct_fault_count[8:0].
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KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
Register 28 (0x1C): Port 1 Control 12
Register 44 (0x2C): Port 2 Control 12
Register 60 (0x3C): Reserved, Not Applicable to Port 3
1
For port 1,
P1LED0 pin
value during
reset.
(default is PD)
For port 2,
SMRXD33 pin
value during
reset
1 = auto negotiation is on
0 = disable auto negotiation; speed and duplex are
determined by bits 6 and 5 of this register.
Auto Negotiation
Enable
7
R/W
1
For port 1,
P1LED1 pin
value during
reset.
For port 2,
SMRXD32 pin
value during
reset.
1 = forced 100BT if AN is disabled (bit 7)
0 = forced 10BT if AN is disabled (bit 7)
6
Force Speed
R/W
1
1 = forced full-duplex if (1) AN is disabled or (2) AN is
enabled but failed.
0 = forced half-duplex if (1) AN is disabled or (2) AN is
enabled but failed.
For port 1,
SMRXDV3 pin
value during
reset.
For port 2,
SMRXD31 pin
value during
reset.
5
Force Duplex
R/W
Note:
This bit or strap pin should be set to ‘0’ for
the correct Duplex mode indication of LED
and register status when the link-up is AN
to force mode.
1 = advertise flow control (pause) capability
0 = suppress flow control (pause) capability from
transmission to link partner
Advertise Flow
Control Capability
4
3
2
1
0
R/W
R/W
R/W
R/W
R/W
1
1
1
1
1
Advertise 100BT
Full-Duplex
Capability
1 = advertise 100BT full-duplex capability
0 = suppress 100BT full-duplex capability from trans-
mission to link partner
Advertise 100BT
Half-Duplex
Capability
1 = advertise 100BT half-duplex capability
0 = suppress 100BT half-duplex capability from trans-
mission to link partner
1 = advertise 10BT full-duplex capability
0 = suppress 10BT full-duplex capability from trans-
mission to link partner
Advertise 10BT Full-
Duplex Capability
1 = advertise 10BT half-duplex capability
0 = suppress 10BT half-duplex capability from trans-
mission to link partner
Advertise 10BT Half-
Duplex Capability
Register 29 (0x1D): Port 1 Control 13
Register 45 (0x2D): Port 2 Control 13
Register 61 (0x3D): Reserved, Not Applicable to Port 3
1 = turn off all port’s LEDs (LEDx_1, LEDx_0, where
“x” is the port number). These pins will be driven high
if this bit is set to one.
7
LED Off
R/W
0
0 = normal operation
2017-2021 Microchip Technology Inc.
DS00002335C-page 51
KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
1 = disable the port’s transmitter
0 = normal operation
6
5
Txdis
Restart AN
R/W
0
1 = restart auto-negotiation
0 = normal operation
R/W
R/W
0
0
1 = disable far-end fault detection and pattern trans-
mission.
0 = enable far-end fault detection and pattern trans-
Disable Far-End
Fault
4
mission
1 = power down
0 = normal operation
3
2
Power Down
R/W
R/W
0
0
Disable Auto MDI/
MDI-X
1 = disable auto MDI/MDI-X function
0 = enable auto MDI/MDI-X function
If auto MDI/MDI-X is disabled,
1 = force PHY into MDI mode (transmit on RXP/RXM
1
Force MDI
R/W
pins)
0
0 = force PHY into MDI-X mode (transmit on TXP/
TXM pins)
1 = perform loopback, as indicated:
Port 1 Loopback (reg. 29, bit 0 = ‘1’)
Start: RXP2/RXM2 (port 2)
Loopback: PMD/PMA of port 1’s PHY
End: TXP2/TXM2 (port 2)
Port 2 Loopback (reg. 45, bit 0 = ‘1’)
Start: RXP1/RXM1 (port 1)
0
Loopback
R/W
0
Loopback: PMD/PMA of port 2’s PHY
End: TXP1/TXM1 (port 1)
0 = normal operation
Register 30 (0x1E): Port 1 Status 0
Register 46 (0x2E): Port 2 Status 0
Register 62 (0x3E): Reserved, Not Applicable to Port 3
1 = MDI
RO
7
6
5
4
3
2
1
0
MDI-X Status
AN Done
0
0
0
0
0
0
0
0
0 = MDI-X
1 = auto-negotiation completed
RO
0 = auto-negotiation not completed
1 = link good
RO
Link Good
0 = link not good
Partner Flow Control
Capability
1 = link partner flow control (pause) capable
0 = link partner not flow control (pause) capable
RO
RO
RO
RO
RO
Partner 100BT Full-
Duplex Capability
1 = link partner 100BT full-duplex capable
0 = link partner not 100BT full-duplex capable
Partner 100BT Half-
Duplex Capability
1 = link partner 100BT half-duplex capable
0 = link partner not 100BT half-duplex capable
Partner 10BT Full-
Duplex Capability
1 = link partner 10BT full-duplex capable
0 = link partner not 10BT full-duplex capable
Partner 10BT Half-
Duplex Capability
1 = link partner 10BT half-duplex capable
0 = link partner not 10BT half-duplex capable
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KSZ8863MLL/FLL/RLL
TABLE 4-7:
Bit
PORT REGISTERS (REGISTERS 16-95) (CONTINUED)
Name
R/W
Description
Default
Register 31 (0x1F): Port 1 Status 1
Register 47 (0x2F): Port 2 Status 1
Register 63 (0x3F): Port 3 Status 1
1
Note that only
ports 1 and 2
are PHY ports.
This bit is not
applicable to
port 3 (MII).
1 = HP Auto MDI/MDI-X mode
0 = Microchip Auto MDI/MDI-X mode
7
6
5
Hp_mdix
R/W
Reserved
Do not change the default value.
Reserved
RO
RO
0
0
Note that this bit
is not applica-
ble to port 3
(MII).
1 = polarity is reversed
0 = polarity is not reversed
Polrvs
This bit is only
valid for 10BT
Transmit Flow
Control Enable
1 = transmit flow control feature is active
0 = transmit flow control feature is inactive
4
3
2
1
RO
RO
RO
RO
0
0
0
0
Receive Flow
Control Enable
1 = receive flow control feature is active
0 = receive flow control feature is inactive
1 = link speed is 100 Mbps
0 = link speed is 10 Mbps
Operation Speed
Operation Duplex
1 = link duplex is full
0 = link duplex is half
0
1 = far-end fault status detected
0 = no far-end fault status detected
This bit is
applicable to
port 1 only.
0
Far-End Fault
RO
Register 67 (0x43): Reset
1 = Software reset
0 = Clear
4
0
Software Reset
PCS Reset
R/W
R/W
0
0
Note:
Software reset will reset all registers to the
initial values of the power-on reset or
warm reset (keep the strap values).
1 = PCS reset is used when is doing software reset
for a complete reset
0 = Clear
Note:
PCS reset will reset the state machine and
clock domain in PHY’s PCS layer.
2017-2021 Microchip Technology Inc.
DS00002335C-page 53
KSZ8863MLL/FLL/RLL
TABLE 4-8:
DATA RATE LIMIT
Data Rate Limit for
100BT
10BT
Ingress or Egress
Register Bit[6:0], Q = 0...3
Register Bit[6:0], Q = 0...3
1 to 0x63 for 1 Mbps to 99 Mbps Rate
0 or 0x64 for 100 Mbps Rate
1 to 0x09 for 1 Mbps to 9 Mbps Rate
0 or 0x0A for 10 Mbps Rate
—
64 kbps
128 kbps
192 kbps
256 kbps
320 kbps
384 kbps
448 kbps
512 kbps
576 kbps
640 kbps
704 kbps
768 kbps
832 kbps
896 kbps
960 kbps
0x65
0x66
0x67
0x68
0x69
0x6A
0x6B
0x6C
Data 0x6D
0x6E
0x6F
0x70
0x71
0x72
0x73
4.5
Advanced Control Registers (Registers 96-198)
The IPv4/IPv6 TOS Priority Control Registers implement a fully decoded, 128-bit Differentiated Services Code Point
(DSCP) register set that is used to determine the priority from the Type of Service (TOS) field in the IP header. The most
significant 6 bits of the TOS field are fully decoded into 64 possibilities, and the singular code that results is compared
against the corresponding bits in the DSCP register to determine the priority.
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198)
Name
R/W
Description
Default
Register 96 (0x60): TOS Priority Control Register 0
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[7:6]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x03.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x02.
DSCP[5:4]
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x01.
DSCP[3:2]
DSCP[1:0]
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x00.
Register 97 (0x61): TOS Priority Control Register 1
The value in this field is used as the frame’s priority
7-6
5-4
DSCP[15:14]
DSCP[13:12]
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x07.
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x06.
DS00002335C-page 54
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x05.
3-2
1-0
DSCP[11:10]
DSCP[9:8]
R/W
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x04.
R/W
00
Register 98 (0x62): TOS Priority Control Register 2
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[23:22]
DSCP[21:20]
DSCP[19:18]
DSCP[17:16]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0B.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0A.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x09.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x08.
Register 99 (0x63): TOS Priority Control Register 3
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[31:30]
DSCP[29:28]
DSCP[27:26]
DSCP[25:24]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0F.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0E.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0D.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x0C.
Register 100 (0x64): TOS Priority Control Register 4
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[39:38]
DSCP[37:36]
DSCP[35:34]
DSCP[33:32]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x13.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x12.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x11.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x10.
Register 101 (0x65): TOS Priority Control Register 5
The value in this field is used as the frame’s priority
7-6
DSCP[47:46]
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x17.
00
2017-2021 Microchip Technology Inc.
DS00002335C-page 55
KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x16.
5-4
3-2
1-0
DSCP[45:44]
DSCP[43:42]
DSCP[41:40]
R/W
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x15.
R/W
R/W
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x14.
Register 102 (0x66): TOS Priority Control Register 6
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[55:54]
DSCP[53:52]
DSCP[51:50]
DSCP[49:48]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x1B.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x1A.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x19.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x18.
Register 103 (0x67): TOS Priority Control Register 7
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[63:62]
DSCP[61:60]
DSCP[59:58]
DSCP[57:56]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x1F.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x1E.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x1D.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x1C.
Register 104 (0x68): TOS Priority Control Register 8
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[71:70]
DSCP[69:68]
DSCP[67:66]
DSCP[65:64]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x23.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x22.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x21.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x20.
DS00002335C-page 56
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Register 105 (0x69): TOS Priority Control Register 9
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[79:78]
DSCP[77:76]
DSCP[75:74]
DSCP[73:72]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x27.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x26.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x25.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x24.
Register 106 (0x6A): TOS Priority Control Register 10
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[87:86]
DSCP[85:84]
DSCP[83:82]
DSCP[81:80]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x2B.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x2A.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x29.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x28.
Register 107 (0x6B): TOS Priority Control Register 11
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[95:94]
DSCP[93:92]
DSCP[91:90]
DSCP[89:88]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x2F.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x2E.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x2D.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x2C.
Register 108 (0x6C): TOS Priority Control Register 12
The value in this field is used as the frame’s priority
7-6
5-4
3-2
DSCP[103:102]
DSCP[101:100]
DSCP[99:98]
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x33.
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x32.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x31.
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x30.
1-0
DSCP[97:96]
R/W
00
Register 109 (0x6D): TOS Priority Control Register 13
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[111:110]
DSCP[109:108]
DSCP[107:106]
DSCP[105:104]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x37.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x36.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x35.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x34.
Register 110 (0x6E): TOS Priority Control Register 14
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[119:118]
DSCP[117:116]
DSCP[115:114]
DSCP[113:112]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3B.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3A.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x39.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x38.
Register 111 (0x6F): TOS Priority Control Register 15
The value in this field is used as the frame’s priority
7-6
5-4
3-2
1-0
DSCP[127:126]
DSCP[125:124]
DSCP[123:122]
DSCP[121:120]
R/W
R/W
R/W
R/W
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3F.
00
00
00
00
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3E.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3D.
The value in this field is used as the frame’s priority
when bits [7:2] of the frame’s IP TOS/DiffServ/Traffic
Class value is 0x3C.
Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address is used as the Source Address
for the MAC’s full duplex flow control (PAUSE) frame.
Register 112 (0x70): MAC Address Register 0
7-0
7-0
MACA[47:40]
MACA[39:32]
R/W
Register 113 (0x71): MAC Address Register 1
R/W
—
0x00
0x10
—
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Register 114 (0x72): MAC Address Register 2
R/W
Register 115 (0x73): MAC Address Register 3
R/W
Register 116 (0x74): MAC Address Register 4
R/W
Register 117 (0x75): MAC Address Register 5
R/W
Description
Default
7-0
7-0
7-0
7-0
MACA[31:24]
MACA[23:16]
MACA[15:8]
MACA[7:0]
—
0xA1
0xFF
0xFF
0xFF
—
—
—
Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be
used to pass user defined control and status information between the KSZ8863 and the external processor.
Register 118 (0x76): User Defined Register 1
7-0
7-0
7-0
UDR1
UDR2
UDR3
R/W
Register 119 (0x77): User Defined Register 2
R/W
Register 120 (0x78): User Defined Register 3
R/W
—
0x00
0x00
0x00
—
—
Registers 121 to 131 provide read and write access to the static MAC address table, VLAN table, dynamic MAC
address table, and MIB counters.
Register 121 (0x79): Indirect Access Control 0
Reserved
Do not change the default values.
7-5
4
Reserved
R/W
R/W
000
0
Read High/Write
Low
1 = read cycle
0 = write cycle
00 = static MAC address table selected
01 = VLAN table selected
10 = dynamic MAC address table selected
11 = MIB counter selected
3-2
1-0
Table Select
R/W
R/W
00
00
Indirect Address
High
Bits [9:8] of indirect address
Register 122 (0x7A): Indirect Access Control 1
Bits [7:0] of indirect address.
Note:
A write to register 122 triggers the read/
write command. Read or write access is
determined by register 121 bit 4.
7-0
Indirect Address Low
R/W
0000_0000
Register 123 (0x7B): Indirect Data Register 8
This bit is applicable only for dynamic MAC address
table and MIB counter reads.
1 = read is still in progress
7
CPU Read Status
RO
0
0 = read has completed
6-3
2-0
Reserved
RO
RO
Reserved
0000
000
Indirect Data [66:64]
Bits [66:64] of indirect data
Register 124 (0x7C): Indirect Data Register 7
R/W Bits [63:56] of indirect data
7-0
Indirect Data [63:56]
0000_0000
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Register 125 (0x7D): Indirect Data Register 6
R/W Bits [55:48] of indirect data
Register 126 (0x7E): Indirect Data Register 5
R/W Bits [47:40] of indirect data
Register 127 (0x7F): Indirect Data Register 4
R/W Bits [39:32] of indirect data
Register 128 (0x80): Indirect Data Register 3
R/W Bits [31:24] of indirect data
Register 129 (0x81): Indirect Data Register 2
R/W Bits [23:16] of indirect data
Register 130 (0x82): Indirect Data Register 1
R/W Bits [15:8] of indirect data
Register 131 (0x83): Indirect Data Register 0
R/W Bits [7:0] of indirect data
Description
Default
7-0
7-0
7-0
7-0
7-0
7-0
7-0
Indirect Data [55:48]
Indirect Data [47:40]
Indirect Data [39:32]
Indirect Data [31:24]
Indirect Data [23:16]
Indirect Data [15:8]
Indirect Data [7:0]
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
0000_0000
Register 147~142 (0x93~0x8E): Station Address 1 MACA1
Register 153~148 (0x99~0x94): Station Address 2 MACA2
48’h0
Note that the
MSB bits[47-40]
of the MAC is
the register 147
and 153. The
LSB bits[7-0] of
MAC is the reg-
ister 142 and
148.
48-bit Station address MACA1 and MACA2.
Note:
The station address is used for self MAC
address filtering, see the port register con-
trol 5 bits [6,5] for detail.
47-0
Station Address
R/W
Register 154[6:0] (0x9A): Port 1 Q0 Egress Data Rate Limit
Register 158[6:0] (0x9E): Port 2 Q0 Egress Data Rate Limit
Register 162[6:0] (0xA2): Port 3 Q0 Egress Data Rate Limit
Egress Rate Limit
Flow Control Enable
1 = enable egress rate limit flow control.
0 = disable
7
R/W
R/W
0
0
Egress data rate limit for priority 0 frames
Egress traffic from this priority queue is shaped
according to the Data Rate Limit Selected Table.
Q0 Egress Data
Rate Limit
6-0
Register 155[6:0] (0x9B): Port 1 Q1 Egress Data Rate Limit
Register 159[6:0] (0x9F): Port 2 Q1 Egress Data Rate Limit
Register 163[6:0] (0xA3): Port 3 Q1 Egress Data Rate Limit
Reserved
R/W
7
Reserved
0
0
Do not change the default values.
Egress data rate limit for priority 1 frames
Q1 Egress Data
Rate Limit
6-0
R/W
Egress traffic from this priority queue is shaped
according to the Data Rate Limit Selected Table.
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Register 156[6:0] (0x9C): Port 1 Q2 Egress Data Rate Limit
Register 160[6:0] (0xA0): Port 2 Q2 Egress Data Rate Limit
Register 164[6:0] (0xA4): Port 3 Q2 Egress Data Rate Limit
Reserved
R/W
7
Reserved
0
0
Do not change the default values.
Egress data rate limit for priority 2 frames
Q2 Egress Data
Rate Limit
6-0
R/W
Egress traffic from this priority queue is shaped
according to the Data Rate Limit Selected Table.
Register 157[6:0] (0x9D): Port 1 Q3 Egress Data Rate Limit
Register 161[6:0] (0xA1): Port 2 Q3 Egress Data Rate Limit
Register 165[6:0] (0xA5): Port 3 Q3 Egress Data Rate Limit
Reserved
R/W
7
Reserved
0
0
Do not change the default values.
Egress data rate limit for priority 3 frames
Q3 Egress Data
Rate Limit
6-0
R/W
Egress traffic from this priority queue is shaped
according to the Data Rate Limit Selected Table.
Register 166 (0xA6): KSZ8863 Mode Indicator
bit7: 1 = Reserved
bit6: 1 = 48P pkg of 2 PHY mode
bit5: 1 = Reserved
bit4: 1 = Port 3 RMII
bit3: 1 = Reserved
0 = Reserved
0 = Port 3 MII
0 = Reserved
0x43 MLL
0x53 RLL
0x41 FLL
KSZ8863 Mode
Indicator
7-0
RO
bit2: 1 = Port 3 MAC MII 0 = Port 3 PHY MII
bit1: 1 = Port 1 Copper
bit0: 1 = Port 2 Copper
0 = Port 1 Fiber
0 = Reserved
Register 167 (0xA7): High Priority Packet Buffer Reserved for Q3
Reserved
Do not change the default values.
7-0
7-0
7-0
7-0
Reserved
Reserved
Reserved
Reserved
RO
0x45
0x35
0x25
0x15
Register 168 (0xA8): High Priority Packet Buffer Reserved for Q2
Reserved
Do not change the default values.
RO
Register 169 (0xA9): High Priority Packet Buffer Reserved for Q1
Reserved
Do not change the default values.
RO
Register 170 (0xAA): High Priority Packet Buffer Reserved for Q0
Reserved
Do not change the default values.
RO
Register 171 (0xAB): PM Usage Flow Control Select Mode 1
Reserved
Do not change the default values.
7
6
Reserved
Reserved
Reserved
RO
0
0
Reserved
Do not change the default values.
RO
Reserved
Do not change the default values.
5-0
RO
0x18
Register 172 (0xAC): PM Usage Flow Control Select Mode 2
Reserved
Do not change the default values.
7-6
Reserved
RO
0
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Reserved
Do not change the default values.
5-0
Reserved
RO
0x10
Register 173 (0xAD): PM Usage Flow Control Select Mode 3
Reserved
Do not change the default values.
7-6
5-0
Reserved
RO
0
Reserved
Do not change the default values.
Reserved
RO
0x08
Register 174 (0xAE): PM Usage Flow Control Select Mode 4
Reserved
Do not change the default values.
7-4
3-0
Reserved
Reserved
RO
0
Reserved
Do not change the default values.
RO
0x05
Register 175 (0xAF): TXQ Split for Q3 in Port 1
0 = enable straight priority with Reg 176/177/178
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 176/177/178 bits[7]=1.
7
Priority Select
Reserved
R/W
1
8
Reserved
Do not change the default values.
6-0
RO
Register 176 (0xB0): TXQ Split for Q2 in Port 1
0 = enable straight priority with Reg 175/177/178
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 175/177/178 bits[7]=1.
7
Priority Select
Reserved
R/W
1
4
Reserved
Do not change the default values.
6-0
RO
Register 177 (0xB1): TXQ Split for Q1 in Port 1
0 = enable straight priority with Reg 175/176/178
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 175/176/178 bits[7]=1.
7
Priority Select
Reserved
R/W
1
2
Reserved
Do not change the default values.
6-0
RO
Register 178 (0xB2): TXQ Split for Q0 in Port 1
0 = enable straight priority with Reg 175/176/177
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 175/176/177 bits[7]=1.
7
Priority Select
Reserved
R/W
1
1
Reserved
Do not change the default values.
6-0
RO
Register 179 (0xB3): TXQ Split for Q3 in Port 2
0 = enable straight priority with Reg 180/181/182
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 180/181/182 bits[7]=1.
7
Priority Select
Reserved
R/W
1
8
Reserved
Do not change the default values.
6-0
RO
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Register 180 (0xB4): TXQ Split for Q2 in Port 2
0 = enable straight priority with Reg 179/181/182
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 179/181/182 bits[7]=1.
7
Priority Select
Reserved
R/W
1
4
Reserved
Do not change the default values.
6-0
RO
Register 181 (0xB5): TXQ Split for Q1 in Port 2
0 = enable straight priority with Reg 179/180/182
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 179/180/182 bits[7]=1.
7
Priority Select
Reserved
R/W
1
2
Reserved
Do not change the default values.
6-0
RO
Register 182 (0xB6): TXQ Split for Q0 in Port 2
0 = enable straight priority with Reg 179/180/181
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 179/180/181 bits[7]=1.
7
Priority Select
Reserved
R/W
1
1
Reserved
Do not change the default values.
6-0
RO
Register 183 (0xB7): TXQ Split for Q3 Port 3
0 = enable straight priority with Reg 184/185/186
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 184/185/186 bits[7]=1.
7
Priority Select
Reserved
R/W
1
8
Reserved
Do not change the default values.
6-0
RO
Register 184 (0xB8): TXQ Split for Q2 Port 3
0 = enable straight priority with Reg 183/185/186
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 183/185/186 bits[7]=1.
7
Priority Select
Reserved
R/W
1
4
Reserved
Do not change the default values.
6-0
RO
Register 185 (0xB9): TXQ Split for Q1 in Port 3
0 = enable straight priority with Reg 183/184/186
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
queues with Reg 183/184/186 bits[7]=1.
7
Priority Select
Reserved
R/W
1
2
Reserved
Do not change the default values.
6-0
RO
Register 186 (0xBA): TXQ Split for Q0 in Port 3
0 = enable straight priority with Reg 183/184/185
bits[7]=0 and Reg 5 bit[3]=0 for higher priority first
1 = priority ratio is 8:4:2:1 for 4 queues and 2:1 for 2
7
Priority Select
R/W
1
queues with Reg 183/184/185 bits[7]=1.
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Reserved
Do not change the default values.
6-0
Reserved
RO
1
Register 187 (0xBB): Interrupt Enable Register
Interrupt enable register corresponding to bits in
Register 188
Interrupt Enable
Register
Note:
Set register 187 first and then set register
188 (W1C= Write ‘1’ Clear) to wait the
interrupt at pin 35 INTRN for the link to be
changed.
7-0
R/W
0x00
Register 188 (0xBC): Link Change Interrupt
P1 or P2 Link
Change (LC)
Interrupt
Set to 1 when P1 or P2 link changes in analog inter-
face (W1C).
7
R/W
0
Reserved
R/W
6-3
2
Reserved
0
0
0
0
Do not change the default values.
P3 Link Change (LC)
Interrupt
R/W
R/W
R/W
Set to 1 when P3 link changes in MII interface (W1C).
P2 Link Change (LC)
Interrupt
Set to 1 when P2 link changes in analog interface
(W1C).
1
P1 MII Link Change
(LC) Interrupt
Set to 1 when P1 link changes in analog interface or
MII interface (W1C).
0
Register 189 (0xBD): Force Pause Off Iteration Limit Enable
1 = Enable. It is 160 ms before requesting to
invalidate flow control.
0 = Disable
Force Pause Off
Iteration Limit Enable
7-0
R/W
0
Register 192 (0xC0): Fiber Signal Threshold
Port 2 Fiber Signal
Threshold
1 = Threshold is 2.0V
R/W
7
6
0
0
0
0 = Threshold is 1.2V
Port 1 Fiber Signal
Threshold
1 = Threshold is 2.0V
R/W
0 = Threshold is 1.2V
Reserved
Do not change the default value.
5-0
Reserved
RO
Register 193 (0xC1): Internal 1.8V LDO Control
Reserved
Do not change the default value.
7
6
Reserved
RO
0
0
0
Internal 1.8V LDO
Disable
1 = Disable internal 1.8V LDO
R/W
0 = Enable internal 1.8V LDO
Reserved
Do not change the default value.
5-0
Reserved
RO
Register 194 (0xC2): Insert SRC PVID
Reserved
Do not change the default value.
7-6
5
Reserved
RO
00
0
Insert SRC Port 1
PVID at Port 2
1= insert SRC port 1 PVID for untagged frame at
egress port 2
R/W
Insert SRC Port 1
PVID at Port 3
1= insert SRC port 1 PVID for untagged frame at
egress port 3
4
R/W
0
Insert SRC Port 2
PVID at Port 1
1= insert SRC port 2 PVID for untagged frame at
egress port 1
3
R/W
0
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Insert SRC Port 2
PVID at Port 3
1= insert SRC port 2 PVID for untagged frame at
egress port 3
2
1
0
R/W
0
Insert SRC Port 3
PVID at Port 1
1= insert SRC port 3 PVID for untagged frame at
egress port 1
R/W
R/W
0
0
Insert SRC Port 3
PVID at Port 2
1= insert SRC port 3 PVID for untagged frame at
egress port 2
Register 195 (0xC3): Power Management and LED Mode
CPU interface clock tree power down enable.
1 = Enable
0 = Disable
CPUInterfacePower
Down
7
R/W
0
Note:
Power save a little bit when MII interface is
used and the traffic is stopped in the power
management with Normal mode.
Switch clock tree power down enable.
1 = Enable
0 = Disable
6
Switch Power Down
LED Mode Selection
R/W
R/W
0
Note:
Power save a little bit when MII interface is
used and the traffic is stopped in the power
management with Normal mode
00 = LED0: Link/ACT, LED1: Speed
01 = LED0: Link, LED1: ACT
10 = LED0: Link/ACT, LED1: Duplex
11 = LED0: Link, LED1: Duplex
5-4
00
1 = the internal stretched energy signal from the ana-
log module will be negated and output to LED1 and
the internal device ready signal will be negated and
output to LED0.
0 = the LED1/LED0 pins will indicate the regular LED
outputs.
3
LED Output Mode
PLL Off Enable
R/W
0
Note:
This is for debugging purpose.
1 = PLL power down enable
0 = disable
2
R/W
R/W
0
Note:
This bit is used in Energy Detect mode
with pin 27 MII_LINK_3 pull-up in the
Bypass mode for saving power
Power management mode
00 = Normal mode
01 = Energy Detection mode
10 = Software Power Down mode
11 = Power Saving mode
Power Management
Mode
1-0
00
Register 196(0xC4): Sleep Mode
This value is used to control the minimum period the
no energy event has to be detected consecutively
before the device enters the low power state when the
ED mode is on.
7-0
Sleep Mode
R/W
0x50
The unit is 20 ms. The default go_sleep time is 1.6
seconds.
Register 198 (0xC6): Forward Invalid VID Frame and Host Mode
Reserved
Do not change the default value.
7
Reserved
RO
0
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KSZ8863MLL/FLL/RLL
TABLE 4-9:
Bit
ADVANCED CONTROL REGISTERS (REGISTERS 96-198) (CONTINUED)
Name
R/W
Description
Default
Forward Invid VID
Frame
6-4
3
R/W
Forwarding ports for frame with invalid VID
3b’0
P3 RMII Clock
Selection
1 = Internal
0 = External
R/W
R/W
0
0
P1 RMII Clock
Selection
1 = Internal
0 = External
2
00 = I2C Host mode
01 = I2C Client mode
10 = SPI Client mode
11 = SMI mode
Strapped value
of P2LED1,
P2LED0.
1-0
Host Interface Mode
R/W
4.6
Static MAC Address Table
KSZ8863 supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look-up,
KSZ8863 searches both tables to make a packet forwarding decision. In response to a Source Address (SA) look-up,
only the dynamic table is searched for aging, migration, and learning purposes.
The static DA look-up result takes precedence over the dynamic DA look-up result. If there is a DA match in both tables,
the result from the static table is used. The entries in the static table will not be aged out by KSZ8863.
The static table is accessed with an external processor via the SMI, SPI, or I2C interfaces. The external processor per-
forms all addition, modification, and deletion of static MAC table entries.
TABLE 4-10: FORMAT OF STATIC MAC TABLE (8 ENTRIES)
Bit
Name
R/W
Description
Default
57-54 FID
R/W
Filter VLAN ID – identifies one of the 16 active VLANs
0000
1 = use (FID+MAC) for static table look ups
0 = use MAC only for static table look ups
53
52
51
Use FID
R/W
R/W
R/W
0
0
0
1 = override port setting “transmit enable=0” or
“receive enable=0” setting
0 = no override
Override
1 = this entry is valid, the lookup result will be used
0 = this entry is not valid
Valid
These 3 bits control the forwarding port(s):
001, forward to port 1
010, forward to port 2
100, forward to port 3
50-48 Forwarding Ports
R/W
R/W
000
011, forward to port 1 and port 2
110, forward to port 2 and port 3
101, forward to port 1 and port 3
111, broadcasting (excluding the ingress port)
0x0000_0000
_0000
47-0
MAC Address
48-bit MAC Address
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KSZ8863MLL/FLL/RLL
Examples:
1. Static Address Table Read (Read the 2nd Entry)
Write to reg. 121 (0x79) with 0x10 // Read static table selected
Write to reg. 122 (0x7A) with 0x01 // Trigger the read operation
Then,
Read reg. 124 (0x7C), static table bits [57:56]
Read reg. 125 (0x7D), static table bits [55:48]
Read reg. 126 (0x7E), static table bits [47:40]
Read reg. 127 (0x7F), static table bits [39:32]
Read reg. 128 (0x80), static table bits [31:24]
Read reg. 129 (0x81), static table bits [23:16]
Read reg. 130 (0x82), static table bits [15:8]
Read reg. 131 (0x83), static table bits [7:0]
2. Static Address Table Write (Write the 8th Entry)
Write to reg. 124 (0x7C), static table bits [57:56]
Write to reg. 125 (0x7D), static table bits [55:48]
Write to reg. 126 (0x7E), static table bits [47:40]
Write to reg. 127 (0x7F), static table bits [39:32]
Write to reg. 128 (0x80), static table bits [31:24]
Write to reg. 129 (0x81), static table bits [23:16]
Write to reg. 130 (0x82), static table bits [15:8]
Write to reg. 131 (0x83), static table bits [7:0]
Write to reg. 121 (0x79) with 0x00 // Write static table selected
Write to reg. 122 (0x7A) with 0x07 // Trigger the write operation
4.7
VLAN Table
KSZ8863 uses the VLAN table to perform look-ups. If 802.1Q VLAN mode is enabled (register 5, bit 7 = 1), this table is
used to retrieve the VLAN information that is associated with the ingress packet. This information includes FID (filter ID),
VID (VLAN ID), and VLAN membership as described in Table 4-11.
TABLE 4-11: FORMAT OF STATIC VLAN TABLE (16 ENTRIES)
Bit
Name
R/W
Description
Default
1 = entry is valid
0 = entry is invalid
19
Valid
R/W
1
Specify which ports are members of the VLAN. If a DA
lookup fails (no match in both static and dynamic
tables), the packet associated with this VLAN will be
forwarded to ports specified in this field. For example,
101 means port 3 and 1 are in this VLAN.
18-16
Membership
R/W
111
Filter ID. KSZ8863 supports 16 active VLANs repre-
sented by these four bit fields. FID is the mapped ID.
If 802.1Q VLAN is enabled, the look up will be based
on FID+DA and FID+SA.
15-12
11-0
FID
VID
R/W
R/W
0x0
IEEE 802.1Q 12 bits VLAN ID
0x001
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If 802.1Q VLAN mode is enabled, KSZ8863 assigns a VID to every ingress packet. If the packet is untagged or tagged
with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with a non-
null VID, the VID in the tag is used. The look-up process starts from the VLAN table look-up. If the VID is not valid, the
packet are dropped and no address learning takes place. If the VID is valid, the FID is retrieved. The FID+DA and
FID+SA look-ups are performed. The FID+DA look-up determines the forwarding ports. If FID+DA fails, the packet is
broadcasted to all the members (excluding the ingress port) of the VLAN. If FID+SA fails, the FID+SA is learned.
Examples:
1. VLAN Table Read (read the 3rd entry)
Write to reg. 121 (0x79) with 0x14 // Read VLAN table selected
Write to reg. 122 (0x7A) with 0x02 // Trigger the read operation
Then,
Read reg. 129 (0x81), VLAN table bits [19:16]
Read reg. 130 (0x82), VLAN table bits [15:8]
Read reg. 131 (0x83), VLAN table bits [7:0]
2. VLAN Table Write (write the 7th entry)
Write to reg. 129 (0x81), VLAN table bits [19:16]
Write to reg. 130 (0x82), VLAN table bits [15:8]
Write to reg. 131 (0x83), VLAN table bits [7:0]
Write to reg. 121 (0x79) with 0x04 // Write VLAN table selected
Write to reg. 122 (0x7A) with 0x06 // Trigger the write operation
4.8
Dynamic MAC Address Table
KSZ8863 maintains the dynamic MAC address table. Only read access is allowed.
TABLE 4-12: FORMAT OF DYNAMIC MAC ADDRESS TABLE (1K ENTRIES)
Bit
Name
R/W
Description
Default
1 = entry is not ready, continue retrying until this bit is
71
Data Not Ready
RO
set to 0
—
0 = entry is ready
70-67
66
Reserved
RO
RO
Reserved
—
1
1 = there is no valid entry in the table
0 = there are valid entries in the table
MAC Empty
Indicates how many valid entries in the table
0x3ff means 1k entries
0x001 means 2 entries
0x000 and bit 66 = 0 means 1 entry
0x000 and bit 66 = 1 means 0 entry
Number of Valid
Entries
65-56
RO
00_0000_0000
55-54
53-52
Time Stamp
Source Port
RO
RO
2 bits counter for internal aging
—
00
The source port where FID+MAC is learned
00 = port 1
01 = port 2
10 = port 3
51-48
47-0
FID
RO
RO
Filter ID
0x0
0x0000_0000
_0000
MAC Address
48-bit MAC Address
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KSZ8863MLL/FLL/RLL
Example:
Dynamic MAC Address Table Read (read the 1st entry and retrieve the MAC table size)
Write to reg. 121 (0x79) with 0x18 // Read dynamic table selected
Write to reg. 122 (0x7A) with 0x00 // Trigger the read operation
Then,
Read reg. 123 (0x7B), bit [7]
// if bit 7 = 1, restart (reread) from this register dynamic table bits [66:64]
Read reg. 124 (0x7C), dynamic table bits [63:56]
Read reg. 125 (0x7D), dynamic table bits [55:48]
Read reg. 126 (0x7E), dynamic table bits [47:40]
Read reg. 127 (0x7F), dynamic table bits [39:32]
Read reg. 128 (0x80), dynamic table bits [31:24]
Read reg. 129 (0x81), dynamic table bits [23:16]
Read reg. 130 (0x82), dynamic table bits [15:8]
Read reg. 131 (0x83), dynamic table bits [7:0]
4.9
Management Information Base (MIB) Counters
KSZ8863 provides 34 MIB counters per port. These counters are used to monitor the port activity for network manage-
ment. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.”
TABLE 4-13: FORMAT OF “PER PORT” MIB COUNTERS
Bit
Name
R/W
Description
Default
1 = counter overflow
0 = no counter overflow
31
Overflow
RO
0
1 = counter value is valid
0 = counter value is not valid
30
Count Valid
RO
RO
0
0
29-0
Counter Values
Counter value
“Per Port” MIB counters are read using indirect memory access. The base address offsets and address ranges for all
three ports are:
• Port 1, base is 0x00 and range is (0x00-0x1f)
• Port 2, base is 0x20 and range is (0x20-0x3f)
• Port 3, base is 0x40 and range is (0x40-0x5f)
Port 1 MIB counters are read using the indirect memory offsets in Table 4-14.
TABLE 4-14: PORT 1’S “PER PORT” MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset
Counter Name
Description
0x0
0x1
0x2
0x3
0x4
RxLoPriorityByte
RxHiPriorityByte
RxUndersizePkt
RxFragments
Rx lo-priority (default) octet count including bad packets
Rx hi-priority octet count including bad packets
Rx undersize packets w/ good CRC
Rx fragment packets w/ bad CRC, symbol errors or alignment errors
Rx oversize packets w/ good CRC (max: 1536 or 1522 bytes)
RxOversize
Rx packets longer than 1522 bytes w/ either CRC errors, alignment
errors, or symbol errors (depends on max packet size setting)
0x5
0x6
0x7
RxJabbers
RxSymbolError
RxCRCError
Rx packets w/ invalid data symbol and legal packet size.
Rx packets within (64,1522) bytes w/ an integral number of bytes and a
bad CRC (upper limit depends on max packet size setting)
Rx packets within (64,1522) bytes w/ a non-integral number of bytes
and a bad CRC (upper limit depends on max packet size setting)
0x8
RxAlignmentError
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TABLE 4-14: PORT 1’S “PER PORT” MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset
Counter Name
Description
Number of MAC control frames received by a port with 88-08h in Ether-
Type field
0x9
RxControl8808Pkts
Number of PAUSE frames received by a port. PAUSE frame is qualified
with EtherType (88-08h), DA, control opcode (00-01), data length (64B
min), and a valid CRC
0xA
RxPausePkts
Rx good broadcast packets (not including error broadcast packets or
valid multicast packets)
0xB
0xC
RxBroadcast
RxMulticast
Rx good multicast packets (not including MAC control frames, error
multicast packets or valid broadcast packets)
0xD
0xE
RxUnicast
Rx good unicast packets
Rx64Octets
Total Rx packets (bad packets included) that were 64 octets in length
Total Rx packets (bad packets included) that are between 65 and 127
octets in length
0xF
0x10
0x11
0x12
0x13
Rx65to127Octets
Rx128to255Octets
Rx256to511Octets
Rx512to1023Octets
Rx1024to1522Octets
Total Rx packets (bad packets included) that are between 128 and 255
octets in length
Total Rx packets (bad packets included) that are between 256 and 511
octets in length
Total Rx packets (bad packets included) that are between 512 and
1023 octets in length
Total Rx packets (bad packets included) that are between 1024 and
1522 octets in length (upper limit depends on max packet size setting)
0x14
0x15
TxLoPriorityByte
TxHiPriorityByte
Tx lo-priority good octet count, including PAUSE packets
Tx hi-priority good octet count, including PAUSE packets
The number of times a collision is detected later than 512 bit-times into
the Tx of a packet
0x16
0x17
0x18
TxLateCollision
TxPausePkts
Number of PAUSE frames transmitted by a port
Tx good broadcast packets (not including error broadcast or valid multi-
cast packets)
TxBroadcastPkts
Tx good multicast packets (not including error multicast packets or valid
broadcast packets)
0x19
0x1A
0x1B
TxMulticastPkts
TxUnicastPkts
TxDeferred
Tx good unicast packets
Tx packets by a port for which the 1st Tx attempt is delayed due to the
busy medium
0x1C
0x1D
TxTotalCollision
Tx total collision, half duplex only
TxExcessiveCollision
A count of frames for which Tx fails due to excessive collisions
Successfully Tx frames on a port for which Tx is inhibited by exactly
one collision
0x1E
0x1F
TxSingleCollision
TxMultipleCollision
Successfully Tx frames on a port for which Tx is inhibited by more than
one collision
TABLE 4-15: FORMAT OF “ALL PORT DROPPED PACKET” MIB COUNTERS
Bit
30-16 Reserved
15-0 Counter Value
Name
R/W
Description
Default
N/A
RO
Reserved
N/A
0
Counter Value
“All Port Dropped Packet” MIB counters are read using indirect memory access. The address offsets for these counters
are shown in Table 4-16.
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KSZ8863MLL/FLL/RLL
TABLE 4-16: “ALL PORT DROPPED PACKET” MIB COUNTERS INDIRECT MEMORY OFFSETS
Offset
Counter Name
Description
0x100
0x101
0x102
0x103
0x104
0x105
Port 1 TX Drop Packets
Port 2 TX Drop Packets
Port 3 TX Drop Packets
Port 1 RX Drop Packets
Port 2 RX Drop Packets
Port 3 RX Drop Packets
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
TX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
RX packets dropped due to lack of resources
Examples:
1. MIB Counter Read (Read port 1 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c // Read MIB counters selected
Write to reg. 122 (0x7A) with 0x0e // Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow
valid bit [30]
// If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
2. MIB Counter Read (Read port 2 “Rx64Octets” Counter)
Write to reg. 121 (0x79) with 0x1c // Read MIB counter selected
Write to reg. 122 (0x7A) with 0x2e // Trigger the read operation
Then,
Read reg. 128 (0x80), overflow bit [31] // If bit 31 = 1, there was a counter overflow
valid bit [30]
// If bit 30 = 0, restart (reread) from this register
counter bits [29:24]
Read reg. 129 (0x81), counter bits [23:16]
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
3. MIB Counter Read (Read “Port1 TX Drop Packets” Counter)
Write to reg. 121 (0x79) with 0x1d // Read MIB counter selected
Write to reg. 122 (0x7A) with 0x00 // Trigger the read operation
Then,
Read reg. 130 (0x82), counter bits [15:8]
Read reg. 131 (0x83), counter bits [7:0]
4.9.1
ADDITIONAL MIB COUNTER INFORMATION
“Per Port” MIB counters are designed as “read clear.” These counters are cleared after they are read.
“All Port Dropped Packet” MIB counters are not cleared after they are accessed and do not indicate overflow or validity;
therefore, the application must keep track of overflow and valid conditions.
To read out all the counters, the best performance over the SPI bus is (160+3) x 8 x 200 = 260 ms, where there are 160
registers, 3 overheads, 8 clocks per access, at 5 MHz. In the heaviest condition, the counters overflow in 2 minutes. It
is recommended that the software reads all the counters at least every 30 seconds.
A high performance SPI Host is also recommended to prevent counters overflow.
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KSZ8863MLL/FLL/RLL
5.0
5.1
OPERATIONAL CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (VIN)
(VDDA_1.8, VDDC) ....................................................................................................................................... –0.5V to +2.4V
(VDDA_3.3, VDDIO) ...................................................................................................................................... –0.5V to +4.0V
Input Voltage .............................................................................................................................................–0.5V to +4.0V
Output Voltage ..........................................................................................................................................–0.5V to +4.0V
Lead Temperature (soldering, 10s) .......................................................................................................................+260°C
Storage Temperature (TS)......................................................................................................................–55°C to +150°C
HBM ESD Rating........................................................................................................................................................4 kV
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating
may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-
ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect
reliability.
5.2
Operating Ratings**
Supply Voltage
(VDDA_1.8, VDDC) ...................................................................................................................................+1.67V to +1.94V
(VDDA_3.3)..........................................................................................................................................+3.135V to +3.465V
(VDDIO) ................................................................................................................................................+1.71V to +3.465V
Ambient Temperature (TA)
(Commercial)................................................................................................................................................0°C to +70°C
(Industrial) ................................................................................................................................................–40°C to +85°C
Junction Temperature (TJ).....................................................................................................................................+125°C
Thermal Resistance LQFP (Note 5-1) (ΘJA) ................................................................................................. +52.83°C/W
Thermal Resistance LQFP (Note 5-1) (ΘJC)................................................................................................. +19.12°C/W
**The device is not guaranteed to function outside its operating ratings.
Note 5-1
No heat spreader (HS) in this package.
Note:
Do not drive input signals without power supplied to the device.
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KSZ8863MLL/FLL/RLL
6.0
ELECTRICAL CHARACTERISTICS
TA = 25°C. Specification is for packaged product only. Current consumption is for the single 3.3V supply device only and
includes the 1.8V supply voltages (VDDA, VDDC) that are provided via power output pin 42 (VDDCO).
Each PHY port’s transformer consumes an additional 45 mA at 3.3V for 100BASE-TX and 70 mA at 3.3V for 10BASE-
T at full traffic.
TABLE 6-1:
ELECTRICAL CHARACTERISTICS
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
100BASE-TX Operation (All Ports @ 100% Utilization)
VDDA_3.3, VDDIO = 3.3V
Core power is provided from the
internal 1.8V LDO with input voltage
VDDIO
100BASE-TX
(analog core + digital core
+ transceiver + digital I/O)
IDDXIO
—
114
—
mA
10BASE-T Operation (All Ports @ 100% Utilization)
VDDA_3.3, VDDIO = 3.3V
Core power is provided from the
internal 1.8V LDO with input voltage
VDDIO
10BASE-T
(analog core + digital core
+ transceiver + digital I/O)
IDDXIO
—
85
—
mA
Power Management Mode
Power Saving Mode
VDDA_3.3, VDDIO = 3.3V
Unplug Port 1 and Port 2
Set Register 195 bit[1,0] = [1,1]
IDD3
—
—
96
8
—
—
mA
mA
Soft Power Down Mode
VDDA_3.3, VDDIO = 3.3V
Set Register 195 bit[1,0] = [1,0]
IDD4
VDDA_3.3, VDDIO = 3.3V
Unplug Port 1 and Port 2
Set Register 195 bit[7,0] = 0x05 with
port 3 PHY mode and Bypass mode.
Energy Detect Mode
IDD5
—
16
—
—
mA
V
CMOS Inputs (VDDIO = 3.3V/2.5V/1.8V)
Input High Voltage
VIH
2.0/1.8/
1.3
—
—
Input Low Voltage
VIL
0.8/0.7/
0.5
—
—
—
V
—
Input Current
IIN
–10
10
µA
VIN = GND ~ VDDIO
CMOS Outputs (VDDIO = 3.3V/2.5V/1.8V)
2.4/2.0/
1.5
Output High Voltage
VOH
VOL
—
—
V
IOH = 8 mA
0.4/0.4/
0.3
Output Low Voltage
—
—
—
—
V
IOL = 8 mA
—
Output Tri-State Leakage
|IOZ
|
10
µA
100BASE-TX Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
Voltage
100Ω termination across differential
output
VO
0.95
—
—
—
1.05
2
V
100Ω termination across differential
output
Output Voltage Imbalance
VIMB
%
Rise/Fall Time
tr/tf
—
—
—
—
3
—
—
5
0.5
±0.5
5
ns
ns
ns
%
—
Rise/Fall Time Imbalance
Duty Cycle Distortion
Overshoot
0
—
—
—
—
—
—
—
—
Output Jitter
0.7
1.4
ns
Peak-to-peak
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TABLE 6-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Parameters
Symbol
Min.
Typ.
Max.
Units
Note
10BASE-T Receive
Squelch Threshold
VSQ
—
400
—
mV
5 MHz square wave
10BASE-T Transmit (measured differentially after 1:1 transformer)
Peak Differential Output
Voltage
100Ω termination across differential
output
VP
—
—
—
2.4
1.4
—
11
V
Output Jitter
ns
Peak-to-peak
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KSZ8863MLL/FLL/RLL
7.0
7.1
TIMING SPECIFICATIONS
EEPROM Timing
FIGURE 7-1:
EEPROM INTERFACE INPUT TIMING DIAGRAM
ts1
tcyc1
th1
Receive Timing
SCL
SDA
FIGURE 7-2:
EEPROM INTERFACE OUTPUT TIMING DIAGRAM
tcyc1
Transmit Timing
SCL
SDA
tov1
TABLE 7-1:
EEPROM TIMING PARAMETERS
Parameter
tcyc1
Description
Min.
Typ.
Max.
Units
Clock cycle
Setup time
Hold time
—
20
16384
—
—
—
ns
ns
ns
ns
ts1
th1
20
—
—
tov1
Output valid
4096
4112
4128
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KSZ8863MLL/FLL/RLL
7.2
MAC Mode MII Timing
FIGURE 7-3:
MAC MODE MII TIMING - DATA RECEIVED FROM MII
FIGURE 7-4:
MAC MODE MII TIMING - DATA TRANSMITTED TO MII
TABLE 7-2:
MAC MODE MII TIMING PARAMETERS
Parameter
tcyc3
ts3
Description
Min.
Typ.
Max.
Units
Clock cycle
Setup time
Hold time
—
4
400/40
—
—
—
—
16
ns
ns
ns
ns
th3
2
—
tov3
Output valid
7
11
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KSZ8863MLL/FLL/RLL
7.3
PHY Mode MII Timing
FIGURE 7-5:
PHY MODE MII TIMING - DATA RECEIVED FROM MII
FIGURE 7-6:
PHY MODE MII TIMING - DATA TRANSMITTED TO MII
TABLE 7-3:
PHY MODE MII TIMING PARAMETERS
Parameter
tcyc4
ts4
Description
Min.
Typ.
Max.
Units
Clock cycle
Setup time
Hold time
—
10
0
400/40
—
—
—
—
19
ns
ns
ns
ns
th4
—
tov4
Output valid
18
—
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KSZ8863MLL/FLL/RLL
7.4
RMII Timing
FIGURE 7-7:
RMII TIMING - DATA RECEIVED FROM RMII
tcyc
Transmit
Timing
REFCLK
t
1
t
2
MTXD [1:0]
MTXEN
FIGURE 7-8:
RMII TIMING - DATA TRANSMITTED TO RMII
Receive
Timing
tcyc
REFCLK
MRXD [1:0]
MRXDV
tod
TABLE 7-4:
RMII TIMING PARAMETERS
Parameter
tcyc
Description
Min.
Typ.
Max.
Units
Clock cycle
Setup time
Hold time
—
4
20
—
—
—
—
—
—
16
ns
ns
ns
ns
t1
t2
2
tod
Output delay
6
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KSZ8863MLL/FLL/RLL
7.5
I2C Client Mode Timing
FIGURE 7-9:
I2C INPUT TIMING
FIGURE 7-10:
I2C START BIT TIMING
FIGURE 7-11:
I2C STOP BIT TIMING
FIGURE 7-12:
I2C OUTPUT TIMING
TABLE 7-5:
I2C TIMING PARAMETERS
Parameter
tcyc
ts
Description
Min.
Typ.
Max.
Units
Clock cycle
Setup time
400
33
0
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
Half-Cycle
th
Hold time
—
—
—
—
—
96
ttbs
ttbh
tsbs
tsbh
tov
Start bit setup time
Start bit hold time
Stop bit setup time
Stop bit hold time
Output valid
33
33
2
33
64
Note:
Data is only allowed to change during SCL low-time, except the start and stop bits.
2017-2021 Microchip Technology Inc.
DS00002335C-page 79
KSZ8863MLL/FLL/RLL
7.6
SPI Timing
FIGURE 7-13:
SPI INPUT TIMING
FIGURE 7-14:
SPI OUTPUT TIMING
TABLE 7-6:
Parameter
SPI TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
fSCLK
t1
SPI_SCLK Clock Frequency
SPI_CSN active setup time
SDA (SPID) data input setup time
SDA (SPID) data input hold time
SPI_CSN active hold time
—
16
5
—
—
—
—
—
—
—
25
—
—
—
—
—
15
MHz
ns
t2
ns
t3
6
ns
t4
16
16
4
ns
t5
SPI_CSN disable high time
ns
t6
SPI_SCLK falling edge to SPIQ
(SDO) data output valid
ns
t7
SPI_CSN inactive to SPIQ (SDO)
data output invalid
2
—
—
ns
DS00002335C-page 80
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
7.7
Auto-Negotiation Timing
FIGURE 7-15:
AUTO-NEGOTIATION TIMING
Auto-Negotiation - Fast Link Pulse Timing
FLP
Burst
FLP
Burst
TX+/TX-
tFLPW
tBTB
Clock
Pulse
Data
Pulse
Clock
Pulse
Data
Pulse
TX+/TX-
tPW
tPW
tCTD
tCTC
TABLE 7-7:
Parameter
AUTO-NEGOTIATION TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
tBTB
tFLPW
tPW
FLP burst to FLP burst
FLP burst width
8
—
16
2
24
—
ms
ms
ns
µs
µs
—
Clock/Data pulse width
Clock pulse to data pulse
Clock pulse to clock pulse
—
100
64
128
—
—
tCTD
tCTC
—
55.5
111
17
69.5
139
33
Number of clock/data pulses per
burst
2017-2021 Microchip Technology Inc.
DS00002335C-page 81
KSZ8863MLL/FLL/RLL
7.8
MDC/MDIO Timing
FIGURE 7-16:
MDC/MDIO TIMING
TABLE 7-8:
Parameter
tP
MDC/MDIO TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
MDC period
—
400
—
ns
MDIO (PHY Input) setup to rising
edge of MDC
tMD1
tMD2
tMD3
10
4
—
—
—
—
—
ns
ns
ns
MDIO (PHY Input) hold from rising
edge of MDC
MDIO (PHY Output) delay from
rising edge of MDC
—
222
DS00002335C-page 82
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
7.9
Reset Timing
The KSZ8863MLL/FLL/RLL reset timing requirement is summarized in Figure 7-17 and Table 7-9.
FIGURE 7-17:
RESET TIMING
SUPPLY
VOLTAGES
tSR
tVR
RST#
tCS
tCH
STRAP-IN
VALUE
tRC
STRAP-IN /
OUTPUT PIN
TABLE 7-9:
Parameter
RESET TIMING PARAMETERS
Description
Min.
Typ.
Max.
Units
Stable supply voltages to reset
high
tSR
10
—
—
ms
tCS
tCH
tRC
tVR
Configuration setup time
Configuration hold time
Reset to strap-in pin output
3.3V rise time
50
50
—
—
—
—
—
—
—
—
ns
ns
ns
µs
50
100
After the deassertion of reset, wait a minimum of 100 µs before starting programming on the managed interface (I2C
Client, SPI Client, SMI, MIIM).
2017-2021 Microchip Technology Inc.
DS00002335C-page 83
KSZ8863MLL/FLL/RLL
8.0
RESET CIRCUIT
Figure 8-1 shows a reset circuit recommended for powering up the KSZ8863MLL/FLL/RLL if reset is triggered only by
the power supply.
FIGURE 8-1:
RECOMMENDED RESET CIRCUIT
VCC
D1: 1N4148
R
D1
10k
KSZ8863
RST
C
10μF
Figure 8-2 shows a reset circuit recommended for applications where reset is driven by another device (for example,
the CPU or an FPGA). At power-on-reset, R, C, and D1 provide the necessary ramp rise time to reset the KSZ8863MLL/
FLL/RLL device. The RST_OUT_N from the CPU/FPGA provides the warm reset after power-up.
FIGURE 8-2:
RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT
VCC
R
D1
10k
KSZ8863
RST
CPU/FPGA
RST_OUT_n
D2
C
10μF
D1, D2: 1N4148
DS00002335C-page 84
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
9.0
SELECTION OF ISOLATION TRANSFORMERS
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements.
Table 9-1 lists recommended transformer characteristics.
TABLE 9-1:
TRANSFORMER SELECTION CRITERIA
Parameter
Turns Ratio
Value
Test Conditions
1 CT : 1 CT
350 µH
0.4 µH
—
Open-Circuit Inductance (min.)
Leakage Inductance (max.)
Interwinding Capacitance (max.)
D.C. Resistance (max.)
Insertion Loss (max.)
100 mV, 100 kHz, 8 mA
1 MHz (min.)
12 pF
—
0.9Ω
—
0 MHz to 65 MHz
—
–1.0 dB
1500 VRMS
HIPOT (min.)
TABLE 9-2:
QUALIFIED SINGLE-PORT MAGNETICS
Manufacturer
Bel Fuse
Part Number
Auto MDI-X
S558-5999-U7
SI-46001
SI-50170
LF8505
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Bel Fuse (MagJack)
Bel Fuse (MagJack)
Delta
LanKom
LF-H41S
H1102
Pulse
Pulse (Low Cost)
Datatronic
H1260
NT79075
HB726
Transpower
YCL
LF-H41S
TLA-6T718
TDK (MagJack)
TABLE 9-3:
TYPICAL REFERENCE CRYSTAL CHARACTERISTICS
Characteristic
Value
Frequency
25.00000 MHz
Frequency Tolerance (max.)
Load Capacitance (max.)
Series Resistance
±50 ppm
20 pF
40Ω
2017-2021 Microchip Technology Inc.
DS00002335C-page 85
KSZ8863MLL/FLL/RLL
10.0 PACKAGE OUTLINE
FIGURE 10-1:
48-LEAD LQFP 7 MM X 7 MM PACKAGE
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging.
DS00002335C-page 86
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision
Section/Figure/Entry
Correction
Figure 1-1
Table 4-10
Updated the figure.
Updated the table to show corrected bit numbers (bit
57-54).
DS00002335C
(04-06-21)
Replaced mentions of “Master” and “Slave” with
“Host” and “Client”, respectively.
All
All
Minor text formatting changes throughout.
Changed PHY1 Register 29 (PHYAD = 0x1, REGAD
= 0x1D) from “Not support” to “LinkMD Control/Sta-
tus”.
Table 4-2
Changed Register 27 (0x1B) from “Not supported” to
“LinkMD Result”.
DS00002335B
(10-19-17)
Table 4-7
Figure 7-13 and Figure 7-14
Updated the SPI input and output timing illustrations.
Updated the SPI timing parameters.
Table 7-6
All
Minor text changes throughout.
Converted Micrel data sheet KSZ8863MLL/FLL/RLL
to Microchip DS00002335A. Minor text changes
throughout.
All
DS00002335A
(1-10-17)
Table 3-5
Updated with a note of RMII interface operation.
Update added VDDA_3.3 data.
Operating Ratings**
Updated junction thermal resistance.
2017-2021 Microchip Technology Inc.
DS00002335C-page 87
KSZ8863MLL/FLL/RLL
THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make
files and information easily available to customers. Accessible by using your favorite Internet browser, the web site con-
tains the following information:
• Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s
guides and hardware support documents, latest software releases and archived software
• General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion
groups, Microchip consultant program member listing
• Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive
e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or
development tool of interest.
To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notifi-
cation” and follow the registration instructions.
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this docu-
ment.
Technical support is available through the web site at: http://microchip.com/support
DS00002335C-page 88
2017-2021 Microchip Technology Inc.
KSZ8863MLL/FLL/RLL
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
XX
PART NO.
Device
X
X
X
X
a)
b)
c)
d)
e)
f)
KSZ8863MLL
MII Interface
48-lead LQFP
Single 3.3V Supply
Commercial Temperature
Tray
KSZ8863MLLI
MII Interface
Media
Type
Interface Package
Temperature
Supply
Voltage
Device:
KSZ8863
48-lead LQFP
Interface:
M = MII
R = RMII
F = Fibre
Single 3.3V Supply
Industrial Temperature
Tray
KSZ8863FLL
Fibre Interface
48-lead LQFP
Single 3.3V Supply
Commercial Temperature
Tray
KSZ8863FLLI
Fibre Interface
48-lead LQFP
Single 3.3V Supply
Industrial Temperature
Tray
KSZ8863RLL
RMII Interface
Package:
L = 48-lead LQFP
Supply Voltage:
Temperature:
L = Single 3.3V Supply
blank = 0C to +70C (Commercial)
I = –40C to +85C (Industrial)
Media Type:
blank = Tray
TR = Tape & Reel
48-lead LQFP
Single 3.3V Supply
Commercial Temperature
Tray
KSZ8863RLLI
RMII Interface
48-lead LQFP
Single 3.3V Supply
Industrial Temperature
Tray
g)
h)
i)
KSZ8863MLL-TR
MII Interface
48-lead LQFP
Single 3.3V Supply
Commercial Temperature
Tape & Reel
KSZ8863MLLI-TR
MII Interface
48-lead LQFP
Single 3.3V Supply
Industrial Temperature
Tape & Reel
KSZ8863FLL-TR
Fibre Interface
48-lead LQFP
Single 3.3V Supply
Commercial Temperature
Tape & Reel
j)
KSZ8863FLLI-TR
Fibre Interface
48-lead LQFP
Single 3.3V Supply
Industrial Temperature
Tape & Reel
k)
l)
KSZ8863RLL-TR
RMII Interface
48-lead LQFP
Single 3.3V Supply
Commercial Temperature
Tape & Reel
KSZ8863RLLI-TR
RMII Interface
48-lead LQFP
Single 3.3V Supply
Industrial Temperature
Tape & Reel
2017-2021 Microchip Technology Inc.
DS00002335C-page 89
KSZ8863MLL/FLL/RLL
NOTES:
DS00002335C-page 90
2017-2021 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
•
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is secure when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods being used in attempts to breach the code protection features of the Microchip devices. We
believe that these methods require using the Microchip products in a manner outside the operating specifications contained in Microchip's
Data Sheets. Attempts to breach these code protection features, most likely, cannot be accomplished without violating Microchip's intellectual
property rights.
•
•
Microchip is willing to work with any customer who is concerned about the integrity of its code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we
are guaranteeing the product is "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously
improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for
relief under that Act.
Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device
applications and the like isprovided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application
meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND
WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT
NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE,
COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP
HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICRO-
CHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF
FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety
applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion,
SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip
Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker,
RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II,
Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and
ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2017-2021, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-8013-6
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
2017-2021 Microchip Technology Inc.
DS00002335C-page 91
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
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Web Address:
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Tel: 678-957-9614
Fax: 678-957-1455
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Tel: 86-20-8755-8029
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Tel: 86-532-8502-7355
Tel: 63-2-634-9065
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Itasca, IL
Tel: 630-285-0071
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Detroit
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Thailand - Bangkok
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Italy - Padova
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Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
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Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS00002335C-page 92
2017-2021 Microchip Technology Inc.
02/28/20
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500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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