KSZ9131MNX [MICROCHIP]
Gigabit Ethernet Transceiver with GMII/MII Support;
| 型号： | KSZ9131MNX |
| 厂家： | 
MICROCHIP |
| 描述： | Gigabit Ethernet Transceiver with GMII/MII Support |
| 文件： | 总146页 (文件大小：2874K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
KSZ9131MNX
Gigabit Ethernet Transceiver with GMII/MII
Support
Features
Target Applications
• Single-Chip 10/100/1000 Mbps Ethernet Trans-
ceiver Suitable for IEEE 802.3 Applications
• GMII/MII Standard Interface with 3.3V/2.5V/1.8V
Tolerant I/Os
• Laser/Network Printer
• Network Attached Storage (NAS)
• Network Server
• Broadband Gateway
• Gigabit SOHO/SMB Router
• IPTV
• Auto-Negotiation to Automatically Select the
Highest Link-Up Speed (10/100/1000 Mbps) and
Duplex (Half/Full)
• IP Set-Top Box
• On-Chip Termination Resistors for the Differential
Pairs
• Game Console
• IP Camera
• On-Chip LDO Controller to Support Single 3.3V
Supply Operation
• Triple-Play (Data, Voice, Video) Media Center
• Media Converter
• Jumbo Frame Support Up to 16 KB
• 125 MHz Reference Clock Output
• Energy-Detect Power-Down Mode for Reduced
Power Consumption When Cable is Not Attached
• Energy Efficient Ethernet (EEE) Support with
Low-Power Idle (LPI) Mode and Clock Stoppable
for 100BASE-TX/1000BASE-T and Transmit
Amplitude Reduction with 10BASE-Te Option
• Wake-On-LAN (WOL) Support with Robust
Custom-Packet Detection
• Programmable LED Outputs for Link, Activity, and
Speed
• Baseline Wander Correction
• Quiet-WIRE® EMI Reduction (100BASE-TX)
• LinkMD® TDR-based Cable Diagnostic to Identify
Faulty Copper Cabling
• Signal Quality Indication
• Parametric NAND Tree Support to Detect Faults
Between Chip I/Os and Board
• Loopback Modes for Diagnostics
• Automatic MDI/MDI-X Crossover to Detect and
Correct Pair Swap at All Speeds of Operation
• Automatic Detection and Correction of Pair
Swaps, Pair Skew, and Pair Polarity
• MDC/MDIO Management Interface for PHY Reg-
ister Configuration
• Interrupt Pin Option
• Power-Down and Power-Saving Modes
• Operating Voltages
- Core (DVDDL, AVDDL, AVDDL_PLL): 1.2V
(External FET or Regulator)
- VDD I/O (DVDDH): 3.3V, 2.5V, or 1.8V
- Transceiver (AVDDH): 3.3V or 2.5V
• 64-pin QFN (8 mm × 8 mm) Package
2018-2021 Microchip Technology Inc.
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KSZ9131MNX
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00002840C-page 2
2018-2021 Microchip Technology Inc.
KSZ9131MNX
Table of Contents
1.0 Preface ............................................................................................................................................................................................ 4
2.0 Introduction ..................................................................................................................................................................................... 8
3.0 Pin Descriptions and Configuration ................................................................................................................................................. 9
4.0 Functional Description .................................................................................................................................................................. 19
5.0 Register Descriptions .................................................................................................................................................................... 47
6.0 Operational Characteristics ......................................................................................................................................................... 116
7.0 Package Outline .......................................................................................................................................................................... 140
Appendix A: Data Sheet Revision History ......................................................................................................................................... 141
The Microchip Web Site .................................................................................................................................................................... 143
Customer Change Notification Service ............................................................................................................................................. 143
Customer Support ............................................................................................................................................................................. 143
Product Identification System ........................................................................................................................................................... 144
2018-2021 Microchip Technology Inc.
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KSZ9131MNX
1.0
1.1
PREFACE
General Terms
TABLE 1-1:
GENERAL TERMS
Term
Description
1000BASE-T
100BASE-TX
10BASE-T
ADC
1 Gbps Ethernet over twisted pair, IEEE 802.3 compliant
100 Mbps Ethernet over twisted pair, IEEE 802.3 compliant
10 Mbps Ethernet over twisted pair, IEEE 802.3 compliant
Analog-to-Digital Converter
AFE
Analog Front End
AN, ANEG
AOAC
ARP
Auto-Negotiation
Always on Always Connected
Address Resolution Protocol
Best Effort Latency Tolerance
8-bits
BELT
BYTE
CSMA/CD
CSR
Carrier Sense Multiple Access/Collision Detect
Control and Status Register
Destination Address
DA
DCQ
Dynamic Channel Quality
DWORD
EC
32-bits
Embedded Controller
EEE
Energy Efficient Ethernet
FCS
Frame Check Sequence
FIFO
First In First Out buffer
FSM
Finite State Machine
FW
Firmware
GMII
Gigabit Media Independent Interface
General Purpose I/O
GPIO
HOST
HW
External system (Includes processor, application software, etc.)
Hardware. Refers to function implemented by digital logic.
Internet Group Management Protocol
Linear Drop-Out Regulator
IGMP
LDO
Level-Triggered Sticky Bit This type of status bit is set whenever the condition that it represents is asserted.
The bit remains set until the condition is no longer true, and the status bit is cleared
by writing a zero.
LFSR
LPM
lsb
Linear Feedback Shift Register
Link Power Management
Least Significant Bit
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KSZ9131MNX
TABLE 1-1:
GENERAL TERMS (CONTINUED)
Term
Description
LSB
LTM
MAC
MDI
Least Significant Byte
Latency Tolerance Messaging
Media Access Controller
Medium Dependent Interface
MDIX
MEF
MII
Media Independent Interface with Crossover
Multiple Ethernet Frames
Media Independent Interface
MLT-3
Multi-Level Transmission Encoding (3-Levels). A tri-level encoding method where a
change in the logic level represents a code bit “1” and the logic output remaining at
the same level represents a code bit “0”.
MSI / MSI-X
N/A
Message Signaled Interrupt
Not Applicable
OTP
One Time Programmable
Physical Coding Sublayer
Phase Locked Loop
Power Management IC
Power on Reset.
PCS
PLL
PMIC
POR
PTP
Precision Time Protocol
64-bits
QWORD
RESERVED
Refers to a reserved bit field or address. Unless otherwise noted, reserved bits must
always be zero for write operations. Unless otherwise noted, values are not guaran-
teed when reading reserved bits. Unless otherwise noted, do not read or write to
reserved addresses.
RMON
SA
Remote Monitoring
Source Address
SCSR
SEF
System Control and Status Registers
Single Ethernet Frame
SFD
Start of Frame Delimiter - The 8-bit value indicating the end of the preamble of an
Ethernet frame
SMNP
SQI
Simple Network Management Protocol
Signal Quality Indicator
UDP
User Datagram Protocol - A connectionless protocol run on top of IP networks
16-bits
WORD
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KSZ9131MNX
1.2
Buffer Types
TABLE 1-2:
BUFFER
BUFFER TYPE DESCRIPTIONS
DESCRIPTION
AI
AO
AI Analog input
AI Analog output
AIO
AIO Analog bidirectional
ICLK Crystal oscillator input pin
OCLK Crystal oscillator output pin
Variable voltage input
ICLK
OCLK
VI
VIS
Variable voltage Schmitt-triggered input
VO8
VOD8
VO24
PU
Variable voltage output with 8 mA sink and 8 mA source
Variable voltage open-drain output with 8 mA sink
Variable voltage output with 24 mA sink and 24 mA source
44/59/96 KΩ (typical @3.3/2.5/1.8V) internal pull-up. Unless otherwise noted in the pin
description, internal pull-ups are always enabled.
Note:
Internal pull-up resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled high, an external resistor must be added.
PD
47/58/86 KΩ (typical @3.3/2.5/1.8V) internal pull-down. Unless otherwise noted in the pin
description, internal pull-downs are always enabled.
Note:
Internal pull-down resistors prevent unconnected inputs from floating. Do not rely on
internal resistors to drive signals external to the device. When connected to a load
that must be pulled low, an external resistor must be added.
P
Power pin
Note:
Note:
Digital signals are not 5V tolerant unless specified.
Sink and source capabilities are dependent on the supplied voltage.
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KSZ9131MNX
1.3
Register Bit Types
Table 1-3 describes the register but attributes used throughout this document.
TABLE 1-3:
REGISTER BIT TYPES
Register Bit Type Notation
Register Bit Description
R
W
Read: A register or bit with this attribute can be read.
Write: A register or bit with this attribute can be written.
Read only: Read only. Writes have no effect.
RO
WO
W1S
W1C
WAC
RC
Write only: If a register or bit is write-only, reads will return unspecified data.
Write One to Set: Writing a one sets the value. Writing a zero has no effect.
Write One to Clear: Writing a one clears the value. Writing a zero has no effect.
Write Anything to Clear: Writing anything clears the value.
Read to Clear: Contents is cleared after the read. Writes have no effect.
Latch Low: Clear on read of register.
LL
LH
Latch High: Clear on read of register.
SC
Self-Clearing: Contents is self-cleared after being set. Writes of zero have no effect.
Contents can be read.
SS
Self-Setting: Contents is self-setting after being cleared. Writes of one have no effect.
Contents can be read.
RO/LH
Read Only, Latch High: This mode is used by the Ethernet PHY registers. Bits with this
attribute will stay high until the bit is read. After it a read, the bit will remain high, but will
change to low if the condition that caused the bit to go high is removed. If the bit has not
been read the bit will remain high regardless of if its cause has been removed.
NASR
STKY
Not Affected by Software Reset. The state of NASR bits does not change on asser-
tion of a software reset.
This field is “Sticky” in that it is neither initialized nor modified by hot reset or Function
Level Reset.
RESERVED
Reserved Field: Reserved fields must be written with zeros, unless otherwise indi-
cated, to ensure future compatibility. The value of reserved bits is not guaranteed on a
read.
Many of these register bit notations can be combined. Come examples of this are:
• R/W: Can be written. Will return current setting on a read.
• R/WAC: Will return current setting on a read. Writing anything clears the bit.
1.4
Reference Documents
1. IEEE 802.3TM-2015 IEEE Standard for Ethernet,
http://standards.ieee.org/about/get/802/802.3.html
2. IEEE 802.3bwTM-2015 IEEE Standard for Ethernet Amendment 1,
https://standards.ieee.org/findstds/standard/802.3bw-2015.html
3. OPEN Alliance TC1 - Advanced diagnostics features for 100BASE-T1 automotive Ethernet PHYs Version 1.0
http://www.opensig.org/download/document/218/Advanced_PHY_features_for_automotive_Ethernet_V1.0.pdf
2018-2021 Microchip Technology Inc.
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KSZ9131MNX
2.0
2.1
INTRODUCTION
General Description
The KSZ9131MNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical-
layer transceiver for transmission and reception of data on standard CAT-5 as well as CAT-5e and CAT-6 unshielded
twisted pair (UTP) cables.
The KSZ9131MNX offers the industry-standard GMII/MII (Gigabit Media Independent Interface/Media Independent
Interface) for connection to GMII/MII MACs in Gigabit Ethernet processors and switches for data transfer at 1000 Mbps
or 10/100 Mbps.
The KSZ9131MNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four
differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.
The KSZ9131MNX offers diagnostic features to facilitate system bring-up and debugging in production testing and in
product deployment. Parametric NAND tree support enables fault detection between KSZ9131MNX I/Os and the board.
The LinkMD® TDR-based cable diagnostic identifies faulty copper cabling. Remote, external, and local loopback func-
tions verify analog and digital data paths.
The KSZ9131MNX is available in a 64-pin, RoHS Compliant QFN package.
FIGURE 2-1:
SYSTEM BLOCK DIAGRAM
CRYSTAL
GMII/MII
MEDIA TYPES
10BASE-T
100BASE-TX
1000BASE-T
10/100/1000Mbps
GMII/MII
Ethernet MAC
RJ-45
CONNECTOR
KSZ9131MNX
MDC/MDIO
MANAGEMENT
INT_N /
PME_N
LDO
/ LEDs
CONTROLLER
SYSTEM POWER CIRCUIT /
INTERUPT CONTROLLER /
LEDs
VIN 3.3V,
2.5V
VOUT 1.2V
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KSZ9131MNX
3.0
3.1
PIN DESCRIPTIONS AND CONFIGURATION
Pin Assignments
FIGURE 3-1:
PIN ASSIGNMENTS (TOP VIEW)
1
48
AVDDH
TXRXP_A
TXRXM_A
AVDDL
RX_CLK/PHYAD2
2
3
47
RX_ER
46
DVDDH
4
45
RX_DV/CLK125_EN
5
44
AVDDL
RXD0/MODE0
6
43
NC
RXD1/MODE1
7
42
TXRXP_B
TXRXM_B
AGNDH
TXRXP_C
TXRXM_C
AVDDL
DVDDL
KSZ9131MNX
8
41
RXD2/MODE2
64-QFN
9
40
DVDDH
(Top View)
10
11
12
13
14
15
16
39
RXD3/MODE3
38
RXD4
37
RXD5
36
AVDDL
DVDDL
35
TXRXP_D
TXRXM_D
AVDDH
RXD6
P_VSS
34
RXD7
(Connect exposed pad to ground with a via field)
33
TX_EN
Note: Exposed pad (P_VSS) on bottom of package must be connected to ground with a via field.
Note: Configuration strap inputs are indicated with an underline.
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KSZ9131MNX
TABLE 3-1:
KSZ9131MNX PIN ASSIGNMENTS
Pin
Num
Pin
Num
Pin Name
Pin Name
1
AVDDH
TXRXP_A
TXRXM_A
AVDDL
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
TX_EN
RXD7
2
3
RXD6
4
DVDDL
5
AVDDL
RXD5
6
NC
RXD4
7
TXRXP_B
TXRXM_B
AGNDH
TXRXP_C
TXRXM_C
AVDDL
RXD3/MODE3
DVDDH
8
9
RXD2/MODE2
DVDDL
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
RXD1/MODE1
RXD0/MODE0
RX_DV/CLK125_EN
DVDDH
AVDDL
TXRXP_D
TXRXM_D
AVDDH
RX_ER
RX_CLK/PHYAD2
CRS
LED2/PHYAD1
DVDDH
LED1/PME_N1/PHYAD0
DVDDL
MDC
MDIO
COL
INT_N/PME_N2/ALLPHYAD
DVDDL
TXD0
TXD1
TXD2
CLK125_NDO/LED_MODE
RESET_N
TX_CLK
TXD3
DVDDL
TXD4
LDO_O
TXD5
AVDDL_PLL
XO
TXD6
TXD7
XI
DVDDH
TX_ER
NC
ISET
GTX_CLK
AGNDH
Exposed Pad (P_VSS) must be connected to ground.
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KSZ9131MNX
3.2
Pin Descriptions
This section contains descriptions of the various KSZ9131MNX pins. The “_N” symbol in the signal name indicates that
the active, or asserted, state occurs when the signal is at a low voltage level. For example, RESET_N indicates that the
reset signal is active low. When “_N” is not present after the signal name, the signal is asserted when at the high voltage
level.
The pin function descriptions have been broken into functional groups as follows:
• Analog Front End
• GMII Interface
• Crystal
• Miscellaneous
• Strap Inputs
• I/O Power, Core Power and Ground
TABLE 3-2:
Name
ANALOG FRONT END
BUFFER
Symbol
DESCRIPTION
TYPE
Ethernet TX/RX
Positive Channel
A
TXRXP_A
AIO
Media Dependent Interface[0], positive signal of differential
pair
1000BT mode: TXRXP_A corresponds to BI_DA+.
10BT/100BT mode: TXRXP_A is the positive transmit signal
(TX+) for MDI configuration and the positive receive signal
(RX+) for MDI-X configuration, respectively.
Ethernet TX/RX
Negative Channel
A
TXRXM_A
TXRXP_B
TXRXM_B
TXRXP_C
AIO
AIO
AIO
AIO
Media Dependent Interface[0], negative signal of differential
pair
1000BT mode: TXRXM_A corresponds to BI_DA-.
10BT/100BT-TX mode: TXRXM_A is the negative transmit sig-
nal (TX-) for MDI configuration and the negative receive signal
(RX-) for MDI-X configuration, respectively.
Ethernet TX/RX
Positive Channel
B
Media Dependent Interface[1], positive signal of differential
pair
1000BT mode: TXRXP_B corresponds to BI_DB+.
10BT/100BT mode: TXRXP_B is the positive receive signal
(RX+) for MDI configuration and the positive transmit signal
(TX+) for MDI-X configuration, respectively.
Ethernet TX/RX
Negative Channel
B
Media Dependent Interface[1], negative signal of differential
pair
1000BT mode: TXRXM_B corresponds to BI_DB-.
10BT/100BT mode: TXRXP_B is the negative receive signal
(RX-) for MDI configuration and the negative transmit signal
(TX-) for MDI-X configuration, respectively.
Ethernet TX/RX
Positive Channel
C
Media Dependent Interface[2], positive signal of differential
pair
1000BT mode: TXRXP_C corresponds to BI_DC+.
10BT/100BT mode: TXRXP_C is not used.
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KSZ9131MNX
TABLE 3-2:
Name
ANALOG FRONT END (CONTINUED)
BUFFER
TYPE
Symbol
DESCRIPTION
Ethernet TX/RX
Negative Channel
C
TXRXM_C
AIO
AIO
AIO
Media Dependent Interface[2], negative signal of differential
pair
1000BT mode: TXRXM_C corresponds to BI_DC-.
10BT/100BT mode: TXRXM_C is not used.
Ethernet TX/RX
Positive Channel
D
TXRXP_D
TXRXM_D
Media Dependent Interface[3], positive signal of differential
pair
1000BT mode: TXRXP_D corresponds to BI_DD+.
10BT/100BT mode: TXRXP_D is not used.
Ethernet TX/RX
Negative Channel
D
Media Dependent Interface[3], negative signal of differential
pair
1000BT mode: TXRXM_D corresponds to BI_DD-.
10BT/100BT mode: TXRXM_D is not used.
TABLE 3-3:
GMII INTERFACE
Symbol
BUFFER
TYPE
Name
DESCRIPTION
Transmit Data
TXD7
TXD6
TXD5
TXD4
TXD3
TXD2
TXD1
TXD0
VI
(PD)
The MAC transmits data to the PHY using these signals.
Note:
Bits 7-4 are not used in MII mode and if not driven,
require external pull-down resistors.
Transmit Enable
Transmit Error
TX_EN
TX_ER
VI
Indicates the presence of valid data on TXD[7:0].
VI
Indicates a transmit error condition during frame transmission.
(PD)
Also used to request Low Power Idle for Energy Efficient
Ethernet operation.
Note:
If the GMII/MII MAC does not provide the TX_ER
output signal, this pin should be tied low.
GMII Transmit
Clock
GTX_CLK
VI
GMII transmit reference clock.
Note: This signal is not used in MII mode and if not driven,
requires an external pull-down resistor.
MII transmit reference clock.
MII Transmit Clock
Collision Detect
Carrier Sense
TX_CLK
COL
VO24
VO24
VO24
Note:
This signal is not used in GMII mode.
Asserted to indicate detection of a collision condition.
Note:
Indicates detection of carrier.
Note: Used in half-duplex mode only.
Used in half-duplex mode only.
CRS
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KSZ9131MNX
TABLE 3-3:
GMII INTERFACE (CONTINUED)
BUFFER
Name
Symbol
TYPE
DESCRIPTION
Receive Data
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
VO24
The PHY transfers data to the MAC using these signals.
Note:
Bits 7-4 are not used in MII mode and are driven low.
Receive Data Valid
Receive Error
RX_DV
VO24
VO24
Indicates that recovered and decoded data is being presented
on the receive data pins.
RX_ER
Asserted to indicate an error has been detected in the frame
presently being transferred from the PHY.
Also used to indicate Low Power Idle for Energy Efficient
Ethernet operation.
Receive Clock
RX_CLK
VO24
Receive reference clock.
TABLE 3-4:
CRYSTAL
BUFFER
TYPE
Name
Symbol
DESCRIPTION
Crystal Input
XI
ICLK
When using a 25MHz crystal, this input is connected to one
lead of the crystal.
When using an clock source, this is the input from the oscilla-
tor.
Note:
The crystal or oscillator should have a tolerance of
±50ppm.
Crystal Output
XO
OCLK
When using a 25MHz crystal, this output is connected to one
lead of the crystal.
When using an external oscillator, this pin is not connected.
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KSZ9131MNX
TABLE 3-5:
MISCELLANEOUS
Symbol
BUFFER
TYPE
Name
DESCRIPTION
Programmable LED outputs.
This is the management data from/to the MAC.
Indicator LEDs
LED2
LED1
VO8
Management
Interface Data
MDIO
VIS/
VO8
VOD8
(PU)
Note:
An external pull-up resistor to DVDDH in the range
of 1.0 kΩ to 4.7 kΩ is required.
Management
Interface Clock
MDC
VIS
(PU)
This is the management clock input from the MAC.
Programmable PME_N output.
Power Manage-
ment Event
PME_N2
PME_N1
VO8
When asserted low, this pin signals that a WOL event has
occurred.
PME_N can be mapped to either (or both) pins.
Programmable interrupt output.
PHY Interrupt
CLK125 MHz
INT_N
VO8
CLK125_NDO
VO24
125 MHz clock output.
This pin provides a 125 MHz reference clock output option for
use by the MAC.
This pin may also provide a 125 MHz clock output synchro-
nous to the receive data for use in Synchronous Ethernet
(SyncE) applications.
System Reset
RESET_N
LDO_O
VIS
(PU)
Chip reset (active low).
Hardware pin configurations are strapped-in at the de-asser-
tion (rising edge) of RESET_N. See the Strap Inputs section
for details.
LDO Controller
Output
AO
On-chip 1.2V LDO controller output.
This pin drives the input gate of a P-channel MOSFET to gen-
erate 1.2V for the chip’s core voltages.
Note:
If the system provides 1.2V, this pin is not used and
can be left unconnected.
PHY Bias Resistor
No Connect
ISET
NC
AI
-
This pin should be connect to ground through a 6.04KΩ 1%
resistor.
APPLICATION NOTE: The resistor value is different from
the 12.1KΩ used on the KSZ9031.
For normal operation, these pins should be left unconnected.
Note:
Pin 62 is not bonded and can be connected to
AVDDH power for footprint compatibility with older
generation devices.
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KSZ9131MNX
TABLE 3-6:
STRAP INPUTS
Symbol
BUFFER
TYPE
Name
DESCRIPTION
PHY Address
PHYAD2
PHYAD1
PHYAD0
VI
The PHY address, PHYAD[2:0], is sampled and latched at
power-up/reset and is configurable to any value from 0 to 7.
Each PHY address bit is configured as follows:
Pulled-up = 1
Pulled-down = 0
PHY Address Bits [4:3] are always set to ‘00’.
All PHY Address
Enable
ALLPHYAD
VI
The ALLPHYAD strap-in pin is sampled and latched at power-
up/reset and are defined as follows:
0 = PHY will respond to PHY address 0 as well as it’s assigned
PHY address
1= PHY will respond to only it’s assigned PHY address
Note:
This strap input is inverted compared to the All-
PHYAD Enable register bit.
Device Mode
MODE3
MODE2
MODE1
MODE0
VI
VI
Note:
The MODE[3:0] strap-in pins are sampled and
latched at power-up/reset and are defined in Section
3.3.1, "Device Mode Select"
125MHz Output
Clock Enable
CLK125_EN
CLK125_EN is sampled and latched at power-up/reset and is
defined as follows:
Pulled-up (1) = Enable 125 MHz clock output
Pulled-down (0) = Disable 125 MHz clock output
CLK125_NDO provides the 125 MHz reference clock output
option for use by the MAC.
LED Mode
LED_MODE
VI
LED_MODE is sampled and latched at power-up/reset and is
defined as follows:
Pulled-up (1) = Individual-LED mode
Pulled-down (0) = Tri-color-LED mode
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DS00002840C-page 15
KSZ9131MNX
TABLE 3-7:
Name
I/O POWER, CORE POWER AND GROUND
BUFFER
TYPE
Symbol
DESCRIPTION
+2.5/3.3V
Analog Power
Supply
AVDDH
P
+2.5/3.3V analog power supply VDD
+1.2V Analog
Power Supply
AVDDL
P
P
+1.2V analog power supply VDD
+1.2V Analog
PLL Power
Supply
AVDDL_PLL
+1.2V analog PLL power supply VDD
+3.3/2.5/1.8V
Variable I/O
Power Supply
Input
DVDDH
DVDDL
P
P
+3.3/2.5/1.8V variable I/O digital power supply VDD_IO
+1.2V digital core power supply input
+1.2V Digital
Core Power
Supply Input
Paddle Ground
P_VSS
GND
GND
Common ground. This exposed paddle must be connected to
the ground plane with a via array.
Analog Ground
High
AGNDH
Analog ground high
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KSZ9131MNX
3.3
Configuration Straps
Configuration straps allow various features of the device to be automatically configured to user defined values. Config-
uration straps are latched upon the release of pin reset (RESET_N). Configuration straps do not include internal resis-
tors and require the use of external resistors.
Note:
• The system designer must ensure that configuration strap pins meet the timing requirements specified in Section
6.6.3, "Reset Pin Configuration Strap Timing". If configuration strap pins are not at the correct voltage level prior
to being latched, the device may capture incorrect strap values.
• When externally pulling configuration straps high, the strap should be tied to DVDDH.
APPLICATION NOTE: All straps should be pulled-up or pulled-down externally on the PCB to enable the desired
operational state.
3.3.1
DEVICE MODE SELECT
The MODE[3:0] configuration straps selects the device mode as follows:
TABLE 3-8:
DEVICE MODE SELECTIONS
Functional Modes
Auto-negotiation Advertisement
Pin 19
Function Function
Pin 53
MODE[3:0]
Mode
1000BT Full 1000BT Half 10/100BT Full 10/100BT Half
Duplex
Duplex
Duplex
Duplex
0000
0001
1000
RESERVED
GMII/MII
-
-
-
-
yes
-
no
-
yes
-
yes
-
RESERVED
1001
1010
1011
GMII/MII
LED1
(PME_N1)
no
-
no
-
yes
-
yes
-
RESERVED
GMII/MII
INT_N
no
no
yes
yes
(PME_N2)
1100
1101
1110
1111
RESERVED
RESERVED
RESERVED
RESERVED
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Test Modes
Mode
MODE[3:0]
0010
0011
0100
0101
0110
0111
RESERVED
RESERVED
NAND tree mode
RESERVED
RESERVED
Device power down mode
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DS00002840C-page 17
KSZ9131MNX
3.3.2
PHY ADDRESS
The PHYAD2:0 configuration straps set the value of the PHY’s management address. PHYAddress Bits [4:3] are always
set to ‘00’.
3.3.3
ALL PHYs ADDRESS
The ALLPHYAD configuration strap sets the default of the All-PHYAD Enable bit in the Common Control Register which
enables or disables the PHY’s ability to respond to PHY address 0 as well as it’s assigned PHY address.
Note:
This strap input is inverted compared to the register bit.
3.3.4
125MHZ OUTPUT CLOCK ENABLE
The CLK125_EN configuration strap enables the 125 MHz clock output onto the CLK125_NDO pin.
The output clock defaults to a locally generated 125MHz clock. The recovered 125MHz RX clock can be selected for
use in Synchronous Ethernet (SyncE) applications.
3.3.5
LED MODE SELECT
The LED_MODE configuration strap selects between Individual-LED (1) or Tri-color-LED (0) modes. LED operation is
described in Section 4.13, "LED Support".
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KSZ9131MNX
4.0
FUNCTIONAL DESCRIPTION
The KSZ9131MNX is a completely integrated triple-speed (10BASE-T/100BASE-TX/1000BASE-T) Ethernet physical
layer transceiver solution for transmission and reception of data over a standard CAT-5 unshielded twisted pair (UTP)
cable.
The KSZ9131MNX reduces board cost and simplifies board layout by using on-chip termination resistors for the four
differential pairs and by integrating an LDO controller to drive a low-cost MOSFET to supply the 1.2V core.
On the copper media interface, the KSZ9131MNX can automatically detect and correct for differential pair misplace-
ments and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as
specified in the IEEE 802.3 standard for 1000BASE-T operation.
The KSZ9131MNX provides the GMII/MII interface for connection to GMACs in Gigabit Ethernet processors and
switches for data transfer at 10/100/1000Mbps.
Figure 4-1 shows a high-level block diagram of the KSZ9131MNX.
FIGURE 4-1:
KSZ9131MNX BLOCK DIAGRAM
PMA
TX10/100/1000
CLOCK
RESET
CONFIGURATIONS
PMA
RX1000
PCS1000
MEDIA
INTERFACE
PMA
RX100
GMII/MII
INTERFACE
PCS100
PCS10
PMA
RX10
LED
DRIVERS
AUTO-
NEGOTIATION
4.1
10BASE-T/100BASE-TX Transceiver
4.1.1
100BASE-TX TRANSMIT
The 100BASE-TX transmit function performs parallel-to-serial conversion, 4B/5B coding, scrambling, NRZ-to-NRZI con-
version, and MLT-3 encoding and transmission.
The circuitry starts with a parallel-to-serial conversion, which converts the MII data from the MAC into a 125 MHz serial
bit stream. The data and control stream is then converted into 4B/5B coding, followed by a scrambler. The serialized
data is further converted from NRZ-to-NRZI format, and then transmitted in MLT-3 current output. The output current is
set by an external 6.04 kΩ 1% resistor for the 1:1 transformer ratio.
The output signal has a typical rise/fall time of 4 ns and complies with the ANSI TP-PMD standard regarding amplitude
balance, and overshoot. The wave-shaped 10BASE-T output is also incorporated into the 100BASE-TX transmitter.
4.1.2
100BASE-TX RECEIVE
The 100BASE-TX receiver function performs adaptive equalization, DC restoration, MLT-3-to-NRZI conversion, data
and clock recovery, NRZI-to-NRZ conversion, de-scrambling, 4B/5B decoding, and serial-to-parallel conversion.
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DS00002840C-page 19
KSZ9131MNX
The receiving side starts with the equalization filter to compensate for inter-symbol interference (ISI) over the twisted
pair cable. Because the amplitude loss and phase distortion are a function of the cable length, the equalizer must adjust
its characteristics to optimize performance. In this design, the variable equalizer makes an initial estimation based on
comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization.
This is an ongoing process and self-adjusts against environmental changes such as temperature variations.
Next, the equalized signal goes through a DC-restoration and data-conversion block. The DC-restoration circuit com-
pensates for the effect of baseline wander and improves the dynamic range. The differential data conversion circuit con-
verts the MLT-3 format back to NRZI. The slicing threshold is also adaptive.
The clock-recovery circuit extracts the 125 MHz clock from the edges of the NRZI signal. This recovered clock is then
used to convert the NRZI signal into the NRZ format. This signal is sent through the de-scrambler followed by the 4B/
5B decoder. Finally, the NRZ serial data is converted to the GMII/MII format and provided as the input data to the MAC.
4.1.3
SCRAMBLER/DE-SCRAMBLER (100BASE-TX ONLY)
The purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (EMI)
and baseline wander. Transmitted data is scrambled using an 11-bit wide linear feedback shift register (LFSR). The
scrambler generates a 2047-bit non-repetitive sequence, then the receiver de-scrambles the incoming data stream
using the same sequence as at the transmitter.
4.1.4
10BASE-T TRANSMIT
The 10BASE-T output drivers are incorporated into the 100BASE-TX drivers to allow for transmission with the same
magnetic. The drivers perform internal wave-shaping and pre-emphasis, and output signals with typical amplitude of
2.5V peak for standard 10BASE-T mode and 1.75V peak for energy-efficient 10BASE-Te mode. The 10BASE-T/
10BASE-Te signals have harmonic contents that are at least 31 dB below the fundamental frequency when driven by
an all-ones Manchester-encoded signal.
4.1.5
10BASE-T RECEIVE
On the receive side, input buffer and level-detecting squelch circuits are used. A differential input receiver circuit and a
phase-locked loop (PLL) perform the decoding function. The Manchester-encoded data stream is separated into clock
signal and NRZ data. A squelch circuit rejects signals with levels less than 300 mV or with short pulse widths to prevent
noises at the receive inputs from falsely triggering the decoder. When the input exceeds the squelch limit, the PLL locks
onto the incoming signal and the KSZ9131MNX decodes a data frame. The receiver clock is maintained active during
idle periods between receiving data frames.
The KSZ9131MNX removes all 7 bytes of the preamble and presents the received frame starting with the SFD (start of
frame delimiter) to the MAC.
Auto-polarity correction is provided for the receiving differential pair to automatically swap and fix the incorrect +/– polar-
ity wiring in the cabling.
4.2
1000BASE-T Transceiver
The 1000BASE-T transceiver is based-on a mixed-signal/digital-signal processing (DSP) architecture, which includes
the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, preci-
sion clock recovery scheme, and power-efficient line drivers.
Figure 4-2 shows a high-level block diagram of a single channel of the 1000BASE-T transceiver for one of the four dif-
ferential pairs.
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KSZ9131MNX
FIGURE 4-2:
KSZ9131 1000BASE-T BLOCK DIAGRAM - SINGLE CHANNEL
OTHER
CHANNELS
XTAL
CLOCK
GENERATION
SIDE-STREAM
SCRAMBLER
&
TX
SYMBOL ENCODER
SIGNAL
TRANSMIT
BLOCK
PCS STATE
MACHINES
LED DRIVER
PAIR SWAP
&
NEXT
ECHO
CANCELLER
ANALOG
HYBRID
DESCRAMBLER
ALIGN UNIT
CANCELLER
+
DECODER
BASELINE
WANDER
COMPENSATION
RX-
ADC
FFE
SLICER
+
RX
SIGNAL
CLOCK
& PHASE
DFE
RECOVERY
MII
AUTO -
NEGOTIATION
MII
MANAGEMENT
CONTROL
REGISTERS
PMA STATE
MACHINES
4.2.1
ANALOG ECHO-CANCELLATION CIRCUIT
In 1000BASE-T mode, the analog echo-cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit
relieves the burden of the ADC and the adaptive equalizer.
This circuit is disabled in 10BASE-T/100BASE-TX mode.
4.2.2
AUTOMATIC GAIN CONTROL (AGC)
In 1000BASE-T mode, the automatic gain control (AGC) circuit provides initial gain adjustment to boost up the signal
level. This pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.
4.2.3
ANALOG-TO-DIGITAL CONVERTER (ADC)
In 1000BASE-T mode, the analog-to-digital converter (ADC) digitizes the incoming signal. ADC performance is essen-
tial to the overall performance of the transceiver.
This circuit is disabled in 10BASE-T/100BASE-TX mode.
4.2.4
TIMING RECOVERY CIRCUIT
In 1000BASE-T mode, the mixed-signal clock recovery circuit together with the digital phase-locked loop is used to
recover and track the incoming timing information from the received data. The digital phase-locked loop has very low
long-term jitter to maximize the signal-to-noise ratio of the receive signal.
The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to
the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This
also helps to facilitate echo cancellation and NEXT removal.
4.2.5
ADAPTIVE EQUALIZER
In 1000BASE-T mode, the adaptive equalizer provides the following functions:
• Detection for partial response signaling
• Removal of NEXT and ECHO noise
• Channel equalization
Signal quality is degraded by residual echo that is not removed by the analog hybrid because of impedance mismatch.
The KSZ9131MNX uses a digital echo canceler to further reduce echo components on the receive signal.
In 1000BASE-T mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels).
This results in high-frequency cross-talk coming from adjacent wires. The KSZ9131MNX uses three NEXT cancelers
on each receive channel to minimize the cross-talk induced by the other three channels.
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DS00002840C-page 21
KSZ9131MNX
In 10BASE-T/100BASE-TX mode, the adaptive equalizer needs only to remove the inter-symbol interference and
recover the channel loss from the incoming data.
4.2.6
TRELLIS ENCODER AND DECODER
In 1000BASE-T mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4D-PAM5
symbols. The initial scrambler seed is determined by the specific PHY address to reduce EMI when more than one
KSZ9131 is used on the same board. On the receiving side, the idle stream is examined first. The scrambler seed, pair
skew, pair order, and polarity must be resolved through the logic. The incoming 4D-PAM5 data is then converted into 9-
bit symbols and de-scrambled into 8-bit data.
4.3
Auto MDI/MDI-X
The Automatic MDI/MDI-X feature eliminates the need to determine whether to use a straight cable or a crossover cable
between the KSZ9131MNX and its link partner. This auto-sense function detects the MDI/MDI-X pair mapping from the
link partner, and assigns the MDI/MDI-X pair mapping of the KSZ9131MNX accordingly.
Table 4-1 shows the KSZ9131MNX 10/100/1000 pin configuration assignments for MDI/MDI-X pin mapping.
TABLE 4-1:
MDI/MDI-X PIN MAPPING
MDI
MDI-X
Pin
(RJ-45 Pair)
1000BASE-T
100BASE-T
10BASE-T
1000BASE-T
100BASE-T
10BASE-T
TXRXP/M_A
(1, 2)
A+/–
TX+/–
TX+/–
A+/–
RX+/–
TX+/–
RX+/–
TXRXP/M_B
(3, 6)
B+/–
C+/–
D+/–
RX+/–
RX+/–
B+/–
C+/–
D+/–
TX+/–
TXRXP/M_C
(4, 5)
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
Not Used
TXRXP/M_D
(7, 8)
Auto MDI/MDI-X is enabled by default. It is disabled by writing a one to the Swap-Off bit in the Auto-MDI/MDI-X Register.
MDI and MDI-X mode is set by the MDI Set bit in the Auto-MDI/MDI-X Register if Auto MDI/MDI-X is disabled.
An isolation transformer with symmetrical transmit and receive data paths is recommended to support Auto MDI/MDI-X.
4.4
Pair-Swap, Alignment, and Polarity Check
In 1000BASE-T mode, the KSZ9131MNX
• Detects incorrect channel order and automatically restores the pair order for the A, B, C, D pairs (four channels).
• Supports 50 ns ±10 ns difference in propagation delay between pairs of channels in accordance with the IEEE
802.3 standard, and automatically corrects the data skew so the corrected four pairs of data symbols are synchro-
nized.
Incorrect pair polarities of the differential signals are automatically corrected for all speeds.
4.5
Wave Shaping, Slew-Rate Control, and Partial Response
In communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and
to minimize distortion and error in the transmission channel.
• For 1000BASE-T, a special partial-response signaling method is used to provide the band-limiting feature for the
transmission path.
• For 100BASE-TX, a simple slew-rate control method is used to minimize EMI.
• For 10BASE-T, pre-emphasis is used to extend the signal quality through the cable.
4.6
PLL Clock Synthesizer
The KSZ9131MNX generates 125 MHz, 25 MHz, and 10 MHz clocks for system timing. Internal clocks are generated
from the external 25 MHz crystal or reference clock.
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KSZ9131MNX
4.7
Auto-Negotiation
The KSZ9131MNX conforms to the auto-negotiation protocol, defined in Clause 28 of the IEEE 802.3 Specification.
Auto-negotiation allows UTP (unshielded twisted pair) link partners to select the highest common mode of operation.
During auto-negotiation, link partners advertise capabilities across the UTP link to each other, and then compare their
own capabilities with those they received from their link partners. The highest speed and duplex setting that is common
to the two link partners is selected as the operating mode.
The following list shows the speed and duplex operation mode from highest-to-lowest:
• Priority 1: 1000BASE-T, full-duplex
• Priority 2: 1000BASE-T, half-duplex
Note:
The device does not support 1000BASE-T, half-duplex and should not be enabled to advertise such.
• Priority 3: 100BASE-TX, full-duplex
• Priority 4: 100BASE-TX, half-duplex
• Priority 5: 10BASE-T, full-duplex
• Priority 6: 10BASE-T, half-duplex
If auto-negotiation is not supported or the KSZ9131MNX link partner is forced to bypass auto-negotiation for 10BASE-
T and 100BASE-TX modes, the KSZ9131MNX sets its operating mode by observing the input signal at its receiver. This
is known as parallel detection, and allows the KSZ9131MNX to establish a link by listening for a fixed signal protocol in
the absence of the auto-negotiation advertisement protocol.
The auto-negotiation link-up process is shown in Figure 4-3.
FIGURE 4-3:
AUTO-NEGOTIATION FLOW CHART
START AUTO-NEGOTIATION
PARALLEL
OPERATION
FORCE LINK SETTING
YES
NO
ATTEMPT AUTO-
NEGOTIATION
LISTEN FOR 100BASE-TX
IDLES
LISTEN FOR 10BASE-T
LINK PULSES
BYPASS AUTO-NEGOTIATION
AND SET LINK MODE
NO
JOIN FLOW
LINK MODE SET?
YES
LINK MODE SET
For 1000BASE-T mode, auto-negotiation is required and always used to establish a link. During 1000BASE-T auto-
negotiation, the master and slave configuration is first resolved between link partners. Then the link is established with
the highest common capabilities between link partners.
Auto-negotiation is enabled by default after power-up or hardware reset. After that, auto-negotiation can be enabled or
disabled through the Auto-Negotiation Enable bit in the Basic Control Register. If auto-negotiation is disabled, the speed
is set by the Speed Select[0] and Speed Select[1] bits and the duplex is set by the Duplex Mode, all in the Basic Control
Register.
If the speed is changed on the fly, the link goes down and either auto-negotiation or parallel detection initiates until a
common speed between KSZ9131MNX and its link partner is re-established for a link.
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DS00002840C-page 23
KSZ9131MNX
If the link is already established and there is no change of speed on the fly, the changes (for example, duplex and pause
capabilities) will not take effect unless either auto-negotiation is restarted through the Restart Auto-Negotiation
(PHY_RST_AN) bit in the Basic Control Register, or a link-down to link-up transition occurs (that is, disconnecting and
reconnecting the cable).
After auto-negotiation is completed, the link status is updated in the Link Status bit of the Basic Status Register and the
link partner capabilities are updated in the Auto-Negotiation Link Partner Base Page Ability Register, Auto-Negotiation
Expansion Register, and Auto-Negotiation Master Slave Status Register.
The auto-negotiation finite state machines use interval timers to manage the auto-negotiation process. The duration of
these timers under normal operating conditions is summarized in Table 4-2.
TABLE 4-2:
AUTO-NEGOTIATION TIMERS
Auto-Negotiation Interval Timers
Time Duration
Transmit Burst Interval
16 ms
68 µs
Transmit Pulse Interval
FLP Detect Minimum Time
FLP Detect Maximum Time
Receive Minimum Burst Interval
Receive Maximum Burst Interval
Data Detect Minimum Interval
Data Detect Maximum Interval
NLP Test Minimum Interval
NLP Test Maximum Interval
Link Loss Time
17.2 µs
185 µs
6.8 ms
112 ms
35.4 µs
95 µs
4.5 ms
30 ms
52 ms
Break Link Time
1480 ms
830 ms
1000 ms
Parallel Detection Wait Time
Link Enable Wait Time
4.7.1
AUTO-NEGOTIATION NEXT PAGE USAGE
The device supports “Next Page” capability which is used to negotiate Gigabit Ethernet and Energy Efficient Ethernet
functionality as well as to support software controlled pages.
As described in IEEE 802.3 Annex 40C “Add-on interface for additional Next Pages”, the device will autonomously send
and receive the Gigabit Ethernet and Energy Efficient Ethernet next pages and then optionally send and receive soft-
ware controlled next pages.
Gigabit Ethernet next pages consist of one message and two unformatted pages. The message page contains an 8 as
the message code. The first unformatted page contains the information from the Auto-Negotiation Master Slave Control
Register. The second unformatted page contains the Master-Slave Seed value used to resolve the Master-Slave selec-
tion. The result of the Gigabit Ethernet next pages exchange is stored in Auto-Negotiation Master Slave Status Register.
Gigabit Ethernet next pages are always transmitted, regardless of the advertised settings in the Auto-Negotiation Master
Slave Control Register.
Energy Efficient Ethernet (EEE) next pages consist of one message and one unformatted page. The message page
contains a 10 as the message code (this value can be overridden in the EEE Message Code Register). The unformatted
page contains the information from the EEE Advertisement Register. The result of the Gigabit Ethernet next pages
exchange is stored in EEE Link Partner Ability Register.
EEE next pages are transmitted only if the advertised setting in the EEE Advertisement Register is not zero.
APPLICATION NOTE: The Gigabit Ethernet and EEE next pages may be viewed in Auto-Negotiation Next Page
RX Register as they are exchanged.
Following the EEE next page exchange, software controlled next pages are exchanged when the Next Page bit in the
Auto-Negotiation Advertisement Register is set. Software controlled next page status is monitored via the Auto-Negoti-
ation Expansion Register and Auto-Negotiation Next Page RX Register.
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KSZ9131MNX
4.8
10/100 Mbps Speeds Only
Some applications require link-up to be limited to 10/100 Mbps speeds only.
After power-up/reset, the KSZ9131MNX can be restricted to auto-negotiate and link-up to 10/100 Mbps speeds only by
programming the following register settings:
1. Configure the Speed Select[1] bit in the Basic Control Register to ‘0’ to disable the 1000 Mbps speed.
2. Configure the 1000BASE-T Full Duplex and 1000BASE-T Half Duplex bits in the Auto-Negotiation Master Slave
Control Register to ‘00’ to remove Auto-Negotiation advertisements for 1000 Mbps full/half duplex.
3. Write a ‘1’ to the Restart Auto-Negotiation (PHY_RST_AN) bit in the Basic Control Register, a self-clearing bit,
to force a restart of Auto-Negotiation.
Auto-Negotiation and 10BASE-T/100BASE-TX speeds use only differential pairs A and B. Differential pairs C and D can
be left as no connects.
4.9
GMII Interface
The Gigabit Media Independent Interface (GMII) is compliant to the IEEE 802.3 Specification. It provides a common
interface between GMII PHYs and MACs, and has the following key characteristics:
• Pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision
indication).
• 1000 Mbps is supported at both half- and full-duplex.
Note:
The device does not support 1000BASE-T, half-duplex and should not be enabled to advertise such.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 8 bits wide, a byte.
In GMII operation, the GMII pins function as follows:
• The MAC sources the transmit reference clock, GTX_CLK, at 125 MHz for 1000 Mbps.
• The PHY recovers and sources the receive reference clock, RX_CLK, at 125 MHz for 1000 Mbps.
• TX_EN, TXD[7:0], and TX_ER are sampled by the KSZ9131 on the rising edge of GTX_CLK.
• RX_DV, RXD[7:0], and RX_ER are sampled by the MAC on the rising edge of RX_CLK.
• CRS and COL are driven by the KSZ9131MNX and do not have to transition synchronously with respect to either
GTX_CLK or RX_CLK.
The KSZ9131MNX combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/
1000 Mbps. After power-up or reset, the KSZ9131MNX is configured to GMII/MII mode if the MODE[3:0] strap-in pins
are set to ‘0001’, ‘1001’, or ‘1011’. See Section 3.3, "Configuration Straps" for additional information.
The KSZ9131MNX has the option to output a 125 MHz reference clock on CLK125_NDO (Pin 55). This clock provides
a lower-cost reference clock alternative for GMII/MII MACs that require a 125 MHz crystal or oscillator. The 125 MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high or the clk125 Enable bit is
set in the Common Control Register.
The KSZ9131MNX provides a dedicated transmit clock input pin (GTX_CLK, Pin 32) for GMII mode, which is sourced
by the MAC for 1000 Mbps speed.
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DS00002840C-page 25
KSZ9131MNX
4.9.1
GMII SIGNAL DEFINITION
Table 4-3 describes the GMII signals. Refer to Clause 35 of the IEEE 802.3 Specification for more detailed information.
TABLE 4-3:
GMII SIGNAL DEFINITION
GMII Signal Name GMII Signal Name Pin Type (with
Pin Type (with
Description
(per spec)
(per KSZ9131)
respect to PHY) respect to MAC)
Transmit Reference Clock
(125 MHz for 1000 Mbps)
GTX_CLK
GTX_CLK
Input
Output
TX_EN
TXD[7:0]
TX_ER
TX_EN
TXD[7:0]
TX_ER
Input
Input
Input
Output
Output
Output
Transmit Enable
Transmit Data[7:0]
Transmit Error
Receive Reference Clock
(125 MHz for 1000 Mbps)
RX_CLK
RX_CLK
Output
Input
RX_DV
RXD[7:0]
RX_ER
CRS
RX_DV
RXD[7:0]
RX_ER
CRS
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Receive Data Valid
Receive Data[7:0]
Receive Error
Carrier Sense
COL
COL
Collision Detected
4.9.2
GMII SIGNAL DIAGRAM
The KSZ9131MNX GMII pin connections to the MAC are shown in Figure 4-4.
FIGURE 4-4:
KSZ9131MNX GMII INTERFACE
GMII
ETHERNET MAC
KSZ9131MNX
GTX_CLK
TX_EN
GTX_CLK
TX_EN
TXD[7:0]
TX_ER
TXD[7:0]
TX_ER
RX_CLK
RX_DV
RX_CLK
RX_DV
[7:0]
[7:0]
RXD
RXD
RX_ER
RX_ER
CRS
COL
CRS
COL
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KSZ9131MNX
4.10 MII Interface
The Media Independent Interface (MII) is compliant with the IEEE 802.3 Specification. It provides a common interface
between MII PHYs and MACs, and has the following key characteristics:
• Pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indi-
cation).
• 10 Mbps and 100 Mbps are supported at both half- and full-duplex.
• Data transmission and reception are independent and belong to separate signal groups.
• Transmit data and receive data are each 4 bits wide, a nibble.
In MII operation, the MII pins function as follows:
• The PHY sources the transmit reference clock, TX_CLK, at 25 MHz for 100 Mbps and 2.5 MHz for 10 Mbps.
• The PHY recovers and sources the receive reference clock, RX_CLK, at 25 MHz for 100 Mbps and 2.5 MHz for
10 Mbps.
• TX_EN, TXD[3:0], and TX_ER are driven by the MAC and transition synchronously with respect to TX_CLK.
• RX_DV, RXD[3:0], and RX_ER are driven by the KSZ9131MNX and transition synchronously with respect to
RX_CLK.
• CRS and COL are driven by the KSZ9131MNX and do not have to transition synchronously with respect to either
TX_CLK or RX_CLK.
The KSZ9131MNX combines GMII mode with MII mode to form GMII/MII mode to support data transfer at 10/100/
1000 Mbps. After power-up or reset, the KSZ9131 is configured to GMII/MII mode if the MODE[3:0] strap-in pins are set
to ‘0001’, ‘1001’, or ‘1011’. See Section 3.3, "Configuration Straps" for additional information.
The KSZ9131MNX has the option to output a 125 MHz reference clock on CLK125_NDO (Pin 55). This clock provides
a lower-cost reference clock alternative for GMII/MII MACs that require a 125 MHz crystal or oscillator. The 125 MHz
clock output is enabled after power-up or reset if the CLK125_EN strap-in pin is pulled high or the clk125 Enable bit is
set in the Common Control Register.
The KSZ9131MNX provides a dedicated transmit clock output pin (TX_CLK, Pin 57) for MII mode, which is sourced by
the KSZ9131MNX for 10/100 Mbps speed.
4.10.1
MII SIGNAL DEFINITION
Table 4-4 describes the MII signals. Refer to Clause 22 of the IEEE 802.3 Specification for detailed information.
TABLE 4-4:
MII SIGNAL DEFINITION
MII Signal Name
(per spec)
MII Signal Name
(per KSZ9131)
Pin Type (with
respect to PHY) respect to MAC)
Pin Type (with
Description
Transmit Reference Clock
(25 MHz for 100 Mbps, 2.5 MHz for
10 Mbps)
TX_CLK
TX_CLK
Output
Input
TX_EN
TXD[3:0]
TX_ER
TX_EN
TXD[3:0]
TX_ER
Input
Input
Input
Output
Output
Output
Transmit Enable
Transmit Data[3:0]
Transmit Error
Receive Reference Clock
(25 MHz for 100 Mbps, 2.5 MHz for
10 Mbps)
RX_CLK
RX_CLK
Output
Input
RX_DV
RXD[3:0]
RX_ER
CRS
RX_DV
RXD[3:0]
RX_ER
CRS
Output
Output
Output
Output
Output
Input
Input
Input
Input
Input
Receive Data Valid
Receive Data[3:0]
Receive Error
Carrier Sense
COL
COL
Collision Detection
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4.10.2
MII SIGNAL DIAGRAM
The KSZ9131MNX MII pin connections to the MAC are shown in Figure 4-5.
FIGURE 4-5:
KSZ9131MNX MII INTERFACE
MII
KSZ9131MNX
ETHERNET MAC
TX _CLK
TX_EN
TXD[3:0]
TX_ER
TX _CLK
TX_EN
TXD[3:0]
TX_ER
RX_CLK
RX_DV
RX_CLK
RX_DV
[3:0]
[3:0]
RXD
RXD
RX_ER
RX_ER
CRS
COL
CRS
COL
4.11 MII Management (MIIM) Interface
The KSZ9131MNX supports the IEEE 802.3 MII management interface, also known as the Management Data Input/
Output (MDIO) interface. This interface allows upper-layer devices to monitor and control the state of the KSZ9131MNX.
An external device with MIIM capability is used to read the PHY status and/or configure the PHY settings. More details
about the MIIM interface can be found in Clause 22.2.4 of the IEEE 802.3 Specification.
The MIIM interface consists of the following:
• A physical connection that incorporates the clock line (MDC) and the data line (MDIO).
• A specific protocol that operates across the physical connection mentioned earlier, which allows an external con-
troller to communicate with one or more KSZ9131MNX devices. Each KSZ9131MNX device is assigned a unique
PHY address between 0h and 7h by the PHYAD[2:0] strapping pins.
• A 32-register address space for direct access to IEEE-defined registers and vendor-specific registers, and for indi-
rect access to MMD addresses and registers. See the Register Map section.
Table 4-5 shows the MII management frame format for the KSZ9131MNX.
TABLE 4-5:
MII MANAGEMENT FRAME FORMAT FOR THE KSZ9131MNX
PHY
Address
Bits [4:0] Bits [4:0]
REG
Address
Start of Read/Write
Preamble
TA
Data Bits [15:0]
Idle
Frame
OP Code
Read
Write
32 1’s
32 1’s
01
01
10
01
00AAA
00AAA
RRRRR
RRRRR
Z0 DDDDDDDD_DDDDDDDD
10 DDDDDDDD_DDDDDDDD
Z
Z
4.11.1
ALL PHYS ADDRESS
Normally, the Ethernet PHY is accessed at the PHY address set by the PHYAD[2:0] strapping pins.
PHY Address 0h is optionally supported as the broadcast PHY address, which allows for a single write command to
simultaneously program an identical PHY register for two or more PHY devices (for example, using PHY Address 0h to
set the Basic Control Register to a value of 0x1940 to set Bit [11] to a value of one to enable software power-down).
PHY address 0 is enabled (in addition to the PHY address set by the PHYAD[2:0] strapping pins) when the All-PHYAD
Enable bit in the Common Control Register is a 1.
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4.11.2
MDIO OUTPUT DRIVE MODE
The MDIO output pin drive mode is controlled by the MDIO Drive bit in MDIO Drive Register. When set to a 0, the MDIO
output is open-drain. When set to a 1, the MDIO output is push-pull.
4.12 Interrupt (INT_N)
The INT_N pin is an optional interrupt signal that is used to inform the external controller that there has been a status
update in the KSZ9131MNX PHY register. Bits [15:8] of the Interrupt Control/Status Register are the interrupt control
bits that enable and disable the conditions for asserting the INT_N signal. Bits [7:0] of the Interrupt Control/Status Reg-
ister are the interrupt status bits that indicate which interrupt conditions have occurred. The interrupt status bits are
cleared after reading the Interrupt Control/Status Register.
The Interrupt Polarity Invert bit of the Control Register sets the interrupt level to active high or active low. The default is
active low.
The MII management bus option gives the MAC processor complete access to the KSZ9131MNX control and status
registers. Additionally, an interrupt pin eliminates the need for the processor to poll the PHY for status change.
4.13 LED Support
The KSZ9131MNX provides two programmable LED output pins, LED2 and LED1, which are configurable to support
three LED modes. The LED mode is configured by the LED_MODE strap-in as well as the KSZ9031 LED Mode bit in
the KSZ9031 LED Mode Register. It is latched at power-up/reset and is defined as follows:
• KSZ9031 LED Mode = 1, LED_MODE strap input high (pulled up): Individual-LED Mode
• KSZ9031 LED Mode = 1, LED_MODE strap input low (pulled down): Tri-Color-LED Mode
• KSZ9031 LED Mode = 0, LED_MODE strap is unused: Enhanced LED Mode
Each LED output pin can directly drive an LED with a series resistor (typically 220Ω to 470Ω).
4.13.1
INDIVIDUAL-LED MODE
In individual-LED mode, the LED2 pin indicates the link status while the LED1 pin indicates the activity status, as shown
in Table 4-6.
Note:
• The LEDs are forced OFF when the Isolate (PHY_ISO) bit in the Basic Control Register is set.
• The LEDs are forced OFF when the Power Down bit in the Basic Control Register is set.
TABLE 4-6:
INDIVIDUAL-LED MODE - PIN DEFINITION
LED Pin
LED2
Pin State
LED Definition
Link/Activity
H
L
OFF
ON
Link Off
Link On (any speed)
No Activity
LED1
H
OFF
Toggle
Blinking
Activity (RX, TX)
4.13.2
TRI-COLOR-LED MODE
In tri-color-LED mode, the link and activity status are indicated by the LED2 pin for 1000BASE-T; by the LED1 pin for
100BASE-TX; and by both LED2 and LED1 pins, working in conjunction, for 10BASE-T. This is summarized in Table 4-7.
Note:
• The LEDs are forced OFF when the Isolate (PHY_ISO) bit in the Basic Control Register is set.
• The LEDs are forced OFF when the Power Down bit in the Basic Control Register is set.
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TABLE 4-7:
TRI-COLOR-LED MODE - PIN DEFINITION
LED Pin (State)
LED Pin (Definition)
Link/Activity
LED2
LED1
LED2
LED1
H
H
OFF
ON
OFF
OFF
Link Off
L
Toggle
H
H
1000 Link/No Activity
1000 Link/Activity (RX, TX)
100 Link/No Activity
100 Link/Activity (RX, TX)
10 Link/No Activity
H
L
Blinking
OFF
OFF
ON
H
Toggle
L
OFF
Blinking
ON
L
ON
Toggle
Toggle
Blinking
Blinking
10 Link/Activity (RX, TX)
4.13.3
ENHANCED LED MODE
Enhanced LED mode is enabled when the KSZ9031 LED Mode bit in the KSZ9031 LED Mode Register is cleared. In
Enhanced LED mode, each LED can be configured to display different status information that can be selected by setting
the corresponding LED Configuration field of the LED Mode Select Register. The modes are shown in Table 4-8. The
blink/pulse-stretch and other LED settings can be configured via the LED Behavior Register.
Note:
The LEDs are forced OFF when the Power Down bit in the Basic Control Register is set.
TABLE 4-8:
LED MODE AND FUNCTION SUMMARY
Name
Mode
Description
0
Link/Activity
1 (led off) = No link in any speed on any media interface.
0 (led on) = Valid link at any speed on any media interface.
Blink or pulse stretch (led turns off) = Valid link at any speed on any
media interface with activity present.
1
2
3
4
5
Link1000/Activity
1 (led off) = No link at 1000BASE-T.
0 (led on) = Valid link at 1000BASE-T.
Blink or pulse stretch (led turns off) = Valid link at 1000BASE-T with activ-
ity present.
Link100/Activity
1 (led off) = No link at 100BASE-TX.
0 (led on) = Valid link at 100BASE-TX.
Blink or pulse stretch (led turns off) = Valid link at 100BASE-TX with
activity present.
Link10/Activity
1 (led off) = No link at 10BASE-T.
0 (led on) = Valid link at 10BASE-T.
Blink or pulse stretch (led turns off) = Valid link at 10BASE-T with activity
present.
Link100/1000/Activity
Link10/1000/Activity
1 (led off) = No link at 100BASE-TX or 1000BASE-T.
0 (led on) = Valid link at 100BASE-TX or 1000BASE-T.
Blink or pulse stretch (led turns off) = Valid link at 100BASE-TX or
1000BASE-T, with activity present.
1 (led off) = No link at 10BASE-T or 1000BASE-T.
0 (led on) = Valid link at 10BASE-T or 1000BASE-T.
Blink or pulse stretch (led turns off) = Valid link at 10BASE-T or
1000BASE-T, with activity present.
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TABLE 4-8:
LED MODE AND FUNCTION SUMMARY (CONTINUED)
Mode
Name
Description
1 (led off) = No link at 10BASE-T or 100BASE-TX.
6
Link10/100/Activity
0 (led on) = Valid link at 10BASE-T or 100BASE-TX.
Blink or pulse stretch (led turns off) = Valid link at 10BASE-T or
100BASE-TX, with activity present.
7
8
RESERVED
RESERVED
Duplex/Collision
1 (led off) = Link established in half-duplex mode, or no link established.
0 (led on) = Link established in full-duplex mode.
Blink or pulse stretch (led turns on) = Link established in half-duplex
mode but collisions are present.
9
Collision
Activity
1 (led off) = No collisions detected.
Blink or pulse stretch (led turns on) = Collision detected.
1 (led off) = No activity present.
10
Blink or pulse stretch (led turns on) = Activity present. (becomes TX
activity present if the LED Activity Output Select bit in the LED Behavior
Register is set to 1.)
11
12
RESERVED
RESERVED
Auto-Negotiation Fault
1 (led off) = No Auto-Negotiation fault present.
0 (led on) = Auto-Negotiation fault occurred.
13
14
15
RESERVED
RESERVED
Force LED Off
Force LED On
1 (led off) = De-asserts the LED.
0 (led on) = Asserts the LED.
4.13.3.1
LED Behavior
Using the LED Behavior Register, the following LED behaviors can be configured.:
• LED Combine
• LED Blink or Pulse-Stretch
• Rate of LED Blink or Pulse-Stretch
• LED Pulsing Enable
4.13.3.1.1
LED Combine
Enables an LED to display the status for a combination of primary and secondary modes. This can be enabled or dis-
abled for each LED pin via the LED Combination Disables field of the LED Behavior Register. For example, a copper
link running in 1000BASE-T mode with activity present can be displayed with one LED by configuring an LED pin to
Link1000/Activity mode. The LED asserts when linked to a 1000BASE-T partner and also blinks or performs pulse-
stretch when activity is either transmitted by the PHY or received by the Link Partner. When disabled, the combine fea-
ture only provides status of the selected primary function. In this example, only Link1000 asserts the LED, and the sec-
ondary mode, activity, does not display if the combine feature is disabled.
Note:
LED Behavior Register, Bit 15 = 1 (Default is 0) to set the LED Link/Activity to the desired value. This can
be done in the same LED Behavior Register write to set the LED Combine Disables field.
4.13.3.1.2
LED Blink or Pulse-Stretch
This behavior is used for activity and collision indication. This can be uniquely configured for each LED pin via the LED
Pulse Stretch Enables field of the LED Behavior Register. Activity and collision events can occur randomly and intermit-
tently throughout the link-up period.
Blink is a 50% duty cycle oscillation of asserting and de-asserting an LED pin.
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As shown in Figure 4-6, for a single event, the LED will blink (either on or off depending on the LED function) for half of
the blink period. For continual events, the LED will oscillate at the blink rate.
FIGURE 4-6:
LED BLINK PATTERN
event
LED (blink on)
LED (blink off)
active low LED shown
(up to ½ blink LED blinks
LED
oscillates at
blink rate
period delay)
for ½ blink
period
Not to any scale
Pulse-stretch ensures that an LED is asserted and de-asserted for a specific period of time when activity is either pres-
ent or not present.
As shown in Figure 4-7, for a single event, the LED will pulse (either on or off depending on the LED function) for the
full pulse period. For continual events, the LED will remain on (or off) and will extend from a half to one and a half pulse
periods once the events terminate. Once off (or on), the LED will remain in that state for at least a half pulse period.
FIGURE 4-7:
LED PULSE PATTERN
event
LED (pulse on)
LED (pulse off)
active low LED shown
(up to ½ pulse
period delay)
(½ to 1-½ pulse period
stretch)
LED pulses for
pulse period
LED remains on (or off)
LED remains
off (or on) for ½
pulse period
Not to any scale
The blink / pulse stretch rate can be configured, as detailed in Section 4.13.3.1.3, "Rate of LED Blink or Pulse-Stretch".
4.13.3.1.3 Rate of LED Blink or Pulse-Stretch
This behavior controls the LED blink rate or pulse-stretch length when the blink/pulse-stretch is enabled (LED Pulse
Stretch Enables) on an LED pin. This can be uniquely configured for each LED pin via the LED Blink / Pulse-Stretch
Rate field of the LED Behavior Register. The blink rate, which alternates between a high and low voltage level at a 50%
duty cycle, can be set to 2.5 Hz, 5 Hz, 10 Hz, or 20 Hz. For pulse-stretch, the rate can be set to 50 ms, 100 ms, 200 ms,
or 400 ms.
4.13.3.1.4
LED Pulsing Enable
To provide additional power savings, the LEDs (when asserted) can be modulated at 5 kHz, 20% duty cycle, by setting
the LED Pulsing Enable bit of the LED Behavior Register.
4.14 Loopback Modes
The KSZ9131MNX supports the following loopback operations to verify analog and/or digital data paths.
• Digital (near-end) loopback
• Remote (far-end) loopback
• External connector loopback
4.14.1
DIGITAL (NEAR-END) LOOPBACK
This loopback mode checks the GMII/MII transmit and receive data paths between the KSZ9131MNX and the external
MAC, and is supported for all three speeds (10/100/1000 Mbps) at full-duplex.
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The loopback data path is shown in Figure 4-8.
1. GMII/MII MAC transmits frames to KSZ9131MNX.
2. Frames are wrapped around inside KSZ9131MNX.
3. KSZ9131MNX transmits frames back to GMII/MII MAC.
FIGURE 4-8:
DIGITAL (NEAR-END) LOOPBACK
KSZ9131MNX
AFE
PCS
GMII/
MII
GMII/MII
MAC
(ANALOG)
(DIGITAL)
The following programming steps and register settings are used for local loopback mode.
For 1000 Mbps loopback,
1. Configure the following registers:
- MMD 1C, Register 15 = EEEE
- MMD 1C, Register 16 = EEEE
- MMD 1C, Register 18 = EEEE
- MMD 1C, Register 1B = EEEE
2. Configure the Basic Control Register:
- Bit [14] = 1
- Bits [6, 13] = 10
- Bit [12] = 0
- Bit [8] = 1
// Enable local loopback mode
// Select 1000 Mbps speed
// Disable auto-negotiation
// Select full-duplex mode
3. Configure the Auto-Negotiation Master Slave Control Register:
- Bit [12] = 1
- Bit [11] = 0
// Enable master-slave manual configuration
// Select slave configuration (required for loopback mode)
For 10/100 Mbps loopback,
1. Configure the following registers:
- MMD 1C, Register 15 = EEEE
- MMD 1C, Register 16 = EEEE
- MMD 1C, Register 18 = EEEE
- MMD 1C, Register 1B = EEEE
2. Configure the Basic Control Register:
- Bit [14] = 1
// Enable local loopback mode
- Bits [6, 13] = 00 / 01
- Bit [12] = 0
// Select 10 Mbps/100 Mbps speed
// Disable auto-negotiation
// Select full-duplex mode
- Bit [8] = 1
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4.14.2
REMOTE (FAR-END) LOOPBACK
This loopback mode checks the line (differential pairs, transformer, RJ-45 connector, Ethernet cable) transmit and
receive data paths between the KSZ9131MNX and its link partner, and is supported for 1000BASE-T full-duplex mode
only.
The loopback data path is shown in Figure 4-9.
1. The Gigabit PHY link partner transmits frames to KSZ9131MNX.
2. Frames are wrapped around inside KSZ9131MNX.
3. KSZ9131MNX transmits frames back to the Gigabit PHY link partner.
FIGURE 4-9:
REMOTE (FAR-END) LOOPBACK
KSZ9131MNX
AFE
(ANALOG)
PCS
(DIGITAL)
GMII /
MII
RJ-45
CAT-5
(UTP)
1000BASE-T
LINK PARTNER
RJ-45
The following programming steps and register settings are used for remote loopback mode.
1. Configure the Basic Control Register:
- Bits [6, 13] = 10 // Select 1000 Mbps speed
- Bit [12] = 0
- Bit [8] = 1
// Disable auto-negotiation
// Select full-duplex mode
Or just auto-negotiate and link up at 1000BASE-T full-duplex mode with the link partner.
2. Configure the Remote Loopback Register:
- Bit [8] = 1
// Enable remote loopback mode
3. Connect RX_CLK to TX_CLK
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4.14.3
EXTERNAL CONNECTOR LOOPBACK
The connector loopback testing feature allows the twisted pair interface to be looped back externally. When using this
feature, the PHY must be connected to a loopback connector or a loopback cable. Pair A should be connected to pair
B, and pair C to pair D, as shown in Figure 4-10. The connector loopback feature functions at all available interface
speeds.
This loopback tests the PHY digital and MAC connectivity.
When using the connector loopback testing feature, the device Auto-Negotiation, speed, and duplex configuration is set
using the Basic Control Register, Auto-Negotiation Advertisement Register, and Auto-Negotiation Master Slave Control
Register.
For 1000BASE-T connector loopback, the following additional writes are required to be executed in the following order:
• Disable Auto-Negotiation and set the speed to 1000Mbps and the duplex to full by setting the Basic Control Reg-
ister to a value of 0140h.
• Set the Master-Slave configuration to master by setting the Master/Slave Manual Configuration Enable and Mas-
ter/Slave Manual Configuration Value bits in the Auto-Negotiation Master Slave Control Register.
• Enable the 1000BASE-T connector loopback by setting the Ext_lpbk bit in the External Loopback Register.
FIGURE 4-10:
EXTERNAL CONNECTOR LOOPBACK
A
B
RXD
TXD
Cat‐5
PHY
MAC
C
D
4.15 LinkMD® Cable Diagnostic
The LinkMD function uses time domain reflectometry (TDR) to analyze the cabling plant for common cabling problems,
such as open circuits, short circuits, and impedance mismatches as well as the distance to the fault. Each of the four
twisted pairs is tested separately.
LinkMD operates by sending a pulse of known amplitude and duration down the selected differential pair, then analyzing
the polarity and shape of the reflected signal to determine the type of fault: open circuit for a positive/non-inverted ampli-
tude reflection and short circuit for a negative/inverted amplitude reflection. The time duration for the reflected signal to
return provides the approximate distance to the cabling fault. The LinkMD function processes this TDR information and
presents it as a numerical value that can be translated to a cable distance.
LinkMD is initiated by accessing the LinkMD Cable Diagnostic Register in conjunction with the Auto-MDI/MDI-X Regis-
ter. The latter register is needed to disable the Auto MDI/MDI-X function before running the LinkMD test. Additionally, a
software reset (PHY Soft Reset (RESET) bit in the Basic Control Register = 1) should be performed before and after
running the LinkMD test. The reset helps to ensure the KSZ9131MNX is in the normal operating state before and after
the test.
Prior to running the cable diagnostics, Auto-negotiation should be disabled, full duplex set and the link speed set to
1000Mbps via the Basic Control Register. The Master-Slave configuration should be set to Slave by writing a value of
0x1000 to the Auto-Negotiation Master Slave Control Register.
To test each individual cable pair, set the cable pair in the Cable Diagnostics Test Pair (VCT_PAIR[1:0]) field of the
LinkMD Cable Diagnostic Register, along with setting the Cable Diagnostics Test Enable (VCT_EN) bit. The Cable Diag-
nostics Test Enable (VCT_EN) bit will self clear when the test is concluded.
The test results (for the pair just tested) are available in the LinkMD Cable Diagnostic Register. The Cable Diagnostics
Status (VCT_ST[1:0]) field will indicate a Normal (properly terminated), Open or Short condition.
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If the test result was Open or Short, the Cable Diagnostics Data or Threshold (VCT_DATA[7:0]) field indicates the dis-
tance to the fault in meters as approximately:
• distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
With an accuracy of +/- 2% to 3% for short and medium cables and +/- 5% to 6% for long cables.
APPLICATION NOTE: If the Cable Diagnostics Status (VCT_ST[1:0]) field indicates Failed, it is possible the link
partner is forced to 100BASE-TX or 1000BASE-T mode.
4.16 Self-Test Frame Generation and Checking
The device is capable of generating and checking frames. The device must be connected to a loopback connector or a
loopback cable. Pair A should be connected to pair B, and pair C to pair D, as shown in Figure 4-10.
Normally, the device does not require a 125MHz clock to be supplied into the TXC input pin. An external clock may be
used when the Self_test_external_clk_sel bit in the Self-Test Enable Register is set high.
Auto-negotiation should be disabled, full duplex set and the desired link speed set via the Basic Control Register.
For 10BASE-T and 100BASE-TX:
• Auto-MDIX should be disabled and the desired configuration (MDI vs. MDIX) selected via the Swap-Off and MDI
Set bits in the Auto-MDI/MDI-X Register. Selecting MDI vs. MDIX will test different sections of the PHY.
For 1000BASE-T:
• Set the Master-Slave configuration to master by setting the Master/Slave Manual Configuration Enable and Mas-
ter/Slave Manual Configuration Value bits in the Auto-Negotiation Master Slave Control Register.
• Enable the 1000BASE-T connector loopback by setting the Ext_lpbk bit in the External Loopback Register.
• Set the Ethernet MAC to 1000 Mbps operation (this is necessary so that a 125MHz clock is provided to the TXC
input pin).
The Self-Test mode is enabled by setting a frame count into the Self-Test Packet Count LO Register and Self-Test
Packet Count HI Register and then setting the following in order:
• Self_test_frame_cnt_en bit in the Self-Test Frame Count Enable Register
• Self_test_en bit in the Self-Test Enable Register
• Self_test_pgen_en bit in the Self-Test PGEN Enable Register
Once the Self_test_done bit in the Self-Test Status Register is set, the results can be determined through the following:
• Self-Test Correct Count HI Register / Self-Test Correct Count LO Register
• Self-Test Error Count HI Register / Self-Test Error Count LO Register
• Self-Test Bad SFD Count HI Register / Self-Test Bad SFD Count LO Register
4.17 NAND Tree Support
The KSZ9131MNX provides parametric NAND tree support for fault detection between chip I/Os and board. NAND tree
mode is enabled at power-up/reset with the MODE[3:0] strap-in pins set to ‘0100’. Table 4-9 lists the NAND tree pin
order. To test any given pin, the pin is toggled while holding the lower ranked pins low and the higher ranked pins high,
causing a toggle on the output of the tree.
APPLICATION NOTE: Since the NAND tree output is on the CLK125_NDO pin, the pin must be enabled for output
by using the CLK125_EN strap input.
TABLE 4-9:
NAND TREE TEST PIN ORDER FOR KSZ9131
Pin
Description
LED2
LED1/PME_N1
TXD0
Input
Input
Input
Input
Input
TXD1
TXD2
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TABLE 4-9:
NAND TREE TEST PIN ORDER FOR KSZ9131 (CONTINUED)
Pin
Description
TXD3
TXD4
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
TXD5
TXD6
TXD7
TX_ER
GTX_CLK
TX_EN
RXD7
RXD6
RXD5
RXD4
RXD3
RXD2
RXD1
RXD0
RX_DV
RX_ER
RX_CLK
CRS
COL
INT_N/PME_N2
MDC
MDIO
TX_CLK
CLK125_NDO
4.18 Power Management
The KSZ9131MNX incorporates a number of power-management modes and features that provide methods to con-
sume less energy. These are discussed in the following sections.
4.18.1
SMART POWER SAVING
For shorter cable lengths (< ~70 meters) the signal to noise ratio is sufficiently high to allow the reduction of ADC reso-
lution as well as DPS taps, Based on the detected cable length, the device automatically reduces power consumption
by approximately 20mW.
4.18.2
ENERGY-DETECT POWER-DOWN MODE (EDPD)
Energy-detect power-down (EDPD) mode is used to further reduce the transceiver power consumption when the cable
is unplugged. It is enabled by writing a one to the EDPD Mode Enable bit in the EDPD Control Register, and is in effect
when auto-negotiation mode is enabled and the cable is disconnected (no link).
In EDPD Mode, the KSZ9131MNX shuts down all transceiver blocks, except for the transmitter and energy detect cir-
cuits. Power can be reduced further by extending the time interval between the transmissions of link pulses to check for
the presence of a link partner. The periodic transmission of link pulses is needed to ensure the KSZ9131MNX and its
link partner, when operating in the same low-power state and with Auto MDI/MDI-X disabled, can wake up when the
cable is connected between them. By default, EDPD mode is disabled after power-up. Previous register setting are
maintained when EDPD mode is cleared. EDPD operation may be adjusted via the p_edpd_mask_timer[1:0], p_edpd_-
timer[1:0] and p_EDPD_random_dis fields in the EDPD Control Register within the MMD address space.
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KSZ9131MNX
4.18.3
SOFTWARE POWER-DOWN MODE (SPD)
The KSZ9131MNX supports a software power down (SPD) mode. This mode is used to power down the device when
it is not in use after power-up. Software power-down mode is enabled by writing a one to the Power Down bit in the
Basic Control Register. The device exits the SPD state after a zero is written to the Power Down bit.
In the SPD state, the device disables most internal functions.
During SPD, the crystal oscillator and PLL are enabled and the internal (125MHz and 250MHz) clocks are gated, The
standard registers (0 through 31) and the MII Management Interface operate using the crystal clock.
Previous register settings are maintained during and following the removal of SPD.
APPLICATION NOTE: The internal (125MHz and 250MHz) clock gating maybe overridden by setting the
spd_clock_gate_override bit in the Software Power Down Control Register at the cost of
increased power.
The following remain operational during SPD:
• MII Management Interface
- Only access to the standard registers (0 through 31) is supported.
- Access to MMD address spaces other than MMD address space 1 is possible if the spd_clock_gate_override
bit is set.
- Access to MMD address space 1 is not possible.
• Voltage Regulator Controller (LDO)
- The LDO controller can be disabled by setting the active low LDO enable bit in LDO Control Register. An
external source of 1.2V is necessary for operation in this case.
• PLL
- Normally the PLL is enabled during SPD. It may be disabled by setting the spd_pll_disable bit described in
Section 4.18.3.1, "SPD Extra Power Savings".
• Crystal Oscillator
- Normally the Crystal Oscillator is enabled during SPD. It may be disabled by setting the XTAL Disable bit
described in Section 4.18.3.1, "SPD Extra Power Savings".
The following are normally disabled during SPD:
• TX and RX clocks
- If the above mentioned spd_clock_gate_override bit is set, TX and RX clocks would be enabled. They may
alternately be stopped by setting the Isolate (PHY_ISO) bit in the Basic Control Register.
• CLK125_NDO pin
- If the above mentioned spd_clock_gate_override bit is set, CLK125_NDO would be enabled (if previously
enabled for clock output). It may alternately be disabled by clearing the clk125 Enable bit in Common Control
Register
4.18.3.1
SPD Extra Power Savings
To achieve a lower power usage, the PLL maybe disable during SPD by setting the spd_pll_disable bit in the Software
Power Down Control Register prior to entering SPD.
APPLICATION NOTE: A full device reset occurs following the removal of SPD, therefore previous register settings
are not maintained for this option.
To further reduce power usage, the crystal oscillator maybe disable by setting the XTAL Disable bit in the XTAL Control
Register after setting the spd_pll_disable bit and entering SPD.
Since the MII Management Interface operates using the crystal clock, once this bit is set, the device will become inac-
cessible. A pin reset or power cycle is required to resume operation.
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KSZ9131MNX
4.18.4
CHIP POWER-DOWN MODE (CPD)
This mode provides the lowest power state for the KSZ9131MNX device when it is mounted on the board but not in use.
Chip power-down (CPD) mode is enabled after power-up/reset with the MODE[3:0] strap-in pins set to ‘0111’. Chip
power-down mode can only be exited by removing device power.
4.19 Energy Efficient Ethernet
The KSZ9131MNX implements Energy Efficient Ethernet (EEE), as described in IEEE Standard 802.3az. The Standard
is defined around an EEE-compliant MAC on the host side and an EEE-compliant link partner on the line side that sup-
port the special signaling associated with EEE. EEE saves power by keeping theAC signal on the copper Ethernet cable
at approximately 0V peak-to-peak as often as possible during periods of no traffic activity, while maintaining the link-up
status. This is referred to as low-power idle (LPI) mode or state.
The KSZ9131MNX has the EEE function enabled as the power-up default setting. The EEE function can be disabled
by configuring the following EEE advertisement bits in the EEE Advertisement Register, followed by restarting auto-
negotiation (writing a ‘1’ to the Restart Auto-Negotiation (PHY_RST_AN) bit in the Basic Control Register:
• 1000BASE-T EEE bit = 0
• 100BASE-TX EEE bit = 0
// Disable 1000 Mbps EEE mode
// Disable 100 Mbps EEE mode
During LPI mode, the copper link responds automatically when it receives traffic and resumes normal PHY operation
immediately, without blockage of traffic or loss of packet. This involves exiting LPI mode and returning to normal 100/
1000 Mbps operating mode. The LPI state is controlled independently for transmit and receive paths, allowing the LPI
state to be active (enabled) for:
• Transmit cable path only
• Receive cable path only
• Both transmit and receive cable paths
During LPI mode, refresh transmissions are used to maintain the link; power savings occur in quiet periods. Approxi-
mately every 20 to 22 milliseconds, a refresh transmission of 200 to 220 microseconds is sent to the link partner. The
refresh transmissions and quiet periods are shown in Figure 4-11.
FIGURE 4-11:
LPI MODE (REFRESH TRANSMISSIONS AND QUIET PERIODS)
ACTIVE
LOW-POWER
ACTIVE
QUIET
TQ
QUIET
QUIET
TS
TR
TW_PHY
TW_SYSTEM
4.19.1
TRANSMIT DIRECTION CONTROL (MAC-TO-PHY)
The KSZ9131MNX enters LPI mode for the transmit direction when its attached EEE-compliant MAC de-asserts
TX_EN, asserts TX_ER, and sets TXD[7:0] to 0000_0001 for GMII (1000 Mbps) or TXD[3:0] to 0001 for MII (100 Mbps).
The KSZ9131MNX remains in the transmit LPI state while the MAC maintains the states of these signals. When the
MAC changes any of the TX_EN, TX_ER, or TX data signals from their LPI state values, the KSZ9131MNX exits the
LPI transmit state.
For GMII (1000 Mbps), the GTX_CLK clock can be stopped by the MAC to save additional power, after the GMII signals
for the LPI state have been asserted for nine or more GTX_CLK clock cycles.
Figure 4-12 shows the LPI transition for GMII transmit.
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KSZ9131MNX
FIGURE 4-12:
LPI TRANSITION - GMII (1000 MBPS) TRANSMIT
9 CLOCKS MINIMUM
GTX_CLK
TX_EN
TXD[7:0]
TX_ER
0x01
WAKE TIME
ENTER LOW-
EXIT LOW-
POWER IDLE
MODE
POWER
IDLE MODE
For MII (100 Mbps), the TX_CLK is not stopped, because it is sourced from the PHY and is used by the MAC for MII
transmit.
Figure 4-13 shows the LPI transition for MII transmit.
FIGURE 4-13:
LPI TRANSITION - MII (100 MBPS) TRANSMIT
TX_CLK
TX_EN
0001
TXD<3:0>
WAKE TIME
ENTER LOW
POWER STATE
EXIT LOW
POWER STATE
TX_ER
4.19.2
RECEIVE DIRECTION CONTROL (PHY-TO-MAC)
The KSZ9131MNX enters LPI mode for the receive direction when it receives the /P/ code bit pattern (Sleep/Refresh)
from its EEE-compliant link partner. It then de-asserts RX_DV, asserts RX_ER, and drives RXD[7:0] to 0000_0001 for
GMII (1000 Mbps) or RXD[3:0] to 0001 for MII (100 Mbps). The KSZ9131MNX remains in the receive LPI state while it
continues to receive the refresh from its link partner, so it will continue to maintain and drive the LPI output states for the
GMII/MII receive signals to inform the attached EEE-compliant MAC that it is in the receive LPI state. When the
KSZ9131MNX receives a non /P/ code bit pattern (non-refresh), it exits the receive LPI state and sets the RX_DV,
RX_ER, and RX data signals to set a normal frame or normal idle.
For GMII (1000 Mbps), the KSZ9131MNX stops the RX_CLK clock output to the MAC after nine or more RX_CLK clock
cycles have occurred in the receive LPI state, to save more power. The Clock-stop enable bit in the PCS Control 1 Reg-
ister controls if the device stops the RX_CLK clock output.
Figure 4-14 shows the LPI transition for GMII receive.
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KSZ9131MNX
FIGURE 4-14:
LPI TRANSITION - GMII (1000 MBPS) RECEIVE
AT LEAST 9 CLOCK CYCLES
RX_CLK
RX_DV
0x01
x
x
x
x
RXD<7:0>
WAKE TIME
ENTER LOW-
POWER IDLE
MODE
EXIT LOW-
POWER IDLE
MODE
RX_ER
Similarly, for MII (100 Mbps), the KSZ9131MNX stops the RX_CLK clock output to the MAC after nine or more RX_CLK
clock cycles have occurred in the receive LPI state, to save more power. The Clock-stop enable bit in the PCS Control
1 Register controls if the device stops the RX_CLK clock output.
Figure 4-15 shows the LPI transition for MII receive.
FIGURE 4-15:
LPI TRANSITION - MII (100 MBPS) RECEIVE
≥9 CYCLES
RX_CLK
RX_DV
0001
XX XX XX
XX XX XX XX
RXD<3:0>
RX_ER
4.19.3
10BASE-Te MODE
For standard (non-EEE) 10BASE-T mode, normal link pulses (NLPs) with long periods of no AC signal transmission are
used to maintain the link during the idle period when there is no traffic activity. To save more power, the device provides
the option to enable 10BASE-Te mode, which saves additional power by reducing the transmitted signal amplitude from
2.5V to 1.75V. 10BASE-Te mode is enabled by default and can be disabled by setting the p_cat3 bit in the AFED Control
Register in MMD space.
4.19.4
REGISTERS ASSOCIATED WITH EEE
The following MMD registers are provided for EEE configuration and management:
• MMD Address 3h, Register 0h — PCS Control 1 Register
• MMD Address 3h, Register 1h — PCS Status 1 Register
• MMD Address 7h, Register 3Ch — EEE Advertisement Register
• MMD Address 7h, Register 3Dh — EEE Link Partner Ability Register
4.20 Dynamic Channel Quality (DCQ) (TC1)
The KSZ9131MNX provides dynamic channel quality features that include Mean Square Error (MSE), Signal Quality
Indicator (SQI), and peak Mean Square Error (pMSE) values. These features are designed to be compliant with Sec-
tions 6.1.1, 6.1.2, and 6.1.3 of the OPEN Alliance TC1 - Advanced diagnostics features for 100BASE-T1 automotive
Ethernet PHYs Version 1.0 specification, respectively. These DCQ features are detailed in the following sections:
• Mean Square Error (MSE)
• Signal Quality Indicator (SQI)
• Peak Mean Square Error (pMSE)
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MLT-3 modulation is used for data transmission in 100BASE-TX and PAM5 modulation is used for data transmission in
1000BASE-T.
Logically, 100BASE-TX (MLT-3) and 1000BASE-T (PAM5) have signal values of {-1, 0, +1} and {-2, -1, 0, +1, +2},
respectively. These logic levels are mapped to slicer reference levels of {-128, 0, 128} for 100BASE-TX and {-128, -64,
0, 64, 128} for 1000BASE-T. The middle points (the compare thresholds) are {-64, 64} for 100BASE-TX and are {-96, -
32, 32, 96} for 1000BASE-T.
Ideally, each receive data sample would be the maximum distance from the compare thresholds, with error values of 0.
But because of noise and imperfection in real applications, the sampled data may be off from its ideal. The closer to the
compare threshold, the worse the signal quality.
The slicer error is a measurement of how far the processed data off from its ideal location. The largest instantaneous
slicer error for 1000BASE-T is +/-32. The largest instantaneous slicer error for 100BASE-TX is +/-64. A higher absolute
slicer error means a degraded signal receiving condition.
4.20.1
MEAN SQUARE ERROR (MSE)
This section defines the implementation of section 6.1.1 of the TC1 specification. The KSZ9131MNX can provide
detailed information of the dynamic signal quality by means of a MSE value. This mode is enabled by setting the sqi_en-
able bit in the DCQ Configuration Register. This bit must be set for all DCQ measurements.
With this method, the slicer error is converted into a squared value and then filtered by a programmable low pass filter.
This is similar to taking the average of absolute slicer error over a long moving time window. For each data sample, the
difference between the absolute slicer error (scaled by x2 (before squaring) for 1000BASE-T) and the current filtered
value is added back into the current filtered value.
Note:
The sqi_squ_mode_en bit in the DCQ Configuration Register must be set to choose square mode.
The sqi_kp field in the DCQ Configuration Register sets the weighting of the add back as a divide by 2^sqi_kp, effectively
setting the filter bandwidth. As the sqi_kp value is increased, the weighing is decreased, and the mean slicer error value
takes a longer time to settle to a stable value. Also as the sqi_kp value is increased, there will be less variation in the
mean slicer error value reported.
The scale611 field in the DCQ Configuration Register is used to set a divide by factor (divide by 2^scale611) such that the
MSE value is linearly scaled to the range of 0 to 511. If the divide by factor is too small, the MSE value is capped at a
maximum of 511.
In order to capture the MSE Value, the DCQ Read Capture bit in the DCQ Configuration Register needs to be written
as a high with the desired cable pair specified in the DCQ Channel Number field of the same register. The DCQ Read
Capture bit will immediately self-clear and the result will be available in the DCQ Mean Square Error Register. The fil-
tered error value is saved every 1.0 ms (125,000 symbols).
In addition to the current MSE Value, the worst case MSE value since the last read of DCQ Mean Square Error Register
is stored in DCQ Mean Square Error Worst Case Register.
4.20.2
SIGNAL QUALITY INDICATOR (SQI)
The KSZ9131MNX provides two SQI methods:
• SQI Method A: TC1 Section 6.1.2 compliant
• SQI Method B: Proprietary method
4.20.2.1
SQI Method A
This section defines the implementation of section 6.1.2 of the TC1 specification. This mode builds upon the Mean
Square Error (MSE) method by mapping the MSE value onto a simple quality index. This mode is enabled by setting
the sqi_enable bit, in the DCQ Configuration Register.
Note:
As in the Mean Square Error (MSE) method, the sqi_squ_mode_en bit in the DCQ Configuration Register
must be set to choose square mode and the scale611 field in the DCQ Configuration Register is used to
set the divide by factor (divide by 2^scale611) such that the MSE value is linearly scaled to the range of 0 to
511.
The MSE value is compared to the thresholds set in the DCQ SQI Table Registers to provide a SQI value between 0
(worst value) and 7 (best value) as follows:
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KSZ9131MNX
TABLE 4-10: MSE TO SQI MAPPING
MSE Value
SQI Value
Greater Than
Less Than or Equal To
SQI_TBL7.SQI_VALUE
SQI_TBL6.SQI_VALUE
SQI_TBL5.SQI_VALUE
SQI_TBL4.SQI_VALUE
SQI_TBL3.SQI_VALUE
SQI_TBL2.SQI_VALUE
SQI_TBL1.SQI_VALUE
7
6
5
4
3
2
1
0
SQI_TBL7.SQI_VALUE
SQI_TBL6.SQI_VALUE
SQI_TBL5.SQI_VALUE
SQI_TBL4.SQI_VALUE
SQI_TBL3.SQI_VALUE
SQI_TBL2.SQI_VALUE
SQI_TBL1.SQI_VALUE
In order to capture the SQI value, the DCQ Read Capture bit in the DCQ Configuration Register needs to be written as
a high with the desired cable pair specified in the DCQ Channel Number field of the same register. The DCQ Read Cap-
ture bit will immediately self-clear and the result will be available in the DCQ SQI Register.
In addition to the current SQI the worst case (lowest) SQI since the last read is available in the SQI Worst Case field.
The correlation between the SQI values stored in the DCQ SQI Register and an according signal to noise ratio (SNR)
based on AWG noise (bandwidth of 80MHz) is shown in Table 4-11. The bit error rates to be expected in the case of
white noise as interference signal is shown in the table as well for information purposes.
A link loss only occurs if the SQI value is 0.
TABLE 4-11: SQI VALUE CORRELATION
SQI Value
SNR Value @ MDI - AWG Noise
Recommended BER for AWG Noise Model
0
1
2
3
4
5
6
7
< 18 dB
18 dB <= SNR < 19 dB
19 dB <= SNR < 20 dB
20 dB <= SNR < 21 dB
21 dB <= SNR < 22 dB
22 dB <= SNR < 23 dB
23 dB <= SNR < 24 dB
SNR <= 24 dB
BER>10^-10
BER<10^-10
4.20.2.2
SQI Method B
With the SQI Method B, the slicer error is converted into an absolute value and then filtered by a programmable low
pass filter. This is similar to taking the average of absolute slicer error over a long moving time window. This mode is
enabled by setting the sqi_enable bit, in the DCQ Configuration Register.
For each data sample, the difference between the absolute slicer error (scaled by x2 (before squaring) for 1000BASE-
T) and the current filtered value is added back into the current filtered value. The sqi_squ_mode_en bit in the DCQ Con-
figuration Register is used to square the (scaled) slicer error.
The sqi_kp field in the DCQ Configuration Register sets the weighting of the add back as a divide by 2^sqi_kp, effectively
setting the filter bandwidth. As the sqi_kp value is increased, the weighing is decreased, and the mean slicer error value
takes a longer time to settle to a stable value. Also as the sqi_kp value is increased, there will be less variation in the
mean slicer error value reported.
In order to capture the current error value, the DCQ Read Capture bit in the DCQ Configuration Register needs to be
written as a high with the desired cable pair specified in the DCQ Channel Number field of the same register. The DCQ
Read Capture bit immediately self-clears and the result is available in the Mean Slicer Error Register. The filtered error
value is saved every 1.0 ms (125,000 symbols).
A software based lookup table (derived empirically in lab conditions) may be used to report a SQI number.
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KSZ9131MNX
4.20.3
PEAK MEAN SQUARE ERROR (PMSE)
This section defines the implementation of section 6.1.3 of the TC1 specification. The peak MSE value is intended to
identify transient disturbances which are typically in the microsecond range. This mode is enabled by setting the sqi_en-
able bit, in the DCQ Configuration Register.
With this method, the slicer error is converted into a squared value and then filtered by a programmable low pass filter.
This is similar to taking the average of absolute slicer error over a moving time window.
For each data sample, the difference between the absolute slicer error (scaled by x2 (before squaring) for 1000BASE-
T) and the current filtered value is added back into the current filtered value.
Note:
The sqi_squ_mode_en bit in the DCQ Configuration Register must be set to choose square mode.
The sqi_kp3 field in the DCQ Configuration Register sets the weighting of the add back as a divide by 2^(sqi_kp3), effec-
tively setting the filter bandwidth. As the sqi_kp3 value is increased, the weighing is decreased, and the mean slicer
error value takes a longer time to settle to a stable value.
Every 1.0ms (125,000 symbols), the highest filtered value over that previous 1.0ms period is saved.
The scale613 field in the DCQ Configuration Register is used to set a divide by factor (divide by 2^scale613+3) such that
the peak MSE value is linearly scaled to the range of 0 to 63. If the divided by factor is too small, the peak MSE value
is capped at a maximum of 63.
In order to capture the Peak MSE Value, the DCQ Read Capture bit in the DCQ Configuration Register needs to be
written as a high with the desired cable pair specified in the DCQ Channel Number field of the same register. The DCQ
Read Capture bit will immediately self-clear and the result will be available in the DCQ Peak MSE Register.
In addition to the current Peak MSE Value the worst case Peak MSE value since the last read of DCQ Peak MSE Reg-
ister is stored in the same register.
4.21 Quiet-WIRE® EMI Reduction
Quiet-WIRE® patented technology, delivers fully programmable, integrated noise filtering to reduce Ethernet line emis-
sions without need for additional external BoM components.
Quiet-WIRE® is enabled by setting the Quiet-WIRE Enable bit in MMD31 Register 19. Once the Quiet-WIRE Enable bit
is set, the transmit parameters must be configured through the EMITX Control Register and EMITX Coefficient Registers
in MMD address space. The values must be set as shown in the default column.
Quiet-WIRE® applies only to 100BASE-TX.
4.22 Wake-On-LAN
Wake-On-LAN (WOL) is normally a MAC-based function to wake up a host system (for example, an Ethernet end
device, such as a PC) that is in standby power mode. Wake-up is triggered by receiving and detecting a special packet
(commonly referred to as the “magic packet”) that is sent by the remote link partner. The KSZ9131MNX can perform the
same WOL function if the MAC address of its associated MAC device is entered into the KSZ9131MNX PHY registers
for magic-packet detection. When the KSZ9131MNX detects the magic packet, it wakes up the host by driving its power
management event (PME) output pin low.
By default, the WOLfunction is disabled. It is enabled by setting the enabling bit and configuring the associated registers
for the selected PME wake-up detection method.
The KSZ9131MNX provides three methods to trigger a PME wake-up:
• Magic-packet detection
• Customized-packet detection
• Link status change detection
4.22.1
MAGIC-PACKET DETECTION
The magic packet’s frame format starts with 6 bytes of 0xFFh and is followed by 16 repetitions of the MAC address of
its associated MAC device (local MAC device).
When the magic packet is detected from its link partner, the KSZ9131MNX asserts its PME output pin low.
The following MMD registers are provided for magic-packet detection:
• Magic-packet detection is enabled by writing a ‘1’ to the Enable Magic Packet Detection Wake Event bit of the
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KSZ9131MNX
Wake-On-LAN Control Register
• The MAC address (for the local MAC device) is written to and stored in the Wake-On-LAN-MAC-LO Register,
Wake-On-LAN-MAC-MI Register, and Wake-On-LAN-MAC-HI Register
The KSZ9131MNX does not generate the magic packet. The magic packet must be provided by the external system.
Magic packet detection status can be read from the Wake-on-LAN Magic Packet Receive Status Register.
4.22.2
CUSTOMIZED-PACKET DETECTION
The customized packet has associated register/bit masks to select which byte, or bytes, of the first 64 bytes of the packet
to use in the CRC calculation. After the KSZ9131MNX receives the packet from its link partner, the selected bytes for
the received packet are used to calculate the CRC. The calculated CRC is compared to the expected CRC value that
was previously written to and stored in the KSZ9131MNX PHY registers. If there is a match, the KSZ9131MNX asserts
its PME output pin low.
Four customized packets are provided to support four types of wake-up scenarios. A dedicated set of registers is used
to configure and enable each customized packet.
The following MMD registers are provided for customized-packet detection:
• Each of the four customized packets is enabled via the Enable Customized Frame Filter Wake Event field of the
Wake-On-LAN Control Register,
- Bit [2]
- Bit [3]
- Bit [4]
- Bit [5]
// For customized packets, type 0
// For customized packets, type 1
// For customized packets, type 2
// For customized packets, type 3
• 32-bit expected CRCs are written to and stored in:
- Customized-Pkt-0-CRC-LO Register and Customized-Pkt-0-CRC-HI Register (Type 0 customized packets)
- Customized-Pkt-1-CRC-LO Register and Customized-Pkt-1-CRC-HI Register (Type 1 customized packets)
- Customized-Pkt-2-CRC-LO Register and Customized-Pkt-2-CRC-HI Register (Type 2 customized packets)
- Customized-Pkt-3-CRC-LO Register and Customized-Pkt-3-CRC-HI Register (Type 3 customized packets)
• Masks to indicate which of the first 64-bytes to use in the CRC calculation are set in:
- Customized-Pkt-0-MASK_LL Register, Customized-Pkt-0-MASK_LH Register, Customized-Pkt-0-MASK_HL
Register, and Customized-Pkt-0-MASK_HH Register (Type 0 customized packets)
- Customized-Pkt-1-MASK_LL Register, Customized-Pkt-1-MASK_LH Register, Customized-Pkt-1-MASK_HL
Register, and Customized-Pkt-1-MASK_HH Register (Type 1 customized packets)
- Customized-Pkt-2-MASK_LL Register, Customized-Pkt-2-MASK_LH Register, Customized-Pkt-2-MASK_HL
Register, and Customized-Pkt-2-MASK_HH Register (Type 2 customized packets)
- Customized-Pkt-3-MASK_LL Register, Customized-Pkt-3-MASK_LH Register, Customized-Pkt-3-MASK_HL
Register, and Customized-Pkt-3-MASK_HH Register (Type 3 customized packets)
4.22.3
LINK STATUS CHANGE DETECTION
If link status change detection is enabled, the KSZ9131MNX asserts its PME output pin low whenever there is a link
status change using the following bits in the Wake-On-LAN Control Register:
• Enable Link Up Wake Event
• Enable Link Down Wake Event
// For link-up detection
// For link-down detection
The link change status can be read from the Interrupt Control/Status Register.
4.22.4
PME OUTPUT SIGNAL
The PME output signal is available on either LED1 as PME_N1 or INT_N as PME_N2, and is selected and enabled
using the gmii_pme_on_led1_mode and gmii_pme_on_int_mode fields in the Operation Mode Strap Override Register.
Additionally, the PME Output Select field in the Wake-On-LAN Control Register defines the output functions for PME_N1
and PME_N2.
When asserted, the PME output is cleared by disabling the register bit that enabled the PME trigger source (magic
packet, customized packet, link status change).
The PME output is active low.
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KSZ9131MNX
Note:
When mapped to INT_N, the polarity can be inverted by use of the Interrupt Polarity Invert bit in the Control
Register.
APPLICATION NOTE: When mapped to LED1, Enhanced LED mode must be disabled.
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KSZ9131MNX
5.0
REGISTER DESCRIPTIONS
This chapter describes the various control and status registers (CSRs).
Note:
RESERVED address space must not be written under any circumstances. Failure to heed this warn-
ing may result in untoward operation and unexpected results.
5.1
Register Map
The register space within the KSZ9131MNX consists of two distinct areas.
• Standard Registers (Direct register access)
• MDIO Manageable Device (MMD) Registers (Indirect register access)
The KSZ9131MNX supports the following standard registers. These registers are accessed through the SMI (MDIO/
MDC) interface.
TABLE 5-1:
Index
STANDARD REGISTERS
Index
Register Name
(in decimal) (in hex)
IEEE-Defined Registers
Basic Control Register
0
1
0
1
Basic Status Register
2
2
Device Identifier 1 Register
Device Identifier 2 Register
3
3
4
4
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Base Page Ability Register
Auto-Negotiation Expansion Register
Auto-Negotiation Next Page TX Register
Auto-Negotiation Next Page RX Register
Auto-Negotiation Master Slave Control Register
Auto-Negotiation Master Slave Status Register
RESERVED
5
5
6
6
7
7
8
8
9
9
10
11-12
13
14
15
Ah
Bh-Ch
Dh
Eh
Fh
MMD Access Control Register
MMD Access Address/Data Register
Extended Status Register
Vendor-Specific Registers
RESERVED
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Remote Loopback Register
LinkMD Cable Diagnostic Register
Digital PMA/PCS Status Register
RESERVED
RXER Counter Register
LED Mode Select Register
LED Behavior Register
RESERVED
MDIO Drive Register
KSZ9031 LED Mode Register
Interrupt Control/Status Register
Auto-MDI/MDI-X Register
Software Power Down Control Register
External Loopback Register
Control Register
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KSZ9131MNX
The device supports the following MMD device addresses and their associated register addresses, which make up the
indirect MMD registers.
TABLE 5-2:
MMD CONTROL AND STATUS REGISTERS MAP
MMD
Device
Address
(in decimal)
Index
(in
decimal)
Index
(in hex)
Register Name
225
226
227
228
229
230
231
E1h
E2h
E3h
E4h
E5h
E6h
E7h
Mean Slicer Error Register
DCQ Mean Square Error Register
DCQ Mean Square Error Worst Case Register
DCQ SQI Register
1
DCQ Peak MSE Register
DCQ Control Register
DCQ Configuration Register
232-238 E8h-EEh DCQ SQI Table Registers
0
1
0h
1h
2h
3h
4h
Common Control Register
Strap Status Register
2
Operation Mode Strap Override Register
Operation Mode Strap Register
Clock Invert and Control Signal Pad Skew Register
3
4
5-7
8
5h-7h RESERVED
8
Clock Pad Skew Register
9
9
Self-Test Packet Count LO Register
Self-Test Packet Count HI Register
Self-Test Status Register
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
Ah
Bh
Ch
Self-Test Frame Count Enable Register
Self-Test PGEN Enable Register
Self-Test Enable Register
Dh
Eh
Fh
RESERVED
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
20h
21h
Wake-On-LAN Control Register
Wake-On-LAN-MAC-LO Register
Wake-On-LAN-MAC-MI Register
Wake-On-LAN-MAC-HI Register
Customized-Pkt-0-CRC-LO Register
Customized-Pkt-0-CRC-HI Register
Customized-Pkt-1-CRC-LO Register
Customized-Pkt-1-CRC-HI Register
Customized-Pkt-2-CRC-LO Register
Customized-Pkt-2-CRC-HI Register
Customized-Pkt-3-CRC-LO Register
Customized-Pkt-3-CRC-HI Register
Customized-Pkt-0-MASK_LL Register
Customized-Pkt-0-MASK_LH Register
Customized-Pkt-0-MASK_HL Register
Customized-Pkt-0-MASK_HH Register
Customized-Pkt-1-MASK_LL Register
Customized-Pkt-1-MASK_LH Register
2
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KSZ9131MNX
TABLE 5-2:
MMD CONTROL AND STATUS REGISTERS MAP (CONTINUED)
MMD
Device
Address
(in decimal)
Index
(in
decimal)
Index
(in hex)
Register Name
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56-59
60
61
62
63
64
65
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
36h
37h
Customized-Pkt-1-MASK_HL Register
Customized-Pkt-1-MASK_HH Register
Customized-Pkt-2-MASK_LL Register
Customized-Pkt-2-MASK_LH Register
Customized-Pkt-2-MASK_HL Register
Customized-Pkt-2-MASK_HH Register
Customized-Pkt-3-MASK_LL Register
Customized-Pkt-3-MASK_LH Register
Customized-Pkt-3-MASK_HL Register
Customized-Pkt-3-MASK_HH Register
Wake-on-LAN Control Status Register
Wake-on-LAN Custom Packet Receive Status Register
Wake-on-LAN Magic Packet Receive Status Register
Wake-on-LAN Data Module Status Register
Customized Pkt-0 Received CRC-L Register
Customized Pkt-0 Received CRC-H Register
Customized Pkt-1 Received CRC-L Register
Customized Pkt-1 Received CRC-H Register
Customized Pkt-2 Received CRC-L Register
Customized Pkt-2 Received CRC-H Register
Customized Pkt-3 Received CRC-L Register
Customized Pkt-3 Received CRC-H Register
2 (cont.)
38h-3B RESERVED
3Ch
3Dh
3Eh
3Fh
40h
41h
Self-Test Correct Count LO Register
Self-Test Correct Count HI Register
Self-Test Error Count LO Register
Self-Test Error Count HI Register
Self-Test Bad SFD Count LO Register
Self-Test Bad SFD Count HI Register
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KSZ9131MNX
TABLE 5-2:
MMD CONTROL AND STATUS REGISTERS MAP (CONTINUED)
MMD
Device
Address
(in decimal)
Index
(in
decimal)
Index
(in hex)
Register Name
0
1
0
PCS Control 1 Register
1
PCS Status 1 Register
8
8
EEE Quiet Timer Register
EEE Update Timer Register
EEE Link-Fail Timer Register
EEE Post-Update Timer Register
EEE WaitWQ Timer Register
EEE Wake Timer Register
EEE WakeTX Timer Register
EEE WakeMz Timer Register
RESERVED
9
9
10
11
Ah
Bh
12
13
14
15
16
20
22
24
25
26
27
60
61
62
63
1
Ch
Dh
Eh
3
Fh
10h
14h
16h
18h
19h
1Ah
1Bh
3Ch
3Dh
3Eh
3Fh
1h
EEE Control and Capability Register
EEE Wake Error Counter Register
EEE 100 Timer-0 Register
EEE 100 Timer-1 Register
EEE 100 Timer-2 Register
EEE 100 Timer-3 Register
EEE Advertisement Register
EEE Link Partner Ability Register
EEE Link Partner Ability Override Register
EEE Message Code Register
XTAL Control Register
7
2-8
9
2h-8h RESERVED
9h
AFED Control Register
10-13
14
15-35
36
37
38-52
19
Ah-Dh RESERVED
28
(1Ch)
Eh
LDO Control Register
Fh-23h RESERVED
24h
25h
EDPD Control Register
EMITX Control Register
26h-34h EMITX Coefficient Registers
13h MMD31 Register 19
31
(1Fh)
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KSZ9131MNX
5.2
Standard Registers
Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE
802.3 Specification. Within this address space, the first 16 registers (Registers 0 to 15 (Fh)) are defined according to
the IEEE specification, while the remaining 16 registers (Registers 16 (10h) to 31 (1Fh)) are defined specific to the PHY
vendor.
5.2.1
BASIC CONTROL REGISTER
Index (In Decimal):
0
Size:
16 bits
This read/write register is used to configure the PHY.
Bits
Description
Type
Default
15
PHY Soft Reset (RESET)
When set, this bit resets all the PHY and all its registers to their default state.
This bit is self clearing.
R/W1S/
SC
0b
1 = PHY software reset.
14
13
Loopback (PHY_LOOPBACK)
R/W
R/W
0b
0b
This bit enables/disables the loopback mode. When enabled, transmissions
are not sent to network. Instead, they are looped back into the PHY.
0 = Loopback mode disabled (normal operation)
1 = Loopback mode enabled
Speed Select[0]
Together with Speed Select[1], sets speed per the following table:
[Speed Select1][Speed Select0]
00 = 10Mbps
01 = 100Mbps
10 = 1000Mbps
11 = Reserved
Note:
Ignored if the Auto-Negotiation Enable bit of this register is 1.
12
Auto-Negotiation Enable
This bit enables/disables Auto-Negotiation.
R/W
1b
0 = disable auto-negotiate process
1 = enable auto-negotiate process (overrides the Speed Select[0], Speed
Select[1] and Duplex Mode bits of this register)
11
10
Power Down
R/W
R/W
0b
0b
This bit controls the power down mode of the PHY.
0 = Normal operation
1 = General power down mode
Isolate (PHY_ISO)
This bit controls the isolation of the PHY from the MII interface.
0 = Non-Isolated (Normal operation)
1 = Isolated
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KSZ9131MNX
Bits
Description
Type
Default
9
Restart Auto-Negotiation (PHY_RST_AN)
R/W1S/
SC
0b
When set, this bit restarts the Auto-Negotiation process.
This bit is self clearing.
1 = Auto-Negotiation restarted
8
Duplex Mode
R/W
R/W
1b
0b
This bit is used to set the duplex.
0 = Half Duplex
1 = Full Duplex
Note:
Ignored if the Auto-Negotiation Enable bit of this register is 1.
7
Collision Test Mode (PHY_COL_TEST)
This bit enables/disables the collision test mode of the PHY. When set, the
collision signal is active during transmission. It is recommended that this fea-
ture be used only in loopback mode.
0 = Collision test mode disabled
1 = Collision test mode enabled
6
Speed Select[1]
R/W
R/W
1b
-
See description for Speed Select[0] for details.
RESERVED
5:0
5.2.2
BASIC STATUS REGISTER
Index (In Decimal):
1
Size:
16 bits
This register is used to monitor the status of the PHY.
Bits
Description
Type
Default
15
100BASE-T4
RO
0b
This bit displays the status of 100BASE-T4 compatibility.
0 = PHY not able to perform 100BASE-T4
1 = PHY able to perform 100BASE-T4
14
13
100BASE-X Full Duplex
RO
RO
1b
1b
This bit displays the status of 100BASE-X full duplex compatibility.
0 = PHY not able to perform 100BASE-X full duplex
1 = PHY able to perform 100BASE-X full duplex
100BASE-X Half Duplex
This bit displays the status of 100BASE-X half duplex compatibility.
0 = PHY not able to perform 100BASE-X half duplex
1 = PHY able to perform 100BASE-X half duplex
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KSZ9131MNX
Bits
Description
Type
Default
12
10BASE-T Full Duplex
This bit displays the status of 10BASE-T full duplex compatibility.
RO
1b
0 = PHY not able to perform 10BASE-T full duplex
1 = PHY able to perform 10BASE-T full duplex
11
10
9
10BASE-T Half Duplex
RO
RO
RO
RO
1b
0b
0b
1b
This bit displays the status of 10BASE-T half duplex compatibility.
0 = PHY not able to perform 10BASE-T half duplex
1 = PHY able to perform 10BASE-T half duplex
100BASE-T2 Full Duplex
This bit displays the status of 100BASE-T2 full duplex compatibility.
0 = PHY not able to perform 100BASE-T2 full duplex
1 = PHY able to perform 100BASE-T2 full duplex
100BASE-T2 Half Duplex
This bit displays the status of 100BASE-T2 half duplex compatibility.
0 = PHY not able to perform 100BASE-T2 half duplex
1 = PHY able to perform 100BASE-T2 half duplex
8
Extended Status
This bit displays whether extended status information is in register 15 (per
IEEE 802.3 clause 22.2.4).
0 = No extended status information in Register 15
1 = Extended status information in Register 15
7
6
Unidirectional Ability
RO
RO
0b
1b
This bit indicates whether the PHY is able to transmit regardless of whether
the PHY has determined that a valid link has been established.
0 = Can only transmit when a valid link has been established
1 = Can transmit regardless
MF Preamble Suppression
This bit indicates whether the PHY accepts management frames with the pre-
amble suppressed.
0 = Management frames with preamble suppressed not accepted
1 = Management frames with preamble suppressed accepted
5
4
Auto-Negotiation Complete
RO
0b
0b
This bit indicates the status of the Auto-Negotiation process.
0 = Auto-Negotiation process not completed
1 = Auto-Negotiation process completed
Remote Fault
RO/LH
This bit indicates if a remote fault condition has been detected.
0 = No remote fault condition detected
1 = Remote fault condition detected
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KSZ9131MNX
Bits
Description
Type
Default
3
2
1
0
Auto-Negotiation Ability
RO
1b
This bit indicates the PHY’s Auto-Negotiation ability.
0 = PHY is unable to perform Auto-Negotiation
1 = PHY is able to perform Auto-Negotiation
Link Status
This bit indicates the status of the link.
RO/LL
RO/LH
RO
0b
0b
1b
0 = Link is down
1 = Link is up
Jabber Detect
This bit indicates the status of the jabber condition.
0 = No jabber condition detected
1 = Jabber condition detected
Extended Capability
This bit indicates whether extended register capability is supported.
0 = Basic register set capabilities only
1 = Extended register set capabilities
5.2.3
DEVICE IDENTIFIER 1 REGISTER
Index (In Decimal):
2
Size:
16 bits
This register contains the MSB of the Organizationally Unique Identifier (OUI) for the PHY. The LSB of the PHY OUI is
contained in the Device Identifier 2 Register.
Bits
Description
Type
Default
15:0
PHY ID Number
RO
0022h
Assigned to the 3rd through 18th bits of the Organizationally Unique Identifier
(OUI), respectively.
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KSZ9131MNX
5.2.4
DEVICE IDENTIFIER 2 REGISTER
Index (In Decimal):
3
Size:
16 bits
This register contains the LSB of the Organizationally Unique Identifier (OUI) for the PHY. The MSB of the PHY OUI is
contained in the Device Identifier 1 Register.
Bits
Description
Type
Default
15:10
PHY ID Number
RO
000101b
Assigned to the 19th through 24th bits of the Organizationally Unique Identi-
fier (OUI), respectively.
9:4
3:0
Model Number
RO
RO
100100b
Note 5-1
Six-bit manufacturer’s model number.
Revision Number
Four-bit manufacturer’s revision number.
Note 5-1
Note:
The default value of the Revision Number field varies dependent on the silicon revision number.
The hexadecimal equivalent of this register is 1640h (A0) or 1641h (B0).
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5.2.5
AUTO-NEGOTIATION ADVERTISEMENT REGISTER
Index (In Decimal):
4
Size:
16 bits
This read/write register contains the advertised ability of the PHY and is used in the Auto-Negotiation process with the
link partner.
Bits
Description
Type
Default
15
Next Page
0 = No next page ability
R/W
0b
1 = Next page capable
14
13
RESERVED
RO
-
Remote Fault
R/W
0b
This bit determines if remote fault indication will be advertised to the link part-
ner.
0 = Remote fault indication not advertised
1 = Remote fault indication advertised
12
11
Extended Next Page
R/W
R/W
0b
1b
Note:
This bit should be written as 0.
Asymmetric Pause
This bit determines the advertised asymmetric pause capability.
0 = No Asymmetric PAUSE toward link partner advertised
1 = Asymmetric PAUSE toward link partner advertised
10
Symmetric Pause
R/W
R/W
1b
This bit determines the advertised symmetric pause capability.
0 = No Symmetric PAUSE toward link partner advertised
1 = Symmetric PAUSE toward link partner advertised
9
100BASE-T4
0 = no T4 ability
0
1 = T4 able
Note:
The device does not support this mode and this bit should always
be written as a 0.
8
7
100BASE-X Full Duplex
R/W
R/W
Note 5-2
Note 5-2
This bit determines the advertised 100BASE-X full duplex capability.
0 = 100BASE-X full duplex ability not advertised
1 = 100BASE-X full duplex ability advertised
100BASE-X Half Duplex
This bit determines the advertised 100BASE-X half duplex capability.
0 = 100BASE-X half duplex ability not advertised
1 = 100BASE-X half duplex ability advertised
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KSZ9131MNX
Bits
Description
Type
Default
6
10BASE-T Full Duplex
This bit determines the advertised 10BASE-T full duplex capability.
R/W
Note 5-2
0 = 10BASE-T full duplex ability not advertised
1 = 10BASE-T full duplex ability advertised
5
10BASE-T Half Duplex
R/W
R/W
Note 5-2
00001b
This bit determines the advertised 10BASE-T half duplex capability.
0 = 10BASE-T half duplex ability not advertised
1 = 10BASE-T half duplex ability advertised
4:0
Selector Field
This field identifies the type of message being sent by Auto-Negotiation.
00001 = IEEE 802.3
Note 5-2
Set by the MODE[3:0] strapping pins. Refer to Section 3.3, "Configuration Straps" for details.
5.2.6
AUTO-NEGOTIATION LINK PARTNER BASE PAGE ABILITY REGISTER
Index (In Decimal):
5
Size:
16 bits
This read-only register contains the advertised ability of the link partner’s PHY and is used in the Auto-Negotiation pro-
cess between the link partner and the PHY.
Bits
Description
Type
Default
15
Next Page
RO
0b
This bit indicates the link partner PHY page capability.
0 = Link partner PHY does not advertise next page capability
1 = Link partner PHY advertises next page capability
14
Acknowledge
RO
0b
This bit indicates whether the link code word has been received from the part-
ner.
0 = Link code word not yet received from partner
1 = Link code word received from partner
13
12
Remote Fault
RO
RO
0b
0b
This bit indicates whether a remote fault has been detected.
0 = No remote fault
1 = Remote fault detected
Extended Next Page
0 = Link partner PHY does not advertise extended next page capability
1 = Link partner PHY advertises extended next page capability
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KSZ9131MNX
Bits
Description
Type
Default
11
10
9
Asymmetric Pause
RO
0b
This bit indicates the link partner PHY asymmetric pause capability.
0 = No Asymmetric PAUSE toward link partner
1 = Asymmetric PAUSE toward link partner
Pause
RO
RO
RO
RO
RO
RO
RO
0b
0b
This bit indicates the link partner PHY symmetric pause capability.
0 = No Symmetric PAUSE toward link partner
1 = Symmetric PAUSE toward link partner
100BASE-T4
This bit indicates the link partner PHY 100BASE-T4 capability.
0 = 100BASE-T4 ability not supported
1 = 100BASE-T4 ability supported
8
100BASE-X Full Duplex
This bit indicates the link partner PHY 100BASE-X full duplex capability.
0b
0 = 100BASE-X full duplex ability not supported
1 = 100BASE-X full duplex ability supported
7
100BASE-X Half Duplex
This bit indicates the link partner PHY 100BASE-X half duplex capability.
0b
0 = 100BASE-X half duplex ability not supported
1 = 100BASE-X half duplex ability supported
6
10BASE-T Full Duplex
This bit indicates the link partner PHY 10BASE-T full duplex capability.
0b
0 = 10BASE-T full duplex ability not supported
1 = 10BASE-T full duplex ability supported
5
10BASE-T Half Duplex
This bit indicates the link partner PHY 10BASE-T half duplex capability.
0b
0 = 10BASE-T half duplex ability not supported
1 = 10BASE-T half duplex ability supported
4:0
Selector Field
00000b
This field identifies the type of message being sent by Auto-Negotiation.
00001 = IEEE 802.3
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KSZ9131MNX
5.2.7
AUTO-NEGOTIATION EXPANSION REGISTER
Index (In Decimal):
6
Size:
16 bits
This read/write register is used in the Auto-Negotiation process between the link partner and the PHY.
Bits
Description
Type
Default
15:7
6
RESERVED
RO
RO
-
Receive Next Page Location Able
1b
0 = Received next page storage location is not specified by bit 6.5
1 = Received next page storage location is specified by bit 6.5
5
Received Next Page Storage Location
RO
1b
0 = Link partner next pages are stored in the Auto-Negotiation Link Partner
Base Page Ability Register (PHY register 5)
1 = Link partner next pages are stored in the Auto-Negotiation Next Page RX
Register (PHY register 8)
4
3
2
1
0
Parallel Detection Fault
RO/LH
RO
0b
0b
1b
0b
0b
This bit indicates whether a Parallel Detection Fault has been detected.
0 = A fault hasn’t been detected via the Parallel Detection function
1 = A fault has been detected via the Parallel Detection function
Link Partner Next Page Able
This bit indicates whether the link partner has next page ability.
0 = Link partner does not contain next page capability
1 = Link partner contains next page capability
Next Page Able
This bit indicates whether the local device has next page ability.
RO
0 = Local device does not contain next page capability
1 = Local device contains next page capability
Page Received
This bit indicates the reception of a new page.
RO/LH
RO
0 = A new page has not been received
1 = A new page has been received
Link Partner Auto-Negotiation Able
This bit indicates the Auto-Negotiation ability of the link partner.
0 = Link partner is not Auto-Negotiation able
1 = Link partner is Auto-Negotiation able
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5.2.8
AUTO-NEGOTIATION NEXT PAGE TX REGISTER
Index (In Decimal):
7
Size:
16 bits
Bits
Description
Type
Default
15
Next Page
0 = No next page ability
1 = Next page capable
R/W
0b
14
13
RESERVED
RO
-
Message Page
0 = Unformatted page
R/W
1b
1 = Message page
12
11
Acknowledge 2
R/W
RO
0b
0b
0 = Device cannot comply with message.
1 = Device will comply with message.
Toggle
0 = Previous value was HIGH.
1 = Previous value was LOW.
10:0
Message Code
Message/Unformatted Code Field
R/W
000
0000
0001b
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5.2.9
AUTO-NEGOTIATION NEXT PAGE RX REGISTER
Index (In Decimal):
8
Size:
16 bits
Bits
Description
Type
Default
15
Next Page
0 = No next page ability
1 = Next page capable
RO
0b
14
Acknowledge
RO
0
This bit indicates whether the link code word has been received from the part-
ner.
0 = Link code word not yet received from partner
1 = Link code word received from partner
13
12
Message Page
RO
RO
RO
RO
0b
0b
0b
0 = Unformatted page
1 = Message page
Acknowledge 2
0 = Device cannot comply with message.
1 = Device will comply with message.
11
Toggle
0 = Previous value was HIGH.
1 = Previous value was LOW.
10:0
Message Code
Message/Unformatted Code Field
000
0000
0000b
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5.2.10
AUTO-NEGOTIATION MASTER SLAVE CONTROL REGISTER
Index (In Decimal):
9
Size:
16 bits
Bits
Description
Type
Default
15:13
Test Mode
R/W
000b
IEEE 802.3 clause 40.6.1.1.2 transmitter test mode.
000 = Normal mode
001 = Test Mode 1 - Transmit waveform test
010 = Test Mode 2 - Transmit jitter test in Master mode
011 = Test Mode 3 - Transmit jitter test in Slave mode
100 = Test Mode 4 - Transmitter distortion test
101 = Reserved
110 = Reserved
111 = Reserved
12
11
Master/Slave Manual Configuration Enable
R/W
R/W
0b
0b
0 = disable MASTER-SLAVE manual configuration value
1 = enable MASTER-SLAVE manual configuration value
Master/Slave Manual Configuration Value
Active only when the Master/Slave Manual Configuration Enable bit of this
register is 1.
0 = Configure PHY as slave
1 = Configure PHY as master
10
9
Port Type
R/W
R/W
R/W
0b
1b
0b
0 = single-port device
1 = multi-port device
1000BASE-T Full Duplex
0 = advertise PHY is not 1000BASE-T full duplex capable
1 = advertise PHY is 1000BASE-T full duplex capable
8
1000BASE-T Half Duplex
0 = advertise PHY is not 1000BASE-T half duplex capable
1 = advertise PHY is 1000BASE-T half duplex capable
Note:
The device does not support this mode and this bit should always
be written as a 0.
7:0
RESERVED
RO
-
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KSZ9131MNX
5.2.11
AUTO-NEGOTIATION MASTER SLAVE STATUS REGISTER
Index (In Decimal): 10
Size:
16 bits
Bits
Description
Master/Slave Configuration Fault
0 = No MASTER-SLAVE configuration fault detected
1 = MASTER-SLAVE configuration fault detected
Type
Default
15
RO/LH
0b
14
13
12
11
10
Master/Slave Configuration Resolution
RO
RO
RO
RO
RO
0b
0b
0b
0b
0b
0 = Local PHY configuration resolved to SLAVE
1 = Local PHY configuration resolved to MASTER
Local 1000BASE-T Receiver Status
0 = Local Receiver not OK
1 = Local Receiver OK
Remote (Link Partner) Receiver Status
0 = Remote Receiver not OK
1 = Remote Receiver OK
Link Partner Advertised 1000BASE-T Full Duplex Capability
0 = Link Partner is not capable of 1000BASE-T full duplex
1 = Link Partner is capable of 1000BASE-T full duplex
Link Partner Advertised 1000BASE-T Half Duplex Capability
0 = Link Partner is not capable of 1000BASE-T half duplex
1 = Link Partner is capable of 1000BASE-T half duplex
9:8
7:0
RESERVED
RO
-
1000BASE-T Idle Error Count
Cumulative count of the errors detected when the receiver is receiving idles.
RO/RC
00h
Note:
This counter halts at a value of 0xFF.
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KSZ9131MNX
5.2.12
MMD ACCESS CONTROL REGISTER
Index (In Decimal): 13
Size:
16 bits
Bits
Description
Type
Default
15:14
MMD Function
This field is used to select the desired MMD function:
00 = Address
R/W
00b
01 = Data, no post increment
10 = Data, post increment on reads and writes
11 = Data, post increment on writes only
13:5
4:0
RESERVED
RO
-
MMD Device Address (DEVAD)
This field is used to select the desired MMD device address.
R/W
00000b
5.2.13
MMD ACCESS ADDRESS/DATA REGISTER
Index (In Decimal): 14
Size:
16 bits
Bits
Description
Type
Default
15:0
MMD Register Address/Data
R/W
0000h
If the MMD Function field of the MMD Access Control Register is “00”, this
field is used to indicate the MMD register address to read/write of the device
specified in the MMD Device Address (DEVAD) field. Otherwise, this register
is used to read/write data from/to the previously specified MMD address.
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KSZ9131MNX
5.2.14
EXTENDED STATUS REGISTER
Index (In Decimal): 15
Size:
16 bits
This register is used to monitor the status of the PHY.
Bits
Description
Type
Default
15
1000BASE-X Full Duplex
This bit displays the status of 1000BASE-X full duplex compatibility.
RO
0b
0 = PHY not able to perform 1000BASE-X full duplex
1 = PHY able to perform 1000BASE-X full duplex
14
13
12
1000BASE-X Half Duplex
RO
RO
RO
RO
0b
1b
0b
-
This bit displays the status of 1000BASE-X half duplex compatibility.
0 = PHY not able to perform 1000BASE-X half duplex
1 = PHY able to perform 1000BASE-X half duplex
1000BASE-T Full Duplex
This bit displays the status of 1000BASE-T full duplex compatibility.
0 = PHY not able to perform 1000BASE-T full duplex
1 = PHY able to perform 1000BASE-T full duplex
1000BASE-T Half Duplex
This bit displays the status of 1000BASE-T half duplex compatibility.
0 = PHY not able to perform 1000BASE-T half duplex
1 = PHY able to perform 1000BASE-T half duplex
11:0
RESERVED
5.2.15
REMOTE LOOPBACK REGISTER
Index (In Decimal): 17
Size:
16 bits
Bits
Description
Type
Default
15:9
8
RESERVED
RO
-
Remote Loopback
1 = Enable remote loopback
R/W
0b
0 = Disable remote loopback
7:0
RESERVED
RO
-
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DS00002840C-page 65
KSZ9131MNX
5.2.16
LINKMD CABLE DIAGNOSTIC REGISTER
Index (In Decimal): 18
Size:
16 bits
Bits
Description
Type
Default
15
Cable Diagnostics Test Enable (VCT_EN)
Writing a 1 enables the test.
R/W/SC
0b
This bit is self-cleared when the test is complete.
Writing a 0 will disable the test.
Reading a 0 indicates the cable diagnostic test is completed and the status
information is valid.
Reading a 1 indicates the cable diagnostic test is in progress and the status
information is NOT valid.
14
Cable Diagnostic Disable Transmitter (VCT_DIS_TX)
R/W
R/W
0b
[0] = The transmitter is enabled to start cable diagnostic.
[1] = The transmitter is disabled and cable diagnostic is on hold to break
down the link.
13:12
Cable Diagnostics Test Pair (VCT_PAIR[1:0])
This field defines which channel to be tested.
00b
00 = Pair A
01 = Pair B
10 = Pair C
11 = Pair D
11:10
9:8
RESERVED
R/W
RO
00b
00b
Cable Diagnostics Status (VCT_ST[1:0])
Valid only when VCT_EN = 0.
00 = Normal, no fault has been detected
01 = Open Fault has been detected
10 = Short Fault has been detected
11 = Cable diagnostic test failed
7:0
Cable Diagnostics Data or Threshold (VCT_DATA[7:0])
This is the data of cable diagnostics. Valid only when VCT_EN = 0.
RO
00h
(1) If cable is normal, i.e., VCT_ST = 00, VCT_DATA don’t care.
(2) If cable is open or short, i.e., VCT_ST = 01 or 10, the distance to fault is
approximately 0.8 * (VCT_DATA - 22) (Meters) (see Section 4.15)
(3) If cable diagnostics failed, i.e., VCT_ST = 11,
Bit[7] = 1 means invalid reflected pulse width, i.e. equal or greater than
152ns, equal or less than 48ns.
Bit[6] = 1 means cable has signal for too long time during WAIT state. It’s
unusual and for debug only.
Bit[5] = 1 means mask100 detected and no silent time window can be found
for diagnostics. It means high frequency signal is found on the line. The link
partner probably is in forced 100BT or 1000BT mode.
Bit[4] = 1 means signals faster than NLP and FLP exists and no silent time
window can be found for diagnostics. It’s unusual and for debug only.
Bit[3:2] = number of low pulses detected. If more than 3, stay at 3.
Bit[1:0] = number of high pulses detected. If more than 3, stay at 3.
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KSZ9131MNX
5.2.17
DIGITAL PMA/PCS STATUS REGISTER
Index (In Decimal): 19
Size:
16 bits
Bits
Description
Type
Default
15:2
1
RESERVED
RO
RO
-
1000BT link status
1000 BT link status
0b
1 = link status OK
0 = link status not OK
0
100BT link status
100 BT link status
RO
0b
1 = link status OK
0 = link status not OK
5.2.18
RXER COUNTER REGISTER
Index (In Decimal): 21
Size:
16 bits
Bits
Description
Type
Default
15:0
RXER Counter
RX Error counter for the RX_ER signal
RC
0000h
Note:
This counter halts at a value of 0xFFFF.
5.2.19
LED MODE SELECT REGISTER
Index (In Decimal): 22
Size:
16 bits
This register selects the operating mode of the PHY LEDs when in extended mode. This register is only used when the
KSZ9031 LED Mode bit in the KSZ9031 LED Mode Register is clear.
Bits
15:8
7:4
Description
Type
R/W
R/W
Default
-
RESERVED
LED2 Configuration
0010b
This field configures the LED2 pin function. Refer to Table 4-8 for definitions.
3:0
LED1 Configuration
This field configures the LED1 pin function. Refer to Table 4-8 for definitions.
R/W
0001b
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5.2.20
LED BEHAVIOR REGISTER
Index (In Decimal): 23
Size:
16 bits
This register selects the operating parameters of the PHY LEDs when in extended mode. This register is only used when
the KSZ9031 LED Mode bit in the KSZ9031 LED Mode Register is clear.
Bits
Description
Type
Default
15
RESERVED
R/W
-
14
13
LED Activity Output Select
RESERVED
R/W
R/W
R/W
R/W
0b
-
12
LED Pulsing Enable
1b
00b
11:10
LED Blink / Pulse-Stretch Rate
00 = 2.5 Hz Blink Rate / 400 ms pulse-stretch
01 = 5 Hz Blink Rate / 200 ms pulse-stretch
10 = 10 Hz Blink Rate / 100 ms pulse-stretch
11 = 20 Hz Blink Rate / 50 ms pulse-stretch
9:7
6:5
RESERVED
R/W
R/W
-
LED Pulse Stretch Enables
Configures LED2 (bit 6) and LED1 (bit 5) to either pulse-stretch when 1, or
00b
blink when 0.
4:2
1:0
RESERVED
R/W
R/W
-
LED Combination Disables
Configures LED2 (bit 1) and LED1 (bit 0) to either combine link/activity and
00b
duplex/collision when 0, or disable combination, providing link-only and
duplex-only when 1.
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KSZ9131MNX
5.2.21
MDIO DRIVE REGISTER
Index (In Decimal): 25
Size:
16 bits
Bits
Description
Type
Default
15:2
1
RESERVED
R/W
R/W
-
MDIO Drive
When set to a 0, the MDIO output is open-drain
0b
When set to a 1, the MDIO output is push-pull
0
RESERVED
R/W
-
5.2.22
KSZ9031 LED MODE REGISTER
Index (In Decimal): 26
Size:
16 bits
Bits
Description
Type
Default
15
14
RESERVED
R/W
R/W
-
KSZ9031 LED Mode
1 = KSZ9031 LED mode
1b
0 = Extended LED mode
Note:
For normal LED operation, this bit should always be written as a 1.
13:0
RESERVED
R/W
-
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KSZ9131MNX
5.2.23
INTERRUPT CONTROL/STATUS REGISTER
Index (In Decimal): 27
Size:
16 bits
Bits
Description
Type
Default
15
Jabber Interrupt Enable
1 = Enable jabber interrupt
0 = Disable jabber interrupt
R/W
0b
14
13
12
11
10
9
Receive Error Interrupt Enable
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RC
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
0b
1 = Enable receive error interrupt
0 = Disable receive error interrupt
Page Received Interrupt Enable
1 = Enable page received interrupt
0 = Disable page received interrupt
Parallel Detect Fault Interrupt Enable
1 = Enable parallel detection fault interrupt
0 = Disable parallel detection fault interrupt
Link Partner Acknowledge Interrupt Enable
1 = Enable link partner acknowledge interrupt
0 = Disable link partner acknowledge interrupt
Link Down Interrupt Enable
1 = Enable link down interrupt
0 = Disable link down interrupt
Remote Fault Interrupt Enable
1 = Enable remote fault interrupt
0 = Disable remote fault interrupt
8
Link Up Interrupt Enable
1 = Enable link up interrupt
0 = Disable link up interrupt
7
Jabber Interrupt
1 = Jabber interrupt
0 = No jabber interrupt
6
Receive Error Interrupt
1 = Receive error interrupt
0 = No receive error interrupt
RC
5
Page Receive Interrupt
1 = Page receive interrupt
0 = No page receive interrupt
RC
4
Parallel Detect Fault Interrupt
1 = Parallel detection fault interrupt
0 = No parallel detection fault interrupt
RC
3
Link Partner Acknowledge Interrupt
1 = Link partner acknowledge interrupt
0 = No link partner acknowledge interrupt
RC
2
Link Down Interrupt
1 = Link down interrupt
RC
0 = No link down interrupt
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KSZ9131MNX
Bits
Description
Type
Default
1
Remote Fault Interrupt
1 = Remote fault interrupt
RC
0b
0 = No remote fault interrupt
0
Link Up Interrupt
RC
0b
1 = Link up interrupt
0 = No link up interrupt
5.2.24
AUTO-MDI/MDI-X REGISTER
Index (In Decimal): 28
Size:
16 bits
Bits
Description
Type
Default
15:8
7
RESERVED
MDI Set
RO
-
R/W
0b
When the Swap-Off bit of this register is asserted (1),
1 = PHY is set to operate in MDI mode
0 = PHY is set to operate in MDI-X mode
6
Swap-Off
R/W
RO
0b
-
1 = Disable Auto-MDI/MDI-X function
0 = Enable Auto-MDI/MDI-X function
5:0
RESERVED
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5.2.25
SOFTWARE POWER DOWN CONTROL REGISTER
Index (In Decimal): 29
Size:
16 bits
Bits
Description
Type
Default
15:12
11
RESERVED
spd_clock_gate_override
0 = internal clocks are gated during the Software Power Down (SPD) mode.
1 = internal clock gating is overridden during the SPD mode.
R/W
R/W
-
0b
10
spd_pll_disable
0 = PLL is enabled during the Software Power Down (SPD) mode.
R/W
0b
1 = PLL is disabled during the SPD mode.
9:8
7
RESERVED
R/W
R/W
-
IO_DC_test_en
1 = enable IO test
0b
6
VOH
R/W
0b
1 = “VDD” to output IO
0 = “GND” to IO
5.2.26
EXTERNAL LOOPBACK REGISTER
Index (In Decimal): 30
Size:
16 bits
Bits
Description
Type
Default
15:4
3
RESERVED
R/W
R/W
-
Ext_lpbk
External loopback enable
0b
2:0
RESERVED
R/W
-
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KSZ9131MNX
5.2.27
CONTROL REGISTER
Index (In Decimal): 31
Size:
16 bits
Bits
Description
Type
Default
15
14
RESERVED
RO
-
Interrupt Polarity Invert
1 = invert
R/W
0b
0 = normal
13:10
9
RESERVED
RO
-
Enable Jabber
1 = Enable jabber counter
R/W
1b
0 = Disable
8
Enable SQE Test
1 = Enable SQE test
R/W
1b
0 = Disable
7
6
RESERVED
RO
RO
-
Speed status 1000T
Indicates speed is 1000T
0b
5
4
3
2
Speed status 100TX
RO
RO
RO
RO
0b
0b
0b
0b
Indicates speed is 100TX
Speed status 10BT
Indicates speed is 10BT
Duplex status
Indicates duplex status
1000BASE-T Mater/Slave status
1 = Indicates 1000BASE-T Master mode
0 = Indicates 1000BASE-T Slave mode
1
0
Software Reset
W1S/RC
RC
0b
0b
1 = Reset PHY except all registers
0 = Disable reset
Link Status Check Fail
1 = Fail
0 = Not Failing
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KSZ9131MNX
5.3
MDIO Manageable Device (MMD) Registers
MMD registers provide indirect read/write access to up to 32 MMD device addresses with each device supporting up to
65,536 16-bit registers, as defined in Clause 22 of the IEEE 802.3 Specification. This device, however, uses only a small
fraction of the available registers. See Table 5-2 for a list of supported MMD device addresses and their associated reg-
ister addresses. These registers are accessed through the SMI (MDIO/MDC) interface.
The following two standard registers serve as the portal registers to access the indirect MMD registers.
• MMD Access Control Register
• MMD Access Address/Data Register
Example: MMD Register Write
Write MMD - Device Address 2h, Register 10h = 0001h to enable link-up detection to trigger PME for WOL.
1. Write the MMD Access Control Register with 0002h // Select address register for MMD – Device Address 2h.
2. Write the MMD Access Address/Data Register with 0010h // Set address register = 10h.
3. Write the MMD Access Control Register with 4002h // Select data register for MMD – Device Address 2h.
4. Write the MMD Access Address/Data Register with 0001h // Write value 0001h to MMD – Device Address 2h,
Register 10h.
Example: MMD Register Read
Read MMD - Device Address 3h, Register 14h EEE Control and Capability.
1. Write the MMD Access Control Register with 0003h // Select address register for MMD – Device Address 3h.
2. Write the MMD Access Address/Data Register with 0014h // Set address register = 14h.
3. Write the MMD Access Control Register with 4003h // Select data register for MMD – Device Address 3h.
4. Read the MMD Access Address/Data Register // Read data in MMD – Device Address 3h, Register 14h.
It is also possible to automatically increment the register address for reads and/or writes
Example: MMD Register Writes with Post Increment
Write MMD - Device Address 2h, Register 11h – 13h = 0123_4567_89ABh for the magic packet’s MAC address.
1. Write the MMD Access Control Register with 0002h // Select address register for MMD – Device Address 2h.
2. Write the MMD Access Address/Data Register with 0011h // Set address register = 11h.
3. Write the MMD Access Control Register with 8002h or C002h // Select data register with post increment for MMD
– Device Address 2h.
4. Write the MMD Access Address/Data Register with 0123h // Write value 0123h to MMD – Device Address 2h,
Register 11h.
5. Write the MMD Access Address/Data Register with 4567h // Write value 4567h to MMD – Device Address 2h,
Register 12h.
6. Write the MMD Access Address/Data Register with 89ABh // Write value 89ABh to MMD – Device Address 2h,
Register 13h.
Example: MMD Register Reads with Post Increment
Read MMD - Device Address 2h, Register 11h – 13h for the magic packet’s MAC address.
1. Write the MMD Access Control Register with 0002h // Select address register for MMD – Device Address 2h.
2. Write the MMD Access Address/Data Register with 0011h // Set address register = 11h.
3. Write the MMD Access Control Register with 8002h // Select data register with post increment for MMD – Device
Address 2h.
4. Read the MMD Access Address/Data Register // Read data in MMD – Device Address 2h, Register 11h.
5. Read the MMD Access Address/Data Register // Read data in MMD – Device Address 2h, Register 12h.
6. Read the MMD Access Address/Data Register // Read data in MMD – Device Address 2h, Register 13h.
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KSZ9131MNX
5.3.1
MEAN SLICER ERROR REGISTER
Index (In Decimal): 1.225
Size:
16 bits
Bits
15:0
Description
Type
Default
Mean Slicer Error
RO
0000h
This field provides the current mean error value. Either absolute or square
mode values can be provided.
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
5.3.2
DCQ MEAN SQUARE ERROR REGISTER
Index (In Decimal): 1.226
Size:
16 bits
Bits
15:10
9
Description
Type
RO
Default
RESERVED
-
MSE Value Valid
RO
0b
This field provides the mean square error valid indication.
1 = invalid
0 = valid
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
8:0
MSE Value
RO
000h
This field provides the current mean square error value.
Note:
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
The DCQ Channel Number field specifies which channel is
captured.
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KSZ9131MNX
5.3.3
DCQ MEAN SQUARE ERROR WORST CASE REGISTER
Index (In Decimal): 1.227
Size:
16 bits
Bits
Description
Type
RO
Default
15:10
9
RESERVED
MSE Worst Case Value Valid
-
RO
0b
This field provides the worst case mean square error valid indication.
1 = invalid
0 = valid
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
8:0
MSE Worst Case Value
This field provides the worst case mean square error value since the last time
RO
000h
the channel was captured for reading.
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
5.3.4
DCQ SQI REGISTER
Index (In Decimal): 1.228
Size:
16 bits
Bits
15:8
7:5
Description
Type
RO
Default
-
RESERVED
SQI Worst Case
RO
000b
This field indicates the worst case SQI value since the last time the channel
was captured for reading.
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
4
RESERVED
RO
-
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KSZ9131MNX
Bits
Description
Type
Default
3:1
SQI
This field indicates the current SQI value.
RO
000b
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
0
RESERVED
RO
-
5.3.5
DCQ PEAK MSE REGISTER
Index (In Decimal): 1.229
Size:
16 bits
Bits
Description
Type
Default
15:8
Peak MSE Worst Case
RO
00h
This field indicates the worst case peak MSE value since the last time the
channel was captured for reading.
0-63 = Peak MSE
64-254 = Invalid
255 = measurement not ready
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
Note:
The DCQ Channel Number field specifies which channel is
captured.
7:0
Peak MSE Value
This field provides the current peak MSE value.
RO
00h
0-63 = Peak MSE
64-254 = Invalid
255 = measurement not ready
Note:
Note:
This field is updated when the DCQ Read Capture bit in the DCQ
Control Register is written as a 1.
The DCQ Channel Number field specifies which channel is
captured.
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KSZ9131MNX
5.3.6
DCQ CONTROL REGISTER
Index (In Decimal): 1.230
Size:
16 bits
Bits
Description
Type
Default
15
DCQ Read Capture
When this bit is set the DCQ values are captured.
R/W/SC
0b
14:2
1:0
RESERVED
R/W
R/W
-
DCQ Channel Number
This field specifies which channel’s (wire pair) values are captured into the
00b
DCQ registers.
00 = Channel A
01 = Channel B
10 = Channel C
11 = Channel D
Note:
Channel A is used for both 100BASE-TX and 1000BASE-T.
Channels B-D are only used for 1000BASE-T.
5.3.7
DCQ CONFIGURATION REGISTER
Index (In Decimal): 1.231
Size:
16 bits
Bits
Description
Type
Default
15:14
scale613
R/W
00b
Scaling factor for SQI method 5 (TC1 peak MSE).
13:10
9:8
7
sqi_kp3
R/W
R/W
R/W
101b
00b
0b
LPF bandwidth control.for SQI method 5 (TC1 peak MSE).
scale611
Scaling factor for SQI methods 3 (TC1 MSE) and 4 (TC1 SQI).
sqi_reset
When set the SQI logic is reset.
Note:
This bit does not self-clear.
6
sqi_squ_mode_en
0 = Absolute mode
R/W
1b
1 = Square mode
5
sqi_enable
R/W
R/W
1b
When set SQI measurements are enabled.
4:0
sqi_kp
0Dh
LPF bandwidth control.for SQI methods 2 (non TC1 LPF mean), 3 (TC1 MSE)
and 4 (TC1 SQI).
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KSZ9131MNX
5.3.8
DCQ SQI TABLE REGISTERS
Index (In Decimal): 1.232-238
Size:
16 bits
Bits
Description
Type
RO
Default
-
15:9
8:0
RESERVED
SQI_VALUE
R/W
Table 5-3
Lookup table utilized for implement of SQI method 4 (TC1 SQI). These regis-
ters set the thresholds to map the error value to a SQI level.
TABLE 5-3:
SQI VALUE DEFAULTS
Default
(Hexadecimal)
Register
SQI_TBL1.SQI_VALUE
SQI_TBL2.SQI_VALUE
SQI_TBL3.SQI_VALUE
SQI_TBL4.SQI_VALUE
SQI_TBL5.SQI_VALUE
SQI_TBL6.SQI_VALUE
SQI_TBL7.SQI_VALUE
A3h
82h
67h
52h
41h
34h
29h
5.3.9
COMMON CONTROL REGISTER
Index (In Decimal): 2.0
Size:
16 bits
Bits
Description
Type
RO
Default
-
15:5
4
RESERVED
Single LED
1 = Individual-LED mode
R/W
Note 5-3
0 = Tri-color-LED mode
By default, this bit reflects the value of the LED_MODE strapping pin.
If written as a 1, the value of the LED_MODE strapping pin is overridden and
Single-LED mode is selected.
3:2
1
RESERVED
R/W
R/W
-
clk125 Enable
Note 5-4
A 1 enables the 125 MHz clock output onto the CLK125_NDO pin.
0
All-PHYAD Enable
When this bit is set, the PHY will respond to PHY address 0 as well as it’s
assigned PHY address.
R/W
Note 5-5
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KSZ9131MNX
Note 5-3
Note 5-4
Note 5-5
Set by the LED_MODE strapping pin. See Section 3.3, "Configuration Straps" for details.
Set by the CLK125_EN strapping pin. See Section 3.3, "Configuration Straps" for details.
Set by the inverse of the ALLPHYAD strapping pin. See Section 3.3, "Configuration Straps" for
details.
5.3.10
STRAP STATUS REGISTER
Index (In Decimal): 2.1
Size:
16 bits
Bits
15:8
7
Description
Type
RO
Default
-
RESERVED
LED_MODE Strap-In Status
1 = Individual LED mode
RO
Note 5-6
0 = Tri-color LED mode
6
5
RESERVED
RO
RO
-
CLK125_EN Strap-In Status
1 = CLK125_EN strap-in is enabled
Note 5-7
0 = CLK125_EN strap-in is disabled
4:0
PHYAD[2:0] Strap-In Status
Strap-in value for PHY address
RO
Note 5-8
Note:
Bits [4:3] of PHY address are always set to ‘00’.
Note 5-6
Note 5-7
Note 5-8
Set by the LED_MODE strapping pin. See Section 3.3, "Configuration Straps" for details.
Set by the CLK125_EN strapping pin. See Section 3.3, "Configuration Straps" for details
Set by the PHYAD[2:0] strapping pins. See Section 3.3, "Configuration Straps" for details.
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KSZ9131MNX
5.3.11
OPERATION MODE STRAP OVERRIDE REGISTER
Index (In Decimal): 2.2
Size:
16 bits
This register may be used to override the value of the MODE[3:0] configuration straps.
Bits
15:14
13:12
11
Description
Type
RO
Default
RESERVED
-
RESERVED
RO
-
gmii_pme_on_int_mode
R/W
Note 5-9
1 = GMII mode with PME_N2 mapped onto INT_N
10
9
RESERVED
RO
-
gmii_pme_on_led1_mode
1 = GMII mode with PME_N1 mapped onto LED1
R/W
Note 5-9
8
7
RESERVED
RO
RO
-
iddq_mode
Chip IDDQ Power-Down
Note 5-9
1 = Chip power-down mode
6:5
4
RESERVED
RO
-
ntree_mode
NAND Tree mode
R/W
Note 5-9
1 = NAND Tree mode
3:2
1
RESERVED
RO
-
gmii_mode
GMII/MII mode
R/W
Note 5-9
1 = GMII/MII mode
0
RESERVED
RO
-
Note 5-9
Set by the MODE[3:0] strapping pins. See Section 3.3, "Configuration Straps" for details.
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KSZ9131MNX
5.3.12
OPERATION MODE STRAP REGISTER
Index (In Decimal): 2.3
Size:
16 bits
This register indicates the value of the MODE[3:0] configuration straps that were latched into the device at reset.
Bits
15:14
13:12
11
Description
Type
RO
Default
RESERVED
-
RESERVED
RO
-
Strap_gmii_pme_on_int_mode
1 = GMII mode with PME_N2 mapped onto INT_N
RO
Note 5-10
10
9
RESERVED
RO
RO
-
Strap_gmii_pme_on_led1_mode
1 = GMII mode with PME_N1 mapped onto LED1
Note 5-10
8
7
RESERVED
RO
RO
-
Strap_iddq_mode
Chip IDDQ Power-Down Strap-In Status
Note 5-10
1 = Chip power-down mode
6:5
4
RESERVED
RO
RO
-
Strap_ntree_mode
NAND Tree Strap-In Status
Note 5-10
1 = NAND Tree mode
3:2
1
RESERVED
RO
RO
-
Strap_gmii_mode
GMII/MII mode Strap-In status
Note 5-10
1 = Strapped to GMII/MII mode
0
RESERVED
RO
-
Note 5-10
Set by the MODE[3:0] strapping pins. See Section 3.3, "Configuration Straps" for details.
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KSZ9131MNX
5.3.13
CLOCK INVERT AND CONTROL SIGNAL PAD SKEW REGISTER
Index (In Decimal): 2.4
Size:
16 bits
16 bits
16 bits
Bits
15:8
7:4
Description
Type
R/W
R/W
Default
0h
RESERVED
RX_DV Skew
7h
RX_DV output skew Control (~28 min to ~73 max ps/step)
3:0
TX_EN Skew
R/W
7h
TX_EN input skew Control (~28 min to ~73 max ps/step)
5.3.14
CLOCK PAD SKEW REGISTER
Index (In Decimal): 2.8
Size:
Bits
15:10
9:5
Description
Type
RO
Default
RESERVED
GTX_CLK Pad Input Skew
-
R/W
07h
GTX_CLK input Skew Control (~24 min to ~58 max ps/step)
4:0
RX_CLK_pad_oskew
RX_CLK output Skew Control (~24 min to ~58 max ps/step)
R/W
07h
5.3.15
SELF-TEST PACKET COUNT LO REGISTER
Index (In Decimal): 2.9
Size:
Bits
Description
Type
Default
15:0
Self_test_frame_cnt[15:0]
R/W
0000h
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KSZ9131MNX
5.3.16
SELF-TEST PACKET COUNT HI REGISTER
Index (In Decimal): 2.10
Size:
16 bits
Bits
Description
Type
Default
15:0
Self_test_frame_cnt[31:16]
R/W
0001h
5.3.17
SELF-TEST STATUS REGISTER
Index (In Decimal): 2.11
Size:
16 bits
Bits
15:1
0
Description
Type
RO
Default
RESERVED
-
Self_test_done
0 = Self test running
RO
0b
1 = Self test finished
5.3.18
SELF-TEST FRAME COUNT ENABLE REGISTER
Index (In Decimal): 2.12
Size:
16 bits
Bits
15:1
0
Description
Type
RO
Default
RESERVED
-
Self_test_frame_cnt_en
0 = disabled
R/W
0b
1 = enabled
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KSZ9131MNX
5.3.19
SELF-TEST PGEN ENABLE REGISTER
Index (In Decimal): 2.13
Size:
16 bits
Bits
15:1
0
Description
Type
RO
Default
RESERVED
-
Self_test_pgen_en
0 = disabled
R/W
0b
1 = enabled
5.3.20
SELF-TEST ENABLE REGISTER
Index (In Decimal): 2.14
Size:
16 bits
Bits
Description
Type
Default
15
Self_test_external_clk_sel
When this bit is high, the self-test function requires a clock to be supplied onto
R/W
0b
the GTX_CLK input pin.
When this bit is low, the self-test function does not require a clock to be sup-
plied.
14:1
0
RESERVED
RO
-
Self_test_en
0 = disabled
R/W
0b
1 = enabled
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5.3.21
WAKE-ON-LAN CONTROL REGISTER
Index (In Decimal): 2.16
Size:
16 bits
Bits
Description
Type
Default
15:14
PME Output Select
Controls definition of PME signal when assigned to INT_N.
R/W
00b
00 = PME
01 = Interrupt
10 = Interrupt ORed with PME
11 = always 0
Controls definition of PME signal when assigned to LED1.
00 = PME
01 = LED
10 = LED ORed with PME
11 = always 1
13:8
7
RESERVED
R/W
R/W
-
Wake-on-LAN Reset (Wol_reset)
Write a 1 then a 0 to reset the WoL module.
0b
6
5:2
1
Enable Magic Packet Detection Wake Event
R/W
R/W
R/W
R/W
0b
0h
0b
0b
Enables magic packet detection as a wake event
Enable Customized Frame Filter Wake Event
Enables customized frame filters as wake events
Enable Link Down Wake Event
Enables link down as a wake event
0
Enable Link Up Wake Event
Enables link up as a wake event
5.3.22
WAKE-ON-LAN-MAC-LO REGISTER
Index (In Decimal): 2.17
Size:
16 bits
Bits
Description
Type
Default
15:0
m-pkt-mac-lo
MAC-Address[15:0] of magic packet
R/W
0000h
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KSZ9131MNX
5.3.23
WAKE-ON-LAN-MAC-MI REGISTER
Index (In Decimal): 2.18
Size:
Size:
Size:
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
m-pkt-mac-mi
MAC-Address[31:16] of magic packet
R/W
0000h
5.3.24
WAKE-ON-LAN-MAC-HI REGISTER
Index (In Decimal): 2.19
Bits
Description
Type
Default
15:0
m-pkt-mac-hi
MAC-Address[47:32] of magic packet
R/W
0000h
5.3.25
CUSTOMIZED-PKT-0-CRC-LO REGISTER
Index (In Decimal): 2.20
Bits
Description
Type
Default
15:0
c-pkt-0-crc-lo
Customized frame filter 0 CRC[15:0]
R/W
0000h
5.3.26
CUSTOMIZED-PKT-0-CRC-HI REGISTER
Index (In Decimal): 2.21
Bits
Description
Type
Default
15:0
c-pkt-0-crc-hi
Customized frame filter 0 CRC[31:16]
R/W
0000h
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5.3.27
CUSTOMIZED-PKT-1-CRC-LO REGISTER
Index (In Decimal): 2.22
Size:
Size:
Size:
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
c-pkt-1-crc-lo
Customized frame filter 1 CRC[15:0]
R/W
0000h
5.3.28
CUSTOMIZED-PKT-1-CRC-HI REGISTER
Index (In Decimal): 2.23
Bits
Description
Type
Default
15:0
c-pkt-1-crc-hi
Customized frame filter 1 CRC[31:16]
R/W
0000h
5.3.29
CUSTOMIZED-PKT-2-CRC-LO REGISTER
Index (In Decimal): 2.24
Bits
Description
Type
Default
15:0
c-pkt-2-crc-lo
Customized frame filter 2 CRC[15:0]
R/W
0000h
5.3.30
CUSTOMIZED-PKT-2-CRC-HI REGISTER
Index (In Decimal): 2.25
Bits
Description
Type
Default
15:0
c-pkt-2-crc-hi
Customized frame filter 2 CRC[31:16]
R/W
0000h
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KSZ9131MNX
5.3.31
CUSTOMIZED-PKT-3-CRC-LO REGISTER
Index (In Decimal): 2.26
Size:
Size:
Size:
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
c-pkt-3-crc-lo
Customized frame filter 3 CRC[15:0]
R/W
0000h
5.3.32
CUSTOMIZED-PKT-3-CRC-HI REGISTER
Index (In Decimal): 2.27
Bits
Description
Type
Default
15:0
c-pkt-3-crc-hi
Customized frame filter 3 CRC[31:16]
R/W
0000h
5.3.33
CUSTOMIZED-PKT-0-MASK_LL REGISTER
Index (In Decimal): 2.28
Bits
Description
Type
Default
15:0
c-pkt-0-mask-ll
Customized frame filter 0 mask[15:0]
R/W
0000h
5.3.34
CUSTOMIZED-PKT-0-MASK_LH REGISTER
Index (In Decimal): 2.29
Bits
Description
Type
Default
15:0
c-pkt-0-mask-lh
Customized frame filter 0 mask[31:16]
R/W
0000h
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DS00002840C-page 89
KSZ9131MNX
5.3.35
CUSTOMIZED-PKT-0-MASK_HL REGISTER
Index (In Decimal): 2.30
Size:
Size:
Size:
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
c-pkt-0-mask-hl
Customized frame filter 0 mask[47:32]
R/W
0000h
5.3.36
CUSTOMIZED-PKT-0-MASK_HH REGISTER
Index (In Decimal): 2.31
Bits
Description
Type
Default
15:0
c-pkt-0-mask-hh
Customized frame filter 0 mask[63:48]
R/W
0000h
5.3.37
CUSTOMIZED-PKT-1-MASK_LL REGISTER
Index (In Decimal): 2.32
Bits
Description
Type
Default
15:0
c-pkt-1-mask-ll
Customized frame filter 1 mask[15:0]
R/W
0000h
5.3.38
CUSTOMIZED-PKT-1-MASK_LH REGISTER
Index (In Decimal): 2.33
Bits
Description
Type
Default
15:0
c-pkt-1-mask-lh
Customized frame filter 1 mask[31:16]
R/W
0000h
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KSZ9131MNX
5.3.39
CUSTOMIZED-PKT-1-MASK_HL REGISTER
Index (In Decimal): 2.34
Size:
Size:
Size:
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
c-pkt-1-mask-hl
Customized frame filter 1 mask[47:32]
R/W
0000h
5.3.40
CUSTOMIZED-PKT-1-MASK_HH REGISTER
Index (In Decimal): 2.35
Bits
Description
Type
Default
15:0
c-pkt-1-mask-hh
Customized frame filter 1 mask[63:48]
R/W
0000h
5.3.41
CUSTOMIZED-PKT-2-MASK_LL REGISTER
Index (In Decimal): 2.36
Bits
Description
Type
Default
15:0
c-pkt-2-mask-ll
Customized frame filter 2 mask[15:0]
R/W
0000h
5.3.42
CUSTOMIZED-PKT-2-MASK_LH REGISTER
Index (In Decimal): 2.37
Bits
Description
Type
Default
15:0
c-pkt-2-mask-lh
Customized frame filter 2 mask[31:16]
R/W
0000h
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DS00002840C-page 91
KSZ9131MNX
5.3.43
CUSTOMIZED-PKT-2-MASK_HL REGISTER
Index (In Decimal): 2.38
Size:
Size:
Size:
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
c-pkt-2-mask-hl
Customized frame filter 2 mask[47:32]
R/W
0000h
5.3.44
CUSTOMIZED-PKT-2-MASK_HH REGISTER
Index (In Decimal): 2.39
Bits
Description
Type
Default
15:0
c-pkt-2-mask-hh
Customized frame filter 2 mask[63:48]
R/W
0000h
5.3.45
CUSTOMIZED-PKT-3-MASK_LL REGISTER
Index (In Decimal): 2.40
Bits
Description
Type
Default
15:0
c-pkt-3-mask-ll
Customized frame filter 3 mask[15:0]
R/W
0000h
5.3.46
CUSTOMIZED-PKT-3-MASK_LH REGISTER
Index (In Decimal): 2.41
Bits
Description
Type
Default
15:0
c-pkt-3-mask-lh
Customized frame filter 3 mask[31:16]
R/W
0000h
DS00002840C-page 92
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KSZ9131MNX
5.3.47
CUSTOMIZED-PKT-3-MASK_HL REGISTER
Index (In Decimal): 2.42
Size:
16 bits
Bits
Description
Type
Default
15:0
c-pkt-3-mask-hl
Customized frame filter 3 mask[47:32]
R/W
0000h
5.3.48
CUSTOMIZED-PKT-3-MASK_HH REGISTER
Index (In Decimal): 2.43
Size:
16 bits
Bits
Description
Type
Default
15:0
c-pkt-3-mask-hh
Customized frame filter 3 mask[63:48]
R/W
0000h
5.3.49
WAKE-ON-LAN CONTROL STATUS REGISTER
Index (In Decimal): 2.44
Size:
16 bits
Bits
Description
Type
Default
15:0
Wol_ctrl_status
Wake-on-LAN Control module status
RO
0000h
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DS00002840C-page 93
KSZ9131MNX
5.3.50
WAKE-ON-LAN CUSTOM PACKET RECEIVE STATUS REGISTER
Index (In Decimal): 2.45
Size:
16 bits
Bits
Description
Type
Default
15
cpkt_pmen
RO
0b
custom packet 0 enabled and custom packet 0 found
14:12
11
mismatch code
RO
RO
RO
000b
0b
good_pkt_crc
10:7
crc_match
crc matched
0000b
bit 10 = custom packet 3
bit 9 = custom packet 2
bit 8 = custom packet 1
bit 7 = custom packet 0
6:3
cpkt_found
RO
RO
0000b
000b
custom packet found
bit 6 = custom packet 3
bit 5 = custom packet 2
bit 4 = custom packet 1
bit 3 = custom packet 0
2:0
cpkt_state
custom packet detection state
5.3.51
WAKE-ON-LAN MAGIC PACKET RECEIVE STATUS REGISTER
Index (In Decimal): 2.46
Size:
16 bits
Bits
Description
Type
Default
15
mpkt_pmen
magic packet enabled and magic packet found
RO
0b
14:12
11:9
8:5
4
byte count
RO
RO
RO
RO
RO
000b
000b
0h
mismatch code
macda_match_count
good_pkt_crc
0b
3
mpkt_found
magic packet found
0b
2:0
mpkt_state
magic packet detection state
RO
000b
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KSZ9131MNX
5.3.52
WAKE-ON-LAN DATA MODULE STATUS REGISTER
Index (In Decimal): 2.47
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
Wol_data_status
Wake-on-LAN Data module status
RO
0000h
5.3.53
CUSTOMIZED PKT-0 RECEIVED CRC-L REGISTER
Index (In Decimal): 2.48
Size:
Bits
Description
Type
Default
15:0
Wol_crc_rcv_0 [15:0]
Wake-on-LAN CRC [15:0] calculated on Customized frame filter 0
RO
0000h
5.3.54
CUSTOMIZED PKT-0 RECEIVED CRC-H REGISTER
Index (In Decimal): 2.49
Size:
Bits
Description
Type
Default
15:0
Wol_crc_rcv_0 [31:16]
Wake-on-LAN CRC [31:16] calculated on Customized frame filter 0
RO
0000h
5.3.55
CUSTOMIZED PKT-1 RECEIVED CRC-L REGISTER
Index (In Decimal): 2.50
Size:
Bits
Description
Type
Default
15:0
Wol_crc_rcv_1 [15:0]
Wake-on-LAN CRC [15:0] calculated on Customized frame filter 1
RO
0000h
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DS00002840C-page 95
KSZ9131MNX
5.3.56
CUSTOMIZED PKT-1 RECEIVED CRC-H REGISTER
Index (In Decimal): 2.51
Size:
16 bits
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
Wol_crc_rcv_1 [31:16]
Wake-on-LAN CRC [31:16] calculated on Customized frame filter 1
RO
0000h
5.3.57
CUSTOMIZED PKT-2 RECEIVED CRC-L REGISTER
Index (In Decimal): 2.52
Size:
Bits
Description
Type
Default
15:0
Wol_crc_rcv_2 [15:0]
Wake-on-LAN CRC [15:0] calculated on Customized frame filter 2
RO
0000h
5.3.58
CUSTOMIZED PKT-2 RECEIVED CRC-H REGISTER
Index (In Decimal): 2.53
Size:
Bits
Description
Type
Default
15:0
Wol_crc_rcv_2 [31:16]
Wake-on-LAN CRC [31:16] calculated on Customized frame filter 2
RO
0000h
5.3.59
CUSTOMIZED PKT-3 RECEIVED CRC-L REGISTER
Index (In Decimal): 2.54
Size:
Bits
Description
Type
Default
15:0
Wol_crc_rcv_3 [15:0]
Wake-on-LAN CRC [15:0] calculated on Customized frame filter 3
RO
0000h
DS00002840C-page 96
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KSZ9131MNX
5.3.60
CUSTOMIZED PKT-3 RECEIVED CRC-H REGISTER
Index (In Decimal): 2.55
Size:
16 bits
Bits
Description
Type
Default
15:0
Wol_crc_rcv_3 [31:16]
Wake-on-LAN CRC [31:16] calculated on Customized frame filter 3
RO
0000h
5.3.61
SELF-TEST CORRECT COUNT LO REGISTER
Index (In Decimal): 2.60
Size:
16 bits
Following a self-test, this register along with Self-Test Correct Count HI Register indicate the count of frames with a cor-
rect FCS.
Bits
Description
Type
Default
15:0
Self_test_correct_cnt[15:0]
RO
-
5.3.62
SELF-TEST CORRECT COUNT HI REGISTER
Index (In Decimal): 2.61
Size:
16 bits
Following a self-test, this register along with Self-Test Correct Count LO Register indicate the count of frames with a
correct FCS.
Bits
Description
Type
Default
15:0
Self_test_correct_cnt[31:16]
RO
-
5.3.63
SELF-TEST ERROR COUNT LO REGISTER
Index (In Decimal): 2.62
Size:
16 bits
Following a self-test, this register along with Self-Test Error Count HI Register indicate the count of frames with an incor-
rect FCS.
Bits
Description
Type
Default
15:0
Self_test_error_cnt[15:0]
RO
-
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DS00002840C-page 97
KSZ9131MNX
5.3.64
SELF-TEST ERROR COUNT HI REGISTER
Index (In Decimal): 2.63
Size:
16 bits
Following a self-test, this register along with Self-Test Error Count LO Register indicate the count of frames with an incor-
rect FCS.
Bits
Description
Type
Default
15:0
Self_test_error_cnt[31:16]
RO
-
5.3.65
SELF-TEST BAD SFD COUNT LO REGISTER
Index (In Decimal): 2.64
Size:
16 bits
Following a self-test, this register along with Self-Test Bad SFD Count HI Register indicate the count of frames with a
bad SFD.
Bits
Description
Type
Default
15:0
Self_test_bad_sfd_cnt[15:0]
RO
-
5.3.66
SELF-TEST BAD SFD COUNT HI REGISTER
Index (In Decimal): 2.65
Size:
16 bits
Following a self-test, this register along with Self-Test Bad SFD Count LO Register indicate the count of frames with a
bad SFD.
Bits
Description
Type
Default
15:0
Self_test_bad_sfd_cnt[31:16]
RO
-
DS00002840C-page 98
2018-2021 Microchip Technology Inc.
KSZ9131MNX
5.3.67
PCS CONTROL 1 REGISTER
Index (In Decimal): 3.0
Size:
16 bits
Bits
Description
Type
Default
15
RESET
1=PCS reset
R/W
0b
0=Normal Operation
This bit is not used
14
13
Loop Back
R/W
R/W
0b
0b
1 = enable loop-back mode
0 = Normal Operation
This bit is not used
Speed Selection
(bit13 / bit6)
11 = bit 5:2 select speed
0x = unspecified
x0 = unspecified
This bit is not used
12
11
10
EEE100_idle_sel
R/W
R/W
R/W
0b
0b
0b
0 = 9031
1 = 8050
Low power
1 = low-power-mode
0 = normal operation
Clock-stop enable
1 = the PHY may stop the clock during LPI
0 = clock not stoppable
9:7
6
TX FIFO threshold
R/W
R/W
111b
0b
Speed Selection
(bit13 / bit6)
11 = bit 5:2 select speed
0x = unspecified
x0 = unspecified
This bit is not used
2018-2021 Microchip Technology Inc.
DS00002840C-page 99
KSZ9131MNX
Bits
Description
Type
Default
5:2
Speed Selection
(bits [5:2])
R/W
0000b
1 x x x = Reserved
0 1 1 x = Reserved
0 1 0 1 = Reserved
0 1 0 0 = 100Gb/s
0 0 1 1 = 40Gb/s
0 0 1 0 = 10/1Gb/s
0 0 0 1 = 10PASS-TS/2BASE-TL
0 0 0 0 = 10Gb/s
These bits are not used
1
0
RESERVED
R/W
R/W
-
Dbg_pcs100_sel
1 = select eee100 RX signals
0b
0 = original
5.3.68
PCS STATUS 1 REGISTER
Index (In Decimal): 3.1
Size:
16 bits
Bits
15:12
11
Description
Type
RO
Default
RESERVED
-
TX LPI received
1 = TX PCS has received LPI
RO/LH
0b
0 = LPI not received
10
9
RX LPI received
RO/LH
RO
0b
0b
0b
0b
1b
-
1 = RX PCS has received LPI
0 = LPI not received
TX LPI indication
1 = TX PCS is currently receiving LPI
0 = PCS is not currently receiving LPI
8
RX LPI indication
1 = RX PCS is currently receiving LPI
0 = PCS is not currently receiving LPI
RO
7
Fault
RO
1 = Fault condition detected
0 = No fault condition detected
6
Clock stop capable
1 = The MAC may stop the clock during LPI
0 = Clock not stoppable
RO
5:3
RESERVED
RO
DS00002840C-page 100
2018-2021 Microchip Technology Inc.
KSZ9131MNX
Bits
Description
Type
Default
2
PCS receive link status
1 = PCS receive link up
RO
0b
0 = PCS receive link down
1
0
Low-power ability
RO
RO
Note 5-11
-
1 = PCS supports low-power mode
0 = PCS does not support low-power mode
RESERVED
Note 5-11
This bit is a 1 if either the 1000BASE-T EEE or 100BASE-TX EEE bit in the EEE Advertisement
Register is set. Otherwise it is a 0.
5.3.69
EEE QUIET TIMER REGISTER
Index (In Decimal): 3.8
Size:
Size:
Size:
16 bits
16 bits
16 bits
Bits
Description
Type
Default
15:0
Quiet-Timer
1G-EEE quieter Timer Max Value
R/W
006Eh
5.3.70
EEE UPDATE TIMER REGISTER
Index (In Decimal): 3.9
Bits
Description
Type
Default
15:0
Update-Timer
1G-EEE Update Timer Max Value
R/W
005Fh
5.3.71
EEE LINK-FAIL TIMER REGISTER
Index (In Decimal): 3.10
Bits
15:8
7:0
Description
Type
R/W
R/W
Default
RESERVED
-
Link-Fail-Timer
5Ah
1G-EEE Link-Fail Timer Max Value
2018-2021 Microchip Technology Inc.
DS00002840C-page 101
KSZ9131MNX
5.3.72
EEE POST-UPDATE TIMER REGISTER
Index (In Decimal): 3.11
Size:
Size:
Size:
16 bits
16 bits
16 bits
Bits
15:8
7:0
Description
Type
R/W
R/W
Default
RESERVED
-
Post-Update-Timer
1G-EEE Post-Update Timer Max Value
50h
5.3.73
EEE WAITWQ TIMER REGISTER
Index (In Decimal): 3.12
Bits
15:8
7:0
Description
Type
R/W
R/W
Default
RESERVED
-
WaitWQ-Timer
1G-EEE WaitWQ Timer Max Value
5Bh
5.3.74
EEE WAKE TIMER REGISTER
Index (In Decimal): 3.13
Bits
15:8
7:0
Description
Type
R/W
R/W
Default
RESERVED
-
Wake-Timer
1G-EEE Wake Timer Max Value
89h
DS00002840C-page 102
2018-2021 Microchip Technology Inc.
KSZ9131MNX
5.3.75
EEE WAKETX TIMER REGISTER
Index (In Decimal): 3.14
Size:
16 bits
16 bits
16 bits
Bits
15:8
7:0
Description
Type
R/W
R/W
Default
RESERVED
-
WakeTX-Timer
1G-EEE WakeTX Timer Max Value
21h
5.3.76
EEE WAKEMZ TIMER REGISTER
Index (In Decimal): 3.15
Size:
Bits
15:8
7:0
Description
Type
R/W
R/W
Default
RESERVED
-
WakeMz-Timer
1G-EEE WakeMz Timer Max Value
6Eh
5.3.77
EEE CONTROL AND CAPABILITY REGISTER
Index (In Decimal): 3.20
Size:
Bits
Description
Type
Default
15:14
13
RESERVED
100GBASE-R deep sleep
1 = EEE deep sleep is supported for 100GBASE-R
0 = EEE deep sleep is not supported for 100GBASE-R
RO
RO
-
0b
Note:
The device does not support this mode.
12
100GBASE-R fast wake
1 = EEE fast wake is supported for 100GBASE-R
RO
0b
0 = EEE fast wake is not supported for 100GBASE-R
Note:
The device does not support this mode.
11:10
9
RESERVED
RO
RO
-
40GBASE-R deep sleep
1 = EEE deep sleep is supported for 40GBASE-R
0b
0 = EEE deep sleep is not supported for 40GBASE-R
Note:
The device does not support this mode.
2018-2021 Microchip Technology Inc.
DS00002840C-page 103
KSZ9131MNX
Bits
Description
Type
Default
8
40GBASE-R fast wake
1 = EEE fast wake is supported for 40GBASE-R
0 = EEE fast wake is not supported for 40GBASE-R
RO
0b
Note:
The device does not support this mode.
7
6
RESERVED
RO
RO
-
10GBASE-KR EEE
0 = EEE is not supported for 10GBASE-KR.
0b
1 = EEE is supported for 10GBASE-KR.
Note:
The device does not support this mode.
5
4
3
10GBASE-KX4 EEE
RO
RO
RO
0b
0b
0b
0 = EEE is not supported for 10GBASE-KX4.
1 = EEE is supported for 10GBASE-KX4.
Note:
The device does not support this mode.
10GBASE-KX EEE
0 = EEE is not supported for 10GBASE-KX.
1 = EEE is supported for 10GBASE-KX.
Note:
The device does not support this mode.
10GBASE-T EEE
0 = EEE is not supported for 10GBASE-T.
1 = EEE is supported for 10GBASE-T.
Note:
The device does not support this mode.
2
1
0
1000BASE-T EEE
RO
RO
RO
0b
0b
-
0 = EEE is not supported for 1000BASE-T.
1 = EEE is supported for 1000BASE-T.
100BASE-TX EEE
0 = EEE is not supported for 100BASE-TX.
1 = EEE is supported for 100BASE-TX.
RESERVED
5.3.78
EEE WAKE ERROR COUNTER REGISTER
Index (In Decimal): 3.22
Size:
16 bits
Bits
Description
Type
Default
15:0
EEE Wake Error Counter
This counter is cleared to zeros on read and is held to all ones on overflow.
RC
0000h
DS00002840C-page 104
2018-2021 Microchip Technology Inc.
KSZ9131MNX
5.3.79
EEE 100 TIMER-0 REGISTER
Index (In Decimal): 3.24
Size:
16 bits
Bits
Description
Type
Default
15:8
TX_SLEEP_TIMER_ADD
tx_sleep_time = (5250 + TX_SLEEP_TIMER_ADD * 32) * 40ns
R/W
00h
7:1
0
TX_WAKE_TIMER_ADD
R/W
R/W
00h
0b
tx_wake_time = (512 + TX_WAKE_TIMER_ADD * 32) * 40ns
RESERVED
5.3.80
EEE 100 TIMER-1 REGISTER
Index (In Decimal): 3.25
Size:
16 bits
Bits
Description
Type
Default
15:8
RX_SLEEP_TIMER_ADD
rx_sleep_time = (6250 + RX_SLEEP_TIMER_ADD * 32) * 40ns
R/W
00h
7:1
0
TX_QUIET_TIMER_ADD
R/W
R/W
00h
0b
tx_quiet_time = (525000 + TX_QUIET_TIMER_ADD * 8192) * 40ns
eee_100_test
1 = force TX LPI
5.3.81
EEE 100 TIMER-2 REGISTER
Index (In Decimal): 3.26
Size:
16 bits
Bits
Description
RX_WAIT_IDLE_EXIT_TIMER_ADD
rx_wait_idle_exit_time = (16 + RX_WAIT_IDLE_EXIT_TIMER_ADD * 2) *
40ns
Type
Default
15:12
R/W
0h
11:8
7:0
RX_IDLE_WAIT_TIMER_ADD
R/W
R/W
0h
rx_idle_wait_time = (20 + RX_IDLE_WAIT_TIMER_ADD * 2) * 40ns
RX_QUIET_TIMER_ADD
rx_quiet_time = (625000 + RX_QUIET_TIMER_ADD * 4096) * 40ns
00h
2018-2021 Microchip Technology Inc.
DS00002840C-page 105
KSZ9131MNX
5.3.82
EEE 100 TIMER-3 REGISTER
Index (In Decimal): 3.27
Size:
16 bits
Bits
Description
Type
Default
15:8
RX_WAKE_TIMER_ADD
rx_wake_time = (512 + RX_WAKE_TIMER_ADD * 4) * 40ns
R/W
00h
7:0
RX_LINK_FAIL_TIMER_ADD
rx_link_fail_time = (2500 + RX_LINK_FAIL_TIMER_ADD * 16) * 40ns
R/W
00h
5.3.83
EEE ADVERTISEMENT REGISTER
Index (In Decimal): 7.60
Size:
16 bits
Bits
Description
Type
Default
15:14
13
RESERVED
100GBASE-CR4 EEE
0 = Do not advertise EEE capability for 100GBASE-CR4 deep sleep
1 = Advertise EEE capability for 100GBASE-CR4 deep sleep
R/W
R/W
-
0b
Note:
The device does not support this mode.
This bit is not used.
12
11
10
100GBASE-KR4 EEE
R/W
R/W
R/W
0b
0b
0b
0 = Do not advertise EEE capability for 100GBASE-KR4 deep sleep
1 = Advertise EEE capability for 100GBASE-KR4 deep sleep
Note:
The device does not support this mode.
This bit is not used.
100GBASE-KP4 EEE
0 = Do not advertise EEE capability for 100GBASE-KP4 deep sleep
1 = Advertise EEE capability for 100GBASE-KP4 deep sleep
Note:
The device does not support this mode.
This bit is not used.
100GBASE-CR10 EEE
0 = Do not advertise EEE capability for 100GBASE-CR10 deep sleep
1 = Advertise EEE capability for 100GBASE-CR10 deep sleep
Note:
The device does not support this mode.
9
8
RESERVED
R/W
R/W
-
40GBASE-CR4 EEE
0 = Do not advertise EEE capability for 40GBASE-CR4 deep sleep
0b
1 = Advertise EEE capability for 40GBASE-CR4 deep sleep
Note:
The device does not support this mode.
DS00002840C-page 106
2018-2021 Microchip Technology Inc.
KSZ9131MNX
Bits
Description
Type
Default
7
40GBASE-KR4 EEE
0 = Do not advertise EEE capability for 40GBASE-KR4 deep sleep
1 = Advertise EEE capability for 40GBASE-KR4 deep sleep
R/W
0b
Note:
The device does not support this mode.
6
5
4
3
10GBASE-KR EEE
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0 = Do not advertise EEE capability for 10GBASE-KR
1 = Advertise EEE capability for 10GBASE-KR
Note:
The device does not support this mode.
10GBASE-KX4 EEE
0 = Do not advertise EEE capability for 10GBASE-KX4
1 = Advertise EEE capability for 10GBASE-KX4
Note:
The device does not support this mode.
10GBASE-KX EEE
0 = Do not advertise EEE capability for 10GBASE-KX
1 = Advertise EEE capability for 10GBASE-KX
Note:
The device does not support this mode.
10GBASE-T EEE
0 = Do not advertise EEE capability for 10GBASE-T
1 = Advertise EEE capability for 10GBASE-T
Note:
The device does not support this mode.
2
1
0
1000BASE-T EEE
R/W
R/W
R/W
1b
1b
-
0 = Do not advertise EEE capability for 1000BASE-T
1 = Advertise EEE capability for 1000BASE-T
100BASE-TX EEE
0 = Do not advertise EEE capability for 100BASE-TX.
1 = Advertise EEE capability for 100BASE-TX.
RESERVED
2018-2021 Microchip Technology Inc.
DS00002840C-page 107
KSZ9131MNX
5.3.84
EEE LINK PARTNER ABILITY REGISTER
Index (In Decimal): 7.61
Size:
16 bits
Bits
Description
Type
Default
15:11
10
RESERVED
100GBASE-CR10 EEE
0 = Link partner does not advertise EEE deep sleep capability for
100GBASE-CR10.
R/W
RO
-
0b
1 = Link partner advertises EEE deep sleep capability for 100GBASE-CR10.
Note: This device does not support this mode.
9
8
RESERVED
RO
RO
0b
0b
40GBASE-CR4 EEE
0 = Link partner does not advertise EEE deep sleep capability for 40GBASE-
CR4.
1 = Link partner advertises EEE deep sleep capability for 40GBASE-CR4.
Note:
This device does not support this mode.
7
40GBASE-KR4 EEE
0 = Link partner does not advertise EEE deep sleep capability for 40GBASE-
RO
0b
KR4.
1 = Link partner advertises EEE deep sleep capability for 40GBASE-KR4.
Note:
This device does not support this mode.
6
5
4
3
10GBASE-KR EEE
RO
RO
RO
RO
0b
0b
0b
0b
0 = Link partner does not advertise EEE capability for 10GBASE-KR.
1 = Link partner advertises EEE capability for 10GBASE-KR.
Note:
This device does not support this mode.
10GBASE-KX4 EEE
0 = Link partner does not advertise EEE capability for 10GBASE-KX4.
1 = Link partner advertises EEE capability for 10GBASE-KX4.
Note:
This device does not support this mode.
10GBASE-KX EEE
0 = Link partner does not advertise EEE capability for 10GBASE-KX.
1 = Link partner advertises EEE capability for 10GBASE-KX.
Note:
This device does not support this mode.
10GBASE-T EEE
0 = Link partner does not advertise EEE capability for 10GBASE-T.
1 = Link partner advertises EEE capability for 10GBASE-T.
Note:
This device does not support this mode.
2
1
0
1000BASE-T EEE
RO
RO
RO
0b
0b
-
0 = Link partner does not advertise EEE capability for 1000BASE-T.
1 = Link partner advertises EEE capability for 1000BASE-T.
100BASE-TX EEE
0 = Link partner does not advertise EEE capability for 100BASE-TX.
1 = Link partner advertises EEE capability for 100BASE-TX.
RESERVED
DS00002840C-page 108
2018-2021 Microchip Technology Inc.
KSZ9131MNX
5.3.85
EEE LINK PARTNER ABILITY OVERRIDE REGISTER
Index (In Decimal): 7.62
Size:
16 bits
Bits
Description
Type
Default
15
LP AN Override
0 = Use Link partner AN results
R/W
0b
1 = Use bits 10:0 as Link partner results
14:11
10
RESERVED
R/W
R/W
-
100GBASE-CR10 EEE
0 = Link partner does not advertise EEE deep sleep capability for
100GBASE-CR10.
0b
1 = Link partner advertises EEE deep sleep capability for 100GBASE-CR10.
Note: This device does not support this mode.
9
8
RESERVED
R/W
R/W
-
40GBASE-CR4 EEE
0 = Link partner does not advertise EEE deep sleep capability for 40GBASE-
0b
CR4.
1 = Link partner advertises EEE deep sleep capability for 40GBASE-CR4.
Note:
This device does not support this mode.
7
40GBASE-KR4 EEE
0 = Link partner does not advertise EEE deep sleep capability for 40GBASE-
R/W
0b
KR4.
1 = Link partner advertises EEE deep sleep capability for 40GBASE-KR4.
Note:
This device does not support this mode.
6
5
4
3
2
10GBASE-KR EEE
R/W
R/W
R/W
R/W
R/W
0b
0b
0b
0b
0b
0 = Link partner does not advertise EEE capability for 10GBASE-KR.
1 = Link partner advertises EEE capability for 10GBASE-KR.
Note:
This device does not support this mode.
10GBASE-KX4 EEE
0 = Link partner does not advertise EEE capability for 10GBASE-KX4.
1 = Link partner advertises EEE capability for 10GBASE-KX4.
Note:
This device does not support this mode.
10GBASE-KX EEE
0 = Link partner does not advertise EEE capability for 10GBASE-KX.
1 = Link partner advertises EEE capability for 10GBASE-KX.
Note:
This device does not support this mode.
10GBASE-T EEE
0 = Link partner does not advertise EEE capability for 10GBASE-T.
1 = Link partner advertises EEE capability for 10GBASE-T.
Note:
This device does not support this mode.
1000BASE-T EEE
0 = Link partner does not advertise EEE capability for 1000BASE-T.
1 = Link partner advertises EEE capability for 1000BASE-T.
2018-2021 Microchip Technology Inc.
DS00002840C-page 109
KSZ9131MNX
Bits
Description
Type
Default
1
0
100BASE-TX EEE
R/W
0b
0 = Link partner does not advertise EEE capability for 100BASE-TX.
1 = Link partner advertises EEE capability for 100BASE-TX.
RESERVED
R/W
-
5.3.86
EEE MESSAGE CODE REGISTER
Index (In Decimal): 7.63
Size:
16 bits
Bits
Description
Type
Default
15:11
10:0
RESERVED
EEE_message_code
R/W
R/W
-
00Ah
Programmable EEE specific message code for AN
5.3.87
XTAL CONTROL REGISTER
Index (In Decimal): 28.1
Size:
16 bits
Bits
Description
Type
Default
15:14
13
RESERVED
R/W
R/W
-
XTAL Disable
Crystal oscillator disable
0b
0 = XTAL enabled
1 = XTAL disabled
12:0
RESERVED
R/W
-
DS00002840C-page 110
2018-2021 Microchip Technology Inc.
KSZ9131MNX
5.3.88
AFED CONTROL REGISTER
Index (In Decimal): 28.9
Size:
16 bits
Bits
Description
Type
Default
15:10
9
RESERVED
RO
-
p_cat3
R/W
0b
0 = cat5 parameter for 10 Base-T TX
1 = cat3 parameter for 10 Base-T TX
8:0
RESERVED
RO
-
5.3.89
LDO CONTROL REGISTER
Index (In Decimal): 28.14
Size:
16 bits
Bits
Description
Type
Default
15
LDO enable
turn off VDD regulator by software
R/W
0b
1 = off
0 = on
14:0
RESERVED
R/W
-
5.3.90
EDPD CONTROL REGISTER
Index (In Decimal): 28.36
Size:
16 bits
Bits
Description
Type
Default
15:6
5:4
RESERVED
RO
-
p_edpd_mask_timer[1:0]
00 = EDPD mask for 2.6us
R/W
00b
01 = 3.2us
10 = 4.0us
11 = 5.0us
3:2
p_edpd_timer[1:0]
00 = EDPD pulse separation for 1s
01 = 1.3s
R/W
00b
10 = 1.6s
11 = 1.9s
2018-2021 Microchip Technology Inc.
DS00002840C-page 111
KSZ9131MNX
Bits
Description
Type
Default
1
0
p_EDPD_random_dis
R/W
0b
1 = use edpd_timer value as EDPD pulse separation selection
0 = use random seed value as EDPD pulse separation selection
EDPD Mode Enable
0 = EDPD mode disabled
R/W
0b
1 = EDPD mode enabled
5.3.91
EMITX CONTROL REGISTER
Index (In Decimal): 28.37
Size:
16 bits
Type
Note 5-12
Default
Note 5-12
Bits
Description
15:2
1:0
RESERVED
p_scale
RO
-
RO / R/W
00b / 01b
Note 5-12
The type and default value depends on the Quiet-WIRE Enable bit in MMD31 Register 19. The values
are listed as Quiet-WIRE Enable = 0 / Quiet-WIRE Enable = 1.
5.3.92
EMITX COEFFICIENT REGISTERS
Index (In Decimal): 28.38-52
Size:
16 bits
Type
Note 5-13
Default
Note 5-13
Register
Bits
Description
15
14:8
7
RESERVED
p_coeff1
RO
RO / R/W
RO
-
31d / 14d
38
RESERVED
p_coeff0
-
6:0
15
RO / R/W
RO
15d / 3d
RESERVED
p_coeff3
-
14:8
7
RO / R/W
RO
31d / 48d
-
39
RESERVED
p_coeff2
6:0
RO / R/W
31d / 32d
DS00002840C-page 112
2018-2021 Microchip Technology Inc.
KSZ9131MNX
Type
Note 5-13
Default
Note 5-13
Register
Bits
Description
15
14:8
7
RESERVED
p_coeff5
RO
RO / R/W
RO
-
0d / 46d
40
RESERVED
p_coeff4
-
6:0
15
RO / R/W
RO
16d / 54d
RESERVED
p_coeff7
-
14:8
7
RO / R/W
RO
0d / 11d
41
42
RESERVED
p_coeff6
-
6:0
15
RO / R/W
RO
0d / 28d
-
RESERVED
p_coeff9
14:8
RO / R/W
0d /
126d (-2d)
7
RESERVED
p_coeff8
RO
-
6:0
15
RO / R/W
RO
0d / 1d
-
RESERVED
p_coeff11
14:8
RO / R/W
0d /
127d (-1d)
43
7
RESERVED
p_coeff10
RO
-
6:0
RO / R/W
0d /
126d (-2d)
15
14:8
7
RESERVED
p_coeff13
RESERVED
p_coeff12
RESERVED
p_coeff15
RESERVED
p_coeff14
RESERVED
p_coeff17
RESERVED
p_coeff16
RO
R/W / R/W
RO
-
0d / 0d
44
45
46
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
-
6:0
R/W / R/W
0d / 0d
2018-2021 Microchip Technology Inc.
DS00002840C-page 113
KSZ9131MNX
Type
Note 5-13
Default
Note 5-13
Register
Bits
Description
15
14:8
7
RESERVED
p_coeff19
RESERVED
p_coeff18
RESERVED
p_coeff21
RESERVED
p_coeff20
RESERVED
p_coeff23
RESERVED
p_coeff22
RESERVED
p_coeff25
RESERVED
p_coeff24
RESERVED
p_coeff27
RESERVED
p_coeff26
RESERVED
p_coeff29
RESERVED
p_coeff28
RO
R/W / R/W
RO
-
0d / 0d
47
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
48
49
50
51
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
-
6:0
15
R/W / R/W
RO
0d / 0d
-
14:8
7
R/W / R/W
RO
0d / 0d
-
52
6:0
R/W / R/W
0d / 0d
Note 5-13
The type and default value depends on the Quiet-WIRE Enable bit in MMD31 Register 19. The values
are listed as Quiet-WIRE Enable = 0 / Quiet-WIRE Enable = 1.
DS00002840C-page 114
2018-2021 Microchip Technology Inc.
KSZ9131MNX
5.3.93
MMD31 REGISTER 19
Index (In Decimal): 31.19
Size:
16 bits
Bits
15:11
10
Description
Type
RO
Default
RESERVED
-
Quiet-WIRE Enable
1 = Enable Quiet-WIRE®
R/W
0b
0 = Disable Quiet-WIRE®
9:0
RESERVED
RO
-
2018-2021 Microchip Technology Inc.
DS00002840C-page 115
KSZ9131MNX
6.0
6.1
OPERATIONAL CHARACTERISTICS
Absolute Maximum Ratings*
Supply Voltage (VIN)
(DVDDL, AVDDL, AVDDL_PLL) ................................................................................................................ –0.5V to +1.8V
(AVDDH)....................................................................................................................................................–0.5V to +5.0V
(DVDDH)................................................................................................................................................... –0.5V to +5.0V
Input Voltage (all inputs)............................................................................................................................ –0.5V to +5.0V
Output Voltage (all outputs).......................................................................................................................–0.5V to +5.0V
Lead Temperature (soldering, 10s) .......................................................................................................................+260°C
Storage Temperature (TS)......................................................................................................................–55°C to +150°C
HBM ESD Performance ..........................................................................................................................................+/-5kV
*Exceeding the absolute maximum rating may damage the device. Stresses greater than the absolute maximum rating
may cause permanent damage to the device. Operation of the device at these or any other conditions above those spec-
ified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect
reliability.
6.2
Operating Ratings**
Supply Voltage
(DVDDL, AVDDL, AVDDL_PLL) ........................................................................................................+1.140V to +1.320V
(AVDDH @ 3.3V) ..............................................................................................................................+3.135V to +3.630V
(AVDDH @ 2.5V)............................................................................................................................... +2.375V to +2.750V
(DVDDH @ 3.3V) .............................................................................................................................+3.135V to +3.630V
(DVDDH @ 2.5V)..............................................................................................................................+2.375V to +2.750V
(DVDDH @ 1.8V)..............................................................................................................................+1.710V to +1.980V
Input voltage (all inputs) ........................................................................................................................-0.3 V to +3.63 V
Output voltage (all outputs) ...................................................................................................................-0.3 V to +3.63 V
Ambient Temperature
(TA Commercial: KSZ9131MNXC)...............................................................................................................0°C to +70°C
(TA Industrial: KSZ9131MNXI) .................................................................................................................–40°C to +85°C
Maximum Junction Temperature (TJ max.) ...........................................................................................................+125°C
**The device is not guaranteed to function outside its operating ratings.
Note:
Do not drive input signals without power supplied to the device.
DS00002840C-page 116
2018-2021 Microchip Technology Inc.
KSZ9131MNX
6.3
Package Thermal Specifications
Thermal parameters are measured or estimated for devices with the ground soldered to thermal vias in a multilayer
2S2P PCB per JESD51. Thermal resistance is measured from the die to the ambient air. The values provided are based
on the package body, die size, maximum power consumption.
TABLE 6-1:
PACKAGE THERMAL PARAMETERS
Parameter
Symbol
Value
Units
Notes
26
22
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
mW
0 Meters/second
1 Meters/second
2.5 Meters/second
0 Meters/second
0 Meters/second
-
Junction-to-Ambient
JA
20
Junction-to-Top-of-Package
Junction-to-Board
JT
JB
JC
JB
0.2
13
Junction-to-Case
2.5
14
Junction-to-Board
-
Maximum Power Dissipation
PMAX
756
1000BASE-T Traffic, 3.3V I/O
Use the following formulas to calculate the junction temperature:
TJ = P x JA + TA
TJ = P x JT + TT
TJ = P x JC + TC
TABLE 6-2:
Symbol
PACKAGE THERMALS LEGEND
Description
TJ
P
Junction temperature
Power dissipated
JA
JC
JT
TA
Junction-to-ambient-temperature
Junction-to-top-of-package
Junction-to-bottom-of-case
Ambient temperature
TC
Temperature of the bottom of the case
Temperature of the top of the case
TT
2018-2021 Microchip Technology Inc.
DS00002840C-page 117
KSZ9131MNX
6.4
Power Consumption
This section details the device power measurements taken over various operating conditions. Unless otherwise noted,
all measurements were taken with power supplies at nominal values. Refer to Section 4.18, Power Management for a
description of the power down modes.
TABLE 6-3:
POWER CONSUMPTION
Mode
Typical Power (mW)
Typical Power (mW)
DVDDH=3.3V, AVDDH=3.3V DVDDH=2.5V, AVDDH=2.5V
1000BASE-T Traffic (GMII)
100BASE-TX Traffic (GMII)
10BASE-T Traffic (GMII)
707.1
268.8
163.5
147.0
3.4
544.0
194.0
119.1
101.6
3.4
10BASE-Te Traffic (GMII)
Chip Power-Down (CPD)
Energy-Detect Power-Down (EDPD)
EEE 1000BASE-T Idle
55.2
32.4
236.7
108.6
175.8
61.2
140.2
78.5
EEE 100BASE-TX Idle
Normal Operation (No Link)
RESET
128.6
43.4
Software Power-Down (SPD)
Max Power (85°C w/AVDDH/DVDDH +10°)
Max Power (105°C w/AVDDH/DVDDH +10°)
19.8
10.0
928.3
938.9
681.9
692.5
TABLE 6-4:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (3.3V), DIGITAL I/O (3.3V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
3.3V Transceiver
(AVDDH)
3.3V Digital I/O
Condition
Total Power
(DVDDH)
1000BT Idle (GMII 3V3 IO)
1000BT Traffic (GMII 3V3 IO)
100BTX Idle (GMII 3V3 IO)
100BTX Traffic (GMII 3V3 IO)
100BTX Idle (MII 3V3 IO)
100BTX Traffic (MII 3V3 IO)
10BT Idle (GMII 3V3 IO)
10BT Traffic (GMII 3V3 IO)
10BT Idle (MII 3V3 IO)
10BT Traffic (MII 3V3 IO)
10BTe Idle (GMII 3V3 IO)
10BTe Traffic (GMII 3V3 IO)
10BTe Idle (MII 3V3 IO)
10BTe Traffic (MII 3V3 IO)
EDPD
210.0 mA
218.0 mA
70.0 mA
70.0 mA
70.0 mA
70.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
2.0 mA
90.0 mA
89.0 mA
45.0 mA
42.0 mA
42.0 mA
43.0 mA
26.0 mA
41.0 mA
26.0 mA
40.0 mA
26.0 mA
34.0 mA
24.0 mA
35.0 mA
15.0 mA
33.0 mA
14.0 mA
15.0 mA
5.0 mA
15.0 mA
46.0 mA
5.0 mA
12.0 mA
10.0 mA
13.0 mA
3.0 mA
3.0 mA
3.0 mA
3.0 mA
3.0 mA
3.0 mA
2.0 mA
3.0 mA
1.0 mA
22.0 mA
8.0 mA
1.0 mA
1.0 mA
598.5 mW
707.1 mW
249.0 mW
262.2 mW
255.6 mW
268.8 mW
117.3 mW
166.8 mW
117.3 mW
163.5 mW
117.3 mW
143.7 mW
107.4 mW
147.0 mW
55.2 mW
EEE 1000BT Idle
46.0 mA
30.0 mA
7.0 mA
236.7 mW
108.6 mW
61.2 mW
EEE 100BTX Idle
RESET
SFPD
0.0 mA
19.8 mW
DS00002840C-page 118
2018-2021 Microchip Technology Inc.
KSZ9131MNX
TABLE 6-5:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (2.5V), DIGITAL I/O (2.5V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
2.5V Transceiver
2.5V Digital I/O
Total Power
(DVDDH)
Condition
(AVDDH)
1000BT Idle (GMII 2V5 IO)
1000BT Traffic (GMII 2V5 IO)
100BTX Idle (GMII 2V5 IO)
100BTX Traffic (GMII 2V5 IO)
100BTX Idle (MII 2V5 IO)
100BTX Traffic (MII 2V5 IO)
10BT Idle (GMII 2V5 IO)
10BT Traffic (GMII 2V5 IO)
10BT Idle (MII 2V5 IO)
10BT Traffic (MII 2V5 IO)
10BTe Idle (GMII 2V5 IO)
10BTe Traffic (GMII 2V5 IO)
10BTe Idle (MII 2V5 IO)
10BTe Traffic (MII 2V5 IO)
EDPD
208.0 mA
220.0 mA
68.0 mA
70.0 mA
70.0 mA
70.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
2.0 mA
77.0 mA
76.0 mA
37.0 mA
37.0 mA
37.0 mA
37.0 mA
20.0 mA
37.0 mA
21.0 mA
37.0 mA
20.0 mA
30.0 mA
20.0 mA
31.0 mA
11.0 mA
26.0 mA
12.0 mA
13.0 mA
3.0 mA
11.0 mA
36.0 mA
4.0 mA
7.0 mA
7.0 mA
7.0 mA
2.0 mA
2.0 mA
2.0 mA
2.0 mA
2.0 mA
2.0 mA
2.0 mA
2.0 mA
1.0 mA
8.0 mA
5.0 mA
1.0 mA
1.0 mA
469.6 mW
544.0 mW
184.1 mW
194.0 mW
194.0 mW
194.0 mW
76.6 mW
119.1 mW
79.1 mW
119.1 mW
76.6 mW
101.6 mW
76.6 mW
104.1 mW
32.4 mW
140.2 mW
78.5 mW
43.4 mW
10.0 mW
EEE 1000BT Idle
46.0 mA
30.0 mA
7.0 mA
EEE 100BTX Idle
RESET
SFPD
0.0 mA
TABLE 6-6:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (2.5V), DIGITAL I/O (1.8V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
2.5V Transceiver
1.8V Digital I/O
(DVDDH)
Condition
Total Power
(AVDDH)
1000BT Idle (GMII 1V8 IO)
1000BT Traffic (GMII 1V8 IO)
100BTX Idle (GMII 1V8 IO)
100BTX Traffic (GMII 1V8 IO)
100BTX Idle (MII 1V8 IO)
100BTX Traffic (MII 1V8 IO)
10BT Idle (GMII 1V8 IO)
10BT Traffic (GMII 1V8 IO)
10BT Idle (MII 1V8 IO)
10BT Traffic (MII 1V8 IO)
10BTe Idle (GMII 1V8 IO)
10BTe Traffic (GMII 1V8 IO)
10BTe Idle (MII 1V8 IO)
10BTe Traffic (MII 1V8 IO)
EDPD
208.0 mA
218.0 mA
70.0 mA
70.0 mA
70.0 mA
70.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
2.0 mA
77.0 mA
76.0 mA
37.0 mA
37.0 mA
37.0 mA
37.0 mA
20.0 mA
37.0 mA
20.0 mA
37.0 mA
20.0 mA
30.0 mA
20.0 mA
31.0 mA
6.0 mA
5.0 mA
18.0 mA
2.0 mA
4.0 mA
4.0 mA
10.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
1.0 mA
0.0 mA
8.0 mA
4.0 mA
451.1 mW
484.0 mW
180.1 mW
183.7 mW
183.7 mW
194.5 mW
73.4 mW
115.9 mW
73.4 mW
115.9 mW
73.4 mW
98.4 mW
73.4 mW
100.9 mW
17.4 mW
134.6 mW
75.7 mW
EEE 1000BT Idle
46.0 mA
30.0 mA
26.0 mA
13.0 mA
EEE 100BTX Idle
2018-2021 Microchip Technology Inc.
DS00002840C-page 119
KSZ9131MNX
TABLE 6-6:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (2.5V), DIGITAL I/O (1.8V) (CONTINUED)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
2.5V Transceiver
1.8V Digital I/O
(DVDDH)
Condition
Total Power
(AVDDH)
RESET
SFPD
7.0 mA
0.0 mA
13.0 mA
3.0 mA
0.0 mA
0.0 mA
40.9 mW
7.5 mW
TABLE 6-7:
TYPICAL CURRENT/POWER CONSUMPTION
TRANSCEIVER (3.3V), DIGITAL I/O (2.5V)
1.2V Core
(DVDDL, AVDDL,
AVDDL_PLL)
3.3V Transceiver
2.5V Digital I/O
(DVDDH)
Condition
Total Power
(AVDDH)
1000BT Idle (GMII 2V5 IO)
1000BT Traffic (GMII 2V5 IO)
100BTX Idle (GMII 2V5 IO)
100BTX Traffic (GMII 2V5 IO)
100BTX Idle (MII 2V5 IO)
100BTX Traffic (MII 2V5 IO)
10BT Idle (GMII 2V5 IO)
10BT Traffic (GMII 2V5 IO)
10BT Idle (MII 2V5 IO)
10BT Traffic (MII 2V5 IO)
10BTe Idle (GMII 2V5 IO)
10BTe Traffic (GMII 2V5 IO)
10BTe Idle (MII 2V5 IO)
10BTe Traffic (MII 2V5 IO)
EDPD
210.0 mA
218.0 mA
70.0 mA
70.0 mA
70.0 mA
70.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
18.0 mA
2.0 mA
77.0 mA
76.0 mA
37.0 mA
37.0 mA
37.0 mA
37.0 mA
20.0 mA
37.0 mA
21.0 mA
37.0 mA
20.0 mA
30.0 mA
20.0 mA
31.0 mA
11.0 mA
26.0 mA
12.0 mA
13.0 mA
3.0 mA
15.0 mA
46.0 mA
5.0 mA
12.0 mA
10.0 mA
13.0 mA
3.0 mA
3.0 mA
3.0 mA
3.0 mA
3.0 mA
3.0 mA
2.0 mA
3.0 mA
1.0 mA
22.0 mA
8.0 mA
1.0 mA
1.0 mA
543.6 mW
627.4 mW
218.6 mW
236.1 mW
231.1 mW
238.6 mW
95.1 mW
151.2 mW
98.4 mW
151.2 mW
95.1 mW
128.1 mW
92.6 mW
131.4 mW
41.2 mW
196.0 mW
95.6 mW
53.8 mW
12.4 mW
EEE 1000BT Idle
46.0 mA
30.0 mA
7.0 mA
EEE 100BTX Idle
RESET
SFPD
0.0 mA
6.5
DC Specifications
TABLE 6-8:
NON-VARIABLE I/O DC ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
0.5
10
Units
Notes
ICLK Type Input Buffer
Low Input Level
Note 6-1
VIL
VIH
IIH
V
V
High Input Level
Input Leakage
2.0
-10
µA
Note 6-1
XI can optionally be driven from a 25 MHz single-ended clock oscillator to which these specifications
apply.
DS00002840C-page 120
2018-2021 Microchip Technology Inc.
KSZ9131MNX
TABLE 6-9:
VARIABLE I/O DC ELECTRICAL CHARACTERISTICS DVDDH = 3.3/2.5/1.8V
Parameter
Symbol
Min
Typ
Max
Units
Notes
VI Type Input Buffer
Low Input Level
VIL
VIH
IIH
0.9/0.9/0.6
V
V
High Input Level
2.1/1.7/1.3
-10
Input Leakage
(VIN = VSS or DVDDH)
10
3
µA
Note 6-2
Input Capacitance
(generic guess)
CIN
RPU
RPD
pF
KΩ
KΩ
Effective Pull-Up Resistance
(VIN = VSS)
44/59/96
47/58/86
Effective Pull-Down Resis-
tance
(VIN = DVDDH)
VIS Type Input Buffer
Low Input Level
VIL
VIH
0.9/0.9/0.6
V
V
V
V
V
High Input Level
2.1/1.7/1.3
Schmitt Falling Trip Point
Schmitt Rising Trip Point
Schmitt Trigger Hysteresis
VT-
1.0/0.8/0.6 1.2/1.0/0.7 1.5/1.1/0.8
1.5/1.2/0.9 1.7/1.4/1.1 1.9/1.6/1.3
0.4/0.3/0.3 0.5/0.4/0.4 0.6/0.5/0.5
VT+
VHYS
(VIHT - VILT
)
Input Leakage
(VIN = VSS or DVDDH)
IIH
-10
10
3
µA
pF
Note 6-2
Input Capacitance
(generic guess)
CIN
Effective Pull-Up Resistance
(VIN = VSS)
RPU
44/59/96
47/58/86
KΩ
Effective Pull-Down Resis-
tance
RPD
KΩ
(VIN = DVDDH)
VO8 Type Buffer
Low Output Level
VOL
VOH
IOZ
0.4/0.4/0.2
10
V
V
I
OL = -8/-8/-6 mA
IOH = -8/-8/-6 mA
High Output Level
Output Tri-State Leakage
2.4/1.9/1.5
-10
Note 6-2
µA
2018-2021 Microchip Technology Inc.
DS00002840C-page 121
KSZ9131MNX
TABLE 6-9:
VARIABLE I/O DC ELECTRICAL CHARACTERISTICS DVDDH = 3.3/2.5/1.8V
Parameter
Symbol
Min
Typ
Max
Units
Notes
VOD8 Type Buffer
Low Output Level
VOL
IOZ
0.4/0.4/0.2
10
V
IOL = -8/-8/-6 mA
Note 6-2
Output Tri-State Leakage
-10
µA
VO24 Type Buffer
Low Output Level
VOL
VOH
IOZ
0.4/0.4/0.2
V
V
I
OL = -24/-24/-14 mA
High Output Level
2.4/1.9/1.5
-10
I
OH = 24/-24/-14 mA
Output Tri-State Leakage
10
µA
Note 6-2
Note 6-2
This specification applies to all inputs without pull-ups or pull-downs and three-stated bi-directional
pins.
TABLE 6-10: 1000BASE-T TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
Notes
Peak Differential Output Voltage
IEEE 802.3 clause 40.6.1.2.1
VOP
670
820
mV
Note 6-3
Signal Amplitude Symmetry
IEEE 802.3 clause 40.6.1.2.1
VSS
VSC
VOD
1
2
%
%
Note 6-3
Note 6-4
Note 6-3
Note 6-5
Signal Scaling
IEEE 802.3 clause 40.6.1.2.1
Output Droop
IEEE 802.3 clause 40.6.1.2.2
73.1
%
Transmission Distortion
10
mV
IEEE 802.3 clause 40.6.1.2.4
Note 6-3
Note 6-4
Note 6-5
IEEE 802.ab Test Mode 1
From 1/2 of average VOP, Test Mode 1
IEEE 802.ab distortion processing
DS00002840C-page 122
2018-2021 Microchip Technology Inc.
KSZ9131MNX
TABLE 6-11: 100BASE-TX TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
Notes
Peak Differential Output Voltage
ANSI X3.263 clause 9.1.2.2
VOUT
±0.95
±1.05
V
Note 6-6
Signal Amplitude Symmetry
ANSI X3.263 clause 9.1.4
VSS
2
5
%
ns
ns
ns
%
ns
V
Note 6-6
Note 6-6
Note 6-6
Note 6-7
Signal Rise and Fall Time
ANSI X3.263 clause 9.1.6
TRF
3
0
Rise and Fall Symmetry
ANSI X3.263 clause 9.1.6
TRFS
DCD
VOS
0.5
±0.25
5
Duty Cycle Distortion
ANSI X3.263 clause 9.1.8
Overshoot and Undershoot
ANSI X3.263 clause 9.1.3
Output Jitter
ANSI X3.263 clause 9.1.9
0.7
1.4
Note 6-8
Reference Voltage of ISET
(using 6.04kΩ - 1% resistor)
VSET
1.20
Note 6-6
Note 6-7
Note 6-8
Measured at line side of transformer, line replaced by 100 (+/- 1%) resistor.
Offset from 16ns pulse width at 50% of pulse peak.
Peak to Peak, measured differentially.
TABLE 6-12: 10BASE-T/10BASE-Te TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
Min
Typ
Max
Units
Notes
Transmitter Peak Differential Output
Voltage
VOUT
10BASE-T
2.2
2.5
2.8
V
Note 6-9
IEEE 802.3 clause 14.3.1.2.1
VOUT
10BASE-Te
1.54
300
1.96
3.5
V
Note 6-9
Output Jitter
IEEE 802.3 clause 14.3.1.2.3
1.8
ns
Note 6-10
Signal Rise and Fall Time
TRF
VDS
25
ns
Receiver Differential Squelch Threshold
IEEE 802.3 clause 14.3.1.3.2
400
mV
Note 6-11
Note 6-9
Note 6-10
Note 6-11
Measured with 100 resistive load.
Measured differentially following the twisted-pair model with a 100 resistive load.
5MHz square wave.
2018-2021 Microchip Technology Inc.
DS00002840C-page 123
KSZ9131MNX
TABLE 6-13: LDO CONTROLLER
Parameter
Symbol
Min
Typ
Max
Units
Notes
1.2
3.11
V
AVDDH = 3.3V
for MOSFET source voltage
Output drive range for
LDO_O to gate input of P-
channel MOSFET
VLDO_O
1.2
2.0
V
V
AVDDH = 2.5V
for MOSFET source voltage
Output of P-channel
MOSFET
1.23
1.25
1.32
TABLE 6-14: POR THRESHOLDS
Rising threshold
volts
Falling threshold
volts
Hysteresis
millivolts
POR
Conditions
min
typ
max
min
typ
max
min
typ
max
AVDDH =
2.5V
0.73
0.73
1.9
0.76
0.80
0.82
2.2
0.64
0.63
1.9
0.68
0.80
0.82
2.1
0
80
114
1.2V Ethernet
PHY Analog
(AVDDL)
AVDDH =
3.3V
0.76
2.1
0.70
2.0
0
65
120
145
2.5V / 3.3V
Ethernet PHY
Analog (AVDDH)
65
110
3.3V / 2.5V /
1.8V VariableI/O
(DVDDH)
1.40
1.48
1.57
1.35
1.42
1.51
45
58
73
DS00002840C-page 124
2018-2021 Microchip Technology Inc.
KSZ9131MNX
6.6
AC Specifications
This section details the various AC timing specifications of the device.
Note:
The GMII/MII timing adheres to or exceeds the IEEE 802.3 specification. Refer to the IEEE 802.3 specifi-
cation for additional GMII/MII timing information.
6.6.1
EQUIVALENT TEST LOAD
Output timing specifications assume a 5pF equivalent test load, unless otherwise noted, as illustrated in Figure 6-1.
FIGURE 6-1:
OUTPUT EQUIVALENT TEST LOAD
OUTPUT
5 pF
2018-2021 Microchip Technology Inc.
DS00002840C-page 125
KSZ9131MNX
6.6.2
POWER SEQUENCE TIMING
These diagrams illustrates the device power sequencing requirements.
FIGURE 6-2:
POWER SEQUENCE TIMING INTERNAL REGULATORS
tvr
tpc
DVDDL, VDDAL,
VDDAL_PLL
VDDAH, DVDDH
trstia
tsr
RESET_N
The recommended power-up sequence is to have the transceiver (AVDDH) and digital I/O (DVDDH) voltages power up
before the 1.2V core (DVDDL, AVDDL, AVDDL_PLL) voltage. If the 1.2V core must power up first, the maximum lead
time for the 1.2V core voltage with respect to the transceiver and digital I/O voltages should be 200 μs.
There is no power sequence requirement between transceiver (AVDDH) and digital I/O (DVDDH) power rails.
The power-up waveforms must be monotonic for all supply voltages to the device.
RESET_N must be held asserted following stable voltages for the minimum period specified and if re-asserted, for the
minimum period specified.
The recommended power-down sequence is to have the 1.2V core voltage power-down before powering down the
transceiver and digital I/O voltages.
Before the next power-up cycle, all supply voltages to the device should reach less than 0.4V and there should be a
minimum wait time of 150 ms from power-off to power-on.
TABLE 6-15: POWER SEQUENCING TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tvr
tsr
Supply voltages rise time (must be monotonic)
Stable supply voltages to de-assertion of reset
RESET_N input assertion time
200
µs
ms
µs
10
1
trstia
tpc
Supply voltages cycle off-to-on time
150
ms
DS00002840C-page 126
2018-2021 Microchip Technology Inc.
KSZ9131MNX
6.6.3
RESET PIN CONFIGURATION STRAP TIMING
Figure 6-3 illustrates the RESET_N timing requirements and its relation to the configuration straps. RESET_N must be
asserted for the minimum period specified.
FIGURE 6-3:
RESET_N CONFIGURATION STRAP TIMING
trstia
RESET_N
tcsh
Configuration
Strap Pins
Output Drive
TABLE 6-16: RESET_N CONFIGURATION STRAP TIMING
Symbol
Description
RESET_N input assertion time
Min
Typ
Max
Units
trstia
tcss
1
5
5
1
µs
ns
ns
us
Configuration strap setup before RESET_N de-assertion
Configuration strap hold after RESET_N de-assertion
Output drive after RESET_N de-assertion
tcsh
todad
2018-2021 Microchip Technology Inc.
DS00002840C-page 127
KSZ9131MNX
6.6.4
GMII TIMING (1000BASE-T)
This section specifies the GMII interface transmit and receive timing.
Note:
• All GMII timing specifications assume a point-to-point test circuit as defined in Section 35.4.2.2 of the IEEE
802.3-2005 specification.
• The below timing parameters assume default values for the following registers:
Clock Invert and Control Signal Pad Skew Register
Clock Pad Skew Register
FIGURE 6-4:
GMII TRANSMIT TIMING
tclkp
tclkh tclkl
tr
tf
GTX_CLK
thold
TXD[7:0],
TX_ER, TX_EN
TABLE 6-17: GMII TRANSMIT TIMING VALUES
Symbol
Description
GTX_CLK Frequency
Min
Max
Units
Notes
fgtxclk
125 -
125 +
MHz
100ppm
100ppm
tclkp
tclkh
tclkl
GTX_CLK period
GTX_CLK high time
GTX_CLK low time
7.5
2.5
2.5
2.0
8.5
ns
ns
ns
ns
tsetup
TXD[7:0], TX_EN, TX_ER setup to rising edge of
GTX_CLK
thold
TXD[7:0], TX_EN, TX_ER hold time from rising
edge of GTX_CLK
0
ns
tr
tf
GTX_CLK rise time
GTX_CLK fall time
1
1
ns
ns
Note 6-12
Note 6-12
Note 6-12
tr and tf are measured from VIL_AC(Max)=0.7V to VIH_AC(Min)=1.9V.
DS00002840C-page 128
2018-2021 Microchip Technology Inc.
KSZ9131MNX
FIGURE 6-5:
GMII RECEIVE TIMING
tclkp
tclkh tclkl
tr
tf
RX_CLK
thold
RXD[7:0],
RX_DV, RX_ER
TABLE 6-18: GMII RECEIVE TIMING VALUES
Symbol
Description
Min
Max
Units
Notes
tclkp
tclkh
tclkl
RX_CLK period
7.5
2.5
2.5
3.0
ns
ns
ns
ns
RX_CLK high time
RX_CLK low time
tsetup
RXD[7:0], RX_DV, RX_ER setup time (provided
by PHY) to rising edge of RX_CLK
thold
RXD[7:0], RX_DV, RX_ER hold time (provided
by PHY) after rising edge of RX_CLK
1.0
ns
tr
tf
RX_CLK rise time
RX_CLK fall time
1
1
ns
ns
Note 6-13
Note 6-13
Note 6-13
tr and tf are measured from VIL_AC(Max)=0.7V to VIH_AC(Min)=1.9V.
2018-2021 Microchip Technology Inc.
DS00002840C-page 129
KSZ9131MNX
6.6.5
MII TIMING (100BASE-TX, 10BASE-T)
This section specifies the MII interface transmit and receive timing.
Note:
The below timing parameters assume default values for the following registers:
Clock Invert and Control Signal Pad Skew Register
Clock Pad Skew Register
FIGURE 6-6:
MII TRANSMIT TIMING
tclkp
tclkh tclkl
TX_CLK
tsu thold
tsu thold
thold
TXD[3:0],
TX_ER
tsu
TX_EN
TABLE 6-19: MII TRANSMIT TIMING VALUES
Symbol
Description
Min
Max
Units
Notes
tclkp
tclkh
tclkl
tsu
TX_CLK period
Note 6-14
ns
ns
ns
ns
TX_CLK high time
TX_CLK low time
tclkp*0.35
tclkp*0.35
13
tclkp*0.65
tclkp*0.65
TXD[3:0], TX_EN, TX_ER setup time to rising
edge of TX_CLK
thold
TXD[3:0], TX_EN, TX_ER output hold from ris-
0
ns
ing edge of TX_CLK
Note 6-14
40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
DS00002840C-page 130
2018-2021 Microchip Technology Inc.
KSZ9131MNX
FIGURE 6-7:
MII RECEIVE TIMING
tclkp
tclkh tclkl
RX_CLK
tsu thold
tsu thold
thold
RXD[3:0],
RX_ER
tsu
RX_DV
TABLE 6-20: MII RECEIVE TIMING VALUES
Symbol
Description
Min
Max
Units
Notes
tclkp
tclkh
tclkl
tsu
RX_CLK period
Note 6-15
ns
ns
ns
ns
RX_CLK high time
RX_CLK low time
tclkp*0.35
tclkp*0.35
12
tclkp*0.65
tclkp*0.65
RXD[3:0], RX_DV, RX_ER setup time (provided
by PHY) to rising edge of RX_CLK
thold
RXD[3:0], RX_DV, RX_ER hold time (provided
by PHY) after rising edge of RX_CLK
12
ns
Note 6-15
40ns for 100BASE-TX operation, 400ns for 10BASE-T operation.
2018-2021 Microchip Technology Inc.
DS00002840C-page 131
KSZ9131MNX
6.6.6
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
FIGURE 6-8:
AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING
TABLE 6-21: AUTO-NEGOTIATION FAST LINK PULSE (FLP) TIMING PARAMETERS
Symbol
Description
FLP burst to FLP burst
Min
Typ
Max
Units
tBTB
tFLPW
tPW
8
16
2
24
ms
ms
ns
FLP burst width
Clock/Data pulse width
100
64
tCTD
tCTC
Clock pulse to data pulse
Clock pulse to clock pulse
Number of clock/data pulses per FLP burst
55.5
111
17
69.5
139
33
µs
µs
128
DS00002840C-page 132
2018-2021 Microchip Technology Inc.
KSZ9131MNX
6.6.7
MDC/MDIO TIMING
This section specifies the MDC/MDIO timing of the device.
FIGURE 6-9:
MDC/MDIO TIMING
tclkp
tclkh tclkl
MDC
tohold
MDIO
(Data-Out)
tsu tihold
MDIO
(Data-In)
TABLE 6-22: MDC/MDIO TIMING VALUES
Symbol
Description
Min
Typ
Max
Units
tclkp
MDC period
120
400
Note 6-17
ns
Note 6-16
tclkh
tclkl
tval
MDC high time
MDC low time
40
40
ns
ns
ns
MDIO (read from PHY) output valid from rising
MDIO of MDC
80
tohold
MDIO (read from PHY) output hold from rising
edge of MDC
0
8
8
ns
ns
ns
tsu
MDIO (write to PHY) input setup time to rising
edge of MDC
tihold
MDIO (write to PHY) input hold time after rising
edge of MDC
Note 6-16
Note 6-17
Test condition for 8.33 MHz (120 ns) is for one device PHY on the MDIO line with a 1.0 kΩ pull-up
to the DVDDH supply rail.
The device can operate with MDC clock frequencies generated from bit banging with GPIO pin in the
10s/100s of Hertz.
2018-2021 Microchip Technology Inc.
DS00002840C-page 133
KSZ9131MNX
6.7
Clock Circuit
The device can accept either a 25MHz crystal (preferred) or a 25 MHz single-ended clock oscillator (+/- 50ppm) input.
If the single-ended clock oscillator method is implemented, XO should be left unconnected and XI should be driven with
either a nominal 0-2.5V or a nominal 0-3.3V clock signal, dependent on the supply level of AVDDH (2.5V and 3.3V,
respectively). The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the crystal input/output signals
(XI/XO). See Table 6-23 for the recommended crystal specifications.
TABLE 6-23: CRYSTAL SPECIFICATIONS
Parameter
Crystal Cut
Symbol
Min
Nom
AT, typ
Fundamental Mode
Parallel Resonant Mode
Max
Units
Notes
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Ffund
Ftol
-
25.000
-
MHz
PPM
PPM
PPM
PPM
pF
Frequency Tolerance @ 25oC
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
-
-
-
-
-
-
-
+/-50
Note 6-18
Note 6-18
Note 6-19
Note 6-20
Ftemp
Fage
-
+/-50
+/-3 to 5
-
-
-
-
+/-50
CO
CL
6
Load Capacitance
25
pF
Motional Inductance
LM
PW
R1
10
mH
µW
Ohm
oC
Drive Level
-
-
100
Equivalent Series Resistance
Operating Temperature Range
XI Pin Capacitance
-
-
50
Note 6-21
-
Note 6-22
-
-
2 typ
2 typ
-
-
pF
Note 6-23
Note 6-23
XO Pin Capacitance
pF
Note 6-18
The maximum allowable values for Frequency Tolerance and Frequency Stability are application
dependent. Since any particular application must meet the IEEE +/-50 PPM Total PPM Budget, the
combination of these two values must be approximately +/-45 PPM (allowing for aging).
Note 6-19
Note 6-20
Note 6-21
Note 6-22
Note 6-23
Frequency Deviation Over Time is also referred to as Aging.
The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as +/- 50 PPM.
0oC for commercial version, -40oC for industrial.
+70oC for commercial version, +85oC for industrial.
This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included
in this value. The XO/XI pin and PCB capacitance values are required to accurately calculate the
value of the two external load capacitors. These two external load capacitors determine the accuracy
of the 25.000 MHz frequency.
DS00002840C-page 134
2018-2021 Microchip Technology Inc.
KSZ9131MNX
6.8
Reset Circuit
The following are some reset circuit suggestions.
Figure 6-10 illustrates the reset circuit for powering up the KSZ9131MNX if reset is triggered by the power supply.
FIGURE 6-10:
RESET CIRCUIT IF TRIGGERED BY THE POWER SUPPLY
DVDDH
D1: 1N4148
D1
R 10K
KSZ9131MNX
RESET_N
C 10μF
Figure 6-11 illustrates the reset circuit for applications where reset is driven by another device (for example, the CPU or
an FPGA). At power-on-reset, R, C, and D1 provide the monotonic rise time to reset the KSZ9131MNX device. The
RST_OUT_N from the CPU/FPGA provides the warm reset after power-up.
The KSZ9131MNX and CPU/FPGA references the same digital I/O voltage (DVDDH).
FIGURE 6-11:
RECOMMENDED RESET CIRCUIT FOR CPU/FPGA RESET OUTPUT
DVDDH
R 10K
D1
KSZ9131MNX
RESET_N
CPU/FPGA
RST_OUT_N
D2
C 10μF
D1, D2: 1N4148
2018-2021 Microchip Technology Inc.
DS00002840C-page 135
KSZ9131MNX
Figure 6-12 illustrates the reset circuit with an MIC826 voltage supervisor driving the KSZ9131MNX reset input.
FIGURE 6-12:
RESET CIRCUIT WITH MIC826 VOLTAGE SUPERVISOR
DVDDH
DVDDH
MIC826
Reset
Threshold
Part
Number
KSZ9131MNX
MIC826TYMT / 3.075V
MIC826ZYMT / 2.315V
MIC826WYMT / 1.665V
RESET_N
RESET#
DVDDH = 3.3V, 2.5V, or 1.8V
DS00002840C-page 136
2018-2021 Microchip Technology Inc.
KSZ9131MNX
6.9
Reference Circuits — LED Strap-In Pins
The pull-up and pull-down reference circuits for the LED2/PHYAD1 and LED1/PHYAD0 strapping pins are shown in
Figure 6-13 for 3.3V and 2.5V DVDDH.
FIGURE 6-13:
REFERENCE CIRCUITS FOR LED STRAPPING PINS
DVDDH = 3.3V, 2.5V
470Ω
PULL‐UP
10kΩ
KSZ9131MNX
LED PIN
DVDDH = 3.3V, 2.5V
PULL‐DOWN
470Ω
KSZ9131MNX
LED PIN
1kΩ
For 1.8V DVDDH, LED indication support requires voltage level shifters between LED[2:1] pins and LED indicator
diodes to ensure the multiplexed PHYAD[1:0] strapping pins are latched in high/low correctly. If LED indicator diodes
are not implemented, the PHYAD[1:0] strapping pins just need 10 kΩ pull-up to 1.8V DVDDH for a value of 1, and 1.0 kΩ
pull-down to ground for a value of 0.
2018-2021 Microchip Technology Inc.
DS00002840C-page 137
KSZ9131MNX
6.10 On-Chip LDO Controller - MOSFET Selection
If the optional LDO controller is used to generate 1.2V for the core voltage, the selected MOSFET should exceed the
following minimum requirements:
• P-channel
• 500 mA (continuous current)
• 3.3V or 2.5V (source – input voltage)
• 1.2V (drain – output voltage)
• VGS in the range of:
- (–1.2V to –1.5V) @ 500 mA for 3.3V source voltage
- (–1.0V to –1.1V) @ 500 mA for 2.5V source voltage
The VGS for the MOSFET needs to be operating in the constant current saturated region, and not towards the VGS(th)
the threshold voltage for the cut-off region of the MOSFET.
,
6.11 Magnetic - Connection and Selection
A 1:1 isolation transformer is required at the line interface. Use one with integrated common-mode chokes for designs
exceeding FCC requirements. An optional auto-transformer stage following the chokes provides additional common-
mode noise and signal attenuation.
The KSZ9131MNX design incorporates voltage-mode transmit drivers and on-chip terminations.
With the voltage-mode implementation, the transmit drivers supply the common-mode voltages to the four differential
pairs. Therefore, the four transformer center tap pins on the KSZ9131MNX side should not be connected to any power
supply source on the board; rather, the center tap pins should be separated from one another and connected through
separate 0.1 µF common-mode capacitors to ground. Separation is required because the common-mode voltage could
be different between the four differential pairs, depending on the connected speed mode.
Figure 6-14 shows the typical Gigabit magnetic interface circuit for the KSZ9131MNX.
FIGURE 6-14:
TYPICAL GIGABIT MAGNETIC INTERFACE CIRCUIT
1
2
TXRXP_A
TXRXM_A
3
TXRXP_B
TXRXM_B
4
5
TXRXP_C
TXRXM_C
6
7
8
TXRXP_D
TXRXM_D
4 x75ꢀ
(4x 0.1μF)
1000pF / 2kV
CHASSIS GROUND
SIGNAL GROUND
DS00002840C-page 138
2018-2021 Microchip Technology Inc.
KSZ9131MNX
Table 6-24 lists recommended magnetic characteristics.
TABLE 6-24: MAGNETICS SELECTION CRITERIA
Parameter
Value
Test Conditions
Turns Ratio
Open-Circuit Inductance (min.)
Insertion Loss (max.)
HIPOT (min.)
1 CT : 1 CT
350 µH
—
100 mV, 100 kHz, 8 mA
0 MHz to 100 MHz
—
1.0 dB
1500 VRMS
Table 6-25 is a list of compatible single-port magnetics with separated transformer center tap pins on the G-PHY chip
side that can be used with the KSZ9131MNX.
TABLE 6-25: COMPATIBLE SINGLE-PORT 10/100/1000 MAGNETICS
Manufacturer
Part Number
Auto-Transformer
Temperature Range
Magnetic + RJ-45
Bel Fuse
HALO
0826-1G1T-23-F
TG1G-E001NZRL
TG1G-S001NZRL
TG1G-S002NZRL
H5007NL
Yes
No
0°C to 70°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
Yes
No
No
No
No
No
No
Yes
Yes
No
No
HALO
No
HALO
Yes
Yes
Yes
Yes
Yes
No
Pulse
Pulse
H5062NL
Pulse
HX5008NL
Pulse
JK0654219NL
JK0-0136NL
Pulse
TDK
TLA-7T101LF
000-7093-37R-LF1
No
Wurth/Midcom
Yes
2018-2021 Microchip Technology Inc.
DS00002840C-page 139
KSZ9131MNX
7.0
PACKAGE OUTLINE
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
FIGURE 7-1:
64-LEAD QFN 8 MM X 8 MM PACKAGE WITH 6.5 MM X 6.5 MM EXPOSED PAD
AREA
DS00002840C-page 140
2018-2021 Microchip Technology Inc.
KSZ9131MNX
APPENDIX A: DATA SHEET REVISION HISTORY
TABLE A-1:
REVISION HISTORY
Revision
Section/Figure/Entry
Correction
Table 3-8, "Device Mode Selec-
tions"
1000BT Full Duplex need to change to 'no' for
modes 1001 (9) and 1011 (11).
DS00002840C (04-20-21)
Replace one column "PME Pin Enable" with
two columns: "Pin 19 Function" (PME_N1) and
"Pin 53 Function" (PME_N2).
Section 4.13.3.1.1 “LED Com-
bine”
Note added at end of the paragraph: LED
Behavior Register, Bit 15 = 1 (Default is 0) to
set the LED Link/Activity to the desired value.
This can be done in the same LED Behavior
Register write to set the LED Combine Dis-
ables field.
Section 4.15 “LinkMD® Cable
Diagnostic”
6th paragraph: Removed "With the Bit[9:0]
Definition (VCT_SEL[1:0]) field set to 0,"
Section 5.1 “Register Map”
"These registers are accessed through the SMI
(MDIO/MDC) interface." added before the reg-
isters.
Section 5.2.16 “LinkMD Cable
Diagnostic Register”
Register bits [11:10]: Reserved.
Register bits [9:8]: Sentences removed with
"VCT_SEL".
Register bits [7:0]: Sentence removed about
"VCT_SEL!=00". "When VCT_SEL = 0,"
removed in the next sentence.
Section 5.3 “MDIO Manageable
Device (MMD) Registers”
"These registers are accessed through the SMI
(MDIO/MDC) interface." added before the reg-
isters.
Table 6-3, "Power Consumption"
Right column, 85°C max power: 793.7
changed to 681.9 mW.
Right column, 105°C max power: 804.2
changed to 692.5 mW.
Section 6.4 “Power Consump-
tion”
Added new tables after Table 6-3, "Power Con-
sumption": Table 6-4, Table 6-5, Table 6-6,
Table 6-7
Table 6-11, "100BASE-TX Trans-
ceiver Characteristics"
Last row: Typical Reference voltage of ISET
changed from "0.61 V" to "1.20 V".
Figure 6-2, "Power Sequence Tim-
VDDIO to DVDDH changed in the graphic.
ing Internal Regulators"
Section 6.7 “Clock Circuit”
Second sentence changed to "If the single-
ended clock oscillator method is implemented,
XO should be left unconnected and XI should
be driven with either a nominal 0-2.5V or a
nominal 0-3.3V clock signal, dependent on the
supply level of AVDDH (2.5V and 3.3V, respec-
tively)."
2018-2021 Microchip Technology Inc.
DS00002840C-page 141
KSZ9131MNX
TABLE A-1:
REVISION HISTORY (CONTINUED)
Revision
DS00002840B (10-09-19)
Section/Figure/Entry
Correction
Revised loopback steps
Section 4.14.1, "Digital (near-end)
Loopback"
Table 3-3, "GMII Interface"
Revised note in table
Added step 3
Section 4.14.2, "Remote (far-end)
Loopback"
Table 6-3, "Power Consumption"
Updated values
Modified figure
Figure 6-13, "Reference Circuits
For LED Strapping Pins"
DS00002840A (11-08-18) All
Initial release.
DS00002840C-page 142
2018-2021 Microchip Technology Inc.
KSZ9131MNX
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• Field Application Engineer (FAE)
• Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales
offices are also available to help customers. A listing of sales offices and locations is included in the back of this
document.
Technical support is available through the web site at: http://microchip.com/support
2018-2021 Microchip Technology Inc.
DS00002840C-page 143
KSZ9131MNX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
XX
X
[XX]
Examples:
a)
b)
c)
d)
KSZ9131MNXC
MII, GMII Interface
64-pin QFN (Pb-Free, 6.5 mm x 6.5 mm ePad)
Commercial Temperature
Tray
KSZ9131MNXC-TR
MII, GMII Interface
64-pin QFN (Pb-Free, 6.5 mm x 6.5 mm ePad)
Commercial Temperature
Tape and reel
KSZ9131MNXI
MII, GMII Interface
64-pin QFN (Pb-Free, 6.5 mm x 6.5 mm ePad)
Industrial Temperature
Tray
Interface Package Temperature Media Type
Device:
KSZ9131
Interface:
M
= MII, GMII
Package:
NX
= 64-pin QFN
Temperature:
C
I
=
=
0C to +70C (Commercial)
-40C to +85C (Industrial)
KSZ9131MNXI-TR
MII, GMII Interface
64-pin QFN (Pb-Free, 6.5 mm x 6.5 mm ePad)
Industrial Temperature
Tape and reel
Media Type
Blank = Standard packaging (tray)
TR
= Tape and Reel(Note 1)
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office
for package availability with the Tape and
Reel option.
DS00002840C-page 144
2018-2021 Microchip Technology Inc.
KSZ9131MNX
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are
committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection
feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or
other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication is provided for the sole purpose of designing with and using Microchip products. Information regarding device
applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application
meets with your specifications.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND
WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT
NOT LIMITED TO ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE
OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL LOSS, DAMAGE,
COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP
HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW,
MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT
OF FEES, IFANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety
applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless
otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch,
MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PackeTime, PIC, picoPower, PICSTART, PIC32 logo,
PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other
countries.
AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire, SmartFusion,
SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, WinPath, and ZL are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom,
CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, Espresso T1S, EtherGREEN, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip
Connectivity, JitterBlocker, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK,
NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker,
RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II,
Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and
ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage Technology, and Symmcom are registered trademarks of Microchip Technology Inc. in
other countries.
GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other
countries.
All other trademarks mentioned herein are property of their respective companies.
© 2018-2021, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 9781522478874
For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
2018-2021 Microchip Technology Inc.
DS00002840C-page 145
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-72400
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7288-4388
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
2018-2021 Microchip Technology Inc.
DS00002840C-page 146
02/28/20
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