LND150N8GP003 [MICROCHIP]

N-Channel Depletion-Mode DMOS FETs;
LND150N8GP003
型号: LND150N8GP003
厂家: MICROCHIP    MICROCHIP
描述:

N-Channel Depletion-Mode DMOS FETs

文件: 总16页 (文件大小:580K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
LND150/LND250  
N-Channel Depletion-Mode DMOS FETs  
Features  
General Description  
The LND150 and LND250 are high-voltage N-channel  
Depletion-mode (normally-on) transistors utilizing  
lateral DMOS technology. The gate is ESD protected.  
• Free from Secondary Breakdown  
• Low-Power Drive Requirement  
• Ease of Paralleling  
The LND150/LND250 are ideal for high-voltage appli-  
cations, such as normally-on switches, precision  
constant-current sources, voltage-ramp generation  
and amplification.  
• Excellent Thermal Stability  
• Integral Source-Drain Diode  
• High Input Impedance and Low CISS  
• ESD Gate Protection  
Applications  
• Solid-State Relays  
• Normally-On Switches  
• Converters  
• Power Supply Circuits  
• Constant-Current Sources  
• Input Protection Circuits  
Package Types  
3-lead TO-92  
3-lead SOT-89  
3-lead SOT-23  
(Top view)  
(Top view)  
(Top view)  
SOURCE  
SOURCE  
DRAIN  
DRAIN  
SOURCE  
DRAIN  
SOURCE  
GATE  
GATE  
GATE  
See Table 3-1, Table 3-2 and Table 3-3 for pin information.  
2018 Microchip Technology Inc.  
DS20005454A-page 1  
LND150/LND250  
1.0  
ELECTRICAL CHARACTERISTICS  
ABSOLUTE MAXIMUM RATINGS  
Drain-to-Source Voltage ...................................................................................................................................... BVDSX  
Drain-to-Gate Voltage .......................................................................................................................................... BVDGX  
Gate-to-Source Voltage ......................................................................................................................................... ±20V  
Operating Ambient Temperature, TA ...................................................................................................... –55°C to 150°C  
Storage Temperature, TS ....................................................................................................................... –55°C to 150°C  
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is  
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the  
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods  
may affect device reliability.  
DC ELECTRICAL CHARACTERISTICS  
Electrical Specifications: TA = 25°C unless otherwise specified. All DC parameters are 100% tested at 25°C unless  
otherwise stated. Pulse test: 300 µs pulse, 2% duty cycle  
Parameter  
Sym.  
Min. Typ. Max. Unit  
Conditions  
Drain-to-Source Breakdown Voltage  
Gate-to-Source Off Voltage  
BVDSX  
VGS(OFF)  
VGS(OFF)  
500  
–1  
–3  
5
V
V
VGS = –10V, ID = 1 mA  
VGS = 25V, ID = 100 nA  
Change in VGS(OFF) with Temperature  
mV/°C VGS = 25V, ID = 100 nA  
(Note 1)  
Gate Body Leakage Current  
IGSS  
100  
100  
nA  
nA  
VGS = ±20V, VDS = 0V  
VGS = –10V, VDS = 450V  
VDS = 0.8V Maximum rating,  
VGS = –10V, TA= 125°C  
(Note 1)  
Drain-to-Source Leakage Current  
ID(OFF)  
100  
3
µA  
Saturated Drain-to-Source Current  
IDSS  
1
mA VGS = 0V, VDS = 25V  
Static Drain-to-Source On-State Resistance  
RDS(ON)  
850 1000  
VGS = 0V, ID = 0.5 mA  
VGS = 0V, ID = 0.5 mA  
(Note 1)  
Change in RDS(ON) with Temperature  
RDS(ON)  
1.2 %/°C  
Note 1: Specification is obtained by characterization and is not 100% tested.  
DS20005454A-page 2  
2018 Microchip Technology Inc.  
LND150/LND250  
AC ELECTRICAL CHARACTERISTICS  
Electrical Specifications: TA = 25°C unless otherwise specified. Specification is obtained by characterization and is  
not 100% tested.  
Parameter  
Sym. Min. Typ. Max. Unit  
Conditions  
Forward Transconductance  
Input Capacitance  
GFS  
CISS  
COSS  
CRSS  
td(ON)  
tr  
1
2
10  
3.5  
1
mmho VDS = 0V, ID = 1 mA  
pF  
7.5  
2
VGS = –10V,  
Common Source Output Capacitance  
Reverse Transfer Capacitance  
Turn-On Delay Time  
pF  
pF  
ns  
ns  
ns  
ns  
VDS = 25V,  
f = 1 MHz  
0.5  
0.09  
0.45  
0.1  
1.3  
VDD = 25V,  
Rise Time  
ID = 1 mA,  
RGEN = 25Ω  
Turn-Off Delay Time  
td(OFF)  
tf  
Fall Time  
DIODE PARAMETER  
Diode Forward Voltage Drop  
Reverse Recovery Time  
VSD  
trr  
0.9  
V
VGS = –10V, ISD = 1 mA (Note 1)  
200  
ns  
VGS = –10V, ISD = 1 mA  
Note 1: Unless otherwise stated, all DC parameters are 100% tested at +25°C. Pulse test: 300 µs pulse, 2% duty  
cycle.  
TEMPERATURE SPECIFICATIONS  
Parameter  
Sym. Min. Typ. Max. Unit  
Conditions  
TEMPERATURE RANGE  
Operating Ambient Temperature  
Storage Temperature  
PACKAGE THERMAL RESISTANCE  
3-lead TO-92  
TA  
TS  
–55  
–55  
+150  
+150  
°C  
°C  
JA  
JA  
JA  
132  
203  
133  
°C/W  
°C/W  
°C/W  
3-lead SOT-23  
3-lead SOT-89  
THERMAL CHARACTERISTICS  
ID (Note 1)  
(Continuous) (Pulsed)  
ID  
Power Dissipation  
at TA = 25°C  
(W)  
IDRM  
(Note 1)  
(A)  
IDR  
(mA)  
Package  
(mA)  
(A)  
3-lead TO-92  
3-lead SOT-23  
3-lead SOT-89  
30  
13  
30  
30  
30  
30  
0.74  
0.36  
30  
13  
30  
30  
30  
1.6 (Note 2) 30  
Note 1: ID (continuous) is limited by maximum rated TJ.  
2: TA = 25°C. Mounted on an FR4 Board, 25 mm x 25 mm x 1.57 mm.  
2018 Microchip Technology Inc.  
DS20005454A-page 3  
LND150/LND250  
2.0  
TYPICAL PERFORMANCE CURVES  
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g. outside specified power supply range) and therefore outside the warranted range.  
6
5
4
3
2
1
0
6
5
4
3
2
1
0
VGS = 1.0V  
VGS = 1.0V  
0.5V  
0V  
0.5V  
0V  
-0.5V  
-1.0V  
-0.5V  
-1.0V  
0
1
2
3
5
0
250  
500  
4
VDS (V)  
VDS (V)  
FIGURE 2-1:  
OutputCharacteristics.  
FIGURE 2-4:  
Saturation Characteristics.  
10  
2
VDS = 400V  
SOT-89  
8
6
4
2
0
TA = -55°C  
25°C  
1
TO-92  
125°C  
SOT-23  
0
0
2
4
6
8
10  
0
50  
100  
150  
ID (milliamps)  
TA (°C)  
FIGURE 2-2:  
Transconductance vs. Drain  
FIGURE 2-5:  
Power Dissipation vs.  
Current.  
Ambient Temperature.  
100  
1.0  
SOT-89 (DC)  
TO-92 (DC)  
Pulsed  
SOT-89  
TA = 25°C  
PD = 1.2W  
0.8  
0.6  
0.4  
10  
SOT-23 (DC)  
1
TO-92  
PD = 1.0W  
TC = 25°C  
0.2  
0
TA = 25°C  
300μs pulse  
2% duty cycle  
0.1  
0.001  
0.01  
0.1  
1.0  
10  
1
10  
100  
1000  
tP (seconds)  
VDS (V)  
FIGURE 2-6:  
Thermal Response  
FIGURE 2-3:  
Maximum Rated Safe  
Characteristics.  
Operating Area.  
DS20005454A-page 4  
2018 Microchip Technology Inc.  
LND150/LND250  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
VGS = -5.0V  
1.1  
ID  
25°C  
LND1  
125°C  
RSOURCE  
1.0  
0.9  
-50  
0
50  
100  
150  
10  
100  
1K  
10K  
100K  
Tj (OC)  
RSOURCE (Ω)  
FIGURE 2-7:  
Temperature.  
10  
BV  
Variation with  
FIGURE 2-10:  
Drain Current vs. R  
.  
SOURCE  
DSS  
1.8  
VDS = 400V  
2.0  
1.6  
1.4  
1.2  
1.0  
TA = -55°C  
RDS(ON) @ ID = 1.0mA  
1.6  
25°C  
125°C  
1.2  
0.8  
0.4  
5
VGS(OFF) @ 100nA  
0.8  
-50  
0
0
50  
100  
150  
-1  
0
1
2
3
VGS (V)  
Tj (OC)  
FIGURE 2-8:  
Transfer Characteristics.  
FIGURE 2-11:  
V
and R Variation  
GS(OFF) DS  
with Temperature.  
10  
10  
VGS = -10V  
8.7pF  
CISS  
VDS = 20V  
40V  
60V  
5
0
5
COSS  
CRSS  
0
-5  
0
10  
20  
30  
40  
0
0.1  
0.2  
0.3  
VDS (V)  
QC (nanocoulombs)  
FIGURE 2-9:  
Capacitance vs. Drain-to-  
FIGURE 2-12:  
Gate Drive Dynamic  
Source Voltage.  
Characteristics.  
2018 Microchip Technology Inc.  
DS20005454A-page 5  
LND150/LND250  
3.0  
PIN DESCRIPTION  
The details on the pins of LND150/LND250 are listed  
on Table 3-1, Table 3-2 and Table 3-3. Refer  
to Package Types for the location of pins.  
TABLE 3-1:  
Pin Number  
TO-92 PIN FUNCTION TABLE  
Pin Name  
Description  
Description  
Description  
1
2
3
SOURCE  
GATE  
SOURCE  
GATE  
DRAIN  
DRAIN  
TABLE 3-2:  
Pin Number  
SOT-23 PIN FUNCTION TABLE  
Pin Name  
GATE  
DRAIN  
GATE  
1
2
3
DRAIN  
SOURCE  
SOURCE  
TABLE 3-3:  
Pin Number  
SOT-89 PIN FUNCTION TABLE  
Pin Name  
1
2, 4  
3
GATE  
SOURCE  
DRAIN  
GATE  
SOURCE  
DRAIN  
DS20005454A-page 6  
2018 Microchip Technology Inc.  
LND150/LND250  
4.0  
FUNCTIONAL DESCRIPTION  
Figure 4-1 illustrates the switching waveforms and test  
circuit for LND150/LND250.  
0V  
VDD  
90%  
INPUT  
Pulse  
RL  
10%  
Generator  
-10V  
OUTPUT  
t(ON)  
td(ON)  
t(OFF)  
td(OFF)  
RGEN  
tf  
tr  
VDD  
OUTPUT  
INPUT  
D.U.T.  
10%  
10%  
90%  
90%  
0V  
FIGURE 4-1:  
Switching Waveforms and Test Circuit.  
TABLE 4-1:  
PRODUCT SUMMARY  
RDS(ON)  
IDSS(ON)  
(Minimum)  
(mA)  
BVDSX/BVDGX  
(Maximum)  
(V)  
()  
500  
1000  
1
2018 Microchip Technology Inc.  
DS20005454A-page 7  
LND150/LND250  
5.0  
5.1  
PACKAGING INFORMATION  
Package Marking Information  
Example  
LND150  
3-lead TO-92  
XXXXXX  
e
3
e3  
XX  
N3  
YWWNNN  
802343  
3-lead SOT-23  
Example  
NDE343  
XXXNNN  
3-lead SOT-89  
Example  
LN1E802  
XXXXYWW  
343  
NNN  
Legend: XX...X Product Code or Customer-specific information  
Y
Year code (last digit of calendar year)  
YY  
WW  
NNN  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
Pb-free JEDEC® designator for Matte Tin (Sn)  
This package is Pb-free. The Pb-free JEDEC designator ( )  
e
3
*
e
3
can be found on the outer packaging for this package.  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for product code or customer-specific information. Package may or  
not include the corporate logo.  
DS20005454A-page 8  
2018 Microchip Technology Inc.  
LND150/LND250  
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  
2018 Microchip Technology Inc.  
DS20005454A-page 9  
LND150/LND250  
3-Lead TO-236AB (SOT-23) Package Outline (K1/T)  
2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch  
D
3
E1  
E
Gauge  
Plane  
0.25  
Seating  
Plane  
L
1
2
L1  
e
b
e1  
View B  
Top View  
View B  
A
A2  
A
Seating  
Plane  
A1  
View A - A  
Side View  
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  
Symbol  
A
0.89  
-
A1  
0.01  
-
A2  
b
0.30  
-
D
E
2.10  
-
E1  
e
e1  
L
L1  
ș
0O  
-
MIN  
NOM  
MAX  
0.88  
0.95  
1.02  
2.80  
2.90  
3.04  
1.20  
1.30  
1.40  
0.20†  
0.50  
0.60  
Dimension  
(mm)  
0.95  
BSC  
1.90  
BSC  
0.54  
REF  
1.12  
0.10  
0.50  
2.64  
8O  
JEDEC Registration TO-236, Variation AB, Issue H, Jan. 1999.  
† This dimension differs from the JEDEC drawing.  
Drawings not to scale.  
DS20005454A-page 10  
2018 Microchip Technology Inc.  
LND150/LND250  
3-Lead TO-243AA (SOT-89) Package Outline (N8)  
D
D1  
C
H
E
E1  
1
2
3
L
b
b1  
A
e
e1  
Top View  
Side View  
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.  
Symbol  
A
1.40  
-
b
0.44  
-
b1  
0.36  
-
C
0.35  
-
D
4.40  
-
D1  
1.62  
-
E
2.29  
-
E1  
2.00†  
-
e
e1  
H
3.94  
-
L
0.73†  
-
MIN  
NOM  
MAX  
Dimensions  
(mm)  
1.50  
BSC  
3.00  
BSC  
1.60  
0.56  
0.48  
0.44  
4.60  
1.83  
2.60  
2.29  
4.25  
1.20  
JEDEC Registration TO-243, Variation AA, Issue C, July 1986.  
This dimension differs from the JEDEC drawing  
Drawings not to scale.  
2018 Microchip Technology Inc.  
DS20005454A-page 11  
LND150/LND250  
NOTES:  
DS20005454A-page 12  
2018 Microchip Technology Inc.  
LND150/LND250  
APPENDIX A: REVISION HISTORY  
Revision A (August 2018)  
• Converted and merged Supertex Doc#s  
DSFP-LND150 and DSFP-LND250 to Microchip  
DS20005454  
• Changed the package marking format  
• Removed the TO-92 N3 P005 media type  
• Added some sections to comply with the standard  
Microchip Technology Inc. documentation format  
• Made minor text changes throughout the docu-  
ment  
2018 Microchip Technology Inc.  
DS20005454A-page 13  
LND150/LND250  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
-
-
PART NO.  
Device  
XX  
X
X
Examples:  
Package Environmental Media  
Options Type  
a) LND150N3-G:  
N-Channel Depletion-Mode  
DMOS FET, 3-lead TO-92,  
1000/Bag  
Devices:  
LND150 = N-Channel Depletion-Mode DMOS FET  
LND250 = N-Channel Depletion-Mode DMOS FET  
b) LND150K1-G:  
N-Channel Depletion-Mode   
DMOS FET, 3-lead SOT-23,  
3000/Reel  
Packages:  
N3  
K1  
N8  
= 3-lead TO-92  
= 3-lead SOT-23  
= 3-lead SOT-89  
c) LND150N8-G:  
d) LND150N3-G-P002:  
N-Channel Depletion-Mode   
DMOS FET, 3-lead TO-92,  
2000/Reel  
Environmental:  
Media Types:  
G
= Lead (Pb)-free/ROHS-compliant package  
(blank) = 1000/Bag for an N3 package  
= 3000/Reel for a K1 package  
N-Channel Depletion-Mode   
DMOS FET, 3-lead TO-92,  
2000/Reel  
= 2000/Reel for an N8 package  
= 2000/Reel for an N3 package  
= 2000/Reel for an N3 package  
= 2000/AMMO Pack for an N3 package  
= 2000/AMMO Pack for an N3 package  
P002  
P003  
P013  
P014  
Note: LND250 is only offered in 3-lead SOT-23 package.  
DS20005454A-page 14  
2018 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
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OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
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conveyed, implicitly or otherwise, under any Microchip  
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The Microchip name and logo, the Microchip logo, AnyRate, AVR,  
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,  
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,  
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All other trademarks mentioned herein are property of their  
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QUALITYMANAGEMENTꢀꢀSYSTEMꢀ  
CERTIFIEDBYDNVꢀ  
© 2018, Microchip Technology Incorporated, All Rights Reserved.  
ISBN: 978-1-5224-3438-2  
== ISO/TS16949==ꢀ  
2018 Microchip Technology Inc.  
DS20005454A-page 15  
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Canada - Toronto  
Tel: 905-695-1980  
Fax: 905-695-2078  
DS20005454A-page 16  
2018 Microchip Technology Inc.  
08/15/18  

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