MC3424T-E/SL [MICROCHIP]
4-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14, 0.150 INCH, PLASTIC, SOIC-14;型号: | MC3424T-E/SL |
厂家: | MICROCHIP |
描述: | 4-CH 18-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO14, 0.150 INCH, PLASTIC, SOIC-14 光电二极管 转换器 |
文件: | 总42页 (文件大小:794K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MCP3424
18-Bit, 4-Channel ΔΣ Analog-to-Digital Converter with
I2C™ Interface and On-Board Reference
Features
Description
• 18-bit ΔΣ ADC with 4 Input Channels
• Differential Inputs (CHn+, CHn-) for each channel
The MCP3424 is a low noise, high accuracy
delta-sigma analog-to-digital (ΔΣ A/D) converter with 4
differential input channels and up to 18 bits of resolu-
tion. The on-board 2.048V reference voltage enables
an input range of ± 2.048V differentially (full-scale
range = 4.096V/PGA). The MCP3424 is a family
member of the MCP342X series from Microchip Tech-
nology Inc.
- Differential Input Full-Scale Range:
-VREF to +VREF
• Self Calibration of Internal Offset and Gain per
Each Conversion
• On-Board Voltage Reference (VREF):
- Accuracy: 2.048V ± 0.05%
- Drift: 15 ppm/°C
The device can output analog-to-digital conversion
results at rates of 3.75, 15, 60, or 240 samples per
second depending on the user controllable configura-
tion bit settings using the two-wire I2C serial interface.
During each conversion, the device calibrates offset
and gain errors automatically. This provides accurate
conversion results from conversion to conversion over
variations in temperature and power supply fluctuation.
• On-Board Programmable Gain Amplifier (PGA):
- Gains of 1,2, 4 or 8
• INL: 10 ppm of Full-Scale Range
(FSR = 4.096V/PGA)
• Programmable Data Rate Options:
- 3.75 SPS (18 bits)
The user can select the PGA gain of x1, x2, x4, or x8
before the analog-to-digital conversion takes place.
This allows the MCP3424 device to convert a very
weak input signal with high resolution.
- 15 SPS (16 bits)
- 60 SPS (14 bits)
- 240 SPS (12 bits)
• One-Shot or Continuous Conversion Options
• Low Current Consumption:
The MCP3424 device has two conversion modes: (a)
One-Shot Conversion mode and (b) Continuous Con-
version mode. In One-Shot conversion mode, the
device performs a single conversion and enters a low
current standby mode automatically until it receives
another conversion command. This reduces current
consumption greatly during idle periods. In continuous
conversion mode, the conversion takes place
continuously at the set conversion speed. The device
updates its output buffer with the most recent conver-
sion data.
- 135 µA typical
(VDD= 3V, Continuous Conversion)
- 36 µA typical
(VDD= 3V, One-Shot Conversion with 1 SPS)
• On-Board Oscillator
• I2CTM Interface:
- User configurable eight available addresses
- Two address selection pins (Adr0, Adr1)
- Standard, Fast and High Speed Modes
• Single Supply Operation: 2.7V to 5.5V
• Extended Temperature Range: -40°C to +125°C
The device has two external I2C address selection pins
(Adr0 and Adr1). The user can configure the device to
one of eight available addresses by connecting these
two address selection pins to VDD, VSS or float.
Typical Applications
The MCP3424 device operates from a single 2.7V to
5.5V power supply and has a two-wire I2C compatible
• Portable Instrumentation
serial interface for
a standard (100 kHz), fast
• Temperature Sensing with RTD, Thermistor, and
Thermocouple
(400 kHz), or high-speed (3.4 MHz) mode.
The MCP3424 device is available in 14-pin SOIC and
TSSOP packages.
• Bridge Sensing for Pressure, Strain, and Force
• Factory Automation Equipment
• Consumer Goods
• Weigh Scales and Fuel Gauges
© 2008 Microchip Technology Inc.
DS22088A-page 1
MCP3424
Package Types
SOIC, TSSOP
14
CH1+
CH1-
1
2
3
4
5
6
7
CH4-
13
12
CH4+
CH3-
CH2+
CH2-
VSS
11
10
CH3+
Adr1
9
8
VDD
SDA
Adr0
SCL
Functional Block Diagram
VDD
VSS
CH1+
CH1-
CH2+
CH2-
Voltage Reference
(2.048V)
VREF
Adr1
Adr0
SCL
I2C
ΔΣ ADC
Converter
PGA
Interface
CH3+
CH3-
SDA
Gain = 1,2,4, or 8
Clock
Oscillator
CH4+
CH4-
DS22088A-page 2
© 2008 Microchip Technology Inc.
MCP3424
†Notice: Stresses above those listed under “Maximum Rat-
ings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings†
VDD...................................................................................7.0V
All inputs and outputs ............. ..........VSS –0.4V to VDD+0.4V
Differential Input Voltage ...................................... |VDD - VSS
|
Output Short Circuit Current ................................Continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±10 mA
Storage Temperature ....................................-65°C to +150°C
Ambient Temp. with power applied ...............-55°C to +125°C
ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM
Maximum Junction Temperature (TJ)..........................+150°C
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
CHn+ = CHn- = VREF/2. All ppm units use 2*VREF as differential full-scale range.
Parameters
Analog Inputs
Sym
Min
Typ
Max
Units
Conditions
Differential Full-Scale Input
Voltage Range
FSR
—
±2.048/PGA
—
V
VIN = [CHn+ - CHn-]
Maximum Input Voltage Range
Differential Input Impedance
V
SS-0.3
—
—
VDD+0.3
—
V
(Note 1)
ZIND (f)
2.25/PGA
MΩ
During normal mode operation
(Note 2)
Common Mode input
Impedance
ZINC (f)
—
25
—
MΩ
PGA = 1, 2, 4, 8
System Performance
Resolution and No Missing
Codes
(Effective Number of Bits)
(Note 7)
12
14
—
—
—
—
Bits
Bits
DR = 240 SPS
DR = 60 SPS
DR = 15 SPS
DR = 3.75 SPS
12 bits mode
14 bits mode
16 bits mode
18 bits mode
16
—
—
Bits
18
—
—
Bits
Data Rate
(Note 3)
DR
INL
176
44
240
60
328
82
SPS
SPS
SPS
SPS
11
15
20.5
5.1
—
2.75
—
3.75
1.5
Output Noise
µVRMS TA = +25°C, DR = 3.75 SPS,
PGA = 1, VIN+ = VIN- = GND
Integral Non-Linearity
—
10
35
DR = 3.75 SPS
(Note 4)
ppm of
FSR
Internal Reference Voltage
VREF
—
—
2.048
0.05
—
V
Gain Error (Note 5)
0.35
%
PGA = 1, DR = 3.75 SPS
Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2: This input impedance is due to 3.2 pF internal input sampling capacitor.
3: The total conversion speed includes auto-calibration of offset and gain.
4: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
5: Includes all errors from on-board PGA and VREF
.
6: This parameter is ensured by characterization and not 100% tested.
7: This parameter is ensured by design and not 100% tested.
8: Addr_Float voltage is applied at address pin.
9: No voltage is applied at address pin (left “floating”).
© 2008 Microchip Technology Inc.
DS22088A-page 3
MCP3424
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V,
CHn+ = CHn- = VREF/2. All ppm units use 2*VREF as differential full-scale range.
Parameters
Sym
Min
Typ
Max
Units
Conditions
PGA Gain Error Match (Note 5)
Gain Error Drift (Note 5)
Offset Error
—
—
—
0.1
15
15
—
—
55
%
Between any 2 PGA settings
ppm/°C PGA=1, DR=3.75 SPS
VOS
µV
Tested at PGA = 1
DR = 3.75 SPS
Offset Drift vs. Temperature
Common-Mode Rejection
—
—
—
—
50
105
110
5
—
—
—
—
nV/°C
dB
at DC and PGA =1,
dB
at DC and PGA =8, TA = +25°C
Gain vs. VDD
ppm/V TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Supply Rejection at DC
Input
—
100
—
dB
TA = +25°C, VDD = 2.7V to 5.5V,
PGA = 1
Power Requirements
Voltage Range
VDD
IDDA
2.7
—
—
—
—
5.5
180
—
V
Supply Current during
Conversion
145
135
0.3
µA
µA
µA
VDD = 5.0V
VDD = 3.0V
VDD = 5.0V
Supply Current during Standby
Mode
IDDS
1
I2C Digital Inputs and Digital Outputs
High level input voltage
Low level input voltage
Low level output voltage
VIH
0.7VDD
—
—
—
—
—
VDD
0.3VDD
0.4
V
V
V
V
at SDA and SCL pins
at SDA and SCL pins
IOL = 3 mA
VIL
VOL
—
Hysteresis of Schmidt Trigger
VHYST
0.05VDD
—
fSCL = 100 kHz
for inputs (Note 6)
Supply Current when I2C bus
line is active
IDDB
—
—
10
µA
Device is in standyby mode
while I2C bus is active
Input Leakage Current
IILH
IILL
—
-1
—
—
1
µA
µA
VIH = 5.5V
VIL = GND
—
Logic Status of I2C Address Pins
Adr0 and Adr1 Pins
Adr0 and Adr1 Pins
Adr0 and Adr1 Pins
Addr_Low
VSS
—
—
—
0.2VDD
VDD
V
V
V
The device reads logic low.
The device reads logic high.
Addr_High 0.75VDD
Addr_Float 0.35VDD
0.6VDD
Read pin voltage if voltage is
applied to the address pin.
(Note 8)
—
V
DD/2
—
Device outputs float output
voltage (VDD/2) on the address
pin, if left “floating”. (Note 9)
Pin Capacitance and I2C Bus Capacitance
Pin capacitance
I2C Bus Capacitance
CPIN
Cb
—
—
—
—
10
pF
pF
400
Note 1: Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins.
This parameter is ensured by characterization and not 100% tested.
2: This input impedance is due to 3.2 pF internal input sampling capacitor.
3: The total conversion speed includes auto-calibration of offset and gain.
4: INL is the difference between the endpoints line and the measured code at the center of the quantization band.
5: Includes all errors from on-board PGA and VREF
.
6: This parameter is ensured by characterization and not 100% tested.
7: This parameter is ensured by design and not 100% tested.
8: Addr_Float voltage is applied at address pin.
9: No voltage is applied at address pin (left “floating”).
DS22088A-page 4
© 2008 Microchip Technology Inc.
MCP3424
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, TA = -40°C to +125°C, VDD = +5.0V, VSS = 0V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+85
+125
+150
°C
°C
°C
θJA
θJA
—
—
120
100
—
—
°C/W
°C/W
© 2008 Microchip Technology Inc.
DS22088A-page 5
MCP3424
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2.
8
0.0035
TA = +25°C
TA = +25°C
7
0.003
0.0025
0.002
0.0015
0.001
0.0005
0
PGA = 1
6
5
4
3
2
1
0
PGA = 8
PGA = 4
PGA = 2
PGA = 4
PGA = 8
PGA = 2
PGA = 1
2.5
3
3.5
4
4.5
5
5.5
-100 -75
-50
-25
0
25
50
75
100
V
DD (V)
Input Signal (% of FSR)
FIGURE 2-1:
(V ).
INL vs. Supply Voltage
FIGURE 2-4:
Voltage.
Output Noise vs. Input
DD
0.0035
0.003
0.0025
0.002
0.0015
0.001
0.0005
0
2
1.5
1
PGA = 1
TA = +25°C
PGA = 1
PGA = 8
0.5
0
2.7V
PGA = 4
-0.5
-1
PGA = 2
5V
-1.5
-2
5.5V
-60 -40 -20
0
20 40 60 80 100 120 140
-100 -75 -50 -25
0
25
50
75 100
Temperature (oC)
Input Voltage (% of Full-Scale)
FIGURE 2-2:
INL vs. Temperature.
FIGURE 2-5:
Total Error vs. Input Voltage.
0.2
0.1
20
15
10
5
PGA = 8
0
PGA = 8
PGA = 4
PGA = 1
-0.1
-0.2
-0.3
-0.4
-0.5
-0.6
0
-5
-10
-15
-20
PGA = 2
PGA = 2
PGA = 1
PGA = 4
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
FIGURE 2-3:
Offset Error vs.
FIGURE 2-6:
Gain Error vs. Temperature.
Temperature.
DS22088A-page 6
© 2008 Microchip Technology Inc.
MCP3424
Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, CHn+ = CHn- = VREF/2.
200
180
160
140
120
100
80
3
2
Data Rate = 3.75 SPS
VDD = 5.5V
1
0
VDD = 2.7V
VDD = 5.0V
-1
-2
60
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
FIGURE 2-7:
I
vs. Temperature.
FIGURE 2-10:
Oscillator Drift vs.
DDA
Temperature.
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
Data Rate = 3.75 SPS
VDD = 5.5V
VDD = 5.0V
VDD = 2.7V
-120
0.1
10
100
1
1k
10k
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
Input Signal Frequency (Hz)
FIGURE 2-8:
I
vs. Temperature.
FIGURE 2-11:
Frequency Response.
DDS
14
VDD = 5.5V
12
10
8
VDD = 5.0V
VDD = 4.5V
6
4
VDD = 2.7V
2
0
-60 -40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
FIGURE 2-9:
I
vs. Temperature.
DDB
© 2008 Microchip Technology Inc.
DS22088A-page 7
MCP3424
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
Pin No
PIN FUNCTION TABLE
Sym
Function
1
2
3
4
5
6
7
CH1+
CH1-
CH2+
CH2-
VSS
Positive Differential Analog Input Pin of Channel 1
Negative Differential Analog Input Pin of Channel 1
Positive Differential Analog Input Pin of Channel 2
Negative Differential Analog Input Pin of Channel 2
Ground Pin
VDD
Positive Supply Voltage Pin
Bidirectional Serial Data Pin of the I2C Interface
Serial Clock Pin of the I2C Interface
SDA
8
9
SCL
Adr0
Adr1
I2C Address Selection Pin. See Section 5.3.2.
I2C Address Selection Pin. See Section 5.3.2.
Positive Differential Analog Input Pin of Channel 3
Negative Differential Analog Input Pin of Channel 3
Positive Differential Analog Input Pin of Channel 4
Negative Differential Analog Input Pin of Channel 4
10
11
12
13
14
CH3+
CH3-
CH4+
CH4-
This ESD current can cause unexpected performance
of the device. The input voltage at the input pins should
be within the specified operating range defined in
Section 1.0 “Electrical Characteristics” and
Section 4.0 “Description of Device Operation”.
3.1
Analog Inputs (CHn+, CHn-)
CHn+ and CHn- are differential input pins for
channel n. The user can also connect CHn- pin to VSS
for a single-ended operation. See Figure 6-4 for differ-
ential and single-ended connection examples.
See Section 4.5 “Input Voltage Range” for more
The maximum voltage range on each differential input
pin is from VSS-0.3V to VDD+0.3V. Any voltage below or
above this range will cause leakage currents through
the Electrostatic Discharge (ESD) diodes at the input
pins.
details of the input voltage range.
Figure 3-1 shows the input structure of the MCP3424.
The device uses a switched capacitor input stage at the
front end. CPIN is the package pin capacitance and
typically about 4 pF. D1 and D2 are the ESD diodes.
CSAMPLE is the differential input sampling capacitor.
VDD
Sampling
Switch
D1
VT = 0.6V
VT = 0.6V
RS
SS
CHn
RSS
ILEAKAGE
(~ ±1 nA)
CPIN
4 pF
CSAMPLE
(3.2 pF)
V
D2
VSS
LEGEND
V
=
=
=
=
=
Signal Source
ILEAKAGE
SS
=
=
=
=
Leakage Current at Analog Pin
Rss
Source Impedance
Analog Input Pin
Sampling Switch
CHn
CPIN
VT
Rs
CSAMPLE
Sampling Switch Resistor
Sample Capacitance
Input Pin Capacitance
Threshold Voltage
FIGURE 3-1:
MCP3424 Analog Input Model.
DS22088A-page 8
© 2008 Microchip Technology Inc.
MCP3424
3.2
Supply Voltage (VDD, VSS
)
3.4
Serial Data Pin (SDA)
VDD is the power supply pin for the device. This pin
requires an appropriate bypass capacitor of about
0.1 µF (ceramic) to ground. An additional 10 µF
capacitor (tantalum) in parallel is also recommended
to further attenuate high frequency noise present in
SDA is the serial data pin of the I2C interface. The SDA
pin is used for input and output data. In read mode, the
conversion result is read from the SDA pin (output). In
write mode, the device configuration bits are written
(input) though the SDA pin. The SDA pin is an
open-drain N-channel driver. Therefore, it needs a
pull-up resistor from the VDD line to the SDA pin.
Except for start and stop conditions, the data on the
SDA pin must be stable during the high period of the
clock. The high or low state of the SDA pin can only
change when the clock signal on the SCL pin is low.
Refer to Section 5.3 “I2C Serial Communications”
for more details of I2C Serial Interface communication.
some application boards. The supply voltage (VDD
)
must be maintained in the 2.7V to 5.5V range for
specified operation.
VSS is the ground pin and the current return path of the
device. The user must connect the VSS pin to a ground
plane through a low impedance connection. If an
analog ground path is available in the application PCB
(printed circuit board), it is highly recommended that
the VSS pin be tied to the analog ground path or
isolated within an analog ground plane of the circuit
board.
Typical range of the pull-up resistor value for SCL and
SDA is from 5 kΩ to 10 kΩ for standard (100 kHz) and
fast (400 kHz) modes, and less than 1 kΩ for high
speed mode (3.4 MHz).
3.3
Serial Clock Pin (SCL)
SCL is the serial clock pin of the I2C interface. The
MCP3424 acts only as a slave and the SCL pin
accepts only external serial clocks. The input data
from the Master device is shifted into the SDA pin on
the rising edges of the SCL clock and output from the
MCP3424 occurs at the falling edges of the SCL clock.
The SCL pin is an open-drain N-channel driver.
Therefore, it needs a pull-up resistor from the VDD line
to the SCL pin. Refer to Section 5.3 “I2C Serial Com-
munications” for more details of I2C Serial Interface
communication.
© 2008 Microchip Technology Inc.
DS22088A-page 9
MCP3424
The POR circuit is shut-down during the low-power
standby mode. Once a power-up event has occurred,
the device requires additional delay time (approxi-
mately 300 µs) before a conversion takes place. During
this time, all internal analog circuitries are settled
before the first conversion occurs. Figure 4-1 illustrates
the conditions for power-up and power-down events
under typical start-up conditions.
4.0
DESCRIPTION OF DEVICE
OPERATION
4.1
General Overview
The MCP3424 is a 4-channel low-power, 18-Bit
Delta-Sigma A/D converter with an I2C serial interface.
The device contains an input channel selection multi-
plexer (mux), a programmable gain amplifier (PGA), an
on-board voltage reference (2.048V), and an internal
oscillator.
VDD
2.2V
2.0V
300 µS
When the device powers up (POR is set), it automati-
cally resets the configuration bits to default settings.
Device default settings are:
• Conversion bit resolution: 12 bits (240 sps)
• Input channel: Channel 1
• PGA gain setting: x1
Time
Reset Start-up
Normal Operation
Reset
FIGURE 4-1:
POR Operation.
• Continuous conversion
Once the device is powered-up, the user can repro-
gram the configuration bits using I2C serial interface
any time. The configuration bits are stored in volatile
memory.
4.3
Internal Voltage Reference
The device contains an on-board 2.048V voltage
reference. This reference voltage is for internal use
only and not directly measurable. The specification of
the reference voltage is part of the device’s gain and
drift specifications. Therefore, there is no separate
specification for the on-board reference.
User selectable options are:
• Conversion bit resolution: 12, 14, 16, or 18 bits
• Input channel selection: CH1, CH2, CH3, or CH4.
• PGA Gain selection: x1, x2, x4, or x8
• Continuous or one-shot conversion
4.4
Analog Input Channels
In the Continuous Conversion mode, the device
converts the inputs continuously. While in the One-Shot
Conversion mode, the device converts the input one
time and stays in the low-power standby mode until it
receives another command for a new conversion. Dur-
ing the standby mode, the device consumes less than
1 µA maximum.
The user can select the input channel using the config-
uration register bits. Each channel has positive and
negative input pins. Each channel can be used for
differential or single-ended input.
Each input channel has a switched capacitor input
structure. The internal sampling capacitor (3.2 pF for
PGA = 1) is charged and discharged to process a
conversion. The charging and discharging of the input
sampling capacitor creates dynamic input currents at
each input pin. The current is a function of the differen-
tial input voltages, and inversely proportional to the
internal sampling capacitance, frequency, and PGA
setting.
4.2
Power-On-Reset (POR)
The device contains an internal Power-On-Reset
(POR) circuit that monitors power supply voltage (VDD
)
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
The device resets all configuration register bits to
default settings as soon as the POR is set.
The POR has built-in hysteresis and a timer to give a
high degree of immunity to potential ripples and noises
on the power supply. A 0.1 µF decoupling capacitor
should be mounted as close as possible to the VDD pin
for additional transient immunity.
The threshold voltage is set at 2.2V with a tolerance of
approximately ±5%. If the supply voltage falls below
this threshold, the device will be held in a reset
condition. The typical hysteresis value is approximately
200 mV.
DS22088A-page 10
© 2008 Microchip Technology Inc.
MCP3424
4.5
Input Voltage Range
4.6
Input Impedance
The differential (VIN) and common mode voltage
(VINCOM) at the input pins without considering PGA
setting are defined by:
The MCP3424 uses a switched-capacitor input stage
using a 3.2 pF sampling capacitor. This capacitor is
switched (charged and discharged) at a rate of the
sampling frequency that is generated by on-board
clock. The differential input impedance varies with the
PGA settings. The typical differential input impedance
during a normal mode operation is given by:
VIN = (CHn+) – (CHn-)
(CHn+) + (CHn-)
VINCOM = -----------------------------------------------
2
Where:
ZIN(f) = 2.25 MΩ/PGA
n
=
nth input channel (n=1, 2, 3, or 4)
Since the sampling capacitor is only switching to the
input pins during a conversion process, the above input
impedance is only valid during conversion periods. In a
low power standby mode, the above impedance is not
presented at the input pins. Therefore, only a leakage
current due to ESD diode is presented at the input pins.
The input signal levels are amplified by the internal
programmable gain amplifier (PGA) at the front end of
the ΔΣ modulator.
The user needs to consider two conditions for the input
voltage range: (a) Differential input voltage range and
(b) Absolute input voltage range.
The conversion accuracy can be affected by the input
signal source impedance when any external circuit is
connected to the input pins. The source impedance
adds to the internal impedance and directly affects the
time required to charge the internal sampling capacitor.
Therefore, a large input source impedance connected
to the input pins can degrade the system performance,
such as offset, gain, and Integral Non-Linearity (INL)
errors. Ideally, the input source impedance should be
zero. This can be achievable by using an operational
amplifier with a closed-loop output impedance of tens
of ohms.
4.5.1
Differential Input Voltage Range
The device performs conversions using its internal
reference voltage (VREF = 2.048V). Therefore, the
absolute value of the differential input voltage (VIN),
with PGA setting is included, needs to be less than the
internal reference voltage. The device will output satu-
rated output codes (all 0s or all 1s except sign bit ) if the
absolute value of the input voltage (VIN), with PGA
setting is included, is greater than the internal
reference voltage (VREF = 2.048V). The input full-scale
voltage range is given by:
4.7
Aliasing and Anti-aliasing Filter
EQUATION 4-1:
Aliasing occurs when the input signal contains
time-varying signal components with frequency greater
than half the sample rate. In the aliasing conditions, the
device can output unexpected output codes. For
applications that are operating in electrical noise
environments, the time-varying signal noise or high
frequency interference components can be easily
added to the input signals and cause aliasing. Although
the MCP3424 device has an internal first order sinc
filter, its filter response (Figure 2-11) may not give
enough attenuation to all aliasing signal components.
To avoid the aliasing, an external anti-aliasing filter,
which can be accomplished with a simple RC low-pass
filter, is typically used at the input pins. The low-pass
filter cuts off the high frequency noise components and
provides a band-limited input signal to the MCP3424
input pins.
–VREF ≤ (VIN • PGA) ≤ (VREF – 1LSB)
Where:
VIN
=
=
CHn+ - CHn-
2.048V
VREF
If the input voltage level is greater than the above limit,
the user can use a voltage divider and bring down the
input level within the full-scale range. See Figure 6-6
for more details of the input voltage divider circuit.
4.5.2
Absolute Maximum Input Voltage Range:
The input voltage at each input pin must be less than
the following absolute maximum input voltage limits:
• Input voltage < VDD+0.3V
• Input voltage > VSS-0.3V
4.8
Self-Calibration
Any input voltage outside this range can turn on the
input ESD protection diodes, and result in input leak-
age current, causing conversion errors, or permanently
damage the device.
The device performs a self-calibration of offset and
gain for each conversion. This provides reliable
conversion results from conversion-to-conversion over
variations in temperature as well as power supply
fluctuations.
Care must be taken in setting the input voltage ranges
so that the input voltage does not exceed the absolute
maximum input voltage range.
© 2008 Microchip Technology Inc.
DS22088A-page 11
MCP3424
Table 4-1 shows the LSB size of each conversion rate
setting. The measured unknown input voltage is
obtained by multiplying the output codes with LSB. See
the following section for the input voltage calculation
using the output codes.
4.9
Digital Output Code and
Conversion to Real Number
4.9.1
DIGITAL OUTPUT CODE FROM
DEVICE
The digital output code is proportional to the input volt-
age and PGA settings. The output data format is a
binary two’s complement. With this code scheme, the
MSB can be considered a sign indicator. When the
MSB is a logic ‘0’, the input is positive. When the MSB
is a logic ‘1’, the input is negative. The following is an
example of the output code:
TABLE 4-1:
RESOLUTION SETTINGS VS.
LSB
Resolution Setting
12 bits
LSB
1 mV
14 bits
16 bits
18 bits
250 µV
62.5 µV
(a) for a negative full-scale input voltage: 100...000
Example: (CHn+ - CHn-) •PGA = -2.048V
(b) for a zero differential input voltage: 000...000
Example: (CHn+ - CHn-) = 0
15.625 µV
TABLE 4-2:
EXAMPLE OF OUTPUT CODE
FOR 18 BITS
(c) for a positive full-scale input voltage: 011...111
Example: (CHn+ - CHn-) • PGA = 2.048V
Input Voltage:
[CHn+ - CHn-] • PGA
Digital Output Code
The MSB (sign bit) is always transmitted first through
the I2C serial data line. The resolution for each conver-
sion is 18, 16, 14, or 12 bits depending on the conver-
sion rate selection bit settings by the user.
≥ VREF
011111111111111111
011111111111111111
000000000000000010
000000000000000001
000000000000000000
111111111111111111
111111111111111110
100000000000000000
100000000000000000
V
REF - 1 LSB
2 LSB
1 LSB
0
The output codes will not roll-over even if the input volt-
age exceeds the maximum input range. In this case,
the code will be locked at 0111...11for all voltages
greater than (VREF - 1 LSB)/PGA and 1000...00for
voltages less than -VREF/PGA. Table 4-2 shows an
example of output codes of various input levels for 18
bit conversion mode. Table 4-3 shows an example of
minimum and maximum output codes for each conver-
sion rate option.
-1 LSB
-2 LSB
- VREF
< -VREF
Note 1: MSB is a sign indicator:
0: Positive input (CHn+ > CHn-)
1: Negative input (CHn+ < CHn-)
The number of output code is given by:
2: Output data format is binary two’s
complement.
EQUATION 4-2:
Number of Output Code =
TABLE 4-3:
MINIMUM AND MAXIMUM
OUTPUT CODES
(CHn+ – CHn-)
----------------------------------------
= (Maximum Code + 1) × PGA ×
2.048V
Where:
Resolution
Setting
Minimum Maximum
Data Rate
See Table 4-3 for Maximum Code
Code
Code
12
14
16
18
240 SPS
60 SPS
-2048
-8192
2047
8191
The LSB of the data conversion is given by:
15 SPS
-32768
-131072
32767
131071
EQUATION 4-3:
3.75 SPS
2 × VREF
LSB = --------------------- = --------------------------
Maximum n-bit code = 2N-1 - 1
2 × 2.048V
Note:
2N 2N
Minimum n-bit code = -1 x 2N-1
Where:
N
=
Resolution, which is set in the
Configuration Register.
DS22088A-page 12
© 2008 Microchip Technology Inc.
MCP3424
4.9.2
CONVERTING THE DEVICE
OUTPUT CODE TO INPUT SIGNAL
VOLTAGE
EQUATION 4-4:
CONVERTING OUTPUT
CODES TO INPUT
VOLTAGE
When the user gets the digital output codes from the
device as described in Section 4.9.1 “Digital output
code from device”, the next step is converting the
digital output codes to a measured input voltage.
Equation 4-4 shows an example of converting the
output codes to its corresponding input voltage.
If MSB = 0 (Positive Output Code):
Input Voltage = (Output Code) •
LSB
PGA
-----------
If MSB = 1 (Negative Output Code):
LSB
PGA
-----------
•
Input Voltage =
(2′s complement of Output Code)
If the sign indicator bit (MSB) is ‘0’, the input voltage
is obtained by multiplying the output code with the LSB
and divided by the PGA setting.
Where:
LSB
2’s complement
=
=
See Table 4-1
1’s complement + 1
If the sign indicator bit (MSB) is ‘1’, the output code
needs to be converted to two’s complement before
multiplied by LSB and divided by the PGA setting.
Table 4-4 shows an example of converting the device
output codes to input voltage.
TABLE 4-4:
EXAMPLE OF CONVERTING OUTPUT CODE TO VOLTAGE (WITH 18 BIT SETTING)
Input Voltage
[CHn+ - CHn-] • PGA]
Digital Output Code
MSB
Example of Converting Output Codes to Input Voltage
≥ VREF
011111111111111111
(216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+
0
21+20)x LSB(15.625μV)/PGA = 2.048 (V) for PGA = 1
VREF - 1 LSB
2 LSB
011111111111111111
000000000000000010
000000000000000001
000000000000000000
111111111111111111
111111111111111110
100000000000000000
100000000000000000
(216+215+214+213+212+211+210+29+28+27+26+25+24+23+22+
0
0
0
0
1
1
1
1
21+20)x LSB(15.625μV)/PGA = 2.048 (V) for PGA = 1
(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x
LSB(15.625μV)/PGA = 31.25 (μV) for PGA = 1
(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x
LSB(15.625μV)/PGA = 15.625 (μV)for PGA = 1
1 LSB
0
(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0)x
LSB(15.625μV)/PGA = 0 V (V) for PGA = 1
-(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+20)x
LSB(15.625μV)/PGA = - 15.625 (μV)for PGA = 1
-(0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+21+0)x
LSB(15.625μV)/PGA = - 31.25 (μV)for PGA = 1
-(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x
LSB(15.625μV)/PGA = - 2.048 (V) for PGA = 1
-1 LSB
-2 LSB
- VREF
≤ -VREF
-(217+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0+0) x
LSB(15.625μV)/PGA = - 2.048 (V) for PGA = 1
Note 1: See Table 5-3 for more details of digital output codes for each conversion mode.
© 2008 Microchip Technology Inc.
DS22088A-page 13
MCP3424
5.1.2
ONE-SHOT CONVERSION MODE
(O/C BIT = 0)
5.0
5.1
USING THE MCP3424 DEVICE
Operating Modes
Once the One-Shot Conversion (single conversion)
Mode is selected, the device performs only one conver-
sion, updates the output data register, clears the data
ready flag (RDY = 0), and then enters a low power
standby mode. A new One-Shot Conversion is started
again when the device receives a new write command
with RDY = 1.
The user operates the device by setting up the device
configuration register and reads the conversion data
using serial I2C interface commands. The MCP3424
operates in two modes: (a) Continuous Conversion
Mode or (b) One-Shot Conversion Mode (single
conversion). This mode selection is made by setting
the O/C bit in the Configuration Register. Refer to
Section 5.2 “Configuration Register” for more
information.
• When writing configuration register:
- The RDY bit needs to be set to begin a new
conversion in one-shot mode.
• When reading conversion data:
5.1.1
CONTINUOUS CONVERSION
MODE (O/C BIT = 1)
- RDY bit = 0 means the latest conversion
result is ready.
The MCP3424 device performs
a
Continuous
-
means the conversion result is
RDY bit = 1
Conversion if the O/C bit is set to logic “high”. Once the
conversion is completed, RDY bit is toggled to ‘0’and
the result is placed at the output data register. The
device immediately begins another conversion and
overwrites the output data register with the most recent
result. The device clears the data ready flag (RDY
bit = 0) when the conversion is completed. The device
sets the ready flag bit (RDY bit = 1), if the latest
conversion result has been read by the Master.
not updated since the last reading. A new
conversion is under processing and the RDY
bit will be cleared when the new conversion is
done.
This One-Shot Conversion Mode is highly recom-
mended for low power operating applications where the
conversion result is needed by request on demand.
During the low current standby mode, the device con-
sumes less than 1 µA maximum (or 300 nA typical).
For example, if the user collects 18 bit conversion data
once a second in One-Shot Conversion mode, the
device draws only about one fourth of its total operating
current. In this example, the device consumes approx-
imately 36 µA (135 µA / 3.75 SPS = 36 µA), if the
device performs only one conversion per second
(1 SPS) in 18-bit conversion mode with 3V power
supply.
• When writing configuration register:
- Setting RDY bit in continuous mode does not
affect anything.
• When reading conversion data:
- RDY bit = 0 means the latest conversion
result is ready.
- RDY bit = 1 means the conversion result is
not updated since the last reading. A new
conversion is under processing and the RDY
bit will be cleared when the new conversion
result is ready.
DS22088A-page 14
© 2008 Microchip Technology Inc.
MCP3424
The user can rewrite the configuration byte any time
during the device operation. Register 5-1 shows the
configuration register bits.
5.2
Configuration Register
The MCP3424 has an 8-bit wide configuration register
to select for: input channel, conversion mode, conver-
sion rate, and PGA gain. This register allows the user
to change the operating condition of the device and
check the status of the device operation.
REGISTER 5-1:
CONFIGURATION REGISTER
R/W-1
RDY
R/W-0
C1
R/W-0
C0
R/W-1
O/C
1 *
R/W-0
S1
R/W-0
S0
R/W-0
G1
R/W-0
G0
1 *
0 *
0 *
0 *
0 *
0 *
0 *
bit 7
bit 0
* Default Configuration after Power-On Reset
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
RDY: Ready Bit
This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated
with a latest conversion result. In One-Shot Conversion mode, writing this bit to “1” initiates a new
conversion.
Reading RDY bit with the read command:
1= Output register has not been updated.
0= Output register has been updated with the latest conversion result.
Writing RDY bit with the write command:
Continuous Conversion mode: No effect
One-Shot Conversion mode:
1= Initiate a new conversion.
0= No effect.
bit 6-5
C1-C0: Channel Selection Bits
00
01
10
11
=
=
=
=
Select Channel 1 (Default)
Select Channel 2
Select Channel 3
Select Channel 4
bit 4
O/C: Conversion Mode Bit
1= Continuous Conversion Mode (Default). The device performs data conversions continuously.
0= One-Shot Conversion Mode. The device performs a single conversion and enters a low power
standby mode until it receives another write/read command.
bit 3-2
S1-S0: Sample Rate Selection Bit
00
01
10
11
=
=
=
=
240 SPS (12 bits) (Default)
60 SPS (14 bits)
15 SPS (16 bits)
3.75 SPS (18 bits)
bit 1-0
G1-G0: PGA Gain Selection Bits
00
01
10
11
=
=
=
=
x1 (Default)
x2
x4
x8
© 2008 Microchip Technology Inc.
DS22088A-page 15
MCP3424
If the configuration byte is read repeatedly by clocking
continuously after reading the data bytes (i.e., after the
5th byte in the 18-bit conversion mode), the state of the
RDY bit indicates whether the device is ready with new
conversion result. When the Master finds the RDY bit is
cleared, it can send a stop bit to exit the current read
operation and send a new read command for the latest
conversion data. Once the conversion data has been
read, the ready bit toggles to ‘1’ until the next new
conversion data is ready. The conversion data in the
output register is overwritten every time a new conver-
sion is completed.
5.3
I2C Serial Communications
The MCP3424 device communicates with Master
(microcontroller) through a serial I2C (Inter-Integrated
Circuit)
(100 kbits/sec), fast (400 kbits/sec) and high-speed
(3.4 Mbits/sec) modes. The serial I2C is a bidirectional
2-wire data bus communication protocol using
open-drain SCL and SDA lines.
interface
and
supports
standard
The MCP3424 can only be addressed as a slave. Once
addressed, it can receive configuration bits or transmit
the latest conversion results. The serial clock pin (SCL)
is an input only and the serial data pin (SDA) is
bidirectional. An example of a hardware connection
diagram is shown in Figure 6-1.
Figure 5-4 and Figure 5-5 show the examples of
reading the conversion data. The user can rewrite the
configuration byte any time for a new setting. Table 5-1
and Table 5-2 show the examples of the configuration
bit operation.
More details of the I2C bus characteristic is described
in Section 5.6 “I2C Bus Characteristics”.
2
TABLE 5-1:
WRITE CONFIGURATION BITS
Operation
5.3.1
I C DEVICE ADDRESSING
R/W O/C RDY
The Master starts communication by sending a START
bit and terminates the communication by sending a
STOP bit. The first byte after the START bit is always
the address byte of the device, which includes the
device code, address bits, and R/W bit. The device
code for the MCP3424 device is 1101, which is
programmed at the factory. The I2C address bits (A2,
A1, A0) are user programmable and determined by the
logic status of the two external address selection pins
on the user’s application board (Adr0 and Adr1 pins).
The Master must know the Adr0 and Adr1 pin
conditions before sending read or write command.
Figure 5-1 shows the details of the MCP3424 address
byte.
0
0
0
No effect if all other bits remain
the same - operation continues
with the previous settings
0
0
0
0
1
1
1
0
1
Initiate One-Shot Conversion
Initiate Continuous Conversion
Initiate Continuous Conversion
TABLE 5-2:
READ CONFIGURATION BITS
Operation
R/W O/C RDY
1
1
1
1
0
0
1
1
0
1
0
1
New conversion result in
One-Shot conversion mode has
just been read. The RDY bit
remains low until set by a new
write command.
The three address bits allow up to eight MCP3424
devices on the same data bus line. The (R/W) bit
determines if the Master device wants to read the
conversion data or write to the Configuration register. If
the (R/W) bit is set (read mode), the MCP3424 outputs
the conversion data in the following clocks. If the (R/W)
bit is cleared (write mode), the MCP3424 expects a
configuration byte in the following clocks. When the
MCP3424 receives the correct address byte, it outputs
an acknowledge bit after the R/W bit.
One-Shot Conversion is in
progress. The conversion result
is not updated yet. The RDY bit
stays high until the current
conversion is completed.
New conversion result in Contin-
uous Conversion mode has just
been read. The RDY bit changes
to high after reading the conver-
sion data.
Figure 5-1 shows the MCP3424 address byte.
Figure 5-3 through Figure 5-5 show how to write the
configuration register bits and read the conversion
results.
The conversion result in Continu-
ous Conversion mode was
already read. The next new con-
version data is not ready. The
RDY bit stays high until a new
conversion is completed.
DS22088A-page 16
© 2008 Microchip Technology Inc.
MCP3424
It is recommended to issue a General Call Reset or
General Call Latch command once after the device
has powered up. This will ensure that the device reads
the address pins in a stable condition, and avoid latch-
ing the address bits while the power supply is ramping
up. This might cause inaccurate address pin detection.
Acknowledge bit
Read/Write bit
Start bit
R/W ACK
Address
When the address pin is left “floating”:
Address Byte
When the address pin is left “floating”, the address pin
momentarily outputs a short pulse with an amplitude of
about VDD/2 during the latch event. The device also
latches this pin voltage at the same time.
Address
Device Code
Address Bits (Note 1)
A2 A1 A0
If the “floating” pin is connected to a large parasitic
capacitance (>20 pF) or to a long PCB trace, this short
floating voltage output can be altered. As a result, the
device may not latch the pin correctly.
1
1
1
0
Note 1: See Table 5-3 for address bit selection
It is strongly recommended to keep the “floating” pin
pad as short as possible in the customer application
PCB and minimize the parasitic capacitance to the pin
as small as possible (< 20 pF).
FIGURE 5-1:
5.3.2
MCP3424 Address Byte.
DEVICE ADDRESS BITS (A2, A1, A2)
AND ADDRESS SELECTION PINS.
Figure 5-2 shows an example of the Latch voltage out-
put at the address pin when the address pin is left
“floating”. The waveform at the Adr0 pin is captured by
using an oscilloscope probe with 15 pF of capacitance.
The device latches the floating condition immediately
after the General Call Latch command.
The MCP3424 has two external device address pins
(Adr1, Adr0). These pins can be set to a logic high (or
tied to VDD), low (or tied to VSS), or left floating (not
connected to anything, or tied to VDD/2), These combi-
nations of logic level using the two pins allow eight
possible addresses. Table 5-3 shows the device
address depending on the logic status of the address
selection pins.
The device samples the logic status of the Adr0 and
Adr1 pins in the following events:
Float waveform (output)
a
t address pin
(a) Device power-up.
SCL
SDA
(b) General Call Reset
(See Section 5.4 “General Call”).
(c) General Call Latch
(See Section 5.4 “General Call”).
The device samples the logic status (address pins)
during the above events, and latches the values until a
new latch event occurs. During normal operation (after
the address pins are latched), the address pins are
internally disabled from the rests of the internal circuit.
FIGURE 5-2:
Command and Voltage Output at Address Pin
Left “Floating”.
General Call Latch
© 2008 Microchip Technology Inc.
DS22088A-page 17
MCP3424
TABLE 5-3:
ADDRESS BITS VS. ADDRESS
SELECTION PINS
5.3.3
WRITING A CONFIGURATION BYTE
TO THE DEVICE
When the Master sends an address byte with the R/W
bit low (R/W = 0), the MCP3424 expects one
configuration byte following the address. Any byte sent
after this second byte will be ignored. The user can
change the operating mode of the device by writing the
configuration register bits.
I2C Device
Address Bits
Logic Status of Address
Selection Pins
A2
A1
A0
Adr0 Pin
Adr1 Pin
0
0
0
1
1
1
0
1
0
0
0
1
0
0
1
1
1
0
0
1
0
0
1
0
1
1
0
0 (Addr_Low)
0 (Addr_Low)
0 (Addr_Low)
0 (Addr_Low)
Float
If the device receives a write command with a new
configuration setting, the device immediately begins a
new conversion and updates the conversion data.
1 (Addr_High)
1 (Addr_High) 0 (Addr_Low)
1 (Addr_High) Float
1 (Addr_High) 1 (Addr_High)
Float
Float
Float
0 (Addr_Low)
1 (Addr_High)
Float
Note 1: Float: (a) Leave pin without connecting to
anything (left floating), or (b) apply
Addr_Float voltage.
2: The user can tie the pins to VSS or VDD
:
- Tie to VSS for Addr_Low
- Tie to VDD for Addr_High
3: See Addr_Low, Addr_High, and
Addr_Float parameters in Electrical
Characteristics Table.
1
1
9
9
SCL
SDA
1
1
1
A2 A1 A0
R/W
C1 C0
S1 S0 G1 G0
0
Start Bit by
Master
ACK by
MCP3424
Stop Bit by
Master
ACK by
MCP3424
O/C
RDY
(a) One-Shot Mode: 1
(b) Continuous Mode: not effected
1st Byte:
MCP3424 Address Byte
with Write command
2nd Byte:
Configuration Byte
Note:
– Stop bit can be issued any time during writing.
– MCP3424 device code is 1101(programmed at the factory).
– Address Bits A2- A0 are user programmable and determined by the logic status of the two external
address selection pins (Adr1 and Adr0 pins)
FIGURE 5-3:
Timing Diagram For Writing To The MCP3424.
DS22088A-page 18
© 2008 Microchip Technology Inc.
MCP3424
MSB bits and can be ignored. The 5th bit (D11) of the
byte represents the MSB (= sign bit) of the conversion
data. Table 5-3 summarizes the conversion data output
of each conversion mode.
5.3.4
READING OUTPUT CODES AND
CONFIGURATION BYTE FROM THE
DEVICE
When the Master sends a read command (R/W = 1),
the MCP3424 outputs both the conversion data and
configuration bytes. Each byte consists of 8 bits with
one acknowledge (ACK) bit. The ACK bit after the
address byte is issued by the MCP3424 and the ACK
bits after each conversion data bytes are issued by the
Master.
The configuration byte follows the output data bytes.
The device repeatedly outputs the configuration byte
only if the Master sends clocks repeatedly after the
data bytes.
The device terminates the current outputs when it
receives a Not-Acknowledge (NAK), a repeated start or
a stop bit at any time during the output bit stream. It is
not required to read the configuration byte. However,
the Master may read the configuration byte to check
the RDY bit condition.The Master may continuously
send clock (SCL) to repeatedly read the configuration
byte (to check the RDY bit status).
When the device is configured for 18-bit conversion
mode, the device outputs three data bytes followed by
a configuration byte. The first 6 data bits in the first data
byte are repeated MSB (= sign bit) of the conversion
data. The user can ignore the first 6 data bits, and take
the 7th data bit (D17) as the MSB of the conversion
data. The LSB of the 3rd data byte is the LSB of the
conversion data (D0).
Figures 5-4 and 5-5 show the timing diagrams of the
reading.
If the device is configured for 12, 14, or 16 bit-mode, the
device outputs two data bytes followed by
a
configuration byte. In 16 bit-conversion mode, the MSB
(= sign bit) of the first data byte is D15. In 14-bit conver-
sion mode, the first two bits in the first data byte are
repeated MSB bits and can be ignored, and the 3rd bit
(D13) is the MSB (=sign bit) of the conversion data. In
12-bit conversion mode, the first four bits are repeated
TABLE 5-3:
OUTPUT CODES OF EACH RESOLUTION OPTION
Digital Output Codes
Conversion
Option
18-bits
MMMMMMD17D16 (1st data byte) - D15 ~ D8 (2nd data byte) - D7 ~ D0 (3rd data byte) - Configuration
byte. (Note 1)
16-bits
14-bits
12-bits
D15 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 2)
MMD13D ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 3)
MMMMD11 ~ D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte. (Note 4)
Note 1: D17 is MSB (= sign bit), M is repeated MSB of the data byte.
2: D15 is MSB (= sign bit).
3: D13 is MSB (= sign bit), M is repeated MSB of the data byte.
4: D11 is MSB (= sign bit), M is repeated MSB of the data byte.
© 2008 Microchip Technology Inc.
DS22088A-page 19
MCP3424
FIGURE 5-4:
Timing Diagram For Reading From The MCP3424 With 18-Bit Mode.
DS22088A-page 20
© 2008 Microchip Technology Inc.
MCP3424
FIGURE 5-5:
Timing Diagram For Reading From The MCP3424 With 12-Bit to 16-Bit Modes.
© 2008 Microchip Technology Inc.
DS22088A-page 21
MCP3424
5.4
General Call
5.5
High-Speed (HS) Mode
The MCP3424 acknowledges the general call address
(0x00 in the first byte). The meaning of the general call
address is always specified in the second byte. Refer
to Figure 5-6. The MCP3424 supports the following
three general calls.
For more information on the general call, or other I2C
modes, please refer to the Phillips I2C specification.
The I2C specification requires that a high-speed mode
device must be ‘activated’ to operate in high-speed
mode. This is done by sending a special address byte
of “00001XXX” following the START bit. The “XXX”bits
are unique to the High-Speed (HS) mode Master. This
byte is referred to as the High-Speed (HS) Master
Mode Code (HSMMC). The MCP3424 device does not
acknowledge this byte. However, upon receiving this
code, the MCP3424 switches on its HS mode filters
and communicates up to 3.4 MHz on SDA and SCL
bus lines. The device will switch out of the HS mode on
the next STOP condition.
5.4.1
GENERAL CALL RESET
The general call reset occurs if the second byte is
‘00000110’ (06h). At the acknowledgement of this
byte, the device will abort current conversion and
perform the following tasks:
For more information on the HS mode, or other I2C
modes, please refer to the Phillips I2C specification.
(a) Internal reset similar to a Power-On-Reset (POR).
All configuration and data register bits are reset to
default values.
5.6
I2C Bus Characteristics
The I2C specification defines the following bus
protocol:
(b) Latch the logic status of external address selection
pins (Adr0 and Adr1 pins).
• Data transfer may be initiated only when the bus
is not busy
5.4.2
GENERAL CALL LATCH
The general call latch occurs if the second byte is
‘00000100’ (04h). The device will latch the logic status
of the external address selection pins (Adr0 and Adr1
pins), but will not perform a reset.
• During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined using Figure 5-7.
5.4.3
GENERAL CALL CONVERSION
The general call conversion occurs if the second byte
is ‘00001000’ (08h). All devices on the bus initiate a
conversion simultaneously. For the MCP3424 device,
the configuration will be set to the One-Shot Conver-
sion mode and a single conversion will be performed.
The PGA and data rate settings are unchanged with
this general call.
5.6.1
BUS NOT BUSY (A)
Both data and clock lines remain HIGH.
5.6.2
START DATA TRANSFER (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
ACK
ACK
LSB
5.6.3
STOP DATA TRANSFER (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations can be ended with a STOP condition.
0
0 0 0 0 0 0 0
A
x
x x x x x x x A
First Byte
(General Call Address)
Second Byte
5.6.4
DATA VALID (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
Note:
The I2C specification does not allow
“00000000” (00h) in the second byte.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
FIGURE 5-6:
Format.
General Call Address
Each data transfer is initiated with a START condition
and terminated with a STOP condition.
DS22088A-page 22
© 2008 Microchip Technology Inc.
MCP3424
During reads, the Master (microcontroller) can
terminate the current read operation by not providing
an acknowledge bit on the last byte that has been
clocked out from the MCP3424. In this case, the
MCP3424 releases the SDA line to allow the Master
(microcontroller) to generate a STOP or repeated
START condition.
5.6.5
ACKNOWLEDGE
The Master (microcontroller) and the slave (MCP3424)
use an acknowledge pulse as a hand shake of
communication for each byte. The ninth clock pulse of
each byte is used for the acknowledgement. The clock
pulse is always provided by the Master (microcontrol-
ler) and the acknowledgement is issued by the
receiving device of the byte (Note: The transmitting
device must release the SDA line during the acknowl-
edge pulse.). The acknowledgement is achieved by
pulling-down the SDA line “LOW” during the 9th clock
pulse by the receiving device.
(A)
(B)
(D)
(D)
(C) (A)
SCL
SDA
START
STOP
ADDRESS OR
DATA
CONDITION
CONDITION
ACKNOWLEDGE ALLOWED
VALID TO CHANGE
2
FIGURE 5-7:
Data Transfer Sequence on I C Serial Bus.
© 2008 Microchip Technology Inc.
DS22088A-page 23
MCP3424
2
TABLE 5-4:
I C SERIAL TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V,
V
SS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Standard Mode (100 kHz)
Clock frequency
fSCL
0
—
—
—
—
—
—
100
—
kHz
ns
Clock high time
T
4000
4700
—
HIGH
Clock low time
T
—
ns
LOW
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
T
1000
300
—
ns
From VIL to VIH (Note 1)
From VIH to VIL (Note 1)
R
T
—
ns
F
T
T
4000
ns
After this period, the first clock
pulse is generated.
HD:STA
Repeated START condition
setup time
4700
—
—
ns
Only relevant for repeated Start
condition
SU:STA
Data hold time
T
T
0
—
—
—
—
—
3450
—
ns
ns
ns
ns
ns
(Note 3)
HD:DAT
SU:DAT
SU:STO
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
250
4000
0
T
—
T
3750
—
(Note 2, Note 3)
AA
T
4700
Time between START and STOP
conditions.
BUF
Fast Mode (400 kHz)
Clock frequency
T
0
—
—
—
—
—
—
400
—
kHz
ns
SCL
Clock high time
T
600
HIGH
Clock low time
T
1300
—
ns
LOW
SDA and SCL rise time
SDA and SCL fall time
START condition hold time
T
20 + 0.1Cb
20 + 0.1Cb
600
300
300
—
ns
From VIL to VIH (Note 1)
From VIH to VIL (Note 1)
R
T
ns
F
T
T
ns
After this period, the first clock
pulse is generated
HD:STA
Repeated START condition
setup time
600
—
—
ns
Only relevant for repeated Start
condition
SU:STA
Data hold time
T
T
0
100
600
0
—
—
—
—
—
900
—
ns
ns
ns
ns
ns
(Note 4)
HD:DAT
SU:DAT
SU:STO
Data input setup time
STOP condition setup time
Output valid from clock
Bus free time
T
—
T
1200
—
(Note 2, Note 3)
AA
T
1300
Time between START and STOP
conditions.
BUF
Input filter spike suppression
T
0
—
50
ns
SDA and SCL pins (Note 5)
SP
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (T
)
HD:DAT
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.
DS22088A-page 24
© 2008 Microchip Technology Inc.
MCP3424
2
TABLE 5-4:
I C SERIAL TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V to +5.0V,
V
SS = 0V, CHn+ = CHn- = VREF/2.
Parameters
Sym
Min
Typ
Max
Units
Conditions
High Speed Mode (3.4 MHz)
Clock frequency
fSCL
0
—
—
—
—
—
—
—
3.4
1.7
—
MHz
MHz
ns
Cb = 100 pF
Cb = 400 pF
0
Clock high time
Clock low time
T
60
Cb = 100 pF, fSCL = 3.4 MHz
Cb = 400 pF, fSCL = 1.7 MHz
Cb = 100 pF, fSCL = 3.4 MHz
Cb = 400 pF, fSCL = 1.7 MHz
HIGH
120
160
320
—
—
ns
T
—
ns
LOW
—
ns
SCL rise time
(Note 1)
T
40
ns
From VIL to VIH
Cb = 100 pF, fSCL = 3.4 MHz
From VIL to VIH
,
R
—
—
—
—
—
—
—
—
—
—
—
—
—
—
80
40
ns
ns
ns
ns
ns
ns
ns
,
Cb = 400 pF, fSCL = 1.7 MHz
SCL fall time
(Note 1)
T
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
F
80
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
SDA rise time
(Note 1)
T
80
From VIL to VIH
Cb = 100 pF, fSCL = 3.4 MHz
From VIL to VIH
,
R: DAT
160
80
,
Cb = 400 pF, fSCL = 1.7 MHz
SDA fall time
(Note 1)
T
T
From VIH to VIL,
Cb = 100 pF, fSCL = 3.4 MHz
F: DATA
160
From VIH to VIL,
Cb = 400 pF, fSCL = 1.7 MHz
Data hold time
(Note 4)
0
0
—
—
—
—
—
70
150
150
310
—
ns
ns
ns
ns
ns
Cb = 100 pF, fSCL = 3.4 MHz
Cb = 400 pF, fSCL = 1.7 MHz
Cb = 100 pF, fSCL = 3.4 MHz
Cb = 400 pF, fSCL = 1.7 MHz
HD:DAT
Output valid from clock
(Notes 2 and 3)
T
—
—
160
AA
START condition hold time
T
After this period, the first clock
pulse is generated
HD:STA
Repeated START condition
setup time
TSU:STA
160
—
—
ns
Only relevant for repeated Start
condition
Data input setup time
T
10
160
0
—
—
—
—
—
10
ns
ns
ns
SU:DAT
T
SU:STO
STOP condition setup time
Input filter spike suppression
T
SDA and SCL pins (Note 5)
SP
Note 1: This parameter is ensured by characterization and not 100% tested.
2: This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (T
)
HD:DAT
plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR).
3: If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this
parameter is too long, Clock Low time (TLOW) can be affected.
4: For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or
Clock Low time (TLOW) can be affected.
For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter.
5: This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode.
© 2008 Microchip Technology Inc.
DS22088A-page 25
MCP3424
TF
TR
THIGH
TSU:STA
SCL
SDA
TSU:STO
TBUF
TSU:DAT
TLOW
THD:STA
THD:DAT
0.7VDD
0.3VDD
TSP
TAA
2
FIGURE 5-8:
I C Bus Timing Data.
DS22088A-page 26
© 2008 Microchip Technology Inc.
MCP3424
2
6.1.3
I C ADDRESS SELECTION PINS
6.0
BASIC APPLICATION
CONFIGURATION
The user can tie the Adr0 and Adr1 pins to VSS, VDD
,
or left floating. See more details in Section 5.3.2
“Device Address Bits (A2, A1, A2) and Address
Selection Pins.”
The MCP3424 device can be used for various precision
analog-to-digital converter applications. The device
operates with very simple connections to the
application circuit. The following sections discuss the
examples of the device connections and applications.
MCP3424
Input
Input
Signal 1
1
2
3
4
5
6
7
CH1+
CH1-
CH4- 14
Signal 4
6.1
Connecting to the Application
Circuits
13
12
CH4+
CH3-
Input
Input
CH2+
CH2-
Signal 3
Signal 2
11
CH3+
2
V
6.1.1
BYPASS CAPACITORS ON V PIN
I C Address
Selection
Pins
Adr1 10
SS
DD
V
9
DD
Adr0
For an accurate measurement, the application circuit
needs a clean supply voltage and must block any noise
signal to the MCP3424 device. Figure 6-1 shows an
example of using two bypass capacitors (a 10 µF
tantalum capacitor and a 0.1 µF ceramic capacitor) on
the VDD line. These capacitors are helpful to filter out
any high frequency noises on the VDD line and also
provide the momentary bursts of extra currents when
the device needs from the supply. These capacitors
should be placed as close to the VDD pin as possible
(within one inch). If the application circuit has separate
digital and analog power supplies, the VDD and VSS of
the MCP3424 device should reside on the analog
plane.
C
1
SDA
8
SCL
C
2
TO MCU
(MASTER)
RP
RP
V
DD
Rp is the pull-up resistor:
5 kΩ - 10 kΩ for fSCL
~700Ω for fSCL
=
100 kHz to 400 kHz
3.45 MHz
=
2
C1: 0.1 µF, Ceramic capacitor
C2: 10 µF, Tantalum capacitor
6.1.2
CONNECTING TO I C BUS USING
PULL-UP RESISTORS
The SCL and SDA pins of the MCP3424 are open-drain
configurations. These pins require a pull-up resistor as
shown in Figure 6-1. The value of these pull-up
resistors depends on the operating speed (standard,
fast, and high speed) and loading capacitance of the
I2C bus line. Higher value of pull-up resistor consumes
less power, but increases the signal transition time
(higher RC time constant) on the bus. Therefore, it can
limit the bus operating speed. The lower value of
resistor, on the other hand, consumes higher power,
but allows higher operating speed. If the bus line has
higher capacitance due to long bus line or high number
of devices connected to the bus, a smaller pull-up
resistor is needed to compensate the long RC time
constant. The pull-up resistor is typically chosen
between 5 kΩ and 10 kΩ ranges for standard and fast
modes, and less than 1 kΩ for high speed mode
depending on the presence of bus loading capacitance.
FIGURE 6-1:
Typical Connection.
Figure 6-2 shows an example of multiple device con-
nections. The I2C bus loading capacitance increases
as the number of device connected to the I2C bus line
increases. The bus loading capacitance affects on the
bus operating speed. For example, the highest bus
operating speed for the 400 pF bus capacitance is
1.7 MHz, and 3.4 MHz for 100 pF. Therefore, the user
needs to consider the releationship between the maxi-
mum operation speed versus. the number of I2C
devices that are connected to the I2C bus line.
SDA SCL
Microcontroller
(PIC16F876)
EEPROM
(24LC01)
MCP3424
MCP4725
FIGURE 6-2:
Connection on I C Bus.
Example of Multiple Device
2
© 2008 Microchip Technology Inc.
DS22088A-page 27
MCP3424
6.1.4
DEVICE CONNECTION TEST
6.1.5
DIFFERENTIAL AND
SINGLE-ENDED CONFIGURATION
The user can test the presence of the MCP3424 on the
I2C bus line without performing an input data conver-
sion. This test can be achieved by checking an
acknowledge response from the MCP3424 after send-
ing a read or write command. Here is an example using
Figure 6-3:
Figure 6-4 shows typical connection examples for dif-
ferential and single-ended inputs. Differential input sig-
nals can be connected to the CHn+ and CHn- input
pins, where n = the channel number (1, 2, 3, or 4). For
the single-ended input, the input signal is applied to one
of the input pins (typically connected to the CHn+ pin)
while the other input pin (typically CHn- pin) is
grounded. All device characteristics hold for the
single-ended configuration, but this configuration loses
one bit resolution because the input can only stand in
positive half scale. Refer to Section 1.0 “Electrical
a. Set the R/W bit “HIGH” in the address byte.
b. Check the ACK pulse after sending the
address byte.
If the device acknowledges (ACK = 0), then the
device is connected, otherwise it is not
connected.
Characteristics”
.
c. Send STOP or START bit.
(a) Differential Input Signal Connection:
Excitation
Address Byte
Sensor
SCL
SDA
1
1
2
1
3
0
4
5
6
7
8
1
9
CHn+
Input Signal
CHn-
1 A2 A1 A0
MCP3424
Start
Bit
Stop
Bit
Address bits
Device bits
(b) Single-ended Input Signal Connection:
R/W
Excitation
MCP3424
Response
R1
CHn+
2
FIGURE 6-3:
I C Bus Connection Test.
Input Signal
Sensor
R2
CHn-
MCP3424
FIGURE 6-4:
Differential and
Single-Ended Input Connections.
DS22088A-page 28
© 2008 Microchip Technology Inc.
MCP3424
Figure 6-5, shows an example of using the MCP3424
for multi-channel thermocouple temperature measure-
ment applications.
6.2
Application Examples
The MCP3424 device can be used for broad ranges of
sensor and data acquisition applications.
Thermocouple Sensor
Isothermal Block
Isothermal Block
MCP9800
MCP3424
MCP9800
1
2
CH1+
CH1-
14
13
12
11
CH4-
SDA
SCL
SDA
CH4+
CH3-
SCL
3 CH2+
CH2-
4
CH3+
Adr1
Adr0
SCL
5 VSS
10
9
8
VDD
0.1 µF
10 µF
VDD
6
7
SDA
MCP9800
MCP9800
SDA
Heat
SCL
SCL
SDA
SCL
TO MCU
SDA
(MASTER)
5 kΩ
5 kΩ
VDD
FIGURE 6-5:
Multichannel Thermocouple Applications.
With Type K thermocouple, it can measure tempera-
ture from 0°C to 1250°C degrees. The full scale output
range of the Type K thermocouple is about 50 mV. This
provides 40 µV/°C (= 50 mV/1250°C) of measurement
resolution. Equation 6-1 shows the measurement bud-
get for sensor signal using the MCP3424 device with
18 bits and PGA = 8 settings. With this configuration,
the MCP3424 device can detect the input signal level
as low as approximately 2 µV. The internal PGA boosts
the input signal level eight times. The 40 µV/°C input
from the thermocouple is amplified internally to
320 µV/°C before the conversion takes place. This
results in 20.48 LSB/°C output codes. This means
there are about 20 LSB output codes (or about 4.32
bits) per 1°C of change in temperature.
EQUATION 6-1:
Detectable Input Signal Level = 15.625μV/PGA
= 1.953125μV for PGA = 8
Input Signal Level after gain of 8:
= (40μV/°C) • 8 = 320μV/°C
320μV/°C
15.625μV
No. of LSB/°C = ------------------------ = 20.48 Bits/°C
Where:
1 LSB
=
15.625 µV with 18 bit configuration
© 2008 Microchip Technology Inc.
DS22088A-page 29
MCP3424
Equation 6-2 shows an example of calculating the
expected number of output code with various PGA gain
settings for Type K thermocouple output.
EQUATION 6-2:
EXPECTED NUMBER OF
OUTPUT CODE FOR TYPE
K THERMOCOUPLE
Expected
Number of Output Code =
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
50 mV
------------------------
log2
15.625μV
-----------------------
PGA
= 11.6 bits for PGA = 1
= 12.6 bits for PGA = 2
= 13.6 bits for PGA = 4
= 14.6 bits for PGA = 8
Where:
1 LSB
=
15.625 µV with 18 Bit configuration.
VDD
VDD
Pressure Sensor
(NPP301)
Pressure Sensor
(NPP301)
MCP3424
1
2
CH1+
CH1-
14
CH4-
13
12
CH4+
CH3-
VDD
3 CH2+
CH2-
VSS
VDD
SDA
11
10
4
5
6
VDD
CH3+
Adr1
VDD
R1
9
8
Adr0
SCL
0.1 µF
7
R1
R2
R2
Thermistor
10 µF
TO MCU
(MASTER)
Thermistor
5 kΩ
5 kΩ
VDD
for CH2+ and CH3+ pins.
R2
VIN = ------------------
R1 + R2
R1 and R2 = Voltage Divider
FIGURE 6-6:
Example of Pressure and Temperature Measurement.
Figure 6-6 shows an example of measuring both
pressure and temperature. The pressure is measured
by using NPP 301 (manufactured by GE NovaSensor),
and temperature is measured by a thermistor. The
pressure sensor output is 20 mV/V. This gives 100 mV
of full scale output for VDD of 5V (sensor excitation volt-
age). Equation 6-3 shows an example of calculating
the number of output code for the full scale output of the
NPP301.
DS22088A-page 30
© 2008 Microchip Technology Inc.
MCP3424
EQUATION 6-3:
EXPECTED NUMBER OF
OUTPUT CODE FOR
NPP301 PRESSURE
SENSOR
⎛
⎜
⎜
⎝
⎞
⎟
⎟
⎠
Expected
Number of Output Code =
100 mV
------------------------
log2
15.625μV
-----------------------
PGA
= 12.64 bits for PGA = 1
= 13.64 bits for PGA = 2
= 14.64 bits for PGA = 4
= 15.64 bits for PGA = 8
Where:
1 LSB
=
15.625 µV with 18 Bit configuration.
The thermistor temperature sensor can measure the
temperature range from -100°C to 300°C. The resis-
tance of the thermistor sensor decreases as tempera-
ture increases (negative temperature coefficient). As
shown in Figure 6-6, the thermistor (R2) forms a
voltage divider with R1.
The thermistor sensor is simple to use and widely used
for the temperature measurement applications. It has
both linear and non-linear responses over temperature
range. R1 is used to adjust the linear region of interest
for measurement.
© 2008 Microchip Technology Inc.
DS22088A-page 31
MCP3424
7.0
DEVELOPMENT TOOL
SUPPORT
USB Cable
to PC
7.1
MCP3424 Evaluation Board
The MCP3424 Evaluation Board is available from
Microchip Technology Inc. This board works with Micro-
chip’s PICkit™ Serial Analyzer. The user can connect
any sensing voltage to the input pins and read conver-
sion codes using the easy-to-use PICkit™ Serial Ana-
lyzer. Refer to www.microchip.com for further
information on this product’s capabilities and availabil-
ity.
PICkit
Serial
Analog
Input
MCP3424 Evaluation Board
Setup for the MCP3424
FIGURE 7-2:
FIGURE 7-1:
MCP3424 Evaluation Board.
Evaluation Board with PICkit™ Serial Analyzer.
FIGURE 7-3:
Example of PICkit™ Serial User Interface.
DS22088A-page 32
© 2008 Microchip Technology Inc.
MCP3424
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
14-Lead SOIC (150 mil)
Example:
MCP3424
E/SL
XXXXXXXXXXX
XXXXXXXXXXX
e
3
YYWWNNN
0816256
14-Lead TSSOP (4.4 mm)
Example:
XXXXXXXX
YYWW
MCP3424E
0816
NNN
256
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e
3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2008 Microchip Technology Inc.
DS22088A-page 33
MCP3424
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢎꢏꢅꢉꢉꢇꢐꢑꢋꢉꢌꢒꢄꢇꢓꢎꢃꢔꢇMꢇꢕꢅꢖꢖꢗꢘꢙꢇꢚꢛꢜ ꢇꢏꢏꢇ!ꢗꢆ"ꢇ#ꢎꢐ$%&
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4ꢈꢑꢔꢌꢐꢅꢕꢎꢅꢂꢃꢄꢇ
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ꢀꢁꢙ7ꢅ*ꢚꢜ
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ꢚꢏꢉꢄꢋꢕꢎꢎꢅꢅ"
(
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$ꢕꢊꢋꢅ!ꢐꢉꢎꢏꢅ(ꢄꢛꢊꢌꢅ*ꢕꢏꢏꢕꢑ
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ꢙꢁ "ꢅꢚꢃꢛꢄꢃꢎꢃꢖꢉꢄꢏꢅꢜꢘꢉꢐꢉꢖꢏꢌꢐꢃꢇꢏꢃꢖꢁ
ꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅ!ꢅꢉꢄꢋꢅꢝꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅ#ꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅ$ꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅ#ꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅ%ꢁꢀ&ꢅꢑꢑꢅ#ꢌꢐꢅꢇꢃꢋꢌꢁ
'ꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢛꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢛꢅ#ꢌꢐꢅ(ꢚ$ꢝꢅ)ꢀ'ꢁ&$ꢁ
*ꢚꢜ+ *ꢉꢇꢃꢖꢅ!ꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅ,ꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
-ꢝ.+ -ꢌꢎꢌꢐꢌꢄꢖꢌꢅ!ꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅ#ꢈꢐ#ꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
$ꢃꢖꢐꢕꢖꢘꢃ# ,ꢌꢖꢘꢄꢕꢊꢕꢛꢒ !ꢐꢉꢗꢃꢄꢛ ꢜ%'A%;&*
DS22088A-page 34
© 2008 Microchip Technology Inc.
MCP3424
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇ()ꢌꢒꢇꢎ)ꢖꢌꢒ*ꢇꢎꢏꢅꢉꢉꢇꢐꢑꢋꢉꢌꢒꢄꢇꢓꢎ(ꢔꢇMꢇꢁꢛꢁꢇꢏꢏꢇ!ꢗꢆ"ꢇ#(ꢎꢎꢐꢈ&
ꢕꢗꢋꢄ' .ꢕꢐꢅꢏꢘꢌꢅꢑꢕꢇꢏꢅꢖꢈꢐꢐꢌꢄꢏꢅ#ꢉꢖ/ꢉꢛꢌꢅꢋꢐꢉꢗꢃꢄꢛꢇꢓꢅ#ꢊꢌꢉꢇꢌꢅꢇꢌꢌꢅꢏꢘꢌꢅ$ꢃꢖꢐꢕꢖꢘꢃ#ꢅꢂꢉꢖ/ꢉꢛꢃꢄꢛꢅꢚ#ꢌꢖꢃꢎꢃꢖꢉꢏꢃꢕꢄꢅꢊꢕꢖꢉꢏꢌꢋꢅꢉꢏꢅ
ꢘꢏꢏ#+00ꢗꢗꢗꢁꢑꢃꢖꢐꢕꢖꢘꢃ#ꢁꢖꢕꢑ0#ꢉꢖ/ꢉꢛꢃꢄꢛ
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ꢙꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅ!ꢅꢉꢄꢋꢅꢝꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅ#ꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅ$ꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅ#ꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅ%ꢁꢀ&ꢅꢑꢑꢅ#ꢌꢐꢅꢇꢃꢋꢌꢁ
ꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢃꢄꢛꢅꢉꢄꢋꢅꢏꢕꢊꢌꢐꢉꢄꢖꢃꢄꢛꢅ#ꢌꢐꢅ(ꢚ$ꢝꢅ)ꢀ'ꢁ&$ꢁ
*ꢚꢜ+ *ꢉꢇꢃꢖꢅ!ꢃꢑꢌꢄꢇꢃꢕꢄꢁꢅ,ꢘꢌꢕꢐꢌꢏꢃꢖꢉꢊꢊꢒꢅꢌꢍꢉꢖꢏꢅꢆꢉꢊꢈꢌꢅꢇꢘꢕꢗꢄꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢇꢁ
-ꢝ.+ -ꢌꢎꢌꢐꢌꢄꢖꢌꢅ!ꢃꢑꢌꢄꢇꢃꢕꢄꢓꢅꢈꢇꢈꢉꢊꢊꢒꢅꢗꢃꢏꢘꢕꢈꢏꢅꢏꢕꢊꢌꢐꢉꢄꢖꢌꢓꢅꢎꢕꢐꢅꢃꢄꢎꢕꢐꢑꢉꢏꢃꢕꢄꢅ#ꢈꢐ#ꢕꢇꢌꢇꢅꢕꢄꢊꢒꢁ
$ꢃꢖꢐꢕꢖꢘꢃ# ,ꢌꢖꢘꢄꢕꢊꢕꢛꢒ !ꢐꢉꢗꢃꢄꢛ ꢜ%'A%=7*
© 2008 Microchip Technology Inc.
DS22088A-page 35
MCP3424
NOTES:
DS22088A-page 36
© 2008 Microchip Technology Inc.
MCP3424
APPENDIX A: REVISION HISTORY
Revision A (June 2008)
• Original Release of this Document.
© 2008 Microchip Technology Inc.
DS22088A-page 39
MCP3424
NOTES:
DS22088A-page 40
© 2008 Microchip Technology Inc.
MCP3424
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
-X
/XX
Examples:
Temperature Package
Range
a)
MC3424-E/SL:
4-Channel ADC,
14LD SOIC package.
b)
MC3424T-E/SL: Tape and Reel,
4-Channel ADC,
14LD SOIC package.
Device:
MC3424:
MC3424T:
4-Channel 18-Bit ADC
4-Channel 18-Bit ADC
(Tape and Reel)
c)
d)
MC3424-E/ST:
4-Channel ADC,
14LD TSSOP package.
MC3424T-E/ST: Tape and Reel,
4-Channel ADC,
Temperature Range:
Package:
E
=
-40°C to +125°C
14LD TSSOP package.
SL
ST
=
=
Plastic SOIC (150 mil Body), 14-lead
Plastic TSSOP (4.4mm Body), 14-lead
© 2007 Microchip Technology Inc.
DS22088A-page 41
MCP3424
NOTES:
DS22088A-page 42
© 2007 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEVAL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2008 Microchip Technology Inc.
DS22088A-page 43
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
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Tel: 33-1-69-53-63-20
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India - Pune
Tel: 91-20-2566-1512
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Japan - Yokohama
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Fax: 886-3-572-6459
Los Angeles
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Tel: 949-462-9523
Fax: 949-462-9608
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
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Fax: 886-7-536-4803
Santa Clara
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China - Xiamen
Tel: 86-592-2388138
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Taiwan - Taipei
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Fax: 886-2-2508-0102
Toronto
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Canada
Tel: 905-673-0699
Fax: 905-673-6509
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
01/02/08
DS22088A-page 44
© 2008 Microchip Technology Inc.
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