MCP1727T-5002ESN [MICROCHIP]

1.5A, Low Voltage, Low Quiescent Current LDO Regulator;
MCP1727T-5002ESN
型号: MCP1727T-5002ESN
厂家: MICROCHIP    MICROCHIP
描述:

1.5A, Low Voltage, Low Quiescent Current LDO Regulator

文件: 总32页 (文件大小:705K)
中文:  中文翻译
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MCP1727  
1.5A, Low Voltage, Low Quiescent Current LDO Regulator  
Features  
Description  
• 1.5A Output Current Capability  
The MCP1727 is a 1.5A Low Dropout (LDO) linear  
regulator that provides high current and low output  
voltages in a very small package. The MCP1727  
comes in a fixed (or adjustable) output voltage version,  
with an output voltage range of 0.8V to 5.0V. The 1.5A  
output current capability, combined with the low output  
voltage capability, make the MCP1727 a good choice  
for new sub-1.8V output voltage LDO applications that  
have high current demands.  
• Input Operating Voltage Range: 2.3V to 6.0V  
• Adjustable Output Voltage Range: 0.8V to 5.0V  
• Standard Fixed Output Voltages:  
- 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V  
• Other Fixed Output Voltage Options Available  
Upon Request  
• Low Dropout Voltage: 330 mV Typical at 1.5A  
• Typical Output Voltage Tolerance: 0.5%  
• Stable with 1.0 µF Ceramic Output Capacitor  
• Fast response to Load Transients  
The MCP1727 is stable using ceramic output  
capacitors that inherently provide lower output noise  
and reduce the size and cost of the entire regulator  
solution. Only 1 µF of output capacitance is needed to  
stabilize the LDO.  
• Low Supply Current: 120 µA (typ)  
• Low Shutdown Supply Current: 0.1 µA (typ)  
• Adjustable Delay on Power Good Output  
Using CMOS construction, the quiescent current  
consumed by the MCP1727 is typically less than  
120 µA over the entire input voltage range, making it  
attractive for portable computing applications that  
demand high output current. When shut down, the  
quiescent current is reduced to less than 0.1 µA.  
• Short Circuit Current Limiting and  
Overtemperature Protection  
• 3x3 DFN-8 and SOIC-8 Package Options  
Applications  
The scaled-down output voltage is internally monitored  
and a power good (PWRGD) output is provided when  
the output is within 92% of regulation (typical). An  
external capacitor can be used on the CDELAY pin to  
adjust the delay from 200 µs to 300 ms.  
• High-Speed Driver Chipset Power  
• Networking Backplane Cards  
• Notebook Computers  
• Network Interface Cards  
• Palmtop Computers  
The overtemperature and short circuit current-limiting  
provide additional protection for the LDO during system  
fault conditions.  
• 2.5V to 1.XV Regulators  
Package Types  
Adjustable (SOIC-8)  
Fixed (SOIC-8)  
Adjustable (3x3 DFN)  
Fixed (3x3 DFN)  
V
V
8
7
6
5
V
OUT  
V
V
IN  
IN  
1
2
V
1
2
3
4
8
7
6
5
V
IN  
IN  
V
V
V
1
2
3
4
V
OUT  
OUT  
1
2
3
4
8
7
6
5
IN  
IN  
8
7
6
5
IN  
OUT  
ADJ  
C
Sense  
V
Sense  
ADJ  
IN  
3
4
SHDN  
GND  
C
DELAY  
SHDN  
GND  
DELAY  
C
SHDN  
GND  
SHDN  
GND  
C
DELAY  
DELAY  
PWRGD  
PWRGD  
PWRGD  
PWRGD  
© 2007 Microchip Technology Inc.  
DS21999B-page 1  
MCP1727  
Typical Application  
MCP1727 Fixed Output Voltage  
VOUT = 1.8V @ 1A  
VIN = 2.3V to 2.8V  
1
2
3
4
VOUT  
8
VIN  
VIN  
Sense 7  
C1  
4.7 µF  
C2  
1 µF  
SHDN CDELAY  
6
R1  
100 kΩ  
GND PWRGD 5  
C3  
On  
1000 pF  
Off  
PWRGD  
MCP1727 Adjustable Output Voltage  
VOUT = 1.2V @ 1A  
VIN = 2.3V to 2.8V  
1
2
3
4
VOUT  
ADJ  
8
7
6
VIN  
VIN  
R1  
40 kΩ  
C1  
4.7 µF  
C2  
1 µF  
SHDN CDELAY  
R3  
100 kΩ  
GND PWRGD 5  
On  
R2  
20 kΩ  
C3  
1000 pF  
Off  
PWRGD  
DS21999B-page 2  
© 2007 Microchip Technology Inc.  
MCP1727  
Functional Block Diagram - Adjustable Output  
PMOS  
VIN  
VOUT  
Undervoltage  
Lock Out  
(UVLO)  
ISNS  
Cf  
Rf  
SHDN  
ADJ  
+
Driver w/limit  
and SHDN  
EA  
Overtemperature  
Sensing  
SHDN  
VREF  
V
IN  
Reference  
SHDN  
Soft-Start  
PWRGD  
TDELAY  
Comp  
GND  
92% of VREF  
CDELAY  
© 2007 Microchip Technology Inc.  
DS21999B-page 3  
MCP1727  
Functional Block Diagram - Fixed Output  
PMOS  
VIN  
VOUT  
Undervoltage  
Lock Out  
(UVLO)  
ISNS  
Cf  
Rf  
SHDN  
Sense  
+
Driver w/limit  
and SHDN  
EA  
Overtemperature  
Sensing  
SHDN  
VREF  
V
IN  
Reference  
SHDN  
Soft-Start  
PWRGD  
CDELAY  
Comp  
TDELAY  
GND  
92% of VREF  
DS21999B-page 4  
© 2007 Microchip Technology Inc.  
MCP1727  
† Notice: Stresses above those listed under “Maximum Rat-  
ings” may cause permanent damage to the device. This is a  
stress rating only and functional operation of the device at  
those or any other conditions above those indicated in the  
operational listings of this specification is not implied. Expo-  
sure to maximum rating conditions for extended periods may  
affect device reliability.  
1.0  
ELECTRICAL  
CHARACTERISTICS  
Absolute Maximum Ratings †  
VIN....................................................................................6.5V  
Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V  
Maximum Power Dissipation......... Internally-Limited (Note 6)  
Output Short Circuit Duration................................Continuous  
Storage temperature .....................................-65°C to +150°C  
Maximum Junction Temperature, TJ ...........................+150°C  
ESD protection on all pins (HBM/MM) ........... ≥ 2 kV; 200V  
AC/DC CHARACTERISTICS  
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR=1.8V for Adjustable Output,  
OUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.  
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C  
I
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Input Operating Voltage  
Input Quiescent Current  
VIN  
Iq  
2.3  
6.0  
V
Note 1  
IL = 0 mA, VIN = Note 1,  
OUT = 0.8V to 5.0V  
120  
0.1  
220  
µA  
V
Input Quiescent Current for  
SHDN Mode  
ISHDN  
IOUT  
1.5  
3
µA  
A
SHDN = GND  
Maximum Output Current  
VIN = 2.3V to 6.0V  
V
R = 0.8V to 5.0V, Note 1  
Line Regulation  
ΔVOUT  
(VOUT x ΔVIN  
/
0.05  
±0.5  
2.2  
0.16  
1.0  
%/V  
%
(Note 1) VIN 6V  
)
Load Regulation  
ΔVOUT/VOUT  
-1.0  
IOUT = 1 mA to 1.5A,  
V
IN = Note 1, (Note 4)  
Output Short Circuit Current  
IOUT_SC  
A
VIN = Note 1, RLOAD < 0.1Ω,  
Peak Current  
Adjust Pin Characteristics (Adjustable Output Only)  
Adjust Pin Reference Voltage  
VADJ  
0.402  
0.410  
0.418  
V
VIN = 2.3V to VIN = 6.0V,  
I
OUT = 1 mA  
Adjust Pin Leakage Current  
IADJ  
-10  
±0.01  
40  
+10  
nA  
VIN = 6.0V, VADJ = 0V to 6V  
Adjust Temperature Coefficient  
TCVOUT  
ppm/°C Note 3  
Fixed-Output Characteristics (Fixed Output Only)  
Voltage Regulation VOUT  
VR - 2.5%  
VR  
VR + 2.5%  
V
Note 2  
±0.5%  
Note 1: The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX).  
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output  
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.  
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the  
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.  
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is  
tested over a load range from 1 mA to the maximum specified output current.  
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its  
nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX)  
.
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction  
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power  
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained  
junction temperatures above 150°C can impact device reliability.  
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the  
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the  
ambient temperature is not significant.  
© 2007 Microchip Technology Inc.  
DS21999B-page 5  
MCP1727  
AC/DC CHARACTERISTICS (CONTINUED)  
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR=1.8V for Adjustable Output,  
I
OUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.  
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C  
Parameters  
Sym  
Min  
Typ  
Max  
550  
Units  
Conditions  
Dropout Characteristics  
Dropout Voltage  
V
IN-VOUT  
330  
mV  
Note 5, IOUT = 1.5A,  
V
IN(MIN) = 2.3V  
Power Good Characteristics  
PWRGD Input Voltage Operat-  
ing Range  
VPWRGD_VIN  
1.0  
6.0  
V
TA = +25°C  
1.2  
6.0  
TA = -40°C to +125°C  
For VIN < 2.3V, ISINK = 100 µA  
PWRGD Threshold Voltage  
VPWRGD_TH  
89  
90  
1.0  
92  
95  
%VOUT Falling Edge  
VOUT < 2.5V Fixed, VOUT = Adj.  
(Referenced to VOUT  
)
92  
94  
VOUT >= 2.5V Fixed  
PWRGD Threshold Hysteresis  
PWRGD Output Voltage Low  
VPWRGD_HYS  
VPWRGD_L  
2.0  
0.2  
3.0  
0.4  
%VOUT  
V
IPWRGD SINK = 1.2 mA,  
ADJ = 0V, SENSE = 0V  
PWRGD Leakage  
PWRGD  
_
1
nA  
VPWRGD = VIN = 6.0V  
Rising Edge  
LK  
PWRGD Time Delay  
TPG  
RPULLUP = 10 kΩ  
ICDELAY  
= 140 nA (Typ)  
CDELAY = OPEN  
10  
200  
30  
55  
µs  
ms  
ms  
µs  
CDELAY = 0.01 µF  
CDELAY = 0.1 µF  
300  
200  
Detect Threshold to PWRGD  
Active Time Delay  
TVDET-PWRGD  
VADJ or VSENSE = VPWRGD_TH  
20 mV to VPWRGD_TH - 20 mV  
+
Shutdown Input  
Logic High Input  
VSHDN-HIGH  
VSHDN-LOW  
SHDNILK  
45  
%VIN  
%VIN  
µA  
VIN = 2.3V to 6.0V  
VIN = 2.3V to 6.0V  
Logic Low Input  
15  
SHDN Input Leakage Current  
-0.1  
±0.001  
100  
+0.1  
VIN = 6V, SHDN =VIN  
SHDN = GND  
,
AC Performance  
Output Delay From SHDN  
TOR  
µs  
SHDN = GND to VIN  
V
OUT = GND to 95% VR  
Note 1: The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX).  
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output  
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.  
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the  
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.  
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is  
tested over a load range from 1 mA to the maximum specified output current.  
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its  
nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX)  
.
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction  
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power  
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained  
junction temperatures above 150°C can impact device reliability.  
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the  
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the  
ambient temperature is not significant.  
DS21999B-page 6  
© 2007 Microchip Technology Inc.  
MCP1727  
AC/DC CHARACTERISTICS (CONTINUED)  
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX) (Note 1), VR=1.8V for Adjustable Output,  
OUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C.  
Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C  
I
Parameters  
Output Noise  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
eN  
2.0  
µV/Hz IOUT = 200 mA, f = 1 kHz, COUT  
= 10 µF (X7R Ceramic), VOUT  
2.5V  
=
Power Supply Ripple Rejection  
Ratio  
PSRR  
60  
dB  
f = 100 Hz, COUT = 10 µF,  
I
OUT = 10 mA,  
INAC = 30 mV pk-pk,  
IN = 0 µF  
V
C
Thermal Shutdown Temperature  
Thermal Shutdown Hysteresis  
TSD  
150  
10  
°C  
°C  
IOUT = 100 µA, VOUT = 1.8V,  
IN = 2.8V  
V
ΔTSD  
IOUT = 100 µA, VOUT = 1.8V,  
IN = 2.8V  
V
Note 1: The minimum VIN must meet two conditions: VIN 2.3V and VIN VOUT(MAX) + VDROPOUT(MAX).  
2: VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output  
voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1.  
3: TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the  
temperature range. VOUT-LOW is the lowest voltage measured over the temperature range.  
4: Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is  
tested over a load range from 1 mA to the maximum specified output current.  
5: Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its  
nominal value that was measured with an input voltage of VOUT = VR + VDROPOUT(MAX)  
.
6: The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction  
temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power  
dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained  
junction temperatures above 150°C can impact device reliability.  
7: The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the  
desired junction temperature. The test time is small enough such that the rise in the junction temperature over the  
ambient temperature is not significant.  
TEMPERATURE SPECIFICATIONS  
Electrical Specifications: Unless otherwise indicated, all limits apply for VIN = 2.3V to 6.0V.  
Parameters  
Temperature Ranges  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Operating Junction Temperature Range  
Maximum Junction Temperature  
Storage Temperature Range  
TJ  
TJ  
TA  
-40  
+125  
+150  
+150  
°C  
°C  
°C  
Steady State  
Transient  
-65  
Thermal Package Resistances  
Thermal Resistance, 8LD 3x3 DFN  
θJA  
41  
°C/W 4-Layer JC51-7  
Standard Board with  
vias  
Thermal Resistance, 8LD SOIC  
θJA  
150  
°C/W 4-Layer JC51-7  
Standard Board  
© 2007 Microchip Technology Inc.  
DS21999B-page 7  
MCP1727  
2.0  
TYPICAL PERFORMANCE CURVES  
Note:  
The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.  
NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF  
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.  
NOTE: Junction Temperature (TJ) is approximated by soaking the device under test to an ambient temperature equal  
to the desired Junction temperature. The test time is small enough such that the rise in Junction temperature over the  
Ambient temperature is not significant.  
150  
140  
130  
120  
110  
100  
90  
0.1  
0.09  
0.08  
0.07  
0.06  
0.05  
0.04  
0.03  
0.02  
0.01  
0
VOUT = 1.2V adj  
VIN = 2.3V to 6.0V  
IOUT = 1 mA  
130°C  
90°C  
IOUT = 1000 mA  
IOUT = 100 mA  
25°C  
IOUT = 500 mA  
-45°C  
VOUT = 1.2V Adj  
IOUT = 0 mA  
2
3
4
5
6
-45  
-20  
5
30  
55  
80  
105  
130  
Input Voltage (V)  
Temperature (°C)  
FIGURE 2-1:  
Quiescent Current vs. Input  
FIGURE 2-4:  
Line Regulation vs.  
Voltage (1.2V Adjustable).  
Temperature (1.2V Adjustable).  
0.15  
200  
190  
IOUT = 1.0 mA to 1500 mA  
VOUT = 1.2V Adj  
VIN=5.0V  
VOUT = 3.3V  
0.10  
0.05  
180  
170  
160  
150  
140  
130  
120  
110  
100  
0.00  
VOUT = 0.8V  
VOUT = 5.0V  
VOUT = 1.8V  
VIN=3.3V  
-0.05  
-0.10  
-0.15  
VIN=2.3V  
500  
0
250  
750  
1000  
1250  
1500  
-45  
-20  
5
30  
55  
80  
105 130  
Load Current (mA)  
Temperature (°C)  
FIGURE 2-2:  
Ground Current vs. Load  
FIGURE 2-5:  
Load Regulation vs.  
Current (1.2V Adjustable).  
Temperature.  
0.411  
0.410  
0.410  
0.409  
0.409  
0.408  
140  
135  
130  
125  
IOUT = 0 mA  
VOUT = 1.2V Adj  
VIN = 6.0V  
VIN = 5.0V  
120  
VIN=5.0V  
VIN = 2.3V  
VIN=2.5V  
115  
110  
105  
100  
VIN=4.0V  
IOUT = 1.0 mA  
-45  
-20  
5
30  
55  
80  
105  
130  
-45 -20  
5
30  
55  
80  
105 130  
Temperature (°C)  
Temperature (°C)  
FIGURE 2-3:  
Junction Temperature (1.2V Adjustable).  
Quiescent Current vs.  
FIGURE 2-6:  
Temperature.  
Adjust Pin Voltage vs.  
DS21999B-page 8  
© 2007 Microchip Technology Inc.  
MCP1727  
NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF  
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
150  
140  
130  
120  
110  
100  
90  
VOUT = 5.0V Adj  
VOUT = 0.8V  
IOUT = 0 mA  
+130°C  
+85°C  
+25°C  
-45°C  
VOUT = 2.5V Adj  
80  
2
3
4
5
6
0
250  
500  
750  
1000 1250 1500  
Input Voltage (V)  
Load Current (mA)  
FIGURE 2-7:  
Dropout Voltage vs. Load  
FIGURE 2-10:  
Quiescent Current vs. Input  
Current (Adjustable Version).  
Voltage (0.8V Fixed).  
0.42  
150  
IOUT = 1.5A  
VOUT = 2.5V  
140 IOUT = 0 mA  
0.40  
0.38  
+130°C  
+90°C  
+25°C  
130  
120  
110  
100  
90  
VOUT = 5.0V Adj  
0.36  
0.34  
0.32  
0.30  
VOUT = 3.3V Adj  
-45°C  
VOUT = 2.5V Adj  
80  
3
3.5  
4
4.5  
5
5.5  
6
-45  
-20  
5
30  
55  
80  
105 130  
Input Voltage (V)  
Temperature (°C)  
FIGURE 2-8:  
Dropout Voltage vs.  
FIGURE 2-11:  
Quiescent Current vs. Input  
Temperature (Adjustable Version).  
Voltage (2.5V Fixed).  
32  
250.00  
200.00  
150.00  
100.00  
50.00  
CDELAY = 0.01 μF  
31  
30  
29  
28  
27  
26  
25  
VOUT = 1.8V Adj  
VIN = 2.4V  
VIN = 5.0V  
VOUT=0.8V  
VOUT=2.5V  
VIN = 2.3V for VR=0.8V  
VIN = 3.1V for VR=2.5V  
VIN = 3.3V  
55  
0.00  
-45  
-20  
5
30  
80  
105  
130  
0
250  
500  
750  
1000 1250 1500  
Temperature (°C)  
Load Current (mA)  
FIGURE 2-9:  
Power Good (PWRGD)  
FIGURE 2-12:  
Ground Current vs. Load  
Time Delay vs. Temperature.  
Current.  
© 2007 Microchip Technology Inc.  
DS21999B-page 9  
MCP1727  
NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF  
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.  
130  
125  
120  
115  
110  
105  
100  
95  
0.045  
0.040  
0.035  
0.030  
0.025  
0.020  
0.015  
IOUT = 0 mA  
VR = 2.5V  
VIN = 3.1 to 6.0V  
IOUT = 1 mA  
IOUT = 100 mA  
VOUT = 0.8V  
IOUT = 1000 mA  
IOUT = 500 mA  
IOUT = 1500 mA  
VOUT = 2.5V  
-45  
-20  
5
30  
55  
80  
105  
130  
-45  
-20  
5
30  
55  
80  
105  
130  
Temperature (°C)  
Temperature (°C)  
FIGURE 2-13:  
Quiescent Current vs.  
FIGURE 2-16:  
Line Regulation vs.  
Temperature.  
Temperature (2.5V Fixed).  
0.30  
0.30  
VR = 0.8V  
VIN = 2.3V  
VOUT = 0.8V  
0.20  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
0.10  
0.00  
VIN = 6.0V  
VIN = 4.0V  
VIN = 2.3V  
-0.10  
-0.20  
-0.30  
IOUT = 1 mA to 1500 mA  
-45  
-20  
5
30  
55  
80  
105  
130  
-45  
-20  
5
30  
55  
80  
105 130  
Temperature (°C)  
Temperature (°C)  
FIGURE 2-14:  
I
vs. Temperature.  
FIGURE 2-17:  
Temperature (V  
Load Regulation vs.  
< 2.5V Fixed).  
SHDN  
OUT  
0.10  
0.08  
0.06  
0.04  
0.00  
-0.05  
-0.10  
-0.15  
-0.20  
-0.25  
-0.30  
-0.35  
-0.40  
-0.45  
IOUT = 1 mA to 1500 mA  
IOUT = 1 mA  
VOUT = 2.5V  
VOUT = 5.0V  
IOUT = 1A  
IOUT = 100 mA  
IOUT = 500mA  
VOUT = 0.8V  
IN = 2.3V to 6.0V  
0.02  
0.00  
V
-45  
-20  
5
30  
55  
80  
105  
130  
-45  
-20  
5
30  
55  
80  
105  
130  
Temperature (°C)  
Temperature (°C)  
FIGURE 2-15:  
Temperature (0.8V Fixed).  
Line Regulation vs.  
FIGURE 2-18:  
Temperature (V  
Load Regulation vs.  
2.5V Fixed).  
OUT  
DS21999B-page 10  
© 2007 Microchip Technology Inc.  
MCP1727  
NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF  
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.  
0.40  
10  
Temperature = 25°C  
COUT=1 μF ceramic X7R  
0.35  
0.30  
0.25  
0.20  
0.15  
0.10  
0.05  
0.00  
VR=2.5V, VIN=3.3V  
VR=0.8V, VIN=2.3V  
CIN=10 μF ceramic  
VOUT = 2.5V  
1
0.1  
IOUT=200 mA  
VOUT = 5.0V  
0.01  
0.001  
0
250  
500  
750 1000 1250 1500  
0.01  
0.1  
1
10  
100  
1000  
Load Current (mA)  
Frequency (kHz)  
FIGURE 2-19:  
Dropout Voltage vs. Load  
FIGURE 2-22:  
Output Noise Voltage  
Current.  
Density vs. Frequency.  
0.45  
0.40  
0.35  
0
-10  
-20  
-30  
-40  
IOUT = 1.5A  
VOUT = 5.0V  
VR=1.2V Adj  
C
OUT=10 μF ceramic X7R  
-50  
-60  
-70  
-80  
VIN=3.1V  
0.30  
0.25  
CIN=0 μF  
VOUT = 2.5V  
IOUT=10 mA  
-45  
-20  
5
30  
55  
80  
105  
130  
0.01  
0.1  
1
10  
100  
1000  
Frequency (kHz)  
Temperature (°C)  
FIGURE 2-20:  
Dropout Voltage vs.  
FIGURE 2-23:  
Power Supply Ripple  
Temperature.  
Rejection (PSRR) vs. Frequency (V  
Adj.).  
= 1.2V  
OUT  
0
-10  
-20  
-30  
3.00  
2.50  
2.00  
1.50  
1.00  
0.50  
0.00  
-40  
VR=1.2V Adj  
-50  
-60  
-70  
-80  
C
OUT=22 μF ceramic X7R  
VIN=3.1V  
IN=0 μF  
IOUT=10 mA  
C
VOUT = 2.5V  
Temperature = 25°C  
3.0  
3.5  
4.0  
4.5  
5.0  
5.5  
6.0  
0.01  
0.1  
1
10  
100  
1000  
Frequency (kHz)  
Input Voltage (V)  
FIGURE 2-21:  
Short Circuit Current vs.  
FIGURE 2-24:  
Power Supply Ripple  
Input Voltage.  
Rejection (PSRR) vs. Frequency (V  
Adj.).  
= 1.2V  
OUT  
© 2007 Microchip Technology Inc.  
DS21999B-page 11  
MCP1727  
NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF  
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.  
0
-10  
-20  
-30  
-40  
VR=2.5V Fixed  
C
V
OUT=10 μF ceramic X7R  
IN=3.3V  
CIN=0 μF  
OUT=10 mA  
-50  
-60  
-70  
-80  
I
0.01  
0.1  
1
10  
100  
1000  
Frequency (kHz)  
FIGURE 2-25:  
Power Supply Ripple  
FIGURE 2-28:  
2.5V (Fixed) Startup from  
Rejection (PSRR) vs. Frequency (V  
Fixed).  
= 2.5V  
Shutdown.  
OUT  
0
-10  
-20  
-30  
-40  
VR=2.5V Fixed  
-50  
C
V
OUT=22 μF ceramic X7R  
IN=3.3V  
CIN=0 μF  
OUT=10 mA  
-60  
-70  
-80  
-90  
I
0.01  
0.1  
1
10  
100  
1000  
Frequency (kHz)  
FIGURE 2-29:  
Power Good (PWRGD)  
of 1000 pF.  
FIGURE 2-26:  
Rejection (PSRR) vs. Frequency (V  
Fixed).  
Power Supply Ripple  
Timing with C  
= 2.5V  
BYPASS  
OUT  
FIGURE 2-30:  
Power Good (PWRGD)  
of 0.1 µF.  
FIGURE 2-27:  
2.5V (Fixed) Startup from  
Timing with C  
V .  
BYPASS  
IN  
DS21999B-page 12  
© 2007 Microchip Technology Inc.  
MCP1727  
NOTE: Unless otherwise indicated VOUT = 1.8V (Adjustable), VIN = 2.8V, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF  
Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, RPWRGD = 10 kΩ To VIN.  
FIGURE 2-31:  
Dynamic Line Response  
FIGURE 2-33:  
Dynamic Load Response  
(0.8V Fixed).  
(2.5V Fixed, 10 mA to 1000 mA).  
FIGURE 2-32:  
Dynamic Line Response  
FIGURE 2-34:  
Dynamic Load Response  
(2.5V Fixed).  
(2.5V Fixed, 100 mA to 1000 mA).  
© 2007 Microchip Technology Inc.  
DS21999B-page 13  
MCP1727  
3.0  
PIN DESCRIPTION  
The descriptions of the pins are listed in Table 3-1.  
TABLE 3-1:  
Fixed Output  
PIN FUNCTION TABLE  
Adjustable  
Name  
Description  
Output  
1
2
1
2
VIN  
VIN  
Input Voltage Supply  
Input Voltage Supply  
3
3
SHDN  
GND  
Shutdown Control Input (active-low)  
Ground  
4
4
5
5
PWRGD  
CDELAY  
ADJ  
Power Good Output (open-drain)  
Power Good Delay Set-Point Input  
Voltage Sense Input (adjustable version)  
Voltage Sense Input (fixed voltage version)  
Regulated Output Voltage  
6
6
7
7
Sense  
VOUT  
EP  
8
8
Exposed Pad  
Exposed Pad  
Exposed Pad of the DFN Package (ground potential)  
3.1  
Input Voltage Supply (VIN)  
3.4  
Power Good Output (PWRGD)  
Connect the unregulated or regulated input voltage  
source to VIN. If the input voltage source is located  
several inches away from the LDO, or the input source  
is a battery, it is recommended that an input capacitor  
be used. A typical input capacitance value of 1 µF to  
10 µF should be sufficient for most applications.  
The PWRGD output is an open-drain output used to  
indicate when the LDO output voltage is within 92%  
(typically) of its nominal regulation value. The PWRGD  
threshold has a typical hysteresis value of 2%. The  
PWRGD output is typically delayed by 200 µs (typical,  
no capacitance on CDELAY pin) from the time the LDO  
output is within 92% + 3% (max hysteresis) of the  
regulated output value on power-up. This delay time is  
controlled by the CDELAY pin.  
3.2  
Shutdown Control Input (SHDN)  
The SHDN input is used to turn the LDO output voltage  
on and off. When the SHDN input is at a logic-high  
level, the LDO output voltage is enabled. When the  
SHDN input is pulled to a logic-low level, the LDO  
output voltage is disabled. When the SHDN input is  
pulled low, the PWRGD output also goes low and the  
LDO enters a low quiescent current shutdown state  
where the typical quiescent current is 0.1 µA.  
3.5  
Power Good Delay Set-Point Input  
(CDELAY  
)
The CDELAY input sets the power-up delay time for the  
PWRGD output. By connecting an external capacitor  
from the CDELAY pin to ground, the typical delay times  
for the PWRGD output can be adjusted from 200 µs (no  
capacitance) to 300 ms (0.1 µF capacitor). This allows  
for the optimal setting of the system reset time.  
3.3  
Ground (GND)  
Connect the GND pin of the LDO to a quiet circuit  
ground. This will help the LDO power supply rejection  
ratio and noise performance. The ground pin of the  
LDO only conducts the quiescent current of the LDO  
(typically 120 µA), so a heavy trace is not required.  
For applications have switching or noisy inputs tie the  
GND pin to the return of the output capacitor. Ground  
planes help lower inductance and voltage spikes  
caused by fast transient load currents and are  
recommended for applications that are subjected to  
fast load transients.  
3.6  
Output Voltage Sense/Adjust Input  
(ADJ/Sense)  
3.6.1  
ADJ  
For adjustable applications, the output voltage is  
connected to the ADJ input through a resistor divider  
that sets the output voltage regulation value. This  
provides the user the capability to set the output  
voltage to any value they desire within the 0.8V to 5.0V  
range of the device.  
DS21999B-page 14  
© 2007 Microchip Technology Inc.  
MCP1727  
3.6.2  
Sense  
3.7  
Regulated Output Voltage (VOUT)  
For fixed output voltage versions of the device, the  
SENSE input is used to provide output voltage  
feedback to the internal circuitry of the MCP1727. The  
SENSE pin typically improves load regulation by  
allowing the device to compensate for voltage drops  
due to packaging and circuit board layout.  
The VOUT pin(s) is the regulated output voltage of the  
LDO. A minimum output capacitance of 1.0 µF is  
required for LDO stability. The MCP1727 is stable with  
ceramic,  
tantalum  
and  
aluminum-electrolytic  
capacitors. See Section 4.3 “Output Capacitor” for  
output capacitor selection guidance.  
3.8  
Exposed Pad (EP)  
The 3x3 DFN package has an exposed pad on the  
bottom of the package. This pad should be soldered to  
the Printed Circuit Board (PCB) to aid in the removal of  
heat from the package during operation. The exposed  
pad is at the ground potential of the LDO.  
© 2007 Microchip Technology Inc.  
DS21999B-page 15  
MCP1727  
EQUATION 4-2:  
R1 = R2  
4.0  
DEVICE OVERVIEW  
VOUT VADJ  
--------------------------------  
VADJ  
The MCP1727 is a high output current, Low Dropout  
(LDO) voltage regulator with an adjustable delay  
power-good output and shutdown control input. The  
low dropout voltage of 330 mV typical at 1.5A of current  
makes it ideal for battery-powered applications. Unlike  
other high output current LDOs, the MCP1727 only  
draws a maximum of 220 µA of quiescent current.  
Where:  
VOUT  
VADJ  
=
=
LDO Output Voltage  
ADJ Pin Voltage  
(typically 0.41V)  
4.2  
Output Current and Current  
Limiting  
4.1  
LDO Output Voltage  
The MCP1727 LDO is available with either a fixed  
output voltage or an adjustable output voltage. The  
output voltage range is 0.8V to 5.0V for both versions.  
The MCP1727 LDO is tested and ensured to supply a  
minimum of 1.5A of output current. The MCP1727 has  
no minimum output load, so the output load current can  
go to 0 mA and the LDO will continue to regulate the  
output voltage to within tolerance.  
4.1.1  
ADJUST INPUT  
The adjustable version of the MCP1727 uses the ADJ  
pin (pin 7) to get the output voltage feedback for output  
voltage regulation. This allows the user to set the  
output voltage of the device with two external resistors.  
The nominal voltage for ADJ is 0.41V.  
The MCP1727 also incorporates an output current limit.  
If the output voltage falls below 0.7V due to an overload  
condition (usually represents a shorted load condition),  
the output current is limited to 2.2A (typical). If the  
overload condition is a soft overload, the MCP1727 will  
supply higher load currents of up to 3A. The MCP1727  
should not be operated in this condition continuously as  
it may result in failure of the device. However, this does  
allow for device usage in applications that have higher  
pulsed load currents having an average output current  
value of 1.5A or less.  
Figure 4-1 shows the adjustable version of the  
MCP1727. Resistors R1 and R2 form the resistor  
divider network necessary to set the output voltage.  
With this configuration, the equation for setting VOUT is:  
EQUATION 4-1:  
R1 + R2  
------------------  
VOUT = VADJ  
Output overload conditions may also result in an over-  
temperature shutdown of the device. If the junction  
temperature rises above 150°C, the LDO will shut  
down the output voltage. See Section 4.9 “Overtem-  
perature Protection” for more information on  
overtemperature shutdown.  
R2  
Where:  
VOUT  
VADJ  
=
=
LDO Output Voltage  
ADJ Pin Voltage  
(typically 0.41V)  
4.3  
Output Capacitor  
MCP1727-ADJ  
The MCP1727 requires a minimum output capacitance  
of 1 µF for output voltage stability. Ceramic capacitors  
are recommended because of their size, cost and  
environmental robustness qualities.  
V
V
OUT  
IN  
V
V
1
2
3
4
V
8
7
6
IN  
IN  
OUT  
C
4.7 µF  
1
ADJ  
R
1
C2  
1 µF  
SHDN  
GND  
C
DELAY  
PWRGD 5  
Aluminum-electrolytic and tantalum capacitors can be  
used on the LDO output as well. The Equivalent Series  
Resistance (ESR) of the electrolytic output capacitor  
must be no greater than 1 ohm. The output capacitor  
should be located as close to the LDO output as is  
practical. Ceramic materials X7R and X5R have low  
temperature coefficients and are well within the  
acceptable ESR range required. A typical 1 µF X7R  
0805 capacitor has an ESR of 50 milli-ohms.  
On  
Off  
C
3
R
2
1000 pF  
FIGURE 4-1:  
voltage application circuit.  
Typical adjustable output  
The allowable resistance value range for resistor R2 is  
from 10 kΩ to 200 kΩ. Solving the equation for R1  
yields the following equation:  
Larger LDO output capacitors can be used with the  
MCP1727 to improve dynamic performance and power  
supply ripple rejection performance. A maximum of  
22 µF  
is  
recommended.  
Aluminum-electrolytic  
capacitors are not recommended for low-temperature  
applications of 25°C.  
DS21999B-page 16  
© 2007 Microchip Technology Inc.  
MCP1727  
The power good output is an open-drain output that can  
be pulled up to any voltage that is equal to or less than  
the LDO input voltage. This output is capable of sinking  
1.2 mA (VPWRGD < 0.4V maximum).  
4.4  
Input Capacitor  
Low input source impedance is necessary for the LDO  
output to operate properly. When operating from  
batteries, or in applications with long lead length  
(> 10 inches) between the input source and the LDO,  
some input capacitance is recommended. A minimum  
of 1.0 µF to 4.7 µF is recommended for most  
applications.  
V
PWRGD_TH  
V
OUT  
For applications that have output step load  
requirements, the input capacitance of the LDO is very  
important. The input capacitance provides the LDO  
with a good local low-impedance source to pull the  
transient currents from in order to respond quickly to  
the output load step. For good step response  
performance, the input capacitor should be of  
equivalent (or higher) value than the output capacitor.  
The capacitor should be placed as close to the input of  
the LDO as is practical. Larger input capacitors will also  
help reduce any high-frequency noise on the input and  
output of the LDO and reduce the effects of any  
inductance that exists between the input source  
voltage and the input capacitance of the LDO.  
T
PG  
V
OH  
T
VDET_PWRGD  
PWRGD  
V
OL  
FIGURE 4-2:  
Power Good Timing.  
V
IN  
4.5  
Power Good Output (PWRGD)  
T
OR  
The PWRGD output is used to indicate when the output  
voltage of the LDO is within 92% (typical value, see  
Section 1.0 “Electrical Characteristics” for Minimum  
and Maximum specifications) of its nominal regulation  
value.  
70 µs  
30 µs  
T
PG  
SHDN  
As the output voltage of the LDO rises, the PWRGD  
output will be held low until the output voltage has  
exceeded the power good threshold plus the hysteresis  
value. Once this threshold has been exceeded, the  
power good time delay is started (shown as TPG in the  
Electrical Characteristics table). The power good time  
delay is adjustable via the CDELAY pin of the LDO (see  
Section 4.6 “CDELAY Input”). By placing a capacitor  
from the CDELAY pin to ground, the power good time  
delay can be adjusted from 200 µs (no capacitance) to  
300 ms (0.1 µF capacitor). After the time delay period,  
the PWRGD output will go high, indicating that the  
output voltage is stable and within regulation limits.  
V
OUT  
PWRGD  
FIGURE 4-3:  
Shutdown.  
Power Good Timing from  
If the output voltage of the LDO falls below the power  
good threshold, the power good output will transition  
low. The power good circuitry has a 170 µs delay when  
detecting a falling output voltage, which helps to  
increase noise immunity of the power good output and  
avoid false triggering of the power good output during  
fast output transients. See Figure 4-2 for power good  
timing characteristics.  
4.6  
CDELAY Input  
The CDELAY input is used to provide the power-up delay  
timing for the power good output, as discussed in the  
previous section. By adding a capacitor from the  
CDELAY pin to ground, the PWRGD power-up time  
delay can be adjusted from 200 µs (no capacitance on  
CDELAY) to 300 ms (0.1 µF of capacitance on CDELAY).  
See Section 1.0 “Electrical Characteristics” for  
CDELAY timing tolerances.  
When the LDO is put into Shutdown mode using the  
SHDN input, the power good output is pulled low  
immediately, indicating that the output voltage will be  
out of regulation. The timing diagram for the power  
good output when using the shutdown input is shown in  
Figure 4-3.  
© 2007 Microchip Technology Inc.  
DS21999B-page 17  
MCP1727  
Once the power good threshold (rising) has been  
reached, the CDELAY pin charges the external capacitor  
to VIN. The charging current is 140 nA (typical). The  
PWRGD output will transition high when the CDELAY pin  
voltage has charged to 0.42V. If the output falls below  
the power good threshold limit during the charging time  
between 0.0V and 0.42V on the CDELAY pin, the  
high (turn-on) to the LDO output being in regulation is  
typically 100 µs. See Figure 4-5 for a timing diagram of  
the SHDN input.  
T
OR  
400 ns (typ)  
70 µs  
30 µs  
CDELAY pin voltage will be pulled to ground, thus reset-  
ting the timer. The CDELAY pin will be held low until the  
output voltage of the LDO has once again risen above  
the power good rising threshold. A timing diagram  
showing CDELAY, PWRGD and VOUT is shown in  
Figure 4-4.  
SHDN  
V
OUT  
V
OUT  
V
PWRGD_TH  
FIGURE 4-5:  
Shutdown Input Timing  
Diagram.  
V
(typ)  
IN  
C
T
DELAY  
C
PG  
4.8  
Dropout Voltage and Undervoltage  
Lockout  
Threshold (0.42V)  
DELAY  
0V  
Dropout voltage is defined as the input-to-output  
voltage differential at which the output voltage drops  
2% below the nominal value that was measured with a  
VR + 0.6V differential applied. The MCP1727 LDO has  
a very low dropout voltage specification of 330 mV  
(typical) at 1.5A of output current. See Section 1.0  
“Electrical Characteristics” for maximum dropout  
voltage specifications.  
PWRGD  
FIGURE 4-4:  
C
and PWRGD Timing  
DELAY  
Diagram.  
The MCP1727 LDO operates across an input voltage  
range of 2.3V to 6.0V and incorporates input Undervolt-  
age Lockout (UVLO) circuitry that keeps the LDO  
output voltage off until the input voltage reaches a  
minimum of 2.18V (typical) on the rising edge of the  
input voltage. As the input voltage falls, the LDO output  
will remain on until the input voltage level reaches  
2.04V (typical).  
4.7  
Shutdown Input (SHDN)  
The SHDN input is an active-low input signal that turns  
the LDO on and off. The SHDN threshold is a  
percentage of the input voltage. The typical value of  
this shutdown threshold is 30% of VIN, with minimum  
and maximum limits over the entire operating  
temperature range of 45% and 15%, respectively.  
Since the MCP1727 LDO undervoltage lockout  
activates at 2.04V as the input voltage is falling, the  
dropout voltage specification does not apply for output  
voltages that are less than 1.9V.  
The SHDN input will ignore low-going pulses (pulses  
meant to shut down the LDO) that are up to 400 ns in  
pulse width. If the shutdown input is pulled low for more  
than 400 ns, the LDO will enter Shutdown mode. This  
small bit of filtering helps to reject any system noise  
spikes on the shutdown input signal.  
For high-current applications, voltage drops across the  
PCB traces must be taken into account. The trace  
resistances can cause significant voltage drops  
between the input voltage source and the LDO. For  
applications with input voltages near 2.3V, these PCB  
trace voltage drops can sometimes lower the input  
On the rising edge of the SHDN input, the shutdown  
circuitry has a 30 µs delay before allowing the LDO  
output to turn on. This delay helps to reject any false  
turn-on signals or noise on the SHDN input signal. After  
the 30 µs delay, the LDO output enters its soft-start  
period as it rises from 0V to its final regulation value. If  
the SHDN input signal is pulled low during the 30 µs  
delay period, the timer will be reset and the delay time  
will start over again on the next rising edge of the  
SHDN input. The total time from the SHDN input going  
voltage enough to trigger  
undervoltage lockout.  
a shutdown due to  
DS21999B-page 18  
© 2007 Microchip Technology Inc.  
MCP1727  
4.9  
Overtemperature Protection  
The MCP1727 LDO has temperature-sensing circuitry  
to prevent the junction temperature from exceeding  
approximately 150°C. If the LDO junction temperature  
does reach 150°C, the LDO output will be turned off  
until the junction temperature cools to approximately  
140°C, at which point the LDO output will automatically  
resume normal operation. If the internal power  
dissipation continues to be excessive, the device will  
again shut off. The junction temperature of the die is a  
function of power dissipation, ambient temperature  
and package thermal resistance. See Section 5.0  
“Application Circuits/Issues” for more information  
on LDO power dissipation and junction temperature.  
© 2007 Microchip Technology Inc.  
DS21999B-page 19  
MCP1727  
In addition to the LDO pass element power dissipation,  
there is power dissipation within the MCP1727 as a  
result of quiescent or ground current. The power  
dissipation as a result of the ground current can be  
calculated using the following equation:  
5.0  
APPLICATION CIRCUITS/  
ISSUES  
5.1  
Typical Application  
The MCP1727 is used for applications that require high  
LDO output current and a power good output.  
EQUATION 5-2:  
PI(GND) = VIN(MAX) × IVIN  
Where:  
MCP1727-2.5  
V
= 3.3V  
V
= 2.5V @ 1.5A  
IN  
OUT  
PI(GND  
=
Power dissipation due to the  
quiescent current of the LDO  
1
2
3
4
V
V
V
OUT  
8
7
6
5
IN  
IN  
C
R
1
1
Sense  
10 µF  
C
2
10 µF  
10kΩ  
VIN(MAX)  
IVIN  
=
=
Maximum input voltage  
SHDN C  
DELAY  
GND PWRGD  
Current flowing in the VIN pin  
with no LDO output current  
(LDO quiescent current)  
On  
Off  
C
3
1000 pF  
The total power dissipated within the MCP1727 is the  
sum of the power dissipated in the LDO pass device  
PWRGD  
and the P(IGND  
) term. Because of the CMOS  
construction, the typical IGND for the MCP1727 is  
120 µA. Operating at a maximum of 3.465V results in a  
power dissipation of 0.49 milli-Watts. For most  
applications, this is small compared to the LDO pass  
device power dissipation and can be neglected.  
FIGURE 5-1:  
Typical Application Circuit.  
5.1.1  
APPLICATION CONDITIONS  
Package Type = 3x3DFN8  
The maximum continuous operating junction  
temperature specified for the MCP1727 is +125°C. To  
estimate the internal junction temperature of the  
MCP1727, the total internal power dissipation is  
multiplied by the thermal resistance from junction to  
ambient (RθJA) of the device. The thermal resistance  
from junction to ambient for the 3x3 DFN package is  
estimated at 41° C/W.  
Input Voltage Range = 3.3V ± 5%  
IN maximum = 3.465V  
IN minimum = 3.135V  
VDROPOUT (max) = 0.525V  
OUT (typical) = 2.5V  
OUT = 1.5A maximum  
V
V
V
I
PDISS (typical) = 1.2W  
EQUATION 5-3:  
Temperature Rise = 49.2°C  
TJ(MAX) = PTOTAL × RθJA + TAMAX  
5.2  
Power Calculations  
TJ(MAX) = Maximum continuous junction  
temperature  
5.2.1  
POWER DISSIPATION  
PTOTAL = Total device power dissipation  
The internal power dissipation within the MCP1727 is a  
function of input voltage, output voltage, output current  
and quiescent current. Equation 5-1 can be used to  
calculate the internal power dissipation for the LDO.  
RθJA = Thermal resistance from junction to  
ambient  
TAMAX = Maximum ambient temperature  
EQUATION 5-1:  
PLDO = (VIN(MAX)) VOUT(MIN)) × IOUT(MAX))  
Where:  
PLDO  
=
LDO Pass device internal  
power dissipation  
VIN(MAX)  
=
=
Maximum input voltage  
VOUT(MIN)  
LDO minimum output voltage  
DS21999B-page 20  
© 2007 Microchip Technology Inc.  
MCP1727  
The maximum power dissipation capability for a  
package can be calculated given the junction-to-  
ambient thermal resistance and the maximum ambient  
temperature for the application. Equation 5-4 can be  
used to determine the package maximum internal  
power dissipation.  
5.3  
Typical Application  
Internal power dissipation, junction temperature rise,  
junction temperature and maximum power dissipation  
is calculated in the following example. The power  
dissipation as a result of ground current is small  
enough to be neglected.  
EQUATION 5-4:  
5.3.1  
POWER DISSIPATION EXAMPLE  
(TJ(MAX) TA(MAX)  
)
PD(MAX) = ---------------------------------------------------  
RθJA  
Package  
Package Type = 3x3DFN  
PD(MAX) = Maximum device power dissipation  
Input Voltage  
TJ(MAX) = maximum continuous junction  
temperature  
V
IN = 3.3V ± 5%  
LDO Output Voltage and Current  
TA(MAX) = maximum ambient temperature  
V
OUT = 2.5V  
OUT = 1.5A  
RθJA = Thermal resistance from junction to  
I
ambient  
Maximum Ambient Temperature  
A(MAX) = 60°C  
Internal Power Dissipation  
T
EQUATION 5-5:  
TJ(RISE) = PD(MAX) × RθJA  
PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX)  
PLDO = ((3.3V x 1.05) – (2.5V x 0.975))  
x 1.5A  
TJ(RISE) = Rise in device junction temperature  
over the ambient temperature  
PLDO = 1.54 Watts  
PD(MAX) = Maximum device power dissipation  
RθJA = Thermal resistance from junction to  
5.3.1.1  
Device Junction Temperature Rise  
ambient  
The internal junction temperature rise is a function of  
internal power dissipation and the thermal resistance  
from junction-to-ambient for the application. The  
thermal resistance from junction-to-ambient (RθJA) is  
derived from an EIA/JEDEC standard for measuring  
thermal resistance for small surface-mount packages.  
The EIA/JEDEC specification is JESD51-7 “High  
Effective Thermal Conductivity Test Board for Leaded  
Surface-Mount Packages”. The standard describes the  
test method and board specifications for measuring the  
thermal resistance from junction to ambient. The actual  
thermal resistance for a particular application can vary  
depending on many factors such as copper area and  
thickness. Refer to AN792, “A Method to Determine  
How Much Power a SOT23 Can Dissipate in an  
Application” (DS00792), for more information regarding  
this subject.  
EQUATION 5-6:  
TJ = TJ(RISE) + TA  
TJ = Junction temperature  
TJ(RISE) = Rise in device junction temperature  
over the ambient temperature  
TA = Ambient temperature  
T
J(RISE) = PTOTAL x RθJA  
TJRISE = 1.54 W x 41.0° C/W  
JRISE = 63.14°C  
T
© 2007 Microchip Technology Inc.  
DS21999B-page 21  
MCP1727  
5.3.1.2  
Junction Temperature Estimate  
5.4  
CDELAY Calculations (typical)  
To estimate the internal junction temperature, the  
calculated temperature rise is added to the ambient or  
offset temperature. For this example, the worst-case  
junction temperature is estimated below:  
ΔT  
ΔV  
-------  
C = I •  
Where:  
C
=
=
C
DELAY Capacitor  
TJ = TJRISE + TA(MAX)  
TJ = 63.14°C + 60.0°C  
TJ = 123.14°C  
I
CDELAY charging current,  
140 nA typical.  
ΔT  
ΔV  
=
=
time delay  
As you can see from the result, this application will be  
operating very near the maximum operating junction  
temperature of 125°C. The PCB layout for this  
application is very important as it has a significant  
impact on the junction-to-ambient thermal resistance  
(RθJA) of the 3x3 DFN package, which is very important  
in this application.  
CDELAY threshold voltage,  
0.42V typical  
C = I •  
= --------------------------------- = 333.3×10–09 • ΔT  
0.42V  
ΔT  
-------  
(140nA • ΔT)  
ΔV  
For a delay of 300 ms:  
C = 333.3E-09 * .300  
C = 100E-09uF (0.1 μF)  
5.3.1.3  
Maximum Package Power  
Dissipation at 60°C Ambient  
Temperature  
3x3DFN (41° C/W RθJA):  
P
D(MAX) = (125°C – 60°C) / 41° C/W  
D(MAX) = 1.585W  
P
SOIC8 (150°C/Watt RθJA):  
P
D(MAX) = (125°C – 60°C)/ 150° C/W  
D(MAX) = 0.433W  
P
From this table, you can see the difference in maximum  
allowable power dissipation between the 3x3 DFN  
package and the 8-pin SOIC package. This difference  
is due to the exposed metal tab on the bottom of the  
DFN package. The exposed tab of the DFN package  
provides a very good thermal path from the die of the  
LDO to the PCB. The PCB then acts like a heatsink,  
providing more area to distribute the heat generated by  
the LDO.  
DS21999B-page 22  
© 2007 Microchip Technology Inc.  
MCP1727  
6.0  
6.1  
PACKAGING INFORMATION  
Package Marking Information  
8-Lead DFN (3x3)  
Example:  
Standard  
Extended Temp  
XXXX  
YYWW  
NNN  
CAAJ  
0620  
256  
Voltage  
Voltage  
Options *  
Code  
Code  
Options *  
CAAJ  
CAAK  
CAAL  
CAAM  
0.8  
1.2  
1.8  
2.5  
CAAP  
CAAQ  
CAAR  
CAAH  
3.0  
3.3  
5.0  
ADJ  
* Custom output voltages available upon request.  
Contact your local Microchip sales office for more  
information.  
8-Lead SOIC (150 mil)  
Example:  
1727082E  
Standard  
Extended Temp  
XXXXXXXX  
XXXXYYWW  
Voltage  
Options *  
Voltage  
Code  
Code  
e3  
SN 0620  
Options *  
NNN  
256  
082E  
122E  
182E  
252E  
0.8  
1.2  
1.8  
2.5  
302E  
332E  
502E  
ADJE  
3.0  
3.3  
5.0  
ADJ  
* Custom output voltages available upon request.  
Contact your local Microchip sales office for more  
information.  
Legend: XX...X Customer-specific information  
Y
YY  
WW  
NNN  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
e
3
Pb-free JEDEC designator for Matte Tin (Sn)  
*
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
)
e3  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
© 2007 Microchip Technology Inc.  
DS21999B-page 23  
MCP1727  
8-Lead Plastic Dual Flat, No Lead Package (MF) – 3x3x0.9 mm Body [DFN]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
e
D
b
N
N
L
EXPOSED PAD  
E
E2  
K
NOTE 1  
NOTE 1  
1
2
2
1
D2  
BOTTOM VIEW  
TOP VIEW  
A
NOTE 2  
A3  
A1  
Units  
MILLIMETERS  
NOM  
Dimension Limits  
MIN  
MAX  
Number of Pins  
Pitch  
N
e
8
0.65 BSC  
0.90  
Overall Height  
Standoff  
A
0.80  
0.00  
1.00  
0.05  
A1  
A3  
D
0.02  
Contact Thickness  
Overall Length  
Exposed Pad Width  
Overall Width  
0.20 REF  
3.00 BSC  
E2  
E
0.00  
1.60  
3.00 BSC  
Exposed Pad Length  
Contact Width  
Contact Length  
Contact-to-Exposed Pad  
D2  
b
0.00  
0.25  
0.20  
0.20  
2.40  
0.35  
0.55  
0.30  
L
0.30  
K
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. Package may have one or more exposed tie bars at ends.  
3. Package is saw singulated.  
4. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-062B  
DS21999B-page 24  
© 2007 Microchip Technology Inc.  
MCP1727  
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
e
N
E
E1  
NOTE 1  
1
2
3
α
h
b
h
c
φ
A2  
A
L
A1  
L1  
β
Units  
MILLMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
8
1.27 BSC  
Overall Height  
A
1.75  
Molded Package Thickness  
Standoff  
A2  
A1  
E
1.25  
0.10  
§
0.25  
Overall Width  
6.00 BSC  
Molded Package Width  
Overall Length  
Chamfer (optional)  
Foot Length  
E1  
D
h
3.90 BSC  
4.90 BSC  
0.25  
0.40  
0.50  
1.27  
L
Footprint  
L1  
φ
1.04 REF  
Foot Angle  
0°  
0.17  
0.31  
5°  
8°  
Lead Thickness  
Lead Width  
c
0.25  
0.51  
15°  
b
Mold Draft Angle Top  
Mold Draft Angle Bottom  
α
β
5°  
15°  
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. § Significant Characteristic.  
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.  
4. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-057B  
© 2007 Microchip Technology Inc.  
DS21999B-page 25  
MCP1727  
NOTES:  
DS21999B-page 26  
© 2007 Microchip Technology Inc.  
MCP1727  
APPENDIX A: REVISION HISTORY  
Revision B (February 2007)  
• Revised Notes on pages 8–13.  
• Added junction temperature note.  
• Figure 2-22: Revised label on Y-axis  
• Figure 2-27 and Figure 2-28: Replaced figure and  
revised figure captions.  
• Added disclaimers to package outline drawings.  
• Updated package outline drawings.  
Revision A (July 2006)  
• Original Release of this Document.  
© 2007 Microchip Technology Inc.  
DS21999B-page 27  
MCP1727  
NOTES:  
DS21999B-page 28  
© 2007 Microchip Technology Inc.  
MCP1727  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PART NO.  
Device  
XX  
X
X
X/  
XX  
a)  
b)  
MCP1727-0802E/MF: 0.8V Low Dropout  
Output Feature Tolerance Temp. Package  
Voltage  
Regulator,  
DFN8 pkg.  
Code  
MCP1727T-1202E/MF: Tape and Reel,  
1.2V Low Dropout  
Regulator,  
Device:  
MCP1727: 1.5A Low Dropout Regulator  
MCP1727T: 1.5A Low Dropout Regulator  
Tape and Reel  
DFN8 pkg.  
c)  
d)  
MCP1727-1802E/MF: 1.8V Low Dropout  
Voltage Regulator,  
Output Voltage *:  
08  
12  
18  
25  
30  
33  
50  
=
=
=
=
=
=
=
0.8V “Standard”  
1.2V “Standard”  
1.8V “Standard”  
2.5V “Standard”  
3.0V “Standard”  
3.3V “Standard”  
5.0V “Standard”  
DFN8 pkg.  
MCP1727T-2502E/MF: Tape and Reel,  
2.5V Low Dropout  
Voltage Regulator,  
DFN8 pkg.  
e)  
f)  
MCP1727-3002E/MF: 3.0V Low Dropout  
Voltage Regulator,  
*Contact factory for other output voltage options  
DFN8 pkg.  
Extra Feature Code:  
Tolerance:  
0
2
E
=
=
=
Fixed  
MCP1727-3302E/MF: 3.3V Low Dropout  
Voltage Regulator,  
DFN8 pkg.  
2.0% (Standard)  
-40°C to +125°C  
g)  
MCP1727T-5002E/MF: Tape and Reel,  
5.0V Low Dropout  
Temperature:  
Voltage Regulator,  
DFN8 pkg.  
Package Type:  
MF  
SN  
=
=
Plastic Dual Flat No Lead (DFN)  
(3x3x0.9 mm Body), 8-lead  
Plastic Small Outline (150 mil Body), 8-lead  
h)  
MCP1727T-0802E/SN: Tape and Reel,  
0.8V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
i)  
j)  
MCP1727-1202E/SN: 1.2V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
MCP1727T-1802E/SN: Tape and Reel,  
1.8V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
k)  
l)  
MCP1727-2502E/SN: 2.5V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
MCP1727-3002E/SN: 3.0V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
m) MCP1727-3302E/SN: 3.3V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
n)  
MCP1727T-5002E/SN: Tape and Reel,  
5.0V Low Dropout  
Voltage Regulator,  
SOIC8 pkg.  
© 2007 Microchip Technology Inc.  
DS21999B-page 29  
MCP1727  
NOTES:  
DS21999B-page 30  
© 2007 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, Accuron,  
dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC,  
PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and  
SmartShunt are registered trademarks of Microchip  
Technology Incorporated in the U.S.A. and other countries.  
AmpLab, FilterLab, Linear Active Thermistor, Migratable  
Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor  
and The Embedded Control Solutions Company are  
registered trademarks of Microchip Technology Incorporated  
in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, CodeGuard,  
dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,  
ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,  
In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi,  
MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit,  
PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,  
PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,  
rfPICDEM, Select Mode, Smart Serial, SmartTel, Total  
Endurance, UNI/O, WiperLock and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2007, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
Microchip received ISO/TS-16949:2002 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona, Gresham, Oregon and Mountain View, California. The  
Company’s quality system processes and procedures are for its PIC®  
MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial  
EEPROMs, microperipherals, nonvolatile memory and analog  
products. In addition, Microchip’s quality system for the design and  
manufacture of development systems is ISO 9001:2000 certified.  
© 2007 Microchip Technology Inc.  
DS21999B-page 31  
WORLDWIDE SALES AND SERVICE  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Habour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-4182-8400  
Fax: 91-80-4182-8422  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://support.microchip.com  
Web Address:  
www.microchip.com  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
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Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
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Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Japan - Yokohama  
Tel: 81-45-471- 6166  
Fax: 81-45-471-6122  
China - Beijing  
Tel: 86-10-8528-2100  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
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Tel: 82-54-473-4301  
Fax: 82-54-473-4302  
Boston  
China - Chengdu  
Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
China - Fuzhou  
Tel: 86-591-8750-3506  
Fax: 86-591-8750-3521  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Malaysia - Penang  
Tel: 60-4-646-8870  
Fax: 60-4-646-5086  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Detroit  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
Kokomo  
Kokomo, IN  
Tel: 765-864-8360  
Fax: 765-864-8387  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Taiwan - Hsin Chu  
Tel: 886-3-572-9526  
Fax: 886-3-572-6459  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-536-4803  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Shunde  
Tel: 86-757-2839-5507  
Fax: 86-757-2839-5571  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Santa Clara  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
Toronto  
Mississauga, Ontario,  
Canada  
Tel: 905-673-0699  
Fax: 905-673-6509  
China - Xian  
Tel: 86-29-8833-7250  
Fax: 86-29-8833-7256  
12/08/06  
DS21999B-page 32  
© 2007 Microchip Technology Inc.  

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