MCP2004-E/SNVAO [MICROCHIP]
Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, PDSO8;
| 型号： | MCP2004-E/SNVAO |
| 厂家： | 
MICROCHIP |
| 描述： | Line Transceiver, 1 Func, 1 Driver, 1 Rcvr, PDSO8 驱动 光电二极管 接口集成电路 驱动器 |
| 文件： | 总34页 (文件大小：772K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Not Recommended for New Designs
Please use ATA663211 or MCP2003B
MCP2003/4/3A/4A
LIN J2602 Transceiver
Description
Features
• The MCP2003/2003A and MCP2004/2004A are
Compliant with Local Interconnect Network (LIN)
Bus Specifications 1.3, 2.0 and 2.1, and are
Compliant to SAE J2602
This device provides a bidirectional, half-duplex commu-
nication, physical interface to automotive and industrial
LIN systems to meet the LIN Bus Specification
Revision 2.1 and SAE J2602. The device is short-circuit
and overtemperature protected by internal circuitry. The
device has been specifically designed to operate in the
automotive operating environment and will survive all
specified transient conditions, while meeting all of the
stringent quiescent current requirements.
• Supports Baud Rates up to 20 Kbaudwith
LIN Bus Compatible Output Driver
• 43V Load Dump Protected
• Very Low/High Electromagnetic Immunity (EMI)
meets Stringent Original Equipment
Manufacturers (OEM) Requirements
MCP200X family members:
• Very High Electrostatic Discharge (ESD)
Immunity:
• 8-pin PDIP, DFN and SOIC packages:
- MCP2003: LIN bus compatible driver with
- >20 kV on V (IEC 61000-4-2)
WAKE pins, wake-up on falling edge of L
BB
BUS
- >14 kV on L
(IEC 61000-4-2)
- MCP2003A: LIN bus compatible driver with
WAKE pins, wake-up on rising edge of L
BUS
• Very High Immunity to RF Disturbances meets
Stringent OEM Requirements
BUS
- MCP2004: LIN bus compatible driver with
FAULT/T pins, wake-up on falling edge of
• Wide Supply Voltage, 6.0V-27.0V Continuous
• Extended Temperature Range: -40°C to +125°C
XE
L
BUS
- MCP2004A: LIN bus compatible driver with
FAULT/T pins, wake-up on rising edge of
®
• Interface to PIC MCU EUSART and Standard
USARTs
XE
L
BUS
• LIN Bus Pin:
- Internal pull-up resistor and diode
- Protected against battery shorts
- Protected against loss of ground
- High-current drive
Package Types
MCP2003/2003A
MCP2004/2004A
PDIP, SOIC
PDIP, SOIC
• Automatic Thermal Shutdown
• Low-Power mode:
RXD
RXD
VREN
VBB
VREN
VBB
1
8
1
2
8
CS
WAKE
TXD
2
3
4
CS/WAKE
FAULT/
7
6
5
7
6
5
- Receiver monitoring bus and transmitter off
TXE
LBUS
VSS
LBUS
VSS
3
4
(
5 µA)
TXD
MCP2003/2003A
MCP2004/2004A
4x4 DFN*
4x4 DFN*
RXD
RXD
VREN
1
2
VREN
VBB
1
8
7
8
7
CS
WAKE
TXD
VBB
2
3
4
CS/WAKE
EP
9
EP
9
LBUS
VSS
3
4
LBUS
VSS
FAULT/TXE
TXD
6
5
6
5
* Includes Exposed Thermal Pad (EP); see Table 1-2.
2010-2016 Microchip Technology Inc.
DS20002230G-page 1
MCP2003/4/3A/4A
MCP2003/2003A Block Diagram
V
V
BB
REN
Ratiometric
Reference
Wake-up
Logic and
4.3V
WAKE
Power Control
–
R
XD
+
~30 k
CS
T
L
OC
XD
BUS
V
SS
Thermal
Protection
Short-Circuit
Protection
MCP2004/2004A Block Diagram
V
V
BB
REN
Ratiometric
Reference
4.3V 4.3V
Wake-up
Logic and
Power Control
–
+
R
XD
~30 k
CS/WAKE
T
L
BUS
OC
XD
FAULT/T
V
XE
SS
Thermal
Protection
Short-Circuit
Protection
DS20002230G-page 2
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
1.2.2
GROUND LOSS PROTECTION
1.0
DEVICE OVERVIEW
The LIN Bus Specification states that the LIN pin must
transition to the Recessive state when the ground is
disconnected. Therefore, a loss of ground effectively
forces the LIN line to a high-impedance level.
The MCP2003/4/3A/4A devices provide a physical
interface between a microcontroller and a LIN bus.
These devices will translate the CMOS/TTL logic levels
to the LIN logic level and vice versa. It is intended for
automotive and industrial applications with serial bus
speeds up to 20 Kbaud.
1.2.3
THERMAL PROTECTION
The thermal protection circuit monitors the die
temperature and is able to shut down the LIN
transmitter.
LIN Bus Specification Revision 2.1 requires that the
transceiver of all nodes in the system is connected via
the LIN pin, referenced to ground, and with a maximum
external termination resistance load of 510 from LIN
bus to battery supply. The 510 corresponds to
1 master and 15 slave nodes.
There are two causes for a thermal overload. A thermal
shutdown can be triggered by either, or both, of the
following thermal overload conditions:
• LIN bus output overload
The V
pin can be used to drive the logic input of an
REN
external voltage regulator. This pin is high in all modes
except for Power-Down mode.
• Increase in die temperature due to increase in
environment temperature
Driving the T pin and checking the R pin makes it
XD
XD
1.1
External Protection
possible to determine whether there is a bus contention
(R = low, T = high) or a thermal overload condition
XD
XD
1.1.1
REVERSE BATTERY PROTECTION
(R = high, T = low). After a thermal overload event,
XD
XD
the device will automatically recover once the die
temperature has fallen below the recovery temperature
threshold (see Figure 1-1).
An external reverse battery blocking diode should be
used to provide polarity protection (see Example 1-1).
1.1.2
TRANSIENT VOLTAGE
PROTECTION (LOAD DUMP)
FIGURE 1-1:
THERMAL SHUTDOWN
STATE DIAGRAM
An external 43V Transient Suppressor (TVS) diode,
between V and ground with a 50 Transient
BB
Shorted LIN Bus
to VBB
Protection Resistor (RTP) in series with the battery
supply and the V pin, serve to protect the device from
BB
power transients (see Example 1-1) and ESD events.
While this protection is optional, it is considered good
engineering practice.
Transmitter
Shutdown
Operation
Mode
1.2
Internal Protection
1.2.1
ESD PROTECTION
Temp < ShutdownTEMP
For component-level ESD ratings, please refer to the
maximum operation specifications.
2010-2016 Microchip Technology Inc.
DS20002230G-page 3
MCP2003/4/3A/4A
Upon V supply pin power-on, the device will remain
in Ready mode as long as CS is low. When CS
transitions high, the device will either enter Operation
1.3
Modes of Operation
BB
For an overview of all operational modes, refer to
Table 1-1.
mode, if the T pin is held high, or the device will enter
XD
Transmitter Off mode, if the T pin is held low.
XD
1.3.1
POWER-DOWN MODE
1.3.3
OPERATION MODE
In Power-Down mode, everything is off except the
wake-up section. This is the lowest power mode. The
receiver is off, thus its output is open-drain.
In this mode, all internal modules are operational.
The device will go into Power-Down mode on the falling
edge of CS. For the MCP2003/4 device, a specific
process should be followed to put all nodes into Power-
Down mode. Refer to Section 1.6 “MCP2003/4 and
MCP2003A/4A Difference Details” and Figure 1-6.
The device will enter Transmitter Off mode in the event
of a Fault condition, such as thermal overload, bus
On CS going to a high level or a falling edge on WAKE
(MCP2003/MCP2003A only), the device will enter
Ready mode as soon as the internal voltage stabilizes.
Refer to Section 2.4 “AC Specifications” for further
information. In addition, LIN bus activity will change the
device from Power-Down mode to Ready mode;
MCP2003/4 wakes up on a falling edge on L
,
BUS
contention and T timer expiration.
XD
followed by a low level lasting at least 20 µs.
MCP2003A/4A wakes up on a rising edge on L
The MCP2004/2004A device can also enter Transmitter
,
BUS
Off mode if the FAULT/T pin is pulled low. The V to
XE
BB
followed by a high level lasting 70 µs, typically. See
Figures 1-2 to 1-5 about remote wake-up. If CS is held
high as the device transitions from Power-Down to
Ready mode, the device will transition to either Opera-
L
pull-up resistor is connected only in Operation
BUS
mode.
1.3.4
TRANSMITTER OFF MODE
tion or Transmitter Off mode, depending on the T
input, as soon as internal voltages stabilize.
XD
Transmitter Off mode is reached whenever the
transmitter is disabled, either due to a Fault condition or
1.3.2
READY MODE
pulling the FAULT/T pin low on the MCP2004/2004A.
XE
The Fault conditions include: thermal overload, bus
Upon entering Ready mode, V
is enabled and the
REN
contention, R monitoring or T timer expiration.
XD
XD
receiver detect circuit is powered up. The transmitter
remains disabled and the device is ready to receive
data but not to transmit.
The device will go into Power-Down mode on the falling
edge of CS or return to Operation mode if all Faults are
resolved and the FAULT/T pin on the MCP2004/2004A
XE
is high.
FIGURE 1-2:
OPERATIONAL MODES STATE DIAGRAM – MCP2003
Ready
VREN ON
RX ON
TX OFF
POR
VBAT > 5.5V
VREN OFF
RX OFF
TX OFF
CS = 1and TXD = 1
CS = 1and TXD = 0
CS = 1and TXD = 1and No Fault
TOFF
Operation
Mode
VREN ON
RX ON
TX ON
Falling Edge on LIN
or CS = 1
Mode
VREN ON
RX ON
TX OFF
or Falling Edge on WAKE Pin
Fault (thermal or timer)
CS = 0
CS = 0
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
DS20002230G-page 4
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
FIGURE 1-3:
OPERATIONAL MODES STATE DIAGRAM – MCP2003A
Ready
VREN ON
RX OFF
TX OFF
POR
VBAT > 5.5V
VREN OFF
RX OFF
TX OFF
CS = 1and TXD = 1
CS = 1and TXD = 0
CS = 1and TXD = 1and No Fault
TOFF
Operation
Mode
VREN ON
RX ON
TX ON
Rising Edge on LIN
or CS = 1
Mode
VREN ON
RX ON
TX OFF
or Falling Edge on WAKE Pin
Fault (thermal or timer)
CS = 0
CS = 0
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
FIGURE 1-4:
OPERATIONAL MODES STATE DIAGRAM – MCP2004
Ready
POR
VREN ON
RX ON
TX OFF
VBAT > 5.5V
VREN OFF
RX OFF
TX OFF
CS = 1and TXD = 1and TXE = 1
CS = 1and (TXE = 0or TXD = 0)
CS = 1and TXD = 1and TXE = 1
and No Fault
TOFF
Operation
Mode
VREN ON
RX ON
TX ON
Falling Edge on LIN or
CS = 1
Mode
Fault (thermal or time-out) or
FAULT/TXE = 0
VREN ON
RX ON
TX OFF
CS = 0
CS = 0
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
2010-2016 Microchip Technology Inc.
DS20002230G-page 5
MCP2003/4/3A/4A
FIGURE 1-5:
OPERATIONAL MODES STATE DIAGRAM – MCP2004A
Ready
VREN ON
RX ON
TX OFF
POR
VBAT > 5.5V
VREN OFF
RX OFF
TX OFF
CS = 1 and TXD = 1and TXE = 1
CS = 1and (TXE = 0or TXD = 0)
CS = 1and TXD = 1and
XE = 1and No Fault
T
TOFF
Operation
Rising Edge on LIN
or CS = 1
Mode
Mode
VREN ON
RX ON
TX ON
Fault (thermal or time-out) or
FAULT/TXE = 0
VREN ON
RX ON
TX OFF
CS = 0
CS = 0
POWER-
DOWN
VREN OFF
RX OFF
TX OFF
TABLE 1-1:
State
OVERVIEW OF OPERATIONAL MODES
Transmitter Receiver
V
Operation
Comments
OFF Check CS; if low, then proceed to Ready mode. V > V and
BB BB(MIN)
REN
POR
OFF
OFF
If high, transitions to either T
or Operation internal supply is
OFF
mode, depending on T (MCP2003/A), or T
stable
XD
XD
and FAULT/T (MCP2004/A).
XE
Ready
OFF
ON
ON
ON
ON If CS is a high level, then proceed to Operation Bus Off state
or T mode.
OFF
Operation
ON If CS is a low level, then proceed to
Normal Operation
Power-Down mode. If FAULT/T is a low level, mode
XE
then proceed to Transmitter Off mode.
Power-Down
OFF
Activity
Detect
OFF On CS high level, proceed to Ready mode; then Low-Power mode
proceed to either Operation mode or TOFF mode.
MCP2003/2003A: Falling edge on WAKE will
put the device into Ready mode.
MCP2003/MCP2004: Falling edge on LIN bus
will put the device into Ready mode.
MCP2003A/MCP2004A: Rising edge on
LIN bus will put the device into Ready mode.
Transmitter Off
OFF
ON
ON If CS is a low level, then proceed to
FAULT/T is only
XE
Power-Down mode. If FAULT/T and T are available on
XE
XD
high, then proceed to Operation mode.
MCP2004/2004A
DS20002230G-page 6
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
1.4
Typical Applications
EXAMPLE 1-1:
TYPICAL MCP2003/2003A APPLICATION
+12
Optional Resistor and
Transient Suppressor
+12
50
43V
Master Node Only
+12
(Note 1)
3.9 k
1.0 µF
V
V
T
V
BB
Voltage Reg
DD
REN
4.7 k
T
1 k
XD
XD
XD
R
R
L
LIN Bus
XD
BUS
(2)
MMBZ27V
I/O
CS
WAKE
33 k
220 pF
Wake-up
V
SS
Note 1: For applications with current requirements of less than 20 mA, the connection to +12V can be deleted and voltage
to the regulator can be supplied directly from the V
pin.
REN
2: ESD protection diode.
EXAMPLE 1-2:
TYPICAL MCP2004/2004A APPLICATION
+12
Optional Resistor and
Transient Suppressor
+12
50
43V
Wake-up
Master Node Only
+12
1.0 µF
(Note 1)
220 k
V
L
V
V
T
Voltage Reg
BB
DD
REN
4.7 k
T
XD
XD
XD
1 k
R
R
XD
LIN Bus
BUS
CS/WAKE
FAULT/T
I/O
I/O
(2)
MMBZ27V
220 pF
XE
V
SS
100 nF
Note 1: For applications with current requirements of less than 20 mA, the connection to +12V can be deleted and voltage
to the regulator can be supplied directly from the V
pin.
REN
2: ESD protection diode.
2010-2016 Microchip Technology Inc.
DS20002230G-page 7
MCP2003/4/3A/4A
EXAMPLE 1-3:
TYPICAL LIN NETWORK CONFIGURATION
40m + Return
LIN Bus
1 k
V
BB
LIN Bus
MCP2000X
Slave 1
(MCU)
LIN Bus
MCP200X
LIN Bus
MCP200X
LIN Bus
MCP200X
Slave 2
(MCU)
Slave n < 23
(MCU)
Master
(MCU)
DS20002230G-page 8
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
1.5
TABLE 1-2:
Pin Name
Pin Descriptions
PINOUT DESCRIPTIONS
8-Lead
4x4
MCP2003/2003A
MCP2004/2004A
PDIP,
SOIC
DFN
Normal Operation
Normal Operation
R
1
2
3
1
Receive Data Output (OD),
HV tolerant
Receive Data Output (OD),
HV tolerant
XD
CS
2
3
Chip Select (TTL), HV tolerant
Chip Select/Local WAKE (TTL),
HV tolerant
WAKE
(MCP2003/2003A only)
Wake-up, HV tolerant
Fault Detect Output (OD),
Transmitter Enable (TTL),
HV tolerant
FAULT/T
XE
(MCP2004/2004A only)
T
4
4
Transmit Data Input (TTL),
HV tolerant
Transmit Data Input (TTL),
HV tolerant
XD
V
5
6
5
6
7
8
9
Ground
Ground
SS
L
LIN Bus (bidirectional)
Battery Positive
LIN Bus (bidirectional)
Battery Positive
BUS
V
V
7
BB
8
Voltage Regulator Enable Output Voltage Regulator Enable Output
REN
EP
—
Exposed Thermal Pad; do not
electrically connect or connect
Exposed Thermal Pad; do not
electrically connect or connect
to V
to V
SS
SS
Legend: TTL = TTL Input Buffer; OD = Open-Drain Output
If CS = 1 when the V supply is turned on, the device
1.5.1 RECEIVE DATA OUTPUT (RXD
)
BB
will proceed to Operation mode or TOFF mode (refer to
Figures 1-2 to 1-5) as soon as internal voltages
stabilize.
The Receive Data Output pin is an Open-Drain (OD)
output and follows the state of the LIN pin, except in
Power-Down mode.
This pin may also be used as a local wake-up input
(refer to Example 1-1). In this implementation, the
microcontroller I/O controlling the CS should be con-
verted to a high-impedance input, allowing the internal
pull-down resistor to keep CS low. An external switch,
or other source, can then wake-up both the transceiver
and the microcontroller (if powered). Refer to
Section 1.3 “Modes of Operation”, for detailed
operation of CS.
1.5.1.1
RXD Monitoring
The R pin is internally monitored. It has to be at a
XD
high level (> 2.5V typical) while L
Otherwise, an internal Fault will be created and the
device will transition to Transmitter Off mode. On the
MCP2004/2004A, the FAULT/T pin will be driven low
to indicate the Transmitter Off state.
is recessive.
BUS
XE
1.5.2
CHIP SELECT (CS)
This is the Chip Select input pin. An internal pull-down
resistor will keep the CS pin low. This is done to ensure
that no disruptive data will be present on the bus while
the microcontroller is executing a Power-on Reset and
an I/O initialization sequence. The pin must detect a high
level to activate the transmitter. An internal low-pass
filter, with a typical time constant of 10 µs, prevents
unwanted wake-up (or transition to Power-Down mode)
on glitches.
Note:
It is not recommended to tie CS high as
this can result in the device entering
Operation mode before the microcontrol-
ler is initialized and may result in
unintentional LIN traffic.
1.5.3
WAKE-UP INPUT (WAKE)
This pin is only available on the MCP2003/2003A.
The WAKE pin has an internal 800 kΩ pull-up to V
.
BB
If CS = 0 when the V supply is turned on, the device
BB
A falling edge on the WAKE pin causes the device to
wake from Power-Down mode. Upon waking, the
MCP2003/3A will enter Ready mode.
goes to Ready mode as soon as internal voltages sta-
bilize and stays there as long as the CS pin is held low
(0). In Ready mode, the receiver is on and the LIN
transmitter driver is off.
2010-2016 Microchip Technology Inc.
DS20002230G-page 9
MCP2003/4/3A/4A
Fault condition or by an external drive. While the trans-
mitter is disabled, the internal 30 k pull-up resistor on
1.5.4
FAULT/TXE
This pin is only available on the MCP2004/2004A. This
pin is bidirectional and allows disabling of the transmitter,
as well as Fault reporting related to disabling the
transmitter. This pin is an open-drain output with states
as defined in Table 1-3. The transmitter is disabled
whenever this pin is low (‘0’), either from an internal
the L
pin is also disconnected to reduce current.
BUS
Note:
The FAULT/T pin is true (‘0’) whenever
XE
the internal circuits have detected a short
or thermal excursion and have disabled
the L
output driver.
BUS
TABLE 1-3:
FAULT/TXE TRUTH TABLE
FAULT/T
XE
R
Out
LIN
I/O
Thermal
Override
XD
BUS
T
In
Definition
XD
External
Driven
Output
Input
L
H
V
V
OFF
H
L
FAULT, T driven low, L
(Note 1)
shorted to V
BUS BB
BB
XD
H
L
H
x
H
L
L
x
OFF
OFF
OFF
ON
x
H
H
H
H
L
H
H
H
L
OK
BB
GND
GND
OK
OK, data is being received from L
BUS
V
V
FAULT, transceiver in thermal shutdown
NO FAULT, the CPU is commanding the
BB
BB
x
x
x
transceiver to turn off the transmitter driver
Legend: x = don’t care.
Note 1: The FAULT/T is valid after approximately 25 µs after the T falling edge. This is to eliminate false Fault
XE
XD
reporting during bus propagation delays.
1.5.5
The Transmit Data input pin has an internal pull-up.
The LIN pin is low (dominant) when T is low and high
TRANSMIT DATA INPUT (TXD
)
1.5.7.1
The Bus Dominant Timer is an internal timer that
deactivates the L transmitter after approximately
Bus Dominant Timer
XD
BUS
(recessive) when T is high.
25 ms of Dominant state on the L
pin. The timer is
XD
BUS
reset on any recessive L
state.
BUS
For extra bus security, T
is internally forced to ‘1’
XD
whenever the transmitter is disabled, regardless of the
external T voltage.
The LIN bus transmitter will be reenabled after a
Recessive state on the L pin as long as CS is high.
XD
BUS
Disabling can be caused by the LIN bus being
externally held dominant or by T being driven low.
Additionally, on the MCP2004/2004A, the FAULT pin
will be driven low to indicate the Transmitter Off state.
1.5.5.1
If T
TXD Dominant Time-out
is driven low for longer than approximately
XD
XD
25 ms, the L
pin is switched to Recessive mode and
BUS
the part enters T
node from permanently driving the LIN bus dominant.
The transmitter is reenabled on the T rising edge.
mode. This is to prevent the LIN
OFF
1.5.8
BATTERY (VBB)
This is the Battery Positive Supply Voltage pin.
XD
1.5.6
GROUND (VSS
)
1.5.9
VOLTAGE REGULATOR ENABLE
OUTPUT (VREN
This is the External Voltage Regulator Enable pin. The
)
This is the Ground pin.
1.5.7
LIN BUS (LBUS)
open source output is pulled high to V in all modes,
BB
except Power-Down.
The bidirectional LIN Bus pin (L
) is controlled by the
BUS
T
input. L
has a current-limited open-collector
XD
BUS
1.5.10
EXPOSED THERMAL PAD (EP)
output. To reduce EMI, the edges, during the signal
changes, are slope controlled, and include corner
rounding control for both falling and rising edges.
Do not electrically connect or connect to V
.
SS
The internal LIN receiver observes the activities on the
LIN bus and matches the output signal, R , to follow
XD
the state of the L
pin.
BUS
DS20002230G-page 10
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
If the MCP2003/4 is placed into Operational mode, the
1.6
MCP2003/4 and MCP2003A/4A
Difference Details
V
to L
pull-up resistor is automatically connected,
BB
BUS
which will raise the LIN bus to a Recessive level; then
putting the device into Power-Down mode may cause
The differences between the MCP2003/4 and the
MCP2003A/4A devices are isolated to the wake-up
functionality. The changes were implemented to make
the device more robust to LIN bus conditions outside of
the normal operating conditions. The MCP2003/4 will
wake-up from Power-Down mode during any LIN falling
edge held low longer than 20 µs.
L
to be floating, and thus, wake-up all bus nodes. To
BUS
prevent this, the designer should ensure T (MCP2003)
XD
or T (MCP2004) is held low until valid bus activity is
XE
verified (see Figure 1-6). This will ensure the transceiver
transitions from Ready mode to Transmitter Off mode
until bus activity can be verified.
In the case where a LIN system is designed to minimize
standby current by disconnecting all bus pull-up resis-
tors (including the external master pull-up resistor to
In the case of valid bus activity, the transceiver can shift to
Operation mode; while if there is no bus activity, the
device can again be placed into Power-Down mode. The
design practices needed to accomplish this are fully
detailed in Tech Brief TB3067, “MCP2003 Power-Down
Mode and Wake-up Handling in the Case of LIN Bus
Loss” (DS93067).
V
), the original MCP2003/4 could wake-up if the float-
BB
ing bus drifted to a valid low level. The MCP2003A/4A
revisions were modified to require a rising edge after a
valid low level. This will prevent an undesired system
wake-up in this scenario, while maintaining functional
capability with the original version.
The revised MCP2003A/4A devices now eliminate the
need for firmware to prevent system wide wake-up.
The revised devices now require a longer valid bus low
It should be noted that the original MCP2003/4 meets
all LIN transceiver specification requirements and
modules can be designed to pass all LIN system
requirements. However, when all bus pull-up resistors
are disconnected, the MCP2003/4 requires the module
designer to write firmware to monitor the LIN bus, after
any wake-up event, to prevent the transceiver from
automatically transitioning from Ready mode to
Operational mode.
(see updated t
value in Section 2.3 “DC Specifi-
BDB
cations” and Figure 2-7), which enables a rising edge
detect circuit. The device will now only wake-up after a
rising edge, following a low longer than t
. While
BDB
the module designer can still hold T (MCP2003) or
XD
T
(MCP2004) low during wake-up to enter Transmitter
XE
Off mode from Ready mode, it is not required to prevent
an advertent system wake-up.
In addition to the longer t
value, the time from wake-
BDB
up detect to V
enable is shortened, as documented
REN
in Section 2.3 “DC Specifications”.
FIGURE 1-6:
MCP2003/2004 SWITCHING TIMING DIAGRAM FOR THE FORCED
POWER-DOWN MODE SEQUENCE
tTx2CS ꢀꢁꢂꢂꢀQV
tCSactive ꢀꢁꢂꢂꢀV
CS
TXD State Depending
on how the Slave
Microcontroller is
Powered
TXD to ‘0’
VREN
Forced
Externally
TXD
LBUS
LIN Bus
Disconnected
Power-Down
Mode after Master
SLEEP Instruction
Ready
Mode
Transmitter Off
Mode
Power-Down
Mode
State
2010-2016 Microchip Technology Inc.
DS20002230G-page 11
MCP2003/4/3A/4A
2.0
2.1
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
V
V
V
V
V
V
V
V
V
V
DC Voltage on R , T , FAULT/T , CS .............................................................................................. -0.3 to +43V
XD XD XE
IN
DC Voltage on WAKE and V
............................................................................................................. -0.3 to +V
BB
IN
REN
Battery Voltage, Continuous, Non-Operating (Note 1)........................................................................... -0.3 to +40V
Battery Voltage, Non-Operating (LIN bus recessive) (Note 2)............................................................... -0.3 to +43V
Battery Voltage, Transient ISO 7637 Test 1..................................................................................................... -200V
Battery Voltage, Transient ISO 7637 Test 2a...................................................................................................+150V
Battery Voltage, Transient ISO 7637 Test 3a................................................................................................... -300V
Battery Voltage, Transient ISO 7637 Test 3b...................................................................................................+200V
BB
BB
BB
BB
BB
BB
Bus Voltage, Continuous..................................................................................................................... -18 to +40V
LBUS
LBUS
Bus Voltage, Transient (Note 3).......................................................................................................... -27 to +43V
I
Bus Short-Circuit Current Limit....................................................................................................................200 mA
LBUS
ESD Protection on LIN, V , WAKE (IEC 61000-4-2) (Note 4) .............................................................................. ±8 KV
BB
ESD Protection on LIN, V (Human Body Model) (Note 5) .................................................................................. ±8 KV
BB
ESD Protection on All Other Pins (Human Body Model) (Note 5) .......................................................................... ±4 KV
ESD Protection on All Pins (Charge Device Model) (Note 6) ................................................................................. ±2 KV
ESD Protection on All Pins (Machine Model) (Note 7)............................................................................................±200V
Maximum Junction Temperature.............................................................................................................................150C
Storage Temperature...................................................................................................................................-65 to +150C
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device, at those or any other conditions above
those indicated in the operational listings of this specification, is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
Note 1: LIN 2.x compliant specification.
2: SAE J2602 compliant specification.
3: ISO 7637/1 load dump compliant (t < 500 ms).
4: According to IEC 61000-4-2, 330 ohm, 150 pF and Transceiver EMC Test Specifications [2] to [4]. For
WAKE pin to meet the specification, a series resistor must be in place (refer to Example 1-2).
5: According to AEC-Q100-002/JESD22-A114.
6: According to AEC-Q100-011B.
7: According to AEC-Q100-003/JESD22-A115.
2.2
Nomenclature Used in This Document
Some terms and names used in this data sheet deviate from those referred to in the LIN specifications. Equivalent
values are shown below.
LIN 2.1 Name
Term Used in the Following Tables
Definition
ECU operating voltage
V
not used
BAT
V
V
Supply voltage at device pin
Current limit of driver
Recessive state
SUP
BB
SC
I
I
BUS_LIM
V
V
IH(LBUS)
BUSREC
BUSDOM
V
V
Dominant state
IL(LBUS)
DS20002230G-page 12
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
2.3
DC Specifications
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
= 6.0V to 30.0V, T = -40°C to +125°C
DC Specifications
V
BB
A
Parameter
Power
Sym.
Min.
Typ.
Max.
Units
Conditions
V
Quiescent Operating
I
—
—
90
75
150
120
µA
µA
Operating mode, bus is
Recessive (Note 1)
BB
BBQ
Current
V
Transmitter Off
I
Transmitter off, bus is
BB
BBTO
Current
Recessive (Note 1)
V
V
Power-Down Current
Current
I
—
-1
5
15
1
µA
BB
BBPD
I
—
mA
V
V
= 12V, GND to V
= 0-27V
,
BB
BB
BBNOGND
BB
with V Floating
SS
LIN
Microcontroller Interface
High-Level Input Voltage
V
2.0
-0.3
-2.5
-10
—
—
—
—
30
0.8
—
V
V
IH
(T , FAULT/T
)
XD
XE
Low-Level Input Voltage
(T , FAULT/T
V
IL
)
XE
XD
High-Level Input Current
(T , FAULT/T
I
µA
µA
V
Input voltage = 4.0V
Input voltage = 0.5V
IH
)
XE
XD
Low-Level Input Current
(T , FAULT/T
I
—
IL
)
XE
XD
High-Level Voltage (V
)
V
-0.3
-40
—
—
—
—
V
+ 0.3
REN
HVREN
BB
High-Level Output Current
(V
I
-10
-35
30
mA Output voltage = V – 0.5V
BB
HVREN
)
REN
-125
2.0
Output voltage = V -2.0V
BB
High-Level Input Voltage
(CS)
V
V
V
Through a current-limiting
resistor
IH
Low-Level Input Voltage
(CS)
V
-0.3
—
—
—
—
—
—
—
0.8
10.0
5.0
—
IL
High-Level Input Current
(CS)
I
µA
µA
V
Input voltage = 4.0V
Input voltage = 0.5V
IH
Low-Level Input Current
(CS)
I
—
IL
Low-Level Input Voltage
(WAKE)
V
V
– 4.0V
IL
BB
Low-Level Output Voltage
V
—
-1
0.4
-1
V
I
= 2 mA
IN
OL
(R
)
XD
High-Level Output Current
(R
I
µA
V
= V , V
= 5.5V
OH
LIN
BB
RXD
)
XD
Note 1: Internal current limited; 2.0 ms maximum recovery time (R
= 0, TX = 0.4 V
, V
= V ).
LBUS
REG LBUS BB
2: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
2010-2016 Microchip Technology Inc.
DS20002230G-page 13
MCP2003/4/3A/4A
2.3
DC Specifications (Continued)
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
DC Specifications
Parameter
V
= 6.0V to 30.0V, T = -40°C to +125°C
BB
A
Sym.
Min.
Typ.
Max.
Units
Conditions
Bus Interface
High-Level Input Voltage
Low-Level Input Voltage
Input Hysteresis
V
0.6 V
-8
—
—
—
—
—
V
V
V
Recessive state
Dominant state
– V
IL(LBUS)
IH(LBUS)
BB
V
0.4 V
BB
IL(LBUS)
V
—
0.175 V
200
V
IH(LBUS)
HYS
BB
Low-Level Output Current
I
40
mA Output voltage = 0.1 V
,
OL(LBUS)
BB
V
= 12V
BB
High-Level Output Current
Pull-up Current on Input
I
—
5
—
—
20
µA
µA
OH(LBUS)
I
180
~30 k internal pull-up
@ V = 0.7 V
PU(LBUS)
IH(LBUS)
BB
Short-Circuit Current Limit
High-Level Output Voltage
Driver Dominant Voltage
Driver Dominant Voltage
Driver Dominant Voltage
Driver Dominant Voltage
I
50
0.9 V
—
—
—
200
mA (Note 1)
SC
V
V
V
OH(LBUS)
BB
BB
V_
—
1.2
2.0
—
V
V
V
V
V
V
V
V
= 7V, R
= 500
LOSUP
BB
BB
BB
BB
LOAD
V_
—
—
= 18V, R
= 500
LOAD
HISUP
V_
– 1k
0.6
0.8
-1
—
= 7V, R
= 1 k
= 1 k
LOSUP
LOAD
V_
– 1k
—
—
= 18V, R
LOAD
HISUP
BUS_PAS_DOM
Input Leakage Current
(at the receiver during
Dominant bus level)
I
-0.4
—
mA Driver off, V
= 0V,
BUS
V
= 12V
BB
Input Leakage Current
(at the receiver during
Recessive bus level)
I
—
12
1.0
—
20
µA
µA
Driver off, 8V < V < 18V,
BB
BUS_PAS_REC
8V < V
< 18V,
BUS
V
V
BUS
BB
Leakage Current
(disconnected from ground)
I
-10
+10
GND
= V
,
BUS_NO_GND
DEVICE
BB
0V < V
< 18V,
BUS
V
= 12V
BB
Leakage Current
I
—
10
µA
V
V
= GND,
BUS_NO_VBB
BB
(disconnected from V
)
0 < V
< 18V (Note 2)
BB
BUS
Receiver Center Voltage
V
0.475 V
0.5 V
0.525 V
V
V
= (V
/2
+
BUS_CNT
BB
BB
BB
BUS_CNT
IL(LBUS)
IH(LBUS)
Slave Termination
R
C
20
—
30
—
47
50
k
SLAVE
Capacitance of Slave
Node
pF
SLAVE
Note 1: Internal current limited; 2.0 ms maximum recovery time (R
= 0, TX = 0.4 V
, V
= V ).
LBUS
REG LBUS BB
2: Node has to sustain the current that can flow under this condition; bus must be operational under this
condition.
DS20002230G-page 14
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
2.4
AC Specifications
Electrical Characteristics: Unless otherwise indicated, all limits are specified for
AC Characteristics
Parameter
V
= 6.0V to 27.0V; T = -40°C to +125°C
BB
A
Sym.
Min. Typ. Max. Units
Test Conditions
Bus Interface – Constant Slope Time Parameters
Slope Rising and Falling Edges
t
3.5
—
—
—
22.5
4.0
µs 7.3V V 18V
BB
SLOPE
Propagation Delay of
Transmitter
t
µs
t
t
= max (t
TRANSPDR
or
TRANSPD
TRANSPD
)
TRANSPDF
Propagation Delay of Receiver
t
—
—
—
6.0
2.0
µs
µs
t
= max (t
or t
)
RECPDF
RECPD
RECPD
RECPDR
Symmetry of Propagation
Delay of Receiver Rising Edge
w.r.t. Falling Edge
t
-2.0
t
= max (t
– t
)
RECPDR
RECSYM
RECSYM
RECPDF
R
2.4 to V , C
20 pF
RXD
CC
RXD
Symmetry of Propagation
Delay of Transmitter Rising
Edge w.r.t. Falling Edge
t
-2.0
—
2.0
µs
t
(t
= max
TRANSSYM
TRANSSYM
– t
)
TRANSPDF
TRANSPDR
Time to Sample FAULT/T for
Bus Conflict Reporting
t
—
—
—
32.5
—
µs
—
t
(t
= max
XE
FAULT
FAULT
+
+ t
)
RECPD
TRANSPD TSLOPE
Duty Cycle 1 @ 20.0 kbit/sec
0.396
C
; R
Conditions:
BUS
BUS
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500,
TH
TH
= 0.744 x V
= 0.581 x V
,
REC(MAX)
DOM(MAX)
BB
,
BB
V
= 7.0V – 18V, t
= 50 µs,
BB
BIT
D1 = t
/2 x t
)
BIT
BUS_REC(MIN)
Duty Cycle 2 @ 20.0 kbit/sec
Duty Cycle 3 @ 10.4 kbit/sec
Duty Cycle 4 @ 10.4 kbit/sec
—
0.417
—
—
—
—
0.581
—
—
—
C
; R
Conditions:
BUS
BUS
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500,
TH
TH
= 0.284 x V
= 0.422 x V
,
REC(MAX)
BB
,
DOM(MAX)
= 7.6V – 18V, t
BB
V
= 50 µs,
BB
BIT
D2 = t
/2 x t
)
BIT
BUS_REC(MAX)
—
C
; R
Conditions:
BUS
BUS
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500,
TH
TH
= 0.778 x V
= 0.616 x V
,
REC(MAX)
DOM(MAX)
= 7.0V – 18V, t
BB
,
BB
V
= 96 µs,
BB
BIT
D3 = t
/2 x t
)
BIT
BUS_REC(MIN)
0.590
C
; R
Conditions:
BUS
BUS
1 nF; 1 k | 6.8 nF; 660 | 10 nF; 500,
TH
= 0.251 x V
,
REC(MAX)
BB
TH
= 0.389 x V
,
DOM(MAX)
BB
V
= 7.6V – 18V, t
= 96 µs,
BB
BIT
D4 = t
/2 x t
BIT
BUS_REC(MAX)
Wake-up Timing
Bus Activity Debounce Time
t
5
—
70
—
30
—
—
—
20
125
150
90
µs MCP2003/2004
µs MCP2003A/2004A
µs MCP2003/2004
µs MCP2003A/2004A
µs
BDB
30
35
10
—
—
—
Bus Activity to V
On
t
BACTVE
REN
WAKE to V
On
t
t
150
150
80
REN
WAKE
Chip Select to V
Chip Select to V
On
Off
µs
µs
V
V
floating
floating
REN
REN
CSOR
REN
REN
t
CSPD
2010-2016 Microchip Technology Inc.
DS20002230G-page 15
MCP2003/4/3A/4A
(1)
2.5
Thermal Specifications
Parameter
Symbol
Typ.
Max.
Units
Test Conditions
Recovery Temperature
+140
+150
1.5
—
—
C
C
ms
RECOVERY
Shutdown Temperature
SHUTDOWN
Short-Circuit Recovery Time
Thermal Package Resistances
Thermal Resistance, 8L-DFN
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
t
5.0
THERM
JA
JA
JA
35.7
89.3
—
—
—
C/W
C/W
C/W
149.5
Note 1: The maximum power dissipation is a function of T
, and ambient temperature, T . The maximum
JMAX JA
A
allowable power dissipation at an ambient temperature is P = (T
– T ) . If this dissipation is
D
JMAX
A
JA
exceeded, the die temperature will rise above +150C and the device will go into thermal shutdown.
DS20002230G-page 16
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
2.6
Typical Performance Curves
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, V = 6.0V to 18.0V, T = -40°C to +125°C.
BB
A
FIGURE 2-1:
TYPICAL IBBQ
FIGURE 2-3:
TYPICAL IBBTO
0.14
0.12
0.1
0.12
0.1
0.08
0.06
0.04
0.02
-40C
-40C
0.08
0.06
0.04
0.02
ꢀ25C
ꢀ85C
ꢀ125C
ꢀ25C
ꢀ85C
ꢀ125C
0
0
6
7.3
12
14.4
18
6V
7.3V
12V
14.4V
18V
VBB (V)
VBB (V)
FIGURE 2-2:
TYPICAL IBBPD
0.008
0.007
0.006
0.005
0.004
0.003
0.002
0.001
-40C
ꢀ25C
ꢀ85C
ꢀ125C
0
6
7.3
12
14.4
18
VBB (V)
2010-2016 Microchip Technology Inc.
DS20002230G-page 17
MCP2003/4/3A/4A
2.7
Timing Diagrams and Specifications
BUS TIMING DIAGRAM
FIGURE 2-4:
T
50%
50%
XD
.95 V
.50 V
L
LBUS
BUS
BB
0.05 V
LBUS
0.0V
T
T
TRANSPDR
TRANSPDF
T
T
RECPDF
RECPDR
R
XD
50%
50%
Internal T /R
XD XD Match
Match
Match
Match
Match
Compare
FAULT Sampling
T
T
FAULT
FAULT
Hold
Value
Hold
Value
FAULT/T Output
Stable
Stable
Stable
XE
FIGURE 2-5:
CS TO VREN TIMING DIAGRAM
CS
T
CSOR
V
BB
V
REN
Off
T
CSPD
DS20002230G-page 18
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
FIGURE 2-6:
LBUS
MCP2003/4 REMOTE WAKE-UP
0.4 VBB
tBDB
tBACTIVE
VBB
VREN
FIGURE 2-7:
MCP2003A/4A REMOTE WAKE-UP
LBUS
0.4 VBB
tBDB
tBACTIVE
VBB
VREN
2010-2016 Microchip Technology Inc.
DS20002230G-page 19
MCP2003/4/3A/4A
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (4x4x0.9 mm)
Example:
2003
e
3
E/MD
1642
256
8-Lead PDIP (300 mil)
Example:
MCP2003
e
3
E/P^256
1642
8-Lead SOIC (150 mil)
Example:
MCP2003E
e
3
SN1642
256
NNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
®
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS20002230G-page 20
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 1 of 2
2010-2016 Microchip Technology Inc.
DS20002230G-page 21
MCP2003/4/3A/4A
8-Lead Plastic Dual Flat, No Lead Package (MD) – 4x4x0.9 mm Body [DFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-131E Sheet 2 of 2
DS20002230G-page 22
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2016 Microchip Technology Inc.
DS20002230G-page 23
MCP2003/4/3A/4A
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
DS20002230G-page 24
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
2010-2016 Microchip Technology Inc.
DS20002230G-page 25
MCP2003/4/3A/4A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002230G-page 26
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010-2016 Microchip Technology Inc.
DS20002230G-page 27
MCP2003/4/3A/4A
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DS20002230G-page 28
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
APPENDIX A: REVISION HISTORY
Revision G (December 2016)
The following is the list of modifications”
1. Added note to page 1 header: “Not recommended
for new designs”.
2. Updated Section 3.1 “Package Marking
Information”.
3. Minor typographical corrections.
Revision F (November 2014)
The following is the list of modifications:
1. Updated typical application circuits with values
used during ESD tests.
Revision E (October 2013)
The following is the list of modifications:
1. Added additional specification for IHVREN in
Section 2.3 “DC Specifications”.
2. Clarified wake-up on L
functionality.
BUS
3. Added R monitoring description.
XD
Revision D (December 2011)
The following is the list of modifications:
1. Added the MCP2003A and MCP2004A devices
and related information throughout the docu-
ment.
2. Updated Figures 1.2, 1.3, 1.4, 1.5, 2.6, 2.7.
Revision C (August 2010)
The following is the list of modifications:
1. Updated all references of Sleep mode to Power-
Down mode, and updated the Max. parameter
for Duty Cycle 2 in Section 2.4 “AC Specifica-
tions”.
Revision B (July 2010)
The following is the list of modifications:
1. Added Section 2.2 “Nomenclature Used in
This Document”, and added the “Capacitance
of Slave Node” parameter to Section 2.3 “DC
Specifications”.
Revision A (March 2010)
• Original release of this document.
2010-2016 Microchip Technology Inc.
DS20002230G-page 29
MCP2003/4/3A/4A
NOTES:
DS20002230G-page 30
2010-2016 Microchip Technology Inc.
MCP2003/4/3A/4A
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office
.
PART NO.
Device
X
/XX
Examples:
a)
b)
c)
d)
MCP2003A-E/MD: Extended Temperature,
8L-DFN package
Temperature
Range
Package
MCP2003A-E/P:
Extended Temperature,
8L-PDIP package
MCP2003A-E/SN: Extended Temperature,
8L-SOIC package
Device:
MCP2003: LIN Transceiver with WAKE pins, wake-up on
falling edge of LBUS
MCP2003AT-E/MD: Tape and Reel,
Extended Temperature,
MCP2003T: LIN Transceiver with WAKE pins, wake-up on
falling edge of LBUS (Tape and Reel) (DFN and
SOIC only)
8L-DFN package
e)
MCP2003AT-E/SN: Tape and Reel,
Extended Temperature,
MCP2003A: LIN Transceiver with WAKE pins, wake-up on
rising edge of LBUS
8L-SOIC package
MCP2003AT: LIN Transceiver with WAKE pins, wake-up on
rising edge of LBUS (Tape and Reel) (DFN and
SOIC only)
a)
b)
c)
d)
MCP2004-E/MD: Extended Temperature,
8L-DFN package
MCP2004: LIN Transceiver with FAULT/TXE pins, wake-up
on falling edge of LBUS
MCP2004-E/P:
Extended Temperature,
8L-PDIP package
MCP2004T: LIN Transceiver with FAULT/TXE pins, wake-up
on falling edge of LBUS (Tape and Reel) (DFN
and SOIC only)
MCP2004A-E/SN: Extended Temperature,
8L-SOIC package
MCP2004AT-E/MD: Tape and Reel,
Extended Temperature,
MCP2004A: LIN Transceiver with FAULT/TXE pins, wake-up
on rising edge of LBUS
8L-DFN package
MCP2004AT: LIN Transceiver with FAULT/TXE pins, wake-up
on rising edge of LBUS (Tape and Reel) (DFN
and SOIC only)
e)
MCP2004AT-E/SN: Tape and Reel,
Extended Temperature,
8L-SOIC package
Temperature Range:
Package:
E
=
=
-40°C to +125°C
MD
Plastic Dual Flat, No Lead Package – 4x4x0.9mm
Body, 8-Lead
P
SN
=
=
Plastic Dual In-Line – 300 mil Body, 8-Lead
Plastic Small Outline – Narrow 3.90 mm Body, 8-Lead
2010-2016 Microchip Technology Inc.
DS20002230G-page 31
MCP2003/4/3A/4A
NOTES:
DS20002230G-page 32
2010-2016 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, CryptoMemory,
CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KEE
LOQ,
K
EEL
OQ logo, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, RightTouch, SAM-BA, SpyNIC, SST, SST
Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, Mindi, MiWi, motorBench, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PureSilicon, QMatrix, RightTouch logo, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
are for its PIC® MCUs and dsPIC® DSCs, KEE OQ® code hopping
L
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2010-2016, Microchip Technology Incorporated, All Rights
Reserved.
ISBN: 978-1-5224-1230-4
== ISO/TS 16949 ==
2010-2016 Microchip Technology Inc.
DS20002230G-page 33
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DS20002230G-page 34
2010-2016 Microchip Technology Inc.
11/07/16
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