MCP23016T-I/ML_技术文档

MCP23016

16-Bit I²C^™I/O Expander

Features

Package Types

• 16-bit remote bidirectional I/O port

- 16 I/O pins default to 16 inputs

PDIP, SOIC, SSOP

Vss

GP1.0

GP1.1

GP1.2

GP1.3

INT

GP1.4

VSS

CLK

TP

GP1.5

GP1.6

GP1.7

SCL

• 1

2

3

4

5

6

7

8

28

27

26

25

24

23

22

21

20

19

18

17

16

15

GP0.7

GP0.6

GP0.5

GP0.4

GP0.3

GP0.2

GP0.1

GP0.0

VDD

VSS

• Fast I²C™ bus clock frequency (0 - 400 kbits/s)

• Three hardware address pins allow use of up to

eight devices

• High-current drive capability per I/O: ±25 mA

• Open-drain interrupt output on input change

• Interrupt port capture register

9

10

11

12

13

14

A2

A1

A0

SDA

• Internal Power-On Reset (POR)

• Polarity inversion register to configure the polarity

of the input port data

• Compatible with most microcontrollers

• Available temperature range:

- Industrial (I): -40°C to +85°C

QFN

28272625242322

GP1.2

1

21

GP0.3

GP0.2

GP0.1

GP0.0

VDD

GP1.3

INT

20

19

18

17

16

15

2

3

4

5

6

7

CMOS Technology

MCP23016

GP1.4

VSS

• Operating Supply Voltage: 2.0V to 5.5V

• Low standby current

VSS

A2

CLK

TP

8 9 1011121314

Packages

• 28-pin PDIP, 300 mil; 28-pin SOIC, 300 mil

• 28-pin SSOP, 209 mil; 28-pin QFN, 6x6 mm

Block Diagram

Low Pass

Filter

Interrupt

INT

Logic

A0

A1

A2

IARES

16 Bits

Address

I²C™ Bus

SCL

SDA

Decoder

Interface/

Protocol

Handler

GP0.0 to GP0.7

GP1.0 to GP1.7

I/O

Port

I²C™ Bus

Control

CLKIN

TP

Clock

Gen

Write pulse

Read pulse

Power-on

Reset

VDD

VSS

8-Bit

Configuration

Registers

Control

DS20090C-page 1

MCP23016

NOTES:

DS20090C-page 2

MCP23016

input or output register. The polarity of the read register

can be inverted with the polarity inversion register (see

Section 1.7.3, “Input Polarity Registers”). All

registers can be read by the system master.

1.0

DEVICE OVERVIEW

The MCP23016 device provides 16-bit, general

purpose, parallel I/O expansion for I²C bus

applications.

The open-drain interrupt output is activated when any

input state differs from its corresponding input port

register state. This is used to indicate to the system

master that an input state has changed. The interrupt

capture register captures port value at this time. The

Power-on Reset sets the registers to their default val-

ues and initializes the device state machine.

Three device inputs (A0 - A2) determine the I²C

address and allow up to eight I/O expander devices to

share the same I²C bus.

This device includes high-current drive capability, low

supply current and individual I/O configuration. I/O

expanders provide a simple solution when additional

I/Os are needed for ACPI, power switches, sensors,

push buttons, LEDs and so on.

The MCP23016 consists of multiple 8-bit configuration

registers for input, output and polarity selection. The

system master can enable the I/Os as either inputs or

outputs by writing the I/O configuration bits. The data

for each input or output is kept in the corresponding

1.1

Pin Descriptions

TABLE 1-1:

PINOUT DESCRIPTION

PDIP,

SOIC,

SSOP

QFN

Pin No.

I/O/P

Type

Buffer

Pin Name

Description

Type

Pin No.

CLK

9

10

2

6

7

I

ST

—

Clock source input

TP

O

Test Pin (This pin must be left floating)

D0 digital input/output for GP1

D1 digital input/output for GP1

D2 digital input/output for GP1

D3 digital input/output for GP1

D4 digital input/output for GP1

D5 digital input/output for GP1

D6 digital input/output for GP1

D7 digital input/output for GP1

D0 digital input/output for GP0

D1 digital input/output for GP0

D2 digital input/output for GP0

D3 digital input/output for GP0

D4 digital input/output for GP0

D5 digital input/output for GP0

D6 digital input/output for GP0

D7 digital input/output for GP0

Serial clock input

GP1.0

GP1.1

GP1.2

GP1.3

GP1.4

GP1.5

GP1.6

GP1.7

GP0.0

GP0.1

GP0.2

GP0.3

GP0.4

GP0.5

GP0.6

GP0.7

SCL

27

28

1

I/O

I

TTL

ST

3

4

5

2

7

4

11

12

13

21

22

23

24

25

26

27

28

14

15

6

8

9

ST

10

18

19

20

21

22

23

24

25

11

12

3

ST

TTL

ST

SDA

I/O

O

ST

Serial data I/O

INT

OD

ST

Interrupt output

A0

16

17

18

1, 8, 19

20

13

14

15

5, 16, 26

17

I

Address input 1

A1

I

ST

Address input 2

A2

I

ST

Address input 3

VSS

P

—

Ground reference for logic and I/O pins

Positive supply for logic and I/O pins

VDD

P

—

DS20090C-page 3

MCP23016

A 1 MHz (typ.) internal clock is needed for the device to

function properly. The internal clock can be measured

on the TP pin. Recommended REXT and CEXT values

are shown in Table 1-2.

1.2

Power-on Reset (POR)

The on-chip POR circuit holds the chip in RESET until

VDD has reached a high enough level to deactivate the

POR circuit (i.e., release RESET). A maximum rise

time for VDD is specified in the electrical specifications.

Note:

Set IARES = 1 to measure the clock

output on TP.

When the device starts normal operation (exits the

RESET condition), device operating parameters

(voltage, frequency, temperature) must be met to

ensure proper operation.

TABLE 1-2:

RECOMMENDED VALUES

REXT

CEXT

3.9 kΩ

33 pF

1.3

Power-up Timer (PWRT)

2

1.5

I C Bus Interface/ Protocol

Handler

The Power-up Timer provides a 72 ms nominal time-

out on power-up, keeping the device in RESET and

allowing VDD to rise to an acceptable level.

This block manages the functionality of the I²C bus

interface and protocol handling. The MCP23016

supports the following commands:

The power-up time delay will vary from chip-to-chip due

to VDD, temperature and process variation. See

Table 2-4 for details (TPWRT, parameter 3).

TABLE 1-3:

COMMAND BYTE TO

REGISTER RELATIONSHIP

1.4

Clock Generator

Command Byte

Result

The MCP23016 uses an external RC circuit to

determine the internal clock speed. The user must

connect R and C to the MCP23016, as shown in

Figure 1-1.

0h

1h

2h

3h

4h

5h

6h

7h

8h

9h

Ah

Bh

Access to GP0

Access to GP1

Access to OLAT0

Access to OLAT1

FIGURE 1-1:

CLOCK CONFIGURATION

Access to IPOL0

VDD

Access to IPOL1

Access to IODIR0

REXT

Internal Clock

Access to IODIR1

CLK

Access to INTCAP0 (Read-Only)

Access to INTCAP1 (Read-Only)

Access to IOCON0

Access to IOCON1

CEXT

VSS

MCP23016

1.6

Address Decoder

The last three LSb of the 7-bit address are user-defined

(see Table 1-4). Three hardware pins (<A2:A0>) define

these bits.

TABLE 1-4:

DEVICE ADDRESS

A2

0

1

0

A1

A0

DS20090C-page 4

MCP23016

1.7

Register Block

The register block contains the Configuration and Port registers, as shown in Table 1-5.

TABLE 1-5:

REGISTER SUMMARY

Value on

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

POR

Port Registers

GP0

GP1

GP0.7

GP1.7

OL0.7

OL1.7

GP0.6

GP1.6

OL0.6

OL1.6

GP0.5

GP1.5

OL0.5

OL1.5

GP0.4

GP1.4

OL0.4

OL1.4

GP0.3

GP1.3

OL0.3

OL1.3

GP0.2

GP1.2

OL0.2

OL1.2

GP0.1

GP1.1

OL0.1

OL1.1

GP0.0 0000 0000

OL0.0 0000 0000

OL1.0 0000 0000

OLAT0

OLAT1

Configuration Registers

IPOL0

IPOL1

IGP0.7

IGP1.7

IOD0.7

IOD1.7

ICP0.7

ICP1.7

—

IGP0.6

IGP1.6

IOD0.6

IOD1.6

ICP0.6

ICP1.6

—

IGP0.5

IGP1.5

IOD0.5

IOD1.5

ICP0.5

ICP1.5

—

IGP0.4

IGP1.4

IOD0.4

IOD1.4

ICP0.4

ICP1.4

—

IGP0.3

IGP1.3

IOD0.3

IOD1.3

ICP0.3

ICP1.3

—

IGP0.2

IGP1.2

IOD0.2

IOD1.2

ICP0.2

ICP1.2

—

IGP0.1

IGP1.1

IOD0.1

IOD1.1

ICP0.1

ICP1.1

—

IGP0.0 0000 0000

IGP1.0 0000 0000

IOD0.0 1111 1111

IOD1.0 1111 1111

ICP0.0 xxxx xxxx

ICP1.0 xxxx xxxx

IARES ---- ---0

IODIR0

IODIR1

INTCAP0

INTCAP1

IOCON0

IOCON1

—

Legend: ‘1’ bit is set, ‘0’ bit is cleared, x = unknown, — = unimplemented.

DS20090C-page 5

MCP23016

1.7.1

DATA PORT REGISTERS

Two registers provide access to the two GPIO ports:

• GP0 (provides access to data port GP0)

• GP1 (provides access to data port GP1)

A read from this register provides status on pins of

these ports. A write to these registers will modify the

output latch registers (OLAT0, OLAT1) and data output.

REGISTER 1-1:

R/W-0

GP0 - GENERAL PURPOSE I/O PORT REGISTER 0

R/W-0

GP0.6

R/W-0

GP0.5

R/W-0

GP0.4

R/W-0

GP0.3

R/W-0

GP0.2

R/W-0

GP0.1

R/W-0

GP0.0

bit 0

GP0.7

bit 7

bit 7-0

GP0.0:GP0.7: Reflects the logic level on the pins.

1= Logic ‘1’

0= Logic ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

REGISTER 1-2:

R/W-0

GP1 - GENERAL PURPOSE I/O PORT REGISTER 1

R/W-0

GP1.6

R/W-0

GP1.5

R/W-0

GP1.4

R/W-0

GP1.3

R/W-0

GP1.2

R/W-0

GP1.1

R/W-0

GP1.0

bit 0

GP1.7

bit 7

bit 7-0

GP1.0:GP1.7: Reflects the logic level on the pins.

1= Logic ‘1’

0= Logic ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

DS20090C-page 6

MCP23016

1.7.2

OUTPUT LATCH REGISTERS

Two registers provide access to the two port output

latches:

• OLAT0 (provides access to the output latch for

port GP0)

• OLAT1 (provides access to the output latch for

port GP1)

A read from these registers results in a read of the latch

that controls the output and not the actual port. A write

to these registers updates the output latch that controls

the output.

REGISTER 1-3:

R/W-0

OLAT0 - OUTPUT LATCH REGISTER 0

R/W-0

OL0.6

R/W-0

OL0.5

R/W-0

OL0.4

R/W-0

OL0.3

R/W-0

OL0.2

R/W-0

OL0.1

R/W-0

OL0.0

bit 0

OL0.7

bit 7

bit 7-0

OL0.0:O0.7: Reflects the logic level on the output latch.

1= Logic ‘1’

0= Logic ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

REGISTER 1-4:

R/W-0

OLAT1 - OUTPUT LATCH REGISTER 1

R/W-0

OL1.6

R/W-0

OL1.5

R/W-0

OL1.4

R/W-0

OL1.3

R/W-0

OL1.2

R/W-0

OL1.1

R/W-0

OL1.0

bit 0

OL1.7

bit 7

bit 7-0

OL1.0:O1.7: Reflects the logic level on the output latch.

1= Logic ‘1’

0= Logic ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

DS20090C-page 7

MCP23016

1.7.3

INPUT POLARITY REGISTERS

These registers allow the user to configure the polarity

of the input port data (GP0 and GP1). If a bit in this reg-

ister is set, the corresponding input port (GPn) data bit

polarity will be inverted.

• IPOL0 (controls the polarity of GP0)

• IPOL1 (controls the polarity of GP1)

REGISTER 1-5:

R/W-0

IPOL0 - INPUT POLARITY PORT REGISTER 0

R/W-0

IGP0.0

bit 0

IGP0.7

bit 7

IGP0.6

IGP0.5

IGP0.4

IGP0.3

IGP0.2

IGP0.1

bit 7-0

IGP0.0:IGP0.7: Controls the polarity inversion for the input pins

1= Corresponding GP0 bit is inverted

0= Corresponding GP0 bit is not inverted

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

REGISTER 1-6:

R/W-0

IPOL1 - INPUT POLARITY PORT REGISTER 1

R/W-0

IGP1.0

bit 0

IGP1.7

bit 7

IGP1.6

IGP1.4

IGP1.3

IGP1.2

IGP1.1

bit 7-0

IGP1.0:IGP1.7: Controls the polarity inversion for the input pins

1= Corresponding GP1 bit is inverted

0= Corresponding GP1 bit is not inverted

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

DS20090C-page 8

MCP23016

1.7.4

I/O DIRECTION REGISTERS

Two registers control the direction of data I/O:

• IODIR0 (controls GP0)

• IODIR1 (controls GP1)

When a bit in these registers is set, the corresponding

pin becomes an input. Otherwise, it becomes an

output. At Power-on Reset, the device ports are

configured as inputs.

REGISTER 1-7:

R/W-1

IODIR0 - I/O DIRECTION REGISTER 0

R/W-1

IOD0.1

R/W-1

IOD0.0

bit 0

IOD0.7

bit 7

IOD0.6

IOD0.5

IOD0.4

IOD0.3

IOD0.2

bit 7-0

IOD0.0:IO0.7: Controls the direction of data I/O

1= Input

0= Output

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

REGISTER 1-8:

R/W-1

IODIR1 - I/O DIRECTION REGISTER 1

R/W-1

IOD1.0

bit 0

IOD1.7

bit 7

IOD1.6

IOD1.5

IOD1.4

IOD1.3

IOD1.2

IOD1.1

bit 7-0

IOD1.0:IO1.7: Controls the direction of data I/O

1= Input

0= Output

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

DS20090C-page 9

MCP23016

1.7.5

INTERRUPT CAPTURE REGISTERS

Two registers contain the value of the port that

generated the interrupt:

• INTCAP0 contains the value of GP0 at time of

GP0 change interrupt

• INTCAP1 contains the value of GP1 at time of

GP1 change interrupt

These registers are ‘read-only’ registers (A write to

these registers is ignored).

REGISTER 1-9:

R-x

INTCAP0 - INTERRUPT CAPTURED VALUE FOR PORT REGISTER 0

R-x

ICP0.0

bit 0

ICP0.7

bit 7

ICP0.6

ICP0.5

ICP0.4

ICP0.3

ICP0.2

ICP0.1

bit 7-0

ICP0.0:ICP0.7: Reflects the logic level on the GP0 pins at the time of interrupt due to pin

change

1= Logic ‘1’

0= Logic ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

REGISTER 1-10: INTCAP1 - INTERRUPT CAPTURED VALUE FOR PORT REGISTER 1

R-x

ICP1.7

bit 7

R-x

ICP1.0

bit 0

ICP1.6

ICP1.5

ICP1.4

ICP1.3

ICP1.2

ICP1.1

bit 7-0

ICP1.0:ICP1.7: Reflects the logic level on the GP1 pins at the time of interrupt due to pin

change

1= Logic ‘1’

0= Logic ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

DS20090C-page 10

MCP23016

1.7.6

I/O EXPANDER CONTROL

REGISTER

• IOCON0 controls the functionality of the

MCP23016.

The IARES (Interrupt Activity Resolution) bit controls

the sampling frequency of the GP port pins. The higher

the sampling frequency, the higher the device current

requirements. If this bit is ‘0’ (default), the maximum

time to detect the activity on the port is 32 ms (max.),

which results in lower standby current. If this bit is ‘1’,

the maximum time to detect activity on the port is

200 µsec. (max.) and results in higher standby current.

REGISTER 1-11: IOCON0 - I/0 EXPANDER CONTROL REGISTER

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

R/W-0

IARES

bit 0

—

bit 7

bit 1-7

bit 0

Unimplemented bit: Read as ‘0’

IARES: Interrupt Activity Resolution

1 = Fast sample rate

0 = Normal sample rate

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

- n = Value at POR

‘1’ = Bit is set

IOCON1 is a shadow register for IOCON0. Access to IOCON1 results in access to IOCON0.

DS20090C-page 11

MCP23016

1.9.1

INTERRUPT EVENT DETECTION

1.8

Serializer/Deserializer

The IARES bit controls the resolution for detecting an

interrupt-on-change event. If this bit is ‘0’ (default), the

maximum time for detecting a change of event is high,

which results in lower standby current. If this bit is ‘1’, it

takes less time for scanning the activity on the port and

results in higher standby current.

The Serializer/Deserializer block converts and

transfers data between the I²C bus and GPIO.

1.9

Interrupt Logic

The MCP23016 asserts the open-drain interrupt output

(INT) low when one of the port pins changes state. Only

those pins that are configured as an input can cause an

interrupt. Pins defined as an output have no effect on

INT. The interrupt will remain active until a read from

either the port (GPn) on which the interrupt occurred or

the INTCAPn register is performed. If the input returns

to its previous state before a read operation, it will reset

the interrupt and the INT pin output will tri-state. Each

8-bit port is read separately, so reading GP0 or

INTCAP0 will not clear the interrupt generated by GP1

or INTCAP1, and vice versa.

FIGURE 1-2:

READING PORTX AFTER

INTERRUPT EVENT

PORT X

GPx

INT

Input change activity on each port will generate an

interrupt and the value of the particular port will be

captured and copied into INTCAP0/INTCAP1. The

INTCAPn registers are only updated when an interrupt

occurs on INT. These values will stay unchanged until

the user clears the interrupt by reading the port or the

INTCAPn register.

Port value

is captured

and written to

INTCAPn

Port value

is captured

and written to

INTCAPn

Read GPx

or INTCAPn

If the input port value changes back to normal before a

user-read, the INT output will be reset. However, the

INTCAP0/INTCAP1 will still contain the value of the

port at the interrupt change. If the port value changes

again, it will re-activate the interrupt and the new value

will be captured.

The first interrupt on change event following an

interrupt RESET will result in a capture event. Any fur-

ther change event that occurs before the interrupt is

reset will not result in a capture event.

DS20090C-page 12

MCP23016

1.9.2

WRITING THE REGISTERS

FIGURE 1-3:

WRITE TO CONFIGURATION

REGISTERS (CASE 1)

To write to a MCP23016 register, the Master I²C device

needs to follow the requirements, as illustrated in

Figure 1-3. First, the device is selected by sending the

slave address and setting the R/W bit to logic ‘0’. The

command byte is sent after the address and

determines which register will be written. Table 1-3

shows the relationship of the command byte and

register.

The MCP23016 has twelve 8-bit registers. They are

configured to operate as six 16-bit register pairs,

supporting the device’s 16-bit port. These pairs are

formed based on their functions (e.g., GP0 and GP1

are grouped together). The I²C commands apply to one

register pair to provide faster access. The first data byte

following a command byte is written into the register

pointed to by the command byte, while the second data

is written into another register in the same pair. For

example, if the first byte is sent to OLAT1 (command

byte 03h), the next data byte will be written into the sec-

ond register of that pair, OLAT0. If the first byte is writ-

ten to OLAT0 (command byte 02h), the second byte

will be written to OLAT1.

There is no limitation on the number of data bytes in

one write transmission. Figure 1-4 shows the case of

multiple byte writes in one write operation. In this case,

the multiple writes are made to the same data pair.

Note:

The bus must remain free until after the

ninth clock pulse for a minimum of 12 µs

(see Table 2-5 and Figure 2-4).

DS20090C-page 13

MCP23016

FIGURE 1-4:

WRITE TO CONFIGURATION

REGISTERS (CASE 2)

FIGURE 1-5:

WRITE TO OUTPUT PORTS

DS20090C-page 14

MCP23016

1.9.3

READING THE REGISTERS

FIGURE 1-6:

READ FROM

CONFIGURATION

REGISTER

To read a MCP23016 register, the Master needs to

follow the requirements shown in Figure 1-6. First, the

device is selected by sending the slave address and

setting the R/W bit to logic ‘0’. The command byte is

sent after the address and determines which register

will be read. A restart condition is generated and the

device address is sent again with the R/W bit set to

logic ‘1’. The data register defined by the command

byte will be sent first, followed by the other register in

the register pair. The logic for register selection is the

same as explained in Write mode (Section 1.9.2,

“Writing the Registers”).

The falling edge of the ninth clock initiates the register

read action. The SCL clock will be held low while the

data is read from the register and is transferred to the

I²C bus control block by the Serializer/Deserializer

block.

The MCP23016 holds the clock low after the falling

edge of the ninth clock pulse. The configuration

registers (or port control registers) are read and the

value is stored. Finally, the clock is released to enable

the next transmission.

There is no limitation on the number of data bytes in

one read transmission. Figure 1-8 shows the case of

multiple byte read in one read operation. In this case,

the multiple writes are made to the same data pair.

Note:

The bus must remain free until after the

ninth clock pulse for a minimum of 12 µs

(see Table 2-5 and Figure 2-4).

DS20090C-page 15

MCP23016

FIGURE 1-7:

READ FROM INPUT PORTS (CASE 1)

DS20090C-page 16

MCP23016

FIGURE 1-8:

READ FROM INPUT PORTS

(CASE 2)

DS20090C-page 17

MCP23016

NOTES:

DS20090C-page 18

MCP23016

2.0

ELECTRICAL CHARACTERISTICS

Absolute Maximum Ratings †

Ambient temperature under bias................................................................................................................ -55 to +125°C

Storage temperature .............................................................................................................................. -65°C to +150°C

Voltage on any pin with respect to VSS ......................................................................................... -0.3V to (VDD + 0.3V)

Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +6.5V

Total power dissipation (Note 1) ............................................................................................................................ 1.0 W

Maximum current out of VSS pin .......................................................................................................................... 300 mA

Maximum current into VDD pin ............................................................................................................................. 250 mA

Input clamp current, IIK (VI < 0, or VI > VDD)....................................................................................................... ± ±20 mA

Output clamp current, IOK (VO < 0, or VO > VDD) ................................................................................................ ± ±20 mA

Maximum output current sunk by any I/O pin......................................................................................................... 25 mA

Maximum output current sourced by any I/O pin ................................................................................................... 25 mA

Maximum current sunk by±combined PORTS...................................................................................................... 200 mA

Maximum current sourced by combined PORTS ................................................................................................ 200 mA

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at those or any other conditions above those

indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for

extended periods may affect device reliability.

DS20090C-page 19

MCP23016

2.1

TABLE 2-1:

DC CHARACTERISTICS

DC Characteristics

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Operating temperature: -40°C ≤ TA ≤ +85°C for industrial

Param

No.

Characteristic

Sym

Min

Typ†

Max

Units

Conditions

D001 Supply Voltage

D002 Standby Current

D003 Standby Current

Input Low Voltage

I/O ports

VDD

IDD

IPD

2.0

—

0.4

25

5.5

V

mA IARES = 1

µA IARES = 0

—

VIL

D004

D004A

D005

TTL buffer

Vss

—

0.15 VDD

0.8V

V

For entire VDD range

4.5V ≤ VDD ≤±5.5V

Schmitt Trigger buffer

Input High Voltage

I/O ports

0.2 VDD

VIH

—

D006

TTL buffer

2.0

VDD

V

4.5V ≤ VDD ≤±5.5V

D006A

0.25 VDD

+ 0.8V

For entire VDD range

D007

Schmitt Trigger buffer

0.8 VDD

—

VDD

V

For entire VDD range

Input Leakage Current

D008 I/O ports

IIL

—

± 1.0

± 5.0

µA Vss ≤±VPIN ≤±VDD,

Pin at hi-impedance

D009 CLK

µA Vss ≤±VPIN ≤±VDD

Output Low Voltage

D010 I/O Ports

Output High Voltage

VOL

—

0.6

V

IOL = 8.5 mA, VDD = 4.5V

IOH = 3.0 mA, VDD = 4.5V

D010 I/O Ports

VOH

VDD-0.7

—

V

D011 VDD start voltage to ensure

internal POR signal

VPOR

Vss

D012 VDD rise rate to ensure

internal POR signal

SVDD

0.05

-

—

V/ms Note 1

DC Trip Point

VTPOR

SVDD

1.5

1.7

—

1.9

—

V

DC Slow Ramp

D012 VDD rise rate to ensure

internal POR signal with

PWRT enabled

0.05

V/ms Note 1

DC Current Draw

IPOR

—

5.0

—

µA At 5.0V (1 µ/Volt typical)

Note 1: These parameters are characterized but not tested.

2: Data in "Typ" column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

3: Standby current is measured with all I/O in hi-impedance state and tied to VDD and VSS.

4: For RC CLK, current through REXT is not included. The current through the resistor can be estimated by

the formula

Ir = VDD/2 REXT (mA) with REXT in kohm.

5: Negative current is defined as coming out of the pin.

DS20090C-page 20

MCP23016

FIGURE 2-1:

RESPONSE TIME

VDD

1

TABLE 2-2:

RESPONSE TIME

Symbol Characteristic

Response Time

Parameter

No.

Min

Typ† Max Units

ns

Conditions

1

100

—

Minimum time where a VDD

transition from 5.0V to 0.0V to

5.0V will cause a RESET. All

times less than 100 ns will be

filtered.

FIGURE 2-2:

TEST POINT CLOCK TIMING

2

TTP

TABLE 2-3:

TEST POINT CLOCK TIMING

Parameter

No.

Symbol

Characteristic

Min

Typ^†Max Units

Conditions

FTP

TTP

TP pin Frequency

—

1.0

—

MHz Measured at TP pin,

IARES = ‘1’.

2

TP pin CLK Period

µs

Measured at TP pin,

IARES = ‘1’.

†

Data in "Typ" column is at 5V, +25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

TABLE 2-4:

POWER-UP TIMER REQUIREMENTS

Parameter

No.

Symbol

Characteristic

Min

Typ^†Max Units

72 ms

Conditions

3

TPWRT Power-up Timer Period

—

†

Data in "Typ" column is at 5V, +25°C unless otherwise stated. These parameters are for design guidance

only and are not tested.

DS20090C-page 21

MCP23016

FIGURE 2-3:

I²C BUS START/STOP BITS TIMING

SCL

SDA

91

93

90

92

STOP

Condition

START

Condition

TABLE 2-5:

I²C BUS START/STOP BITS REQUIREMENTS

Param

No.

Ty

p

Symbol

Characteristic

Min

Max Units

Conditions

90

TSU:STA

START condition 100 kHz mode 4700

Setup time 400 kHz mode 600

THD:STA START condition 100 kHz mode 4000

—

ns Only relevant for Repeated

START condition (Note 1)

91

ns After this period, the first

clock pulse is generated

(Note 1)

Hold time

400 kHz mode 600

92

93

TSU:STO

THD:STO

STOP condition

Setup time

100 kHz mode 4700

400 kHz mode 600

100 kHz mode 4000

400 kHz mode 600

—

ns

STOP condition

Hold time

ns

Note 1: These parameters are characterized but not tested.

DS20090C-page 22

MCP23016

FIGURE 2-4:

I²C BUS DATA TIMING

103

102

100

101

SCL

90

106

111

107

91

92

SDA

In

110

109

SDA

Out

DS20090C-page 23

MCP23016

TABLE 2-5:

I²C BUS DATA REQUIREMENTS

Param

No.

Symbol Characteristic

Min

Max Units

Conditions

(Note 1)

100

THIGH

TLOW

TR

Clock High Time

Clock Low Time

100 kHz mode

4.0

0.6

4.7

1.3

—

µs

ns

400 kHz mode

100 kHz mode

400 kHz mode

101

102

—

(Note 1)

—

SDA and SCL Rise 100 kHz mode

Time

1000

(Note 1)

400 kHz mode 20 + 0.1 CB 300

CB is specified to be from

10 - 400 pF

103

TF

SDA and SCL Fall 100 kHz mode

Time

—

300

ns

(Note 1)

400 kHz mode 20 + 0.1 CB 300

CB is specified to be from

10 - 400 pF

90

91

TSU:STA START Condition

Setup Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

4.7

0.6

4.0

0.6

—

µs

Only relevant for repeated

START condition (Note 1)

THD:STA START Condition

Hold Time

After this period, the first

clock pulse is generated

(Note 1)

106

107

92

THD:DAT Data Input Hold

Time

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

100 kHz mode

400 kHz mode

0

—

0.9

—

ns

µs

ns

µs

ns

µs

(Note 1)

0

TSU:DAT Data Input Setup

Time

250

100

4.7

0.6

—

(Note 1) (Note 3)

(Note 1)

—

TSU:STO STOP Condition

Setup Time

—

109

110

TAA

Output Valid from

Clock

3500

—

(Note 1) (Note 2)

—

TBUF

Bus Free Time

4.7

1.3

—

Time the bus must be free

before a new transmis-

sion can start (Note 1)

—

CB

Bus Capacitive Loading

—

400

—

pF

µs

111

TWAIT

Clock wait time

after ninth pulse

100 kHz mode

400 kHz mode

12 µs

Time the bus must remain

free after the ninth clock

pulse before a new

—

transmission can start.

Note 1: These parameters are characterized but not tested.

2: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement TSU:DAT ≥±250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line TR max.+TSU:DAT = 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification), before the SCL line is released.

DS20090C-page 24

MCP23016

TABLE 2-7:

Param

GP0 AND GP1 TIMING REQUIREMENTS

Symbol

Characteristic

Min

Typ.

Max

Units

Conditions

No.

t_GPV0

t_GPV1

t_RDd0

t_RDd1

t_ISD0

GP0 output data

valid time

—

40

—

µs

TP = 1 MHz

GP1 output data

valid time

—

50

40

50

—

µs

GP0 data read

delay time

GP1 data read

delay time

GP0 Interrupt set

delay time

—

200

32

µs

ms

µs

IARES = 1, TP = 1 MHz

IARES = 0, TP = 1 MHz

IARES = 1, TP = 1 MHz

IARES = 0, TP = 1 MHz

TP = 1 MHz

t_ISD1

GP1 Interrupt set

delay time

—

200

32

—

ms

µs

t_LCD0

GP0 Interrupt clear

delay time (for

read)

100

—

t_LCD1

GP1 Interrupt clear

delay time (for

read)

—

100

—

µs

Note 1: These parameters are characterized but not tested.

DS20090C-page 25

MCP23016

FIGURE 2-5:

GP0 AND GP1 PORT TIMINGS

DS20090C-page 26

MCP23016

3.0

3.1

PACKAGE INFORMATION

Package Marking Information

28-Lead PDIP (Skinny DIP)

Example:

XXXXXXXXXXXXXXXXX

YYWWNNN

MCP23016-I/SP

0717017

e

3

28-Lead SOIC

XXXXXXXXXXXXXXXXX

MCP23016-I/SO

e

3

YYWWNNN

0710017

28-Lead SSOP

Example:

XXXXXXXXXXXX

MCP23016

-I/SS

e

3

YYWWNNN

0720017

28-Lead QFN

Example:

XXXXXXXX

YYWWNNN

MCP23016

-I/ML

0710017

e

3

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS20090C-page 27

MCP23016

28-Lead Skinny Plastic Dual In-Line (SP) – 300 mil Body [SPDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1

2 3

D

E

A2

A

L

c

b1

A1

b

e

eB

Units

INCHES

NOM

28

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.200

.150

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.120

.015

.290

.240

1.345

.110

.008

.040

.014

–

.135

–

.310

.285

1.365

.130

.010

.050

.018

–

.335

.295

1.400

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

DS20090C-page 28

MCP23016

28-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

h

α

h

c

φ

A2

A

L

A1

L1

β

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

1.27 BSC

Overall Height

A

–

2.65

–

Molded Package Thickness

Standoff §

A2

A1

E

2.05

0.10

–

0.30

Overall Width

10.30 BSC

Molded Package Width

Overall Length

Chamfer (optional)

Foot Length

E1

D

h

7.50 BSC

17.90 BSC

0.25

0.40

–

0.75

1.27

L

–

Footprint

L1

φ

1.40 REF

Foot Angle Top

Lead Thickness

Lead Width

0°

0.18

0.31

5°

–

8°

c

0.33

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-052B

DS20090C-page 29

MCP23016

28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm Body [SSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

1

2

b

NOTE 1

e

c

A2

A

φ

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

28

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.75

–

2.00

1.85

–

A2

A1

E

1.65

0.05

7.40

5.00

9.90

0.55

Overall Width

Molded Package Width

Overall Length

Foot Length

7.80

5.30

10.20

0.75

1.25 REF

–

8.20

5.60

10.50

0.95

E1

D

L

Footprint

L1

c

Lead Thickness

Foot Angle

0.09

0°

0.25

8°

φ

4°

Lead Width

b

0.22

–

0.38

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.20 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-073B

DS20090C-page 30

MCP23016

28-Lead Plastic Quad Flat, No Lead Package (ML) – 6x6 mm Body [QFN]

with 0.55 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

D2

EXPOSED

PAD

e

E

b

E2

2

1

2

1

K

N

NOTE 1

L

BOTTOM VIEW

TOP VIEW

A

A3

A1

Units

MILLIMETERS

NOM

Dimension Limits

MIN

MAX

Number of Pins

N

e

28

Pitch

0.65 BSC

0.90

Overall Height

Standoff

A

0.80

0.00

1.00

0.05

A1

A3

E

0.02

Contact Thickness

Overall Width

0.20 REF

6.00 BSC

3.70

Exposed Pad Width

Overall Length

Exposed Pad Length

Contact Width

Contact Length

Contact-to-Exposed Pad

E2

D

3.65

4.20

6.00 BSC

3.70

D2

b

3.65

0.23

0.50

0.20

4.20

0.35

0.70

–

0.30

L

0.55

K

–

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-105B

DS20090C-page 31

MCP23016

NOTES:

DS20090C-page 32

MCP23016

APPENDIX A: REVISION HISTORY

Revision A (December 2002)

Original data sheet for MCP23016 device.

Revision B (September 2003)

1. Addition of Output Low Voltage section to

Table 2-1 in Electrical Characteristics.

2. Addition of Output High Voltage section to

Table 2-1 in Electrical Characteristics.

Revision C (January 2007)

This revision includes updates to the packaging

diagrams.

DS20090C-page 33

MCP23016

NOTES:

DS20090C-page 34

MCP23016

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information (e.g., on pricing or delivery) refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a) DSTEMP-I/P:

Industrial Temperature,

PDIP package.

Temperature

Range

Package

a) DSTEMP-I/SO: IndustrialTemperature,

SOIC package.

2

a) DSTEMP-I/SS: Industrial Temperature,

SOIC package.

Device:

DSTEMP: 16-Bit I C I/O Expander

a) DSTEMP-I/ML: Industrial Temperature,

QFN package.

Temperature

Range:

I = -40°C to +85°C

Package:

SP = Plastic DIP (300 mil Body), 28-lead

SO = Plastic SOIC, Wide (300 mil Body), 28-lead

SS = Plastic SOIC, (209 mil, 5.30mm), 28-lead

ML = Plastic Quad, Flat No Leads (QFN), 28-lead

DS20090C-page 35

MCP23016

NOTES:

DS20090C-page 36

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS20090C-page 37

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS20090C-page 38


型号：	MCP23016T-I/ML
厂家：	MICROCHIP
描述：	16 BIT I/O EXPANDER, -40C to +85C, 28-QFN, T/R 外围集成电路
文件：	总38页 (文件大小：543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP23016T-I/ML [MICROCHIP]

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MCP23016T-I/SS

MCP23017

MCP23017-E/ML

MCP23017-E/MLT

MCP23017-E/SO

MCP23017-E/SP

MCP23017-E/SS

MCP23017-E/SST

MCP23017-E/SSVAO

MCP23017-I/ML

MCP23017-I/SP

MCP23017-I/SS