MCP2510T-I/STVAO_技术文档

MCP2510

Stand-Alone CAN Controller with SPI^™Interface

Features

Description

• Implements Full CAN V2.0A and V2.0B at 1 Mb/s:

- 0 - 8 byte message length

The Microchip Technology Inc. MCP2510 is a Full Con-

troller Area Network (CAN) protocol controller imple-

menting CAN specification V2.0 A/B. It supports CAN

1.2, CAN 2.0A, CAN 2.0B Passive, and CAN 2.0B

Active versions of the protocol, and is capable of trans-

mitting and receiving standard and extended mes-

sages. It is also capable of both acceptance filtering

and message management. It includes three transmit

buffers and two receive buffers that reduce the amount

of microcontroller (MCU) management required. The

MCU communication is implemented via an industry

standard Serial Peripheral Interface (SPI) with data

rates up to 5 Mb/s.

- Standard and extended data frames

- Programmable bit rate up to 1 Mb/s

- Support for remote frames

- Two receive buffers with prioritized message

storage

- Six full acceptance filters

- Two full acceptance filter masks

- Three transmit buffers with prioritization and

abort features

- Loop-back mode for self test operation

• Hardware Features:

Package Types

- High Speed SPI Interface

(5 MHz at 4.5V I temp)

18 LEAD PDIP/SOIC

1

VDD

TXCAN

18

- Supports SPI modes 0,0 and 1,1

- Clock out pin with programmable prescaler

- Interrupt output pin with selectable enables

RXCAN

CLKOUT

TX0RTS

TX1RTS

2

3

17

16

RESET

CS

- ‘Buffer full’ output pins configureable as inter-

rupt pins for each receive buffer or as general

purpose digital outputs

4

5

SO

SI

15

14

13

12

11

10

SCK

TX2RTS

OSC2

OSC1

VSS

6

7

- ‘Request to Send’ input pins configureable as

control pins to request immediate message

transmission for each transmit buffer or as

general purpose digital inputs

INT

RX0BF

RX1BF

8

9

- Low Power Sleep mode

• Low power CMOS technology:

- Operates from 3.0V to 5.5V

20 LEAD TSSOP

- 5 mA active current typical

1

20

19

18

17

16

15

14

VDD

TXCAN

RXCAN

CLKOUT

TX0RTS

TX1RTS

NC

2

3

4

- 10 µA standby current typical at 5.5V

• 18-pin PDIP/SOIC and 20-pin TSSOP packages

• Temperature ranges supported:

RESET

CS

SO

SI

NC

SCK

5

- Industrial (I):

- Extended (E):

-40°C to +85°C

-40°C to +125°C

6

7

TX2RTS

8

9

10

13 INT

OSC2

OSC1

VSS

12

11

RX0BF

RX1BF

DS21291F-page 1

MCP2510

Table of Contents

1.0

Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.0

3.0

4.0

5.0

6.0

7.0

8.0

9.0

10.0

11.0

12.0

13.0

Can Message Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Message Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reader Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Product Identification System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Worldwide Sales and Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

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DS21291F-page 2

MCP2510

checked for errors and then matched against the user

defined filters to see if it should be moved into one of

the two receive buffers.

1.0

1.1

DEVICE FUNCTIONALITY

Overview

The MCU interfaces to the device via the SPI interface.

Writing to and reading from all registers is done using

standard SPI read and write commands.

The MCP2510 is a stand-alone CAN controller devel-

oped to simplify applications that require interfacing

with a CAN bus. A simple block diagram of the

MCP2510 is shown in Figure 1-1. The device consists

of three main blocks:

Interrupt pins are provided to allow greater system flex-

ibility. There is one multi-purpose interrupt pin as well

as specific interrupt pins for each of the receive regis-

ters that can be used to indicate when a valid message

has been received and loaded into one of the receive

buffers. Use of the specific interrupt pins is optional,

and the general purpose interrupt pin as well as status

registers (accessed via the SPI interface) can also be

used to determine when a valid message has been

received.

1. The CAN protocol engine.

2. The control logic and SRAM registers that are

used to configure the device and its operation.

3. The SPI protocol block.

A typical system implementation using the device is

shown in Figure 1-2.

The CAN protocol engine handles all functions for

receiving and transmitting messages on the bus. Mes-

sages are transmitted by first loading the appropriate

message buffer and control registers. Transmission is

initiated by using control register bits, via the SPI inter-

face, or by using the transmit enable pins. Status and

errors can be checked by reading the appropriate reg-

isters. Any message detected on the CAN bus is

There are also three pins available to initiate immediate

transmission of a message that has been loaded into

one of the three transmit registers. Use of these pins is

optional and initiating message transmission can also

be done by utilizing control registers accessed via the

SPI interface.

Table 1-1 gives a complete list of all of the pins on the

MCP2510.

FIGURE 1-1:

BLOCK DIAGRAM

RXCAN

2 RX Buffers

CAN

Protocol

Engine

CS

SCK

SI

SPI

Interface

Logic

3 TX

Buffers

6 Acceptance

Filters

SPI

Bus

Message Assembly

Buffer

TXCAN

SO

Control Logic

INT

RX0BF

RX1BF

TX0RTS

TX1RTS

TX2RTS

DS21291F-page 3

MCP2510

FIGURE 1-2:

TYPICAL SYSTEM IMPLEMENTATION

Main

System

Controller

MCP2510

CAN

Transceiver

CAN

BUS

CAN

Transceiver

MCP2510

SPI

INTERFACE

Node

Controller

TABLE 1-1:

PIN DESCRIPTIONS

DIP/

SOIC

Pin #

TSSOP

Pin #

I/O/P

Type

Name

Description

TXCAN

RXCAN

CLKOUT

TX0RTS

1

2

3

4

1

2

3

4

O

I

Transmit output pin to CAN bus

Receive input pin from CAN bus

O

I

Clock output pin with programmable prescaler

Transmit buffer TXB0 request to send or general purpose digital input. 100 kΩ

internal pullup to VDD

TX1RTS

TX2RTS

5

6

5

7

I

Transmit buffer TXB1 request to send or general purpose digital input. 100 kΩ

internal pullup to VDD

Transmit buffer TXB2 request to send or general purpose digital input. 100 kΩ

internal pullup to VDD

OSC2

OSC1

VSS

7

8

9

O

I

Oscillator output

8

Oscillator input

9

10

11

12

13

14

16

17

18

19

20

6,15

P

O

I

Ground reference for logic and I/O pins

Receive buffer RXB1 interrupt pin or general purpose digital output

Receive buffer RXB0 interrupt pin or general purpose digital output

Interrupt output pin

RX1BF

RX0BF

INT

10

11

12

13

14

15

16

17

18

—

SCK

SI

Clock input pin for SPI interface

Data input pin for SPI interface

I

SO

O

I

Data output pin for SPI interface

Chip select input pin for SPI interface

Active low device reset input

CS

RESET

VDD

I

P

—

Positive supply for logic and I/O pins

No internal connection

NC

Note:

Type Identification: I=Input; O=Output; P=Power

DS21291F-page 4

MCP2510

1.2

Transmit/Receive Buffers

The MCP2510 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a

total of six acceptance filters. Figure 1-3 is a block diagram of these buffers and their connection to the protocol engine.

FIGURE 1-3:

CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM

Acceptance Mask

RXM1

BUFFERS

Acceptance Filter

RXF2

A

c

e

p

t

Acceptance Mask

RXM0

Acceptance Filter

RXF3

A

c

e

p

t

TXB0

TXB1

TXB2

Acceptance Filter

RXF0

Acceptance Filter

RXF4

Acceptance Filter

RXF1

Acceptance Filter

RXF5

R

X

B

0

R

X

B

1

M

A

B

Identifier

Message

Queue

Control

Transmit Byte Sequencer

Data Field

Receive

Error

Counter

REC

TEC

PROTOCOL

ENGINE

Transmit

Error

Counter

ErrPas

BusOff

Transmit<7:0>

Shift<14:0>

Receive<7:0>

{Transmit<5:0>, Receive<8:0>}

Comparator

Protocol

Finite

State

Machine

CRC<14:0>

Bit

Timing

Logic

Transmit

Logic

Clock

Generator

TX

RX

Configuration

Registers

DS21291F-page 5

MCP2510

1.3

CAN Protocol Engine

1.6

Error Management Logic

The CAN protocol engine combines several functional

blocks, shown in Figure 1-4. These blocks and their

functions are described below.

The Error Management Logic is responsible for the

fault confinement of the CAN device. Its two counters,

the Receive Error Counter (REC) and the Transmit

Error Counter (TEC), are incremented and decre-

mented by commands from the Bit Stream Processor.

According to the values of the error counters, the CAN

controller is set into the states error-active, error-pas-

sive or bus-off.

1.4

Protocol Finite State Machine

The heart of the engine is the Finite State Machine

(FSM). This state machine sequences through mes-

sages on a bit by bit basis, changing states as the fields

of the various frame types are transmitted or received.

The FSM is a sequencer controlling the sequential data

stream between the TX/RX Shift Register, the CRC

Register, and the bus line. The FSM also controls the

Error Management Logic (EML) and the parallel data

stream between the TX/RX Shift Registers and the

buffers. The FSM insures that the processes of recep-

tion, arbitration, transmission, and error signaling are

performed according to the CAN protocol. The auto-

matic retransmission of messages on the bus line is

also handled by the FSM.

1.7

Bit Timing Logic

The Bit Timing Logic (BTL) monitors the bus line input

and handles the bus related bit timing according to the

CAN protocol. The BTL synchronizes on a recessive to

dominant bus transition at Start of Frame (hard syn-

chronization) and on any further recessive to dominant

bus line transition if the CAN controller itself does not

transmit a dominant bit (resynchronization). The BTL

also provides programmable time segments to com-

pensate for the propagation delay time, phase shifts,

and to define the position of the Sample Point within the

bit time. The programming of the BTL depends upon

the baud rate and external physical delay times.

1.5

Cyclic Redundancy Check

The Cyclic Redundancy Check Register generates the

Cyclic Redundancy Check (CRC) code which is trans-

mitted after either the Control Field (for messages with

0 data bytes) or the Data Field, and is used to check the

CRC field of incoming messages.

FIGURE 1-4:

CAN PROTOCOL ENGINE BLOCK DIAGRAM

TX

RX

Bit Timing Logic

SAM

Transmit Logic

REC

Receive

Sample<2:0>

Error Counter

TEC

StuffReg<5:0>

Comparator

Transmit

ErrPas

Majority

Decision

Error Counter

BusOff

BusMon

CRC<14:0>

Comparator

Protocol

FSM

Shift<14:0>

(Transmit<5:0>, Receive<7:0>)

Receive<7:0>

Transmit<7:0>

RecData<7:0>

TrmData<7:0>

Rec/Trm Addr.

Interface to Standard Buffer

DS21291F-page 6

MCP2510

dard CAN frame will win arbitration due to the assertion

of a dominant lDE bit. Also, the SRR bit in an extended

CAN frame must be recessive to allow the assertion of

a dominant RTR bit by a node that is sending a stan-

dard CAN remote frame.

2.0

CAN MESSAGE FRAMES

The MCP2510 supports Standard Data Frames,

Extended Data Frames, and Remote Frames (Stan-

dard and Extended) as defined in the CAN 2.0B speci-

fication.

The SRR and lDE bits are followed by the remaining 18

bits of the identifier (Extended lD) and the remote trans-

mission request bit.

2.1

Standard Data Frame

The CAN Standard Data Frame is shown in Figure 2-1.

In common with all other frames, the frame begins with

a Start Of Frame (SOF) bit, which is of the dominant

state, which allows hard synchronization of all nodes.

To enable standard and extended frames to be sent

across a shared network, it is necessary to split the 29-

bit extended message identifier into 11-bit (most signif-

icant) and 18-bit (least significant) sections. This split

ensures that the lDE bit can remain at the same bit

position in both standard and extended frames.

The SOF is followed by the arbitration field, consisting

of 12 bits; the 11-bit ldentifier and the Remote Trans-

mission Request (RTR) bit. The RTR bit is used to dis-

tinguish a data frame (RTR bit dominant) from a remote

frame (RTR bit recessive).

Following the arbitration field is the six-bit control field.

the first two bits of this field are reserved and must be

dominant. the remaining four bits of the control field are

the Data Length Code (DLC) which specifies the num-

ber of data bytes contained in the message.

Following the arbitration field is the control field, con-

sisting of six bits. The first bit of this field is the Identifier

Extension (IDE) bit which must be dominant to specify

a standard frame. The following bit, Reserved Bit Zero

(RB0), is reserved and is defined to be a dominant bit

by the can protocol. the remaining four bits of the con-

trol field are the Data Length Code (DLC) which speci-

fies the number of bytes of data contained in the

message.

The remaining portion of the frame (data field, CRC

field, acknowledge field, end of frame and lntermission)

is constructed in the same way as for a standard data

frame (see Section 2.1).

2.3

Remote Frame

Normally, data transmission is performed on an auton-

omous basis by the data source node (e.g. a sensor

sending out a data frame). It is possible, however, for a

destination node to request data from the source. To

accomplish this, the destination node sends a remote

frame with an identifier that matches the identifier of the

required data frame. The appropriate data source node

will then send a data frame in response to the remote

frame request.

After the control field is the data field, which contains

any data bytes that are being sent, and is of the length

defined by the DLC above (0-8 bytes).

The Cyclic Redundancy Check (CRC) Field follows the

data field and is used to detect transmission errors. The

CRC Field consists of a 15-bit CRC sequence, followed

by the recessive CRC Delimiter bit.

The final field is the two-bit acknowledge field. During

the ACK Slot bit, the transmitting node sends out a

recessive bit. Any node that has received an error free

frame acknowledges the correct reception of the frame

by sending back a dominant bit (regardless of whether

the node is configured to accept that specific message

or not). The recessive acknowledge delimiter com-

pletes the acknowledge field and may not be overwrit-

ten by a dominant bit.

There are two differences between a remote frame

(shown in Figure 2-3) and a data frame. First, the RTR

bit is at the recessive state, and second, there is no

data field. In the event of a data frame and a remote

frame with the same identifier being transmitted at the

same time, the data frame wins arbitration due to the

dominant RTR bit following the identifier. In this way,

the node that transmitted the remote frame receives

the desired data immediately.

2.2

Extended Data Frame

2.4

Error Frame

In the Extended CAN Data Frame, the SOF bit is fol-

lowed by the arbitration field which consists of 32 bits,

as shown in Figure 2-2. The first 11 bits are the most

significant bits (Base-lD) of the 29-bit identifier. These

11 bits are followed by the Substitute Remote Request

(SRR) bit which is defined to be recessive. The SRR bit

is followed by the lDE bit which is recessive to denote

an extended CAN frame.

An Error Frame is generated by any node that detects

a bus error. An error frame, shown in Figure 2-4, con-

sists of two fields, an error flag field followed by an error

delimiter field. There are two types of error flag fields.

Which type of error flag field is sent depends upon the

error status of the node that detects and generates the

error flag field.

It should be noted that if arbitration remains unresolved

after transmission of the first 11 bits of the identifier, and

one of the nodes involved in the arbitration is sending

a standard CAN frame (11-bit identifier), then the stan-

If an error-active node detects a bus error then the

node interrupts transmission of the current message by

generating an active error flag. The active error flag is

composed of six consecutive dominant bits. This bit

DS21291F-page 7

MCP2510

sequence actively violates the bit stuffing rule. All other

stations recognize the resulting bit stuffing error and in

turn generate error frames themselves, called error

echo flags. The error flag field, therefore, consists of

between six and twelve consecutive dominant bits

(generated by one or more nodes). The error delimiter

field completes the error frame. After completion of the

error frame, bus activity returns to normal and the inter-

rupted node attempts to resend the aborted message.

2.5

Overload Frame

An Overload Frame, shown in Figure 2-5, has the

same format as an active error frame. An overload

frame, however can only be generated during an lnter-

frame space. In this way an overload frame can be dif-

ferentiated from an error frame (an error frame is sent

during the transmission of a message). The overload

frame consists of two fields, an overload flag followed

by an overload delimiter. The overload flag consists of

six dominant bits followed by overload flags generated

by other nodes (and, as for an active error flag, giving

a maximum of twelve dominant bits). The overload

delimiter consists of eight recessive bits. An overload

frame can be generated by a node as a result of two

conditions. First, the node detects a dominant bit during

the interframe space which is an illegal condition. Sec-

ond, due to internal conditions the node is not yet able

to start reception of the next message. A node may

generate a maximum of two sequential overload

frames to delay the start of the next message.

If an error-passive node detects a bus error then the

node transmits an error-passive flag followed by the

error delimiter field. The error-passive flag consists of

six consecutive recessive bits, and the error frame for

an error-passive node consists of 14 recessive bits.

From this, it follows that unless the bus error is

detected by the node that is actually transmitting, the

transmission of an error frame by an error-passive

node will not affect any other node on the network. If

the transmitting node generates an error-passive flag

then this will cause other nodes to generate error

frames due to the resulting bit stuffing violation. After

transmission of an error frame, an error-passive node

must wait for six consecutive recessive bits on the bus

before attempting to rejoin bus communications.

2.6

Interframe Space

The lnterframe Space separates a preceeding frame

(of any type) from a subsequent data or remote frame.

The interframe space is composed of at least three

recessive bits called the Intermission. This is provided

to allow nodes time for internal processing before the

start of the next message frame. After the intermission,

the bus line remains in the recessive state (bus idle)

until the next transmission starts.

The error delimiter consists of eight recessive bits and

allows the bus nodes to restart bus communications

cleanly after an error has occurred.

DS21291F-page 8

MCP2510

NOTES:

DS21291F-page 14

MCP2510

ted. If transmission is initiated via the SPI interface, the

TXREQ bit can be set at the same time as the TXP pri-

ority bits.

3.0

3.1

MESSAGE TRANSMISSION

Transmit Buffers

When

TXBNCTRL.ABTF,

TXBNCTRL.TXERR bits will be cleared.

TXBNCTRL.TXREQ

is

set,

the

and

The MCP2510 implements three Transmit Buffers.

Each of these buffers occupies 14 bytes of SRAM and

are mapped into the device memory maps. The first

byte, TXBNCTRL, is a control register associated with

the message buffer. The information in this register

determines the conditions under which the message

will be transmitted and indicates the status of the mes-

sage transmission. (see Register 3-2). Five bytes are

used to hold the standard and extended identifiers and

other message arbitration information (see Register 3-

3 through Register 3-8). The last eight bytes are for the

eight possible data bytes of the message to be trans-

mitted (see Register 3-8).

TXBNCTRL.MLOA

Setting the TXBNCTRL.TXREQ bit does not initiate a

message transmission, it merely flags a message

buffer as ready for transmission. Transmission will start

when the device detects that the bus is available. The

device will then begin transmission of the highest prior-

ity message that is ready.

When the transmission has completed successfully the

TXBNCTRL.TXREQ bit will be cleared, the CAN-

INTF.TXNIF bit will be set, and an interrupt will be gen-

erated if the CANINTE.TXNIE bit is set.

For the MCU to have write access to the message

buffer, the TXBNCTRL.TXREQ bit must be clear, indi-

cating that the message buffer is clear of any pending

message to be transmitted. At a minimum, the TXBN-

SIDH, TXBNSIDL, and TXBNDLC registers must be

loaded. If data bytes are present in the message, the

TXBNDm registers must also be loaded. If the message

is to use extended identifiers, the TXBNEIDm registers

must also be loaded and the TXBNSIDL.EXIDE bit set.

If the message transmission fails, the TXBNC-

TRL.TXREQ will remain set indicating that the mes-

sage is still pending for transmission and one of the

following condition flags will be set. If the message

started to transmit but encountered an error condition,

the TXBNCTRL. TXERR and the CANINTF.MERRF

bits will be set and an interrupt will be generated on the

INT pin if the CANINTE.MERRE bit is set. If the mes-

sage lost arbitration the TXBNCTRL.MLOA bit will be

set.

Prior to sending the message, the MCU must initialize

the CANINTE.TXINE bit to enable or disable the gener-

ation of an interrupt when the message is sent. The

MCU must also initialize the TXBNCTRL.TXP priority

bits (see Section 3.2).

3.4

TXnRTS Pins

The TXNRTS Pins are input pins that can be configured

as request-to-send inputs, which provides a secondary

means of initiating the transmission of a message from

any of the transmit buffers, or as standard digital inputs.

Configuration and control of these pins is accomplished

using the TXRTSCTRL register (see Register 3-2). The

TXRTSCTRL register can only be modified when the

MCP2510 is in configuration mode (see Section 9.0). If

configured to operate as a request to send pin, the pin

is mapped into the respective TXBNCTRL.TXREQ bit

for the transmit buffer. The TXREQ bit is latched by the

falling edge of the TXNRTS pin. The TXNRTS pins are

designed to allow them to be tied directly to the RXNBF

pins to automatically initiate a message transmission

when the RXNBF pin goes low. The TXNRTS pins have

internal pullup resistors of 100 kΩ (nominal).

3.2

Transmit Priority

Transmit priority is a prioritization, within the MCP2510,

of the pending transmittable messages. This is inde-

pendent from, and not necessarily related to, any prior-

itization implicit in the message arbitration scheme built

into the CAN protocol. Prior to sending the SOF, the pri-

ority of all buffers that are queued for transmission is

compared. The transmit buffer with the highest priority

will be sent first. For example, if transmit buffer 0 has a

higher priority setting than transmit buffer 1, buffer 0 will

be sent first. If two buffers have the same priority set-

ting, the buffer with the highest buffer number will be

sent first. For example, if transmit buffer 1 has the same

priority setting as transmit buffer 0, buffer 1 will be sent

first. There are four levels of transmit priority. If TXBNC-

TRL.TXP<1:0> for a particular message buffer is set to

11, that buffer has the highest possible priority. If

TXBNCTRL.TXP<1:0> for a particular message buffer

is 00, that buffer has the lowest possible priority.

3.5

Aborting Transmission

The MCU can request to abort a message in a specific

message buffer by clearing the associated TXBnC-

TRL.TXREQ bit. Also, all pending messages can be

requested to be aborted by setting the CAN-

CTRL.ABAT bit. If the CANCTRL.ABAT bit is set to

abort all pending messages, the user MUST reset this

bit (typically after the user verifies that all TXREQ bits

have been cleared) to continue trasmit messages. The

CANCTRL.ABTF flag will only be set if the abort was

requested via the CANCTRL.ABAT bit. Aborting a mes-

sage by resetting the TXREQ bit does cause the ATBF

bit to be set.

3.3

Initiating Transmission

To initiate message transmission the TXBNC-

TRL.TXREQ bit must be set for each buffer to be trans-

mitted. This can be done by writing to the register via

the SPI interface or by setting the TXNRTS pin low for

the particular transmit buffer(s) that are to be transmit-

DS21291F-page 15

MCP2510

Only messages that have not already begun to be

transmitted can be aborted. Once a message has

begun transmission, it will not be possible for the user

to reset the TXBnCTRL.TXREQ bit. After transmission

of a message has begun, if an error occurs on the bus

or if the message loses arbitration, the message will be

retransmitted regardless of a request to abort.

FIGURE 3-1:

TRANSMIT MESSAGE FLOWCHART

Start

The message transmission

sequence begins when the

device determines that the

TXBnCTRL.TXREQ for any of

the transmit registers has been

set.

Are any

TXBnCTRL.TXREQ

No

bits = 1

?

Yes

Clearing the TxBnCTRL.TXREQ

Clear:

bit while it is set, or setting the

CANCTRL.ABAT bit before the

message has started transmission

will abort the message.

TXBnCTRL.ABTF

TXBnCTRL.MLOA

TXBnCTRL.TXERR

Is

is

No

CAN Bus available

to start transmission

?

TXBnCTRL.TXREQ=0

CANCTRL.ABAT=1

?

Yes

Examine TXBnCTRL.TXP <1:0> to

Determine Highest Priority Message

Transmit Message

Did

Yes

Was

No

Set

a message error

occur?

Message Transmitted

Successfully?

TxBnCTRL.TXERR=1

No

Yes

Set TxBnCTRL.TXREQ=0

Yes

Was

Arbitration lost during

transmission?

TxBnCTRL.MLOA=1

Yes

Generate

Interrupt

CANINTE.TXnIE=1?

No

Set

CANTINF.TXnIF=1

The CANINTE.TXnIE bit

determines if an interrupt

should be generated when

a message is successfully

transmitted.

GOTO START

DS21291F-page 16

MCP2510

REGISTER 3-1:

TXBNCTRL Transmit Buffer N Control Register

(ADDRESS: 30h, 40h, 50h)

U-0

—

R-0

R/W-0

U-0

—

R/W-0

TXP1

R/W-0

TXP0

ABTF

MLOA

TXERR

TXREQ

bit 7

bit 0

bit 7

bit 6

Unimplemented: Read as '0'

ABTF: Message Aborted Flag

1= Message was aborted

0= Message completed transmission successfully

bit 5

bit 4

bit 3

MLOA: Message Lost Arbitration

1= Message lost arbitration while being sent

0= Message did not lose arbitration while being sent

TXERR: Transmission Error Detected

1= A bus error occurred while the message was being transmitted

0= No bus error occurred while the message was being transmitted

TXREQ: Message Transmit Request

1= Buffer is currently pending transmission

(MCU sets this bit to request message be transmitted - bit is automatically cleared when

the message is sent)

0= Buffer is not currently pending transmission

(MCU can clear this bit to request a message abort)

bit 2

Unimplemented: Read as '0'

bit 1-0

TXP<1:0>: Transmit Buffer Priority

11= Highest Message Priority

10= High Intermediate Message Priority

11= Low Intermediate Message Priority

00= Lowest Message Priority

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 17

MCP2510

REGISTER 3-2:

TXRTSCTRL - TXNRTS PIN CONTROL AND STATUS REGISTER

(ADDRESS: 0Dh)

U-0

—

U-0

—

R-x

R/W-0

B2RTS

B1RTS

B0RTS

B2RTSM

B1RTSM B0RTSM

bit 0

bit 7

bit 6

bit 5

Unimplemented: Read as '0'

B2RTS: TX2RTS Pin State

- Reads state of TX2RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

bit 4

bit 3

bit 2

bit 1

bit 0

B1RTS: TX1RTX Pin State

- Reads state of TX1RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

B0RTS: TX0RTS Pin State

- Reads state of TX0RTS pin when in digital input mode

- Reads as ‘0’ when pin is in ‘request to send’ mode

B2RTSM: TX2RTS Pin Mode

1= Pin is used to request message transmission of TXB2 buffer (on falling edge)

0= Digital input

B1RTSM: TX1RTS Pin Mode

1= Pin is used to request message transmission of TXB1 buffer (on falling edge)

0= Digital input

B0RTSM: TX0RTS Pin Mode

1= Pin is used to request message transmission of TXB0 buffer (on falling edge)

0= Digital input

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 3-3:

TXBNSIDH - TRANSMIT BUFFER N STANDARD IDENTIFIER HIGH

(ADDRESS: 31h, 41h, 51h)

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID<10:3>: Standard Identifier Bits <10:3>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 18

MCP2510

REGISTER 3-4:

TXBNSIDL - Transmit Buffer N Standard Identifier Low

(ADDRESS: 32h, 42h, 52h)

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

R/W-x

—

R/W-x

EXIDE

R/W-x

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

bit 4

SID<2:0>: Standard Identifier Bits <2:0>

Unimplemented: Reads as '0’

bit 3

EXIDE: Extended Identifier Enable

1 = Message will transmit extended identifier

0= Message will transmit standard identifier

bit 2

Unimplemented: Reads as '0’

bit 1-0

EID<17:16>: Extended Identifier Bits <17:16>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 3-5:

TXBNEID8 - TRANSMIT BUFFER N EXTENDED IDENTIFIER HIGH

(ADDRESS: 33h, 43h, 53h)

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID<15:8>: Extended Identifier Bits <15:8>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 3-6:

TXBNEID0 - TRANSMIT BUFFER N EXTENDED IDENTIFIER LOW

(ADDRESS: 34h, 44h, 54h)

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID<7:0>: Extended Identifier Bits <7:0>

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 19

MCP2510

REGISTER 3-7:

TXBNDLC - Transmit Buffer N Data Length Code

(ADDRESS: 35h, 45h, 55h)

R/W-x

—

R/W-x

RTR

R/W-x

—

R/W-x

—

R/W-x

DLC3

R/W-x

DLC2

R/W-x

DLC1

R/W-x

DLC0

bit 7

bit 0

bit 7

bit 6

Unimplemented: Reads as '0’

RTR: Remote Transmission Request Bit

1= Transmitted Message will be a Remote Transmit Request

0= Transmitted Message will be a Data Frame

bit 5-4

bit 3-0

Unimplemented: Reads as '0’

DLC<3:0>: Data Length Code

Sets the number of data bytes to be transmitted (0 to 8 bytes)

Note: It is possible to set the DLC to a value greater than 8, however only 8 bytes are trans-

mitted

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 3-8:

TXBNDM - Transmit Buffer N Data Field Byte m

(ADDRESS: 36h-3Dh, 46h-4Dh, 56h-5Dh)

R/W-x

TXBNDm TXBNDm TXBNDm TXBNDm TXBNDm TXBNDm TXBNDm TXBNDm

7

6

5

4

3

2

1

0

bit 7

bit 0

bit 7-0

TXBNDM7:TXBNDM0: Transmit Buffer N Data Field Byte m

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 20

MCP2510

When a message is received, bits <3:0> of the RXBNC-

TRL Register will indicate the acceptance filter number

that enabled reception, and whether the received mes-

sage is a remote transfer request.

4.0

4.1

MESSAGE RECEPTION

Receive Message Buffering

The MCP2510 includes two full receive buffers with

multiple acceptance filters for each. There is also a

separate Message Assembly Buffer (MAB) which acts

as a third receive buffer (see Figure 4-1).

The RXBNCTRL.RXM bits set special receive modes.

Normally, these bits are set to 00 to enable reception of

all valid messages as determined by the appropriate

acceptance filters. In this case, the determination of

whether or not to receive standard or extended mes-

sages is determined by the RFXNSIDL.EXIDE bit in the

acceptance filter register. If the RXBNCTRL.RXM bits

are set to 01 or 10, the receiver will accept only mes-

sages with standard or extended identifiers respec-

tively. If an acceptance filter has the RFXNSIDL.EXIDE

bit set such that it does not correspond with the

RXBNCTRL.RXM mode, that acceptance filter is ren-

dered useless. These two modes of RXBNCTRL.RXM

bits can be used in systems where it is known that only

standard or extended messages will be on the bus. If

the RXBNCTRL.RXM bits are set to 11, the buffer will

receive all messages regardless of the values of the

acceptance filters. Also, if a message has an error

before the end of frame, that portion of the message

assembled in the MAB before the error frame will be

loaded into the buffer. This mode has some value in

debugging a CAN system and would not be used in an

actual system environment.

4.2

Receive Buffers

Of the three Receive Buffers, the MAB is always com-

mitted to receiving the next message from the bus. The

remaining two receive buffers are called RXB0 and

RXB1 and can receive a complete message from the

protocol engine. The MCU can access one buffer while

the other buffer is available for message reception or

holding a previously received message.

The MAB assembles all messages received. These

messages will be transferred to the RXBN buffers (See

Register 4-4 to Register 4-9) only if the acceptance fil-

ter criteria are met.

Note: The entire contents of the MAB is moved

into the receive buffer once a message is

accepted. This means that regardless of

the type of identifier (standard or extended)

and the number of data bytes received, the

entire receive buffer is overwritten with the

MAB contents. Therefore the contents of

all registers in the buffer must be assumed

to have been modified when any message

is received.

4.4

RX0BF and RX1BF Pins

In addition to the INT pin which provides an interrupt

signal to the MCU for many different conditions, the

receive buffer full pins (RX0BF and RX1BF) can be

used to indicate that a valid message has been loaded

into RXB0 or RXB1, respectively.

When a message is moved into either of the receive

buffers the appropriate CANINTF.RXNIF bit is set. This

bit must be cleared by the MCU, when it has completed

processing the message in the buffer, in order to allow

a new message to be received into the buffer. This bit

provides a positive lockout to ensure that the MCU has

finished with the message before the MCP2510

attempts to load a new message into the receive buffer.

If the CANINTE.RXNIE bit is set an interrupt will be gen-

erated on the INT pin to indicate that a valid message

has been received.

The RXBNBF full pins can be configured to act as buffer

full interrupt pins or as standard digital outputs. Config-

uration and status of these pins is available via the

BFPCTRL register (Register 4-3). When set to operate

in interrupt mode (by setting BFPCTRL.BxBFE and

BFPCTRL.BxBFM bits to a 1), these pins are active low

and are mapped to the CANINTF.RXNIF bit for each

receive buffer. When this bit goes high for one of the

receive buffers, indicating that a valid message has

been loaded into the buffer, the corresponding RXNBF

pin will go low. When the CANINTF.RXNIF bit is cleared

by the MCU, then the corresponding interrupt pin will

go to the logic high state until the next message is

loaded into the receive buffer.

4.3

Receive Priority

RXB0 is the higher priority buffer and has two message

acceptance filters associated with it. RXB1 is the lower

priority buffer and has four acceptance filters associ-

ated with it. The lower number of acceptance filters

makes the match on RXB0 more restrictive and implies

a higher priority for that buffer. Additionally, the

RXB0CTRL register can be configured such that if

RXB0 contains a valid message, and another valid

message is received, an overflow error will not occur

and the new message will be moved into RXB1 regard-

less of the acceptance criteria of RXB1. There are also

two programmable acceptance filter masks available,

one for each receive buffer (see Section 4.5).

When used as digital outputs, the BFPCTRL.BxBFM

bits must be cleared to a ‘0’ and BFPCTRL.BxBFE bits

must be set to a ‘1’ for the associated buffer. In this

mode the state of the pin is controlled by the BFPC-

TRL.BxBFS bits. Writting a ‘1’ to the BxBFS bit will

cause a high level to be driven on the assicated buffer

full pin, and a ‘0’ will cause the pin to drive low. When

using the pins in this mode the state of the pin should

be modified only by using the Bit Modify SPI command

to prevent glitches from occuring on either of the buffer

full pins.

DS21291F-page 21

MCP2510

FIGURE 4-1:

RECEIVE BUFFER BLOCK DIAGRAM

Acceptance Mask

RXM1

Acceptance Filter

RXF2

Acceptance Mask

RXM0

Acceptance Filter

RXF3

A

c

e

p

t

Acceptance Filter

RXF4

Acceptance Filter

RXF0

A

c

e

p

t

Acceptance Filter

RXF5

Acceptance Filter

RXF1

R

M

A

B

Identifier

X

B

0

X

B

1

Data Field

DS21291F-page 22

MCP2510

FIGURE 4-2:

MESSAGE RECEPTION FLOWCHART

Start

Detect

No

Start of

Message

?

Yes

Begin Loading Message into

Message Assembly Buffer (MAB)

Valid

Message

Received

?

Generate

Error

Frame

No

Yes

Yes, meets criteria

Message

Identifier meets

a filter criteria

?

for RXBO

for RXB1

No

Go to Start

The CANINTF.RXnIF bit

determines if the receive

register is empty and able

to accept a new message

The RXB0CTRL.BUKT

bit determines if RXB0

can roll over into RXB1

if it is full

Is

Yes

No

RXB0CTRL.BUKT=1

CANINTF.RX0IF=0

?

No

Yes

Is

No

Generate Overflow Error:

Set EFLG.RX0OVR

Generate Overflow Error:

Set EFLG.RX1OVR

Move message into RXB0

CANINTF.RX1IF = 0

?

Set CANINTF.RX0IF=1

Yes

Move message into RXB1

Is

No

Set RXB0CTRL.FILHIT <0>

CANINTE.ERRIE=1

according to which filter criteria

?

Set CANINTF.RX1IF=1

Yes

Go to Start

Set RXB0CTRL.FILHIT <2:0>

according to which filter criteria

was met

Yes

Generate

Interrupt on INT

CANINTE.RX0IE=1?

CANINTE.RX1IE=1?

No

RXB1

RXB0

Set CANSTAT <3:0> accord-

ing to which receive buffer

the message was loaded into

ARE

Yes

BFPCTRL.B1BFM=1

BFPCTRL.B0BFM=1

Set RXBF1

Pin = 0

AND

Set RXBF0

Pin = 0

AND

BF1CTRL.B1BFE=1

?

BF1CTRL.B0BFE=1

?

No

DS21291F-page 23

MCP2510

REGISTER 4-1:

RXB0CTRL - RECEIVE BUFFER 0 CONTROL REGISTER

(ADDRESS: 60h)

U-0

—

R/W-0

RXM1

R/W-0

RXM0

U-0

—

R-0

R/W-0

BUKT

R-0

RXRTR

BUKT1

FILHIT0

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-5

RXM<1:0>: Receive Buffer Operating Mode

11=Turn mask/filters off; receive any message

10=Receive only valid messages with extended identifiers that meet filter criteria

01=Receive only valid messages with standard identifiers that meet filter criteria

00=Receive all valid messages using either standard or extended identifiers that meet filter

criteria

bit 4

bit 3

Unimplemented: Read as '0'

RXRTR: Received Remote Transfer Request

1= Remote Transfer Request Received

0= No Remote Transfer Request Received

bit 2

BUKT: Rollover Enable

1= RXB0 message will rollover and be written to RXB1 if RXB0 is full

0= Rollover disabled

bit 1

bit 0

BUKT1: Read Only Copy of BUKT Bit (used internally by the MCP2510).

FILHIT<0>: Filter Hit - indicates which acceptance filter enabled reception of message

1= Acceptance Filter 1 (RXF1)

0= Acceptance Filter 0 (RXF0)

Note: If a rollover from RXB0 to RXB1 occurs, the FILHIT bit will reflect the filter that accepted

the message that rolled over

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 24

MCP2510

REGISTER 4-2:

RXB1CTRL - RECEIVE BUFFER 1 CONTROL REGISTER

(ADDRESS: 70h)

U-0

—

R/W-0

RXM1

R/W-0

RXM0

U-0

—

R-0

RXRTR

FILHIT2

FILHIT1

FILHIT0

bit 7

bit 0

bit 7

Unimplemented: Read as '0'

bit 6-5

RXM<1:0>: Receive Buffer Operating Mode

11=Turn mask/filters off; receive any message

10=Receive only valid messages with extended identifiers that meet filter criteria

01=Receive only valid messages with standard identifiers that meet filter criteria

00=Receive all valid messages using either standard or extended identifiers that meet filter

criteria

bit 4

bit 3

Unimplemented: Read as '0'

RXRTR: Received Remote Transfer Request

1= Remote Transfer Request Received

0= No Remote Transfer Request Received

bit 2-0

FILHIT<2:0>: Filter Hit - indicates which acceptance filter enabled reception of message

101= Acceptance Filter 5 (RXF5)

100= Acceptance Filter 4 (RXF4)

011= Acceptance Filter 3 (RXF3)

010= Acceptance Filter 2 (RXF2)

001= Acceptance Filter 1 (RXF1) (Only if BUKT bit set in RXB0CTRL)

000= Acceptance Filter 0 (RXF0) (Only if BUKT bit set in RXB0CTRL)

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 25

MCP2510

REGISTER 4-3:

BFPCTRL - RXNBF PIN CONTROL AND STATUS REGISTER

(ADDRESS: 0Ch)

U-0

—

U-0

—

R/W-0

B1BFS

B0BFS

B1BFE

B0BFE

B1BFM

B0BFM

bit 7

bit 0

bit 7

bit 6

bit 5

Unimplemented: Read as '0'

B1BFS: RX1BF Pin State (digital output mode only)

- Reads as ‘0’ when RX1BF is configured as interrupt pin

B0BFS: RX0BF Pin State (digital output mode only)

- Reads as ‘0’ when RX0BF is configured as interrupt pin

B1BFE: RX1BF Pin Function Enable

bit 4

bit 3

1 = Pin function enabled, operation mode determined by B1BFM bit

0= Pin function disabled, pin goes to high impedance state

bit 2

bit 1

bit 0

B0BFE: RX0BF Pin Function Enable

1= Pin function enabled, operation mode determined by B0BFM bit

0= Pin Function disabled, pin goes to high impedance state

B1BFM: RX1BF Pin Operation Mode

1= Pin is used as interrupt when valid message loaded into RXB1

0= Digital output mode

B0BFM: RX0BF Pin Operation Mode

1= Pin is used as interrupt when valid message loaded into RXB0

0= Digital output mode

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-4:

RXBNSIDH - RECEIVE BUFFER N STANDARD IDENTIFIER HIGH

(ADDRESS: 61h, 71h)

R-x

SID10

SID9

SID8

SID7

SID6

SID5

SID4

SID3

bit 7

bit 0

bit 7-0

SID<10:3>: Standard Identifier Bits <10:3>

These bits contain the eight most significant bits of the Standard Identifier for the received mes-

sage

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 26

MCP2510

REGISTER 4-5:

RXBNSIDL - RECEIVE BUFFER N STANDARD IDENTIFIER LOW

(ADDRESS: 62h, 72h)

R-x

IDE

U-0

—

R-x

SID2

SID1

SID0

SRR

EID17

EID16

bit 7

bit 0

bit 7-5

bit 4

SID<2:0>: Standard Identifier Bits <2:0>

These bits contain the three least significant bits of the Standard Identifier for the received mes-

sage

SRR: Standard Frame Remote Transmit Request Bit (valid only if IDE bit = ‘0’)

1= Standard Frame Remote Transmit Request Received

0= Standard Data Frame Received

bit 3

IDE: Extended Identifier Flag

This bit indicates whether the received message was a Standard or an Extended Frame

1= Received message was an Extended Frame

0= Received message was a Standard Frame

bit 2

Unimplemented: Reads as '0'

bit 1-0

EID<17:16>: Extended Identifier Bits <17:16>

These bits contain the two most significant bits of the Extended Identifier for the received mes-

sage

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-6:

RXBNEID8 - RECEIVE BUFFER N EXTENDED IDENTIFIER MID

(ADDRESS: 63h, 73h)

R-x

EID15

EID14

EID13

EID12

EID11

EID10

EID9

EID8

bit 7

bit 0

bit 7-0

EID<15:8>: Extended Identifier Bits <15:8>

These bits hold bits 15 through 8 of the Extended Identifier for the received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 27

MCP2510

REGISTER 4-7:

RXBNEID0 - RECEIVE BUFFER N EXTENDED IDENTIFIER LOW

(ADDRESS: 64h, 74h)

R-x

EID7

EID6

EID5

EID4

EID3

EID2

EID1

EID0

bit 7

bit 0

bit 7-0

EID<7:0>: Extended Identifier Bits <7:0>

These bits hold the least significant eight bits of the Extended Identifier for the received mes-

sage

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-8:

RXBNDLC - RECEIVE BUFFER N DATA LENGTH CODE

(ADDRESS: 65h, 75h)

U-0

—

R-x

RTR

RB1

RB0

DLC3

DLC2

DLC1

DLC0

bit 7

Unimplemented: Reads as '0'

bit 0

bit 7

bit 6

RTR: Extended Frame Remote Transmission Request Bit (valid only when RXBnSIDL.IDE = 1)

1= Extended Frame Remote Transmit Request Received

0= Extended Data Frame Received

bit 5

RB1: Reserved Bit 1

bit 4

RB0: Reserved Bit 0

bit 3-0

DLC<3:0>: Data Length Code

Indicates number of data bytes that were received

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-9:

RXBNDM - RECEIVE BUFFER N DATA FIELD BYTE M

(ADDRESS: 66h-6Dh, 76h-7Dh)

R-x

RBNDm7 RBNDm6 RBNDm5 RBNDm4 RBNDm3 RBNDm2 RBNDm1 RBNDm0

bit 7

bit 0

bit 7-0

RBNDm7:RBNDm0: Receive Buffer N Data Field Byte m

Eight bytes containing the data bytes for the received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 28

MCP2510

4.5

Message Acceptance Filters and

Masks

Note: 000and 001can only occur if the BUKT bit

(see Table 4-1) is set in the RXB0CTRL

register allowing RXB0 messages to roll

over into RXB1.

The Message Acceptance Filters And Masks are used

to determine if a message in the message assembly

buffer should be loaded into either of the receive buff-

ers (see Figure 4-3). Once a valid message has been

received into the MAB, the identifier fields of the mes-

sage are compared to the filter values. If there is a

match, that message will be loaded into the appropriate

receive buffer. The filter masks (see Register 4-10

through Register 4-17) are used to determine which

bits in the identifier are examined with the filters. A truth

table is shown below in Table 4-1 that indicates how

each bit in the identifier is compared to the masks and

filters to determine if a the message should be loaded

into a receive buffer. The mask essentially determines

which bits to apply the acceptance filters to. If any mask

bit is set to a zero, then that bit will automatically be

accepted regardless of the filter bit.

RXB0CTRL contains two copies of the BUKT bit and

the FILHIT<0> bit.

The coding of the BUKT bit enables these three bits to

be used similarly to the RXB1CTRL.FILHIT bits and to

distinguish a hit on filter RXF0 and RXF1 in either

RXB0 or after a roll over into RXB1.

- 111= Acceptance Filter 1 (RXF1)

- 110= Acceptance Filter 0 (RXF0)

- 001= Acceptance Filter 1 (RXF1)

- 000= Acceptance Filter 0

If the BUKT bit is clear, there are six codes correspond-

ing to the six filters. If the BUKT bit is set, there are six

codes corresponding to the six filters plus two addi-

tional codes corresponding to RXF0 and RXF1 filters

that roll over into RXB1.

TABLE 4-1:

FILTER/MASK TRUTH TABLE

Message

If more than one acceptance filter matches, the FILHIT

bits will encode the binary value of the lowest num-

bered filter that matched. In other words, if filter RXF2

and filter RXF4 match, FILHIT will be loaded with the

value for RXF2. This essentially prioritizes the accep-

tance filters with a lower number filter having higher pri-

ority. Messages are compared to filters in ascending

order of filter number.

Mask Bit

n

Filter Bit

Accept or

Identifier bit

n001

n

reject bit n

0

1

X

0

1

X

0

1

0

1

Accept

Reject

Accept

The mask and filter registers can only be modified

when the MCP2510 is in configuration mode (see

Section 9.0).

Note:

X = don’t care

As shown in the Receive Buffers Block Diagram

(Figure 4-1), acceptance filters RXF0 and RXF1, and

filter mask RXM0 are associated with RXB0. Filters

RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are

associated with RXB1. When a filter matches and a

message is loaded into the receive buffer, the filter

number that enabled the message reception is loaded

into the RXBNCTRL register FILHIT bit(s). For RXB1

the RXB1CTRL register contains the FILHIT<2:0> bits.

They are coded as follows:

- 101= Acceptance Filter 5 (RXF5)

- 100= Acceptance Filter 4 (RXF4)

- 011= Acceptance Filter 3 (RXF3)

- 010= Acceptance Filter 2 (RXF2)

- 001= Acceptance Filter 1 (RXF1)

- 000= Acceptance Filter 0 (RXF0)

DS21291F-page 29

MCP2510

FIGURE 4-3:

MESSAGE ACCEPTANCE MASK AND FILTER OPERATION

Acceptance Filter Register

Acceptance Mask Register

RXFn0

RXMn0

RXMn1

RxRqst

RXFn1

RXFnn

RXMnn

Message Assembly Buffer

Identifier

REGISTER 4-10:

RXFNSIDH - ACCEPTANCE FILTER N STANDARD IDENTIFIER HIGH

(ADDRESS: 00h, 04h, 08h, 10h, 14h, 18h)

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID<10:3>: Standard Identifier Filter Bits <10:3>

These bits hold the filter bits to be applied to bits <10:3> of the Standard Identifier portion of a

received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 30

MCP2510

REGISTER 4-11: RXFNSIDL - ACCEPTANCE FILTER N STANDARD IDENTIFIER LOW

(ADDRESS: 01h, 05h, 09h, 11h, 15h, 19h)

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

R/W-x

EXIDE

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

SID<2:0>: Standard Identifier Filter Bits <2:0>

These bits hold the filter bits to be applied to bits <2:0> of the Standard Identifier portion of a

received message

bit 4

bit 3

Unimplemented: Reads as '0'

EXIDE: Extended Identifier Enable

1= Filter is applied only to Extended Frames

0= Filter is applied only to Standard Frames

bit 2

Unimplemented: Reads as '0

bit 1-0

EID<17:16>: Exended Identifier Filter Bits <17:16>

These bits hold the filter bits to be applied to bits <17:16> of the Extended Identifier portion of

a received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-12: RXFNEID8 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER HIGH

(ADDRESS: 02h, 06h, 0Ah, 12h, 16h, 1Ah)

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID<15:8>: Extended Identifier Bits <15:8>

These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a

received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 31

MCP2510

REGISTER 4-13: RXFNEID0 - ACCEPTANCE FILTER N EXTENDED IDENTIFIER LOW

(ADDRESS: 03h, 07h, 0Bh, 13h, 17h, 1Bh)

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID<7:0>: Extended Identifier Bits <7:0>

These bits hold the filter bits to be applied to the bits <7:0> of the Extended Identifier portion of

a received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-14: RXMNSIDH - ACCEPTANCE FILTER MASK N STANDARD IDENTIFIER HIGH

(ADDRESS: 20h, 24h)

R/W-x

SID10

R/W-x

SID9

R/W-x

SID8

R/W-x

SID7

R/W-x

SID6

R/W-x

SID5

R/W-x

SID4

R/W-x

SID3

bit 7

bit 0

bit 7-0

SID<10:3>: Standard Identifier Mask Bits <10:3>

These bits hold the mask bits to be applied to bits <10:3> of the Standard Identifier portion of a

received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-15: RXMNSIDL - ACCEPTANCE FILTER MASK N STANDARD IDENTIFIER LOW

(ADDRESS: 21h, 25h)

R/W-x

SID2

R/W-x

SID1

R/W-x

SID0

U-0

—

U-0

—

U-0

—

R/W-x

EID17

R/W-x

EID16

bit 7

bit 0

bit 7-5

SID<2:0>: Standard Identifier Mask Bits <2:0>

These bits hold the mask bits to be applied to bits<2:0> of the Standard Identifier portion of a

received message

bit 4-2

bit 1-0

Unimplemented: Reads as '0'

EID<17:16>: Extended Identifier Mask Bits <17:16>

These bits hold the mask bits to be applied to bits <17:16> of the Extended Identifier portion of

a received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 32

MCP2510

REGISTER 4-16: RXMNEID8 - ACCEPTANCE FILTER MASK N EXTENDED IDENTIFIER HIGH

(ADDRESS: 22h, 26h)

R/W-x

EID15

R/W-x

EID14

R/W-x

EID13

R/W-x

EID12

R/W-x

EID11

R/W-x

EID10

R/W-x

EID9

R/W-x

EID8

bit 7

bit 0

bit 7-0

EID<15:8>: Extended Identifier Bits <15:8>

These bits hold the filter bits to be applied to bits <15:8> of the Extended Identifier portion of a

received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 4-17: RXMNEID0 - ACCEPTANCE FILTER MASK N EXTENDED IDENTIFIER LOW

(ADDRESS: 23h, 27h)

R/W-x

EID7

R/W-x

EID6

R/W-x

EID5

R/W-x

EID4

R/W-x

EID3

R/W-x

EID2

R/W-x

EID1

R/W-x

EID0

bit 7

bit 0

bit 7-0

EID<7:0>: Extended Identifier Mask Bits <7:0>

These bits hold the mask bits to be applied to the bits <7:0> of the Extended Identifier portion

of a received message

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 33

MCP2510

NOTES:

DS21291F-page 34

MCP2510

The nominal bit rate is the number of bits transmitted

per second assuming an ideal transmitter with an ideal

oscillator, in the absence of resynchronization. The

nominal bit rate is defined to be a maximum of 1 Mb/s.

5.0

BIT TIMING

All nodes on a given CAN bus must have the same

nominal bit rate. The CAN protocol uses Non Return to

Zero (NRZ) coding which does not encode a clock

within the data stream. Therefore, the receive clock

must be recovered by the receiving nodes and syn-

chronized to the transmitters clock.

Nominal Bit Time is defined as:

TBIT = 1 / NOMlNAL BlT RATE

The nominal bit time can be thought of as being divided

into separate non-overlapping time segments. These

segments are shown in Figure 5-1.

As oscillators and transmission time may vary from

node to node, the receiver must have some type of

Phase Lock Loop (PLL) synchronized to data transmis-

sion edges to synchronize and maintain the receiver

clock. Since the data is NRZ coded, it is necessary to

include bit stuffing to ensure that an edge occurs at

least every six bit times, to maintain the Digital Phase

Lock Loop (DPLL) synchronization.

- Synchronization Segment (Sync_Seg)

- Propagation Time Segment (Prop_Seg)

- Phase Buffer Segment 1 (Phase_Seg1)

- Phase Buffer Segment 2 [Phase_Seg2)

Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg +

Phase_Seg1 + Phase_Seg2)

The bit timing of the MCP2510 is implemented using a

DPLL that is configured to synchronize to the incoming

data, and provide the nominal timing for the transmitted

data. The DPLL breaks each bit time into multiple seg-

ments made up of minimal periods of time called the

time quanta (TQ).

The time segments and also the nominal bit time are

made up of integer units of time called time quanta or

T^Q(see Figure 5-1). By definition, the nominal bit time

is programmable from a minimum of 8 TQ to a maxi-

mum of 25 TQ. Also, by definition the minimum nominal

bit time is 1 µs, corresponding to a maximum 1 Mb/s

rate.

Bus timing functions executed within the bit time frame,

such as synchronization to the local oscillator, network

transmission delay compensation, and sample point

positioning, are defined by the programmable bit timing

logic of the DPLL.

All devices on the CAN bus must use the same bit rate.

However, all devices are not required to have the same

master oscillator clock frequency. For the different

clock frequencies of the individual devices, the bit rate

has to be adjusted by appropriately setting the baud

rate prescaler and number of time quanta in each seg-

ment.

FIGURE 5-1:

BIT TIME PARTITIONING

Input Signal

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

Sample Point

TQ

DS21291F-page 35

MCP2510

The total delay is calculated from the following individ-

ual delays:

5.1

Time Quanta

The Time Quanta (TQ) is a fixed unit of time derived

from the oscillator period. There is a programmable

baud-rate prescaler, with integral values ranging from 1

to 64, in addition to a fixed divide by two for clock gen-

eration.

- 2 * physical bus end to end delay; TBUS

- 2 * input comparator delay; TCOMP (depends

on application circuit)

- 2 * output driver delay; TDRIVE (depends on

application circuit)

Time quanta is defined as:

- 1 * input to output of CAN controller; TCAN

(maximum defined as 1 TQ + delay ns)

T_Q= 2*(Baud Rate + 1)*T_OSC

- TPROPOGATION = 2 * (TBUS + TCOMP +

TDRIVE) + TCAN

where Baud Rate is the binary value represented by

CNF1.BRP<5:0>

- Prop_Seg = TPROPOGATION / TQ

For some examples:

5.4

Phase Buffer Segments

If FOSC = 16 MHz, BRP<5:0> = 00h, and Nominal Bit

Time = 8 TQ;

The Phase Buffer Segments are used to optimally

locate the sampling point of the received bit within the

nominal bit time. The sampling point occurs between

phase segment 1 and phase segment 2. These seg-

ments can be lengthened or shortened by the resyn-

chronization process (see Section 5.7.2). Thus, the

variation of the values of the phase buffer segments

represent the DPLL functionality. The end of phase

segment 1 determines the sampling point within a bit

time. phase segment 1 is programmable from 1 TQ to 8

TQ in duration. Phase segment 2 provides delay before

the next transmitted data transition and is also pro-

grammable from 1 TQ to 8 TQ in duration (however due

to IPT requirements the actual minimum length of

phase segment 2 is 2 TQ - see Section 5.6 below), or it

may be defined to be equal to the greater of phase seg-

ment 1 or the Information Processing Time (IPT). (see

Section 5.6).

then TQ= 125 nsec and Nominal Bit Rate = 1 Mb/s

If FOSC = 20 MHz, BRP<5:0> = 01h, and Nominal Bit

Time = 8 TQ;

then TQ= 200 nsec and Nominal Bit Rate = 625 Kb/s

If FOSC = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit

Time = 25 TQ;

then TQ = 5.12 µsec and Nominal Bit Rate = 7.8 Kb/s

The frequencies of the oscillators in the different nodes

must be coordinated in order to provide a system-wide

specified nominal bit time. This means that all oscilla-

tors must have a TOSC that is a integral divisor of TQ. It

should also be noted that although the number of TQ is

programmable from 4 to 25, the usable minimum is 6

TQ Attempting to a bit time of less than 6 TQ in length

.

is not guaranteed to operate correctly

5.5

Sample Point

5.2

Synchronization Segment

The Sample Point is the point of time at which the bus

level is read and value of the received bit is determined.

The Sampling point occurs at the end of phase seg-

ment 1. If the bit timing is slow and contains many TQ,

it is possible to specify multiple sampling of the bus line

at the sample point. The value of the received bit is

determined to be the value of the majority decision of

three values. The three samples are taken at the sam-

ple point, and twice before with a time of TQ/2 between

each sample.

This part of the bit time is used to synchronize the var-

ious CAN nodes on the bus. The edge of the input sig-

nal is expected to occur during the sync segment. The

duration is 1 TQ.

5.3

Propagation Segment

This part of the bit time is used to compensate for phys-

ical delay times within the network. These delay times

consist of the signal propagation time on the bus line

and the internal delay time of the nodes. The delay is

calculated as being the round trip time from transmitter

to receiver (twice the signal's propagation time on the

bus line), the input comparator delay, and the output

driver delay. The length of the Propagation Segment

can be programmed from 1 TQ to 8 TQ by setting the

PRSEG2:PRSEG0 bits of the CNF2 register

(Register 5-2).

5.6

Information Processing Time

The Information Processing Time (IPT) is the time seg-

ment, starting at the sample point, that is reserved for

calculation of the subsequent bit level. The CAN spec-

ification defines this time to be less than or equal to 2

TQ. The MCP2510 defines this time to be 2 TQ. Thus,

phase segment 2 must be at least 2 TQ long.

DS21291F-page 36

MCP2510

The phase error of an edge is given by the position of

the edge relative to Sync Seg, measured in TQ. The

phase error is defined in magnitude of TQ as follows:

5.7

Synchronization

To compensate for phase shifts between the oscillator

frequencies of each of the nodes on the bus, each CAN

controller must be able to synchronize to the relevant

signal edge of the incoming signal. Synchronization is

the process by which the DPLL function is imple-

mented. When an edge in the transmitted data is

detected, the logic will compare the location of the edge

to the expected time (Sync Seg). The circuit will then

adjust the values of phase segment 1 and phase seg-

ment 2 as necessary. There are two mechanisms used

for synchronization.

• e = 0 if the edge lies within SYNCESEG

• e > 0 if the edge lies before the SAMPLE POINT

• e < 0 if the edge lies after the SAMPLE POINT of

the previous bit

If the magnitude of the phase error is less than or equal

to the programmed value of the synchronization jump

width, the effect of a resynchronization is the same as

that of a hard synchronization.

If the magnitude of the phase error is larger than the

synchronization jump width, and if the phase error is

positive, then phase segment 1 is lengthened by an

amount equal to the synchronization jump width.

5.7.1

HARD SYNCHRONIZATION

Hard Synchronization is only done when there is a

recessive to dominant edge during a BUS IDLE condi-

tion, indicating the start of a message. After hard syn-

chronization, the bit time counters are restarted with

Sync Seg. Hard synchronization forces the edge which

has occurred to lie within the synchronization segment

of the restarted bit time. Due to the rules of synchroni-

zation, if a hard synchronization occurs there will not be

a resynchronization within that bit time.

If the magnitude of the phase error is larger than the

resynchronization jump width, and if the phase error is

negative, then phase segment 2 is shortened by an

amount equal to the synchronization jump width.

5.7.3

SYNCHRONIZATION RULES

• Only one synchronization within one bit time is

allowed

5.7.2

RESYNCHRONIZATION

• An edge will be used for synchronization only if

the value detected at the previous sample point

(previously read bus value) differs from the bus

value immediately after the edge

As a result of Resynchronization, phase segment 1

may be lengthened or phase segment 2 may be short-

ened. The amount of lengthening or shortening of the

phase buffer segments has an upper bound given by

the Synchronization Jump Width (SJW). The value of

the SJW will be added to phase segment 1 (see

Figure 5-2) or subtracted from phase segment 2 (see

Figure 5-3). The SJW represents the loop filtering of

the DPLL. The SJW is programmable between 1 TQ

and 4 TQ.

• All other recessive to dominant edges fulfilling

rules 1 and 2 will be used for resynchronization

with the exception that a node transmitting a dom-

inant bit will not perform a resynchronization as a

result of a recessive to dominant edge with a pos-

itive phase error

Clocking information will only be derived from reces-

sive to dominant transitions. The property that only a

fixed maximum number of successive bits have the

same value ensures resynchronization to the bit stream

during a frame.

FIGURE 5-2:

Input Signal

LENGTHENING A BIT PERIOD

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

≤ SJW

Actual Bit

Length

Nominal

Bit Length

Sample

Point

TQ

DS21291F-page 37

MCP2510

FIGURE 5-3:

SHORTENING A BIT PERIOD

Input Signal

Prop

Segment

Phase

Segment 1

Phase

Segment 2

Sync

≤ SJW

Sample

Point

Actual

Bit Length

Nominal

Bit Length

TQ

5.8

Programming Time Segments

5.9

Oscillator Tolerance

Some requirements for programming of the time seg-

ments:

The bit timing requirements allow ceramic resonators

to be used in applications with transmission rates of up

to 125 kbit/sec, as a rule of thumb. For the full bus

speed range of the CAN protocol, a quartz oscillator is

required. A maximum node-to-node oscillator variation

of 1.7% is allowed.

• Prop Seg + Phase Seg 1 >= Phase Seg 2

• Prop Seg + Phase Seg 1 >= TDELAY

• Phase Seg 2 > Sync Jump Width

For example, assuming that a 125 kHz CAN baud rate

with FOSC = 20 MHz is desired:

TOSC = 50 nsec, choose BRP<5:0> = 04h, then TQ =

500 nsec. To obtain 125 kHz, the bit time must be 16

TQ.

Typically, the sampling of the bit should take place at

about 60-70% of the bit time, depending on the system

parameters. Also, typically, the TDELAY is 1-2 TQ.

Sync Seg = 1 TQ; Prop Seg = 2 TQ; So setting Phase

Seg 1 = 7 TQ would place the sample at 10 TQ after the

transition. This would leave 6 TQ for Phase Seg 2.

Since Phase Seg 2 is 6, by the rules, SJW could be the

maximum of 4 TQ. However, normally a large SJW is

only necessary when the clock generation of the differ-

ent nodes is inaccurate or unstable, such as using

ceramic resonators. So an SJW of 1 is typically

enough.

DS21291F-page 38

MCP2510

ting this bit to a ‘1’ causes the bus to be sampled three

times; twice at TQ/2 before the sample point, and once

at the normal sample point (which is at the end of phase

segment 1). The value of the bus is determined to be

the value read during at least two of the samples. If the

SAM bit is set to a ‘0’ then the RXCAN pin is sampled

only once at the sample point. The BTLMODE bit con-

trols how the length of phase segment 2 is determined.

If this bit is set to a ‘1’ then the length of phase segment

2 is determined by the PHSEG2<2:0> bits of CNF3

(see Section 5.10.3). If the BTLMODE bit is set to a ‘0’

then the length of phase segment 2 is the greater of

phase segment 1 and the information processing time

(which is fixed at 2 TQ for the MCP2510).

5.10 Bit Timing Configuration

Registers

The configuration registers (CNF1, CNF2, CNF3) con-

trol the bit timing for the CAN bus interface. These reg-

isters can only be modified when the MCP2510 is in

configuration mode (see Section 9.0).

5.10.1

CNF1

The BRP<5:0> bits control the baud rate prescaler.

These bits set the length of TQ relative to the OSC1

input frequency, with the minimum length of TQ being 2

OSC1 clock cycles in length (when BRP<5:0> are set

to 000000). The SJW<1:0> bits select the synchroni-

zation jump width in terms of number of TQ’s.

5.10.3

CNF3

5.10.2

CNF2

The PHSEG2<2:0> bits set the length, in TQ’s, of

Phase Segment 2, if the CNF2.BTLMODE bit is set to

a ‘1’. If the BTLMODE bit is set to a ‘0’ then the

PHSEG2<2:0> bits have no effect.

The PRSEG<2:0> bits set the length, in TQ’s, of the

propagation segment. The PHSEG1<2:0> bits set the

length, in TQ’s, of phase segment 1. The SAM bit con-

trols how many times the RXCAN pin is sampled. Set-

REGISTER 5-1:

CNF1 - CONFIGURATION REGISTER1 (ADDRESS: 2Ah)

R/W-0

SJW1

R/W-0

SJW0

R/W-0

BRP5

R/W-0

BRP4

R/W-0

BRP3

R/W-0

BRP2

R/W-0

BRP1

R/W-0

BRP0

bit 7

bit 0

bit 7-6

bit 5-0

SJW<1:0>: Synchronization Jump Width Length

11= Length = 4 x TQ

10= Length = 3 x TQ

01= Length = 2 x TQ

00= Length = 1 x TQ

BRP<5:0>: Baud Rate Prescaler

TQ = 2 x (BRP + 1) / FOSC

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 39

MCP2510

REGISTER 5-2:

CNF2 - CONFIGURATION REGISTER2 (ADDRESS: 29h)

R/W-0

BTLMODE

bit 7

R/W-0

SAM

R/W-0

PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0

bit 0

bit 7

bit 6

BTLMODE: Phase Segment 2 Bit Time Length

1= Length of Phase Seg 2 determined by PHSEG22:PHSEG20 bits of CNF3

0= Length of Phase Seg 2 is the greater of Phase Seg 1 and IPT (2TQ)

SAM: Sample Point Configuration

1= Bus line is sampled three times at the sample point

0= Bus line is sampled once at the sample point

bit 5-3

bit 2-0

PHSEG1<2:0>: Phase Segment 1 Length

(PHSEG1 + 1) x TQ

PRSEG<2:0>: Propagation Segment Length

(PRSEG + 1) x TQ

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 5-3:

CNF3 - CONFIGURATION REGISTER 3 (ADDRESS: 28h)

U-0

—

R/W-0

U-0

—

U-0

—

U-0

—

R/W-0

WAKFIL

PHSEG22 PHSEG21 PHSEG20

bit 0

bit 7

bit 6

Unimplemented: Reads as '0'

WAKFIL: Wake-up Filter

1= Wake-up filter enabled

0= Wake-up filter disabled

bit 5-3

bit 2-0

Unimplemented: Reads as '0'

PHSEG2<2:0>: Phase Segment 2 Length

(PHSEG2 + 1) x TQ

Note: Minimum valid setting for Phase Segment 2 is 2TQ

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 40

MCP2510

6.6

Error States

6.0

ERROR DETECTION

Detected errors are made public to all other nodes via

error frames. The transmission of the erroneous mes-

sage is aborted and the frame is repeated as soon as

possible. Furthermore, each CAN node is in one of the

three error states “error-active”, “error-passive” or “bus-

off” according to the value of the internal error counters.

The error-active state is the usual state where the bus

node can transmit messages and active error frames

(made of dominant bits) without any restrictions. In the

error-passive state, messages and passive error

frames (made of recessive bits) may be transmitted.

The bus-off state makes it temporarily impossible for

the station to participate in the bus communication.

During this state, messages can neither be received

nor transmitted.

The CAN protocol provides sophisticated error detec-

tion mechanisms. The following errors can be detected.

6.1

CRC Error

With the Cyclic Redundancy Check (CRC), the trans-

mitter calculates special check bits for the bit sequence

from the start of a frame until the end of the data field.

This CRC sequence is transmitted in the CRC Field.

The receiving node also calculates the CRC sequence

using the same formula and performs a comparison to

the received sequence. If a mismatch is detected, a

CRC error has occurred and an error frame is gener-

ated. The message is repeated.

6.2

Acknowledge Error

6.7

Error Modes and Error Counters

In the acknowledge field of a message, the transmitter

checks if the acknowledge slot (which has sent out as

a recessive bit) contains a dominant bit. If not, no other

node has received the frame correctly. An acknowl-

edge error has occurred; an error frame is generated;

and the message will have to be repeated.

The MCP2510 contains two error counters: the

Receive Error Counter (REC) (see Register 6-2), and

the Transmit Error Counter (TEC) (see Register 6-1).

The values of both counters can be read by the MCU.

These counters are incremented or decremented in

accordance with the CAN bus specification.

6.3

Form Error

The MCP2510 is error-active if both error counters are

below the error-passive limit of 128. It is error-passive

if at least one of the error counters equals or exceeds

128. It goes to bus-off if the transmit error counter

equals or exceeds the bus-off limit of 256. The device

remains in this state, until the bus-off recovery

sequence is received. The bus-off recovery sequence

consists of 128 occurrences of 11 consecutive reces-

sive bits (see Figure 6-1). Note that the MCP2510, after

going bus-off, will recover back to error-active, without

any intervention by the MCU, if the bus remains idle for

128 X 11 bit times. If this is not desired, the error inter-

rupt service routine should address this. The current

error mode of the MCP2510 can be read by the MCU

via the EFLG register (Register 6-3).

lf a node detects a dominant bit in one of the four seg-

ments including end of frame, interframe space,

acknowledge delimiter or CRC delimiter; then a form

error has occurred and an error frame is generated.

The message is repeated.

6.4

Bit Error

A Bit Error occurs if a transmitter sends a dominant bit

and detects a recessive bit or if it sends a recessive bit

and detects a dominant bit when monitoring the actual

bus level and comparing it to the just transmitted bit. In

the case where the transmitter sends a recessive bit

and a dominant bit is detected during the arbitration

field and the acknowledge slot, no bit error is generated

because normal arbitration is occurring.

Additionally, there is an error state warning flag bit,

EFLG:EWARN, which is set if at least one of the error

counters equals or exceeds the error warning limit of

96. EWARN is reset if both error counters are less than

the error warning limit.

6.5

Stuff Error

lf, between the start of frame and the CRC delimiter, six

consecutive bits with the same polarity are detected,

the bit stuffing rule has been violated. A stuff error

occurs and an error frame is generated. The message

is repeated.

DS21291F-page 41

MCP2510

FIGURE 6-1:

ERROR MODES STATE DIAGRAM

RESET

Error-Active

REC > 127 or

TEC > 127

128 occurrences of

11 consecutive

“recessive” bits

REC < 127 or

TEC < 127

Error-Passive

TEC > 255

Bus-Off

REGISTER 6-1:

TEC - TRANSMITTER ERROR COUNTER (ADDRESS: 1Ch)

R-0

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

bit 7

bit 0

bit 7-0

TEC<7:0>: Transmit Error Count

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

REGISTER 6-2:

REC - RECEIVER ERROR COUNTER (ADDRESS: 1Dh)

R-0

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

bit 7

bit 0

bit 7-0

REC<7:0>: Receive Error Count

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 42

MCP2510

REGISTER 6-3:

EFLG - ERROR FLAG REGISTER (ADDRESS: 2Dh)

R/W-0

R-0

RX1OVR RX0OVR

bit 7

TXBO

TXEP

RXEP

TXWAR

RXWAR

EWARN

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

RX1OVR: Receive Buffer 1 Overflow Flag

- Set when a valid message is received for RXB1 and CANINTF.RX1IF = 1

- Must be reset by MCU

RX0OVR: Receive Buffer 0 Overflow Flag

- Set when a valid message is received for RXB0 and CANINTF.RX0IF = 1

- Must be reset by MCU

TXBO: Bus-Off Error Flag

- Bit set when TEC reaches 255

- Reset after a successful bus recovery sequence

TXEP: Transmit Error-Passive Flag

- Set when TEC is equal to or greater than 128

- Reset when TEC is less than 128

RXEP: Receive Error-Passive Flag

- Set when REC is equal to or greater than 128

- Reset when REC is less than 128

TXWAR: Transmit Error Warning Flag

- Set when TEC is equal to or greater than 96

- Reset when TEC is less than 96

RXWAR: Receive Error Warning Flag

- Set when REC is equal to or greater than 96

- Reset when REC is less than 96

EWARN: Error Warning Flag

- Set when TEC or REC is equal to or greater than 96 (TXWAR or RXWAR = 1)

- Reset when both REC and TEC are less than 96

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 43

MCP2510

NOTES:

DS21291F-page 44

MCP2510

7.2

Transmit Interrupt

7.0

INTERRUPTS

When the Transmit Interrupt is enabled (CAN-

INTE.TXNIE = 1) an Interrupt will be generated on the

INT pin when the associated transmit buffer becomes

empty and is ready to be loaded with a new message.

The CANINTF.TXNIF bit will be set to indicate the

source of the interrupt. The interrupt is cleared by the

MCU resetting the TXNIF bit to a ‘0’.

The device has eight sources of interrupts. The CAN-

INTE register contains the individual interrupt enable

bits for each interrupt source. The CANINTF register

contains the corresponding interrupt flag bit for each

interrupt source. When an interrupt occurs the INT pin

is driven low by the MCP2510 and will remain low until

the Interrupt is cleared by the MCU. An Interrupt can

not be cleared if the respective condition still prevails.

7.3

Receive Interrupt

It is recommended that the bit modify command be

used to reset flag bits in the CANINTF register rather

than normal write operations. This is to prevent unin-

tentionally changing a flag that changes during the

write command, potentially causing an interrupt to be

missed.

When the Receive Interrupt is enabled (CAN-

INTE.RXNIE = 1) an interrupt will be generated on the

INT pin when a message has been successfully

received and loaded into the associated receive buffer.

This interrupt is activated immediately after receiving

the EOF field. The CANINTF.RXNIF bit will be set to

indicate the source of the interrupt. The interrupt is

cleared by the MCU resetting the RXNIF bit to a ‘0’.

It should be noted that the CANINTF flags are read/

write and an Interrupt can be generated by the MCU

setting any of these bits, provided the associated CAN-

INTE bit is also set.

7.4

Message Error Interrupt

7.1

Interrupt Code Bits

When an error occurs during transmission or reception

of message the message error flag (CAN-

a

The source of a pending interrupt is indicated in the

CANSTAT.ICOD (interrupt code) bits as indicated in

Register 9-2. In the event that multiple interrupts occur,

the INT will remain low until all interrupts have been

reset by the MCU, and the CANSTAT.ICOD bits will

reflect the code for the highest priority interrupt that is

currently pending. Interrupts are internally prioritized

such that the lower the ICOD value the higher the inter-

rupt priority. Once the highest priority interrupt condi-

tion has been cleared, the code for the next highest

priority interrupt that is pending (if any) will be reflected

by the ICOD bits (see Table 7-1). Note that only those

interrupt sources that have their associated CANINTE

enable bit set will be reflected in the ICOD bits.

INTF.MERRF) will be set and, if the CANINTE.MERRE

bit is set, an interrupt will be generated on the INT pin.

This is intended to be used to facilitate baud rate deter-

mination when used in conjunction with listen-only

mode.

7.5

Bus Activity Wakeup Interrupt

When the MCP2510 is in sleep mode and the bus activ-

ity wakeup interrupt is enabled (CANINTE.WAKIE = 1),

an interrupt will be generated on the INT pin, and the

CANINTF.WAKIF bit will be set when activity is

detected on the CAN bus. This interrupt causes the

MCP2510 to exit sleep mode. The interrupt is reset by

the MCU clearing the WAKIF bit.

TABLE 7-1:

ICOD<2:0> DECODE

ICOD<2:0>

000

Boolean Expression

ERR•WAK•TX0•TX1•TX2•RX0•RX1

ERR

001

010

ERR•WAK

011

ERR•WAK•TX0

100

ERR•WAK•TX0•TX1

101

ERR•WAK•TX0•TX1•TX2

ERR•WAK•TX0•TX1•TX2•RX0

ERR•WAK•TX0•TX1•TX2•RX0•RX1

110

111

DS21291F-page 45

MCP2510

7.6.4

RECEIVER ERROR-PASSIVE

7.6

Error Interrupt

The receive error counter has exceeded the error- pas-

sive limit of 127 and the device has gone to error- pas-

sive state.

When the error interrupt is enabled (CANINTE.ERRIE

= 1) an interrupt is generated on the INT pin if an over-

flow condition occurs or if the error state of transmitter

or receiver has changed. The Error Flag Register

(EFLG) will indicate one of the following conditions.

7.6.5

TRANSMITTER ERROR-PASSIVE

The transmit error counter has exceeded the error-

passive limit of 127 and the device has gone to error-

passive state.

7.6.1

RECEIVER OVERFLOW

An overflow condition occurs when the MAB has

assembled a valid received message (the message

meets the criteria of the acceptance filters) and the

receive buffer associated with the filter is not available

for loading of a new message. The associated

EFLG.RXNOVR bit will be set to indicate the overflow

condition. This bit must be cleared by the MCU.

7.6.6

BUS-OFF

The transmit error counter has exceeded 255 and the

device has gone to bus-off state.

7.7

Interrupt Acknowledge

7.6.2

RECEIVER WARNING

Interrupts are directly associated with one or more sta-

tus flags in the CANINTF register. Interrupts are pend-

ing as long as one of the flags is set. Once an interrupt

flag is set by the device, the flag can not be reset by the

MCU until the interrupt condition is removed.

The receive error counter has reached the MCU warn-

ing limit of 96.

7.6.3

TRANSMITTER WARNING

The transmit error counter has reached the MCU warn-

ing limit of 96.

DS21291F-page 46

MCP2510

REGISTER 7-1:

CANINTE - INTERRUPT ENABLE REGISTER (ADDRESS: 2Bh)

R/W-0

ERRIE

R/W-0

TX2IE

R/W-0

TX1IE

R/W-0

TX0IE

R/W-0

RX1IE

R/W-0

RX0IE

MERRE

WAKIE

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MERRE: Message Error Interrupt Enable

1= Interrupt on error during message reception or transmission

0= Disabled

WAKIE: Wakeup Interrupt Enable

1= Interrupt on CAN bus activity

0= Disabled

ERRIE: Error Interrupt Enable (multiple sources in EFLG register)

1 = Interrupt on EFLG error condition change

0= Disabled

TX2IE: Transmit Buffer 2 Empty Interrupt Enable

1= Interrupt on TXB2 becoming empty

0= Disabled

TX1IE: Transmit Buffer 1 Empty Interrupt Enable

1= Interrupt on TXB1 becoming empty

0= Disabled

TX0IE: Transmit Buffer 0 Empty Interrupt Enable

1= Interrupt on TXB0 becoming empty

0= Disabled

RX1IE: Receive Buffer 1 Full Interrupt Enable

1= Interrupt when message received in RXB1

0= Disabled

RX0IE: Receive Buffer 0 Full Interrupt Enable

1= Interrupt when message received in RXB0

0= Disabled

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 47

MCP2510

REGISTER 7-2:

CANINTF - INTERRUPT FLAG REGISTER (ADDRESS: 2Ch)

R/W-0

ERRIF

R/W-0

TX2IF

R/W-0

TX1IF

R/W-0

TX0IF

R/W-0

RX1IF

R/W-0

RX0IF

MERRF

WAKIF

bit 7

bit 0

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

MERRF: Message Error Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

WAKIF: Wakeup Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

ERRIF: Error Interrupt Flag (multiple sources in EFLG register)

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

TX2IF: Transmit Buffer 2 Empty Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

TX1IF: Transmit Buffer 1 Empty Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

TX0IF: Transmit Buffer 0 Empty Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

RX1IF: Receive Buffer 1 Full Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

RX0IF: Receive Buffer 0 Full Interrupt Flag

1= Interrupt pending (must be cleared by MCU to reset interrupt condition)

0= No interrupt pending

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 48

MCP2510

8.2

CLKOUT Pin

8.0

OSCILLATOR

The MCP2510 is designed to be operated with a crystal

or ceramic resonator connected to the OSC1 and

OSC2 pins. The MCP2510 oscillator design requires

the use of a parallel cut crystal. Use of a series cut crys-

tal may give a frequency out of the crystal manufactur-

ers specifications. A typical oscillator circuit is shown in

Figure 8-1. The MCP2510 may also be driven by an

external clock source connected to the OSC1 pin as

shown in Figure 8-2 and Figure 8-3.

The clock out pin is provided to the system designer for

use as the main system clock or as a clock input for

other devices in the system. The CLKOUT has an inter-

nal prescaler which can divide FOSC by 1, 2, 4 and 8.

The CLKOUT function is enabled and the prescaler is

selected via the CANCNTRL register (see Register 9-

1). The CLKOUT pin will be active upon system reset

and default to the slowest speed (divide by 8) so that it

can be used as the MCU clock. When sleep mode is

requested, the MCP2510 will drive sixteen additional

clock cycles on the CLKOUT pin before entering sleep

mode. The idle state of the CLKOUT pin in sleep mode

is low. When the CLKOUT function is disabled (CAN-

CNTRL.CLKEN = ‘0’) the CLKOUT pin is in a high

impedance state.

8.1

Oscillator Startup Timer

The MCP2510 utilizes an oscillator startup timer (OST),

which holds the MCP2510 in reset, to insure that the

oscillator has stabilized before the internal state

machine begins to operate. The OST maintains reset

for the first 128 OSC1 clock cycles after power up,

RESET, or wake up from sleep mode occurs. It should

be noted that no SPI operations should be attempted

until after the OST has expired.

The CLKOUT function is designed to guarantee that

t_hCLKOUT and t_lCLKOUT timings are preserved when the

CLKOUT pin function is enabled, disabled, or the pres-

caler value is changed.

FIGURE 8-1:

CRYSTAL/CERAMIC RESONATOR OPERATION

OSC1

C₁

To internal logic

SLEEP

XTAL

(2)

RF

(1)

RS

C₂

OSC2

Note 1: A series resistor, RS, may be required for AT strip cut crystals.

Note 2: The feedback resistor, RF, is typically in the range of 2 to 10 MΩ.

FIGURE 8-2:

EXTERNAL CLOCK SOURCE

Clock from

OSC1

external system

(1)

OSC2

Open

Note 1: A resistor to ground may be used to reduce system noise. This may increase system current.

Note 2: Duty cycle restrictions must be observed (see Table 12-2).

DS21291F-page 49

MCP2510

FIGURE 8-3:

EXTERNAL SERIES RESONANT CRYSTAL OSCILLATOR CIRCUIT

To Other

Devices

330 kΩ

74AS04

MCP2510

OSC1

0.1 mF

XTAL

Note 1: Duty cycle restrictions must be observed (see Table 12-2).

DS21291F-page 50

MCP2510

be placed into a sleep mode and use the MCP2510 to

wake it up upon detecting activity on the bus.

9.0

MODES OF OPERATION

The MCP2510 has five modes of operation. These

modes are:

Note: Care must be exercised to not enter sleep

mode while the MCP2510 is transmitting a

1. Configuration Mode.

2. Normal Mode.

message. If sleep mode is requested while

transmitting, the transmission will stop

without completing and errors will occur on

3. Sleep Mode.

4. Listen-Only Mode.

5. Loopback Mode.

the bus. Also, the message will remain

pending and transmit upon wake up.

When in sleep mode, the MCP2510 stops its internal

oscillator. The MCP2510 will wake-up when bus activity

occurs or when the MCU sets, via the SPI interface, the

CANINTF.WAKIF bit to ‘generate’ a wake up attempt

(the CANINTF.WAKIF bit must also be set in order for

the wakeup interrupt to occur). The TXCAN pin will

remain in the recessive state while the MCP2510 is in

sleep mode. Note that Sleep Mode will be entered

immediately, even if a message is currently being

transmitted, so it is necessary to insure that all TXREQ

bits are clear before setting Sleep Mode.

The operational mode is selected via the CANCTRL.

REQOP bits (see Register 9-1). When changing

modes, the mode will not actually change until all pend-

ing message transmissions are complete. Because of

this, the user must verify that the device has actually

changed into the requested mode before further oper-

ations are executed. Verification of the current operat-

ing mode is done by reading the CANSTAT. OPMODE

bits (see Register 9-2).

9.1

Configuration Mode

The MCP2510 must be initialized before activation.

This is only possible if the device is in the configuration

mode. Configuration mode is automatically selected

after powerup or a reset, or can be entered from any

other mode by setting the CANTRL.REQOP bits to

‘100’. When configuration mode is entered all error

counters are cleared. Configuration mode is the only

mode where the following registers are modifiable:

9.2.1

WAKE-UP FUNCTIONS

The device will monitor the RXCAN pin for activity while

it is in sleep mode. If the CANINTE.WAKIE bit is set,

the device will wake up and generate an interrupt.

Since the internal oscillator is shut down when sleep

mode is entered, it will take some amount of time for the

oscillator to start up and the device to enable itself to

receive messages. The device will ignore the message

that caused the wake-up from sleep mode as well as

any messages that occur while the device is ‘waking

up.’ The device will wake up in listen-only mode. The

MCU must set normal mode before the MCP2510 will

be able to communicate on the bus.

• CNF1, CNF2, CNF3

• TXRTSCTRL

• Acceptance Filter Registers

• Acceptance Mask Registers

Only when the CANSTAT.OPMODE bits read as ‘100’

can the initialization be performed, allowing the config-

uration registers, acceptance mask registers, and the

acceptance filter registers to be written. After the con-

figuration is complete, the device can be activated by

programming the CANCTRL.REQOP bits for normal

operation mode (or any other mode).

The device can be programmed to apply a low-pass fil-

ter function to the RXCAN input line while in internal

sleep mode. This feature can be used to prevent the

device from waking up due to short glitches on the CAN

bus lines. The CNF3.WAKFIL bit enables or disables

the filter.

9.3

Listen Only Mode

9.2

Sleep Mode

Listen-only mode provides a means for the MCP2510

to receive all messages including messages with

errors. This mode can be used for bus monitor applica-

tions or for detecting the baud rate in ‘hot plugging’ sit-

uations. For auto-baud detection it is necessary that

there are at least two other nodes, which are communi-

cating with each other. The baud rate can be detected

empirically by testing different values until valid mes-

sages are received. The listen-only mode is a silent

mode, meaning no messages will be transmitted while

in this state, including error flags or acknowledge sig-

nals. The filters and masks can be used to allow only

particular messages to be loaded into the receive reg-

isters, or the filter masks can be set to all zeros to allow

a message with any identifier to pass. The error

The MCP2510 has an internal sleep mode that is used

to minimize the current consumption of the device. The

SPI interface remains active even when the MCP2510

is in sleep mode, allowing access to all registers.

To enter sleep mode, the mode request bits are set in

the CANCTRL register. The CANSTAT.OPMODE bits

indicate whether the device successfully entered sleep

mode. These bits should be read after sending the

sleep command to the MCP2510. The MCP2510 is

active and has not yet entered sleep mode until these

bits indicate that sleep mode has been entered. When

in internal sleep mode, the wakeup interrupt is still

active (if enabled). This is done so the MCU can also

DS21291F-page 51

MCP2510

counters are reset and deactivated in this state. The lis-

ten-only mode is activated by setting the mode request

bits in the CANCTRL register.

9.5

Normal Mode

This is the standard operating mode of the MCP2510.

In this mode the device actively monitors all bus mes-

sages and generates acknowledge bits, error frames,

etc. This is also the only mode in which the MCP2510

will transmit messages over the CAN bus.

9.4

Loopback Mode

This mode will allow internal transmission of messages

from the transmit buffers to the receive buffers without

actually transmitting messages on the CAN bus. This

mode can be used in system development and testing.

In this mode the ACK bit is ignored and the device will

allow incoming messages from itself just as if they were

coming from another node. The loopback mode is a

silent mode, meaning no messages will be transmitted

while in this state, including error flags or acknowledge

signals. The TXCAN pin will be in a reccessive state

while the device is in this mode. The filters and masks

can be used to allow only particular messages to be

loaded into the receive registers. The masks can be set

to all zeros to provide a mode that accepts all mes-

sages. The loopback mode is activated by setting the

mode request bits in the CANCTRL register.

REGISTER 9-1:

CANCTRL - CAN CONTROL REGISTER (ADDRESS: XFh)

R/W-1

R/W-0

ABAT

U-0

—

R/W-1

REQOP2 REQOP1 REQOP0

bit 7

CLKEN CLKPRE1 CLKPRE0

bit 0

bit 7-5

REQOP<2:0>: Request Operation Mode

000= Set Normal Operation Mode

001= Set Sleep Mode

010= Set Loopback Mode

011= Set Listen Only Mode

100= Set Configuration Mode

All other values for REQOP bits are invalid and should not be used

Note: On power up, REQOP = b’111’

bit 4

ABAT: Abort All Pending Transmissions

1= Request abort of all pending transmit buffers

0= Terminate request to abort all transmissions

bit 3

bit 2

Unimplemented: Read as '0'

CLKEN: CLKOUT Pin Enable

1= CLKOUT pin enabled

0= CLKOUT pin disabled (Pin is in high impedance state)

bit 1-0

CLKPRE <1:0>: CLKOUT Pin Prescaler

00= FCLKOUT = System Clock/1

01= FCLKOUT = System Clock/2

10= FCLKOUT = System Clock/4

11= FCLKOUT = System Clock/8

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 52

MCP2510

REGISTER 9-2:

CANSTAT - CAN STATUS REGISTER (ADDRESS: XEh)

R-1

R-0

U-0

—

R-0

U-0

—

OPMOD2 OPMOD1 OPMOD0

bit 7

ICOD2

ICOD1

ICOD0

bit 0

bit 7-5

OPMOD<2:0>: Operation Mode

000= Device is in Normal Operation Mode

001= Device is in Sleep Mode

010= Device is in Loopback Mode

011= Device is in Listen Only Mode

100= Device is in Configuration Mode

bit 4

Unimplemented: Read as '0'

ICOD<2:0>: Interrupt Flag Code

bit 3-1

000= No Interrupt

001= Error Interrupt

010= Wake Up Interrupt

011= TXB0 Interrupt

100= TXB1 Interrupt

101= TXB2 Interrupt

110= RXB0 Interrupt

111= RXB1 Interrupt

bit 0

Unimplemented: Read as '0'

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

’1’ = Bit is set

U = Unimplemented bit, read as ‘0’

’0’ = Bit is cleared x = Bit is unknown

DS21291F-page 53

MCP2510

NOTES:

DS21291F-page 54

MCP2510

writing of data. Some specific control and status regis-

ters allow individual bit modification using the SPI Bit

Modify command. The registers that allow this com-

mand are shown as shaded locations in Table 10-1. A

summary of the MCP2510 control registers is shown in

Table 10-2.

10.0 REGISTER MAP

The register map for the MCP2510 is shown in

Table 10-1. Address locations for each register are

determined by using the column (higher order 4 bits)

and row (lower order 4 bits) values. The registers have

been arranged to optimize the sequential reading and

TABLE 10-1: CAN CONTROLLER REGISTER MAP

Lower

Address

Bits

Higher Order Address Bits

x000 xxxx x001 xxxx x010 xxxx x0011 xxxx x100 xxxx x101 xxxx x110 xxxx x111 xxxx

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Note:

RXF0SIDH

RXF0SIDL

RXF0EID8

RXF0EID0

RXF1SIDH

RXF1SIDL

RXF1EID8

RXF1EID0

RXF2SIDH

RXF2SIDL

RXF2EID8

RXF2EID0

BFPCTRL

TXRTSCTRL

CANSTAT

CANCTRL

RXF3SIDH RXM0SIDH

TXB0CTRL

TXB0SIDH

TXB0SIDL

TXB0EID8

TXB0EID0

TXB0DLC

TXB0D0

TXB1CTRL TXB2CTRL RXB0CTRL RXB1CTRL

TXB1SIDH TXB2SIDH RXB0SIDH RXB1SIDH

RXF3SIDL

RXF3EID8

RXF3EID0

RXM0SIDL

RXM0EID8

RXM0EID0

TXB1SIDL

TXB1EID8

TXB1EID0

TXB1DLC

TXB1D0

TXB1D1

TXB1D2

TXB1D3

TXB1D4

TXB1D5

TXB1D6

TXB1D7

CANSTAT

CANCTRL

TXB2SIDL

TXB2EID8

TXB2EID0

TXB2DLC

TXB2D0

TXB2D1

TXB2D2

TXB2D3

TXB2D4

TXB2D5

TXB2D6

TXB2D7

CANSTAT

CANCTRL

RXB0SIDL RXB1SIDL

RXB0EID8 RXB1EID8

RXB0EID0 RXB1EID0

RXF4SIDH RXM1SIDH

RXF4SIDL

RXF4EID8

RXF4EID0

RXF5SIDH

RXF5SIDL

RXF5EID8

RXF5EID0

TEC

RXM1SIDL

RXM1EID8

RXM1EID0

CNF3

RXB0DLC

RXB0D0

RXB0D1

RXB0D2

RXB0D3

RXB0D4

RXB0D5

RXB0D6

RXB0D7

CANSTAT

CANCTRL

RXB1DLC

RXB1D0

RXB1D1

RXB1D2

RXB1D3

RXB1D4

RXB1D5

RXB1D6

RXB1D7

CANSTAT

CANCTRL

TXB0D1

TXB0D2

CNF2

TXB0D3

CNF1

TXB0D4

CANINTE

CANINTF

EFLG

TXB0D5

TXB0D6

REC

TXB0D7

CANSTAT

CANCTRL

CANSTAT

CANCTRL

CANSTAT

CANCTRL

Shaded register locations indicate that these allow the user to manipulate individual bits using the ‘Bit Modify’ Command.

TABLE 10-2: CONTROL REGISTER SUMMARY

Register

Name

Address

(Hex)

POR/RST

Value

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

BFPCTRL

TXRTSCTRL

CANSTAT

CANCTRL

TEC

0C

0D

xE

xF

1C

1D

28

29

2A

2B

2C

2D

30

40

50

60

70

—

B1BFS

B2RTS

B0BFS

B1RTS

—

B1BFE

B0RTS

ICOD2

—

B0BFE

B1BFM

B0BFM --00 0000

B2RTSM B1RTSM B0RTSM --xx x000

ICOD1 ICOD0 100- 000-

OPMOD2 OPMOD1 OPMOD0

REQOP2 REQOP1 REQOP0

—

ABAT

CLKEN CLKPRE1 CLKPRE0 1110 -111

0000 0000

Transmit Error Counter

Receive Error Counter

REC

0000 0000

CNF3

—

WAKFIL

—

PHSEG22 PHSEG21 PHSEG20 -0-- -000

CNF2

BTLMODE

SJW1

SAM PHSEG12 PHSEG11 PHSEG10 PRSEG2 PRSEG1 PRSEG0 0000 0000

CNF1

SJW0

BRP5

ERRIE

ERRIF

TXBO

MLOA

RXM0

BRP4

TX2IE

TX2IF

TXEP

TXERR

—

BRP3

TX1IE

BRP2

TX0IE

TX0IF

TXWAR

—

BRP1

RX1IE

RX1IF

BRP0

RX0IE

RX0IF

0000 0000

CANINTE

CANINTF

EFLG

MERRE

MERRF

WAKIE

WAKIF

TX1IF

RX1OVR RX0OVR

RXEP

RXWAR EWARN 0000 0000

TXB0CTRL

TXB1CTRL

TXB2CTRL

RXB0CTRL

RXB1CTRL

—

ABTF

RXM1

RSM1

TXREQ

RXRTR

TXP1

TXP0

-000 0-00

—

TXP1

BUKT

FILHIT2

BUKT

FILHIT1

FILHIT0 -00- 0000

—

DS21291F-page 55

MCP2510

NOTES:

DS21291F-page 56

MCP2510

11.5 Read Status Instruction

11.0 SPI INTERFACE

11.1 Overview

The Read Status Instruction allows single instruction

access to some of the often used status bits for mes-

sage reception and transmission.

The MCP2510 is designed to interface directly with the

Serial Peripheral Interface (SPI) port available on many

microcontrollers and supports Mode 0,0 and Mode 1,1.

Commands and data are sent to the device via the SI

pin, with data being clocked in on the rising edge of

SCK. Data is driven out by the MCP2510, on the SO

line, on the falling edge of SCK. The CS pin must be

held low while any operation is performed. Table 11-1

shows the instruction bytes for all operations. Refer to

Figure 11-8 and Figure 11-9 for detailed input and out-

put timing diagrams for both Mode 0,0 and Mode 1,1

operation.

The part is selected by lowering the CS pin and the

read status command byte, shown in Figure 11-6, is

sent to the MCP2510. After the command byte is sent,

the MCP2510 will return eight bits of data that contain

the status. If additional clocks are sent after the first

eight bits are transmitted, the MCP2510 will continue to

output the status bits as long as the CS pin is held low

and clocks are provided on SCK. Each status bit

returned in this command may also be read by using

the standard read command with the appropriate regis-

ter address.

11.2 Read Instruction

11.6 Bit Modify Instruction

The Read Instruction is started by lowering the CS pin.

The read instruction is then sent to the MCP2510 fol-

lowed by the 8-bit address (A7 through A0). After the

read instruction and address are sent, the data stored

in the register at the selected address will be shifted out

on the SO pin. The internal address pointer is automat-

ically incremented to the next address after each byte

of data is shifted out. Therefore it is possible to read the

next consecutive register address by continuing to pro-

vide clock pulses. Any number of consecutive register

locations can be read sequentially using this method.

The read operation is terminated by raising the CS pin

(Figure 11-2).

The Bit Modify Instruction provides a means for setting

or clearing individual bits in specific status and control

registers. This command is not available for all regis-

ters. See Section 10.0 (register map) to determine

which registers allow the use of this command.

The part is selected by lowering the CS pin and the Bit

Modify command byte is then sent to the MCP2510.

After the command byte is sent, the address for the

register is sent followed by the mask byte and then the

data byte. The mask byte determines which bits in the

register will be allowed to change. A ‘1’ in the mask byte

will allow a bit in the register to change and a ‘0’ will not.

The data byte determines what value the modified bits

in the register will be changed to. A ‘1’ in the data byte

will set the bit and a ‘0’ will clear the bit, provided that

the mask for that bit is set to a ‘1’. (see Figure 11-1)

11.3 Write Instruction

The Write Instruction is started by lowering the CS pin.

The write instruction is then sent to the MCP2510 fol-

lowed by the address and at least one byte of data. It is

possible to write to sequential registers by continuing to

clock in data bytes, as long as CS is held low. Data will

actually be written to the register on the rising edge of

the SCK line for the D0 bit. If the CS line is brought high

before eight bits are loaded, the write will be aborted for

that data byte, previous bytes in the command will have

been written. Refer to the timing diagram in

Figure 11-3 for more detailed illustration of the byte

write sequence.

11.7 Reset Instruction

The Reset Instruction can be used to re-initialize the

internal registers of the MCP2510 and set configuration

mode. This command provides the same functionality,

via the SPI interface, as the RESET pin. The Reset

instruction is a single byte instruction which requires

selecting the device by pulling CS low, sending the

instruction byte, and then raising CS. It is highly recom-

mended that the reset command be sent (or the

RESET pin be lowered) as part of the power-on initial-

ization sequence. The MCP2510 will be held in reset

for 128 FOSC cycles.

11.4 Request To Send (RTS) Instruction

The RTS command can be used to initiate message

transmission for one or more of the transmit buffers.

The part is selected by lowering the CS pin and the

RTS command byte is then sent to the MCP2510. As

shown in Figure 11-4, the last 3 bits of this command

indicate which transmit buffer(s) are enabled to send.

This command will set the TxBnCTRL.TXREQ bit for

the respective buffer(s). Any or all of the last three bits

can be set in a single command. If the RTS command

is sent with nnn = 000, the command will be ignored.

DS21291F-page 57

MCP2510

FIGURE 11-1:

Mask byte

BIT MODIFY

0 0 1 1 0 1 0 1

X X 1 0 X 0 X 1

0 1 0 1 0 0 0 1

0 1 1 0 0 0 0 1

Data byte

Contents

Resulting

Register

Contents

TABLE 11-1: SPI INSTRUCTION SET

Instruction Name Instruction Format

Description

RESET

READ

1100 0000

0000 0011

0000 0010

1000 0nnn

Resets internal registers to default state, set configuration mode

Read data from register beginning at selected address

Write data to register beginning at selected address

WRITE

RTS

Sets TXBnCTRL.TXREQ bit for one or more transmit buffers

(Request To Send)

10000nnn

Request to send for TXB0

Request to send for TXB2

Request to send for TXB1

Read Status

Bit Modify

1010 0000

0000 0101

Polling command that outputs status bits for transmit/receive functions

Bit modify selected registers

FIGURE 11-2:

READ INSTRUCTION

CS

0

1

0

2

3

4

5

0

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

instruction

address byte

A0

don’t care

data out

0

1

A7

6

5

4

3

2

1

SI

high impedance

SO

7

6

5

4

3

2

1

0

FIGURE 11-3:

BYTE WRITE INSTRUCTION

CS

0

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

address byte

data byte

instruction

0

1

0

A7

6

5

4

3

2

1

A0

7

6

5

4

3

2

1

0

SI

high impedance

SO

DS21291F-page 58

MCP2510

FIGURE 11-4:

REQUEST TO SEND INSTRUCTION

CS

0

1

0

2

3

4

5

6

7

SCK

instruction

T1

0

T2

T0

SI

high impedance

SO

FIGURE 11-5:

BIT MODIFY INSTRUCTION

CS

23 24 25 26 27 28 29 30 31

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

0

SCK

data byte

6 5 4 3 2 1 0

mask byte

address byte

instruction

7

6 5 4 3 2 1 0

7

0

0 0 0 0 1 0 1 A7 6 5 4 3 2

1

A0

SI

high impedance

SO

Note: Not all registers can be accessed with this command. See the register map in Section 10.0

for a list of the registers that apply.

FIGURE 11-6:

READ STATUS INSTRUCTION

CS

0

1

0

2

3

4

5

0

6

0

7

8

9

10 11 12 13 14 15 16 17 18 19 20 21 22 23

SCK

instruction

don’t care

repeat

1

0

SI

data out

high impedance

SO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

CANINTF.RX0IF

CANINTF.RX1IF

TXB0CNTRL.TXREQ

CANINTF.TX0IF

TXB1CNTRL.TXREQ

CANINTF.TX1IF

TXB2CNTRL.TXREQ

CANINTF.TX2IF

DS21291F-page 59

MCP2510

FIGURE 11-7:

RESET INSTRUCTION

CS

0

1

2

3

4

5

0

6

0

7

SCK

instruction

0

SI

high impedance

SO

FIGURE 11-8:

SPI INPUT TIMING

3

CS

11

10

6

1

2

7

Mode 1,1

SCK

SI

Mode 0,0

4

5

MSB in

LSB in

high impedance

SO

FIGURE 11-9:

SPI OUTPUT TIMING

CS

2

8

9

SCK

Mode 1,1

Mode 0,0

12

14

LSB out

13

SO

SI

MSB out

don’t care

DS21291F-page 60

MCP2510

12.0 ELECTRICAL CHARACTERISTICS

12.1 Absolute Maximum Ratings†

VDD.............................................................................................................................................................................7.0V

All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VDD +1.0V

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temp. with power applied..........................................................................................................-65°C to +125°C

Soldering temperature of leads (10 seconds)....................................................................................................... +300°C

ESD protection on all pins ......................................................................................................................................................≥ 4 kV

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated in

the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended peri-

ods may affect device reliability.

DS21291F-page 61

MCP2510

TABLE 12-1:

DC CHARACTERISTICS

Industrial (I):

Extended (E):

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

VDD = 3.0V to 5.5V

VDD = 4.5V to 5.5V

DC Characteristics

Param.

No.

Sym

Characteristic

Supply Voltage

Min

3.0

2.4

Max

Units

Conditions

VDD

5.5

—

V

VRET

Register Retention Voltage

High Level Input Voltage

RXCAN

Note

VIH

2

VDD+1

VDD

V

SCK, CS, SI, TXnRTS Pins

OSC1

.7 VDD

.85 VDD

RESET

VDD

Low Level Input Voltage

RXCAN,TXnRTS Pins

SCK, CS, SI

Note

VIL

-0.3

VSS

.15 VDD

0.4

V

OSC1

.3 VDD

.15 VDD

RESET

Low Level Output Voltage

TXCAN

VOL

—

0.6

V

IOL = -6.0 mA, VDD = 4.5V

IOL = -8.5 mA, VDD = 4.5V

IOL = -2.1 mA, VDD = 4.5V

IOL = -1.6 mA, VDD = 4.5V

RXnBF Pins

SO, CLKOUT

INT

High Level Output Voltage

TXCAN, RXnBF Pins

SO, CLKOUT

VOH

VDD -0.7

VDD -0.5

VDD -0.7

—

IOH = 3.0 mA, VDD = 4.5V, I temp

IOH = 400 µA, VDD = 4.5V

IOH = 1.0 mA, VDD = 4.5V

INT

Input Leakage Current

ILI

All I/O except OSC1 and

TXnRTS pins

-1

+1

µA

CS = RESET = VDD,

VIN = VSS to VDD

OSC1 Pin

-5

+5

7

µA

pF

CINT

IDD

Internal Capacitance

—

TAMB = 25°C, f = 1.0 MHz,

C

VDD = 5.0V (Note)

(All Inputs And Outputs)

Operating Current

—

10

5

mA

µA

VDD = 5.5V, FOSC = 25 MHz,

FCLK = 1 MHz, SO = Open

IDDS

Standby Current (Sleep Mode)

CS, TXnRTS = VDD, Inputs tied to

VDD or VSS

Note:

This parameter is periodically sampled and not 100% tested.

DS21291F-page 62

MCP2510

TABLE 12-2: OSCILLATOR TIMING CHARACTERISTICS

Industrial (I):

Oscillator Timing Characteristics

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

VDD = 3.0V to 5.5V

VDD = 4.5V to 5.5V

Extended (E):

Param.

No.

Sym

FOSC

TOSC

Characteristic

Clock In Frequency

Min

Max

Units

Conditions

1

25

16

MHz

4.5V to 5.5V

3.0V to 4.5V

Clock In Period

40

62.5

1000

ns

4.5V to 5.5V

3.0V to 4.5V

TDUTY

Duty Cycle (External Clock

Input)

0.45

0.55

—

TOSH / (TOSH + TOSL)

Note:

This parameter is periodically sampled and not 100% tested.

TABLE 12-3: CAN INTERFACE AC CHARACTERISTICS

Industrial (I):

CAN Interface AC Characteristics

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

VDD = 3.0V to 5.5V

VDD = 4.5V to 5.5V

Extended (E):

Param.

No.

Sym

Characteristic

Min

Max

Units

Conditions

50

—

ns

TWF

Wakeup Noise Filter

100

TDCLK

CLOCKOUT Propagation

Delay

TABLE 12-4: CLKOUT PIN AC/DC CHARACTERISTICS

Industrial (I):

CLKOUT Pin AC/DC Characteristics

Extended (E):

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

VDD = 3.0V to 5.5V

VDD = 4.5V to 5.5V

Param.

No.

Sym

Characteristic

Min

Max

Units

Conditions

t CLKOUT CLKOUT Pin High Time

h

15

—

5

ns

TOSC = 40 ns (Note)

t CLKOUT CLKOUT Pin Low Time

l

TOSC = 40 ns (Note)

t CLKOUT CLKOUT Pin Rise Time

r

Measured from 0.3 VDD to 0.7 VDD

(Note)

t CLKOUT CLKOUT Pin Fall Time

f

—

5

ns

Measured from 0.7 VDD to 0.3 VDD

(Note)

t CLKOUT CLOCKOUT Propagation Delay

d

100

Note:

CLKOUT prescaler set to divide by one.

DS21291F-page 63

MCP2510

TABLE 12-5: SPI INTERFACE AC CHARACTERISTICS

Industrial (I):

SPI Interface AC Characteristics

TAMB = -40°C to +85°C

TAMB = -40°C to +125°C

VDD = 3.0V to 5.5V

VDD = 4.5V to 5.5V

Extended (E):

Param.

No.

Sym

Characteristic

Clock Frequency

Min

Max

Units

Conditions

FCLK

—

5

4

2.5

MHz

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

1

2

TCSS

TCSH

CS Setup Time

CS Hold Time

100

—

ns

100

115

180

—

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

3

4

5

TCSD

TSU

CS Disable Time

Data Setup Time

Data Hold Time

100

280

—

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

20

30

—

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

THD

20

50

—

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

6

7

8

TR

TF

CLK Rise Time

CLK Fall Time

Clock High Time

—

2

µs

Note

THI

90

115

180

—

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

9

TLO

Clock Low Time

90

115

180

—

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

10

11

12

TCLD

TCLE

TV

Clock Delay Time

50

—

ns

Clock Enable Time

Output Valid from Clock Low

—

90

115

180

ns

VDD = 4.5V to 5.5V

VDD = 4.5V to 5.5V (E temp)

VDD = 3.0V to 4.5V

13

14

THO

TDIS

Output Hold Time

0

—

ns

Note

Output Disable Time

—

200

Note:

This parameter is not 100% tested.

DS21291F-page 64

MCP2510

13.0 PACKAGING INFORMATION

13.1 Package Marking Information

18-Lead PDIP (300 mil)

Example:

XXXXXXXXXXXXXXXXX

YYWWNNN

MCP2510-I/P

e

XXXXXXXXXXXXXXXXX

0726NNN

3

18-Lead SOIC (300 mil)

Example:

XXXXXXXXXXXX

YYWWNNN

MCP2510-I/SO_e

XXXXXXXXXXXX

0737NNN

3

20-Lead TSSOP (4.4 mm)

Example:

XXXXXXXX

XXXXXNNN

YYWW

MCP2510

I/STNNN

0728

e

3

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21291F-page 65

MCP2510

18-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

2

3

1

D

E

A2

A

L

c

A1

b1

e

b

eB

Units

INCHES

NOM

18

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.880

.115

.008

.045

.014

–

.130

–

.310

.250

.900

.130

.010

.060

.018

–

.325

.280

.920

.150

.014

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-007B

DS21291F-page 66

MCP2510

18-Lead Plastic Small Outline (SO) – Wide, 7.50 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

b

α

h

c

φ

A2

A

β

A1

L

L1

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

18

1.27 BSC

Overall Height

A

–

2.65

–

Molded Package Thickness

Standoff §

A2

A1

E

2.05

0.10

–

0.30

Overall Width

10.30 BSC

Molded Package Width

Overall Length

E1

D

h

7.50 BSC

11.55 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.75

1.27

L

–

Footprint

L1

φ

1.40 REF

Foot Angle

0°

0.20

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.33

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-051B

DS21291F-page 67

MCP2510

20-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

e

b

c

φ

A2

A

L

A1

L1

MILLIMETERS

Units

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

20

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.20

1.05

0.15

A2

A1

E

0.80

0.05

1.00

–

Overall Width

Molded Package Width

Molded Package Length

Foot Length

6.40 BSC

E1

D

4.30

6.40

0.45

4.40

4.50

6.60

0.75

6.50

L

0.60

Footprint

L1

φ

1.00 REF

Foot Angle

0°

–

8°

Lead Thickness

Lead Width

c

0.09

0.20

0.30

b

0.19

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-088B

DS21291F-page 68

MCP2510

APPENDIX A: REVISION HISTORY

Revision F (January 2007)

This revision includes updates to the packaging

diagrams.

DS21291F-page 69

NOTES:

DS21291F-page 70

MCP2510

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

INDEX

A

L

Lenghtening a Bit Period . . . . . . . . . . . . . . . . . . . . . . . . . 37

Listen Only Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Loopback Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Acknowledge Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

B

BFpctrl - RXnBF Pin Control and Status Register . . . . . . . 26

Bit Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

BIT Modify instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Bit Modify Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Bit Timing Configuration Registers . . . . . . . . . . . . . . . . . . 39

Bit Timing Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Bus Activity Wakeup Interrupt . . . . . . . . . . . . . . . . . . . . . . 45

Bus Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Byte Write instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

M

Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Message Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . 30

Message Acceptance Filters and Masks . . . . . . . . . . . . . 29

Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Message Reception Flowchart . . . . . . . . . . . . . . . . . . . . . 23

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

N

Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

C

O

CAN Buffers and Protocol Engine Block Diagram . . . . . . . . 5

CAN controller Register Map . . . . . . . . . . . . . . . . . . . . . . . 55

CAN Interface AC characteristics . . . . . . . . . . . . . . . . . . . 63

CAN Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

CAN Protocol Engine Block Diagram . . . . . . . . . . . . . . . . . 6

CANCTRL - CAN Control Register . . . . . . . . . . . . . . . . . . 52

CANINTE - Interrupt Enable Register . . . . . . . . . . . . . . . . 47

CANSTAT - CAN Status Register . . . . . . . . . . . . . . . . . . . 53

CNF1 - Configuration Register1 . . . . . . . . . . . . . . . . . . . . 39

CNF2 - Configuration Register2 . . . . . . . . . . . . . . . . . . . . 40

CNF3 - Configuration Register3 . . . . . . . . . . . . . . . . . . . . 40

Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

CRC Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Crystal/ceramic resonator operation . . . . . . . . . . . . . . . . . 49

Cyclic Redundancy Check . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Oscillator Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Overload Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

P

Package Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Phase Buffer Segments . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Programming Time Segments . . . . . . . . . . . . . . . . . . . . . 38

Propagation Segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Protocol Finite State Machine . . . . . . . . . . . . . . . . . . . . . . 6

R

Read Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Read instruction Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 58

Read Status Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Read Status instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 59

REC - Receiver Error Count . . . . . . . . . . . . . . . . . . . . . . . 42

Receive Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Receive Buffers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . 22

Receive Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Receive Message Buffering . . . . . . . . . . . . . . . . . . . . . . . 21

Receiver Error Passive . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Receiver Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Receiver Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Remote Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Request To Send (RTS) Instruction . . . . . . . . . . . . . . 57, 59

Resynchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

RXB0BF and RXB1BF Pins . . . . . . . . . . . . . . . . . . . . . . . 21

RXB0CTRL - Receive Buffer 0 Control Register . . . . . . . 24

RXB1CTRL - Receive Buffer 1 Control Register . . . . . . . 25

RXBnDLC - Receive Buffer n Data Length Code . . . . . . . 28

RXBnDm - Receive Buffer n Data Field Byte m . . . . . . . . 28

RXBnEID0 - Receive Buffer n Extended Identifier Low . . 28

RXBnEID8 - Receive Buffer n Extended Identifier Mid . . 27

RXBnSIDH - Receive Buffer n Standard Identifier High . . 26

RXBnSIDL - Receive Buffer n Standard Identifier Low . . 27

RXFnEID0 - Acceptance Filter n Extended Identifier Low 32

RXFnEID8 - Acceptance Filter n Extended Identifier Mid 31

RXFnSIDH - Acceptance Filter n Standard Identifier High 30

RXFnSIDL - Acceptance Filter n Standard Identifier Low 31

RXMnEID0 - Acceptance Filter Mask n Extended Identifier

Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

RXMnEID8 - Acceptance Filter Mask n Extended Identifier

Mid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

RXMnSIDH - Acceptance Filter Mask n Standard Identifier

High . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

D

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

E

EFLG - Error Flag Register . . . . . . . . . . . . . . . . . . . . . . . . 43

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Error Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7, 13

Error Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Error Management Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Error Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Error Modes and Error Counters . . . . . . . . . . . . . . . . . . . . 41

Error States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Extended Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

External Clock (osc1) Timing characteristics . . . . . . . . . . . 63

External Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

External Series Resonant Crystal Oscillator Circuit . . . . . . 50

F

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Filter/Mask Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Form Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Frame Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

H

Hard Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

I

Information Processing Time . . . . . . . . . . . . . . . . . . . . . . . 36

Initiating Message Transmission . . . . . . . . . . . . . . . . . . . . 15

Interframe Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Interrupt Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DS21291F-page 71

MCP2510

RXMnSIDL - Acceptance Filter Mask n Standard Identifier

Low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

S

Sample Point . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Shortening a Bit Period . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

SPI Interface Overview . . . . . . . . . . . . . . . . . . . . . . . . . . .57

SPI Port AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .64

Standard Data Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Stuff Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Synchronization Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Synchronization Segment . . . . . . . . . . . . . . . . . . . . . . . . .36

T

TEC - Transmitter Error Count . . . . . . . . . . . . . . . . . . . . . .42

Time Quanta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Transmit Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Transmit Message Aborting . . . . . . . . . . . . . . . . . . . . . . . .15

Transmit Message Buffering . . . . . . . . . . . . . . . . . . . . . . .15

Transmit Message Buffers . . . . . . . . . . . . . . . . . . . . . . . . .15

Transmit Message flowchart . . . . . . . . . . . . . . . . . . . . . . .16

Transmit Message Priority . . . . . . . . . . . . . . . . . . . . . . . . .15

Transmitter Error Passive . . . . . . . . . . . . . . . . . . . . . . . . .46

Transmitter Warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

TXBnCTRL Transmit buffer n Control Register . . . . . . . . .17

TXBnDm - Transmit Buffer n Data Field Byte m . . . . . . . .20

TXBnEID0 - Transmit Buffer n Extended Identifier Low . .20

TXBnEID8 - Transmit Buffer n Extended Identifier Mid . . .19

TXBnEIDH - Transmit Buffer n Extended Identifier High . .19

TXBnSIDH - Transmit Buffer n Standard Identifier High . .18

TXBnSIDL - Transmit Buffer n Standard Identifier Low . . .19

TXnRTS Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

TXRTSCTRL - TXBNRTS Pin Control and Status Register

18

.

Typical System Implementation . . . . . . . . . . . . . . . . . . . . . .4

W

WAKE-up functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Write Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

WWW, On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . .2

DS21291F-page 72

MCP2510

THE MICROCHIP WEB SITE

CUSTOMER SUPPORT

Microchip provides online support via our WWW site at

www.microchip.com. This web site is used as a means

to make files and information easily available to

customers. Accessible by using your favorite Internet

browser, the web site contains the following

information:

Users of Microchip products can receive assistance

through several channels:

• Distributor or Representative

• Local Sales Office

• Field Application Engineer (FAE)

• Technical Support

• Product Support – Data sheets and errata,

application notes and sample programs, design

resources, user’s guides and hardware support

documents, latest software releases and archived

software

• Development Systems Information Line

Customers

should

contact

their

distributor,

representative or field application engineer (FAE) for

support. Local sales offices are also available to help

customers. A listing of sales offices and locations is

included in the back of this document.

• General Technical Support – Frequently Asked

Questions (FAQ), technical support requests,

online discussion groups, Microchip consultant

program member listing

Technical support is available through the web site

at: http://support.microchip.com

• Business of Microchip – Product selector and

ordering guides, latest Microchip press releases,

listing of seminars and events, listings of

Microchip sales offices, distributors and factory

representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE

Microchip’s customer notification service helps keep

customers current on Microchip products. Subscribers

will receive e-mail notification whenever there are

changes, updates, revisions or errata related to a

specified product family or development tool of interest.

To register, access the Microchip web site at

www.microchip.com, click on Customer Change

Notification and follow the registration instructions.

Advance Information

DS21291F-page 73

MCP2510

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod-

uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation

can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.

Please list the following information, and use this outline to provide us with your comments about this document.

To:

Technical Publications Manager

Reader Response

Total Pages Sent ________

RE:

From:

Name

Company

Address

City / State / ZIP / Country

Telephone: (_______) _________ - _________

FAX: (______) _________ - _________

Application (optional):

Would you like a reply?

Y

N

MCP2510

DS21291F

Literature Number:

Device:

Questions:

1. What are the best features of this document?

2. How does this document meet your hardware and software development needs?

3. Do you find the organization of this document easy to follow? If not, why?

4. What additions to the document do you think would enhance the structure and subject?

5. What deletions from the document could be made without affecting the overall usefulness?

6. Is there any incorrect or misleading information (what and where)?

7. How would you improve this document?

DS21291F-page 74

Advance Information

MCP2510

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a)

b)

c)

d)

e)

f)

MCP2510-E/P:

PDIP package.

Extended

Industrial

temperature,

Temperature Package

Range

MCP2510-I/P:

PDIP package.

MCP2510-E/SO: Extended

SOIC package.

Device:

MCP2510:

CAN Controller w/SPI Interface

MCP2510T: CAN Controller w/SPI Interface

(Tape and Reel)

MCP2510-I/SO:

SOIC package.

Industrial

MCP2510-I/SO:

temperature, SOIC package.

Tape and Reel, Industrial

Temperature Range:

Package:

-

E

=

-40°C to +85°C

-40°C to +125°C

MCP2510I/ST:

Industrial

temperature,

TSSOP package.

P

=

Plastic DIP (300 mil Body), 18-Lead

Plastic SOIC (300 mil Body), 18-Lead

TSSOP, (4.4 mm Body), 20-Lead

SO

ST

g)

MCP2510T-I/ST: Tape and Reel, Industrial

temperature, TSSOP package.

DS21291F-page75

MCP2510

NOTES:

DS21291F-page 76

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21291F-page 77

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21291F-page 78

MCP2510

™

Stand-Alone CAN Controller with SPI Interface 1

1.0

2.0

3.0

4.0

5.0

6.0

7.0

8.0

Device Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Can Message Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Message Transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Message Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

SPI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

9.0

10.0

11.0

12.0

13.0

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

On-Line Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Reader Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Product Identification System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Worldwide Sales and Service ............................................................................................................................................................. 76

DS21291F-page 79

MCP2510

DS21291F-page 80


型号：	MCP2510T-I/STVAO
厂家：	MICROCHIP
描述：	1 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDSO20, 4.40 MM, PLASTIC, TSSOP-20 光电二极管
文件：	总80页 (文件大小：1002K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP2510T-I/STVAO [MICROCHIP]

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