MCP2562FD-H/P [MICROCHIP]
High-Speed CAN Flexible Data Rate Transceiver;
| 型号： | MCP2562FD-H/P |
| 厂家： | 
MICROCHIP |
| 描述： | High-Speed CAN Flexible Data Rate Transceiver |
| 文件： | 总32页 (文件大小：1322K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP2561/2FD
High-Speed CAN Flexible Data Rate Transceiver
Features:
Description:
• Optimized for CAN FD (Flexible Data rate) at 2, 5
and 8 Mbps Operation
The MCP2561/2FD is a second generation high-speed
CAN transceiver from Microchip Technology Inc. It
offers the same features as the MCP2561/2.
Additionally, it guarantees Loop Delay Symmetry in
order to support the higher data rates required for CAN
FD. The maximum propagation delay was improved to
support longer bus length.
The device meets the automotive requirements for
CAN FD bit rates exceeding 2 Mbps, low quiescent
current, electromagnetic compatibility (EMC) and
electrostatic discharge (ESD).
- Maximum Propagation Delay: 120 ns
- Loop Delay Symmetry: -10%/+10% (2 Mbps)
• Implements ISO-11898-2 and ISO-11898-5
Standard Physical Layer Requirements
• Very Low Standby Current (5 µA, typical)
• VIO Supply Pin to Interface Directly to
CAN Controllers and Microcontrollers with
1.8V to 5.5V I/O
• SPLIT Output Pin to Stabilize Common Mode in
Biased Split Termination Schemes
• CAN Bus Pins are Disconnected when Device is
Unpowered
Package Types
MCP2561FD
MCP2562FD
PDIP, SOIC
PDIP, SOIC
- An Unpowered Node or Brown-Out Event will
Not Load the CAN Bus
• Detection of Ground Fault:
TXD
VSS
STBY
CANH
1
2
8
7
TXD
VSS
STBY
CANH
1
2
8
7
- Permanent Dominant Detection on TXD
- Permanent Dominant Detection on Bus
• Power-on Reset and Voltage Brown-Out
Protection on VDD Pin
VDD 3
6
5
CANL
SPLIT
VDD 3
6
5
CANL
VIO
4
RXD
4
RXD
MCP2561FD
MCP2562FD
3x3 DFN*
3x3 DFN*
• Protection Against Damage Due to Short-Circuit
Conditions (Positive or Negative Battery Voltage)
• Protection Against High-Voltage Transients in
Automotive Environments
• Automatic Thermal Shutdown Protection
• Suitable for 12V and 24V Systems
• Meets or exceeds stringent automotive design
requirements including “Hardware Requirements
for LIN, CAN and FlexRay Interfaces in
Automotive Applications”, Version 1.3, May 2012
- Radiated emissions @ 2 Mbps with Common
Mode Choke (CMC)
TXD
VSS
STBY
CANH
1
2
8
7
TXD
VSS
STBY
CANH
1
2
8
7
EP
9
EP
9
VDD
RXD
CANL
SPLIT
3
4
6
5
VDD
RXD
CANL
VIO
3
4
6
5
* Includes Exposed Thermal Pad (EP); see Table 1-2
- DPI @ 2 Mbps with CMC
• High ESD Protection on CANH and CANL,
meeting IEC61000-4-2 up to ±14 kV
• Available in PDIP-8L, SOIC-8L and 3x3 DFN-8L
• Temperature ranges:
- Extended (E): -40°C to +125°C
- High (H): -40°C to +150°C
MCP2561/2FD Family Members
Device
Feature
Description
MCP2561FD
MCP2562FD
SPLIT pin
VIO pin
Common mode stabilization
Internal level shifter on digital I/O pins
Note: For ordering information, see the “Product Identification System” section on page 29.
2014 Microchip Technology Inc.
DS20005284A-page 1
MCP2561/2FD
Block Diagram
SPLIT(2)
V
IO(3)
VDD
Digital I/O
Supply
Thermal
Protection
POR
UVLO
VDD/2
V
IO
Permanent
Dominant Detect
T
XD
CANH
CANL
Driver
and
Slope Control
V
IO
Mode
Control
STBY
CANH
Wake-Up
Filter
LP_RX(1)
HS_RX
CANL
Receiver
R
XD
CANH
CANL
VSS
Note 1: There is only one receiver implemented. The receiver can operate in Low-Power or High-Speed mode.
2: Only MCP2561FD has the SPLIT pin.
3: Only MCP2562FD has the VIO pin. In MCP2561FD, the supply for the digital I/O is internally connected
to VDD.
DS20005284A-page 2
2014 Microchip Technology Inc.
MCP2561/2FD
1.1.1
NORMAL MODE
1.0
DEVICE OVERVIEW
Normal mode is selected by applying low-level voltage
to the STBY pin. The driver block is operational and
can drive the bus pins. The slopes of the output signals
on CANH and CANL are optimized to produce minimal
electromagnetic emissions (EME).
The MCP2561/2FD is a high-speed CAN device,
fault-tolerant device that serves as the interface
between a CAN protocol controller and the physical
bus. The MCP2561/2FD device provides differential
transmit and receive capability for the CAN protocol
controller, and is fully compatible with the ISO-11898-2
and ISO-11898-5 standards.
The high speed differential receiver is active.
1.1.2
STANDBY MODE
The Loop Delay Symmetry is guaranteed to support
data rates that are up to 5 Mbps for CAN FD (Flexible
Data rate). The maximum propagation delay was
improved to support longer bus length.
The device may be placed in Standby mode by
applying high-level voltage to the STBY pin. In Standby
mode, the transmitter and the high-speed part of the
receiver are switched off to minimize power
consumption. The low-power receiver and the wake-up
filter blocks are enabled to monitor the bus for activity.
The receive pin (RXD) will show
representation of the CAN bus, due to the wake-up
filter.
Typically, each node in a CAN system must have a
device to convert the digital signals generated by a
CAN controller to signals suitable for transmission over
the bus cabling (differential output). It also provides a
buffer between the CAN controller and the high-voltage
spikes that can be generated on the CAN bus by
outside sources.
a
delayed
The CAN controller gets interrupted by a negative edge
on the RXD pin (Dominant state on the CAN bus). The
CAN controller must put the MCP2561/2FD back into
Normal mode, using the STBY pin, in order to enable
high speed data communication.
1.1
Mode Control Block
The MCP2561/2FD supports two modes of operation:
• Normal Mode
• Standby Mode
The CAN bus wake-up function requires both supply
voltages, VDD and VIO, to be in valid range.
These modes are summarized in Table 1-1.
TABLE 1-1:
Mode
MODES OF OPERATION
RXD Pin
STBY Pin
LOW
HIGH
Normal
LOW
Bus is Dominant
Bus is Recessive
Standby
HIGH
Wake-up request is detected
No wake-up request detected
1.2
Transmitter Function
1.4
Internal Protection
The CAN bus has two states:
CANH and CANL are protected against battery
short-circuits and electrical transients that can occur on
the CAN bus. This feature prevents destruction of the
transmitter output stage during such a fault condition.
• Dominant State
• Recessive State
A Dominant state occurs when the differential voltage
between CANH and CANL is greater than VDIFF(D)(I).
A Recessive state occurs when the differential voltage
is less than VDIFF(R)(I). The Dominant and Recessive
states correspond to the Low and High state of the TXD
input pin, respectively. However, a Dominant state
The device is further protected from excessive current
loading by thermal shutdown circuitry that disables the
output drivers when the junction temperature exceeds
a nominal limit of +175°C. All other parts of the chip
remain operational, and the chip temperature is
lowered due to the decreased power dissipation in the
transmitter outputs. This protection is essential to
protect against bus line short-circuit-induced damage.
initiated by another CAN node will override
Recessive state on the CAN bus.
a
1.3
Receiver Function
In Normal mode, the RXD output pin reflects the
differential bus voltage between CANH and CANL. The
Low and High states of the RXD output pin correspond
to the Dominant and Recessive states of the CAN bus,
respectively.
2014 Microchip Technology Inc.
DS20005284A-page 3
MCP2561/2FD
1.5
Permanent Dominant Detection
1.6
Power-On Reset (POR) and
Undervoltage Detection
The MCP2561/2FD device prevents two conditions:
The MCP2561/2FD has undervoltage detection on
both supply pins: VDD and VIO. Typical undervoltage
thresholds are 1.2V for VIO and 4V for VDD.
• Permanent Dominant condition on TXD
• Permanent Dominant condition on the bus
In Normal mode, if the MCP2561/2FD detects an
extended Low state on the TXD input, it will disable the
CANH and CANL output drivers in order to prevent the
corruption of data on the CAN bus. The drivers will
remain disabled until TXD goes High.
When the device is powered on, CANH and CANL
remain in a high-impedance state until both VDD and
VIO exceed their undervoltage levels. Once powered
on, CANH and CANL will enter a high-impedance state
if the voltage level at VDD drops below the undervoltage
level, providing voltage brown-out protection during
normal operation.
In Standby mode, if the MCP2561/2FD detects an
extended Dominant condition on the bus, it will set the
RXD pin to Recessive state. This allows the attached
controller to go to Low-Power mode until the Dominant
issue is corrected. RXD is latched High until a
Recessive state is detected on the bus, and the
wake-up function is enabled again.
In Normal mode, the receiver output is forced to
Recessive state during an undervoltage condition on
VDD. In Standby mode, the low-power receiver is only
enabled when both VDD and VIO supply voltages rise
above their respective undervoltage thresholds. Once
these threshold voltages are reached, the low-power
receiver is no longer controlled by the POR comparator
and remains operational down to about 2.5V on the
VDD supply (MCP2561/2FD). The MCP2562FD
transfers data to the RXD pin down to 1.8V on the VIO
supply.
Both conditions have a time-out of 1.25 ms (typical).
This implies
a maximum bit time of 69.44 µs
(14.4 kHz), allowing up to 18 consecutive dominant bits
on the bus.
1.7
Pin Descriptions
Table 1-2 describes the pinout.
TABLE 1-2:
MCP2561/2FD PIN DESCRIPTIONS
MCP2561FD MCP2561FD MCP2562FD MCP2562FD
Symbol
Pin Function
Transmit Data Input
3x3 DFN
PDIP, SOIC
3x3 DFN
PDIP, SOIC
1
2
1
2
1
2
1
2
TXD
VSS
VDD
RXD
Ground
3
3
3
3
Supply Voltage
Receive Data Output
4
4
4
4
5
5
—
5
—
5
SPLIT Common Mode Stabilization - MCP2561FD only
Digital I/O Supply Pin - MCP2562FD only
—
6
—
6
VIO
6
6
CANL CAN Low-Level Voltage I/O
CANH CAN High-Level Voltage I/O
STBY Standby Mode Input
7
7
7
7
8
8
8
8
9
—
9
—
EP
Exposed Thermal Pad
DS20005284A-page 4
2014 Microchip Technology Inc.
MCP2561/2FD
1.7.1
TRANSMITTER DATA
1.7.6
VIO PIN (MCP2562FD ONLY)
INPUT PIN (TXD)
Supply for digital I/O pins. In the MCP2561FD, the
supply for the digital I/O (TXD, RXD and STBY) is
internally connected to VDD.
The CAN transceiver drives the differential output pins
CANH and CANL according to TXD. It is usually
connected to the transmitter data output of the CAN
controller device. When TXD is Low, CANH and CANL
are in the Dominant state. When TXD is High, CANH
and CANL are in the Recessive state, provided that
another CAN node is not driving the CAN bus with a
Dominant state. TXD is connected to an internal pull-up
resistor (nominal 33 k) to VDD or VIO, in the
MCP2561FD or MCP2562FD, respectively.
1.7.7
CAN LOW PIN (CANL)
The CANL output drives the Low side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANL disconnects from the
bus when MCP2561/2FD is not powered.
1.7.8
CAN HIGH PIN (CANH)
The CANH output drives the high-side of the CAN
differential bus. This pin is also tied internally to the
receive input comparator. CANH disconnects from the
bus when MCP2561/2FD is not powered.
1.7.2
GROUND SUPPLY PIN (VSS)
Ground supply pin.
1.7.3
SUPPLY VOLTAGE PIN (VDD)
1.7.9
STANDBY MODE INPUT PIN (STBY)
Positive supply voltage pin. Supplies transmitter and
receiver, including the wake-up receiver.
This pin selects between Normal or Standby mode. In
Standby mode, the transmitter, high speed receiver and
SPLIT are turned off, only the low power receiver and
wake-up filter are active. STBY is connected to an
internal MOS pull-up resistor to VDD or VIO, in the
MCP2561FD or MCP2562FD, respectively. The value
of the MOS pull-up resistor depends on the supply volt-
age. Typical values are 660 k for 5V, 1.1 M for 3.3V
and 4.4 M for 1.8V
1.7.4
RECEIVER DATA
OUTPUT PIN (RXD)
RXD is a CMOS-compatible output that drives High or
Low depending on the differential signals on the CANH
and CANL pins, and is usually connected to the
receiver data input of the CAN controller device. RXD is
High when the CAN bus is Recessive, and Low in the
Dominant state. RXD is supplied by VDD or VIO, in the
MCP2561FD or MCP2562FD, respectively.
1.7.10
EXPOSED THERMAL PAD (EP)
It is recommended that this pad is connected to VSS for
the enhancement of electromagnetic immunity and
thermal resistance.
1.7.5
SPLIT PIN (MCP2561FD ONLY)
Reference Voltage Output (defined as VDD/2). The pin
is only active in Normal mode. In Standby mode, or
when VDD is off, SPLIT floats.
2014 Microchip Technology Inc.
DS20005284A-page 5
MCP2561/2FD
1.8
Typical Applications
In order to meet the EMC/EMI requirements, a
Common Mode Choke (CMC) might be required for
data rates greater than 1 Mbps.
FIGURE 1-1:
MCP2561FD WITH SPLIT PIN
VBAT
5V LDO
0.1 μF
CANH
CANL
VDD
VSS
VDD
CANH
SPLIT
CANL
CANTX
TXD
60
PIC®
300
CANRX
MCU
RXD
4700 pF
Optional(1)
RBX
STBY
60
VSS
Note 1: Optional resistor to allow communication during bus failure (CANL shorted to ground).
FIGURE 1-2:
MCP2562FD WITH VIO PIN
VBAT
5V LDO
1.8V LDO
0.1 μF
0.1 μF
CANH
CANL
VDD
VIO
TXD
VDD
CANH
CANTX
PIC®
CANRX
MCU
RXD
120
RBX
STBY
CANL
VSS
Vss
DS20005284A-page 6
2014 Microchip Technology Inc.
MCP2561/2FD
2.1.5
DIFFERENTIAL VOLTAGE, VDIFF
(OF CAN BUS)
2.0
2.1
ELECTRICAL
CHARACTERISTICS
Differential voltage of the two-wire CAN bus, value
VDIFF = VCANH – VCANL.
Terms and Definitions
A number of terms are defined in ISO-11898 that are
used to describe the electrical characteristics of a CAN
transceiver device. These terms and definitions are
summarized in this section.
2.1.6
INTERNAL CAPACITANCE, CIN
(OF A CAN NODE)
Capacitance seen between CANL (or CANH) and
ground during the Recessive state, when the CAN
node is disconnected from the bus (see Figure 2-1).
2.1.1
BUS VOLTAGE
VCANL and VCANH denote the voltages of the bus line
wires CANL and CANH relative to ground of each
individual CAN node.
2.1.7
INTERNAL RESISTANCE, RIN
(OF A CAN NODE)
Resistance seen between CANL (or CANH) and
ground during the Recessive state, when the CAN
node is disconnected from the bus (see Figure 2-1).
2.1.2
COMMON MODE BUS VOLTAGE
RANGE
Boundary voltage levels of VCANL and VCANH with
respect to ground, for which proper operation will occur,
if up to the maximum number of CAN nodes are
connected to the bus.
FIGURE 2-1:
PHYSICAL LAYER
DEFINITIONS
ECU
2.1.3
DIFFERENTIAL INTERNAL
CAPACITANCE, CDIFF
(OF A CAN NODE)
RIN
RIN
CANL
Capacitance seen between CANL and CANH during
the Recessive state, when the CAN node is
disconnected from the bus (see Figure 2-1).
CDIFF
RDIFF
CANH
CIN
CIN
2.1.4
DIFFERENTIAL INTERNAL
RESISTANCE, RDIFF
(OF A CAN NODE)
GROUND
Resistance seen between CANL and CANH during the
Recessive state when the CAN node is disconnected
from the bus (see Figure 2-1).
2014 Microchip Technology Inc.
DS20005284A-page 7
MCP2561/2FD
2.2
Absolute Maximum Ratings†
VDD.............................................................................................................................................................................7.0V
VIO..............................................................................................................................................................................7.0V
DC Voltage at TXD, RXD, STBY and VSS.............................................................................................-0.3V to VIO + 0.3V
DC Voltage at CANH, CANL and SPLIT ......................................................................................................-58V to +58V
Transient Voltage on CANH, CANL (ISO-7637) (See Figure 2-5)............................................................-150V to +100V
Storage temperature ...............................................................................................................................-55°C to +150°C
Operating ambient temperature ..............................................................................................................-40°C to +150°C
Virtual Junction Temperature, TVJ (IEC60747-1) ....................................................................................-40°C to +190°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on CANH and CANL pins for MCP2561FD (IEC 61000-4-2)........................................................±14 kV
ESD protection on CANH and CANL pins for MCP2562FD (IEC 61000-4-2)..........................................................±8 kV
ESD protection on CANH and CANL pins (IEC 801; Human Body Model)..............................................................±8 kV
ESD protection on all other pins (IEC 801; Human Body Model).............................................................................±4 kV
ESD protection on all pins (IEC 801; Machine Model)............................................................................................±300V
ESD protection on all pins (IEC 801; Charge Device Model)..................................................................................±750V
† NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
DS20005284A-page 8
2014 Microchip Technology Inc.
MCP2561/2FD
2.3
DC Characteristics
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60, CL = 100 pF; unless otherwise specified.
Characteristic
Sym
Min
Typ
Max
Units
Conditions
SUPPLY
VDD Pin
Voltage Range
Supply Current
4.5
—
5.5
VDD
IDD
—
—
5
45
5
10
70
15
15
4.3
Recessive; VTXD = VDD
Dominant; VTXD = 0V
MCP2561FD
mA
µA
Standby Current
—
IDDS
—
5
MCP2562FD; Includes IIO
High Level of the POR
Comparator
3.8
—
VPORH
VPORL
VPORD
V
V
V
Low Level of the POR
Comparator
3.4
0.3
—
—
4.0
0.8
Hysteresis of POR
Comparator
VIO Pin
Digital Supply Voltage Range
1.8
—
5.5
VIO
IIO
V
Supply Current on VIO
—
—
—
4
30
500
1
Recessive; VTXD = VIO
Dominant; VTXD = 0V
(Note 1)
µA
85
0.3
Standby Current
IDDS
µA
V
Undervoltage detection on VIO
—
1.2
—
(Note 1)
VUVD(IO)
BUS LINE (CANH; CANL) TRANSMITTER
CANH; CANL:
Recessive Bus Output Voltage
2.0
0.5VDD
0.0
3.0
VTXD = VDD; No load
VO(R)
V
V
CANH; CANL:
Bus Output Voltage in Standby
-0.1
+0.1
STBY = VTXD = VDD; No load
VO(S)
Recessive Output Current
IO(R)
-5
—
+5
mA -24V < VCAN < +24V
CANH: Dominant
Output Voltage
2.75
3.50
4.50
TXD = 0; RL = 50 to 65
VO(D)
V
CANL: Dominant
Output Voltage
0.50
-400
1.50
0
2.25
RL = 50 to 65
Symmetry of Dominant
Output Voltage
(VDD – VCANH – VCANL)
+400
mV
V
VTXD = VSS (Note 1)
VO(D)(M)
VO(DIFF)
Dominant: Differential
Output Voltage
1.5
2.0
0
3.0
12
50
VTXD = VSS; RL = 50 to 65
Figure 2-2, Figure 2-4
Recessive:
Differential Output Voltage
-120
-500
mV VTXD = VDD
Figure 2-2, Figure 2-4
0
mV VTXD = VDD no load.
,
Figure 2-2, Figure 2-4
Note 1: Characterized; not 100% tested.
2: Only MCP2562FD has VIO pin. For the MCP2561FD, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.
2014 Microchip Technology Inc.
DS20005284A-page 9
MCP2561/2FD
2.3
DC Characteristics (Continued)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60, CL = 100 pF; unless otherwise specified.
Characteristic
Sym
Min
Typ
Max
Units
Conditions
CANH: Short Circuit
Output Current
IO(SC)
-120
85
—
mA VTXD = VSS; VCANH = 0V;
CANL: floating
-100
—
—
75
—
—
mA same as above, but
VDD=5V, TAMB = 25°C (Note 1)
CANL: Short Circuit
Output Current
+120
+100
mA VTXD = VSS; VCANL = 18V;
CANH: floating
—
mA same as above, but
VDD=5V, TAMB = 25°C (Note 1)
BUS LINE (CANH; CANL) RECEIVER
Recessive Differential
Input Voltage
VDIFF(R)(I)
-1.0
-1.0
0.9
1.0
0.5
0.4
—
—
—
—
0.7
—
+0.5
+0.4
VDD
VDD
0.9
V
V
V
Normal Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Dominant Differential
Input Voltage
VDIFF(D)(I)
VTH(DIFF)
Normal Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Differential
Receiver Threshold
Normal Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
1.15
Standby Mode;
-12V < V(CANH, CANL) < +12V;
See Figure 2-6 (Note 3)
Differential
Input Hysteresis
VHYS(DIFF)
RIN
50
10
-1
—
—
0
200
30
mV Normal mode, see Figure 2-6,
(Note 1)
Common Mode
Input Resistance
k (Note 1)
Common Mode
Resistance Matching
RIN(M)
RIN(DIFF)
CIN(CM)
CIN(DIFF)
ILI
+1
%
VCANH = VCANL, (Note 1)
Differential Input
Resistance
10
—
—
-5
—
—
—
—
100
20
k (Note 1)
Common Mode
Input Capacitance
pF VTXD = VDD; (Note 1)
VTXD = VDD; (Note 1)
Differential
Input Capacitance
10
CANH, CANL:
Input Leakage
+5
µA VDD = VTXD = VSTBY = 0V.
For MCP2562FD, VIO = 0V.
VCANH = VCANL = 5 V.
Note 1: Characterized; not 100% tested.
2: Only MCP2562FD has VIO pin. For the MCP2561FD, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.
DS20005284A-page 10
2014 Microchip Technology Inc.
MCP2561/2FD
2.3
DC Characteristics (Continued)
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60, CL = 100 pF; unless otherwise specified.
Characteristic
Sym
Min
Typ
Max
Units
Conditions
COMMON MODE STABILIZATION OUTPUT (SPLIT)
Output Voltage
Vo
IL
0.3VDD 0.5VDD 0.7VDD
0.45VDD 0.5VDD 0.55VDD
V
V
Normal mode;
ISPLIT = -500 µA to +500 µA
Normal mode; RL 1 M
Leakage Current
-5
—
+5
µA Standby mode;
VSPLIT = -24V to + 24V
(ISO 11898: -12V ~ +12V)
DIGITAL INPUT PINS (TXD, STBY)
High-Level Input Voltage
VIH
VIL
0.7VIO
-0.3
-1
—
—
VIO + 0.3
0.3VIO
+1
V
Low-Level Input Voltage
V
High-Level Input Current
IIH
—
µA
µA
µA
TXD: Low-Level Input Current
STBY: Low-Level Input Current
IIL(TXD)
IIL(STBY)
-270
-30
-150
—
-30
-1
RECEIVE DATA (RXD) OUTPUT
High-Level Output Voltage
VOH
VDD - 0.4
VIO - 0.4
—
—
—
—
—
—
V
IOH = -2 mA (MCP2561FD);
typical -4 mA
IOH = -1 mA (MCP2562FD);
typical -2 mA
Low-Level Output Voltage
VOL
0.4
V
IOL = 4 mA; typical 8 mA
THERMAL SHUTDOWN
Shutdown
Junction Temperature
TJ(SD)
165
20
175
—
185
30
°C -12V < V(CANH, CANL) < +12V,
(Note 1)
Shutdown
Temperature Hysteresis
TJ(HYST)
°C -12V < V(CANH, CANL) < +12V,
(Note 1)
Note 1: Characterized; not 100% tested.
2: Only MCP2562FD has VIO pin. For the MCP2561FD, VIO is internally connected to VDD.
3: -12V to 12V is ensured by characterization, tested from -2V to 7V.
2014 Microchip Technology Inc.
DS20005284A-page 11
MCP2561/2FD
FIGURE 2-2:
PHYSICAL BIT REPRESENTATION AND SIMPLIFIED BIAS IMPLEMENTATION
Normal Mode
CANH
Standby Mode
SPLIT
SPLIT
floating
CANL
Recessive
Dominant
Recessive
Time
V
DD
CANH
Normal
VDD/2
R
XD
Standby
Mode
CANL
DS20005284A-page 12
2014 Microchip Technology Inc.
MCP2561/2FD
2.4
AC Characteristics
Electrical Characteristics: Extended (E): TAMB = -40°C to +125°C and High (H): TAMB = -40°C to +150°C;
VDD = 4.5V to 5.5V, VIO = 1.8V to 5.5V (Note 2), RL = 60CL = 100 pF; unless otherwise specified.
Param.
No.
Sym
Characteristic
Min Typ
Max Units
Conditions
1
2
3
4
5
6
7
tBIT
fBIT
Bit Time
Bit Frequency
0.2
14.4
—
—
—
69.44
µs
5000 kHz
tTXD-BUSON Delay TXD Low to Bus Dominant
tTXD-BUSOFF Delay TXD High to Bus Recessive
tBUSON-RXD Delay Bus Dominant to RXD
tBUSOFF-RXD Delay Bus Recessive to RXD
65
90
60
65
90
120
—
—
ns
ns
ns
ns
ns
ns
(Note 1)
—
(Note 1)
(Note 1)
(Note 1)
—
—
—
—
tTXD - RXD
Propagation Delay TXD to RXD
—
120
180
—
RL = 120CL = 200 pF,
(Note 1)
8a
450 485
400 460
550
550
tBIT(TXD) = 500 ns,
see Figure 2-10
tBIT(RXD),2M Recessive bit time on RXD -
2 Mbps, Loop Delay Symmetry
ns
ns
tBIT(TXD) = 500 ns,
see Figure 2-10,
RL = 120CL = 200 pF,
(Note 1)
8b
8c
160 185
220
140
tBIT(TXD) = 200 ns,
see Figure 2-10
tBIT(RXD),5M Recessive bit time on RXD -
5 Mbps, Loop Delay Symmetry
ns
ns
85
105
tBIT(TXD) = 120 ns,
see Figure 2-10
(Note 1)
tBIT(RXD),8M Recessive bit time on RXD -
8 Mbps, Loop Delay Symmetry
9
tFLTR(WAKE) Delay Bus Dominant to RXD
0.5
5
1
4
µs Standby mode
µs Negative edge on STBY
ms TXD = 0V
(Standby mode)
10
tWAKE
Delay Standby
25
40
to Normal Mode
11
12
tPDT
Permanent Dominant Detect Time
Permanent Dominant Timer Reset
—
—
1.25
100
—
—
tPDTR
ns
The shortest Recessive
pulse on TXD or CAN bus
to reset Permanent
Dominant Timer
Note 1: Characterized, not 100% tested.
FIGURE 2-3:
TEST LOAD CONDITIONS
Load Condition 1
Load Condition 2
VDD/2
RL
CL
CL
Pin
Pin
RL = 464
VSS
VSS
CL = 50 pF for all digital pins
2014 Microchip Technology Inc.
DS20005284A-page 13
MCP2561/2FD
FIGURE 2-4:
TEST CIRCUIT FOR ELECTRICAL CHARACTERISTICS
0.1 µF
VDD
CANH
RL
TXD
SPLIT
CAN
Transceiver
CL
RXD
CANL
15 pF
STBY
GND
Note: On MCP2562FD, VIO is connected to VDD.
FIGURE 2-5:
TEST CIRCUIT FOR AUTOMOTIVE TRANSIENTS
500 pF
CANH
TXD
Transient
Generator
CAN
Transceiver
SPLIT
RXD
RL
CANL
500 pF
STBY
GND
Note 1: On MCP2562FD, VIO is connected to VDD.
2: The wave forms of the applied transients shall be in accordance with ISO-7637,
Part 1, test pulses 1, 2, 3a and 3b.
FIGURE 2-6:
HYSTERESIS OF THE RECEIVER
RXD (receive data
output voltage)
VOH
VOL
VDIFF (r)(i)
VDIFF (d)(i)
VDIFF (h)(i)
VDIFF (V)
0.5
0.9
DS20005284A-page 14
2014 Microchip Technology Inc.
MCP2561/2FD
2.5
Timing Diagrams and Specifications
TIMING DIAGRAM FOR AC CHARACTERISTICS
FIGURE 2-7:
VDD
0V
TXD (transmit data
input voltage)
VDIFF (CANH,
CANL differential
voltage)
RXD (receive data
output voltage)
3
5
6
7
4
7
FIGURE 2-8:
TIMING DIAGRAM FOR WAKEUP FROM STANDBY
VSTBY
Input Voltage
VDD
0V
VDD/2
VCANH/VCANL
0
VTXD = VDD
10
FIGURE 2-9:
PERMANENT DOMINANT TIMER RESET DETECT
Minimum pulse width until CAN bus goes to Dominant state after the falling edge.
TXD
VDIFF (VCANH-VCANL)
Driver is off
11
12
2014 Microchip Technology Inc.
DS20005284A-page 15
MCP2561/2FD
FIGURE 2-10:
TIMING DIAGRAM FOR LOOP DELAY SYMMETRY
TXD
5*tBIT(TXD)
tBIT(TXD)
RXD
8
tBIT(RXD)
Note:
The bit time of a recessive bit after five dominant bits is measured on the RXD pin. Due
to asymmetry of the loop delay, and the CAN transceiver not being a push pull driver,
the recessive bits tend to shorten.
2.6
Thermal Specifications
Parameter
Symbol
Min
Typ
Max
Units
Test Conditions
Temperature Ranges
Specified Temperature Range
TA
-40
-40
-40
-65
—
—
—
—
+125
+150
+150
+155
C
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 8L-DFN 3x3
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
TA
TA
C
C
JA
JA
JA
—
—
—
56.7
89.3
—
—
—
C/W
C/W
C/W
149.5
DS20005284A-page 16
2014 Microchip Technology Inc.
MCP2561/2FD
3.0
3.1
PACKAGING INFORMATION
Package Marking Information
8-Lead DFN (3x3 mm)
Example:
Part Number
Code
MCP2561FD-E/MF
MCP2561FDT-E/MF
MCP2561FD-H/MF
MCP2561FDT-H/MF
MCP2562FD-E/MF
MCP2562FDT-E/MF
MCP2562FD-H/MF
MCP2562FDT-H/MF
DADY
DADY
DADZ
DADZ
DAEA
DAEA
DAEB
DAEB
DADY
1307
256
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
YYWW
2561FD
OR
2561FD
E/P ^256
1307
e
3
e
3
H/P ^256
1307
8-Lead SOIC (150 mil)
Example:
OR
2561FDE
2561FDH
e
3
SN 1246
e3
SN 1246
256
256
NNN
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
e
3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2014 Microchip Technology Inc.
DS20005284A-page 17
MCP2561/2FD
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005284A-page 18
2014 Microchip Technology Inc.
MCP2561/2FD
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc.
DS20005284A-page 19
MCP2561/2FD
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005284A-page 20
2014 Microchip Technology Inc.
MCP2561/2FD
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
N
B
E1
NOTE 1
1
2
TOP VIEW
E
A2
A
C
PLANE
L
c
A1
e
eB
8X b1
8X b
.010
C
SIDE VIEW
END VIEW
Microchip Technology Drawing No. C04-018D Sheet 1 of 2
2014 Microchip Technology Inc.
DS20005284A-page 21
MCP2561/2FD
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
ALTERNATE LEAD DESIGN
(VENDOR DEPENDENT)
DATUM A
DATUM A
b
b
e
2
e
2
e
e
Units
Dimension Limits
INCHES
NOM
8
.100 BSC
-
MIN
MAX
Number of Pins
Pitch
N
e
A
Top to Seating Plane
-
.210
.195
-
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
Tip to Seating Plane
Lead Thickness
Upper Lead Width
A2
A1
E
E1
D
L
c
b1
b
eB
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
.130
-
.310
.250
.365
.130
.010
.060
.018
-
.325
.280
.400
.150
.015
.070
.022
.430
Lower Lead Width
Overall Row Spacing
§
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS20005284A-page 22
2014 Microchip Technology Inc.
MCP2561/2FD
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2014 Microchip Technology Inc.
DS20005284A-page 23
MCP2561/2FD
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20005284A-page 24
2014 Microchip Technology Inc.
MCP2561/2FD
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢍꢓꢔꢆꢕꢆꢓꢄꢖꢖꢗꢘꢙꢆꢚꢛꢜꢝꢆꢎꢎꢆꢞꢗꢅꢟꢆꢠꢍꢏꢡꢢꢣ
ꢓꢗꢊꢃꢤ ꢀꢁꢂꢃꢄꢅꢆꢃ!ꢁ"ꢄꢃꢇ#ꢂꢂꢆꢈꢄꢃꢉꢊꢇ$ꢊꢋꢆꢃ%ꢂꢊ&ꢌꢈꢋ"'ꢃꢉꢍꢆꢊ"ꢆꢃ"ꢆꢆꢃꢄꢅꢆꢃꢎꢌꢇꢂꢁꢇꢅꢌꢉꢃ(ꢊꢇ$ꢊꢋꢌꢈꢋꢃꢏꢉꢆꢇꢌ)ꢌꢇꢊꢄꢌꢁꢈꢃꢍꢁꢇꢊꢄꢆ%ꢃꢊꢄꢃ
ꢅꢄꢄꢉ*++&&&ꢐ!ꢌꢇꢂꢁꢇꢅꢌꢉꢐꢇꢁ!+ꢉꢊꢇ$ꢊꢋꢌꢈꢋ
2014 Microchip Technology Inc.
DS20005284A-page 25
MCP2561/2FD
NOTES:
DS20005284A-page 26
2014 Microchip Technology Inc.
MCP2561/2FD
APPENDIX A: REVISION HISTORY
Revision A (March 2014)
Original Release of this Document.
2014 Microchip Technology Inc.
DS20005284A-page 27
MCP2561/2FD
NOTES:
DS20005284A-page 28
2014 Microchip Technology Inc.
MCP2561/2FD
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact the factory or one of the sales offices listed on the back page.
PART NO.
Device
-X
/XX
Examples:
Temperature
Range
Package
a) MCP2561FD-E/MF:Extended Temperature,
8LD 3x3 DFN package.
b) MCP2561FDT-E/MF:Tape and Reel,
Extended Temperature,
Device:
MCP2561FD:High-Speed CAN Transceiver with SPLIT
MCP2561FDT:High-Speed CAN Transceiver with SPLIT
(Tape and Reel) (DFN and SOIC only)
MCP2562FD:High-Speed CAN Transceiver with VIO
MCP2562FDT:High-Speed CAN Transceiver with VIO
(Tape and Reel) (DFN and SOIC only)
8LD 3x3 DFN package.
c) MCP2561FD-E/P: Extended Temperature,
8LD PDIP package.
d) MCP2561FD-E/SN:Extended Temperature,
8LD SOIC package.
e) MCP2561FDT-E/SN:Tape and Reel,
Extended Temperature,
Temperature
Range:
E
H
=
=
-40°C to +125°C (Extended)
-40°C to +150°C (High)
8LD SOIC package.
a) MCP2561FD-H/MF:High Temperature,
8LD 3x3 DFN package.
Package:
MF = Plastic Dual Flat, No Lead Package -
3x3x0.9 mm Body, 8-lead
b) MCP2561FDT-H/MF:Tape and Reel,
High Temperature,
P
= Plastic Dual In-Line - 300 mil Body, 8-lead
8LD 3x3 DFN package.
SN = Plastic Small Outline - Narrow, 3.90 mm Body,
8-lead
c) MCP2561FD-H/P:High Temperature,
8LD PDIP package.
d) MCP2561FD-H/SN:High Temperature,
8LD SOIC package.
e) MCP2561FDT-H/SN:Tape and Reel,
High Temperature,
8LD SOIC package.
2014 Microchip Technology Inc.
DS20005284A-page 29
MCP2561/2FD
NOTES:
DS20005284A-page 30
2014 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICSTART, PIC logo, rfPIC, SST, SST Logo, SuperFlash
and UNI/O are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
32
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MTP, SEEVAL and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Silicon Storage Technology is a registered trademark of
Microchip Technology Inc. in other countries.
Analog-for-the-Digital Age, Application Maestro, BodyCom,
chipKIT, chipKIT logo, CodeGuard, dsPICDEM,
dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPF, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, SQI, Serial Quad I/O,
Total Endurance, TSHARC, UniWinDriver, WiperLock, ZENA
and Z-Scale are trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
GestIC and ULPP are registered trademarks of Microchip
Technology Germany II GmbH & Co. KG, a subsidiary of
Microchip Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2014, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-63276-020-3
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
== ISO/TS 16949 ==
2014 Microchip Technology Inc.
DS20005284A-page 31
Worldwide Sales and Service
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Technical Support:
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Fax: 44-118-921-5820
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Tel: 886-3-5778-366
Fax: 886-3-5770-955
Houston, TX
Tel: 281-894-5983
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Taiwan - Kaohsiung
Tel: 886-7-213-7830
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Los Angeles
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Canada - Toronto
Tel: 905-673-0699
Fax: 905-673-6509
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/25/14
DS20005284A-page 32
2014 Microchip Technology Inc.
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