MCP3201T-CI/ST_技术文档

MCP3201

2.7V 12-Bit A/D Converter with SPI Serial Interface

Features

Description

• 12-bit resolution

The Microchip Technology Inc. MCP3201 device is a

successive approximation 12-bit Analog-to-Digital

(A/D) Converter with on-board sample and hold

circuitry. The device provides a single pseudo-differen-

tial input. Differential Nonlinearity (DNL) is specified at

±1 LSB, and Integral Nonlinearity (INL) is offered in

±1 LSB (MCP3201-B) and ±2 LSB (MCP3201-C)

versions. Communication with the device is done using

a simple serial interface compatible with the SPI

protocol. The device is capable of sample rates of up to

100 ksps at a clock rate of 1.6 MHz. The MCP3201

device operates over a broad voltage range (2.7V -

5.5V). Low-current design permits operation with

typical standby and active currents of only 500 nA and

300 µA, respectively. The device is offered in 8-pin

MSOP, PDIP, TSSOP and 150 mil SOIC packages.

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3201-B)

• ±2 LSB max INL (MCP3201-C)

• On-chip sample and hold

• SPI serial interface (modes 0,0 and 1,1)

• Single supply operation: 2.7V - 5.5V

• 100 ksps maximum sampling rate at V_DD= 5V

• 50 ksps maximum sampling rate at V_DD= 2.7V

• Low power CMOS technology

• 500 nA typical standby current, 2 µA maximum

• 400 µA maximum active current at 5V

• Industrial temp range: -40°C to +85°C

• 8-pin MSOP, PDIP, SOIC and TSSOP packages

Package Types

Applications

• Sensor Interface

MSOP, PDIP, SOIC, TSSOP

• Process Control

• Data Acquisition

V_REF

1

8

V_DD

• Battery Operated Systems

IN+

IN–

V_SS

2

3

4

7

6

5

CLK

Functional Block Diagram

D_OUT

CS/SHDN

V

SS

DD

V

REF

DAC

Comparator

12-Bit SAR

IN+

IN-

Sample

and

Hold

Shift

Register

Control Logic

CS/SHDN CLK

D

OUT

DS21290E-page 1

MCP3201

NOTES:

DS21290E-page 2

MCP3201

†Notice: Stresses above those listed under “Maximum

ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

1.1

ELECTRICAL

CHARACTERISTICS

Maximum Ratings†

V_DD...................................................................................7.0V

All inputs and outputs w.r.t. V_SS................ -0.6V to V_DD+0.6V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied................-65°C to +125°C

ESD protection on all pins (HBM) .................................> 4 kV

ELECTRICAL CHARACTERISTICS

Electrical Specifications: All parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V, T_A= -40°C to +85°C, f_SAMPLE= 100 ksps, and

fCLK = 16*f_SAMPLE, unless otherwise noted.

Parameter

Conversion Rate:

Sym

Min

Typ

Max

Units

Conditions

Conversion Time

t_CONV

—

1.5

—

12

clock

cycles

Analog Input Sample Time

Throughput Rate

t_SAMPLE

f_SAMPLE

clock

cycles

—

100

50

ksps

V_DD= V_REF= 5V

_DD= V_REF= 2.7V

V

DC Accuracy:

Resolution

12

bits

Integral Nonlinearity

INL

—

±0.75

±1

±2

LSB

MCP3201-B

MCP3201-C

Differential Nonlinearity

DNL

—

±0.5

±1

LSB

No missing codes over

temperature

Offset Error

—

±1.25

±3

±5

LSB

Gain Error

Dynamic Performance:

Total Harmonic Distortion

THD

—

-82

72

—

dB

VIN = 0.1V to 4.9V@1 kHz

Signal to Noise and Distortion

(SINAD)

SINAD

Spurious Free Dynamic Range

Reference Input:

Voltage Range

SFDR

—

86

—

dB

VIN = 0.1V to 4.9V@1 kHz

0.25

V_DD

V

Note 2

Current Drain

—

100

.001

150

3

µA

CS = V_DD= 5V

Analog Inputs:

Input Voltage Range (IN+)

Input Voltage Range (IN-)

Leakage Current

IN+

IN-

V_SS-100

—

V_REF+IN-

V

mV

µA

W

V_SS+100

0.001

1K

±1

—

Switch Resistance

R_SS

—

See Figure 4-1

Sample Capacitor

C_SAMPLE

—

20

pF

Digital Input/Output:

Data Coding Format

High Level Input Voltage

Low Level Input Voltage

Straight Binary

V_IH

V_IL

0.7 V_DD

—

V

0.3 V_DD

Note 1: This parameter is established by characterization and not 100% tested.

2: See graph that relates linearity performance to V_REFlevel.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

DS21290E-page 3

MCP3201

ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Specifications: All parameters apply at V_DD= 5V, V_SS= 0V, V_REF= 5V, T_A= -40°C to +85°C, f_SAMPLE= 100 ksps, and

fCLK = 16*f_SAMPLE, unless otherwise noted.

Parameter

Sym

Min

Typ

Max

Units

Conditions

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

V_OH

V_OL

4.1

—

0.4

10

V

I_OH= -1 mA, V_DD= 4.5V

I_OL= 1 mA, V_DD= 4.5V

V_IN= V_SSor V_DD

V

I_LI

-10

—

µA

pF

I_LO

V_OUT= V_SSor V_DD

Pin Capacitance

C_IN, C_OUT

V_DD= 5.0V (Note 1)

(all inputs/outputs)

T_A= +25°C, f = 1 MHz

Timing Parameters:

Clock Frequency

f_CLK

—

1.6

0.8

MHz

V_DD= 5V (Note 3)

V

_DD= 2.7V (Note 3)

Clock High Time

t_HI

t_LO

t_SUCS

t_DO

312

100

—

ns

Clock Low Time

CS Fall To First Rising CLK Edge

CLK Fall To Output Data Valid

CLK Fall To Output Enable

CS Rise To Output Disable

—

200

100

See Test Circuits, Figure 1-2

t_EN

—

t_DIS

—

See Test Circuits, Figure 1-2

(Note 1)

CS Disable Time

D_OUTRise Time

t_CSH

t_R

625

—

ns

100

See Test Circuits, Figure 1-2

(Note 1)

D_OUTFall Time

t_F

—

100

5.5

ns

V

See Test Circuits, Figure 1-2

(Note 1)

Power Requirements:

Operating Voltage

Operating Current

V_DD

I_DD

2.7

—

300

210

400

—

µA

V_DD= 5.0V, D_OUTunloaded

V

_DD= 2.7V, D_OUTunloaded

Standby Current

I_DDS

—

0.5

2

µA

CS = V_DD= 5.0V

Note 1: This parameter is established by characterization and not 100% tested.

2: See graph that relates linearity performance to V_REFlevel.

3: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance,

especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information.

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 8L-TSSOP

T_A

-40

-65

—

+85

°C

+150

θ_JA

—

211

89.5

149.5

139

—

°C/W

DS21290E-page 4

MCP3201

t_CSH

CS

t_SUCS

t_HI

t_LO

CLK

t_EN

t_DO

t_DIS

t_R

t_F

HI-Z

LSB

D_OUT

MSB OUT

NULL BIT

FIGURE 1-1:

Serial Timing.

Load circuit for t_DISand t_EN

Load circuit for t_R, t_F, t_DO

1.4V

Test Point

V_DD

t_DISWaveform 2

3 kΩ

Test Point

V_DD/2

3 kΩ

D_OUT

t_ENWaveform

D_OUT

30 pF

t

_DISWaveform 1

C_L= 30 pF

V_SS

Voltage Waveforms for t_R, t_F

Voltage Waveforms for t_EN

V_OH

V_OL

D_OUT

CS

t_F

t_R

1

2

3

4

CLK

B9

D_OUT

t_EN

Voltage Waveforms for t_DO

Voltage Waveforms for t_DIS

V_IH

CS

D_OUT

CLK

90%

t_DO

Waveform 1*

t_DIS

D_OUT

10%

D_OUT

Waveform 2†

* Waveform 1 is for an output with internal condi-

tions such that the output is high, unless disabled

by the output control.

† Waveform 2 is for an output with internal condi-

tions such that the output is low, unless disabled

by the output control.

FIGURE 1-2:

Test Circuits.

DS21290E-page 5

MCP3201

NOTES:

DS21290E-page 6

MCP3201

2.0

TYPICAL PERFORMANCE CHARACTERISTICS

Note: The graphs provided following this note are a statistical summary based on a limited number of samples

and are provided for informational purposes only. The performance characteristics listed herein are not

tested or guaranteed. In some graphs, the data presented may be outside the specified operating range

(e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

1.0

0.8

0.6

0.4

0.2

2.0

1.5

V_DD= V_REF= 2.7V

Positive INL

Negative INL

1.0

Positive INL

0.5

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

Negative INL

0

25

50

75

100

125

150

0

20

40

60

80

100

Sample Rate (ksps)

FIGURE 2-1:

Integral Nonlinearity (INL)

FIGURE 2-4:

Integral Nonlinearity (INL)

vs. Sample Rate.

vs. Sample Rate (V = 2.7V).

DD

2.0

1.5

2.0

1.5

V_DD= 2.7V

F_SAMPLE= 50 ksps

1.0

0.5

Positive INL

1.0

Positive INL

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-0.5

-1.0

-1.5

-2.0

Negative INL

0

1

2

3

4

5

0.0

0.5

1.0

1.5

2.0

2.5

3.0

V_REF(V)

FIGURE 2-2:

Integral Nonlinearity (INL)

FIGURE 2-5:

Integral Nonlinearity (INL)

vs. V

(V = 2.7V).

REF.

REF

DD

1.0

0.8

1.0

0.8

0.6

0.4

0.2

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512 1024 1536 2048 2560 3072 3584 4096

0

512 1024 1536 2048 2560 3072 3584 4096

Digital Code

FIGURE 2-3:

Integral Nonlinearity (INL)

FIGURE 2-6:

Integral Nonlinearity (INL)

vs. Code (Representative Part).

vs. Code (Representative Part, V = 2.7V).

DD

DS21290E-page 7

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

1.0

0.8

1.0

0.8

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

Positive INL

0.6

0.4

0.2

0.0

Negative INL

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

Negative INL

25

-50

-25

0

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-7:

Integral Nonlinearity (INL)

FIGURE 2-10:

Integral Nonlinearity (INL)

vs. Temperature.

vs. Temperature (V = 2.7V).

DD

1.0

0.8

0.6

2.0

V_DD= V_REF= 2.7V

1.5

1.0

0.4

0.2

Positive DNL

0.5

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.5

-1.0

-1.5

-2.0

Negative DNL

0

25

50

75

100

125

150

0

20

40

60

80

100

Sample Rate (ksps)

FIGURE 2-8:

Differential Nonlinearity

FIGURE 2-11:

Differential Nonlinearity

(DNL) vs. Sample Rate.

(DNL) vs. Sample Rate (V = 2.7V).

DD

3.0

2.0

3.0

V_DD= 2.7V

F_SAMPLE= 50 ksps

2.0

1.0

Positive DNL

1.0

0.0

Positive DNL

Negative DNL

0.0

-1.0

-2.0

-3.0

Negative DNL

-1.0

-2.0

0.0

0.5

1.0

1.5

2.0

2.5

3.0

0

1

2

3

4

5

V_REF(V)

FIGURE 2-9:

(DNL) vs. V

Differential Nonlinearity

FIGURE 2-12:

(DNL) vs. V

Differential Nonlinearity

(V = 2.7V).

.

REF

DD

DS21290E-page 8

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

1.0

0.8

0.6

V_DD= V_REF= 2.7V

0.8

0.6

F_SAMPLE= 50 ksps

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

512 1024 1536 2048 2560 3072 3584 4096

Digital Code

0

512 1024 1536 2048 2560 3072 3584 4096

Digital Code

FIGURE 2-13:

Differential Nonlinearity

FIGURE 2-16:

Differential Nonlinearity

(DNL) vs. Code (Representative Part).

(DNL) vs. Code (Representative Part,

V

= 2.7V).

DD

1.0

0.8

0.6

V_DD= 2.7V

_SAMPLE= 50ksps

0.8

0.6

F

Positive DNL

Negative DNL

0.4

0.2

Positive DNL

Negative DNL

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

-0.2

-0.4

-0.6

-0.8

-1.0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-14:

Differential Nonlinearity

FIGURE 2-17:

Differential Nonlinearity

(DNL) vs. Temperature.

(DNL) vs. Temperature (V = 2.7V).

DD

20

18

5

4

16

14

12

10

8

V_DD= 5V

_SAMPLE= 100 ksps

V_DD= 2.7V

3

F

F_SAMPLE= 50 ksps

2

1

V_DD= 2.7V

F_SAMPLE= 50ksps

6

0

V_DD= 5V

_SAMPLE= 100 ksps

4

-1

-2

F

2

0

1

2

3

4

5

0

1

2

3

4

5

V_REF(V)

FIGURE 2-15:

Gain Error vs. V

.

FIGURE 2-18:

Offset Error vs. V

.

REF

DS21290E-page 9

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

1.0

0.8

0.6

0.4

0.2

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

V_DD= V_REF= 5V

_SAMPLE= 100 ksps

F

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-19:

Gain Error vs. Temperature.

FIGURE 2-22:

Offset Error vs.

Temperature.

100

90

80

70

60

50

40

30

20

10

0

100

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5V

_SAMPLE= 100 ksps

V_DD= V_REF= 5V

F

F_SAMPLE= 100 ksps

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F_SAMPLE= 50 ksps

F

1

10

Input Frequency (kHz)

100

1

10

100

Input Frequency (kHz)

FIGURE 2-20:

Signal-to-Noise Ratio (SNR)

FIGURE 2-23:

Signal-to-Noise and

vs. Input Frequency.

Distortion (SINAD) vs. Input Frequency.

0

-10

-20

-30

80

V_DD= V_REF= 5V

_SAMPLE= 100 ksps

70

F

60

50

40

30

20

10

0

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

-40

-50

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

-60

-70

-80

V_DD= V_REF= 5V, F_SAMPLE= 100 ksps

-90

-100

-40

-35

-30

-25

-20

-15

-10

-5

0

1

10

100

Input Signal Level (dB)

Input Frequency (kHz)

FIGURE 2-21:

Total Harmonic Distortion

FIGURE 2-24:

Signal-to-Noise and

(THD) vs. Input Frequency.

Distortion (SINAD) vs. Input Signal Level.

DS21290E-page 10

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

12.0

12.00

11.75

11.50

11.25

11.00

10.75

10.50

10.25

10.00

9.75

V_DD= 5V

11.5

11.0

10.5

10.0

9.5

F_SAMPLE= 100 ksps

V_DD= V_REF= 5V

F_SAMPLE=100 ksps

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

9.0

V_DD= 2.7V

9.50

9.25

8.5

F_SAMPLE= 50 ksps

9.00

8.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

1

10

100

V_REF(V)

Input Frequency (kHz)

FIGURE 2-25:

Effective Number of Bits

FIGURE 2-28:

Effective Number of Bits

(ENOB) vs. V

.

(ENOB) vs. Input Frequency.

REF

0

-10

-20

-30

-40

-50

-60

-70

-80

100

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5V, F_SAMPLE= 100 ksps

V_DD= V_REF= 2.7V

_SAMPLE= 50 ksps

F

1

10

100

1000

10000

1

10

Input Frequency (kHz)

100

Ripple Frequency (kHz)

FIGURE 2-26:

Spurious Free Dynamic

FIGURE 2-29:

Power Supply Rejection

Range (SFDR) vs. Input Frequency.

(PSR) vs. Ripple Frequency.

0

-10

-20

-30

-40

0

-10

-20

-30

-40

V_DD= V_REF= 2.7V

F_SAMPLE= 50 ksps

F_INPUT= 998.76 Hz

4096 points

V_DD= V_REF= 5V

F_SAMPLE= 100 ksps

F_INPUT= 9.985kHz

4096 points

-50

-60

-70

-80

-90

-100

-110

-120

-130

-100

-110

-120

-130

0

10000

20000

30000

40000

50000

0

5000

10000

15000

20000

25000

Frequency (Hz)

FIGURE 2-27:

Frequency Spectrum of

FIGURE 2-30:

Frequency Spectrum of

10 kHz input (Representative Part).

1 kHz input (Representative Part, V = 2.7V).

DD

DS21290E-page 11

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

500

450

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

0

V_REF= V_DD

All points at F_CLK= 1.6 MHz, except

at V_REF= V_DD= 2.5V, F_CLK= 800 kHz

V_REF= V_DD

All points at F_CLK= 1.6 MHz, except

at V_REF= V_DD= 2.5V, F_CLK= 800 kHz

0

2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

V_DD(V)

2.0

2.5

3.0

3.5

4.0

V_DD(V)

4.5

5.0

5.5

6.0

FIGURE 2-31:

I

vs. V

.

FIGURE 2-34:

I

vs. V

.

DD

REF

100

90

80

70

60

50

40

30

20

400

350

300

250

200

150

100

50

V_DD= V_REF= 5V

V_DD= V_REF= 2.7V

10

0

10

100

1000

10000

10

100

1000

10000

Clock Frequency (kHz)

FIGURE 2-32:

I

vs. Clock Frequency.

FIGURE 2-35:

I

vs. Clock Frequency.

DD

REF

400

100

90

80

70

60

50

40

30

20

10

0

V_DD= V_REF= 5V

_CLK= 1.6 MHz

350

300

250

200

150

100

50

F_CLK= 1.6 MHz

F

V_DD= V_REF= 2.7V

_CLK= 800 kHz

F

V_DD= V_REF= 2.7V

_CLK= 800 kHz

F

0

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-33:

I

vs. Temperature.

FIGURE 2-36:

I

vs. Temperature.

DD

REF

DS21290E-page 12

MCP3201

Note: Unless otherwise indicated, V_DD= V_REF= 5V, V_SS= 0V, f_SAMPLE= 100 ksps, f_CLK= 16*f_SAMPLE, T_A= +25°C.

80

70

60

50

40

30

20

10

0

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

V_REF= CS = V_DD

V_DD= V_REF= 5V

F_CLK= 1.6 MHz

2.0

2.5

3.0

3.5

4.0

4.5

5.0

5.5

6.0

-50

-25

0

25

50

75

100

V_DD(V)

Temperature (°C)

FIGURE 2-37:

I

vs. V

.

FIGURE 2-39:

Analog Input Leakage

DDS

DD

Current vs. Temperature.

100.00

V_DD= V_REF= CS = 5V

10.00

1.00

0.10

0.01

-50

-25

0

25

50

75

100

Temperature (°C)

FIGURE 2-38:

I

vs. Temperature.

DDS

DS21290E-page 13

MCP3201

NOTES:

DS21290E-page 14

MCP3201

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follows.

TABLE 3-1:

PIN FUNCTION TABLE

MCP3201

Symbol

Description

MSOP, PDIP, SOIC,

TSSOP

1

2

3

4

5

6

7

8

V_REF

IN+

Reference Voltage Input

Positive Analog Input

Negative Analog Input

Ground

IN-

V_SS

CS/SHDN

D_OUT

CLK

Chip Select/Shutdown Input

Serial Data Out

Serial Clock

V_DD

+2.7V to 5.5V Power Supply

3.1

Positive Analog Input (IN+)

3.4

Serial Clock (CLK)

Positive analog input. This input can vary from IN- to

V_REF+ IN-.

The SPI clock pin is used to initiate a conversion and to

clock out each bit of the conversion as it takes place.

See Section 6.2 “Maintaining Minimum Clock

Speed” for constraints on clock speed.

3.2

Negative Analog Input (IN-)

Negative analog input. This input can vary ±100 mV

3.5

Serial Data Output (D_OUT)

from V_SS

.

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place.

3.3

Chip Select/Shutdown (CS/SHDN)

The CS/SHDN pin is used to initiate communication

with the device when pulled low and will end a

conversion and put the device in low power standby

when pulled high. The CS/SHDN pin must be pulled

high between conversions.

DS21290E-page 15

MCP3201

NOTES:

DS21290E-page 16

MCP3201

4.2

Reference Input

4.0

DEVICE OPERATION

The reference input (V_REF) determines the analog input

voltage range and the LSB size, as shown below.

The MCP3201 A/D Converter employs a conventional

SAR architecture. With this architecture, a sample is

acquired on an internal sample/hold capacitor for

1.5 clock cycles starting on the first rising edge of the

serial clock after CS has been pulled low. Following this

sample time, the input switch of the converter opens

and the device uses the collected charge on the

internal sample and hold capacitor to produce a serial

12-bit digital output code. Conversion rates of 100 ksps

are possible on the MCP3201 device. See Section 6.2

“Maintaining Minimum Clock Speed” for information

on minimum clock rates. Communication with the

device is done using a 3-wire SPI-compatible interface.

EQUATION 4-1:

V_REF

LSB Size = ------------

4096

As the reference input is reduced, the LSB size is

reduced accordingly. The theoretical digital output code

produced by the A/D Converter is a function of the

analog input signal and the reference input as shown

below.

EQUATION 4-2:

4.1

Analog Inputs

4096*V_IN

Digital Output Code = ------------------------

V_REF

The MCP3201 device provides a single pseudo-differ-

ential input. The IN+ input can range from IN- to V_REF

(V_REF+ IN-). The IN- input is limited to ±100 mV from

the V_SSrail. The IN- input can be used to cancel small

signal common-mode noise which is present on both

the IN+ and IN- inputs.

Where:

V_IN

=

Analog Input Voltage = V(_IN+) - V(_IN-)

Reference Voltage

V_REF

For the A/D Converter to meet specification, the charge

holding capacitor (C_SAMPLE) must be given enough

time to acquire a 12-bit accurate voltage level during

the 1.5 clock cycle sampling period. The analog input

model is shown in Figure 4-1.

When using an external voltage reference device, the

system designer should always refer to the

manufacturer’s recommendations for circuit layout.

Any instability in the operation of the reference device

will have a direct effect on the operation of the

A/D Converter.

In this diagram, it is shown that the source impedance

(R_S) adds to the internal sampling switch (R_SS

)

impedance, directly affecting the time that is required to

charge the capacitor (C_SAMPLE). Consequently, a

larger source impedance increases the offset, gain,

and integral linearity errors of the conversion.

Ideally, the impedance of the signal source should be

near zero. This is achievable with an operational

amplifier such as the MCP601, which has a closed loop

output impedance of tens of ohms. The adverse affects

of higher source impedances are shown in Figure 4-2.

If the voltage level of IN+ is equal to or less than IN-, the

resultant code will be 000h. If the voltage at IN+ is equal

to or greater than {[V_REF+ (IN-)] - 1 LSB}, then the

output code will be FFFh. If the voltage level at IN- is

more than 1 LSB below V_SS, then the voltage level at

the IN+ input will have to go below V_SSto see the 000h

output code. Conversely, if IN- is more than 1 LSB

above V_SS, then the FFFh code will not be seen unless

the IN+ input level goes above V_REFlevel.

DS21290E-page 17

MCP3201

V_DD

Sampling

Switch

V_T= 0.6V

R_S= 1 kΩ

CHx

R_SS

SS

C_SAMPLE

= DAC capacitance

= 20 pF

C_PIN

7 pF

I_LEAKAGE

±1 nA

VA

V_SS

LEGEND

VA

R_SS

CHx

=

Signal Source

Source Impedance

Input Channel Pad

C_PIN

V_T

I_LEAKAGE

Input Pin Capacitance

Threshold Voltage

Leakage Current At The Pin

Due To Various Junctions

Sampling Switch

SS

R_S

C_SAMPLE

=

Sampling Switch Resistor

Sample/hold Capacitance

FIGURE 4-1:

Analog Input Model.

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

V_DD= V_REF= 5V

V_DD= V_REF= 2.7V

0.0

100

1000

10000

Input Resistance (Ohms)

FIGURE 4-2:

Maximum Clock Frequency

vs. Input Resistance (R ) to maintain less than a

S

0.1 LSB deviation in INL from nominal

conditions.

DS21290E-page 18

MCP3201

5.0

SERIAL COMMUNICATIONS

Communication with the device is done using a

standard SPI-compatible serial interface. Initiating

communication with the MCP3201 device begins with

the CS going low. If the device was powered up with the

CS pin low, it must be brought high and back low to

initiate communication. The device will begin to sample

the analog input on the first rising edge after CS goes

low. The sample period will end in the falling edge of the

second clock, at which time the device will output a low

null bit. The next 12 clocks will output the result of the

conversion with MSB first, as shown in Figure 5-1. Data

is always output from the device on the falling edge of

the clock. If all 12 data bits have been transmitted and

the device continues to receive clocks while the CS is

held low, the device will output the conversion result

LSB first, as shown in Figure 5-2. If more clocks are

provided to the device while CS is still low (after the

LSB first data has been transmitted), the device will

clock out zeros indefinitely.

t_CYC

T

CSH

CS

POWER

DOWN

T

SUCS

CLK

T

t_DATA**

HI-Z

SAMPLE

t_CONV

HI-Z

NULL

D_OUT

B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0*

B11 B10 B9 B8

BIT

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed

by zeros indefinitely. See Figure 5-2 below.

** t

: during this time, the bias current and the comparator power down and the reference input becomes a high-impedance

DATA

node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-1:

Communication with MCP3201 device using MSB first Format.

t_CYC

t_CSH

CS

t_SUCS

POWER DOWN

CLK

t_SAMPLE

t_DATA**

B11B10B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10B11*

t_CONV

HI-Z

NULL

BIT

D_OUT

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely.

** t : during this time, the bias current and the comparator power down and the reference input becomes a high-impedance

DATA

node, leaving the CLK running to clock out the LSB-first data or zeros.

FIGURE 5-2:

Communication with MCP3201 device using LSB first Format.

DS21290E-page 19

MCP3201

NOTES:

DS21290E-page 20

MCP3201

been sent to the device, the microcontroller’s receive

buffer will contain two unknown bits (the output is at

high-impedance for the first two clocks), the null bit and

the highest order five bits of the conversion. After the

second eight clocks have been sent to the device, the

MCU receive register will contain the lowest-order

seven bits and the B1 bit repeated as the A/D

Converter has begun to shift out LSB first data with the

extra clock. Typical procedure would then call for the

lower-order byte of data to be shifted right by one bit to

remove the extra B1 bit. The B7 bit is then transferred

from the high-order byte to the lower-order byte, and

then the higher-order byte is shifted one bit to the right

as well. Easier manipulation of the converted data can

be obtained by using this method.

6.0

6.1

APPLICATIONS INFORMATION

Using the MCP3201 Device with

Microcontroller SPI Ports

With most microcontroller SPI ports, it is required to

clock out eight bits at a time. If this is the case, it will be

necessary to provide more clocks than are required for

the MCP3201. As an example, Figure 6-1 and

Figure 6-2 show how the MCP3201 device can be

interfaced to a microcontroller with a standard SPI port.

Since the MCP3201 always clocks data out on the

falling edge of clock, the MCU SPI port must be

configured to match this operation. SPI Mode 0,0

(clock idles low) and SPI Mode 1,1 (clock idles high)

are both compatible with the MCP3201. Figure 6-1

depicts the operation shown in SPI Mode 0,0, which

requires that the CLK from the microcontroller idles in

the ‘low’ state. As shown in the diagram, the MSB is

clocked out of the A/D Converter on the falling edge of

the third clock pulse. After the first eight clocks have

Figure 6-2 shows the same thing in SPI Mode 1,1

which requires that the clock idles in the high state. As

with mode 0,0, the A/D Converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D Converter in on the rising edge of the clock.

CS

MCU latches data from A/D

Converter on rising edges of SCLK

CLK

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

Data is clocked out of A/D

Converter on falling edges

HI-Z

B2

B1

NULL

BIT

B11 B10 B9

B7

B6

B5 B4 B3 B2 B1 B0

B8

D

OUT

LSB first data begins

to come out

?

0

B11 B10 B9 B8 B7

B6 B5 B4 B3 B2 B1 B0 B1

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

FIGURE 6-1:

SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low).

CS

MCU latches data from A/D

Converter on rising edges of SCLK

CLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

Data is clocked out of A/D

Converter on falling edges

HI-Z

NULL

BIT

B11 B10 B9 B8

B7

B6 B5 B4 B3 B2 B1 B0

B1

D

OUT

LSB first data begins

to come out

?

0

B11 B10 B9 B8 B7

B6 B5 B4 B3 B2 B1 B0 B1

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

FIGURE 6-2:

SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high).

DS21290E-page 21

MCP3201

6.2

Maintaining Minimum Clock Speed

V

DD

When the MCP3201 initiates the sample period, charge

is stored on the sample capacitor. When the sample

period is complete, the device converts one bit for each

clock that is received. It is important for the user to note

that a slow clock rate will allow charge to bleed off the

sample cap while the conversion is taking place. At

85°C (worst case condition), the part will maintain

proper charge on the sample capacitor for at least

1.2 ms after the sample period has ended. This means

that the time between the end of the sample period and

the time that all 12 data bits have been clocked out

must not exceed 1.2 ms (effective clock frequency of

10 kHz). Failure to meet this criteria may induce

linearity errors into the conversion outside the rated

specifications. It should be noted that during the entire

conversion cycle, the A/D Converter does not require a

constant clock speed or duty cycle, as long as all timing

specifications are met.

10 µF

4.096V

Reference

10 µF

0.1 µF

MCP1541

C

L

1 µF

V

REF

IN+

MCP3201

C

1

IN-

MCP601

R

1

V

+

-

IN

R

2

C

2

R

4

R

3

FIGURE 6-3:

The MCP601 Operational

Amplifier is used to implement a 2nd order anti-

aliasing filter for the signal being converted by

the MCP3201 device.

6.3

Buffering/Filtering the Analog

Inputs

If the signal source for the A/D Converter is not a low

impedance source, it will have to be buffered

or inaccurate conversion results may occur.

See Figure 4-2. It is also recommended that a filter be

used to eliminate any signals that may be aliased back

into the conversion results. This is illustrated in

Figure 6-3 where an op amp is used to drive the analog

input of the MCP3201 device. This amplifier provides a

low impedance source for the converter input and a

low-pass filter, which eliminates unwanted high-

frequency noise.

Low-pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab^®software. FilterLab

will calculate capacitor and resistor values, as well as

determine the number of poles that are required for the

application. For more information on filtering signals,

see the application note AN699 “Anti-Aliasing Analog

Filters for Data Acquisition Systems.”

DS21290E-page 22

MCP3201

6.4

Layout Considerations

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor should

always be used with this device and should be placed

as close as possible to the device pin. A bypass

capacitor value of 1 µF is recommended.

Digital and analog traces should be separated as much

as possible on the board and no traces should run

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high-

frequency signals (such as clock lines) as far as

possible from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing V_DDconnections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors. See Figure 6-4. For more information on layout

tips when using A/D Converter, refer to AN688 “Layout

Tips for 12-Bit A/D Converter Applications”.

V

DD

Connection

Device 4

Device 1

Device 3

Device 2

FIGURE 6-4:

V

traces arranged in a

DD

‘Star’ configuration in order to reduce errors

caused by current return paths.

DS21290E-page 23

MCP3201

NOTES:

DS21290E-page 24

MCP3201

7.0

7.1

PACKAGING INFORMATION

Package Marking Information

Example:

8-Lead MSOP

XXXXXX

3201CI

820256

YWWNNN

8-Lead PDIP (300 mil)

Example:

3201-B

XXXXXXXX

XXXXXNNN

e

3

I/P ^^256

YYWW

0820

8-Lead SOIC (150 mil)

Example:

XXXXXXXX

3201-BI

XXXXYYWW

SN 0820

e

3

NNN

256

Example:

8-Lead TSSOP

201C

I820

256

XXXX

YYWW

NNN

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21290E-page 25

MCP3201

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DS21290E-page 26

MCP3201

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢝꢓꢄꢈꢆ ꢔꢁꢂꢋꢔꢃꢆꢗꢇꢘꢆMꢆ"##ꢆꢑꢋꢈꢆ$ꢏꢅ%ꢆꢙꢇꢝ ꢇꢚ

ꢛꢏꢊꢃꢜ 1ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ2ꢇꢔꢉꢅ"ꢊꢇ)ꢃꢄꢔ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ2ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ033)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ2ꢇꢔꢃꢄꢔ

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

A1

c

e

eB

b1

b

4ꢄꢃ%

ꢚ6/;*ꢖ

ꢐꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢒꢚ6

67ꢒ

9

ꢁꢀꢓꢓꢅ.ꢖ/

M

ꢁꢀ,ꢓ

M

ꢁ,ꢀꢓ

ꢁꢏ+ꢓ

ꢁ,:+

ꢁꢀ,ꢓ

ꢁꢓꢀꢓ

ꢁꢓ:ꢓ

ꢁꢓꢀ9

M

ꢒꢕ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

ꢘꢌꢑꢅ%ꢌꢅꢖꢉꢇ%ꢃꢄꢔꢅꢂꢈꢇꢄꢉ

ꢒꢌꢈ"ꢉ"ꢅꢂꢇꢍ2ꢇꢔꢉꢅꢘꢎꢃꢍ2ꢄꢉ

.ꢇ ꢉꢅ%ꢌꢅꢖꢉꢇ%ꢃꢄꢔꢅꢂꢈꢇꢄꢉ

ꢖꢎꢌ!ꢈ"ꢉꢊꢅ%ꢌꢅꢖꢎꢌ!ꢈ"ꢉꢊꢅ=ꢃ"%ꢎ

ꢒꢌꢈ"ꢉ"ꢅꢂꢇꢍ2ꢇꢔꢉꢅ=ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢔ%ꢎ

6

ꢉ

ꢕ

ꢕꢏ

ꢕꢀ

*

*ꢀ

ꢐ

5

ꢍ

(ꢀ

(

ꢉ.

M

ꢁꢏꢀꢓ

ꢁꢀꢜ+

M

ꢁꢀꢀ+

ꢁꢓꢀ+

ꢁꢏꢜꢓ

ꢁꢏꢗꢓ

ꢁ,ꢗ9

ꢁꢀꢀ+

ꢁꢓꢓ9

ꢁꢓꢗꢓ

ꢁꢓꢀꢗ

M

ꢁ,ꢏ+

ꢁꢏ9ꢓ

ꢁꢗꢓꢓ

ꢁꢀ+ꢓ

ꢁꢓꢀ+

ꢁꢓꢛꢓ

ꢁꢓꢏꢏ

ꢁꢗ,ꢓ

ꢘꢃꢑꢅ%ꢌꢅꢖꢉꢇ%ꢃꢄꢔꢅꢂꢈꢇꢄꢉ

5ꢉꢇ"ꢅꢘꢎꢃꢍ2ꢄꢉ

4ꢑꢑꢉꢊꢅ5ꢉꢇ"ꢅ=ꢃ"%ꢎ

5ꢌ)ꢉꢊꢅ5ꢉꢇ"ꢅ=ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅꢙꢌ)ꢅꢖꢑꢇꢍꢃꢄꢔꢅꢅꢟ

ꢛꢏꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢟꢅꢖꢃꢔꢄꢃ$ꢃꢍꢇꢄ%ꢅ/ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ

,ꢁ ꢐꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢐꢅꢇꢄ"ꢅ*ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢒꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢁꢓꢀꢓ@ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

ꢗꢁ ꢐꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢔꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢔꢅꢑꢉꢊꢅꢕꢖꢒ*ꢅ-ꢀꢗꢁ+ꢒꢁ

.ꢖ/0ꢅ.ꢇ ꢃꢍꢅꢐꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢘꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢒꢃꢍꢊꢌꢍꢎꢃꢑ ꢘꢉꢍꢎꢄꢌꢈꢌꢔꢋ ꢐꢊꢇ)ꢃꢄꢔ /ꢓꢗꢞꢓꢀ9.

DS21290E-page 27

MCP3201

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢐꢑꢄꢈꢈꢆꢒꢓꢊꢈꢋꢔꢃꢆꢗꢐꢛꢘꢆMꢆꢛꢄꢎꢎꢏ&'ꢆ"()#ꢆꢑꢑꢆ$ꢏꢅ%ꢆꢙꢐꢒ *ꢚ

ꢛꢏꢊꢃꢜ 1ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ2ꢇꢔꢉꢅ"ꢊꢇ)ꢃꢄꢔ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ2ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ033)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ2ꢇꢔꢃꢄꢔ

D

e

N

E

E1

NOTE 1

1

2

3

α

h

b

h

c

φ

A2

A

L

A1

L1

β

4ꢄꢃ%

ꢒꢚ55ꢚꢒ*ꢘ*ꢙꢖ

ꢐꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢒꢚ6

67ꢒ

ꢒꢕ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

6

ꢉ

9

ꢀꢁꢏꢛꢅ.ꢖ/

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢔꢎ%

ꢕ

M

ꢀꢁꢏ+

ꢓꢁꢀꢓ

M

ꢀꢁꢛ+

M

ꢓꢁꢏ+

ꢒꢌꢈ"ꢉ"ꢅꢂꢇꢍ2ꢇꢔꢉꢅꢘꢎꢃꢍ2ꢄꢉ

ꢖ%ꢇꢄ"ꢌ$$ꢅꢅ

ꢕꢏ

ꢕꢀ

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:ꢁꢓꢓꢅ.ꢖ/

ꢒꢌꢈ"ꢉ"ꢅꢂꢇꢍ2ꢇꢔꢉꢅ=ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢔ%ꢎ

/ꢎꢇ&$ꢉꢊꢅAꢌꢑ%ꢃꢌꢄꢇꢈB

1ꢌꢌ%ꢅ5ꢉꢄꢔ%ꢎ

*ꢀ

ꢐ

ꢎ

,ꢁꢜꢓꢅ.ꢖ/

ꢗꢁꢜꢓꢅ.ꢖ/

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ꢓꢁꢗꢓ

M

ꢓꢁ+ꢓ

ꢀꢁꢏꢛ

5

1ꢌꢌ%ꢑꢊꢃꢄ%

1ꢌꢌ%ꢅꢕꢄꢔꢈꢉ

5ꢉꢇ"ꢅꢘꢎꢃꢍ2ꢄꢉ

5ꢉꢇ"ꢅ=ꢃ"%ꢎ

ꢒꢌꢈ"ꢅꢐꢊꢇ$%ꢅꢕꢄꢔꢈꢉꢅꢘꢌꢑ

ꢒꢌꢈ"ꢅꢐꢊꢇ$%ꢅꢕꢄꢔꢈꢉꢅ.ꢌ%%ꢌ&

5ꢀ

ꢀ

ꢀꢁꢓꢗꢅꢙ*1

ꢓꢝ

ꢓꢁꢀꢛ

ꢓꢁ,ꢀ

+ꢝ

M

9ꢝ

ꢍ

(

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ꢓꢁꢏ+

ꢓꢁ+ꢀ

ꢀ+ꢝ

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+ꢝ

ꢀ+ꢝ

ꢛꢏꢊꢃꢉꢜ

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢟꢅꢖꢃꢔꢄꢃ$ꢃꢍꢇꢄ%ꢅ/ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ

,ꢁ ꢐꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢐꢅꢇꢄ"ꢅ*ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢒꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢓꢁꢀ+ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

ꢗꢁ ꢐꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢔꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢔꢅꢑꢉꢊꢅꢕꢖꢒ*ꢅ-ꢀꢗꢁ+ꢒꢁ

.ꢖ/0 .ꢇ ꢃꢍꢅꢐꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢘꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢙ*10 ꢙꢉ$ꢉꢊꢉꢄꢍꢉꢅꢐꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢒꢃꢍꢊꢌꢍꢎꢃꢑ ꢘꢉꢍꢎꢄꢌꢈꢌꢔꢋ ꢐꢊꢇ)ꢃꢄꢔ /ꢓꢗꢞꢓ+ꢛ.

DS21290E-page 28

MCP3201

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢐꢑꢄꢈꢈꢆꢒꢓꢊꢈꢋꢔꢃꢆꢗꢐꢛꢘꢆMꢆꢛꢄꢎꢎꢏ&'ꢆ"()#ꢆꢑꢑꢆ$ꢏꢅ%ꢆꢙꢐꢒ *ꢚ

ꢛꢏꢊꢃꢜ 1ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ2ꢇꢔꢉꢅ"ꢊꢇ)ꢃꢄꢔ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ2ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ033)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ2ꢇꢔꢃꢄꢔ

DS21290E-page 29

MCP3201

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ+,ꢋꢔꢆꢐ,ꢎꢋꢔꢕꢆꢐꢑꢄꢈꢈꢆꢒꢓꢊꢈꢋꢔꢃꢆꢗꢐ+ꢘꢆMꢆ-(-ꢆꢑꢑꢆ$ꢏꢅ%ꢆꢙ+ꢐꢐꢒꢇꢚ

ꢛꢏꢊꢃꢜ 1ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ2ꢇꢔꢉꢅ"ꢊꢇ)ꢃꢄꢔ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢒꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ2ꢇꢔꢃꢄꢔꢅꢖꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ033)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ2ꢇꢔꢃꢄꢔ

D

N

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b

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4ꢄꢃ%

ꢒꢚ55ꢚꢒ*ꢘ*ꢙꢖ

ꢐꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

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5ꢉꢇ"ꢅꢘꢎꢃꢍ2ꢄꢉ

5ꢉꢇ"ꢅ=ꢃ"%ꢎ

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ꢒꢃꢍꢊꢌꢍꢎꢃꢑ ꢘꢉꢍꢎꢄꢌꢈꢌꢔꢋ ꢐꢊꢇ)ꢃꢄꢔ /ꢓꢗꢞꢓ9:.

DS21290E-page 30

MCP3201

APPENDIX A: REVISION HISTORY

Revision E (November 2008)

The following is the list of modifications:

1. Updated Section 7.0 “Packaging Informa-

tion”

2. Updated Section “Product Identification

System”.

Revision D (January 2007)

The following is the list of modifications:

1. This revision includes updates to the packaging

diagrams.

diagrams.Revision C (August 2001)

The following is the list of modifications:

1. This revision includes undocumented changes.

Revision B (August 1999)

The following is the list of modifications:

1. This revision includes undocumented changes.

Revision A (September 1998)

• Original Release of this Document.

DS21290E-page 31

MCP3201

NOTES:

DS21290E-page 32

MCP3201

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a)

b)

c)

d)

e)

f)

MCP3201-BI/P:

B Grade,

Industrial Temperature,

8LD PDIP package.

Grade

Temperature

Range

Package

MCP3201-BI/SN: B Grade,

Industrial Temperature,

Device

Grade

MCP3201:

MCP3201T:

12-Bit A/D Converter w/SPI Interface

(Tape and Reel)

8LD SOIC package.

MCP3201-CI/P:

C Grade,

Industrial Temperature,

8LD PDIP package.

B:

C:

=

± LSB max INL (MSOP and TSSOP not available)

± LSB max INL

MCP3201-CI/MS: C Grade,

Industrial Temperature,

8LD MSOP package.

MCP3201-CI/SN: C Grade,

Temperature Range

Package

I

=

-40°C to+85°C(Industrial)

Industrial Temperature,

8LD SOIC package.

MS

P

SN

ST

=

Plastic Micro Small Outline (MSOP), 8-lead

Plastic DIP (300 mil Body), 8-lead

Plastic SOIC (150 mil Body), 8-lead

Plastic TSSOP (4.4 mm), 8-lead

MCP3201-CI/ST:

C Grade,

Industrial Temperature,

8LD TSSOP package.

g)

h)

i)

MCP3201T-BI/SN: Tape and Reel,B Grade,

Industrial Temperature,

8LD SOIC package.

MCP3201T-CI/MS: Tape and Reel, C Grade,

Industrial Temperature,

8LD MSOP package.

MCP3201T-CI/SN: Tape and Reel, C Grade,

Industrial Temperature,

8LD SOIC package.

j)

MCP3201T-CI/ST: Tape and Reel, C Grade,

Industrial Temperature,

8LD TSSOP package.

DS21290E-page 33

MCP3201

NOTES:

DS21290E-page 34

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC³²logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21290E-page 35

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/02/08

DS21290E-page 36


型号：	MCP3201T-CI/ST
厂家：	MICROCHIP
描述：	2.7V 12-Bit A/D Converter with SPI Serial Interface 2.7V 12位A / D转换器，带有SPI串行接口转换器模数转换器光电二极管
文件：	总36页 (文件大小：685K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3201T-CI/ST [MICROCHIP]

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