MCP3302T-BI/ST_技术文档

MCP3302/04

13-Bit Differential Input, Low Power A/D Converter

with SPI™ Serial Interface

Features

General Description

• Full Differential Inputs

The Microchip Technology Inc. MCP3302/04 13-bit A/D

converters feature full differential inputs and low power

consumption in a small package that is ideal for battery

powered systems and remote data acquisition applica-

tions. The MCP3302 is programmable to provide two

differential input pairs or four single ended inputs. The

MCP3304 is programmable and provides four differen-

tial input pairs or eight single ended inputs.

• MCP3302: 2 Differential or 4 Single ended Inputs

• MCP3304: 4 Differential or 8 Single ended Inputs

• ±1 LSB max DNL

• ±1 LSB max INL (MCP3302/04-B)

• ±2 LSB max INL (MCP3302/04-C)

• Single supply operation: 2.7V to 5.5V

• 100 ksps sampling rate with 5V supply voltage

• 50 ksps sampling rate with 2.7V supply voltage

• 50 nA typical standby current, 1 μA max

• 450 μA max active current at 5V

• Industrial temp range: -40°C to +85°C

• 14 and 16-pin PDIP, SOIC and TSSOP packages

• MXDEV^TMEvaluation kit available

Incorporating a successive approximation architecture

with on-board sample and hold circuitry, these 13-bit

A/D converters are specified to have ±1 LSB Differen-

tial Nonlinearity (DNL); ±1 LSB Integral Nonlinearity

(INL) for B-grade and ±2 LSB for C-grade devices. The

industry-standard SPI™ serial interface enables 13-bit

A/D converter capability to be added to any PIC^®

microcontroller.

The MCP3302/04 devices feature low current design

that permits operation with typical standby and active

currents of only 50 nA and 300 μA, respectively. The

devices operate over a broad voltage range of 2.7V to

5.5V and are capable of conversion rates of up to

100 ksps. The reference voltage can be varied from

400 mV to 5V, yielding input-referred resolution

between 98 μV and 1.22 mV.

Applications

• Remote Sensors

• Battery Operated Systems

• Transducer Interface

Package Types

PDIP, SOIC, TSSOP

The MCP3302 is available in 14-pin PDIP, 150 mil

SOIC and TSSOP packages. The MCP3304 is avail-

able in 16-pin PDIP and 150 mil SOIC packages. The

full differential inputs of these devices enable a wide

variety of signals to be used in applications such as

remote data acquisition, portable instrumentation and

battery operated applications.

CH0

CH1

CH2

CH3

NC

1

2

3

4

5

6

7

14

13

V_DD

V_REF

12 AGND

CLK

11

10

9

D_OUT

D_IN

NC

DGND

8

CS/SHDN

PDIP, SOIC

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

1

2

3

4

5

6

7

8

16 V_DD

V_REF

15

14

AGND

13 CLK

12 D_OUT

D_IN

11

10

9

CS/SHDN

DGND

DS21697C-page 1

MCP3302/04

Functional Block Diagram

AGND DGND

V_DD

V_REF

CH0

CH1

Input

Channel

Mux

CH7*

CDAC

Comparator

-

Sample

& Hold

Circuits

13-Bit SAR

+

Shift

Register

Control Logic

CS/SHDN D_IN

CLK

D_OUT

* Channels 5-7 available on MCP3304 Only

DS21697C-page 2

MCP3302/04

1.0

ELECTRICAL

PIN FUNCTION TABLE

CHARACTERISTICS

Name

Function

Maximum Ratings*

CH0-CH7

DGND

CS/SHDN

D_IN

Analog Inputs

Digital Ground

V_DD........................................................................7.0V

All inputs and outputs w.r.t. V_SS.....-0.3V to V_DD+0.3V

Storage temperature ..........................-65°C to +150°C

Ambient temp. with power applied.....-65°C to +125°C

Maximum Junction Temperature ....................... 150°C

ESD protection on all pins (HBM)......................... > 4 kV

Chip Select / Shutdown Input

Serial Data In

D_OUT

Serial Data Out

CLK

Serial Clock

AGND

V_REF

Analog Ground

Reference Voltage Input

+2.7V to 5.5V Power Supply

*Notice: Stresses above those listed under “Maximum rat-

ings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied. Expo-

sure to maximum rating conditions for extended periods may

affect device reliability.

V_DD

ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise noted, all parameters apply at V_DD= 5V, V = 0V, and V

= 5V. Full differential

SS

REF

input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

= -40°C to +85°C (Note 7). Conversion speed (F

) is 100 ksps with F

= 21*F

CLK SAMPLE

AMB

SAMPLE

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Conversion Rate

Maximum Sampling Frequency

F

—

100

50

ksps Note 8

SAMPLE

ksps

V

= V

= 2.7V, V

=1.35V

DD

REF

CM

Conversion Time

Acquisition Time

T

13

CLK

periods

CONV

T

1.5

CLK

ACQ

periods

DC Accuracy

Resolution

12 data bits + sign

bits

Integral Nonlinearity

INL

—

±0.5

±1

LSB

MCP3302/04-B

MCP3302/04-C

±2

±1

+2

+6

Differential Nonlinearity

Positive Gain Error

Negative Gain Error

Offset Error

DNL

—

-3

±0.5

-0.75

-0.5

+3

LSB

Monotonic over temperature

Note 1: This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V level.

REF

3:

4:

V

= 0.1V to 4.9V @ 1 kHz.

IN

=5V

±500 mV @ 1 kHz, see test circuit Figure 3-3.

DD

P-P

5: Maximum clock frequency specification must be met.

6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz

7: TSSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.

V

REF

IN

DS21697C-page 3

MCP3302/04

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V_DD= 5V, V = 0V, and V

= 5V. Full differential

SS

REF

input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

= -40°C to +85°C (Note 7). Conversion speed (F

) is 100 ksps with F

= 21*F

CLK SAMPLE

AMB

SAMPLE

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Dynamic Performance

Total Harmonic Distortion

Signal to Noise and Distortion

Spurious Free Dynamic Range

Common Mode Rejection

Channel to Channel Crosstalk

Power Supply Rejection

Reference Input

THD

SINAD

SFDR

CMRR

CT

—

-91

78

—

dB

Note 3

Note 6

Note 4

92

79

> -110

74

PSR

Voltage Range

0.4

—

V

Note 2

DD

Current Drain

—

100

0.001

150

3

μA

CS = V = 5V

DD

Analog Inputs

Full Scale Input Span

Absolute Input Voltage

Leakage Current

CH0 - CH7

-V

—

V

REF

-0.3

V

+ 0.3

DD

—

0.001

1

±1

—

μA

kΩ

pF

Switch Resistance

R

See Figure 6-3

S

Sample Capacitor

C

25

SAMPLE

Digital Input/Output

Data Coding Format

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage

Low Level Output Voltage

Input Leakage Current

Output Leakage Current

Pin Capacitance

Binary Two’s Complement

V

0.7 V

—

0.3 V

—

V

IH

DD

V

IL

DD

V

4.1

—

V

I

= -1 mA, V = 4.5V

DD

OH

OL

V

I

0.4

10

V

= 1 mA, V = 4.5V

OL

DD

-10

—

μA

pF

V

= V or V

DD

LI

IN

SS

I

= V or V

SS DD

LO

OUT

C

, C

T

= 25°C, F = 1 MHz, Note 1

IN

OUT

AMB

Note 1: This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V level.

REF

3:

4:

V

= 0.1V to 4.9V @ 1 kHz.

IN

=5V

±500 mV @ 1 kHz, see test circuit Figure 3-3.

DD

P-P

5: Maximum clock frequency specification must be met.

6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz

7: TSSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.

V

REF

IN

DS21697C-page 4

MCP3302/04

ELECTRICAL SPECIFICATIONS (CONTINUED)

Electrical Characteristics: Unless otherwise noted, all parameters apply at V_DD= 5V, V = 0V, and V

= 5V. Full differential

SS

REF

input configuration (Figure 3-4) with fixed common mode voltage of 2.5V. All parameters apply over temperature with

T

= -40°C to +85°C (Note 7). Conversion speed (F

) is 100 ksps with F

= 21*F

CLK SAMPLE

AMB

SAMPLE

Parameter

Symbol

Min

Typ

Max

Units

Conditions

Timing Specifications:

Clock Frequency (Note 8)

F

0.105

—

2.1

1.05

MHz

V

= 5V, F

= 2.7V, F

= 100 ksps

CLK

DD

SAMPLE

= 50 ksps

SAMPLE

Clock High Time

T

210

100

50

—

50

ns

Note 5

HI

Clock Low Time

T

ns

LO

CS Fall To First Rising CLK Edge

Data In Setup time

T

ns

SUCS

T

ns

SU

Data In Hold Time

T

—

ns

HD

DO

CLK Fall To Output Data Valid

—

125

200

ns

V

= 5V, see Figure 3-1

= 2.7V, see Figure 3-1

DD

CLK Fall To Output Enable

CS Rise To Output Disable

CS Disable Time

T

—

125

200

ns

V

= 5V, see Figure 3-1

= 2.7V, see Figure 3-1

EN

DD

T

100

ns

See test circuits, Figure 3-1

Note 1

DIS

T

475

—

ns

CSH

D

Rise Time

T

100

See test circuits, Figure 3-1

OUT

R

Note 1

D

Fall Time

T

—

100

ns

See test circuits, Figure 3-1

OUT

F

Note 1

Power Requirements:

Operating Voltage

Operating Current

V

I

2.7

—

5.5

V

DD

—

300

200

450

—

μA

V

, V

= 5V, D

= 2.7V, D

unloaded

OUT

DD

REF

unloaded

OUT

Standby Current

I

—

0.05

1

μA

CS = V = 5.0V

DD

DDS

Temperature Ranges:

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistance:

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

Thermal Resistance, 16L-PDIP

Thermal Resistance, 16L-SOIC

T

-40

-65

—

+85

°C

A

T

A

T

+150

A

θ

—

70

108

100

70

—

°C/W

JA

θ

90

Note 1: This specification is established by characterization and not 100% tested.

2: See characterization graphs that relate converter performance to V level.

REF

3:

4:

V

= 0.1V to 4.9V @ 1 kHz.

IN

=5V

±500 mV @ 1 kHz, see test circuit Figure 3-3.

DD

P-P

5: Maximum clock frequency specification must be met.

6: = 400 mV, V = 0.1V to 4.9V @ 1 kHz

7: TSSOP devices are only specified at 25°C and +85°C.

8: For slow sample rates, see Section 6.2.1 for limitations on clock frequency.

V

REF

IN

DS21697C-page 5

MCP3302/04

.

T

CSH

CS

T

SUCS

T

LO

HI

CLK

T

HD

SU

D

IN

MSB IN

T

F

R

T

DO

DIS

T

EN

D

LSB

OUT

Null Bit

Sign BIT

FIGURE 1-1:

Timing Parameters

DS21697C-page 6

MCP3302/04

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

.

1

0.8

0.6

1

0.8

0.6

V_DD=V_REF=2.7V

Positive INL

Negative INL

0.4

0.2

0

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

Negative INL

0

10

20

30

40

50

60

70

0

50

100

Sample Rate (ksps)

150

200

Sample Rate (ksps)

FIGURE 2-1:

Integral Nonlinearity (INL)

FIGURE 2-4:

Integral Nonlinearity (INL)

vs. Sample Rate

vs. Sample Rate (V_DD= 2.7V)

.

2

1.5

1

2

V_DD= 2.7V

1.5

1

Positive INL

Negative INL

0.5

0

0.5

0

-0.5

-1

-0.5

Negative INL

-1

-1.5

-2

-1.5

-2

0

1

2

3

4

5

0

0.5

1

1.5

2

2.5

3

V_REF(V)

FIGURE 2-2:

Integral Nonlinearity (INL)

FIGURE 2-5:

Integral Nonlinearity (INL)

vs. V_REF.

vs. V_REF(V_DD= 2.7V)

1

0.8

0.6

0.4

0.2

0

1

V_DD=V_REF=2.7V

0.8

0.6

0.4

0.2

0

F_SAMPLE= 50 ksps

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

-4096 -3072 -2048 -1024

0

1024

2048

3072

4096

-4096 -3072 -2048 -1024

0

1024

2048

3072

4096

Code

FIGURE 2-3:

Integral Nonlinearity (INL)

FIGURE 2-6:

Integral Nonlinearity (INL)

vs. Code (Representative Part).

vs. Code (Representative Part, V_DD= 2.7V).

DS21697C-page 7

MCP3302/04

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

Positive INL

Negative INL

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

Negative INL

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature(°C)

Temperature (°C)

FIGURE 2-7:

Integral Nonlinearity (INL)

FIGURE 2-10:

Integral Nonlinearity (INL)

vs. Temperature.

vs. Temperature (V_DD= 2.7V).

1

0.8

0.6

0.4

0.2

0

1

V_DD=V_REF=2.7V

0.8

0.6

Positive DNL

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

Negative DNL

-0.4

-0.6

-0.8

-1

Negative DNL

0

10

20

30

40

50

60

70

-1

0

50

100

150

200

Sample Rate (ksps)

FIGURE 2-8:

Differential Nonlinearity

FIGURE 2-11:

Differential Nonlinearity

(DNL) vs. Sample Rate.

(DNL) vs. Sample Rate (V_DD= 2.7V).

2

1.5

1

2

V_DD=2.7V

F_SAMPLE= 50 ksps

1.5

1

Positive DNL

0.5

0

0.5

0

Negative DNL

-0.5

-1

Negative DNL

-0.5

-1

-1.5

-2

-1.5

-2

0

1

2

3

4

5

6

0

0.5

1

1.5

2

2.5

3

V_REF(V)

FIGURE 2-9:

Differential Nonlinearity

FIGURE 2-12:

Differential Nonlinearity

(DNL) vs. V_REF

.

(DNL) vs. V_REF(V_DD= 2.7V).]

DS21697C-page 8

MCP3302/04

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

1

0.8

0.6

0.4

0.2

0

1

0.8

0.6

0.4

0.2

0

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

-4096 -3072 -2048 -1024

0

1024

2048

3072

4096

-4096 -3072 -2048 -1024

0

1024

2048

3072

4096

Code

FIGURE 2-13:

Differential Nonlinearity

FIGURE 2-16:

Differential Nonlinearity

(DNL) vs. Code (Representative Part).

(DNL) vs. Code (Representative Part,

V

_DD= 2.7V).

1

0.8

0.6

1

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

0.8

0.6

0.4

0.2

0

Positive DNL

Negative DNL

Positive DNL

0.4

0.2

0

-0.2

-0.4

-0.6

-0.8

-1

-0.2

-0.4

-0.6

-0.8

-1

Negaitive DNL

-50

-25

0

25

50

75

100

125

150

-50

-25

0

25

50

75

100

125

150

Temperature (°C)

FIGURE 2-14:

Differential Nonlinearity

FIGURE 2-17:

Differential Nonlinearity

(DNL) vs. Temperature.

(DNL) vs. Temperature (V_DD= 2.7V).

4

3

2

20

18

16

14

12

10

8

V_DD=5V

V_DD= 5V

1

F_SAMPLE= 100 ksps

0

-1

-2

-3

6

4

V_DD= 2.7V

2

F_SAMPLE= 50 ksps

0

1

2

3

4

5

6

0

1

2

3

4

5

6

V_REF(V)

FIGURE 2-15:

V_REF

Positive Gain Error vs.

FIGURE 2-18:

Offset Error vs. V_REF.

.

DS21697C-page 9

MCP3302/04

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

0

-0.2

-0.4

-0.6

-0.8

-1

3.5

3

V_DD=V_REF=5V

F_SAMPLE= 100 ksps

V_DD=V_REF=5V

2.5

2

F_SAMPLE= 100 ksps

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

1.5

1

-1.2

-1.4

-1.6

-1.8

V_DD=V_REF=2.7V

0.5

0

F_SAMPLE= 50 ksps

-50

0

50

100

150

-50

0

50

100

150

Temperature (°C)

FIGURE 2-19:

Positive Gain Error vs.

FIGURE 2-22:

Offset Error vs.

Temperature.

90

80

70

100

90

80

70

60

50

40

30

20

10

V_DD=V_REF=5V

F_SAMPLE= 100 ksps

60

50

40

30

20

10

0

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

V_DD=V_REF=2.7V

_SAMPLE= 50 ksps

F

V_DD=V_REF=5V

F_SAMPLE= 100 ksps

0

1

10

100

10

100

Input Frequency (kHz)

FIGURE 2-20:

Signal to Noise Ratio (SNR)

FIGURE 2-23:

Signal to Noise and

vs. Input Frequency.

Distortion (SINAD) vs. Input Frequency.

0

-10

-20

80

70

60

50

40

-30

V_DD=V_REF=2.7V

-40

V_DD=V_REF=5V

F_SAMPLE= 50 ksps

F_SAMPLE= 100 ksps

-50

-60

-70

-80

-90

V_DD=V_REF=2.7V

V_DD=V_REF=5V

30

20

10

0

F_SAMPLE= 50 ksps

F_SAMPLE= 100 ksps

-100

1

-40

-35

-30

-25

-20

-15

-10

-5

0

10

Input Frequency (kHz)

100

Input Signal Level (dB)

FIGURE 2-21:

Total Harmonic Distortion

FIGURE 2-24:

Signal to Noise and

(THD) vs. Input Frequency.

Distortion (SINAD) vs. Input Signal Level.

DS21697C-page 10

MCP3302/04

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

13

12

11

10

9

13

12.8

12.6

12.4

12.2

12

V_DD=V_REF=5V

V_DD=2.7V

V_DD=5V

F_SAMPLE= 100 ksps

F_SAMPLE= 50 ksps

F_SAMPLE= 100 ksps

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

11.8

11.6

11.4

11.2

8

7

0

1

2

3

4

5

1

10

Input Frequency (kHz)

100

V_REF(V)

FIGURE 2-25:

Effective Number of Bits

FIGURE 2-28:

Effective Number of Bits

(ENOB) vs. V_REF

.

(ENOB) vs. Input Frequency.

100

90

80

70

60

-30

-35

-40

-45

-50

-55

-60

-65

-70

-75

-80

V_DD=V_REF=5V

0.1 µF Bypass

Capacitor

F_SAMPLE= 100 ksps

V_DD=V_REF=2.7V

50

40

30

20

10

0

F_SAMPLE= 50 ksps

1

10

Input Frequency (kHz)

100

1

10

100

1000

10000

Ripple Frequency (kHz)

FIGURE 2-26:

Spurious Free Dynamic

FIGURE 2-29:

Power Supply Rejection

Range (SFDR) vs. Input Frequency.

(PSR) vs. Ripple Frequency.

0

-10

0

-10

-20

-30

-40

-50

-60

-70

-80

-90

-100

-110

-120

-130

-140

-150

-100

-110

-120

-130

-140

-150

0

10000

20000

30000

40000

50000

0

5000

10000

Frequency (Hz)

15000

20000

25000

Frequency (Hz)

FIGURE 2-27:

Frequency Spectrum of

FIGURE 2-30:

Frequency Spectrum of

10 kHz Input (Representative Part).

1 kHz Input (Representative Part, V_DD= 2.7V).

DS21697C-page 11

MCP3302/04

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

450

400

350

300

250

200

150

100

50

120

100

80

60

40

20

0

2

2.5

3

50

0

3.5

4

4.5

5

5.5

6

2

2.5

3

3.5

4

4.5

5

5.5

6

V_DD(V)

FIGURE 2-31:

I_DDvs. V_DD

.

FIGURE 2-34:

I_REFvs. V_DD.

600

500

400

300

200

100

120

100

80

V_DD=V_REF=5V

60

40

V_DD=V_REF=2.7V

20

0

100

150

200

50

100

150

200

Sample Rate (ksps)

FIGURE 2-32:

I_DDvs. Sample Rate.

FIGURE 2-35:

I_REFvs. Sample Rate.

400

350

300

250

200

150

100

50

100

90

80

70

60

50

40

30

20

10

V_DD=V_REF=5V

F_SAMPLE= 100 ksps

V_DD=V_REF=2.7V

F_SAMPLE= 50 ksps

0

-50

50

100

150

-50

0

50

100

150

Temperature (°C)

FIGURE 2-33:

I_DDvs. Temperature.

FIGURE 2-36:

I_REFvs. Temperature.

DS21697C-page 12

MCP3302/04

Note: Unless otherwise indicated, V_DD= V_REF= 5V, Full differential input configuration, V_SS= 0V,

F_SAMPLE= 100 ksps, F_CLK= 21*F_SAMPLE, T_A= 25°C.

80

70

60

50

40

30

20

10

0

2

1.5

1

V_DD=V_REF=2.7V

V_DD=V_REF=5V

0.5

0

F_SAMPLE= 50 ksps

F_SAMPLE= 100 ksps

-0.5

-1

-1.5

-2

2

2.5

3

3.5

4

4.5

5

5.5

6

-50

0

50

100

150

V_DD(V)

Temperature (°C)

FIGURE 2-37:

I_DDSvs. V_DD

.

FIGURE 2-40:

Negative Gain Error vs.

Temperature.

100

10

80

79

78

77

76

75

74

73

72

71

1

0.1

0.01

0.001

-50

-25

0

25

50

75

100

70

1

Temperature (°C)

10

100

1000

Input Frequency (kHz)

FIGURE 2-38:

I_DDSvs. Temperature.

FIGURE 2-41:

Common Mode Rejection

vs. Frequency.

4

3.5

3

2.5

2

1.5

1

V_DD=5V

F_SAMPLE= 100 ksps

0.5

0

-0.5

-1

0

1

2

3

4

5

6

V_REF(V)

FIGURE 2-39:

Negative Gain Error vs.

Reference Voltage.

DS21697C-page 13

MCP3302/04

3.0

TEST CIRCUITS

1 kΩ

1/2 MCP602

1 kΩ

+

-

1.4V

5V ±500 mV_P-P

To V_DDon DUT

20 kΩ

5VP-P

3 kΩ

Test Point

D_OUT

1 kΩ

2.63V

C_L= 100 pF

FIGURE 3-3:

Test Circuit (PSRR).

Power Supply Sensitivity

FIGURE 3-1:

Load Circuit for T_R, T_F, T_DO.

Test Point

V

= 5V

V

= 5V

DD

REF

V_DD

1 µF

0.1 µF

T_DISWaveform 2

0.1 µF

V_DD/2

3 kΩ

100 pF

D_OUT

T_ENWaveform

5V

P-P

T_DISWaveform 1

IN(+)

IN(-)

V

REF DD

V_SS

MCP330X

V

SS

5V

P-P

Voltage Waveforms for T_DIS

V_IH

V

= 2.5V

CM

CS

D_OUT

Waveform 1*

90%

10%

FIGURE 3-4:

Configuration Example.

Full Differential Test

T_DIS

D_OUT

Waveform 2†

V

= 2.5V

1µF

V

= 5V

DD

REF

*Waveform 1 is for an output with internal con-

ditions such that the output is high, unless dis-

abled by the output control.

0.1µF

IN(+)

V

5V

†Waveform 2 is for an output with internal con-

ditions such that the output is low, unless dis-

abled by the output control.

REF DD

P-P

MCP330X

IN(-)

V

SS

V

= 2.5V

CM

FIGURE 3-2:

T_EN

Load circuit for T_DISand

.

FIGURE 3-5:

Pseudo Differential Test

Configuration Example.

DS21697C-page 14

MCP3302/04

4.6

Serial Clock (CLK)

4.0

PIN DESCRIPTIONS

The SPI clock pin is used to initiate a conversion and to

clock out each bit of the conversion as it takes place.

See Section 6.2 for constraints on clock speed. See

Figure 7-2 for serial communication protocol.

The descriptions of the pins are listed in Table 4-1.

TABLE 4-1:

Name

PIN FUNCTION TABLE

Function

4.7

AGND

CH0-CH7

DGND

CS/SHDN

D_IN

Analog Inputs

Digital Ground

Ground connection to internal analog circuitry. To

ensure accuracy, this pin must be connected to the

same ground as DGND. If an analog ground plane is

available, it is recommended that this device be tied to

the analog ground plane in the circuit. See Section 6.6

for more information regarding circuit layout.

Chip Select / Shutdown Input

Serial Data In

D_OUT

Serial Data Out

CLK

Serial Clock

AGND

V_REF

Analog Ground

4.8

Voltage Reference (V

)

REF

Reference Voltage Input

+2.7V to 5.5V Power Supply

This input pin provides the reference voltage for the

device, which determines the maximum range of the

analog input signal and the LSB size.

V_DD

4.1

CH0-CH7

The LSB size is determined according to the equation

shown below. As the reference input is reduced, the

LSB size is reduced accordingly.

Analog input channels. These pins have an absolute

voltage range of V_SS- 0.3V to V_DD+ 0.3V. The full scale

differential input range is defined as the absolute value

of (IN+) - (IN-). This difference can not exceed the

value of V_REF- 1 LSB or digital code saturation will

occur.

EQUATION

2 x V_REF

LSB Size =

8192

4.2

DGND

Ground connection to internal digital circuitry. To

ensure accuracy this pin must be connected to the

same ground as AGND. If an analog ground plane is

available, it is recommended that this device be tied to

the analog ground plane in the circuit. See Section 6.6

for more information regarding circuit layout.

When using an external voltage reference device, the

system designer should always refer to the manufac-

turer’s recommendations for circuit layout. Any instabil-

ity in the operation of the reference device will have a

direct effect on the accuracy of the ADC conversion

results.

4.3

Chip Select/Shutdown (CS/SHDN)

4.9

V

DD

The CS/SHDN pin is used to initiate communication

with the device when pulled low. This pin will end a con-

version and put the device in low power standby when

pulled high. The CS/SHDN pin must be pulled high

between conversions and cannot be tied low for multi-

ple conversions. See Figure 7-2 for serial communica-

tion protocol.

The voltage on this pin can range from 2.7 to 5.5V. To

ensure accuracy, a 0.1 μF ceramic bypass capacitor

should be placed as close as possible to the pin. See

Section 6.6 for more information regarding circuit lay-

out.

4.4

Serial Data Input (D )

IN

The SPI port serial data input pin is used to clock in

input channel configuration data. Data is latched on the

rising edge of the clock. See Figure 7-2 for serial com-

munication protocol.

4.5

Serial Data Output (D

)

OUT

The SPI serial data output pin is used to shift out the

results of the A/D conversion. Data will always change

on the falling edge of each clock as the conversion

takes place. See Figure 7-2 for serial communication

protocol.

DS21697C-page 15

MCP3302/04

Signal to Noise Ratio - Signal to Noise Ratio (SNR) is

defined as the ratio of the signal to noise measured at

the output of the converter. The signal is defined as the

rms amplitude of the fundamental frequency of the

input signal. The noise value is dependant on the

device noise as well as the quantization error of the

converter and is directly affected by the number of bits

in the converter. The theoretical signal to noise ratio

limit based on quantization error only for an N-bit con-

verter is defined as:

5.0

DEFINITION OF TERMS

Bipolar Operation - This applies to either a differential

or single ended input configuration, where both positive

and negative codes are output from the A/D converter.

Full bipolar range includes all 8192 codes. For bipolar

operation on a single ended input signal, the A/D con-

verter must be configured to operate in pseudo differ-

ential mode.

Unipolar Operation - This applies to either a single

ended or differential input signal where only one side of

the device transfer is being used. This could be either

the positive or negative side, depending on which input

(IN+ or IN-) is being used for the DC bias. Full unipolar

operation is equivalent to a 12-bit converter.

EQUATION

SNR = (6.02N + 1.76)dB

For a 13-bit converter, the theoretical SNR limit is

80.02 dB.

Full Differential Operation - Applying a full differential

signal to both the IN(+) and IN(-) inputs is referred to as

full differential operation. This configuration is

described in Figure 3-4.

Total Harmonic Distortion - Total Harmonic Distortion

(THD) is the ratio of the rms sum of the harmonics to

the fundamental, measured at the output of the con-

verter. For the MCP3302/04, it is defined using the first

9 harmonics, as is shown in the following equation:

Pseudo-Differential Operation - Applying a single

ended signal to only one of the input channels with a

bipolar output is referred to as pseudo differential oper-

ation. To obtain a bipolar output from a single ended

input signal the inverting input of the A/D converter

must be biased above V_SS. This operation is described

in Figure 3-5.

EQUATION

V₂²+ V²₃+ V²₄+ ..... + V²₈+ V²₉

THD(-dB) = –20 log--------------------------------------------------------------------------

V²₁

Integral Nonlinearity - The maximum deviation from a

straight line passing through the endpoints of the bipo-

lar transfer function is defined as the maximum integral

nonlinearity error. The endpoints of the transfer func-

tion are a point 1/2 LSB above the first code transition

(0x1000) and 1/2 LSB below the last code transition

(0x0FFF).

Here V₁is the rms amplitude of the fundamental and V₂

through V₉are the rms amplitudes of the second

through ninth harmonics.

Signal to Noise plus Distortion (SINAD) - Numeri-

cally defined, SINAD is the calculated combination of

SNR and THD. This number represents the dynamic

performance of the converter, including any harmonic

distortion.

Differential Nonlinearity - The difference between two

measured adjacent code transitions and the 1 LSB

ideal is defined as differential nonlinearity.

Positive Gain Error - This is the deviation between the

last positive code transition (0x0FFF) and the ideal volt-

age level of V_REF-1/2 LSB, after the bipolar offset error

has been adjusted out.

EQUATION

SINAD(dB) = 20 log 10^{(SNR ⁄ 10)}+ 10^{–(THD ⁄ 10)}

Negative Gain Error - This is the deviation between

the last negative code transition (0X1000) and the ideal

voltage level of -V_REF-1/2 LSB, after the bipolar offset

error has been adjusted out.

EffectIve Number of Bits - Effective Number of Bits

(ENOB) states the relative performance of the ADC in

terms of its resolution. This term is directly related to

SINAD by the following equation:

Offset Error - This is the deviation between the first

positive code transition (0x0001) and the ideal 1/2 LSB

voltage level.

EQUATION

SINAD – 1.76

ENOB(N) = ----------------------------------

6.02

Acquisition Time - The acquisition time is defined as

the time during which the internal sample capacitor is

charging. This occurs for 1.5 clock cycles of the exter-

nal CLK as defined in Figure 7-2.

For SINAD performance of 78 dB, the effective number

of bits is 12.66.

Conversion Time - The conversion time occurs imme-

diately after the acquisition time. During this time, suc-

cessive approximation of the input signal occurs as the

13-bit result is being calculated by the internal circuitry.

This occurs for 13 clock cycles of the external CLK as

defined in Figure 7-2.

Spurious Free Dynamic Range - Spurious Free

Dynamic Range (SFDR) is the ratio of the rms value of

the fundamental to the next largest component in

ADC’s output spectrum. This is, typically, the first har-

monic, but could also be a noise peak.

DS21697C-page 16

MCP3302/04

6.2

Driving the Analog Input

6.0

6.1

APPLICATIONS INFORMATION

Conversion Description

The analog input of the MCP3302/04 is easily driven,

either differentially or single ended. Any signal that is

common to the two input channels will be rejected by

the common mode rejection of the device. During the

charging time of the sample capacitor, a small charging

current will be required. For low source impedances,

this input can be driven directly. For larger source

impedances, a larger acquisition time will be required

due to the RC time constant that includes the source

impedance. For the A/D Converter to meet specifica-

tion, the charge holding capacitor (C_SAMPLE) must be

given enough time to acquire a 13-bit accurate voltage

level during the 1.5 clock cycle acquisition period.

The MCP3302/04 A/D converters employ a conven-

tional SAR architecture. With this architecture, the

potential between the IN+ and IN- inputs are simulta-

neously sampled and stored with the internal sample

circuits for 1.5 clock cycles. Following this sampling

time, the input hold switches of the converter open and

the device uses the collected charge to produce a

serial 13-bit binary two’s complement output code. This

conversion process is driven by the external clock and

must include 13 clock cycles, one for each bit. During

this process, the most significant bit (MSB) is output

first. This bit is the sign bit and indicates if the IN+ or IN-

input is at a higher potential.

An analog input model is shown in Figure 6-3. This

model is accurate for an analog input, regardless if it is

configured as a single ended input, or the IN+ and IN-

input in differential mode. In this diagram, it is shown

that the source impedance (R_S) adds to the internal

sampling switch (R_SS) impedance, directly affecting the

time that is required to charge the capacitor (C_SAMPLE).

Consequently, a larger source impedance with no addi-

tional acquisition time increases the offset, gain and

integral linearity errors of the conversion. To overcome

this, a slower clock speed can be used to allow for the

longer charging time. Figure 6-2 shows the maximum

clock speed associated with source impedances.

CDAC

Hold

IN+

C

SAMP

+

-

Comp

13-Bit SAR

SAMP

IN-

Shift

Register

Hold

D

OUT

2.5

2.0

1.5

1.0

0.5

0.0

FIGURE 6-1:

Simplified Block Diagram.

100

1000

10000

100000

Source Resistance (ohms)

FIGURE 6-2:

Maximum Clock Frequency

vs. Source Resistance (R_S) to maintain ±1 LSB

INL.

DS21697C-page 17

MCP3302/04

V_DD

Sampling

Switch

V_T= 0.6V

R_S= 1 kΩ

CHx

R_SS

SS

C_SAMPLE

= DAC capacitance

= 25 pF

C_PIN

7 pF

I_LEAKAGE

±1 nA

VA

V_SS

Legend

VA

signal source

=

source impedance

input channel pad

input pin capacitance

threshold voltage

R

SS

CHx

C

V

T

leakage current at the pin

due to various junctions

I

LEAKAGE

SS

sampling switch

=

sampling switch resistor

sample/hold capacitance

R

S

C

SAMPLE

bring down the high pass corner. The value of R will

need to be 1 kΩ, or less, since higher input impedances

require additional acquisition time. Using the RC values

in Figure 6-4, we have a 100 Hz corner frequency. See

Figure 2-12 for relation between input impedance and

acquisition time.

FIGURE 6-3:

6.2.1

Analog Input Model.

MAINTAINING MINIMUM CLOCK

SPEED

When the MCP3302/04 initiates, charge is stored on

the sample capacitor. When the sample period is com-

plete, the device converts one bit for each clock that is

received. It is important for the user to note that a slow

clock rate will allow charge to bleed off the sample cap

while the conversion is taking place. For the MCP330X

devices, the recommended minimum clock speed dur-

ing the conversion cycle (T_CONV) is 105 kHz. Failure to

meet this criteria may induce linearity errors into the

conversion outside the rated specifications. It should

be noted that during the entire conversion cycle, the

A/D converter does not have requirements for clock

speed or duty cycle, as long as all timing specifications

are met.

V_DD= 5V

0.1 µF

C

10 µF

IN+

VIN

MCP330X

R

1 kΩ

IN-

V_REF

V_OUT

V_IN

6.3

Biasing Solutions

MCP1525

0.1 µF

1 µF

For pseudo-differential bipolar operation, the biasing

circuit (shown in Figure 6-4) shows a single ended

input AC coupled to the converter. This configuration

will give a digital output range of -4096 to +4095. With

the 2.5V reference, the LSB size equal to 610 μV.

FIGURE 6-4:

circuit for bipolar operation.

Pseudo-differential biasing

Using an external operation amplifier on the input

allows for gain and also buffers the input signal from the

input to the ADC allowing for a higher source imped-

ance. This circuit is shown in Figure 6-5.

Although the ADC is not production tested with a 2.5V

reference as shown, linearity will not change more than

0.1 LSB. See Figure 2-2 and Figure 2-9 for DNL and

INL errors versus V_REFat V_DD= 5V. A trade-off exists

between the high pass corner and the acquisition time.

The value of C will need to be quite large in order to

DS21697C-page 18

MCP3302/04

6.4

Common Mode Input Range

The common mode input range has no restriction and is

equal to the absolute input voltage range: V_SS-0.3V to

V_DD+ 0.3V. However, for a given V_REF, the common

mode voltage has a limited swing, if the entire range of

the A/D converter is to be used. Figure 6-7 and

Figure 6-8 show the relationship between V_REFand the

common mode voltage swing. A smaller V_REFallows for

wider flexibility in a common mode voltage. V_REFlevels,

down to 400 mv, exhibit less than 0.1 LSB change in

DNL and INL. For characterization graphs that show

this performance relationship, see Figure 2-9 and

Figure 2-12.

V

= 5V

DD

10 kΩ

0.1 μF

MCP6021

1 kΩ

-

IN+

IN-

V

+

MCP330X

IN

1 μF

V

REF

1 MΩ

1 μF

V

IN

OUT

MCP1525

V_DD= 5V

0.1 μF

5

4

3

4.05V

2.8V

FIGURE 6-5:

Adding an amplifier allows

for gain and also buffers the input from any high

impedance sources.

2

2.3V

1

This circuit shows that some headroom will be lost due

to the amplifier output not being able to swing all the

way to the rail. An example would be for an output

swing of 0V to 5V. This limitation can be overcome by

supplying a V_REFthat is slightly less than the common

mode voltage. Using a 2.048V reference for the A/D

converter while biasing the input signal at 2.5V solves

the problem. This circuit is shown in Figure 6-5.

0.95V

0

-1

0.25

1.0

5.0

2.5

4.0

V

(V)

REF

FIGURE 6-7:

Common Mode Input Range

of Full Differential Input Signal versus V_REF

.

V

= 5V

DD

V_DD= 5V

10 kΩ

0.1 µF

5

4

4.05V

0.95V

MCP606

1 kΩ

2.8V

2.3V

3

2

1

0

-

IN+

IN-

V

+

MCP330X

IN

1 µF

V

REF

1 MΩ

10 kΩ

2.048V

-1

0.25

0.5

2.5

1.25

(V)

2.0

V

IN

OUT

V

REF

1 µF

MCP1525

0.1 µF

FIGURE 6-8:

Common Mode Input Range

versus V_REFfor Pseudo Differential Input.

FIGURE 6-6:

Circuit solution to overcome

amplifier output swing limitation.

DS21697C-page 19

MCP3302/04

6.5

Buffering/Filtering the Analog

Inputs

6.6

Layout Considerations

When laying out a printed circuit board for use with

analog components, care should be taken to reduce

noise wherever possible. A bypass capacitor from V_DD

to ground should always be used with this device and

should be placed as close as possible to the device pin.

A bypass capacitor value of 0.1 μF is recommended.

Inaccurate conversion results may occur if the signal

source for the A/D converter is not a low impedance

source. Buffering the input will overcome the imped-

ance issue. It is also recommended that an analog filter

be used to eliminate any signals that may be aliased

back into the conversion results. This is illustrated in

Figure 6-9, where an op amp is used to drive the ana-

log input of the MCP3302/04. This amplifier provides a

low impedance source for the converter input and a low

pass filter, which eliminates unwanted high frequency

noise. Values shown are for a 10 Hz Butterworth Low

Pass filter.

Digital and analog traces on the board should be sepa-

rated as much as possible, with no traces running

underneath the device or the bypass capacitor. Extra

precautions should be taken to keep traces with high

frequency signals (such as clock lines) as far as possi-

ble from analog traces.

Use of an analog ground plane is recommended in

order to keep the ground potential the same for all

devices on the board. Providing V_DDconnections to

devices in a “star” configuration can also reduce noise

by eliminating current return paths and associated

errors (see Figure 6-10). For more information on lay-

out tips when using the MCP3302/04, or other ADC

devices, refer to Application Note 688, “Layout Tips for

12-Bit A/D Converter Applications”.

Low pass (anti-aliasing) filters can be designed using

Microchip’s interactive FilterLab^®software. FilterLab

will calculate capacitor and resistor values, as well as

determine the number of poles that are required for the

application. For more information on filtering signals,

see Application Note 699 “Anti-Aliasing Analog Filters

for Data Acquisition Systems”.

V_DD

10 µF

V_DD

4.096V

Reference

Connection

1 µF

0.1 µF

MCP1541

C_L

0.1 µF

V_REF

IN+

MCP330X

IN-

Device 4

2.2 µF

MCP601

7.86 kΩ

V_IN

+

-

14.6 kΩ

1 µF

Device 1

FIGURE 6-9:

The MCP601 Operational

Device 3

Amplifier is used to implement a 2nd order anti-

aliasing filter for the signal being converted by

the MCP3302/04.

Device 2

FIGURE 6-10:

V_DDtraces arranged in a

‘Star’ configuration in order to reduce errors

caused by current return paths.

DS21697C-page 20

MCP3302/04

6.7

Utilizing the Digital and Analog

Ground Pins

The MCP3302/04 devices provide both digital and ana-

log ground connections to provide another means of

noise reduction. As shown in Figure 6-11, the analog

and digital circuitry are separated internal to the device.

This reduces noise from the digital portion of the device

being coupled into the analog portion of the device. The

two grounds are connected internally through the sub-

strate which has a resistance of 5 -10 Ω.

If no ground plane is utilized, then both grounds must

be connected to V_SSon the board. If a ground plane is

available, both digital and analog ground pins should

be connected to the analog ground plane. If both an

analog and a digital ground plane are available, both

the digital and the analog ground pins should be con-

nected to the analog ground plane, as shown in

Figure 6-11. Following these steps will reduce the

amount of digital noise from the rest of the board being

coupled into the A/D Converter.

V

DD

MCP3302/04

Analog Side

Digital Side

-Sample Cap

-Capacitor Array

-Comparator

-SPI Interface

-Shift Register

-Control Logic

Substrate

5 - 10

Ω

DGND

AGND

0.1 µF

Analog Ground Plane

FIGURE 6-11:

Separation of Analog and

Digital Ground Pins.

DS21697C-page 21

MCP3302/04

TABLE 7-1:

BINARY TWO’S

COMPLEMENT OUTPUT

CODE EXAMPLES.

7.0

7.1

SERIAL COMMUNICATIONS

Output Code Format

Sign

Bit

Decimal

DATA

The output code format is a binary two’s complement

scheme, with a leading sign bit that indicates the sign

of the output. If the IN+ input is higher than the IN-

input, the sign bit will be a zero. If the IN- input is higher,

the sign bit will be a ‘1’.

Analog Input Levels

Binary Data

Full Scale Positive

(IN+)-(IN-)=V_REF-1 LSB

0

1

1111 1111 1111

1111 1111 1110

0000 0000 0010

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

0000 0000 0001

+4095

+4094

+2

(IN+)-(IN-) = V_REF-2 LSB

IN+ = (IN-) +2 LSB

IN+ = (IN-) +1 LSB

IN+ = IN-

The diagram shown in Figure 7-1 shows the output

code transfer function. In this diagram, the horizontal

axis is the analog input voltage and the vertical axis is

the output code of the ADC. It shows that when IN+ is

equal to IN-, both the sign bit and the data word is zero.

As IN+ gets larger with respect to IN-, the sign bit is a

zero and the data word gets larger. The full scale output

code is reached at +4095 when the input [(IN+) - (IN-)]

reaches V_REF- 1 LSB. When IN- is larger than IN+, the

two’s complement output codes will be seen with the

sign bit being a one. Some examples of analog input

levels and corresponding output codes are shown in

Table 7-1.

+1

0

IN+ = (IN-) - 1 LSB

IN+ = (IN-) - 2 LSB

(IN+)-(IN-) = V_REF-2 LSB

-1

-2

-4095

Full Scale Negative

(IN+)-(IN-) = V_REF-1 LSB

1

0000 0000 0000

-4096

Output

Code

Positive Full

Scale Output = V_REF-1 LSB

0 + 1111 1111 1111 (+4095)

0 + 1111 1111 1110 (+4094)

0 + 0000 0000 0011 (+3)

0 + 0000 0000 0010 (+2)

0 + 0000 0000 0001 (+1)

Analog Input

IN+ > IN-

0 + 0000 0000 0000 (0)

Voltage

IN+ - IN-

IN+ < IN-

1 + 1111 1111 1111 (-1)

1 + 1111 1111 1110 (-2)

-V_REF

V_REF

1 + 1111 1111 1101 (-3)

1 + 0000 0000 0001 (-4095)

1 + 0000 0000 0000 (-4096)

Negative Full

Scale Output = -V_REF

FIGURE 7-1:

Output Code Transfer Function.

DS21697C-page 22

MCP3302/04

TABLE 7-2:

CONFIGURATION BITS FOR

THE MCP3302

7.2

Communicating with the MCP3302

and MCP3304

Control Bit

Selections

Communication with the MCP3302/04 devices is done

using a standard SPI-compatible serial interface. Initi-

ating communication with either device is done by

bringing the CS line low (see Figure 7-2). If the device

was powered up with the CS pin low, it must be brought

high and back low to initiate communication. The first

clock received with CS low and D_INhigh will constitute

a start bit. The SGL/DIFF bit follows the start bit and will

determine if the conversion will be done using single

ended or differential input mode. Each channel in

single ended mode will operate as a 12-bit converter

with a unipolar output. No negative codes will be output

in single ended mode. The next three bits (D0, D1 and

D2) are used to select the input channel configuration.

Table 7-2 and Table 7-3 show the configuration bits for

the MCP3302 and MCP3304, respectively. The device

will begin to sample the analog input on the fourth rising

edge of the clock after the start bit has been received.

The sample period will end on the falling edge of the

fifth clock following the start bit.

Input

Channel

Configuration Selection

Single

D2* D1 D0

/Diff

1

0

X

0

1

0

1

0

1

0

single ended

differential

CH0

CH1

CH2

CH3

CH0 = IN+

CH1 = IN-

0

X

0

1

0

1

differential

CH0 = IN-

CH1 = IN+

CH2 = IN+

CH3 = IN-

CH2 = IN-

CH3 = IN+

*D2 is don’t care for MCP3302

After the D0 bit is input, one more clock is required to

complete the sample and hold period (D_INis a “don’t

care” for this clock). On the falling edge of the next

clock, the device will output a low null bit. The next 13

clocks will output the result of the conversion with the

sign bit first, followed by the 12 remaining data bits, as

shown in Figure 7-2. Note that if the device is operating

in the single ended mode, the sign bit will always be

transmitted as a ‘0’. Data is always output from the

device on the falling edge of the clock. If all 13 data bits

have been transmitted, and the device continues to

receive clocks while the CS is held low, the device will

output the conversion result, LSB, first, as shown in

Figure 7-3. If more clocks are provided to the device

while CS is still low (after the LSB first data has been

transmitted), the device will clock out zeros indefinitely.

TABLE 7-3:

CONFIGURATION BITS FOR

THE MCP3304

Control Bit

Selections

Input

Channel

Configuration Selection

SinglE

/Diff

D2 D1 D0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

single ended

differential

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

If necessary, it is possible to bring CS low and clock in

leading zeros on the D_INline before the start bit. This is

often done when dealing with microcontroller-based

SPI ports that must send 8 bits at a time. Refer to

Section 7.3 for more details on using the MCP3302/04

devices with hardware SPI ports

CH0 = IN+

CH1 = IN-

0

1

0

1

0

1

0

1

0

1

0

1

differential

CH0 = IN-

CH1 = IN+

CH2 = IN+

CH3 = IN-

CH2 = IN-

CH3 = IN+

CH4 = IN+

CH5 = IN-

CH4 = IN-

CH5 = IN+

CH6 = IN+

CH7 = IN-

CH6 = IN-

CH7 = IN+

DS21697C-page 23

MCP3302/04

T

SAMPLE

T

SAMPLE

T

CSH

CS

T

SUCS

CLK

SGL/

DIFF

SGL/

DIFF

Don’t Care

Start

D2 D1 D0

D2

D

IN

HI-Z

Null

Bit

SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 *

OUT

T

CONV

T

ACQ

T

**

DATA

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB

first data, followed by zeros indefinitely. See Figure 7-3 below.

** T_DATA: during this time, the bias current and the comparator power down while the reference input becomes

a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros.

^†When operating in single ended mode, the sign bit will always be transmitted as a ‘0’.

FIGURE 7-2:

Communication with MCP3302/04 (MSB first Format).

T

SAMPLE

T

CSH

CS

T

SUCS

Power Down

CLK

Start

D

D2 D1 D0

Don’t Care

IN

SGL/

DIFF

HI-Z

Null

Bit

HI-Z

SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 SB*

D

OUT

(MSB)

T

**

DATA

T

CONV

ACQ

* After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros

indefinitely.

** T_DATA: During this time, the bias circuit and the comparator power down while the reference input becomes

a high impedance node, leaving the CLK running to clock out LSB first data or zeroes.

^†When operating in single ended mode, the sign bit will always be transmitted as a ‘0’.

FIGURE 7-3:

Communication with MCP3302/04 (LSB first Format).

DS21697C-page 24

MCP3302/04

7.3

Using the MCP3302/04 with

Microcontroller (MCU) SPI Ports

With most microcontroller SPI ports, it is required to

send groups of eight bits. It is also required that the

microcontroller SPI port be configured to clock out data

on the falling edge of clock and latch data in on the ris-

ing edge. Because communication with the MCP3302

and MCP3304 devices may not need multiples of eight

clocks, it will be necessary to provide more clocks than

are required. This is usually done by sending ‘leading

zeros’ before the start bit. For example, Figure 7-4 and

Figure 7-5 show how the MCP3302/04 devices can be

interfaced to a MCU with a hardware SPI port.

Figure 7-4 depicts the operation shown in SPI Mode

0,0, which requires that the SCLK from the MCU idles

in the ‘low’ state, while Figure 7-5 shows the similar

case of SPI Mode 1,1, where the clock idles in the ‘high’

state.

As shown in Figure 7-4, the first byte transmitted to the

A/D Converter contains 6 leading zeros before the start

bit. Arranging the leading zeros this way produces the

13 data bits to fall in positions easily manipulated by the

MCU. The sign bit is clocked out of the A/D Converter

on the falling edge of clock number 11, followed by the

remaining data bits (MSB first). After the second eight

clocks have been sent to the device, the MCU receive

buffer will contain 2 unknown bits (the output is at high

impedance for the first two clocks), the null bit, the sign

bit and the 4 highest order bits of the conversion. After

the third byte has been sent to the device, the receive

register will contain the lowest order eight bits of the

conversion results. Easier manipulation of the con-

verted data can be obtained by using this method.

Figure 7-5 shows the same situation in SPI Mode 1,1,

which requires that the clock idles in the high state. As

with mode 0,0, the A/D Converter outputs data on the

falling edge of the clock and the MCU latches data from

the A/D Converter in on the rising edge of the clock.

DS21697C-page 25

MCP3302/04

CS

MCU latches data from A/D Converter

on rising edges of SCLK

SCLK

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

17 18 19 20 21 22 23 24

Data is clocked out of

A/D Converter on falling edges

SGL/

D1

Start

D2

D0

Don’t Care

D

DIFF

IN

HI-Z

NULL

SB B11 B10 B9 B8

BIT

B7

B6 B5 B4 B3 B2 B1 B0

D

OUT

Start

Bit

MCU Transmitted Data

(Aligned with falling

edge of clock)

SGL/

DIFF

0

1

D2 D1

DO

X

MCU Received Data

(Aligned with rising

edge of clock)

0

?

SB B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

(Null)

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

Data stored into MCU receive register

after transmission of last 8 bits

? = Unknown Bits

X = Don’t Care Bits

FIGURE 7-4:

SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK

idles low).

MCU latches data from A/D Converter

on rising edges of SCLK

CS

4

9

1

2

3

5

6

7

8

10 11 12 13 14 15

16

17 18 19 20 21 22 23

24

SCLK

Data is clocked out of

A/D Converter on falling edges

SGL/

DIFF

DDoonn’t’tCCaarere

Start

D2

D1

D0

D

IN

HI-Z

NULL

SB B11 B10 B9

BIT

B8

B7 B6 B5 B4 B3 B2 B1 B0

D

OUT

Start

Bit

SGL/

DIFF

MCU Transmitted Data

(Aligned with falling

edge of clock)

0

1

D2 D1

?

DO

X

MCU Received Data

(Aligned with rising

edge of clock)

0

?

SB B11 B10 B9 B8

B7 B6 B5 B4 B3 B2 B1 B0

(Null)

Data stored into MCU receive register

after transmission of first 8 bits

Data stored into MCU receive register

after transmission of second 8 bits

Data stored into MCU receive register

after transmission of last 8 bits

? = Unknown Bits

X = Don’t Care Bits

FIGURE 7-5:

SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK

idles high).

DS21697C-page 26

MCP3302/04

8.0

8.1

PACKAGING INFORMATION

Package Marking Information

14-Lead PDIP (300 mil)

Example:

XXXXXXXXXXXXXX

MCP3302-B

I/P

e3

YYWWNNN

0725NNN

14-Lead SOIC (150 mil)

Example:

e

3

MCP3302-B

XXXXXXXXXXX

YYWWNNN

0725NNN

14-Lead TSSOP (4.4mm)

Example:

XXXXXXXX

YYWW

3302-C

e3

0725

NNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21697C-page 27

MCP3302/04

8.2

Package Marking Information (Continued)

16-Lead PDIP (300 mil) (MCP3304)

Example:

e

3

XXXXXXXXXXXXXX

MCP3304-B

I/P

YYWWNNN

0725NNN

16-Lead SOIC (150 mil) (MCP3304)

Example:

e

3

MCP3304-B

XXXXXXXXXXXXX

XXXXXXXXXX

YYWWNNN

0725NNN

DS21697C-page 28

MCP3302/04

14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

Units

INCHES

NOM

14

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.750

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located with the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-005B

DS21697C-page 29

MCP3302/04

14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

3

e

h

b

α

h

c

φ

A2

A

L

A1

β

L1

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff §

A2

A1

E

1.25

0.10

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

E1

D

h

3.90 BSC

8.65 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-065B

DS21697C-page 30

MCP3302/04

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

1

2

e

b

c

φ

A2

A

A1

L

L1

Units

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

14

0.65 BSC

Overall Height

Molded Package Thickness

Standoff

A

–

1.20

1.05

0.15

A2

A1

E

0.80

0.05

1.00

–

Overall Width

Molded Package Width

Molded Package Length

Foot Length

6.40 BSC

E1

D

4.30

4.90

0.45

4.40

4.50

5.10

0.75

5.00

L

0.60

Footprint

L1

φ

1.00 REF

Foot Angle

0°

–

8°

Lead Thickness

Lead Width

c

0.09

0.19

0.20

0.30

b

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-087B

DS21697C-page 31

MCP3302/04

16-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

N

NOTE 1

E1

1

2

3

D

E

A

A2

L

c

A1

b1

e

eB

b

Units

INCHES

NOM

16

Dimension Limits

MIN

MAX

Number of Pins

Pitch

N

e

.100 BSC

–

Top to Seating Plane

A

–

.210

.195

–

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.290

.240

.735

.115

.008

.045

.014

–

.130

–

.310

.250

.755

.130

.010

.060

.018

–

.325

.280

.775

.150

.015

.070

.022

.430

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

b1

b

Lower Lead Width

Overall Row Spacing §

eB

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

Microchip Technology Drawing C04-017B

DS21697C-page 32

MCP3302/04

16-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

3

1

2

e

b

h

α

h

c

φ

A2

A

L

β

A1

L1

Units

MILLMETERS

Dimension Limits

MIN

NOM

MAX

Number of Pins

Pitch

N

e

16

1.27 BSC

Overall Height

A

–

1.75

–

Molded Package Thickness

Standoff §

A2

A1

E

1.25

0.10

–

0.25

Overall Width

6.00 BSC

Molded Package Width

Overall Length

E1

D

h

3.90 BSC

9.90 BSC

Chamfer (optional)

Foot Length

0.25

0.40

–

0.50

1.27

L

–

Footprint

L1

φ

1.04 REF

Foot Angle

0°

0.17

0.31

5°

–

8°

Lead Thickness

Lead Width

c

0.25

0.51

15°

b

Mold Draft Angle Top

Mold Draft Angle Bottom

α

β

5°

15°

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. § Significant Characteristic.

3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.

4. Dimensioning and tolerancing per ASME Y14.5M.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-108B

DS21697C-page 33

MCP3302/04

NOTES:

DS21697C-page 34

MCP3302/04

APPENDIX A: REVISION HISTORY

Revision C (January 2007)

This revision includes updates to the packaging

diagrams.

DS21697C-page 35

MCP3302/04

NOTES:

DS21697C-page 36

MCP3302/04

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PART NO.

Device

X

/XX

Examples:

a)

b)

c)

MCP3302-BI/P: ±1 LSB INL, Industrial Tem-

perature, PDIP package

Grade Temperature Package

Range

MCP3302-BI/SL: ±1 LSB INL, Industrial

Temperature, SOIC package

Device:

MCP3302: 13-Bit Serial A/D Converter

MCP3302T: 13-Bit Serial A/D Converter (Tape and Reel)

MCP3304: 13-Bit Serial A/D Converter

MCP3302-CI/ST: ±2 LSB INL, Industrial

Temperature, TSSOP package

MCP3304T: 13-Bit Serial A/D Converter (Tape and Reel)

a)

b)

MCP3304-BI/P: ±1 LSB INL, Industrial

Temperature, PDIP package

Grade:

B

C

=

±1 LSB INL

±2 LSB INL

MCP3304-BI/SL: ±1 LSB INL, Industrial

Temperature, SOIC package

Temperature Range:

Package:

I

=

-40°C to +85°C

P

SL

ST

=

Plastic DIP (300 mil Body), 14-lead, 16-lead

Plastic SOIC (150 mil Body), 14-lead, 16-lead

Plastic TSSOP (4.4mm), 14-lead

DS21697C-page37

MCP3302/04

NOTES:

DS21697C-page 38

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

MCUs and dsPIC DSCs, KEELOQ^®code hopping devices, Serial

EEPROMs, microperipherals, nonvolatile memory and analog

products. In addition, Microchip’s quality system for the design and

manufacture of development systems is ISO 9001:2000 certified.

DS21697C-page 39

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21697C-page 40


型号：	MCP3302T-BI/ST
厂家：	MICROCHIP
描述：	13-Bit Differential Input, Low Power A/D Converter with SPI⑩ Serial Interface 13位差分输入，低功耗A / D转换器SPI⑩串行接口转换器
文件：	总40页 (文件大小：747K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP3302T-BI/ST [MICROCHIP]

相关型号：

MCP3302T-CI/P

MCP3302T-CI/SL

MCP3302T-CI/ST

MCP3302T-I/P

MCP3302T-I/SL

MCP3302T-I/ST

MCP3302TI/P

MCP3302TI/SL

MCP3302TI/ST

MCP3302_07

MCP3302_08

MCP3302_11