MCP33111-05-E/MS [MICROCHIP]
ADC, Successive Approximation;
| 型号： | MCP33111-05-E/MS |
| 厂家： | 
MICROCHIP |
| 描述： | ADC, Successive Approximation 光电二极管 转换器 |
| 文件： | 总54页 (文件大小：2643K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP33131/21/11-XX
1 Msps/500 kSPS 16/14/12-Bit Single-Ended Input SAR ADC
Features
Typical Applications
• Sample Rate (Throughput):
• High-Precision Data Acquisition
• Medical Instruments
- MCP33131/21/11-10: 1 Msps
- MCP33131/21/11-05: 500 kSPS
• Test Equipment
• 16/14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Wide Operating Voltage Range:
- Analog Supply Voltage (AVDD): 1.8V
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
- Digital Input/Output Interface Voltage (DVIO):
1.7V - 5.5V
System Design Supports
- External Reference (VREF): 2.5V - 5.1V
The MCP331x1-XX Evaluation Kit demonstrates the
performance of the MCP331x1-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1-XX
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
• Pseudo-Differential Input Operation with
Single-Ended Configuration:
- Input Full-Scale Range: 0V to +VREF
• Ultra Low Current Consumption (typical):
- During Input Acquisition (Standby): ~ 0.8 µA
- During Conversion:
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 MCU firmware example codes.
MCP331x1-10: ~1.6 mA
MCP331x1-05: ~1.4 mA
Package Types
VREF
AVDD
AIN+
1
2
3
10 DVIO
9 SDI
• SPI-Compatible Serial Communication:
- SCLK Clock Rate: up to 100 MHz
MSOP-10
Top View
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
8 SCLK
AIN- 4
SDO
7
- During Power-Up (automatic)
GND
5
6 CNVST
- On-Demand via user’s command during
normal operation
VREF
AVDD
DV
IO
1
2
10
• AEC-Q100 Qualified:
Top View
TDFN-10
SDI
9
8
7
6
- Temperature Grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
AIN+
AIN-
SCLK
3
4
5
SDO
CNVST
GND
MCP331x1-XX Device Offering (Note 1):
Performance (Typical)
Sample
Rate
Input Range
Part Number Resolution
Input Type
SNR
(dBFS)
SFDR
THD
(dB)
INL
DNL
(dB)
(LSB)
(LSB)
MCP33131-10
MCP33121-10
MCP33111-10
MCP33131-05
MCP33121-05
MCP33111-05
16-bit
14-bit
12-bit
16-bit
14-bit
12-bit
1 Msps
1 Msps
1 Msps
Single-Ended
Single-Ended
Single-Ended
0V to 5.1V
0V to 5.1V
0V to 5.1V
0V to 5.1V
0V to 5.1V
0V to 5.1V
86.7
83.5
73.8
86.7
83.5
73.8
98.9
98.8
95.9
98.9
98.8
95.9
-97.4
-97.2
-93.7
-97.4
-97.2
-93.7
±2.2
±0.55
±0.12
±2.2
±0.9
±0.25
±0.06
±0.9
500 kSPS Single-Ended
500 kSPS Single-Ended
500 kSPS Single-Ended
±0.55
±0.12
±0.25
±0.06
Note 1:
SNR, SFDR, and THD are measured with fIN = 10 kHz, VIN = -1 dBFS, VREF = 5.1V.
2018 Microchip Technology Inc.
DS20006122A-page 1
MCP33131/21/11-XX
Application Diagram
2.5V to 5.1V 1.8V 1.7V to 5.5V
VREF AVDD DVIO
22Ω
AIN
MCP331x1-XX
AIN
+
Analog Input
1.7 nF
(0V to VREF
)
SDI
CNVST
SCLK
Host Device
(PIC32MZ)
-
SDO
Ground Reference of
Analog Input
GND
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes less than 1 µA during
Standby. A new conversion is started on the rising edge
of CNVST. When the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO, and the device enters Standby to begin acquiring
the next input sample. The user can clock out the ADC
output data using the SPI-compatible serial clock
during Standby.
Description
The MCP33131/MCP33121/MCP33111-10 and
MCP33131/MCP33121/MCP33111-05 are
single-ended 16, 14, and 12-bit, single-channel 1 Msps
and 500 kSPS ADC family devices, respectively,
featuring low power consumption and high
performance, using
register (SAR) architecture.
a
successive approximation
The device operates with a 2.5V to 5.1V external
reference (VREF), which supports a wide range of input
full-scale range from 0V to VREF. The reference voltage
setting is independent of the analog supply voltage
(AVDD) and is higher than AVDD. The conversion output
is available through an easy-to-use simple SPI-
compatible 3-wire interface.
The ADC system clock is generated by an internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7V - 5.5V) allows the device to
interface with most host devices (Master) available in
the current industry such as the PIC32
microcontrollers, without using external voltage level
shifters.
The device is AEC-Q100 qualified for automotive
applications and operates over the extended
temperature range of -40°C to +125°C. The available
package options are Pb-free TDFN-10 and MSOP-10.
When the device is first powered-up, it performs a
self-calibration to minimize offset, gain and linearity
errors. The device performance stays stable across the
specified temperature range. However, when extreme
changes in the operating environment, such as in the
reference voltage, are made with respect to the initial
conditions (e.g. the reference voltage was not fully
settled during the initial power-up sequence), the user
may send a recalibrate command anytime to initiate
another
self-calibration
to
restore
optimum
performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode,
where sampling capacitors are connected to the input
pins. This mode is called Standby.
DS20006122A-page 2
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
†Notice: Stresses above those listed under “Absolute
1.0
1.1
KEY ELECTRICAL
CHARACTERISTICS
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
Absolute Maximum Ratings†
External Analog Supply Voltage (AV ) ................... -0.3V to 2.0V
DD
External Digital Supply Voltage (DV ) ..................... -0.3V to 5.8V
IO
External Reference Voltage (V
) .......................... -0.3V to 5.8V
REF
Analog Inputs w.r.t GND .............................. –0.3V to V
+0.3V
REF
Current at Input Pins ...........................................................±2 mA
Current at Output and Supply Pins .................................±250 mA
Storage Temperature...........................................-65°C to +150°C
Maximum Junction Temperature (T ) ................................+150°C
J
ESD protection on all pins.... ≤2kV HBM, ≤2kV CDM, ≤200V MM
1.2
Electrical Specifications
KEY ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.
•
•
MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Power Supply Requirements
Analog Supply Voltage Range
AVDD
DVIO
1.7
1.7
1.8
—
1.9
5.5
V
V
(Note 3)
(Note 3)
Digital Input/Output Interface Voltage
Range
Analog Supply Current at AVDD pin:
During Conversion
IDDAN
—
—
—
1.6
1.4
0.8
2.4
2.0
—
mA
mA
µA
f
f
s = 1 Msps (MCP331x1-10)
s = 500 kSPS (MCP331x1-05)
During Standby
IDDAN_STBY
During input acquisition (tACQ)
Digital Supply Current At DVDD pin:
During Output Data Reading
IIO_DATA
IIO_STBY
—
—
—
290
200
30
—
—
—
A
A
nA
f
f
s = 1 Msps (MCP331x1-10)
s = 500 kSPS (MCP331x1-05)
During Standby
During input acquisition (tACQ)
External Reference Voltage Input
Reference Voltage
(Note 2), (Note 3)
VREF
2.5
2.7
5.1
5.1
V
-40°C ≤ TA ≤ 85°C
85°C < TA ≤ 125°C
Reference Load Current at VREF pin:
During Conversion
IREF
—
—
450
220
240
600
360
—
µA
µA
nA
f
f
s = 1 Msps (MCP331x1-10)
s = 500 kSPS (MCP331x1-05)
During Standby
IREF_STBY
During input acquisition (tACQ)
Total Power Consumption (Including AV , DV , V
pins)
DD
IO
REF
MCP331x1-10
at 1 Msps
at 500 ksps
at 100 ksps
During Standby
PDISS_TOTAL
—
—
—
—
6.2
3.1
0.6
2.6
—
—
—
—
mW
mW
mW
W
Averaged power for tACQ + tCNV
PDISS_STBY
During input acquisition (tACQ)
MCP331x1-05
at 500 ksps
at 100 ksps
During Standby
PDISS_TOTAL
PDISS_STBY
—
—
—
4.2
0.8
2.6
—
—
—
mW
mW
W
Averaged power for tACQ + tCNV
During input acquisition (tACQ
)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc.
DS20006122A-page 3
MCP33131/MCP33121/MCP33111-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.
•
•
MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Analog Inputs
Input Voltage Range
VIN+
FSR
-0.1
0
—
—
VREF+0.1
V
VPP
pF
(Note 2)
(Note 2)
(Note 1)
(Note 1)
Input Full-Scale Voltage Range
Input Sampling Capacitance
-3dB Input Bandwidth
+VREF
—
CS
—
—
—
31
25
2.5
BW-3dB
—
MHz
ns
Aperture Delay
(Note 1)
—
Time delay between CNVST rising
edge and when input is sampled
Leakage Current at Analog Input Pin ILEAK_AN_INPUT
—
±2
±200
nA
During input acquisition (tACQ)
System Performance
Sample Rate
(Throughput rate)
fs
—
—
—
—
1
500
—
Msps
kSPS
Bits
MCP331x1-10
MCP331x1-05
Resolution
(No Missing Codes)
16
14
12
-6
—
MCP33131-10 and MCP33131-05
MCP33121-10 and MCP33121-05
MCP33111-10 and MCP33111-05
MCP33131-10 and MCP33131-05
MCP33121-10 and MCP33121-05
MCP33111-10 and MCP33111-05
MCP33131-10 and MCP33131-05
MCP33121-10 and MCP33121-05
MCP33111-10 and MCP33111-05
MCP33131-10 and MCP33131-05
MCP33121-10 and MCP33121-05
MCP33111-10 and MCP33111-05
—
—
Bits
—
—
Bits
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
±2.2
±0.55
±0.12
±0.9
±0.25
±0.06
±0.1
±0.125
±0.8
±0.8
±4
+6
LSB
LSB
LSB
LSB
LSB
LSB
mV
-1.5
+1.5
DNL
-0.98
-0.8
+1.8
+0.8
+0.3
±2.3
±3
-0.3
—
—
—
—
—
—
—
—
mV
±3.66
—
mV
Offset Error Drift with Temperature
Gain Error
V/oC
LSB
LSB
LSB
V/oC
dB
GER
—
MCP33131-10 and MCP33131-05
MCP33121-10 and MCP33121-05
MCP33111-10 and MCP33111-05
±1
—
±0.2
±0.35
84
—
Gain Error Drift with temperature
—
Input Common-Mode
Rejection Ratio
CMRR
PSRR
—
Power Supply Rejection Ratio
—
60
—
dB
(Note 4)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
DS20006122A-page 4
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.
•
•
MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Dynamic Performance
Signal-to-Noise Ratio
SNR
MCP33131-10 and MCP33131-05: 16-bit ADC
—
—
86.8
80.9
86.7
80.9
—
—
—
—
dBFS
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
83.5
—
MCP33121-10 and MCP33121-05: 14-bit ADC
—
—
83.6
79.8
83.5
79.8
—
—
—
—
dBFS
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
81.5
—
MCP33111-10 and MCP33111-05: 12-bit ADC
—
—
73.8
73.2
73.8
73.2
—
—
—
—
dBFS
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
71.1
—
Signal-to-Noise and Distortion Ratio
SINAD
MCP33131-10 and MCP33131-05: 16-bit ADC
(Note 5)
—
—
—
—
86.9
80.9
86.6
80
—
—
—
—
dBFS
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
—
—
—
—
83.6
79.8
83.4
79.1
—
—
—
—
dBFS
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
—
—
—
—
73.8
73.2
73.8
73
—
—
—
—
dBFS
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc.
DS20006122A-page 5
MCP33131/MCP33121/MCP33111-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.
•
•
MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Spurious Free Dynamic Range
SFDR
MCP33131-10 and MCP33131-05: 16-bit ADC
—
—
—
—
99.4
94.4
98.9
93.9
—
—
—
—
dBc
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
—
—
—
—
99.3
94.4
98.8
93.9
—
—
—
—
dBc
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
—
—
—
—
97.4
94.2
95.9
93.7
—
—
—
—
dBc
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
Total Harmonic Distortion
(first five harmonics)
THD
MCP33131-10 and MCP33131-05: 16-bit ADC
—
—
—
—
-97.6
-92.5
-97.4
-92.4
—
—
—
—
dBc
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
MCP33121-10 and MCP33121-05: 14-bit ADC
—
—
—
—
-97.4
-92.4
-97.2
-92.3
—
—
—
—
dBc
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
MCP33111-10 and MCP33111-05: 12-bit ADC
—
—
—
—
-94.4
-91.7
-93.7
-91.5
—
—
—
—
dBc
V
V
V
V
REF = 5V, fIN = 1 kHz
REF = 2.5V, fIN = 1 kHz
REF = 5V, fIN = 10 kHz
REF = 2.5V, fIN = 10 kHz
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
DS20006122A-page 6
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
TABLE 1-1:
KEY ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Analog Input (VIN) = -1 dBFS sine wave, fIN = 10 kHz, CLOAD_SDO = 20 pF.
•
•
MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
System Self-Calibration
Self-Calibration Time
tCAL
—
—
500
650
—
ms
(Note 2)
Number of SCLK Clocks for
Recalibrate Command
ReCalNSCLK
1024
clocks
Includes clocks for data bits
Serial Interface Timing Information: See Table 1-2
Digital Inputs/Outputs
High-level Input voltage
Low-level input voltage
VIH
VIL
0.7 * DVIO
0.9 * DVIO
-0.3
—
DVIO + 0.3
DVIO + 0.3
0.3 * DVIO
0.2 * DVIO
—
V
V
V
V
V
V
V
DVIO ≥ 2.3V
—
DVIO < 2.3V
—
DVIO ≥ 2.3V
-0.3
—
0.2 * DVIO
—
DVIO < 2.3V
Hysteresis of Schmitt Trigger Inputs
Low-level output voltage
High-level output voltage
Input leakage current
VHYST
VOL
VOH
ILI
—
All digital inputs
IOL = 500 µA (sink)
IOL = - 500 µA (source)
—
0.2 * DVIO
—
0.8 * DVIO
—
—
—
—
—
±1
±1
µA
µA
CNVST/SDI/SCLK = GND or DVIO
Output leakage current
ILO
Output is high-Z, SDO = GND or
DVIO
Internal capacitance
CINT
—
7
—
pF
TA = 25°C (Note 1)
(all digital inputs and outputs)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 F ceramic capacitor, (b) DVIO pin: 0.1 F ceramic capacitor, (c) VREF pin: 10 F tantalum capacitor.
4: PSRR (dB) = -20 log (DVOUT/AVDD), where DVOUT = change in conversion result.
5: ENOB = (SINAD - 1.76)/6.02
2018 Microchip Technology Inc.
DS20006122A-page 7
MCP33131/MCP33121/MCP33111-XX
TABLE 1-2:
SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V, DVIO = 3.3V, GND = 0V,
Analog Input (AIN) = -1 dBFS sine wave, Resolution = 16-bit (MCP33131-10), fIN = 10 kHz, CLOAD_SDO = 20 pF, +25°C is applied for typical value. All
timings are measured at 50%. See Figure 1-1 for timing diagram.
•
•
MCP331x1-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP331x1-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Serial Clock frequency
SCLK Period
fSCLK
tSCLK
—
10
12
16
3
—
—
—
—
—
—
100
—
MHz
ns
See tSCLK specification
DVIO ≥ 3.3V, fSCLK = 100 MHz (Max)
DVIO ≥ 2.3V, fSCLK = 83.3 MHz (Max)
DVIO ≥ 1.7V, fSCLK = 62.5 MHz (Max)
DVIO ≥ 2.3V
—
ns
—
ns
SCLK Low Time
tSCLK_L
tSCLK_H
tDO
—
ns
4.5
—
ns
DVIO ≥ 1.7V
DVIO ≥ 2.3V
DVIO ≥ 1.7V
DVIO ≥ 3.3V
DVIO ≥ 2.3V
DVIO ≥ 1.7V
(Note 2)
SCLK High Time
3
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
4.5
—
—
—
10
Output Valid from SCLK Low
9.5
12
16
—
Quiet time
tQUIET
3-Wire Operation:
SDI Valid Setup time
CNVST Pulse Width High Time
Output Enable Time
tSU_SDIH_CNV
tCNVH
5
—
—
—
—
—
—
—
10
15
15
ns
ns
ns
ns
ns
SDI High to CNVST Rising Edge
10
—
—
—
tEN
DVIO ≥ 2.3V
DVIO ≥ 1.7V
(Note 2)
Output Disable Time
MCP331x1-10
tDIS
Sample Rate
fs
—
—
1
Msps Throughput rate
Input Acquisition Time
(Note 2)
tACQ
290
250
300
—
—
ns
ns
µs
-40°C ≤ TA ≤ 85°C
85°C < TA ≤ 125°C
Data Conversion Time
tCNV
tCYC
—
—
700
—
710
750
-40°C ≤ TA ≤ 85°C
85°C < TA ≤ 125°C
Time between Conversions
MCP331x1-05
1
—
tCYC = tACQ + tCNV, fS = 1 Msps
Sample Rate
fs
—
700
—
—
800
1200
—
500
—
kSPS Throughput rate
Input Acquisition Time (Note 2)
Data Conversion Time
Time between Conversions
tACQ
tCNV
tCYC
ns
ns
µs
-40°C ≤ TA ≤ 125°C
1300
—
-40°C ≤ TA ≤ 125°C
2
tCYC = tACQ + tCNV, fS = 500 kSPS
Note 1:
2:
This parameter is ensured by design and not 100% tested.
This parameter is ensured by characterization and not 100% tested.
TABLE 1-3:
TEMPERATURE CHARACTERISTICS
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistance
Thermal Resistance, MSOP-10
Thermal Resistance, TDFN-10
TA
TA
-40
-65
—
—
+125
+150
°C
°C
(Note 1)
(Note 1)
JA
JA
—
—
202
68
—
—
°C/W
°C/W
Note 1:
The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC.
DS20006122A-page 8
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
t
= 1/f
CYC
S
SDI = “High”
tCNVH
tSU_SDIH_CNV
CNVST
tSCLK
(Note 1)
1
n
3
n-1
2
SCLK
tDO
tQUIET
tSCLK_L
tSCLK_H
tDIS
Hi-Z
Dn-1
(MSB)
Hi-Z
SDO
D1
D0
Dn-2
Dn-3
tCNV (MAX)
tEN
(Note 2)
(Note 3)
tEN
ADC State
Input Acquisition
Conversion
Input Acquisition
(tACQ
)
(tCNV
)
(tACQ
)
Note 1: n = 16 for 16-bit, 14 for 14-bit device, and 12 for 12-bit device.
2: tEN when CNVST is lowered after tCNV (MAX).
3: tEN when CNVST is lowered before tCNV (MAX).
FIGURE 1-1:
Interface Timing Diagram. CNVST is used as chip select. See Figure 7-2 for More
Details.
2018 Microchip Technology Inc.
DS20006122A-page 9
MCP33131/MCP33121/MCP33111-XX
NOTES:
DS20006122A-page 10
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
2.0
TYPICAL PERFORMANCE CURVES FOR 16-BIT DEVICES (MCP33131-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
2
1
4
V
= 5V
V
= 2.5V
REF
REF
2
0
0
-1
-2
-4
-2
0
16,384
32,768
Code
49,152
65,536
0
16,384
32,768
Code
49,152
65,536
FIGURE 2-1:
INL vs. Output Code.
FIGURE 2-4:
INL vs. Output Code.
2
1.5
1
2
1.5
1
V
= 5V
V
= 2.5V
REF
REF
0.5
0
0.5
0
-0.5
-0.5
-1
0
-1
0
16,384
32,768
Code
49,152
65,536
16,384
32,768
Code
49,152
65,536
FIGURE 2-2:
DNL vs. Output Code.
FIGURE 2-5:
DNL vs. Output Code.
3
2
1.5
1
Max INL (LSB)
Max DNL (LSB)
1
0.5
0
0
V
= 5V
REF
V
= 5V
REF
-1
-2
Min INL (LSB)
-0.5
Min DNL (LSB)
-3
-1
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-3:
INL vs. Temperature.
FIGURE 2-6:
DNL vs. Temperature.
2018 Microchip Technology Inc.
DS20006122A-page 11
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
2
8
6
Max DNL (LSB)
1.5
Max INL (LSB)
4
1
2
0.5
0
-2
-4
-6
0
Min INL (LSB)
-0.5
-1
Min DNL (LSB)
-8
2
2
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 2-7:
INL vs. Reference Voltage.
FIGURE 2-10:
DNL vs. Reference Voltage.
MCP33131-10
MCP33131-10
0
0
V
= 2.5V
V
= 5V
REF
REF
-20
-40
f = 1 Msps
s
-20
-40
f = 1 Msps
s
SNR = 81.7 dBFS
SINAD = 81.6 dBFS
SFDR = 98.0 dBc
THD = -95.8 dBc
Resolution = 16-bit
SNR = 86.7 dBFS
SINAD = 86.6 dBFS
SFDR = 103.6 dBc
THD = -101.4 dBc
Resolution = 16-bit
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 2-11:
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
FFT for 10 kHz Input Signal:
FIGURE 2-8:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
FFT for 10 kHz Input Signal:
MCP33131-05
MCP33131-05
0
0
V
= 2.5V
V
= 5V
REF
REF
-20
-40
f = 0.5 Msps
s
-20
-40
f = 0.5 Msps
s
SNR = 81.8 dBFS
SINAD = 81.7 dBFS
SFDR = 98.9 dBc
THD = -96.0 dBc
Resolution = 16-bit
SNR = 86.7 dBFS
SINAD = 86.6 dBFS
SFDR = 105.0 dBc
THD = -101.5 dBc
Resolution = 16-bit
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 2-12:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
FFT for 10 kHz Input Signal:
FIGURE 2-9:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
FFT for 10 kHz Input Signal:
DS20006122A-page 12
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-90
-92
100
98
96
94
92
90
90
88
86
84
82
80
78
76
14
13.5
13
-94
THD (dB)
SFDR (dB)
-96
ENOB
SNR (dB)
SINAD (dB)
12.5
-98
-100
74
2
12
2
2.5
3
3.5
4
4.5
5
5.5
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 2-13:
SNR/SINAD/ENOB vs. V
FIGURE 2-16:
SFDR/THD vs. VREF
REF
84
83
82
81
80
79
78
77
88
87
86
85
V
= 2.5V
V
= 5V
REF
REF
SNR (dB)
SINAD (dB)
SNR (dB)
SINAD (dB)
76
75
74
84
83
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-17:
Temperature: VREF = 2.5V.
SNR/SINAD vs.
FIGURE 2-14:
Temperature: VREF = 5V.
SNR/SINAD vs.
85
84
83
82
81
80
79
78
77
76
90
89
88
87
86
85
84
83
82
81
V
= 2.5V
V
= 5V
REF
REF
SNR (dBFS)
SNR (dBFS)
SINAD(dBFS)
SINAD(dBFS)
75
80
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 2-18:
Amplitude: FIN = 10 kHz.
SNR/SINAD vs. Input
FIGURE 2-15:
Amplitude: FIN = 10 kHz.
SNR/SINAD vs. Input
2018 Microchip Technology Inc.
DS20006122A-page 13
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
90
90
88
86
84
82
80
78
76
74
72
70
V
= 2.5V
V
= 5V
88
86
84
82
80
78
76
74
72
70
REF
REF
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-19:
SNR/SINAD vs.Input
FIGURE 2-22:
SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
Frequency: VIN = -1 dBFS.
-90
100
-92
104
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-91
-92
-93
-94
-95
-96
99
98
97
96
95
94
-94
-96
102
100
98
-98
-100
96
V
= 5V
V
= 2.5V
REF
REF
-102
94
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-20:
THD/SFDR vs.
FIGURE 2-23:
THD/SFDR vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
-75
110
105
100
95
-75
110
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-80
-85
-80
-85
-90
-90
-95
90
-95
90
-100
-105
-110
85
-100
-105
-110
85
80
80
V
= 5V
V
= 2.5V
REF
REF
75
75
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 2-21:
THD/SFDR vs. Input
FIGURE 2-24:
THD/SFDR vs. Input
Frequency: VREF = 5V.
Frequency: VREF = 2.5V.
DS20006122A-page 14
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-60
-65
105
100
95
-60
-65
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-70
-70
-75
90
-75
90
V
= 5V
-80
85
V
= 2.5V
-80
85
REF
REF
-85
80
-85
80
-90
75
-90
75
-95
70
-95
70
-100
-105
65
-100
-105
65
60
60
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 2-25:
THD/SFDR vs. Input
FIGURE 2-28:
THD/SFDR vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 2.5V.
ꢀ105
ꢀ105
10
5
V
= 5V
V
= 2.5V
REF
REF
402464
757379
8
6
4
4
3
2
1
0
2
119771
93862
59995
14132
3224
65
5
143
0
-5 -3 -1
1
3
5
7
9
11 13 15
0
1
2
3
4
5
6
7
8
9
10
Output Code
Output Code
FIGURE 2-26:
Shorted Input Histogram:
FIGURE 2-29:
Shorted Input Histogram:
VREF = 5V.
V
REF = 2.5V.
400
300
200
100
0
10.49
7.86
800
700
600
500
400
300
200
100
0
10.49
9.18
7.86
Offset Error
Gain Error
5.24
2.62
0
Offset Error
Gain Error
6.55
5.24
3.93
2.62
1.31
0
-100
-200
-300
-400
-2.62
-5.24
-7.86
-10.49
-13.11
V
= 2.5V
V
= 5V
REF
REF
-500
-100
-1.31
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 2-27:
Offset and Gain Error vs.
FIGURE 2-30:
Offset and Gain Error vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
2018 Microchip Technology Inc.
DS20006122A-page 15
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33131-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33131-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
76
8
16
12
8
VREF = 5V
6
Total Power Consumption
4
IIO_STBY (DVIO = 3.3V)
2
4
IREF_STBY (VREF = 5V)
0
0
74
10-3
10-2
10-1
Input Frequency (kHz)
100
101
102
103
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-31:
CMRR vs. Input Frequency:
FIGURE 2-34:
Power Consumption vs.
VREF = 5V.
Temperature During Shutdown.
2
8
6
4
2
0
2
8
6
4
MCP331x1-05
MCP331x1-10
1.5
1
1.5
1
Total Power Consumption
= 5V)
0.5
0.5
0
2
(V
I
0
0
0.1
0.2
0.3
0.4
0.5
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
Sample Rate (Msps)
FIGURE 2-32:
Power Consumption vs.
FIGURE 2-35:
Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
Sample Rate: CLOAD_SDO = 20 pF.
2.5
10
8
2
8
6
4
2
0
MCP331x1-10
MCP331x1-05
2
1.5
1
1.5
1
6
4
IREF (VREF = 5V)
0.5
0.5
0
2
IREF (VREF = 5V)
IIO_DATA (DVIO = 3.3V)
IIO_DATA (DVIO = 3.3V)
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-33:
Temperature: CLOAD_SDO = 20 pF.
Power Consumption vs.
FIGURE 2-36:
Temperature: CLOAD_SDO = 20 pF.
Power Consumption vs.
DS20006122A-page 16
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
3.0
TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33121-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
1
0.5
0
1
V
= 5V
V
= 2.5V
REF
REF
0.5
0
-0.5
-0.5
-1
-1
0
4,096
8,192
Code
12,288
16,384
0
4,096
8,192
Code
12,288
16,384
FIGURE 3-1:
INL vs. Output Code.
FIGURE 3-4:
INL vs. Output Code.
1
0.5
0
1
0.5
0
V
= 2.5V
V
= 5V
REF
REF
-0.5
-0.5
-1
0
-1
0
4,096
8,192
Code
12,288
16,384
4,096
8,192
Code
12,288
16,384
FIGURE 3-2:
DNL vs. Output Code.
FIGURE 3-5:
DNL vs. Output Code.
1
0.5
0
1
0.8
0.6
0.4
0.2
0
Max INL (LSB)
Max DNL (LSB)
V
= 5V
V
= 5V
REF
REF
-0.2
-0.4
-0.6
-0.8
Min DNL (LSB)
-0.5
Min INL (LSB)
-1
-1
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 3-3:
INL vs. Temperature.
FIGURE 3-6:
DNL vs. Temperature.
2018 Microchip Technology Inc.
DS20006122A-page 17
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
2
1.5
1
1
Max DNL (LSB)
Max INL (LSB)
Min INL (LSB)
0.5
0
0.5
0
-0.5
-1
-0.5
-1
Min DNL (LSB)
-1.5
-2
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 3-7:
INL vs. Reference Voltage.
FIGURE 3-10:
DNL vs. Reference Voltage.
MCP33121-10
MCP33121-10
0
0
V
= 2.5V
V
= 5V
REF
REF
-20
-40
f = 1 Msps
s
-20
-40
f = 1 Msps
s
SNR = 80.3 dBFS
SINAD = 80.2 dBFS
SFDR = 97.9 dBc
THD = -95.8 dBc
Resolution = 14-bit
SNR = 83.6 dBFS
SINAD = 83.6 dBFS
SFDR = 104.3 dBc
THD = -100.8 dBc
Resolution = 14-bit
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 3-8:
FFT for 10 kHz Input Signal:
FIGURE 3-11:
FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
MCP33121-05
MCP33121-05
0
0
V
= 5V
V
= 2.5V
REF
REF
-20
-40
f = 0.5 Msps
s
-20
-40
f = 0.5 Msps
s
SNR = 83.5 dBFS
SINAD = 83.4 dBFS
SFDR = 105.0 dBc
THD = -101.6 dBc
Resolution = 14-bit
SNR = 80.6 dBFS
SINAD = 80.5 dBFS
SFDR = 99.4 dBc
THD = -96.4 dBc
Resolution = 14-bit
-60
-60
-80
-80
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 3-9:
FFT for 10 kHz Input Signal:
FIGURE 3-12:
FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
DS20006122A-page 18
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
14
-90
-92
100
98
96
94
92
90
13.5
13
-94
THD (dB)
SFDR (dB)
12.5
12
-96
ENOB
SNR (dB)
SINAD (dB)
-98
76
2
11.5
-100
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 3-13:
SNR/SINAD/ENOB vs. V
FIGURE 3-16:
SFDR/THD vs. VREF.
REF.
85
84
83
82
82
81
80
79
78
77
76
75
V
= 5V
V
= 2.5V
REF
REF
SNR (dB)
SINAD (dB)
81
SNR (dB)
SINAD (dB)
74
73
72
80
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 3-17:
SNR/SINAD vs.
FIGURE 3-14:
SNR/SINAD vs.
Temperature: VREF = 2.5V.
Temperature: VREF = 5V.
86
85
84
83
82
81
80
86
85
84
83
82
81
80
V
= 2.5V
V
= 5V
REF
REF
79
78
77
79
78
77
SNR (dBFS)
SNR (dBFS)
SINAD(dBFS)
SINAD(dBFS)
76
76
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-18:
SNR/SINAD vs. Input
FIGURE 3-15:
SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
Amplitude: FIN = 10 kHz.
2018 Microchip Technology Inc.
DS20006122A-page 19
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
90
88
86
84
82
80
78
76
74
72
70
90
V
= 5V
V
= 2.5V
88
86
84
82
80
78
76
74
72
70
REF
REF
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 3-19:
SNR/SINAD vs.Input
FIGURE 3-22:
SNR/SINAD vs.Input
Frequency: VIN = -1 dBFS.
Frequency: VIN = -1 dBFS.
-92
104
-90
100
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-91
-92
-93
-94
-95
-96
99
98
97
96
95
94
-94
-96
102
100
98
-98
-100
96
V
= 5V
V
= 2.5V
REF
REF
-102
94
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
o
Temperature ( C)
FIGURE 3-20:
THD/SFDR vs.
FIGURE 3-23:
THD/SFDR vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
-75
110
105
100
95
-75
110
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-80
-85
-80
-85
-90
-90
-95
90
-95
90
-100
-105
-110
85
-100
-105
-110
85
80
80
V
= 2.5V
V
= 5V
REF
REF
75
75
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 3-21:
THD/SFDR vs. Input
FIGURE 3-24:
THD/SFDR vs. Input
Frequency: VREF = 5V.
Frequency: VREF = 2.5V.
DS20006122A-page 20
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-60
-65
105
100
95
90
85
80
75
70
65
60
-60
-65
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-70
-70
-75
-75
90
V
= 2.5V
V
= 5V
-80
-80
85
REF
REF
-85
-85
80
-90
-90
75
-95
-95
70
-100
-105
-100
-105
65
60
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-25:
THD/SFDR vs. Input
FIGURE 3-28:
THD/SFDR vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 2.5V.
ꢀ105
ꢀ105
12
10
V
= 5V
V
= 2.5V
REF
REF
985144
10
8
8
6
4
719460
6
4
234082
2
2
79234
63284
15798
148
2
0
0
-3
-2
-1
0
1
2
3
4
5
-4 -3 -2 -1
0
1
2
3
4
5
6
Output Code
Output Code
FIGURE 3-26:
Shorted Input Histogram:
FIGURE 3-29:
VREF = 2.5V.
Shorted Input Histogram:
VREF = 5V.
700
600
500
400
300
200
100
2.29
1.97
400
300
200
100
0
2.62
1.97
1.31
1.64
Offset Error
Offset Error
1.31
0.98
0.66
0
Gain Error
Gain Error
0.66
0.33
0
-100
-200
-300
-0.66
-1.31
-1.97
V
= 5V
V
= 2.5V
REF
REF
0
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 3-27:
Offset and Gain Error vs.
FIGURE 3-30:
Offset and Gain Error vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
2018 Microchip Technology Inc.
DS20006122A-page 21
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33121-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33121-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
76
8
16
12
8
VREF = 5V
6
Total Power Consumption
4
IIO_STBY (DVIO = 3.3V)
2
4
IREF_STBY (VREF = 5V)
74
0
0
10-3
10-2
10-1
100
101
102
103
-40 -25 -10
5
20 35 50 65 80 95 110 125
Input Frequency (kHz)
Temperature (°C)
FIGURE 3-31:
CMRR vs. Input Frequency:
FIGURE 3-34:
Temperature During Shutdown.
Power Consumption vs.
VREF = 5V.
2
8
6
4
2
8
6
4
2
0
MCP331x1-10
MCP331x1-05
1.5
1
1.5
1
= 5V)
0.5
0
2
(V
I
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
0.1
0.2
0.3
0.4
0.5
Sample Rate (Msps)
FIGURE 3-32:
Sample Rate: CLOAD_SDO = 20 pF.
Power Consumption vs.
FIGURE 3-35:
Sample Rate: CLOAD_SDO = 20 pF.
Power Consumption vs.
2.5
10
8
2
8
6
4
2
0
MCP331x1-10
MCP331x1-05
2
1.5
1
1.5
1
6
4
IREF (VREF = 5V)
0.5
0
2
0.5
IREF (VREF = 5V)
IIO_DATA (DVIO = 3.3V)
IIO_DATA (DVIO = 3.3V)
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 3-33:
Temperature: CLOAD_SDO = 20 pF.
Power Consumption vs.
FIGURE 3-36:
Power Consumption vs.
DS20006122A-page 22
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
4.0
TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33111-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
0.5
0.3
0.5
V
= 5V
V
= 2.5V
REF
REF
0.3
0.1
0.1
-0.1
-0.3
-0.1
-0.3
-0.5
-0.5
0
1,024
2,048
Code
3,072
4,096
0
1,024
2,048
Code
3,072
4,096
FIGURE 4-1:
INL vs. Output Code.
FIGURE 4-4:
INL vs. Output Code.
0.5
0.3
0.5
0.3
V
= 5V
V
= 2.5V
REF
REF
0.1
0.1
-0.1
-0.3
-0.1
-0.3
-0.5
0
-0.5
0
1,024
2,048
Code
3,072
4,096
1,024
2,048
Code
3,072
4,096
FIGURE 4-2:
DNL vs. Output Code.
FIGURE 4-5:
DNL vs. Output Code.
0.2
0.15
0.1
0.2
0.15
0.1
Max INL (LSB)
Max DNL (LSB)
0.05
0
0.05
0
V
= 5V
V
= 5V
REF
REF
-0.05
-0.1
-0.15
-0.05
-0.1
-0.15
Min DNL (LSB)
Min INL (LSB)
-0.2
-0.2
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-3:
INL vs. Temperature.
FIGURE 4-6:
DNL vs. Temperature.
2018 Microchip Technology Inc.
DS20006122A-page 23
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
0.6
0.4
0.2
0
0.5
Max INL (LSB)
Min INL (LSB)
Max DNL (LSB)
Min DNL (LSB)
0
-0.2
-0.4
-0.6
-0.5
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 4-7:
INL vs. Reference Voltage.
FIGURE 4-10:
DNL vs. Reference Voltage.
MCP33111-10
MCP33111-10
0
0
V
= 5V
V
= 2.5V
REF
REF
f
= 1 Msps
f
= 1 Msps
s
s
-20
-40
-20
-40
SNR = 73.8 dBFS
SINAD = 73.7 dBFS
SFDR = 99.7 dBc
THD = -98.4 dBc
Resolution = 12-bit
SNR = 73.4 dBFS
SINAD = 73.4 dBFS
SFDR = 99.0 dBc
THD = -95.1 dBc
Resolution = 12-bit
-60
-60
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 4-8:
FFT for 10 kHz Input Signal:
FIGURE 4-11:
FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
fS = 1 Msps, VIN = -1 dBFS, VREF = 2.5V.
MCP33111-05
MCP33111-05
0
0
V
= 2.5V
V
= 5V
REF
REF
f
= 0.5 Msps
f
= 0.5 Msps
s
s
-20
-40
-20
-40
SNR = 73.4 dBFS
SINAD = 73.4 dBFS
SFDR = 100.1 dBc
THD = -96.4 dBc
SNR = 73.8 dBFS
SINAD = 73.8 dBFS
SFDR = 99.9 dBc
THD = -97.5 dBc
Resolution = 12-bit
Resolution = 12-bit
-60
-60
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 4-9:
FFT for 10 kHz Input Signal:
FIGURE 4-12:
FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
fS = 500 kSPS, VIN = -1 dBFS, VREF = 2.5V.
DS20006122A-page 24
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
73.5
73
11.9
11.8
11.7
11.6
11.5
-90
-91
-92
-93
-94
-95
100
98
96
94
92
90
THD (dB)
SFDR (dB)
72.5
72
ENOB
SNR (dB)
SINAD (dB)
71.5
2
2.5
3
3.5
4
4.5
5
5.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 4-13:
SNR/SINAD/ENOB vs. V
FIGURE 4-16:
SFDR/THD vs. VREF
REF
73.2
73
74
73.5
73
V
= 5V
REF
V
= 2.5V
REF
72.5
72
72.8
72.6
71.5
71
SNR (dB)
SINAD (dB)
72.4
SNR (dB)
SINAD (dB)
70.5
70
72.2
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-14:
SNR/SINAD vs.
FIGURE 4-17:
SNR/SINAD vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
75
74
73
72
75
74
73
72
V
= 5V
V
= 2.5V
REF
REF
SNR (dBFS)
71
SNR (dBFS)
71
SINAD(dBFS)
SINAD(dBFS)
70
70
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 4-15:
SNR/SINAD vs. Input
FIGURE 4-18:
SNR/SINAD vs. Input
Amplitude: FIN = 10 kHz.
Amplitude: FIN = 10 kHz.
2018 Microchip Technology Inc.
DS20006122A-page 25
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
80
78
76
74
72
70
68
66
64
62
60
80
V
= 5V
V
= 2.5V
78
76
74
72
70
68
66
64
62
60
REF
REF
SNR (dB)
SNR (dB)
SINAD (dB)
SINAD (dB)
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 4-19:
SNR/SINAD vs. Input
FIGURE 4-22:
SNR/SINAD vs. Input
Frequency: VIN = -1 dBFS.
Frequency: VIN = -1 dBFS.
-90
100
-90
100
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-91
-92
-93
-94
-95
-96
99
98
97
96
95
94
-91
-92
-93
-94
-95
-96
99
98
97
96
95
94
V
= 2.5V
V
= 5V
REF
REF
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-20:
THD/SFDR vs.
FIGURE 4-23:
THD/SFDR vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
-75
110
105
100
95
-75
110
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-80
-85
-80
-85
-90
-90
-95
90
-95
90
-100
-105
-110
85
-100
-105
-110
85
80
80
V
= 5V
V
= 2.5V
REF
REF
75
75
100
101
102
103
100
101
102
103
Input Frequency (kHz)
Input Frequency (kHz)
FIGURE 4-21:
THD/SFDR vs. Input
FIGURE 4-24:
THD/SFDR vs. Input
Frequency: VREF = 5V.
Frequency: VREF = 2.5V.
DS20006122A-page 26
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
105
100
95
90
85
80
75
70
65
60
-55
-60
-65
-70
-75
-80
-85
-90
-95
-100
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
90
V
= 5V
V
= 2.5V
REF
85
REF
80
75
70
65
60
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 4-25:
THD/SFDR vs. Input
FIGURE 4-28:
THD/SFDR vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 2.5V.
ꢀ105
ꢀ105
12
12
1048574
V
= 5V
1048576
V
= 2.5V
REF
REF
10
8
10
8
6
6
4
4
2
2
2
0
0
-3
-2
-1
0
1
2
3
-3
-2
-1
0
1
2
3
Output Code
Output Code
FIGURE 4-26:
Shorted Input Histogram:
FIGURE 4-29:
Shorted Input Histogram:
VREF = 5V.
V
REF = 2.5V.
500
400
300
200
100
0
0.41
0.33
300
200
100
0
0.49
0.33
0.16
Gain Error
0.25
0.16
0.08
0
Offset Error
0
Gain Error
-100
-200
-0.16
-0.33
-0.49
Offset Error
V
= 5V
V
= 2.5V
REF
REF
-100
-0.08
-300
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
-40 -20
0
20 40 60 80 100 120 140
Temperature (oC)
FIGURE 4-27:
Offset and Gain Error vs.
FIGURE 4-30:
Offset and Gain Error vs.
Temperature: VREF = 5V.
Temperature: VREF = 2.5V.
2018 Microchip Technology Inc.
DS20006122A-page 27
MCP33131/MCP33121/MCP33111-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33111-10: Sample Rate (fS) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
MCP33111-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
86
84
82
80
78
76
8
16
12
8
VREF = 5V
6
Total Power Consumption
4
IIO_STBY (DVIO = 3.3V)
2
4
IREF_STBY (VREF = 5V)
0
0
74
10-3
10-2
10-1
Input Frequency (kHz)
100
101
102
103
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 4-31:
CMRR vs. Input Frequency:
FIGURE 4-34:
Power Consumption vs.
VREF = 5V.
Temperature During Shutdown.
2
8
6
4
2
0
2
8
6
4
MCP331x1-05
MCP331x1-10
1.5
1
1.5
1
= 5V)
0.5
0
0.5
0
2
(V
I
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
0.1
0.2
0.3
0.4
0.5
Sample Rate (Msps)
FIGURE 4-32:
Power Consumption vs.
FIGURE 4-35:
Power Consumption vs.
Sample Rate: CLOAD_SDO = 20 pF.
Sample Rate: CLOAD_SDO = 20 pF.
MCP331x1D-10
2
8
6
4
2
0
2.5
10
8
MCP331x1-05
MCP331x1-10
2
1.5
1
1.5
1
6
4
IREF (VREF = 5V)
0.5
0.5
0
2
IREF (VREF = 5V)
IIO_DATA (DVIO = 3.3V)
IIO_DATA (DVIO = 3.3V)
0
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 4-33:
Power Consumption vs.
FIGURE 4-36:
Power Consumption vs.
Temperature: CLOAD_SDO = 20 pF.
Temperature: CLOAD_SDO = 20 pF.
DS20006122A-page 28
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
5.0
PIN FUNCTION DESCRIPTIONS
TABLE 5-1:
Pin Number
1
PIN FUNCTION TABLE
Pin Name
Function
VREF
Reference voltage input (2.5V - 5.1V).
This pin should be decoupled with a 10 F tantalum capacitor.
2
AVDD
DC supply voltage input for analog section (1.8V).
This pin should be decoupled with a 1 F ceramic capacitor.
3
4
AIN+
AIN-
Analog input.
Ground reference pin for analog input. Connect this pin to the ground reference of the
analog input.
5
6
GND
Power supply ground reference. This pin is a common ground for both the analog
power supply (AVDD) and digital I/O supply (DVIO).
CNVST
Conversion-start control and active-low SPI chip-select digital input.
A new conversion is started on the rising edge of CNVST.
When the conversion is complete, output data is available at SDO by lowering CNVST.
7
8
SDO
SPI-compatible serial digital data output: ADC conversion data is shifted out by SCLK
clock, with MSB first.
SCLK
SPI-compatible serial data clock digital input.
The ADC output is synchronously shifted out by this clock.
9
SDI
SPI-compatible serial data digital input. Tie to DVIO for normal operation.
10
DVIO
DC supply voltage for digital input/output interface (1.7V - 5.5V).
This pin should be decoupled with a 0.1 F ceramic capacitor.
5.1
Supply Voltages (AV , DV )
DD IO
Note:
Note:
The reference pin needs a tantalum
decoupling capacitor (10 F, 10V rating).
Additional multiple ceramic capacitors can
be added in parallel to decouple
high-frequency noises.
The device has two power supply pins:
(a) Analog power supply (AVDD): 1.8V
(b) Digital input/output interface power supply (DVIO):
1.7V to 5.5V.
The large supply voltage range of DVIO allows the
device to interface with various host devices that are
operating with different supply voltages. See Table 1-2
for timing specifications for I/O interface signal
parameters depending on DVIO voltage.
During the initial power-up sequence, the
reference voltage (VREF
provided prior to supplying AVDD or within
about 64 ms after supplying AVDD
Otherwise, it is strongly recommended to
send recalibrate command. See
)
must be
.
a
Note:
Proper decoupling capacitors (1 F to
AVDD, 0.1 F to DVIO) should be mounted
as close as possible to the respective
pins. See Figure 6-1 for example circuit.
Section 7.1 “Recalibrate Command” for
more details.
5.2.1
VOLTAGE REFERENCE
SELECTION
5.2
Reference Voltage (V
)
REF
The performance of the voltage reference has a large
impact on the accuracy of high-precision data
acquisition systems. The voltage reference should
have high-accuracy, low-noise, and low-temperature
drift. A ±0.1% output accuracy of the reference directly
corresponds to ±0.1% absolute accuracy of the ADC
output. The RMS output noise voltage of the reference
should be less than 1/2 LSB of the ADC.
The device requires a single-ended external reference
voltage (VREF). The external input reference range is
from 2.5V to 5.1V. This reference voltage sets the
input full-scale range from 0V to VREF. See Figure 6-1
to Figure 6-2 for example application circuit and
reference voltage settings.
2018 Microchip Technology Inc.
DS20006122A-page 29
MCP33131/MCP33121/MCP33111-XX
time. Although the device can be driven directly with a
low impedance source, using a low noise input driver is
highly recommended.
6.0
DEVICE OVERVIEW
The device converts unipolar single-ended analog
input into unipolar straight binary codes.
When the MCP33131/MCP33121/MCP33111-XX is
first powered-up, it performs a self-calibration and
enters a low current input acquisition mode (Standby)
by itself.
MCP331x1-XX
V
REF
V
= 0.6V
T
The external reference voltage (VREF) ranging from
2.5V to 5.1V sets the input full-scale range (FSR) from
Sample VIN
+
D
1
+
SW1
+
SW2
+
R
C
S
SON
AIN
+
0V to +VREF
.
C
PIN
(200 )
(31 pF)
During input acquisition (Standby), the internal input
sampling capacitors are connected to the input signal,
while most of the internal analog circuits are shutdown
to save power. During this input acquisition time
(tACQ), the device consumes less than 1 A.
I
LEAKAGE
D
2
(~ ±1 nA)
V
REF
V
= 0.6V
T
The user can operate the device with an easy-to-use
SPI-compatible 3-wire interface.
Sample VIN
-
D
1
-
SW1
-
SW2
-
R
C
SON
S
AIN
-
The device initiates data conversion on the rising edge
of the conversion-start control (CNVST). The data con-
version time (tCNV) is set by the internal clock. Once
the conversion is complete, the device starts the next
input acquisition. During this input acquisition time
(tACQ), the user can clock out the output data by pro-
viding the external SPI serial clock (SCLK).
C
PIN
(200 )
(31 pF)
I
LEAKAGE
D
2
(~ ±1 nA)
where:
+
-
, C
S
C
S
= Input sample and hold capacitor ≈ 31 pF.
The device provides conversion data with no missing
codes. This ADC device family has a large input
full-scale range, high precision, high throughput with
no output latency, and is an ideal choice for various
ADC applications.
R
SON
= On-resistance of the sampling switch ≈ 200
= Package pin + ESD capacitor ≈ 2 pF.
= Analog input.
CPIN
AIN
AIN
+
= Ground reference of analog input.
-
Simplified Equivalent Analog Input Circuit.
6.1
Analog Input
Note:
The ESD diodes at the analog input pins
are biased from VREF. Any input voltage
outside the absolute maximum range can
turn on the input ESD protection diodes
and results in input leakage current which
may cause conversion errors and
permanent damage to the device. Care
must be taken in setting the input voltage
ranges so that the input voltage does not
exceed the absolute maximum input
voltage range.
Figure shows a simplified equivalent circuit of the
input architecture with a switched capacitor input stage.
The input sampling capacitor (CS+) is about 31 pF. The
back-to-back diodes (D1 - D2) at each input pin are
ESD protection diodes. Note that these ESD diodes are
tied to VREF, so that each input signal can swing from
0V to VREF
.
The input sampling and hold circuit in AIN+ path is also
repeated in AIN- path. This allows the device to perform
a pseudo-differential conversion of the input signal.
Therefore, the common mode signal presented at both
input pins is rejected. In applications, AIN+ pin is for the
input signal and AIN- pin is for the ground reference of
the input signal. The user must connect the AIN- pin to
a clean ground plane of the input signal externally.
During input acquisition phase (Standby), the sampling
switches are closed and each input sees the sampling
capacitor (≈ 31 pF) in series with the on-resistance of
the sampling switch, RSON (≈ 200).
For high-precision data conversion applications, the
input voltage needs to be fully settled within 1/2 LSB
during the input acquisition period (tACQ). The settling
time is directly related to the source impedance: A
lower impedance source results in faster input settling
DS20006122A-page 30
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.1.1
INPUT VOLTAGE RANGE
6.2
Analog Input Conditioning Circuit
The device has two analog input pins: AIN+ and AIN-
pins. The analog input signal is applied to the AIN+ pin,
and the ground reference of the input signal is tied to
the AIN- pin.
The MCP33131/MCP33121/MCP33111-XX can be
driven directly when the source impedance of the input
driver is low.
Large source impedance of the input signal may affect
the ADC’s performance. In general, the source imped-
ance is less sensitive to the ADC’s DC performances
such as INL and DNL. However, it affects significantly
to the dynamic performances such as THD, SFDR and
SNR.
The voltage difference between AIN+ and AIN- is the
ADC input (VIN) and needs to be between 0V and
+VREF to produce unsaturated output codes.
Equation 6-4 shows the input full-scale range (FSR)
and input range.
The device will output unipolar straight binary codes for
the analog input. If the input (VIN) is greater than the
reference voltage (VREF), the output code will be
saturated. If the input (VIN) is less than or equals to 0V,
the output will be all 0’s.
Therefore, it is a good design practice to isolate the
ADC input from the high impedance source using a low
noise input driver amplifier. Figure 6-1 shows an input
configuration example using a low-noise OP amplifier
such as MCP6286 and Figure 6-2 shows the transfer
function of the MCP33131/MCP33121/MCP33111-XX.
EQUATION 6-1:
FSR AND INPUT RANGE
VREF
0V VIN VREF – 1LSB
Input Full-Scale Range (FSR)
=
Input Range:
where VIN = AIN+ - AIN-
VREF
2.5V to 5.1V 1.8V
1.7V to 5.5V
0.1 F
Voltage
Reference
V
DC
C
R
0.1 F
MCP1501
(Note 2)
10 F
(Tantalum)
1
fC
=
2R C
V
1
1
REF
V
REF
R1
VREF
AVDD
DVIO
0V
AIN
+
0V
(22 ±0.1%
)
Analog Input
C1
SDI
(1.7nF, NPO)
Host Device
VIN
MCP6286
(Note 1)
MCP331x1-XX
CNVST
SCLK
SDO
(PIC32MZ)
0V
AIN
-
Ground Reference of
Analog Input
GND
Note 1: Contact Microchip Technology Inc. for more selections of the low-noise input driver amplifiers.
2: Contact Microchip Technology Inc. for the MCP1501 application circuit.
FIGURE 6-1:
Unipolar-Input Application Example
Digital Output Code
2n - 1
2n/2
V
IN (V)
0
+VREF/2 +VREF
range
Analog Input Voltage
V
IN
FIGURE 6-2:
Transfer Function for Figure 6-1.
2018 Microchip Technology Inc.
DS20006122A-page 31
MCP33131/MCP33121/MCP33111-XX
• ADC Input-Referred Noise:
6.3
ADC Input Driver Selection
When the ADC is operating with a full-scale input
range, the ADC input-referred RMS noise for a
single-ended input configuration is approximated as
shown in Equation 6-4.
The noise and distortion of the ADC input driver can
degrade the dynamic performance (SNR, SFDR, and
THD) of the overall ADC application system. Therefore,
the ADC input driver needs better performance specifi-
cations than the ADC itself. The data sheet of the driver
typically shows the output noise voltage and harmonic
distortion parameters.
EQUATION 6-4:
ADC INPUT-REFERRED
NOISE
SNR
20
Figure 6-3 shows
presentation block diagram for the front-end driver and
ADC.
a
simplified system noise
–-----------
VREF
(V)
VN_ADC Input-Referred Noise
=
-------------- 10
2
2
• Noise Contribution from the Front-End Driver:
ADC Input Driver
R
The noise from the input driver can degrade the ADC’s
SNR performance. Therefore, the selected input driver
should have the lowest possible broadband noise den-
sity and 1/f noise. When an anti-aliasing filter is used
after the input driver, the output noise density of the
input driver is integrated over the -3 dB bandwidth of
the filter.
- +
- +
ADC
C
V
V
N_ADC Input-Referred Noise
N_RMS_Driver Noise
FIGURE 6-3:
Simplified System Noise
Equation 6-5 shows the RMS output noise voltage cal-
culation using the RC filter’s bandwidth and noise den-
sity (eN) of the input driver. GN in Equation 6-5 is the
noise gain of the driver amplifier and becomes 1 for a
unity gain buffer driver.
Representation.
• Unity-Gain Bandwidth:
An input driver with higher bandwidth usually results in
better overall linearity performance. Typically, the driver
should have the unity-gain bandwidth greater than 5
times the -3 dB cutoff frequency of the anti-aliasing fil-
ter:
EQUATION 6-5:
NOISE FROM FRONT-END
DRIVER AMPLIFIER
eN
VN_RMS_Driver Noise
(V)
GN------ f
B
EQUATION 6-2:
BANDWIDTH
2
REQUIREMENT FOR ADC
INPUT DRIVER
where eN is the broadband noise density (V/√Hz) of the
front-end driver amplifier and is typically given in its
data sheet. In Equation 6-5, 1/f noise (eNFlicker) is
ignored assuming it is very small compared to the
broadband noise (eN).
BW
Input Driver
5 x f
(Hz)
B
5
--------------
for a single-pole RC filter
2RC
where, fB = -3 dB bandwidth of RC anti-aliasing filter as
shown in Figure 6-3.
For high precision ADC applications, the noise
contribution from the front-end input driver amplifier is
typically constrained to be less than about 20% (or 1/5
times) of the ADC input-referred noise as shown in
Equation 6-6:
• Distortion:
The nonlinearity characteristics of the input driver
cause distortions in the ADC output. Therefore, the
input driver should have less distortion than the ADC
itself. The recommended total harmonic distortion
(THD) of the driver is at least 10 dB less than that of the
ADC:
EQUATION 6-6:
RECOMMENDED ADC
INPUT DRIVER NOISE
1
5
VN_RMS_Driver Noise
V
--
N_ADC Input-Referred Noise
EQUATION 6-3:
RECOMMENDED THD
FOR ADC INPUT DRIVER
Using Equation 6-4 to Equation 6-6, the recommended
noise voltage density (eN) limit of the ADC input driver
is expressed in Equation 6-7:
THD
≤ THD
-10
ADC
(dB)
Input Buffer
DS20006122A-page 32
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
EQUATION 6-7:
NOISE DENSITY FOR ADC
INPUT DRIVER
TABLE 6-2:
Noise Voltage Density (eN) of
Input Driver for MCP33121-XX
ADC
(Note 1)
RC
ADC Input Driver
eN
1
--
5
GN ------ f
VN_ADC Input-Referred Noise
Filter Amplifier (G = 1)
N
B
2
SNR
ADC
–-----------
SNR
Noise Voltage
Density (e )
N
f
B
1
eN ------
10
1
V
V
Input-Referred
Noise
20
REF
----------
(Note 2)
(dBFS)
------------------------- VREF 10
Hz
GN f
B
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
8.1 nV/√Hz
7.1 nV/√Hz
6.3 nV/√Hz
9.0 nV/√Hz
7.8 nV/√Hz
7.0 nV/√Hz
10.9 nV/√Hz
9.4 nV/√Hz
8.4 nV/√Hz
2.5V
3.3V
5V
80
88.4V
98.2 V
118.1 V
Using Equation 6-7, the recommended maximum
noise voltage density limit for unity gain input driver for
single-ended input ADC can be estimated. Table 6-1 to
Table 6-3 show a few example results with GN = 1. The
user may use these tables as a reference when
selecting the ADC input driver amplifier.
81.5
83.5
TABLE 6-1:
Noise Voltage Density (eN) of
Input Driver for MCP33131-XX
Note 1:
2:
See Equation 6-4 for the ADC input-referred noise
calculation for single-ended input.
fB is -3dB bandwidth of the RC anti-aliasing filter.
RC
Filter
ADC Input Driver
Amplifier (G = 1)
N
ADC
(Note 1)
TABLE 6-3:
Noise Voltage Density (eN) of
Input Driver for MCP33111-XX
ADC
Input-Referred
Noise
SNR
(dBFS)
Noise Voltage
Density (e )
N
f
B
V
REF
(Table 2)
RC
ADC Input Driver
ADC
(Note 1)
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
7.3 nV/√Hz
6.3 nV/√Hz
5.6 nV/√Hz
7.6 nV/√Hz
6.6 nV/√Hz
5.9 nV/√Hz
7.3 nV/√Hz
6.3 nV/√Hz
5.6 nV/√Hz
Filter
Amplifier (G = 1)
N
2.5V
3.3V
5V
81
83
87
78.8V
82.6 V
79 V
ADC
Input-Referred
Noise
SNR
(dBFS)
Noise Voltage
Density (e )
N
f
B
V
REF
(Note 2)
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
3 MHZ
4 MHz
5 MHZ
17.8 nV/√Hz
15.4 nV/√Hz
13.8 nV/√Hz
22.7 nV/√Hz
19.7 nV/√Hz
17.6 nV/√Hz
33.3 nV/√Hz
28.8 nV/√Hz
25.8 nV/√Hz
2.5V
3.3V
5V
73.2
73.5
73.8
193.3V
246.6 V
360.9 V
Note 1:
2:
See Equation 6-4 for the ADC input-referred noise
calculation for single-ended input.
B is -3dB bandwidth of the RC anti-aliasing filter.
f
Note 1:
2:
See Equation 6-4 for the ADC input-referred noise cal-
culation for single-ended input.
fB is -3dB bandwidth of the RC anti-aliasing filter.
2018 Microchip Technology Inc.
DS20006122A-page 33
MCP33131/MCP33121/MCP33111-XX
6.4.2
DATA CONVERSION PHASE
6.4
Device Operation
The start of the conversion is controlled by CNVST. On
the rising edge of CNVST, the sampled charge is
locked (sample switches are opened) and the ADC
performs the conversion. Once a conversion is started,
it will not stop until the current conversion is complete.
When the MCP33131/MCP33121/MCP33111-XX is
first powered-up, it self-calibrates internal systems and
enters input acquisition mode by itself. The device
operates in two phases: (a) Input Acquisition (Standby)
and (b) Data Conversion. Figure 6-4 shows the ADC
operating sequence.
The data conversion time (tCNV
)
is not
user-controllable. After the conversion is complete and
the host lowers CNVST, the output data is presented on
SDO.
6.4.1
INPUT ACQUISITION PHASE
(STANDBY)
Any noise injection during the conversion phase may
affect the accuracy of the conversion. To reduce
environment noise, minimize I/O events and running
clocks during the conversion time.
During the input acquisition phase (tACQ), also called
+
Standby, the two input sampling capacitors, CS and
-
CS , are connected to the AIN+ and AIN- pins,
respectively. The input voltage is sampled until a rising
edge on CNVST is detected. The input voltage should
The output data is clocked out MSB first. While the out-
put data is being transferred, the device enters the next
input acquisition phase.
be fully settled within 1/2 LSB during tACQ
During this input acquisition time (tACQ), the ADC
consumes less than 1 A. The acquisition time (tACQ
.
)
Note:
Transferring output data during the
acquisition phase can disturb the next
input sample. It is highly recommended to
allow at least tQUIET (10 ns, typical)
between the last edge on the SPI
interface and the rising edge on CNVST.
is user-controllable. This acquisition time (tACQ) can be
increased as long as needed for additional power
savings.
See Figure 1-1 for tQUIET
.
tCYC = 1/fS
Input Acquisition
Input Acquisition
(Standby)
Data Conversion
tCNV
(Standby)
Operating
Condition
tACQ
tACQ
MCP331x1-10: 300 ns (typical)
MCP331x1-05: 800 ns (typical)
MCP331x1-10: 700 ns (typical)
MCP331x1-05: 1200 ns (typical)
MCP331x1-10: 300 ns (typical)
MCP331x1-05: 800 ns (typical)
(a) At the falling edge of CNVST,
ADC output is available at SDO.
(a) ADC acquires input sample #1. (a) Conversion is initiated at the rising edge of CNVST.
(b) No ADC output is available yet.
(b) All circuits are turned-on.
(b) ADC output can be clocked out
by providing clocks.
(c) Most analog circuits are
turned off.
(c) ADC output is not available yet.
(c) ADC acquires input sample #2.
MCP331x1-10: ~ 1.6 mA
MCP331x1-05: ~ 1.4 mA
(d) Most analog circuits are turned off.
IDDAN
I
~ 0.8 A
Off
(a) Device is first powered-up and
(b) Performs a power-up self-calibration.
Output Data
SDO
FIGURE 6-4:
Device Operating Sequence.
DS20006122A-page 34
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.4.3
SAMPLE (THROUGHPUT) RATE
EQUATION 6-9: SPI CLOCK FREQUENCY
REQUIREMENT
The device completes data conversion within the
maximum specification of the data conversion time
(tCNV). The continuous input sample rate is the inverse
of the sum of input acquisition time (tACQ) and data
conversion time (tCNV). Equation 6-8 shows the
continuous sample rate calculation using the minimum
and maximum specifications of the input acquisition
time (tACQ) and data conversion time (tCNV).
tACQ = N TSCLK + tQUIET + tEN
1
fSCLK = ---------------
TSCLK
N
=
-----------------------------------------------------
tACQ – tQUIET + tEN
where N is the number of output data bits, given by
N
=
=
=
=
=
=
16-bit for MCP33131-XX
14-bit for MCP33121-XX
12-bit for MCP33111-XX
Period of SPI clock
EQUATION 6-8:
SAMPLE RATE
1
T
N x T
t
----------------------------------
SCLK
SCLK
Sample Rate =
tACQ + tCNV
Output data window
(a) MCP331x1-10:
Sample Rate =
Quiet time between the last output bit
and beginning of the next
conversion start.
QUIET
1
---------------------------------------- = 1 Msps
290ns + 710ns
(b) MCP331x1-05:
Sample Rate =
=
=
10 ns (min)
1
------------------------------------------- = 500 kSPS
700ns + 1300ns
Output enable time = 10 ns (max), with
t
EN
DV ≥2.3V
IO
6.4.4
SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
Note:
See Figure 1-1 for digital interface timing dia-
gram.
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by the following equation:
where fSCLK is the minimum SPI serial clock frequency
required to transfer all N-bits of output data during input
acquisition time (tACQ).
Table 6-4 and Table 6-5 show the examples of calcu-
lated minimum SPI clock (fSCLK) requirements for vari-
ous input acquisition times for 1 Msps and 500 kSPS
family devices, respectively.
TABLE 6-4:
SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-10
SPI Clock (f
) Speed Requirement
SCLK
Input
Acquisition Time:
Data
Conversion Time:
(Note 1), (Note 2)
Sample Rate:
Conditions
f
(Msps)
t
(nS)
(Note 4)
t
(nS)
S
ACQ
CNV
MCP33131-10
MCP33121-10
(14-bit)
MCP33111-10
(12-bit)
(Note 5)
(16-bit)
250
270
69.57 MHz
64 MHz
60.87 MHz
56 MHz
52.17 MHz
48 MHz
1
85°C < TA ≤ 125°C
0.98
0.97
1
750
(Note 3)
280
61.54 MHz
59.26 MHz
57.15 MHz
53.33 MHz
42.11 MHz
30.77 MHz
22.86 MHz
17.2 MHz
12.6 MHz
9.04 MHz
6.15 MHz
3.75 MHz
1.73 MHz
53.85 MHz
51.85 MHz
50 MHz
46.15 MHz
44.44 MHz
42.86 MHz
40 MHz
290
300
0.99
0.97
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-40°C ≤ TA ≤ 85°C
320
46.67 MHz
36.84 MHz
26.92 MHz
20 MHz
400
30 MHz
540
23.08 MHz
17.14 MHz
12.9 MHz
9.45 MHz
6.78 MHz
4.62 MHz
2.81 MHz
1.3 MHz
710
720
720
15.05 MHz
11.02 MHz
7.91 MHz
5.39 MHz
3.28 MHz
1.51 MHz
1290
1750
2620
4290
9290
Note 1:
This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the
ADC is operating in continuous input sampling mode.
2:
3:
See Equation 6-9 for the calculation of the SPI clock speed requirement.
In extended temperature range, the device takes longer data conversion time (tCNV: 750 nS, max). Using a shorter input acquisition time
is recommended (tACQ: 250 nS) for 1 Msps throughput rate.
4:
5:
Input acquisition time (tACQ) is user-controllable.
Data conversion time (tCNV) is not user-controllable.
2018 Microchip Technology Inc.
DS20006122A-page 35
MCP33131/MCP33121/MCP33111-XX
TABLE 6-5:
SPI CLOCK SPEED VS. INPUT ACQUISITION TIME (TACQ) FOR MCP331X1-05
SPI Clock (f
) Speed Requirement
SCLK
Input
Acquisition Time:
Data
Conversion Time:
(Note 1), (Note 2)
Sample Rate:
Conditions
f
(kSPS)
t
(nS)
(Note 3)
t
(nS)
S
ACQ
CNV
MCP33131-05
MCP33121-05
(14-bit)
MCP33111-05
(12-bit)
(Note 4)
(16-bit)
700
740
23.53MHz
22.22 MHz
20.78 MHz
17.58 MHz
13.56 MHz
10.39 MHz
7.96 MHz
5.97 MHz
4.35 MHz
2.99 MHz
1.84 MHz
20.59 MHz
19.44 MHz
18.18 MHz
15.39 MHz
11.86 MHz
9.09 MHz
6.97 MHz
5.22MHz
17.65 MHz
16.67 MHz
15.58 MHz
13.19 MHz
10.17 MHz
7.79 MHz
5.97 MHz
4.48 MHz
3.26 MHz
2.25 MHz
1.38 MHz
500
490
480
450
400
350
300
250
200
150
100
-40°C ≤ TA ≤ 125°C
790
930
1300
1200
1560
2030
2700
3700
5370
8700
3.8 MHz
2.62 MHz
1.61 MHz
Note 1:
This is the minimum SPI clock speed requirement to collect all N-bits of the ADC output during the input acquisition time (tACQ), when the
ADC is operating in continuous input sampling mode.
2:
3:
4:
See Equation 6-9 for the calculation of the SPI clock speed requirement.
Input acquisition time (tACQ) is user-controllable.
Data conversion time (tCNV) is not user-controllable.
6.5
Transfer Function
5.1
77.8 V
311.3 V
1.2451 mV
Figure 6-5 shows the ideal transfer function and
Table 6-7 shows the digital output codes for the
MCP33131/MCP33121/MCP33111-XX.
The pseudo-differential analog input is:
VIN = (VIN+) - (VIN-)
where VIN+ is the analog input voltage at AIN+ pin with
respect to the ground reference (GND), and Vin- is the
voltage at AIN- pin, which is 0V when tied to the analog
input ground reference (GND).
Digital Output Code (Unipolar Straight Binary)
111 ...111
111 ...110
The LSB size is given by Equation 6-10. and an
example of LSB size vs. reference voltage is
summarized in Table 6-6.
EQUATION 6-10: LSB SIZE - EXAMPLE
100 ...000
VREF
LSB = ------------
2N
where N is the resolution of the ADC in bits.
000 ...001
TABLE 6-6:
LSB SIZE VS. REFERENCE
000 ...000
0V
VREF
LSB Size
Reference
Voltage
2
0V+ 1 LSB
VREF - 1.5 LSB
VREF - 1 LSB
MCP33131-XX
(16-bit)
MCP33121-XX
(14-bit)
MCP33111-XX
(12-bit)
0V + 0.5 LSB
(V
)
REF
2.5V
2.7V
3V
38.2V
41.2 V
45.8 V
50.4 V
53.4 V
61.0 V
68.7 V
76.3 V
152.6 V
164.8 V
183.1 V
201.4 V
213.6 V
244.1 V
274.7 V
305.2 V
0.6104 mV
0.6592 mV
0.7324 mV
0.8057 mV
0.8545 mV
0.9766 mV
1.0986 mV
1.2207 mV
Analog Input Voltage
FIGURE 6-5:
Ideal Transfer Function.
3.3V
3.5V
4V
4.5V
5V
DS20006122A-page 36
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
6.6
Digital Output Code
The digital output code is proportional to the input
voltage. The output data is in unipolar straight binary
format. The following is an example of the output code:
(a) for a zero or negative input:
Analog Input: VIN ≤ 0 (V)
Output Code: 0000...0000
(b) for a mid-scale input:
Analog Input: VIN = +VREF /2 (V)
Output Code: 1000...0000
(c) for a positive full-scale input:
Analog Input: VIN = +VREF (V)
Output Code: 1111...1111
The code will be locked at 1111...11 for all voltages
greater than (VREF - 1 LSB) and 0000...00 for
voltages less than 0V. Table 6-7 shows an example of
output codes of various input levels.
TABLE 6-7:
DIGITAL OUTPUT CODE
Digital Output Codes
Input Voltage (V)
MCP33131-XX
(16-bit)
MCP33121-XX
(14-bit)
MCP33111-XX
(12-bit)
VREF
1111-1111-1111-1111
1111-1111-1111-1111
11-1111-1111-1111
11-1111-1111-1111
1111-1111-1111
1111-1111-1111
VREF - 1 LSB
.
.
.
.
.
.
.
.
VREF/2
1000-0000-0000-0000
10-0000-0000-0000
1000-0000-0000
.
.
.
.
.
.
.
.
2 LSB
1 LSB
≤ 0V
0000-0000-0000-0010
0000-0000-0000-0001
0000-0000-0000-0000
00-0000-0000-0010
00-0000-0000-0001
00-0000-0000-0000
0000-0000-0010
0000-0000-0001
0000-0000-0000
2018 Microchip Technology Inc.
DS20006122A-page 37
MCP33131/MCP33121/MCP33111-XX
SDO returns to high-Z state after the last data bit is
clocked out or when CNVST goes high, whichever
occurs first.
7.0
DIGITAL SERIAL INTERFACE
The device has
a SPI-compatible serial digital
interface using four digital pins: CNVST, SDI, SDO and
SCLK.
Figure 7-1 shows the connection diagram with the host
device and Figure 7-2 shows the SPI-compatible serial
interface timing diagram.
CS
DV
IO
DV
IO
CNVST
SDI
The SDI pin can be tied to the digital I/O interface
supply voltage (DVIO) or just maintain logic “High” level
by the host. The CNVST pin is used for both chip select
(CS) and conversion-start control.
SDO
SDI
10 k
(Note 1)
SCLK
A rising edge on CNVST initiates the conversion
process. Once the conversion is initiated, the device
will complete the conversion regardless of the state of
CNVST. This means the CNVST pin can be used for
other purposes during tCNV.
SCLK
(b) Host Device (Master)
(a) MCP33131/21/11-XX
Note 1: Adding this pull-up is needed when monitoring
status of Recalibrate.
When the conversion is complete, the output is
available at SDO by lowering CNVST. Data is sent
MSB-first and changes on the falling edge of SCLK.
FIGURE 7-1:
Digital Interface Connection
Output data can be sampled on either edge of SCLK.
However, a digital host capturing data on the falling
edge of SCLK can achieve a faster read out rate.
Diagram.
t
= 1/f
CYC
S
SDI = DV
IO
(Note 1)
tCNVH
(a) Exit input acquisition mode and
(b) Enter new conversion mode
tSU_SDIH_CNV
CNVST
tSCLK
(Note 2)
4
14
1
16
3
15
2
SCLK
SDO
tDO
tQUIET
tDIS
tSCLK_L
(Note 5)
tSCLK_H
Hi-Z
D15
(MSB)
Hi-Z
D12
D2
D0
D1
D14
D13
tCNV (MAX)
tEN
(Note 3)
tEN
(Note 4)
ADC State
Input Acquisition
Conversion
Input Acquisition
(tACQ
)
(tCNV
)
(tACQ
)
Note 1: SDI must maintain “High” during the entire t
.
CYC
2: Any SCLK toggling events (dummy clocks) before CNVST is changed to “Low” are ignored.
3: tEN when CNVST is lowered after tCNV (Max).
4: tEN when CNVST is lowered before tCNV (Max).
5: Recommended data detection: Detect SDO on the falling edge of SCLK.
FIGURE 7-2:
SPI Compatible Serial Interface Timing Diagram (16-bit device).
DS20006122A-page 38
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
A self-calibration is initiated by sending the recalibrate
7.1
Recalibrate Command
command. The host device sends a recalibrate
command by transmitting 1024 SCLK pulses (including
the clocks for data bits) while the device is in the
acquisition phase (Standby).
The user may use the recalibrate command in the
following cases:
• When the reference voltage was not fully settled
during the first-power sequence.
The device drives SDO low during the recalibration
procedure, and returns to high-Z once completed. The
status of the recalibration procedure can be monitored
by placing a pull-up on SDO, so that SDO goes high
when the recalibration is complete.
• During operation, to ensure optimum performance
across varying environment conditions, such as
reference voltage and temperature.
Figure 7-3 shows the recalibrate command timing
diagram. The calibration takes approximately 500 ms
(tCAL).
(Note 1)
SDI = DV
IO
Start recalibration
Finish recalibration
Complete data reading
Device Recalibration
CNVST
1024 clocks
(SPI Recalibrate command)
TM
1024
1
2
3
15 16
tCAL
SCLK
SDO
(Note 2)
“High” with Pull-up
Hi-Z
“High” with Pull-up
Hi-Z
“Low”
ADC Output Data Stream
Hi-Z
(Note 3)
ADC State
(Note 4)
tCNV
Note
1: SDI must remain “High” during the entire recalibration cycle.
2: The 1024 clocks include the clocks for data bits.
3: SDO outputs “Low” during calibration, and Hi-Z when exiting the calibration.
4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.
FIGURE 7-3:
Note:
Recalibrate Command Timing Diagram.
When the device performs a self-calibration, it is important to note that both AVDD and the reference
voltage (VREF) must be stabilized for a correct calibration. This is also true when the device is first
powered-up, the reference voltage (VREF) must be stabilized before self-calibration begins. This means
the VREF must be provided prior to supplying AVDD or within about 64 ms after supplying AVDD
.
2018 Microchip Technology Inc.
DS20006122A-page 39
MCP33131/MCP33121/MCP33111-XX
NOTES:
DS20006122A-page 40
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
TERMINOLOGY
EQUATION 8-2:
8.0
P
S
SINAD = 10log ---------------------
Analog Input Bandwidth (Full-Power
Bandwidth)
P
+ P
D
N
SNR
–-----------
10
THD
–------------
10
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
= –10log 10
– 10
SINAD is either given in units of dBc (dB to carrier),
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale), when the
power of the fundamental is extrapolated to the
converter full-scale range.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
CNVST input and when the input signal is held for a
conversion.
Effective Number of Bits (ENOB)
Differential Nonlinearity
(DNL, No Missing Codes)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
An ideal ADC exhibits code transitions that are exactly
1 LSB apart. DNL is the deviation from this ideal value.
No missing codes to 16-bit resolution indicates that all
65,536 codes (16,384 codes for 14-bit, 4096 codes for
12-bit) must be present over all the operating
conditions.
EQUATION 8-3:
SINAD – 1.76
ENOB = ----------------------------------
6.02
Gain Error
Integral Nonlinearity (INL)
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range. Gain error is usually expressed in LSB or as a
percentage of full-scale range (%FSR).
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
Offset Error
Offset error is the difference between the ideal voltage
(0V + 0.5 LSB) that produces the first code transition
(“000... 000” to “000... 001”) and the actual voltage pro-
ducing that code.
EQUATION 8-1:
P
S
Temperature Drift
SNR = 10log -------
P
N
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value at across the TMIN to TMAX range.
The value is normalized by the reference voltage and
expressed in V/oC or ppm/oC.
SNR is either given in units of dBc (dB to carrier), when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale), when the power
of the fundamental is extrapolated to the converter
full-scale range.
Maximum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
The maximum clock rate at which parametric testing is
performed.
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
2018 Microchip Technology Inc.
DS20006122A-page 41
MCP33131/MCP33121/MCP33111-XX
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 8-4:
P
S
THD = 10log -------
P
D
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 8-5:
2
2
2
3
2
4
2
n
V
+ V + V + + V
THD = –20log-----------------------------------------------------------------
2
V
1
Where:
V1 = RMS amplitude of the
fundamental frequency
V1 through Vn = Amplitudes of the second
through nth harmonics
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential or pseudo-differential input pair. The
common-mode signal can be an AC or DC signal or a
combination of the two. CMRR is measured using the
ratio of the differential signal gain to the common-mode
signal gain and expressed in dB with the following
equation:
EQUATION 8-6:
A
DIFF
CMRR = 20log ------------------
A
CM
Where:
ADIFF = Output Code/Differential Voltage
ADIFF = Output Code/Common-Mode Voltage
DS20006122A-page 42
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
10-Lead MSOP (3x3 mm)
Example
Corresponding Part Number:
31-10 = MCP33131-10
31-05 = MCP33131-05
21-10 = MCP33121-10
21-05 = MCP33121-05
11-10 = MCP33111-10
11-05 = MCP33111-05
31-10
839256
10-Lead TDFN (3x3x0.9 mm)
Example
Corresponding Part Number:
311 = MCP33131-10
310 = MCP33131-05
211 = MCP33121-10
210 = MCP33121-05
111 = MCP33111-10
110 = MCP33111-05
311
1839
256
XXXX
YYWW
NNN
PIN 1
PIN 1
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2018 Microchip Technology Inc.
DS20006122A-page 43
MCP33131/MCP33121/MCP33111-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 H
D
D
2
A
N
E
2
E1
2
E1
E
0.20 H
0.25 C
1
2
e
B
8X b
0.13
C A B
TOP VIEW
H
C
A2
A
SEATING
PLANE
8X
0.10 C
A1
SEE DETAIL A
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-021D Sheet 1 of 2
DS20006122A-page 44
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
4X Ĭ1
c
C
SEATING
PLANE
Ĭ
L
(L1)
4X Ĭ1
DETAIL A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
10
0.50 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
A
-
-
1.10
0.95
0.15
A2
A1
E
E1
D
0.75
0.00
0.85
-
4.90 BSC
3.00 BSC
3.00 BSC
0.60
L
0.40
0.80
Footprint
L1
0.95 REF
Mold Draft Angle
Foot Angle
Lead Thickness
Lead Width
0°
5°
0.08
0.15
-
-
-
-
8°
15°
0.23
0.33
Ĭ
Ĭ1
c
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-021D Sheet 2 of 2
2018 Microchip Technology Inc.
DS20006122A-page 45
MCP33131/MCP33121/MCP33111-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
Z
C
G1
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.50 BSC
4.40
MAX
Contact Pitch
E
C
Contact Pad Spacing
Overall Width
Contact Pad Width (X10)
Contact Pad Length (X10)
Distance Between Pads (X5)
Distance Between Pads (X8)
Z
X1
Y1
G1
G
5.80
0.30
1.40
3.00
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2021B
DS20006122A-page 46
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2018 Microchip Technology Inc.
DS20006122A-page 47
MCP33131/MCP33121/MCP33111-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006122A-page 48
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
APPENDIX A: REVISION HISTORY
Revision A (November 2018)
• Original release of this document.
2018 Microchip Technology Inc.
DS20006122A-page 49
MCP33131/MCP33121/MCP33111-XX
NOTES:
2018 Microchip Technology Inc.
DS20006122A-page 50
MCP33131/MCP33121/MCP33111-XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
X
─X
/XX
─XX
PART NO.
Device
X
Examples:
a)
MCP33131-10-I/MS:
1 Msps, 10LD MSOP,
16-bit device
Input Type
Tape
and
Reel
Temperature Package
Range
Sample Rate
b)
MCP33131-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
16-bit device
Device:
MCP33131-10: 1 Msps 16-Bit Single-Ended Input SAR ADC
MCP33121-10: 1 Msps 14-Bit Single-Ended Input SAR ADC
MCP33111-10: 1 Msps 12-Bit Single-Ended Input SAR ADC
c)
d)
MCP33131-10-I/MN:
1 Msps, 10LD TDFN,
16-bit device
MCP33131-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
16-bit device
MCP33131-05:
MCP33121-05:
MCP33111-05:
500 kSPS 16-Bit Single-Ended Input SAR ADC
500 kSPS 14-Bit Single-Ended Input SAR ADC
500 kSPS 12-Bit Single-Ended Input SAR ADC
e)
f)
MCP33121-10-I/MS:
1 Msps, 10LD MSOP,
14-bit device
MCP33121-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
14-bit device
Input Type
Blank
= Single-Ended Input
g)
h)
MCP33121-10-I/MN:
1 Msps, 10LD TDFN,
14-bit device
Sample Rate: 10
= 1 Msps
= 500 kSPS
MCP33121-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
05
14-bit device
Tape and
Reel Option:
Blank
=
=
Standard packaging (tube or tray)
Tape and Reel
i)
j)
MCP33111-10-I/MS:
1 Msps, 10LD MSOP,
12-bit device
T
MCP33111-10T-I/MS: 1 Msps, 10LD MSOP,
Tape and Reel,
Temperature
Range:
E
I
= -40C to +125C (Extended)
= -40C to +85C (Industrial)
12-bit device
k)
l)
MCP33111-10-I/MN:
1 Msps, 10LD TDFN,
12-bit device
Package:
MS
MN
=
=
Plastic Micro Small Outline Package (MSOP), 10-Lead
MCP33111-10T-I/MN: 1 Msps, 10LD TDFN,
Tape and Reel,
Thin Plastic Dual Flat No Lead Package (TDFN),
10-Lead
12-bit device
m) MCP33131-05-I/MS:
500 kSPS, 10LD MSOP,
16-bit device
n)
MCP33131-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
16-bit device
o)
p)
MCP33131-05-I/MN:
500 kSPS, 10LD TDFN,
16-bit device
Note 1:
Tape and Reel identifier appears only in the catalog part number
description. This identifier is used for ordering purposes and is not
printed on the device package. Check with your Microchip Sales Office
for package availability with the Tape and Reel option.
MCP33131-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
16-bit device
q)
r)
MCP33121-05-I/MS:
500 kSPS, 10LD MSOP,
14-bit device
MCP33121-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
14-bit device
s)
t)
MCP33121-05-I/MN:
500 kSPS, 10LD TDFN,
14-bit device
MCP33121-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
14-bit device
u)
v)
MCP33111-05-I/MS:
500 kSPS, 10LD MSOP,
12-bit device
MCP33111-05T-I/MS: 500 kSPS, 10LD MSOP,
Tape and Reel,
12-bit device
w)
x)
MCP33111-05-I/MN:
500 kSPS, 10LD TDFN,
12-bit device
MCP33111-05T-I/MN: 500 kSPS, 10LD TDFN,
Tape and Reel,
12-bit device
DS20006122A-page 51
2018 Microchip Technology Inc.
MCP33131/MCP33121/MCP33111-XX
NOTES:
2018 Microchip Technology Inc.
DS20006122A-page 52
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3911-0
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20006122A-page 53
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Web Address:
www.microchip.com
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
Germany - Garching
Tel: 49-8931-9700
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
Germany - Haan
Tel: 49-2129-3766400
Austin, TX
Tel: 512-257-3370
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
Germany - Heilbronn
Tel: 49-7131-67-3636
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
Germany - Karlsruhe
Tel: 49-721-625370
China - Qingdao
Philippines - Manila
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Tel: 86-532-8502-7355
Tel: 63-2-634-9065
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
Germany - Rosenheim
Tel: 49-8031-354-560
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Israel - Ra’anana
Tel: 972-9-744-7705
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
Detroit
Novi, MI
Tel: 248-848-4000
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Padova
Tel: 39-049-7625286
Houston, TX
Tel: 281-894-5983
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
China - Xiamen
Tel: 86-592-2388138
Norway - Trondheim
Tel: 47-7289-7561
China - Zhuhai
Tel: 86-756-3210040
Poland - Warsaw
Tel: 48-22-3325737
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Raleigh, NC
Tel: 919-844-7510
Sweden - Gothenberg
Tel: 46-31-704-60-40
New York, NY
Tel: 631-435-6000
Sweden - Stockholm
Tel: 46-8-5090-4654
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006122A-page 54
2018 Microchip Technology Inc.
10/25/17
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