MCP33141D-05T-E/MN [MICROCHIP]
1 Msps/500 kSPS, 14/12-Bit Differential Input SAR ADC;
| 型号： | MCP33141D-05T-E/MN |
| 厂家： | 
MICROCHIP |
| 描述： | 1 Msps/500 kSPS, 14/12-Bit Differential Input SAR ADC 光电二极管 转换器 |
| 文件： | 总66页 (文件大小：3209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP33151D/41D-XX
1 Msps/500 kSPS, 14/12-Bit Differential Input SAR ADC
Features
Typical Applications
• Sample Rate (Throughput):
- MCP33151D/41D-10: 1 Msps
- MCP33151D/41D-05: 500 kSPS
• High-Precision Data Acquisition
• Medical Instruments
• Test Equipment
• 14/12-Bit Resolution with No Missing Codes
• No Latency Output
• Electric Vehicle Battery Management Systems
• Motor Control Applications
• Wide Operating Voltage Range:
- Analog supply voltage (AVDD): 1.8V
- Digital input/output interface voltage (DVIO):
1.7-5.5V
• Switch-Mode Power Supply Applications
• Battery-Powered Equipment
System Design Supports
The MCP331x1D-XX Evaluation Kit demonstrates the
performance of the MCP331x1D-XX SAR ADC family
devices. The evaluation kit includes: (a) MCP331x1D
Evaluation Board, (b) PIC32MZ EF Curiosity Board for
data collection, and (c) SAR ADC Utility PC GUI.
- Externalreferencevoltage(VREF):AVDD - 5.1V
• Differential Input Operation
- Input full-scale range: -VREF to +VREF
• Ultra Low Current Consumption (typical):
- During input acquisition (standby): ~1.5 µA
- During conversion:
Contact Microchip Technology Inc. for the evaluation
tools and the PIC32 firmware example codes.
MCP33151D/41D-10: ~0.66 mA
MCP33151D/41D-05: ~0.33 mA
Package Types
• SPI-Compatible Serial Communication:
- SCLK clock rate: up to 100 MHz
- 3-wire with optional BUSY indicator
MSOP-10
• ADC Self-Calibration for Offset, Gain, and
Linearity Errors:
- During power-up (automatic)
- On-Demand via user’s command during
normal operation
• Built In Data Accumulator
- Integrate up to 1024 consecutive converted
samples
TDFN-10 *
- Increase ENOB up to 18.5 bits by
automatically averaging conversion results
• AEC-Q100 Qualified:
- Temperature grade 1: -40°C to +125°C
• Package Options: MSOP-10 and TDFN-10
* Includes Exposed Thermal Pad (see Table 4-1).
MCP331x1D-XX Device Offering (Note 1)
Performance (Typical)
Input Range
Sample
Rate
Part Number Resolution
Input Type
SNR
SFDR THD
INL
DNL
(Differential)
(dBFS) (dB)
(dB) (LSB) (LSB)
MCP33151D-10
MCP33141D-10
MCP33151D-05
MCP33141D-05
14-bit
12-bit
14-bit
12-bit
1 Msps
1 Msps
Differential
Differential
±5.1V
±5.1V
±5.1V
±5.1V
83.8
73.8
83.7
73.8
107.3 -104.7 ±0.27 ±0.11
100.0 -101.5 ±0.07 ±0.05
103.8 -100.9 ±0.27 ±0.11
500 kSPS Differential
500 kSPS Differential
99.8
-98.9 ±0.07 ±0.05
Note 1: SNR, SFDR, and THD are measured with f = 10 kHz, V = -1 dBFS, V = 5.1V.
REF
IN
IN
2019 Microchip Technology Inc.
DS20006219A-page 1
MCP33151D/41D-XX
Application Diagram
AVDD to 5.1V
1.8V
AVDD
1.8V to 5.5V
DVIO
VREF
15Ω
AIN
MCP331x1D-XX
AIN
+
0V to VREF
2.2nF
SDI
CNVST
SCLK
Host Device
15Ω
-
(PIC32MZ)
SDO
0V to VREF
2.2nF
GND
During Standby, most of the internal analog circuitry is
shutdown in order to reduce current consumption.
Typically, the device consumes approximately 1.5 µA
during Standby. A new conversion is started on the
rising edge of CNVST. When the conversion is
complete and the host lowers CNVST, the output data
is presented on SDO, and the device enters Standby to
begin acquiring the next input sample. The user can
clock out the ADC output data using the
SPI-compatible serial clock during Standby.
Description
The MCP33151D/41D-10 and MCP33151D/41D-05
are fully-differential, 14-bit and 12-bit, single-channel,
1 Msps and 500 kSPS ADC family devices,
respectively, featuring low power consumption and
high performance, using a successive approximation
register (SAR) architecture.
The device operates with an external voltage reference
(VREF) from AVDD to 5.1V, which supports a wide range
of input full-scale range from -VREF to +VREF. The
reference voltage setting is independent of the analog
supply voltage (AVDD). The conversion output is
available through an easy-to-use simple SPI-
compatible 3-wire interface.
The ADC system clock is generated by the internal
on-chip clock, therefore the conversion is performed
independent of the SPI serial clock (SCLK).
This device can be used for various high-speed and
high-accuracy analog-to-digital data conversion
applications, where design simplicity, low power, and
no output latency are needed.
The device requires a 1.8V analog supply voltage
(AVDD) and a 1.7V to 5.5V digital I/O interface supply
voltage (DVIO). The wide digital I/O interface supply
(DVIO) range (1.7-5.5V) allows the device to interface
with most host devices (Master) available in the current
industry such as the PIC32 microcontrollers, without
using external voltage level shifters.
The device is AEC-Q100 qualified for automotive
applications and operates over the extended
temperature range of -40°C to +125°C. The available
package options are Pb-free small 3 mm × 3 mm
TDFN-10 and MSOP-10.
Once all supply voltages are connected, the device will
power-up and perform an automatic calibration to
minimize offset, gain and linearity errors. The
automatic calibration takes place approximately 40 ms
following power-up, and it is necessary to ensure that
all power supplies are fully settled and stable after this
time. See Section 4.3 “Power-Up Sequence and
Auto-Calibration” for more details. The device
performance stays stable across the specified
temperature range. However, when extreme changes
in the operating environment, such as in the reference
voltage, are made with respect to the initial conditions
(e.g. the reference voltage did not fully settle during the
initial power-up sequence), the user may send a
recalibrate command anytime to initiate another
self-calibration and restore optimum performance.
When the initial power-up sequence is completed, the
device enters a low-current input acquisition mode
(also referred to as ‘Standby mode’), where sampling
capacitors are connected to the input pins.
DS20006219A-page 2
2019 Microchip Technology Inc.
MCP33151D/41D-XX
1.0
1.1
KEY ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings †
External Analog Supply Voltage (AVDD) ...................................................................................................... -0.3V to 2.0V
External Digital Supply Voltage (DVIO)......................................................................................................... -0.3V to 5.8V
External Reference Voltage (VREF).............................................................................................................. -0.3V to 5.8V
Analog Inputs w.r.t GND ................................................................................................................. -0.3V to VREF + 0.3V
Current at Input Pins ..............................................................................................................................................±2 mA
Current at Output and Supply Pins ....................................................................................................................±250 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Maximum Junction Temperature (TJ) ................................................................................................................... +150°C
ESD Protection on All Pins ......................................................................................................≤ 4 kV HBM, ≤ 2 kV CDM
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1.2
Electrical Specifications
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF, +25°C is applied
IN
IN
LOAD_SDO
for typical values.
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Power Supply Requirements
Analog Supply Voltage Range
AVDD
DVIO
1.7
1.7
1.8
—
1.9
5.5
V
Note 3
Note 3
Digital Input/Output Interface
Voltage Range
Analog Supply Current at AVDD
Pin:
During Conversion
IDDAN
—
—
—
660
330
1.5
900
600
—
µA fS = 1 Msps (MCP331x1D-10)
µA fS = 500 kSPS (MCP331x1D-05)
µA During Input Acquisition (tACQ
During Standby
IDDAN_STBY
)
Average Digital Supply Current
at DVIO Pin:
—
—
—
—
—
400
343
200
171
120
—
—
—
—
—
µA fS = 1 Msps (MCP33151D-10)
µA fS = 1 Msps (MCP33141D-10)
µA fS = 500 kSPS (MCP33151D-05)
µA fS = 500 kSPS (MCP33141D-05)
During Data Transfer
IIO_DATA
During Standby
IIO_STBY
nA During Input Acquisition (tACQ
)
External Reference Voltage Input
Reference Voltage (Note 2,
Note 3)
VREF
AVDD
—
5.1
V
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
2019 Microchip Technology Inc.
DS20006219A-page 3
MCP33151D/41D-XX
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF, +25°C is applied
IN
IN
LOAD_SDO
for typical values.
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Reference Load Current at
VREF Pin:
During Conversion
IREF
—
—
—
220
110
40
290
180
—
µA fS = 1 Msps (MCP331x1D-10)
µA fS = 500 kSPS (MCP331x1D-05)
nA During Input Acquisition (tACQ
During Standby
IREF_STBY
)
Total Power Consumption (Including AVDD, DVIO, VREF pins)
MCP331x1D-10
at 1 Msps
PDISS_TOTAL
—
—
—
—
3.6
1.8
0.4
3.3
—
—
—
—
mW Averaged power for tACQ + tCNV
mW
mW
at 500 kSPS
at 100 kSPS
During Standby
PDISS_STBY
PDISS_TOTAL
PDISS_STBY
µW Input acquisition (tACQ)
MCP331x1D-05
at 500 kSPS
at 100 kSPS
During Standby
—
—
—
1.8
0.4
3.3
—
—
—
mW Averaged power for tACQ + tCNV
mW
µW Input acquisition (tACQ
)
Analog Inputs
Input Voltage Range
(Note 2)
VIN+
VIN-
FSR
VCM
-0.1
-0.1
-VREF
0
—
—
VREF + 0.1
VREF + 0.1
+VREF
V
Differential Input:
VIN = VIN+ – VIN-
Input Full-Scale Voltage Range
—
VPP Differential Input (Note 2, Note 4)
Input Common-mode Voltage
Range
VREF/2
VREF
Note 2
Input Sampling Capacitance
-3dB Input Bandwidth
CS
—
—
—
10
45
—
—
—
pF
MHz Note 1
ns Time delay between CNVST rising
edge and when input is sampled
Note 1
BW-3dB
Aperture Delay
(Note 1)
2.5
I
Leakage Current at Analog
Input Pin
—
±2.2
±200
nA During Standby
LEAK_AN_INPUT
System Performance
Sample Rate
(Throughput Rate)
fS
—
—
—
—
1
Msps MCP331x1D-10
kSPS MCP331x1D-05
bits MCP33151D-XX
bits MCP33141D-XX
LSB MCP33151D-XX
LSB MCP33141D-XX
LSB MCP33151D-XX
LSB MCP33141D-XX
500
—
Resolution
(No Missing Codes)
14
—
12
—
—
Integral Nonlinearity
INL
-1.5
—
±0.27
±0.07
±0.11
±0.05
+1.5
—
Differential Nonlinearity
DNL
-0.8
-0.3
+0.8
+0.3
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
DS20006219A-page 4
2019 Microchip Technology Inc.
MCP33151D/41D-XX
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF, +25°C is applied
IN
IN
LOAD_SDO
for typical values.
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Offset Error
Sym.
Min.
Typ.
Max.
Units
Conditions
-1.62
-1.33
—
±0.4
±0.4
±0.1
±1
1.62
1.33
—
mV MCP33151D-XX
mV MCP33141D-XX
µV/°C
Offset Error Drift with Temperature
Gain Error
GER
—
—
LSB MCP33151D-XX
LSB MCP33141D-XX
µV/°C
—
±0.2
±8
—
Gain Error Drift with
Temperature
—
—
Input Common-mode Rejection
Ratio
CMRR
PSRR
—
—
84
75
—
—
dB
Power Supply Rejection Ratio
Dynamic Performance
Signal-to-Noise Ratio
dB Note 5
SNR
MCP33151D-10 and MCP33151D-05: 14-bit ADC
—
—
83.9
79.2
83.7
78.8
—
—
—
—
dBFS VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
82.6
—
MCP33141D-10 and MCP33141D-05: 12-bit ADC
—
—
73.8
73.1
73.8
73.0
—
—
—
—
dBFS VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
73.4
—
Signal-to-Noise Distortion Ratio
SINAD
MCP33151D-10 and MCP33151D-05: 14-bit ADC
(Note 6)
—
—
—
—
83.9
79.2
83.6
77.8
—
—
—
—
dBFS VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
—
—
—
—
73.8
73.1
73.8
73.0
—
—
—
—
dBFS VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
2019 Microchip Technology Inc.
DS20006219A-page 5
MCP33151D/41D-XX
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF, +25°C is applied
IN
IN
LOAD_SDO
for typical values.
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Spurious Free Dynamic Range
SFDR
MCP33151D-10 and MCP33151D-05: 14-bit ADC
—
—
—
—
110.5
107.2
105.9
96.3
—
—
—
—
dBc VREF = 5V, fIN = 1 kHz
REF = 1.8V, fIN = 1 kHz
V
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
—
—
—
—
99.8
99.4
99.9
95.2
—
—
—
—
dBc VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
Total Harmonic Distortion
(first five harmonics)
THD
MCP33151D-10 and MCP33151D-05: 14-bit ADC
—
—
—
—
-105.0
-105.2
103.2
95.2
—
—
—
—
dBc VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
MCP33141D-10 and MCP33141D-05: 12-bit ADC
—
—
—
—
-100.7
-100.3
-100.4
-94.2
—
—
—
—
dBc VREF = 5V, fIN = 1 kHz
VREF = 1.8V, fIN = 1 kHz
VREF = 5V, fIN = 10 kHz
VREF = 1.8V, fIN = 10 kHz
System Self-Calibration
Self-Calibration Time
tCAL
—
—
400
550
—
ms Note 2
Number of SCLK Clocks for
Recalibrate Command
ReCalNSCLK
1024
clocks Includes clocks for data bits
Serial Interface Timing Information: See Serial Interface Timing Specifications
Digital Inputs/Outputs
High-level Input Voltage
VIH
0.7 × D
VIO
—
DVIO + 0.3
V
DVIO ≥ 2.3V
0.9 × D
VIO
DVIO < 2.3V
Low-level Input Voltage
VIL
-0.3
-0.3
—
—
0.3 × DVIO
0.2 × DVIO
—
V
V
DVIO ≥ 2.3V
DVIO < 2.3V
All digital inputs
Hysteresis of Schmitt Trigger
Inputs
VHYST
0.2 ×
DVIO
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
DS20006219A-page 6
2019 Microchip Technology Inc.
MCP33151D/41D-XX
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV = 1.8V, DV = 3.3V, V
= 5V,
A
DD
IO
REF
GND = 0V, Differential Analog Input (V ) = -1 dBFS sine wave, f = 10 kHz, C
= 20 pF, +25°C is applied
IN
IN
LOAD_SDO
for typical values.
MCP331x1D-10: Sample Rate (f ) = 1 Msps, SPI Clock Input (SCLK) = 60 MHz.
S
MCP331x1D-05: Sample Rate (f ) = 500 kSPS, SPI Clock Input (SCLK) = 30 MHz.
S
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Low-level Output Voltage
High-level Output Voltage
VOL
VOH
—
—
—
0.2 × DVIO
—
V
V
IOL = 500 µA (source)
IOH = -500 µA (sink)
0.8 × D
VIO
Input Leakage Current
Output Leakage Current
ILI
—
—
—
—
±1
±1
µA CNVST/SDI/SCLK = GND or DVIO
ILO
µA Output is high-Z, SDO = GND or
DVIO
Internal Capacitance
CINT
—
7
—
pF
TA = +25°C
(all digital inputs and outputs)
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
3: Decoupling capacitor is recommended on the following pins:
(a) AVDD pin: 1 µF ceramic capacitor, (b) DVIO pin: 0.1 µF ceramic capacitor,
(c) VREF pin: 10 µF tantalum capacitor.
4: Differential Input Full-Scale Range (FSR) = 2 × VREF
.
5: PSRR (dB) = -20 log(DVOUT/AVDD), where DVOUT = change in conversion result.
6: ENOB = (SINAD - 1.76)/6.02.
TABLE 1-2:
SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V,
DVIO = 3.3V, GND = 0V,
Differential Analog Input (AIN) = -1 dBFS sine wave, Resolution = 14-bit (MCP33151D-10), fIN = 10 kHz, Sample Rate (fS) = 1
Msps, +25°C is applied for typical values. All timings are measured at 50%. See Figure 1-1 for timing diagram.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Serial Clock Frequency
SCLK Period
fSCLK
tSCLK
—
—
—
100
—
MHz See tSCLK specification
10
ns
DVIO ≥ 3.3V, fSCLK = 100 MHz
(Max.)
12
16
—
—
—
—
DVIO ≥ 2.3V, fSCLK = 83.3 MHz
(Max.)
DVIO ≥ 1.7V, fSCLK = 62.5 MHz
(Max.)
SCLK Low Time
tSCLK_L
tSCLK_H
tDO
3
4.5
3
—
—
—
—
—
—
—
—
—
—
—
—
10
12
16
—
ns
ns
ns
DVIO ≥ 2.3V
DVIO ≥ 1.7V
DVIO ≥ 2.3V
SCLK High Time
4.5
—
—
—
10
DVIO ≥ 1.7V
Output Valid from SCLK Low
DVIO ≥ 3.3V
DVIO ≥ 2.3V
DVIO ≥ 1.7V
Quiet Time
tQUIET
ns
3-wire Operation:
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
2019 Microchip Technology Inc.
DS20006219A-page 7
MCP33151D/41D-XX
TABLE 1-2:
SERIAL INTERFACE TIMING SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +125°C, AVDD = 1.8V,
DVIO = 3.3V, GND = 0V,
Differential Analog Input (AIN) = -1 dBFS sine wave, Resolution = 14-bit (MCP33151D-10), fIN = 10 kHz, Sample Rate (fS) = 1
Msps, +25°C is applied for typical values. All timings are measured at 50%. See Figure 1-1 for timing diagram.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
SDI Valid Setup Time
CNVST Pulse Width Time
Output Enable Time
tSU_SDIH_CNV
tCNVH
5
—
—
—
—
—
—
—
10
15
15
ns
SDI High to CNVST Rising Edge
10
—
—
—
tEN
DVIO ≥ 2.3V
DVIO ≥ 1.7V
Output Disable Time
MCP331x1D-10
tDIS
Note 2
Sample Rate
fS
—
250
—
—
490
510
—
1
—
Msps Throughput Rate
Input Acquisition Time
Data Conversion Time
Time Between Conversions
MCP331x1D-05
tACQ
tCNV
tCYC
ns
ns
750
—
1
µs
tCYC = tACQ + tCNV, fS = 1 Msps
Sample Rate
fS
—
600
—
—
800
1200
—
500
—
kSPS Throughput Rate
Input Acquisition Time
Data Conversion Time
Time Between Conversions
tACQ
tCNV
tCYC
ns
ns
1400
—
2
µs
tCYC = tACQ + tCNV, fS = 500 kSPS
Note 1: This parameter is ensured by design and not 100% tested.
2: This parameter is ensured by characterization and not 100% tested.
TCYC = 1/fs
SDI = 1
tSU_SDIH_CNV
tCNVH
tEN (late CNV) (Note 1)
CNV (CS)
tSCLK
tQUIET
SC>K
1
tDO
2
3
4
5
12
13
14
tDIS
tSCLK_L
tSCLK_H
D9
“High” (with pull-up)
SDO
D13
EN (early CNV) (Note 2)
D12
D11
D10
D2
D1
D0
Hi-Z (with no pull-up)
t
ADC
State
Converting Phase
Input Acquisition
(tACQ
)
(tCNV
)
Note 1:
tEN when CNVST is lowered after tCNV (MAX).
2: tEN when CNVST is lowered before tCNV (MAX).
FIGURE 1-1:
Interface Timing Diagram (14-bit device). CNVST is Used as Chip Select. See
Section 6.0 “Digital Serial Interface” for More Details.
DS20006219A-page 8
2019 Microchip Technology Inc.
MCP33151D/41D-XX
TABLE 1-3:
TEMPERATURE CHARACTERISTICS
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Temperature Ranges
Operating Temperature
Range
TA
TA
-40
-65
—
—
+125
+150
°C
°C
Note 1
Note 1
Storage Temperature
Range
Thermal Package Resistance
Thermal Resistance,
MSOP-10
JA
JA
—
—
202
68
—
—
°C/W
°C/W
Thermal Resistance,
TDFN-10
Note 1: The internal junction temperature (Tj) must not exceed the absolute maximum specification of +150oC.
2019 Microchip Technology Inc.
DS20006219A-page 9
MCP33151D/41D-XX
NOTES:
DS20006219A-page 10
2019 Microchip Technology Inc.
MCP33151D/41D-XX
2.0
TYPICAL PERFORMANCE CURVES FOR 14-BIT DEVICES (MCP33151D-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
0.25
0.5
V
= 5V
V
= 5V
REF
REF
0.25
0
0.1
0
-0.1
-.25
-0.5
-0.25
0
4,096
8,192
Code
12,288
16,384
0
4,096
8,192
Code
12,288
16,384
FIGURE 2-1:
VREF = 5V.
INL vs. Output Code:
FIGURE 2-4:
DNL vs. Output Code:
V
REF = 5V.
0.5
0.25
0
0.25
V
= 1.8V
V
= 1.8V
REF
REF
0.10
0
-0.10
-0.25
-0.5
0
-0.25
0
4,096
8,192
Code
12,288
16,384
4,096
8,192
Code
12,288
16,384
FIGURE 2-2:
VREF = 1.8V.
INL vs. Output Code:
FIGURE 2-5:
VREF = 1.8V.
DNL vs. Output Code:
1.5
0.5
0.3
Max DNL (LSB)
1
Max INL (LSB)
0.5
0
0.1
-0.1
-0.3
-0.5
-0.5
-1
Min INL (LSB)
Min DNL (LSB)
-1.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 2-3:
INL vs. Reference Voltage.
FIGURE 2-6:
DNL vs. Reference Voltage.
2019 Microchip Technology Inc.
DS20006219A-page 11
MCP33151D/41D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
1
0.5
0
0.3
0.2
Max INL (LSB)
Max DNL (LSB)
Min DNL (LSB)
0.1
0
V
= 5V
V
= 5V
REF
REF
-0.1
-0.2
-0.3
Min INL (LSB)
-0.5
-1
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
FIGURE 2-7:
INL vs. Temperature.
FIGURE 2-10:
DNL vs. Temperature.
MCP33151D-10
MCP33151D-10
0
0
V
= 5V
V
= 1.8V
REF
REF
-20
-40
f
= 1 Msps
-20
-40
f = 1 Msps
s
s
SNR = 83.8 dBFS
SINAD = 83.8 dBFS
SFDR = 109.2 dBc
THD = -104.9 dBc
Offset = -1 LSB
SNR = 79.1 dBFS
SINAD = 79.0 dBFS
SFDR = 105.6 dBc
THD = -102.6 dBc
Offset = -2 LSB
-60
-60
-80
-80
Resolution = 14-bit
Resolution = 14-bit
-100
-120
-140
-160
-100
-120
-140
-160
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 2-8:
FFT for 10 kHz Input Signal:
FIGURE 2-11:
FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
fS = 1 Msps, VIN = -1 dBFS, VREF = 1.8V.
MCP33151D-05
MCP33151D-05
0
0
V
= 5V
V
= 1.8V
REF
REF
-20
-40
f
= 0.5 Msps
-20
-40
f = 0.5 Msps
s
s
SNR = 83.8 dBFS
SINAD = 83.7 dBFS
SFDR = 106.9 dBc
THD = -102.4 dBc
Offset = -1 LSB
SNR = 79.0 dBFS
SINAD = 78.9 dBFS
SFDR = 101.8 dBc
THD = -98.8 dBc
Offset = -2 LSB
-60
-60
-80
-80
Resolution = 14-bit
Resolution = 14-bit
-100
-120
-140
-160
-100
-120
-140
-160
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 2-9:
FFT for 10 kHz Input Signal:
FIGURE 2-12:
FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
fS = 500 kSPS, VIN = -1 dBFS, VREF = 1.8V.
DS20006219A-page 12
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
85
14
-95
-100
-105
-110
110
105
100
95
82.5
80
13.5
13
THD (dB)
SFDR(dB)
SNR (dB)
SINAD(dB)
ENOB
77.5
12.5
12
75
1.5
2
2.5
3
3.5
4
4.5
5
5.5
2
3
4
5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 2-13:
Reference Voltage.
SNR/SINAD/ENOB vs.
FIGURE 2-16:
Voltage.
THD/SFDR vs. Reference
84.1
84
79.8
79.6
79.4
79.2
79
SNR (dB)
SNR (dB)
SINAD(dB)
SINAD(dB)
83.9
83.8
78.8
V
= 5V
0
V
= 1.8V
0
83.7
83.6
REF
REF
78.6
78.4
-50
-50
50
Temperature (°C)
100
150
50
100
150
Temperature (°C)
FIGURE 2-14:
SNR/SINAD vs.
FIGURE 2-17:
SNR/SINAD vs.
Temperature: VREF = 5V.
Temperature: VREF = 1.8V.
-93
-94
-95
-96
-97
-98
-99
-100
103
102
101
100
99
-105
114
THD(dB)
SFDR(dB)
THD(dB)
SFDR(dB)
-106
-107
-108
112
110
108
V
= 1.8V
REF
98
97
V
= 5V
REF
96
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
FIGURE 2-15:
THD/SFDR vs.
FIGURE 2-18:
THD/SFDR vs.
Temperature: VREF = 5V.
Temperature: VREF = 1.8V.
2019 Microchip Technology Inc.
DS20006219A-page 13
MCP33151D/41D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
85
84
83
82
81
80
79
SNR (dB)
SNR (dB)
78.5
78
SINAD(dB)
SINAD(dB)
77.5
77
76.5
76
V
= 1.8V
V
= 5V
REF
REF
1
10
Input Frequency (kHz)
100
200
1
10
Input Frequency (kHz)
100
200
FIGURE 2-19:
SNR/SINAD vs.Input
FIGURE 2-22:
SNR/SINAD vs.Input
Frequency: VREF = 5V.
Frequency: VREF = 1.8V.
-70
-75
110
105
100
95
-80
-85
115
110
105
100
95
THD (dB)
THD (dB)
SFDR (dB)
SFDR (dB)
-80
-90
-85
-95
-90
90
-100
-105
-95
85
90
-100
-105
80
-110
-115
85
75
V
= 1.8V
V
= 5V
REF
REF
-110
70
80
1
10
100
200
1
10
Input Frequency (kHz)
100
200
Input Frequency (kHz)
FIGURE 2-20:
THD/SFDR vs. Input
FIGURE 2-23:
THD/SFDR vs. Input
Frequency: VREF = 5V.
Frequency: VREF = 1.8V.
85
80
SNR (dB)
SINAD(dB)
SNR (dB)
SINAD(dB)
84.5
84
79.5
79
83.5
78.5
V
= 5V
V
= 1.8V
REF
REF
83
-30
78
-30
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 2-21:
SNR/SINAD vs. Input
FIGURE 2-24:
SNR/SINAD vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 1.8V.
DS20006219A-page 14
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
-95
-100
-105
-110
115
110
105
100
-99
-100
-101
-102
-103
107
106
105
104
103
THD (dB)
SFDR(dB)
THD (dB)
SFDR(dB)
V
= 5V
V
= 1.8V
REF
REF
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
Amplitude (dBFS)
Amplitude (dBFS)
FIGURE 2-25:
THD/SFDR vs. Input
FIGURE 2-28:
THD/SFDR vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 1.8V.
80
14
85
14
79.2
78.4
77.6
76.8
76
13.4
12.8
12.2
11.6
11
84.2
83.4
82.6
81.8
81
13.6
13.2
12.8
12.4
12
SNR (dB)
SINAD(dB)
ENOB
SNR (dB)
SINAD(dB)
ENOB
V
= 5V
V
= 1.8V
REF
REF
25
50
100
250
500
1000
25
50
100
250
500
1000
Sample Rate (kSPS)
Sample Rate (kSPS)
FIGURE 2-26:
SNR/SINAD/ENOB vs.
FIGURE 2-29:
SNR/SINAD/ENOB vs.
Sample Rate: VREF = 5V.
Sample Rate: VREF = 1.8V.
-90
112
108
104
100
96
-90
114
110
106
102
98
THD(dB)
SFDR(dB)
THD(dB)
SFDR(dB)
-94
-98
-94
-98
-102
-106
-102
-106
-110
V
= 5V
V
= 1.8V
REF
REF
92
-110
25
94
25
50
100
250
500
1000
50
100
250
500
1000
Sample Rate (kSPS)
Sample Rate (kSPS)
FIGURE 2-27:
REF = 5V.
THD/SFDR vs Sample Rate:
FIGURE 2-30:
VREF = 1.8V.
THD/SFDR vs Sample Rate:
V
2019 Microchip Technology Inc.
DS20006219A-page 15
MCP33151D/41D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
5
86
84
82
80
78
76
74
72
10
10
V
= 5V
841918
REF
8
6
4
2
0
184932
V
= 5V
REF
21725
1
10-3
10-2
10-1
100
101
102
103
-3
-2
-1
0
1
2
3
Frequency (kHz)
Output Code
FIGURE 2-31:
Shorted Input Histogram:
FIGURE 2-34:
CMRR vs. Input Frequency:
V
REF = 5V.
V
REF = 5V.
1000
750
500
250
0
1.6
1.2
0.8
850
3.9
OFFSET ERROR
GAIN ERROR
650
450
250
50
3.0
2.0
1.1
0.2
-0.7
0.4
OFFSET ERROR
GAIN ERROR
0.0
-250
-500
-750
-0.4
-0.8
-1.2
-150
V
= 5V
60
V
= 1.8V
60
REF
REF
40
-1000
-1.6
80 100 120 140
-350
-1.6
80 100 120 140
-40 -20
0
20
40
-40 -20
0
20
Temperature (°C)
Temperature (°C)
FIGURE 2-32:
Offset and Gain Error vs.
FIGURE 2-35:
Offset and Gain Error vs.
Temperature: VREF = 5V.
Temperature: VREF = 1.8V.
MCP33151D-10
MCP33151D-05
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.5
0.4
0.3
0.2
0.1
0
3
2.4
1.8
1.2
0.6
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
0.1
0.2
0.3
0.4
0.5
Sample Rate (Msps)
FIGURE 2-33:
Power Consumption vs.
FIGURE 2-36:
Sample Rate, MCP33151D-05:
CLOAD_SDO = 20 pF.
Power Consumption vs.
Sample Rate, MCP33151D-10:
CLOAD_SDO = 20 pF.
DS20006219A-page 16
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note:
Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V, VREF = 5V,
GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33151D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33151D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
MCP33151D-10
MCP33151D-05
1
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.5
0.4
0.3
0.2
0.1
0
3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.4
1.8
1.2
0.6
0
I
(DV = 3.3V)
IO
I
(DV = 3.3V)
IO
IO_DATA
IO_DATA
I
(V
= 5V)
REF
I
(V
= 5V)
REF
REF
REF
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-37:
Power Consumption vs.
FIGURE 2-39:
Power Consumption vs.
Temperature, MCP33151D-10:
Temperature, MCP33151D-05:
CLOAD_SDO = 20 pF.
C
LOAD_SDO = 20 pF.
8
7
16
14
12
10
8
I
(AV = 1.8V)
DD
6
5
4
3
2
1
0
DDAN_STBY
Total Power Consumption
(DV = 3.3V)
6
I
IO_STBY
IO
4
2
I
(V
= 5V)
REF
REF_STBY
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 2-38:
Power Consumption vs.
Temperature during Shutdown (Standby).
2019 Microchip Technology Inc.
DS20006219A-page 17
MCP33151D/41D-XX
NOTES:
DS20006219A-page 18
2019 Microchip Technology Inc.
MCP33151D/41D-XX
3.0
TYPICAL PERFORMANCE CURVES FOR 12-BIT DEVICES (MCP33141D-XX)
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
0.2
0.2
V
= 5V
V
= 5V
REF
REF
0.1
0
0.1
0
-0.1
-0.2
-0.1
-0.2
0
1,024
2,048
Code
3,072
4,096
0
1,024
2,048
Code
3,072
4,096
FIGURE 3-1:
VREF = 5V.
INL vs. Output Code:
FIGURE 3-4:
DNL vs. Output Code:
V
REF = 5V.
0.2
0.1
0
0.2
V
= 1.8V
V
= 1.8V
REF
REF
0.1
0
-0.1
-0.1
-0.2
0
-0.2
0
1,024
2,048
Code
3,072
4,096
1,024
2,048
Code
3,072
4,096
FIGURE 3-2:
VREF = 1.8V.
INL vs. Output Code:
FIGURE 3-5:
VREF = 1.8V.
DNL vs. Output Code:
0.5
0.25
0
0.3
0.15
0
Max INL (LSB)
Min INL (LSB)
Max DNL (LSB)
Min DNL (LSB)
-0.25
-0.5
-0.15
-0.3
1.5
2
2.5
3
3.5
4
4.5
5
5.5
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 3-3:
INL vs. Reference Voltage.
FIGURE 3-6:
DNL vs. Reference Voltage.
2019 Microchip Technology Inc.
DS20006219A-page 19
MCP33151D/41D-XX
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
0.5
0.25
0
0.5
V
= 5V
V
= 5V
REF
REF
0.25
0
Max INL (LSB)
Min INL (LSB)
Max DNL (LSB)
Min DNL (LSB)
-0.25
-0.5
-0.25
-0.5
-40 -20
0
20
40
60
80 100 120 140
-40 -20
0
20
40
60
80 100 120 140
Temperature (°C)
Temperature (°C)
FIGURE 3-7:
INL vs. Temperature.
FIGURE 3-10:
DNL vs. Temperature.
MCP33141D-10
MCP33141D-10
0
0
V
= 5V
V
= 1.8V
REF
REF
f
= 1 Msps
f = 1 Msps
s
s
-20
-40
-20
-40
SNR = 73.9 dBFS
SINAD = 73.9 dBFS
SFDR = 100.6 dBc
THD = -98.7 dBc
Offset = 0 LSB
SNR = 73.0 dBFS
SINAD = 73.0 dBFS
SFDR = 101.0 dBc
THD = -100.0 dBc
Offset = -1 LSB
-60
-60
Resolution = 12-bit
Resolution = 12-bit
-80
-80
-100
-120
-100
-120
0
100
200
300
400
500
0
100
200
300
400
500
Frequency (kHz)
Frequency (kHz)
FIGURE 3-8:
FFT for 10 kHz Input Signal:
FIGURE 3-11:
FFT for 10 kHz Input Signal:
fS = 1 Msps, VIN = -1 dBFS, VREF = 5V.
fS = 1 Msps, VIN = -1 dBFS, VREF = 1.8V.
MCP33141D-05
MCP33141D-05
0
0
V
= 5V
V
= 1.8V
REF
REF
f
= 0.5 Msps
f = 0.5 Msps
s
s
-20
-40
-20
-40
SNR = 73.8 dBFS
SINAD = 73.8 dBFS
SFDR = 99.6 dBc
THD = -99.9 dBc
Offset = -1 LSB
SNR = 73.0 dBFS
SINAD = 73.0 dBFS
SFDR = 100.7 dBc
THD = -94.9 dBc
Offset = -1 LSB
-60
-60
Resolution = 12-bit
Resolution = 12-bit
-80
-80
-100
-120
-100
-120
0
50
100
150
200
250
0
50
100
150
200
250
Frequency (kHz)
Frequency (kHz)
FIGURE 3-9:
FFT for 10 kHz Input Signal:
FIGURE 3-12:
FFT for 10 kHz Input Signal:
fS = 500 kSPS, VIN = -1 dBFS, VREF = 5V.
fS = 500 kSPS, VIN = -1 dBFS, VREF = 1.8V.
DS20006219A-page 20
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
-96
-97
100.5
100
99.5
99
74
12.5
12
-98
73
72
71
-99
THD (dB)
SFDR(dB)
-100
-101
-102
-103
98.5
98
11.5
SNR (dB)
SINAD(dB)
ENOB
97.5
97
11
1.5
2
2.5
3
3.5
4
4.5
5
5.5
2
3
4
5
Reference Voltage (V)
Reference Voltage (V)
FIGURE 3-13:
Reference Voltage.
SNR/SINAD/ENOB vs.
FIGURE 3-16:
Voltage.
THD/SFDR vs. Reference
73.86
73.84
73.82
73.8
73.2
73.15
73.1
73.05
73
SNR (dB)
SNR (dB)
SINAD(dB)
SINAD(dB)
72.95
V
V
= 5V
REF
73.78
73.76
= 1.8V
0
REF
72.9
72.85
-50
-50
0
50
100
150
50
100
150
Temperature (°C)
Temperature (°C)
FIGURE 3-14:
SNR/SINAD vs.
FIGURE 3-17:
SNR/SINAD vs.
Temperature: VREF = 5V.
Temperature: VREF = 1.8V.
-98.2
99
-92
99
THD(dB)
SFDR(dB)
-93
-94
-95
-96
-97
98
97
96
95
94
-98.4
-98.6
-98.8
-99
98.5
98
THD(dB)
SFDR(dB)
V
= 1.8V
REF
97.5
97
V
= 5V
REF
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
-40 -20
0
20 40 60 80 100 120 140
Temperature (°C)
FIGURE 3-15:
THD/SFDR vs.
FIGURE 3-18:
THD/SFDR vs.
Temperature: VREF = 5V.
Temperature: VREF = 5V.
2019 Microchip Technology Inc.
DS20006219A-page 21
MCP33151D/41D-XX
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
73
72.6
SNR (dB)
SINAD(dB)
72.4
72.2
72
SNR (dB)
SINAD(dB)
72.9
72.8
72.7
72.6
72.5
71.8
71.6
71.4
71.2
71
V
= 1.8V
V
= 5V
REF
REF
1
10
Input Frequency (kHz)
100
200
1
10
Input Frequency (kHz)
100
200
FIGURE 3-19:
SNR/SINAD vs. Input
FIGURE 3-22:
SNR/SINAD vs. Input
Frequency: VREF = 5V.
Frequency: VREF = 1.8V.
-80
105
100
95
-75
-80
105
100
95
THD (dB)
SFDR (dB)
THD (dB)
SFDR (dB)
-85
-90
-95
-85
-90
90
90
-95
85
-100
85
-100
80
V
= 5V
V
= 1.8V
REF
REF
-105
80
-105
75
1
10
Input Frequency (kHz)
100
200
1
10
100
200
Input Frequency (kHz)
FIGURE 3-20:
THD/SFDR vs. Input
FIGURE 3-23:
THD/SFDR vs. Input
Frequency: VREF = 5V.
Frequency: VREF = 1.8V.
75
74
SNR (dB)
SINAD(dB)
SNR (dB)
SINAD(dB)
74.5
74
73.5
73
73.5
72.5
V
= 5V
V
= 1.8V
REF
REF
73
-30
72
-30
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-21:
SNR/SINAD vs. Input
FIGURE 3-24:
SNR/SINAD vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 1.8V.
DS20006219A-page 22
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
-90
-95
105
100
95
-90
-95
105
100
95
THD (dB)
SFDR(dB)
THD (dB)
SFDR(dB)
-100
-105
-100
-105
V
= 1.8V
-15
REF
V
= 5V
REF
90
90
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-10
-5
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-25:
THD/SFDR vs. Input
FIGURE 3-28:
THD/SFDR vs. Input
Amplitude: VREF = 5V.
Amplitude: VREF = 1.8V.
74
13
73
13
73.4
72.8
72.2
71.6
71
12.6
12.2
11.8
11.4
11
72.4
71.8
71.2
70.6
70
12.4
11.8
11.2
10.6
10
SNR (dB)
SINAD(dB)
ENOB
SNR (dB)
SINAD(dB)
ENOB
V
= 5V
V
= 1.8V
REF
REF
25
50
100
250
500
1000
25
50
100
250
500
1000
Sample Rate (kSPS)
Sample Rate (kSPS)
FIGURE 3-26:
SNR/SINAD/ENOB vs.
FIGURE 3-29:
SNR/SINAD/ENOB vs.
Sample Rate: VREF = 5V.
Sample Rate: VREF = 1.8V.
-88
110
106
102
98
-86
109
105
101
97
THD(dB)
SFDR(dB)
THD(dB)
SFDR(dB)
-92
-96
-90
-94
-98
-100
-104
-108
-102
93
94
V
= 1.8V
V
= 5V
REF
REF
-106
25
89
90
50
100
250
500
1000
25
50
100
250
500
1000
Sample Rate (kSPS)
Sample Rate (kSPS)
FIGURE 3-27:
Rate: VREF = 5V.
THD/SFDR vs. Sample
FIGURE 3-30:
Rate: VREF = 1.8V.
THD/SFDR vs. Sample
2019 Microchip Technology Inc.
DS20006219A-page 23
MCP33151D/41D-XX
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
105
86
10
V
= 5V
84
82
80
78
76
74
72
REF
779082
8
6
4
2
0
269494
V
= 5V
100
REF
10-3
10-2
10-1
101
102
103
-3
-2
-1
0
1
2
3
Frequency (kHz)
Output Code
FIGURE 3-31:
Shorted Input Histogram:
FIGURE 3-34:
CMRR vs. Input Frequency:
V
REF = 5V.
V
REF = 5V.
1500
1000
500
0.6
1000
800
600
400
200
0
1.1
OFFSET ERROR
OFFSET ERROR
GAIN ERROR
0.9
GAIN ERROR
0.4
0.7
0.2
0.5
0
0.0
0.2
-500
-1000
-1500
-2000
-0.2
-0.4
-0.6
-0.8
-1.0
0.0
-200
-400
-600
-800
-0.2
-0.5
-0.7
-0.9
-1.1
V
= 5V
60
V
= 1.8V
60
REF
40
REF
-2500
-1000
-40 -20
0
20
80 100 120 140
-40 -20
0
20
40
80 100 120 140
Temperature (°C)
Temperature (°C)
FIGURE 3-32:
Offset and Gain Error vs.
FIGURE 3-35:
Offset and Gain Error vs.
Temperature: VREF = 5V.
Temperature: VREF = 1.8V.
MCP33141D-10
MCP33141D-05
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.5
0.4
0.3
0.2
0.1
0
3
2.4
1.8
1.2
0.6
0
Total Power Conon
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
Sample Rate (Msps)
1
0.1
0.2
0.3
0.4
0.5
Sample Rate (Msps)
FIGURE 3-33:
Sample Rate, MCP33141D-10:
LOAD_SDO = 20 pF.
Power Consumption vs.
FIGURE 3-36:
Sample Rate, MCP33141D-05:
CLOAD_SDO = 20 pF.
Power Consumption vs.
C
DS20006219A-page 24
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note:
Note: Unless otherwise specified, all parameters apply for TA = +25°C, AVDD = 1.8V, DVIO = 3.3V,
VREF = 5V, GND = 0V, Differential Analog Input (VIN) = -1 dBFS, fIN = 10 kHz, CLOAD_SDO = 20 pF.
MCP33141D-10: Sample Rate (fS) = 1 Msps, SPI Clock Input = 60 MHz.
MCP33141D-05: Sample Rate (fS) = 500 kSPS, SPI Clock Input = 30 MHz.
MCP33141D-10
MCP33141D-05
1
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0.5
0.4
0.3
0.2
0.1
0
3
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.4
1.8
1.2
0.6
0
I
(V
= 5V)
REF
REF
I
(V
= 5V)
REF
REF
I
(DV = 3.3V)
IO
IO_DATA
I
(DV = 3.3V)
IO
IO_DATA
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 3-37:
Power Consumption vs.
FIGURE 3-39:
Power Consumption vs.
Temperature, MCP33141D-10:
Temperature, MCP33141D-05:
CLOAD_SDO = 20 pF.
C
LOAD_SDO = 20 pF.
8
7
16
14
12
10
8
I
(AV = 1.8V)
DD
6
DDAN_STBY
5
Total Power Consumption
(DV = 3.3V)
4
3
2
1
0
6
I
IO_STBY
IO
4
2
I
(V
= 5V)
REF
REF_STBY
0
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 3-38:
Power Consumption vs.
Temperature during Shutdown (Standby).
2019 Microchip Technology Inc.
DS20006219A-page 25
MCP33151D/41D-XX
NOTES:
DS20006219A-page 26
2019 Microchip Technology Inc.
MCP33151D/41D-XX
4.0
PIN DESCRIPTIONS
MSOP-10
TDFN-10 *
* Includes Exposed Thermal Pad (see Table 4-1).
FIGURE 4-1:
Pin Configurations.
TABLE 4-1:
PIN FUNCTION TABLE
Pin Number
MSOP-10 TDFN-10
Pin Name
Description
1
1
VREF
AVDD
Reference voltage input (AVDD - 5.1V).
This pin should be decoupled with a 10 F tantalum capacitor.
2
2
DC supply voltage input for analog section (1.8V).
This pin should be decoupled with a 1 F ceramic capacitor.
3
4
5
3
4
5
AIN+
AIN-
Differential positive analog input.
Differential negative analog input.
GND
Power supply ground reference. This pin is a common ground for both the
analog power supply (AVDD) and digital I/O supply (DVIO).
6
6
CNVST
Conversion-start control and active-low SPI chip-select digital input.
A new conversion is started on the rising edge of CNVST.
When the conversion is complete, output data is available at SDO by lowering
CNVST.
7
8
7
8
SDO
SPI-compatible serial digital data output: ADC conversion data is shifted out
by SCLK clock, with MSB first.
SCLK
SPI-compatible serial data clock digital input.
The ADC output is synchronously shifted out by this clock.
9
9
SDI
SPI-compatible serial data digital input. Tie to DVIO for normal operation.
10
10
DVIO
DC supply voltage for digital input/output interface (1.7V - 5.5V).
This pin should be decoupled with a 0.1 µF ceramic capacitor.
—
11
EP
Exposed Thermal Pad. Not internally bonded (NC).
2019 Microchip Technology Inc.
DS20006219A-page 27
MCP33151D/41D-XX
4.1
Supply Voltages (AV , DV )
4.3
Power-Up Sequence and
Auto-Calibration
DD
IO
The device has two power supply pins: (a) 1.8V
analog power supply (AVDD), and (b) 1.7V to 5.5V
digital input/output interface power supply (DVIO).
Since DVIO has a very wide voltage range, some I/O
interface signal parameters have slightly different
timing specifications depending on the DVIO value.
See Serial Interface Timing Specifications for details.
The device will perform an automatic calibration on
power-up approximately 40 ms after all three power
rails (AVDD, DVIO, and VREF) are powered by their
respective voltage supplies. The calibration process
will take approximately 400 ms to complete before the
device will be ready for acquisition. To avoid potential
auto-calibration issues, all supplies must be fully
stabilized < 40 ms from the moment power is initially
supplied. All digital activity must be avoided prior to
and during device calibration. At higher operating
temperatures (>85°C) it may be necessary to provide
additional time for the device to complete calibration
(up to 550ms at 125°C). Therefore it is advisable to
wait at least 450-500 ms following power-on before
initiating any other activity. Otherwise, it may be
necessary to send a manual recalibration command to
ensure proper operation. See Figure 4-2 for example
power-on operation timing, and refer to Section 6.2
“Recalibrate Command” for more details regarding
initiating manual recalibration. Once the device
finishes calibration it will automatically enter
Acquisition (ACQ) mode.
Note:
Proper decoupling capacitors (1 µF to
AVDD, 0.1 µF to DVIO) should be mounted
as close as possible to the respective
pins.
4.2
Reference Voltage (V
)
REF
The device requires a single-ended external reference
voltage (VREF). The external input reference range is
from AVDD to 5.1V. This reference voltage sets the
differential input full-scale range from -VREF to +VREF
.
The reference pin needs a tantalum decoupling
capacitor (10 F, 10V rating). Additional multiple
ceramic capacitors can be added in parallel to
decouple high-frequency noise.
4.2.1
VOLTAGE REFERENCE
SELECTION
The performance of the voltage reference has a large
impact on the accuracy of high-precision data
acquisition systems. The voltage reference should
have high accuracy, low-noise, and low-temperature
drift. A ±0.1% output accuracy of the reference directly
corresponds to ±0.1% absolute accuracy of the ADC
output. The RMS output noise voltage of the reference
must be less than 1/2 LSB of the ADC.
Device Calibration (tCAL = ~ϰ00ms)
Wait (tWAIT = ~40 ms)
ADC
State
ACQUISITION MODE
WAIT
CALIBRATION
AVDD
VREF
DVIO
FIGURE 4-2:
Note:
Power-Up Sequence and Auto-Calibration Timing Diagram.
Unlike manual recalibration, there will be no activity on SDO to indicate completion of auto-calibration.
Refer to Section 6.2 “Recalibrate Command” for more details.
DS20006219A-page 28
2019 Microchip Technology Inc.
MCP33151D/41D-XX
5.0
DEVICE OVERVIEW
When the MCP33151D/41D-XX is first powered-up, it
automatically performs a self-calibration and enters a
low-current input acquisition mode (Standby).
VREF
+
Sample VIN
VT = 0.6V
D1
+
+
+
SW1
RSON
CS
SW2
+
The external reference voltage (VREF), ranging from
AVDD to 5.1V, sets the differential input full-scale range
AIN
(350Ω) (10 pF)
CPIN
(FSR) from -VREF to +VREF
.
D2
ILEAKAGE
(~ 1 nA)
The differential input signal needs an appropriate input
common-mode voltage from 0V to VREF, depending on
the input signal condition. VREF/2 is typically used for a
symmetric differential input.
VREF
VT = 0.6V
-
Sample VIN
D1
During input acquisition (Standby), the internal input
sampling capacitors are connected to the input signal,
while most of the internal analog circuits are shutdown
to save power. During this input acquisition time
(tACQ), the device consumes a typical current of
1.5 µA.
-
-
-
SW1
RSON
CS
SW2
-
AIN
(350Ω) (10 pF)
CPIN
D2
ILEAKAGE
(~ 1 nA)
The user can operate the device with an easy-to-use,
SPI-compatible, 3-wire interface.
Where:
CS+, CS
The device initiates data conversion on the rising edge
of the conversion-start control (CNVST). The data
conversion time (tCNV) is set by the internal clock.
Once the conversion is complete and the host lowers
CNVST, the output data is available on SDO and the
device automatically starts the next input acquisition.
During this input acquisition time (tACQ), the user can
clock out the output data by providing the
SPI-compatible serial clock (SCLK).
-
=
=
=
input sample and hold capacitor ≈ 10 pF,
On-resistance of the sampling switch ≈ 350
Package pin + ESD capacitor ≈ 2 pF.
RSON
CPIN
FIGURE 5-1:
Analog Input Circuit.
Simplified Equivalent
5.1.1 ABSOLUTE MAXIMUM INPUT
VOLTAGE RANGE
The device provides conversion data with no missing
codes. This ADC device family has a large input
full-scale range, high precision, high throughput with
no output latency, and is an ideal choice for various
ADC applications.
The input voltage at each input pin (AIN+ and AIN-)
must meet the following absolute maximum input
voltage limits:
• (VIN+, VIN-) < VREF + 0.1V
• (VIN+, VIN-) > GND - 0.1V
5.1
Analog Inputs
Note:
The ESD diodes at the analog input pins
are biased from VREF. Any input voltage
outside the absolute maximum range can
turn on the input ESD protection diodes
and results in input leakage current which
may cause conversion errors and
permanent damage to the device. Care
must be taken in setting the input voltage
ranges so that the input voltage does not
exceed the absolute maximum input
voltage range.
Figure 5-1 shows a simplified equivalent circuit of the
differential input architecture with a switched capacitor
input stage. The input sampling capacitors
(CS+ and CS ) are about 10 pF each. The back-to-back
-
diodes (D1 – D2) at each input are ESD protection
diodes. Note that these ESD diodes are tied to VREF, so
that each input signal can swing from 0V to +VREF and
from -VREF to +VREF differentially.
During input acquisition (Standby), the sampling
switches are closed and each input sees the sampling
capacitor (≈ 10 pF) in series with the on-resistance of
the sampling switch, RSON (≈ 350).
For high-precision data conversion applications, the
input voltage needs to be fully settled within 1/2 LSB
during the input acquisition period (tACQ). The settling
time is directly related to the source impedance: A
lower impedance source results in faster input settling
time. Although the device can be driven directly with a
low impedance source, using a low-noise input driver,
such as the MCP6D11, is highly recommended.
2019 Microchip Technology Inc.
DS20006219A-page 29
MCP33151D/41D-XX
The front-end differential driver provides a low output
impedance, which provides fast settling of the analog
inputs during the acquisition phase and provides
isolation between the signal source and the ADC. The
RC low-pass anti-aliasing filter band-limits the output
noise of the input driver and attenuates the kick-back
noise spikes from the ADC during conversion.
5.1.2
INPUT VOLTAGE RANGE
The differential input (VIN) and common-mode voltage
(VCM) at the input pins are defined by Equation 5-1:
EQUATION 5-1:
DIFFERENTIAL INPUT
VIN = VIN+ – VIN-
Figure 5-2 is the reference circuit that is used to collect
most of the linearity performance data shown in
Section 1.0 “Key Electrical Characteristics”.
VIN+ + VIN-
VCM = ---------------------------
2
The differential input driver shown in Figure 5-2 can be
replaced with a low noise dual-channel op-amp. See
Section 5.3 “ADC Input Driver Selection” for the
driver selection.
Where:
VIN+
VIN-
=
=
the input at the AIN+ pin,
the input at the AIN- pin.
5.2.2
ARBITRARY WAVEFORM INPUT
SIGNALS
The input signal swings around an input
common-mode voltage (VCM), typically centered at
VREF/2 for the best performance.
The MCP33151D/41D-XX can convert input signals
with arbitrary waveforms at the inputs AIN+ and AIN-.
These inputs can be symmetric, non-symmetric or
independent with respect to each other.
The absolute value of the differential input (VIN) needs
to be less than the reference voltage. The device will
output saturated output codes if the absolute value of
the input (VIN) is greater than the reference voltage.
In the arbitrary input configuration, each ADC analog
input is connected to a single ended source ranging
from 0V to VREF. In this case, the ADC converts the
voltage difference between the two input signals.
Figure 5-4 shows the configuration example for the
arbitrary input signals.
Note:
Saturation output codes:
01111111111111 for VIN > VREF
10000000000000 for VIN < -VREF
The differential input full-scale voltage range (FSR) is
given by the external reference voltage (VREF) setting
(see Equation 5-2).
5.2.3
SINGLE-ENDED INPUT SIGNALS
Although the MCP33151D/41D-10 is a fully-differential
input device, it can also convert single-ended input
signals. The most commonly recommended
single-ended configurations are:
EQUATION 5-2:
Input Full-Scale Range (FSR) = 2VREF
Input Range:
FSR AND INPUT RANGE
–VREF VIN VREF – 1 LSB
• pseudo-differential bipolar configuration, and
• pseudo-differential unipolar configuration.
5.2
Analog Input Conditioning
Circuits
5.2.3.1
Pseudo-Differential Bipolar
Configuration
In the pseudo-differential bipolar configuration, one of
the ADC analog inputs (typically AIN-) is driven with a
fixed DC voltage (typically VREF/2), while the other
(AIN+) is connected to a single-ended signal in the
The MCP33151D/41D-XX supports various input
types, such as: fully-differential inputs, arbitrary
waveform inputs and single-ended inputs.
range 0V to VREF
.
5.2.1
FULLY-DIFFERENTIAL INPUT
SIGNALS
In this case, the ADC converts the voltage difference
between the single-ended signal and the DC voltage.
Figure 5-5 shows the configuration example and
Figure 5-6 shows its transfer function.
The MCP33151D/41D-XX provides the best linearity
performance with fully-differential inputs. Figure 5-2
shows an example of
a
fully-differential input
conditioning circuit with a differential input driver
followed by an RC anti-aliasing filter. Figure 5-3 shows
its transfer function.
The differential input (VIN) between the two differential
ADC analog input pins (AIN+, AIN-) swings from -VREF
to +VREF centered at the input common-mode voltage
(VOCM).
DS20006219A-page 30
2019 Microchip Technology Inc.
MCP33151D/41D-XX
5.2.3.2
Pseudo-Differential Unipolar
Configuration
In the pseudo-differential unipolar input configuration,
one of the ADC analog inputs (typically AIN-) is
connected to ground, while the other (AIN+) is
connected to a single ended signal in the range 0V to
VREF
.
In this case, the ADC converts the voltage difference
between the single ended signal and ground.
Figure 5-7 shows the configuration example and
Figure 5-8 shows its transfer function.
VREF
Voltage Reference
(MCP1501)
VDC
CR
10 μF
1.8V
AVDD
1.8V to 5.5V
DVIO
(Note 2)
RF
Differential
Inputs
VREF
VREF/2
0V
VREF
RG
VREF/2
RG
VREF
R1
AIN
MCP331x1D-XX
AIN
+
0V
SDI
CNVST
SCLK
C1
VOCM
Host Device
R1
VREF
0V
-
(PIC32MZ)
VREF
VREF/2
0V
SDO
C1
GND
RF
1
fc =
Input Driver
(Note 1)
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of MCP6D11 differential driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 5-2:
Input Conditional Circuit for Fully-Differential Input.
Digital Output Code (Two’s Complement)
2n/2 - 1
-VREF
+VREF - 1 LSB
VIN
Differential Input Voltage
0
- 2n/2
Available V range
IN
FIGURE 5-3:
Transfer Function for Figure 5-2.
2019 Microchip Technology Inc.
DS20006219A-page 31
MCP33151D/41D-XX
VREF
Voltage Reference
(MCP1501)
VDC
CR
1.8V
1.8V to 5.5V
DVIO
(Note 2)
10 μF
Arbitrary Waveform
Differential Input
VREF
AVDD
R1
VREF
0V
AIN
MCP331x1D-XX
AIN
+
SDI
CNVST
SCLK
C1
Host Device
R1
VREF
0V
-
(PIC32MZ)
SDO
C1
GND
Low Noise Input Buffer
1
(Note 1)
fc =
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 5-4:
Input Configuration for Arbitrary Waveform Input Signals.
VREF
Voltage Reference
(MCP1501)
VDC
CR
1.8V
1.8V to 5.5V
(Note 2)
10 μF
Low Noise Input Buffer
(Note 1)
VREF
VREF
AVDD
DVIO
VREF/2
0V
Single-Ended Input
R1
VREF
AIN
MCP331x1D-XX
AIN
+
SDI
CNVST
SCLK
C1
0V
Host Device
R1
-
(PIC32MZ)
SDO
VREF/2
C1
GND
1 μF
1
fc =
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 5-5:
Pseudo-Differential Bipolar-Input Configuration for Single-Ended Input Signal.
Digital Output Code (Two’s Complement)
2n/2 - 1
2n/4
-VREF/2
-VREF
VIN
+VREF - 1 LSB
0
+VREF/2
Analog Input Voltage
- 2n/4
Available V range
IN
- 2n/2
FIGURE 5-6:
Transfer Function for Figure 5-5.
DS20006219A-page 32
2019 Microchip Technology Inc.
MCP33151D/41D-XX
VREF
Voltage Reference
(MCP1501)
VDC
CR
1.8V
1.8V to 5.5V
(Note 2)
10 μF
Low Noise Input Buffer
(Note 1)
VREF
VREF
AVDD
DVIO
VREF/2
0V
Single-Ended Input
R1
VREF
VREF/2
0V
AIN
MCP331x1D-XX
AIN
+
SDI
CNVST
SCLK
C1
Host Device
R1
-
(PIC32MZ)
SDO
C1
GND
1
fc =
2πR1C1
Note 1: Contact Microchip Technology Inc. for availability of the low-noise driver application circuits.
2: Contact Microchip Technology Inc. for the MCP1501 voltage reference application circuit.
FIGURE 5-7:
Pseudo-Differential Unipolar-Input Configuration for Single-Ended Input Signal.
Digital Output Code (Two’s Complement)
2n/2 - 1
2n/4
-VREF/2
-VREF
VIN
0
+VREF/2 +VREF
Analog Input Voltage
Available V range
IN
- 2n/4
- 2n/2
FIGURE 5-8:
Transfer Function for Figure 5-7.
2019 Microchip Technology Inc.
DS20006219A-page 33
MCP33151D/41D-XX
When the ADC is operating with a full-scale input
range, the ADC input-referred RMS noise is
approximated as shown in Equation 5-5:
5.3
ADC Input Driver Selection
The noise and distortion of the ADC input driver can
degrade the dynamic performance (SNR, SFDR, and
THD) of the overall ADC application system. Therefore,
the ADC input driver needs better performance
specifications than the ADC itself. The data sheet of the
driver typically shows the output noise voltage and
harmonic distortion parameters.
EQUATION 5-5:
ADC INPUT-REFERRED
NOISE
VN_ADC Input-Referred Noise (V)
SNR
–----------
Figure 5-9 shows a simplified system noise presenta-
tion block diagram for the front-end driver and ADC.
FSR
20
= --------- 1 0
2 2
SNR
–----------
20
VREF
= -----------10
2
Front-End Driver
, for differential input;
VN_ADC
Input-Referred Noise
SNR
–----------
20
R
VREF
= -----------10
2 2
, for single-ended input.
-
-
+
ADC
+
C
VN_RMS_Driver
Noise
Where FSR is the input full-scale range of the ADC.
• Noise Contribution from the Front-End Driver:
FIGURE 5-9:
Representation.
Simplified System Noise
The noise from the input driver can degrade the ADC’s
SNR performance. Therefore, the selected input driver
should have the lowest possible broadband noise
density and 1/f noise. When an anti-aliasing filter is
used after the input driver, the output noise density of
the input driver is integrated over the -3 dB bandwidth
of the filter.
• Unity Gain Bandwidth:
An input driver with higher bandwidth usually results in
better overall linearity performance. Typically, the
driver should have the unity gain bandwidth greater
than 5 times the -3 dB cutoff frequency of the
anti-aliasing filter:
Equation 5-6 shows the RMS output noise voltage
calculation using the RC filter’s bandwidth and noise
density (eN) of the input driver. GN in Equation 5-6 is
the noise gain of the driver amplifier and becomes 1 for
a unity gain buffer driver.
EQUATION 5-3:
BANDWIDTH
REQUIREMENT FOR ADC
INPUT DRIVER
(Hz)
BW
5 f
Input Driver
B
EQUATION 5-6:
NOISE FROM FRONT-END
DRIVER AMPLIFIER
5
, for a single-pole RC filter.
--------------
2RC
Where:
eN
VN_RMS_Driver_Noise = GN------ fB
V
fB = -3 dB bandwidth of RC anti-aliasing
2
filter, as shown in Figure 5-9.
Where eN is the broadband noise density (V/√Hz) of
the front-end driver amplifier and is typically given in
its data sheet.
• Distortion:
The nonlinearity characteristics of the input driver
cause distortions in the ADC output. Therefore, the
input driver should have less distortion than the ADC
itself. The recommended total harmonic distortion
(THD) of the driver is at least 10 dB less than that of the
ADC:
In Equation 5-6, 1/f noise (eNFlicker) is ignored
assuming it is very small compared to the broadband
noise (eN).
For high precision ADC applications, the noise
contribution from the front-end input driver amplifier is
typically constrained to be less than about 20% (or 1/5
times) of the ADC input-referred noise as shown in
Equation 5-7:
EQUATION 5-4:
RECOMMENDED THD
FOR ADC INPUT DRIVER
THDInput Driver THDADC – 10
(dB)
EQUATION 5-7:
RECOMMENDED ADC
INPUT DRIVER NOISE
• ADC Input-Referred Noise:
1
5
V
--V
N_RMS_Driver_Noise
N_ADC_Input-Referred_Noise
DS20006219A-page 34
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Using Equation 5-5 to Equation 5-7, the recommended
noise voltage density (eN) limit of the ADC input driver
is expressed in Equation 5-8:
TABLE 5-2:
NOISE VOLTAGE DENSITY
(eN) OF INPUT DRIVER FOR
MCP33141D-XX
ADC Input
EQUATION 5-8:
NOISE DENSITY FOR ADC
INPUT DRIVER
RC
Filter
Driver
Amplifier
(GN = 1)
ADC (Note 1)
eN
1
5
GN------ fB --VN_ADC_Input_Referred_Noise
2
ADC
Input-Referred
Noise
Noise
Voltage
SNR
(dBFS)
fB
(Note 2)
(a) eN for differential input ADC:
V
REF
Density (e )
N
SNR
–----------
1
1
20
V
Hz
1.8V
3V
72
319.7 µV
443.2 µV
721.9 µV
3 MHz 29.5 nV/√Hz
4 MHz 25.5 nV/√Hz
5 MHz 22.8 nV/√Hz
3 MHz 40.8 nV/√Hz
4 MHz 35.4 nV/√Hz
5 MHz 31.6 nV/√Hz
3 MHz 66.5 nV/√Hz
4 MHz 57.6 nV/√Hz
5 MHz 51.5 nV/√Hz
eN ---------------------- V REF10
5GN
----------
fB
(a) eN for single-ended input ADC:
73.6
73.8
SNR
–----------
1
1
20
V
eN ------------------------- V REF10
10GN
----------
fB
Hz
5V
Using Equation 5-8, the recommended maximum
noise voltage density limit for unity gain input driver for
differential input ADC can be estimated. Table 5-1 and
Table 5-2 show a few example results with GN = 1.
These tables may be used as a reference when
selecting the ADC input driver amplifier.
Note 1: See Equation 5-5 for the ADC
input-referred noise calculation for
differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing
filter.
TABLE 5-1:
NOISE VOLTAGE DENSITY
(EN) OF INPUT DRIVER FOR
MCP33151D-XX
ADC Input
RC
Filter
Driver
Amplifier
(GN = 1)
ADC (Note 1)
ADC
Input-Referred
Noise
Noise
Voltage
Density (e )
SNR
(dBFS)
fB
(Note 2)
V
REF
N
1.8V 78.8
146 µV
172 µV
231 µV
3 MHz 13.5 nV/√Hz
4 MHz 11.7 nV/√Hz
5 MHz 10.4 nV/√Hz
3 MHz 15.9 nV/√Hz
4 MHz 13.8 nV/√Hz
5 MHz 12.3 nV/√Hz
3 MHz 21.3 nV/√Hz
4 MHz 18.4 nV/√Hz
5 MHz 16.5 nV/√Hz
3V
5V
81.8
83.7
Note 1: See Equation 5-5 for the ADC
input-referred noise calculation for
differential input.
2: fB is -3dB bandwidth of the RC anti-aliasing
filter.
2019 Microchip Technology Inc.
DS20006219A-page 35
MCP33151D/41D-XX
5.4.2
DATA CONVERSION PHASE
5.4
Device Operation
The start of the conversion is controlled by CNVST. On
the rising edge of CNVST, the sampled charge is
locked (sample switches are opened) and the ADC
performs the conversion. Once a conversion is started,
it will not stop until the current conversion is complete.
When the MCP33151D/41D-XX is first powered-up, it
self-calibrates internal systems and automatically
enters Input Acquisition mode. The device operates in
two phases: (a) Input Acquisition (Standby) and (b)
Data Conversion. Figure 5-10 shows the ADC’s
operating sequence.
The data conversion time (tCNV
) is not user
controllable. After the conversion is complete and the
host lowers CNVST, the output data is presented on
SDO.
5.4.1
INPUT ACQUISITION PHASE
(STANDBY)
Any noise injection during the conversion phase may
affect the accuracy of the conversion. To reduce
external environment noise, minimize I/O events and
running clocks during the conversion time.
During the input acquisition phase (tACQ), also called
+
Standby, the two input sampling capacitors, CS and
-
CS , are connected to the AIN+ and AIN- pins,
respectively. The input voltage is sampled until a rising
edge on CNVST is detected. The input voltage should
The output data is clocked out MSB first. While the
output data is being transferred, the device enters the
next input acquisition phase.
be fully settled within 1/2 LSB during tACQ
.
The acquisition time (tACQ) is user-controllable. The
system designer can increase the acquisition time
(tACQ) as much as needed to reduce sampling rate for
additional power savings.
Note:
Transferring output data during the
acquisition phase can disturb the next
input sample. It is highly recommended to
allow at least tQUIET (10 ns, typical)
between the last edge on the SPI interface
and the rising edge on CNVST. See
Figure 1-1 for tQUIET
.
tCYC = 1/fS
Input Acquisition
Input Acquisition
(Standby)
Data Conversion
tCNV
(Standby)
Operating
Condition
tACQ
tACQ
MCP331x1D-10: 490 ns (typical)
MCP331x1D-05: 800 ns (typical)
MCP331x1D-10: 510 ns (typical)
MCP331x1D-05: 1200 ns (typical)
MCP331x1D-10: 490 ns (typical)
MCP331x1D-05: 800 ns (typical)
(a) At the falling edge of CNVST,
ADC output is available at SDO.
(a) ADC acquires input sample #1. (a) Conversion is initiated at the rising edge of CNVST.
(b) No ADC output is available yet.
(b) All circuits are turned-on.
(b) ADC output can be clocked out
by providing clocks.
(c) Most analog circuits are
turned off.
(c) ADC output is not available yet.
(c) ADC acquires input sample #2.
MCP331x1D-10: ~0.66 mA
MCP331x1D-05: ~0.33 mA
(d) Most analog circuits are turned off.
IDDAN
I
~ 1.5 µA
Off
(a) Device is first powered-up and
(b) Performs a power-up self-calibration.
Output Data
SDO
FIGURE 5-10:
Device Operating Sequence.
DS20006219A-page 36
2019 Microchip Technology Inc.
MCP33151D/41D-XX
5.4.3
SAMPLE THROUGHPUT RATE
EQUATION 5-10: SPI CLOCK FREQUENCY
REQUIREMENT
The device completes data conversion within the
maximum specification of the data conversion time
(tCNV). The continuous input sample rate is the inverse
of the sum of input acquisition time (tACQ) and data
conversion time (tCNV). Equation 5-9 shows the
continuous sample rate calculation using the minimum
and maximum specifications of the input acquisition
time (tACQ) and data conversion time (tCNV).
tACQ = N TSCLK + tQUIET + tEN
1
N
fSCLK = -------------- = ----------------------------------------------------
TSCLK tACQ – tQUIET + tEN
Where:
fSCLK
=
minimum SPI serial clock
frequency required to transfer all
N-bits of output data during tACQ
EQUATION 5-9:
SAMPLE RATE
N
TSCLK
=
=
=
=
number of output data bits
Period of SPI clock
1
Sample Rate = ----------------------------------
tACQ + tCNV
N × TSCLK
tQUIET
Output data window
(a) MCP331X1D-10:
Quiet time between the last output
bit and beginning of the next
conversion start
1
Sample Rate = ------------------------------------------- = 1 Msps
250 ns + 750 ns
=
=
=
10 ns (Min.)
(b) MCP331X1D-05:
tEN
Output enable time
10 ns (Max.) with DVIO ≥ 2.3V
1
Sample Rate = ---------------------------------------------- = 500 kSPS
600 ns + 1400 ns
Note:
Refer to Serial Interface Timing
Specifications for relevant timing
information and see Figure 1-1 for
interface timing diagram.
5.4.4
SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by Equation 5-10:
5.4.5
SERIAL SPI CLOCK FREQUENCY
REQUIREMENT
The ADC output is collected during the input acquisition
time (tACQ). For continuous input sampling and data
conversion sequence, the SPI clock frequency should
be fast enough to clock out all output data bits during
the input acquisition time (tACQ). For the continuous
sampling rate (fS), the minimum SPI clock frequency
requirement is determined by Equation 5-10:
2019 Microchip Technology Inc.
DS20006219A-page 37
MCP33151D/41D-XX
5.5
Transfer Function
5.6
Digital Output Code
The differential analog input is VIN = (VIN+) – (VIN-).
The LSB size is given by Equation 5-11. and an
example of LSB size vs. reference voltage is
summarized in Table 5-3.
The digital output code is proportional to the input
voltage. The output data is in binary two’s complement
format. With this coding scheme the MSB can be
considered a sign indicator. When the MSB is a logic
‘0’, the input is positive. When the MSB is a logic ‘1’, the
input is negative. The following is an example of the
output code:
EQUATION 5-11: LSB SIZE (EXAMPLE)
2VREF
(a) for a negative full-scale input:
Analog Input: (VIN+) – (VIN-) = -VREF
Output Code: 1000...0000
(b) for a zero differential input:
Analog Input: (VIN+) – (VIN-) = 0V
Output Code: 0000...0000
(c) for a positive full-scale input:
Analog Input: (VIN+) – (VIN-) = +VREF
Output Code: 0111...1111
LSB = --------------
2N
Where N is the resolution of the ADC in bits.
TABLE 5-3:
LSB SIZE VS. REFERENCE
LSB Size
Reference
Voltage
MCP33151D-XX MCP33141D-XX
(VREF
)
(14-bit)
(12-bit)
1.8V
2V
219.7 µV
244 µV
879.8 µV
976.6 µV
The MSB (sign bit) is always transmitted first through
the SDO pin.
The code will be locked at 0111...11 for all voltages
greater than (VREF - 1 LSB) and 1000...00 for
voltages less than -VREF. Table 5-4 shows an example
of output codes of various input levels.
2.5V
3V
305.2 µV
366.2 µV
402.8 µV
427.3 µV
488.3 µV
549.3 µV
610.4 µV
622.6 µV
1.2207 mV
1.4648 mV
1.6113 mV
1.7090 mV
1.9531 mV
2.1973 mV
2.4414 mV
2.4902 mV
3.3V
3.5V
4V
4.5V
5V
5.1V
Figure 5-11 shows the ideal transfer function and
Table 5-4 shows the digital output codes for the
MCP33151D/41D-XX.
011 … 111
011 … 110
000 … 000
100 … 001
100 … 000
0V
-VREF + 1 LSB
+VREF - 2 LSB
-VREF + 0.5 LSB
+VREF - 1.5 LSB
-VREF
+VREF - 1 LSB
Differential Analog Input Voltage
FIGURE 5-11:
Ideal Transfer Function for
Fully-Differential Input Signal.
DS20006219A-page 38
2019 Microchip Technology Inc.
MCP33151D/41D-XX
TABLE 5-4:
DIGITAL OUTPUT CODE
Digital Output Codes
Input Voltage (V)
MCP33151D-XX
MCP33141D-XX
(12-bit)
(14-bit)
VREF
01-1111-1111-1111
01-1111-1111-1111
0111-1111-1111
0111-1111-1111
V
REF - 1 LSB
.
.
.
.
.
.
2 LSB
1 LSB
0V
00-0000-0000-0010
00-0000-0000-0001
00-0000-0000-0000
11-1111-1111-1111
11-1111-1111-1110
0000-0000-0010
0000-0000-0001
0000-0000-0000
1111-1111-1111
1111-1111-1110
-1 LSB
-2 LSB
.
.
.
.
.
.
-VREF
10-0000-0000-0000
10-0000-0000-0000
1000-0000-0000
1000-0000-0000
< -VREF
5.7
Data Accumulator
120
115
110
105
100
95
-75
The MCP33151D/41D-XX devices feature an internal
integrator capable of accumulating consecutive sample
data and transmitting the accumulated data directly
from the ADC, without requiring any special SPI
settings to operate. This enables the user to achieve a
higher ENOB through consecutive sample integration
utilizing the ADC hardware, without requiring any
external computational resources and reducing the
amount of data transmitted on the serial bus. See
Figure 5-12 for an example FFT performance plot after
1024 integrated samples while sampling a 75Hz input
signal with a 5V reference voltage. Refer to Figure 5-13
for an example of FFT performance across possible
integration lengths.
-80
-85
-90
-95
SNR (dB)
SINAD(dB)
SFDR(dBc)
THD (dB)
-100
-105
-110
-115
-120
90
85
80
75
1
4
16
64
256
1024
Integration Length
FIGURE 5-13:
FFT with 1024 integrated
samples: Input Freq = 75Hz.
0
f
= 1/1024 Msps
-20
-40
5.7.1
DATA ACCUMULATOR USAGE
s
V
= 5V
REF
SNR = 116.7 dBFS
SINAD = 111.5 dBFS
SFDR = 117.2 dBc
THD = -113.5 dBc
ENOB = 18-bit
Data accumulation is performed automatically within
the
device
between
each
sequential
-60
Conversion/Acquisition cycle (TCYC) whenever the
current conversion results are not read out, up to a total
of 1024 consecutive conversions for an ENOB increase
of up to 5 bits above typical. To begin data
accumulation, the user simply avoids transmitting any
SCLK pulses during each sequential conversion cycle.
-80
Resolution = 24-bit
-100
-120
-140
-160
Note:
If a sample has been converted but not
read out, the sample can be discarded by
providing at least 1 SCLK pulse before ini-
tiating the next conversion. Providing at
least 1 SCLK will reset the system for sin-
gle acquisition. Otherwise all consecutive
conversions without an SCLK pulse will
automatically be integrated with the previ-
ous conversion results.
0
0.1
0.2
0.3
0.4
0.5
Frequency (kHz)
FIGURE 5-12:
FFT with 1024 integrated
samples: Input Freq = 75Hz.
2019 Microchip Technology Inc.
DS20006219A-page 39
MCP33151D/41D-XX
After completing the desired number of conversions to
achieve the target ENOB, the user can begin
transferring the total accumulated data by transmitting
the necessary number of SCLK pulses to transfer all
stored bits. Refer to Table 5-5 for number of
conversions, bit size and ENOB relationship. See
Note:
The discrepancy between the output data
size and the actual ENOB is a result of
sample integration doubling both the signal
amplitude and the noise power for each
factor of two that the samples are inte-
grated. By integrating 2 samples, the signal
amplitude increases SNR by 6 dB, and the
noise power decreases SNR by 3 dB,
resulting in an overall SNR increase of 3 dB
(+0.5 ENOB).
Figure 6-5
and
Figure 6-8
for
example
Conversion/Acquisition control and SPI timing
operation.
Consecutive sample integration increases the bit size
of the output data, up to the maximum output size of the
ADC (24-bits / 18.5 ENOB at 1024 samples for a 14-bit
ADC).
TABLE 5-6:
INPUT SIGNAL ROLL-OFF
FREQUENCY VS
INTEGRATION LENGTH
Because the addition of two binary values can produce
a sum with an increased bit size, the ADC will need to
output data proportional to the amount of samples
being integrated. See Table 5-5 for an estimate of the
data size and ENOB capability depending on the
number of conversions the user chooses to integrate.
Roll-Off (Hz @ 1MSPS)
Integration
Length
0.1 dB
0.01 dB
0.001 dB
2
4
41781.9
20890.9
10445.5
5222.7
2611.4
1305.7
652.8
13226.3
6613.2
3306.6
1653.3
826.6
413.3
206.7
103.3
51.7
4183.0
2091.5
1045.7
522.9
261.4
130.7
65.4
When using the accumulator, it is important to consider
the frequency content of the input signal being
sampled. Because the accumulator is averaging all
consecutive conversions over the accumulated time
period, the input frequency must be low enough to
ensure that no signal information is being filtered out.
This means that there is a performance trade-off
between sample integration length (and resulting
ENOB improvement) and the maximum input
frequency that can be sampled. Refer to Table 5-6 to
understand the roll-off frequencies for various
integration lengths, and refer to Figure 5-14 for an
example of the dB attenuation across integration
lengths.
8
16
32
64
128
256
512
1024
326.4
32.7
163.2
16.3
81.6
25.8
8.2
0.02
0
TABLE 5-5:
ACCUMULATED DATA SIZE
AND ENOB FOR 14-BIT ADC
-0.02
-0.04
-0.06
ADC
transmission
size (bits)
Effective
Number of bits
(ENOB) (1)
Number of
Conversions
1
14
15
16
17
18
19
20
21
22
23
24
13.5
2
14
-0.08
1
3 - 4
14 - 14.5
14.5 - 15
15 - 15.5
15.5 - 16
16 - 16.5
16.5 - 17
17 - 17.5
17.5 - 18
18 - 18.5
4
16
64
256
1024
Integration Length
5 - 8
FIGURE 5-14:
Fundamental Frequency (dB) vs Integration
Length: Input Freq = 75 Hz.
Measured Attenuation of
9 - 16
17 - 32
33 - 64
65 - 128
129 - 256
257 - 512
513 - 1024
Note 1: ENOB values based on typical 14b device
characteristics under nominal conditions
and setting N to the maximum value in the
corresponding row.
DS20006219A-page 40
2019 Microchip Technology Inc.
MCP33151D/41D-XX
6.1
Serial Interface Options and Serial
Communications
6.0
DIGITAL SERIAL INTERFACE
The device has an SPI compatible serial digital
interface using four digital interface pins: CNV, SDI,
SDO and SCLK.
The device offers a CS mode with 3-wire interface,
and can operate either with or without a BUSY
indicator status output. This BUSY status output bit is
followed by the conversion output bits, and can be
used as an interrupt request (IRQ) input for the digital
host device.
The following sections describe the operation of the
MCP33151D/41D-XX using the digital serial interface.
Table 6-1 summarizes the descriptions of both digital
interface pins and interface options, respectively. The
communication is always started by the host device
(Master).
The 3-Wire CS mode (using CNV, SCLK, SDO)
interface is simple and useful when the host device
handles a single MCP33151D/41D-XX device.
Note:
This device supports a standard SPI
Mode 0,0 only.
The following sections detail the serial communication
of the 3-Wire CS modes with or without a BUSY output.
SPI MODE 0,0: In this mode, the SCLK
Idle state is “Low”. Data is clocked out on
the SDO pin on the falling edge of the
SCLK pin.
For the MCP33151D/41D-XX, this means
that there will be a rising edge before
there is a falling edge.
TABLE 6-1:
INTERFACE MODE SELECTION SUMMARY
SDI Pin
SCLK at
CNV
Rising
Edge
CNV Pin at tCNV
(recommended)
BUSY bit
at SDO
Interface Mode
At CNV
Rising Edge
After CNV
Rising Edge
3-Wire CS Mode without
BUSY output bit
“High”
“Low”
Transition from “High” to
“Low” after tCNV (Max)
—
No
3-Wire CS Mode with
BUSY output bit
Transition from “High” to
“Low” before tCNV (Max)
—
Yes
completes the conversion regardless of the state of the
CNV pin. This means the CNV pin can be used for
other SPI devices after the conversion is initiated.
6.1.1
CS MODES
Note:
The timing diagram examples in the
following subsections are shown for 14-bit
mode only. The examples are applicable
for 12-bit mode in the same way with
reduced bits.
When conversion is complete, the device enters the
acquisition phase (Power-Down state), and SDO
comes out of the high-Z state when CNV is lowered.
The device exits the acquisition phase when CNV goes
“High”. SDO returns to a high-Z state after the 14th
SCLK falling edge or when CNV goes high, whichever
occurs first.
6.1.1.1
3-Wire CS MODE WITHOUT BUSY
OUTPUT BIT
This interface option is most useful when a single
MCP33151D/41D-XX is connected to an
SPI-compatible digital host. Figure 6-1 shows the
connection diagram with the host device. In this mode,
CNV functions as both conversion control and chip
select (CS).
The device will output the MSB on the SDO pin
following the falling edge of CNV, or once the
Converting Phase (tCNV
)
completes, whichever
happens later. The remaining data bits are then
clocked out on the subsequent SCLK falling edges.
Data is valid on both edges of SCLK and can be
captured on either edge. However, a digital host
capturing data on the SCLK falling edge can achieve a
faster read out rate.
To enable this interface option, SDI can either be tied
to VIO, or otherwise permanently held in a Logic = 1
state. By doing so, the device will never output a BUSY
status bit.
It is recommended to use this mode only when the ADC
Converting Phase (tCNV) will complete before the fall-
ing edge of CNV.
As shown in Figure 6-2, at the rising edge of CNV, the
conversion is initiated. The SDO pin becomes high-Z
state (if no external pull-up is used). Once the
conversion is initiated, it continues and the ADC
Figure 6-2 and Figure 6-3 show the timing diagrams for
both early and late CNV lowering scenarios.
2019 Microchip Technology Inc.
DS20006219A-page 41
MCP33151D/41D-XX
VIO
CNVST
VIO
CNV
SDIꢀ SDO
SC>K
47 kΩ
SDI
(Data In)
SC>K
(a) MCP331xx
(b) Digital Host (Master)
FIGURE 6-1:
Connection Diagram for
3-Wire CS Mode without BUSY Status Indicator
Output Bit.
TCYC = 1/fs
SDI = 1
tCNVH
tSU_SDIH_CNV
CNV (CS
)
tSCLK
tEN
tQUIET
SC>K
1
tDO
2
3
4
5
12
13
14
tDIS
tSCLK_L
D11
tSCLK_H
“High” (with pull-up)ꢀ
SDO
D13
D12
D10
D9
D2
D1
D0
,ŝŐŚ-Z (with no pull-up)
ADC
State
Converting Phase
Input Acquisition
(tACQ
)
(tCNV
)
FIGURE 6-2:
Interface Timing Diagram for 3-Wire CS Mode without BUSY Status Indicator Output
Bit, Late CNV (Recommended).
DS20006219A-page 42
2019 Microchip Technology Inc.
MCP33151D/41D-XX
TCYC = 1/fs
SDI = 1
tCNVH
tSU_SDIH_CNV
CNV (CS)
SC>K
tSCLK
tQUIET
1
tDO
2
3
4
5
12
13
14
tDIS
tSCLK_L
tSCLK_H
“High” (with pull-up)ꢀ
SDO
D13
D12
D11
D10
D9
D2
D1
D0
HŝŐŚ-Z (with no pull-up)ꢀ
tEN
ADC
State
Converting Phase
Input Acquisition
(tACQ
)
(tCNV
)
FIGURE 6-3:
Interface Timing Diagram for 3-Wire CS Mode without BUSY Status Indicator Output
Bit, Early CNV.
TCYC(1)
= 1/fs
TCYC(2)
= 1/fs
TCYC(3) … TCYC(N-1)
TCYC(N) = 1/fs
SDI = 1
tCNVH
tCNVH
tCNVH
tSU_SDIH_CNV
CNV (CS)
tSCLK
tEN
tQUIET
2
3
4
M-2
M-1
D1
M
SCLK
SDO
1
tDO
tSCLK_L
DM-4
tSCLK_H
tDIS
D0
DM-2
DM-3
D2
D14
D15
DM-1
ADC
State
tCNV
tACQ
tCNV
tACQ
tACQ
tCNV
tACQ
Legend
No signal transitions during compressed time
Signal transitions during compressed time
FIGURE 6-4:
Interface Timing Diagram for Accumulator Operation in 3-Wire CS Mode without
BUSY Status Indicator Output Bit.
Note:
Refer to Section 5.7, Data Accumulator for more details about using the data accumulator feature.
2019 Microchip Technology Inc.
DS20006219A-page 43
MCP33151D/41D-XX
6.1.1.2
3-Wire CS Mode with BUSY Output
Bit
CNVST
This interface option is typically used when a single
MCP33151D/41D-XX is connected to an
SPI-compatible digital host that has an interrupt (IRQ)
input.
VIO
CNV
SDIꢀ SDO
SC>K
47 kΩ
SDI
(Data In)
IRQ
Figure 6-5 shows the connection diagram with the host
device. In this mode, CNV functions as both conversion
control and chip select (CS).
SC>K
To enable this interface option, SDI can either be tied
to GND, or otherwise permanently held in a Logic = 0
state. By doing so, the device will output a BUSY bit
before each conversion data sample.
(a) MCP331xx
FIGURE 6-5:
(b) Digital Host (Master)
Connection Diagram for
3-Wire CS Mode with BUSY Status Indicator
Output Bit. IRQ Pin in the Host Device Is Used
for Interrupt Event.
As shown in Figure 6-6, at the rising edge of CNV,
conversion is initiated. The SDO pin becomes high-Z
state (if no external pull-up is used). Once the
conversion is initiated, it continues and the ADC
completes the conversion regardless of the state of the
CNV pin. This means the CNV pin can be used for
other SPI devices after the conversion is initiated.
Note:
The pull-up resistor on the SDO pin is
required in this mode as it ensures that the
IRQ pin of the digital host is held high
when SDO goes to high-Z state.
When conversion is complete, the device enters an
acquisition phase and Power-Down state, SDO comes
out of the high-Z state, and outputs a BUSY status indi-
cator bit (“Low” level). The device exits the acquisition
phase when CNV once again returns to a “High” state.
SDO then returns to a high-Z state after the 15th SCLK
falling edge or when CNV goes high, whichever occurs
first.
Note:
It is recommended that CNV be driven low
before the minimum conversion time
(tCNV) expires, and remain “Low” until the
maximum possible conversion time
(tCONV) expires. A “Low” level on the CNV
input at the end of a conversion ensures
the device generates a BUSY status
indicator bit when the ADC has finished
converting.
This configuration provides a high-to-low transition on
the IRQ pin of the digital host caused by the BUSY bit.
The data bits are clocked out, MSB first, on the subse-
quent SCLK falling edges. Data are valid on both edges
of SCLK and can be captured on either edge. However,
a digital host capturing data on the SCLK falling edge
can achieve a faster reading rate.
Figure 6-6 and Figure 6-7 show the timing diagrams for
both early and late CNV lowering scenarios.
DS20006219A-page 44
2019 Microchip Technology Inc.
MCP33151D/41D-XX
TCYC = 1/fs
SDI = 0
tSU_SDIL_CNV
tCNVH
CNV (CS)
tSCLK
tQUIET
SC>K
1
tDO
2
3
4
5
13
14
15
tDIS
tSCLK_L
tSCLK_H
D10
“High” (with pull-up)ꢀ
SDO
BUSY
D13
D12
D11
D2
D1
D0
HiŐŚ-Z (with no pull-up)ꢀ
tEN
ADC
State
Converting Phase
Input Acquisition
(tACQ
)
(tCNV
)
FIGURE 6-6:
Timing Diagram for 3-Wire CS Mode with BUSY Status indicator Output Bit, Early
CNV (Recommended).
TCYC = 1/fs
SDI = 0
tSU_SDIL_CNV
tCNVH
CNV (CS
SC>K
)
tSCLK
tEN
tQUIET
1
tDO
2
3
4
5
13
14
15
tDIS
tSCLK_L
D12
tSCLK_H
“High” (with pull-up)ꢀ
SDO
BUSY
D2
D1
D0
D13
D11
D10
HiŐŚ-Z (with no pull-up)
ADC
State
Converting Phase
Input Acquisition
(tACQ
)
(tCNV
)
FIGURE 6-7:
Timing Diagram for 3-Wire CS Mode with BUSY Status Indicator Output Bit, Late
CNV.
2019 Microchip Technology Inc.
DS20006219A-page 45
MCP33151D/41D-XX
TCYC(1)
= 1/fs
TCYC(2)
= 1/fs
TCYC(3) … TCYC(N-1)
TCYC(N) = 1/fs
SDI = 1
tCNVH
tCNVH
tCNVH
tSU_SDIH_CNV
CNV (CS)
tSCLK
tQUI
2
3
4
M-2
M-1
D1
M
SCLK
SDO
1
tDO
tSCLK_L
DM-4
tSCLK_H
tDIS
D0
BUSY
BUSY
BUSY
DM-2
DM-3
D2
BUSY
tEN
ADC
State
tCNV
tACQ
tCNV
tACQ
tACQ
tCNV
tACQ
Legend
No signal transitions during compressed time
Signal transitions during compressed time
FIGURE 6-8:
Timing Diagram for Accumulator Operation in 3-Wire CS Mode with BUSY Status
Indicator Output Bit.
Note: Refer to Section 5.7, Data Accumulator for more details about using the data accumulator feature.
DS20006219A-page 46
2019 Microchip Technology Inc.
MCP33151D/41D-XX
A self-calibration is initiated by sending the recalibrate
command. The host device sends a recalibrate
command by transmitting 1024 SCLK pulses (including
the clocks for data bits) while the device is in the
acquisition phase (Standby).
6.2
Recalibrate Command
The recalibrate command may be used in the following
cases:
• When the reference voltage was not fully settled
during the initial power-on sequence.
The device drives SDO low during the recalibration
procedure, and returns to high-Z once completed. The
status of the recalibration procedure can be monitored
by placing a pull-up on SDO, so that SDO goes high
when the recalibration is complete.
• During operation, to ensure optimum performance
across varying environment conditions, such as
reference voltage and temperature.
Figure 6-9 shows the recalibrate command timing
diagram. The calibration takes approximately 500 ms
(tCAL).
(Note 1)
SDI = 1
Start recalibration
Finish recalibration
Device Recalibration
Complete data reading
CNV (CS)
1024 clocks
(SPITM Recalibrate command)
...
1
2
3
...
13
14
1023
1024
tCAL
SC>K
(Note 2)
“High” (with pull-up)
“Low”
SDO
ADC Output Data Stream
HiŐŚ-Z (with no pull-up)
(Note 3)
ADC
State
(Note 4)
tCNV
Note 1: SDI must remain “High” during the entire recalibration cycle.
2: The 1024 clocks include the clocks for data bits.
3: SDO outputs “Low” during calibration, and high-Z when exiting the calibration. This SDO activity is only present during manual reca-
libration and is not present during initial power-on auto-calibration. (See Section 4.3 “Power-Up Sequence and Auto-Calibration”
for more details)
4: After finishing the recalibration procedure, the device is ready for a new input sampling immediately.
FIGURE 6-9:
Note:
Recalibrate Command Timing Diagram.
When the device performs a calibration, it is important to note that the analog supply voltage (AVDD), the
reference voltage (VREF) and the digital I/O interface supply voltage (DVIO) must be stabilized for a correct
calibration. This is particularly relevant during the initial power-on sequence. Refer to Section 4.3
“Power-Up Sequence and Auto-Calibration” for more details.
2019 Microchip Technology Inc.
DS20006219A-page 47
MCP33151D/41D-XX
NOTES:
DS20006219A-page 48
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Figure 7-1 and Figure 7-2 show this evaluation tool.
This evaluation platform allows users to quickly
evaluate the ADC's performance for their specific
application requirements.
7.0
7.1
DEVELOPMENT SUPPORT
Device Evaluation Board
Microchip Technology Inc. offers a high speed/high
precision SAR ADC evaluation platform which can be
used to evaluate Microchip’s latest high speed/high
resolution SAR ADC products. The platform consists of
an MCP331x1D-XX evaluation board, a data capture
board (PIC32 MZ EF Curiosity Board), and a PC-based
Graphical User Interface (GUI) software.
Note:
Contact Microchip Technology Inc. for the
PIC32 MCU firmware and the
MCP331x1D-XX Evaluation Kit.
(a) MCP331x1D-XX Evaluation Board
(b) PIC32MZ EF Curiosity Board
FIGURE 7-1:
MCP331x1D-XX Evaluation Kit.
FIGURE 7-2:
PC-Based Graphical User Interface Software.
2019 Microchip Technology Inc.
DS20006219A-page 49
MCP33151D/41D-XX
The following four layers are recommended:
7.2
PCB Layout Guidelines
(a) Top Layer: Most of the noise-sensitive
analog components are populated on the top
layer. Use all unused surface area as ground
planes: analog ground plane in analog circuit
section and digital ground in digital circuit
section. These ground planes need to be tied to
the corresponding ground planes in the second
and bottom layers using multiple vias.
Microchip provides the schematics and PCB layout of
the MCP331x1D-XX Evaluation Board (P/N:
ADM00873). It is strongly recommended that the user
references the example circuits and PCB layouts.
A good schematic with low noise PCB layout is critical
for high performing ADC application system designs. A
few guidelines are listed below:
• Use low noise supplies (AVDD, DVIO, and VREF).
(b) 2nd Layer: Use this layer as the ground
plane: Analog ground plane under the analog
circuit section of the top layer and digital ground
plane under the digital circuit section on the top
layer. Each ground plane is tied to its
• All supply voltage pins, including reference
voltage, need decoupling capacitors. Decoupling
capacitor requirements for each supply pin are
shown in Figure 4-1.
corresponding ground plane of top and bottom
layers using multiple vias.
• Use NPO or COG type capacitor for the RC
anti-aliasing filters in the analog input network.
• Keep the analog circuit section (analog input
driver amplifiers, filters, voltage reference, ADC,
etc.) with an analog ground plane, and the digital
circuit section (MCU, digital I/O interface) with a
digital ground plane. Keep these sections as
much apart as possible. This will minimize any
digital switching noise coupling into the analog
section.
(c) 3rd Layer: This layer is used to distribute
various power supplies of the circuits. Use
separate trace paths for the power supplies of
analog and digital sections. Do not use the same
power supply source for both analog and digital
circuits.
(d) Bottom Layer: This layer is mostly used as
a solid ground plane: Analog ground plane
under the analog circuit section of the top layer
and digital ground plane under the digital circuit
section on the top layer. Each ground plane is
tied to its corresponding ground plane of all
layers using multiple vias.
• Connect the analog and digital ground planes at a
single point (away from the sensitive analog
sections) with a 0resistor or with a ferrite bead.
See Figure 7-3 as an example of separated
ground planes.
• Keep the clock and digital output data lines short
and away from the sensitive analog sections as
much as possible.
Figure 7-3 and Figure 7-4 show brief examples of the
PCB layout. See more details of the schematics and
PCB layout in the MCP331x1D-XX Evaluation Board
User’s Guide.
• PCB Material and Layers: Low-loss FR-4
material is most commonly used.
Analog Ground Plane
(GND)
MCP331x1D-XX
Analog Ground Plane
Note: Analog and digital
(GND)
ground planes are
connected via R56.
SCLK
SDO
R56
Digital Interface
Connectors for MCU
Digital Ground Plane
(DGND)
(DGND)
Digital Ground Plane
FIGURE 7-3:
PCB Layout Example: Analog and Digital Ground Planes.
DS20006219A-page 50
2019 Microchip Technology Inc.
MCP33151D/41D-XX
SDI
V
V
SCLK
SDO
REF
AV
IO
DD
A
A
+
-
IN
IN
GND
MCP331x1D-XX
CNVST
(a) PCB layout example
(b) Schematic example from the MCP331x1D-XX Evaluation Board
FIGURE 7-4:
PCB Layout Example: See More Details in the MCP331x1D-XX EV Kit User’s Guide.
2019 Microchip Technology Inc.
DS20006219A-page 51
MCP33151D/41D-XX
NOTES:
DS20006219A-page 52
2019 Microchip Technology Inc.
MCP33151D/41D-XX
EQUATION 8-2:
8.0
TERMINOLOGY
P
S
SINAD = 10log ---------------------
Analog Input Bandwidth (Full-Power
Bandwidth)
P
+ P
D
N
SNR
–-----------
10
THD
–------------
10
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
= –10log 10
– 10
SINAD is either given in units of dBc (dB to carrier),
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale), when the
power of the fundamental is extrapolated to the
converter full-scale range.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
CNVST input and when the input signal is held for a
conversion.
Effective Number of Bits (ENOB)
Differential Nonlinearity
(DNL, No Missing Codes)
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
An ideal ADC exhibits code transitions that are exactly
1 LSB apart. DNL is the deviation from this ideal value.
No missing codes indicates that all 16384 codes for
14-bit (4096 codes for 12-bit) must be present over all
the operating conditions.
EQUATION 8-3:
SINAD – 1.76
ENOB = ----------------------------------
6.02
Integral Nonlinearity (INL)
Gain Error
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range. Gain error is usually expressed in LSB or as a
percentage of full-scale range (%FSR).
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS)
to the noise floor power (PN), below the Nyquist
frequency and excluding the power at DC and the first
nine harmonics.
Offset Error
The major carry transition should occur for an analog
value of ½ LSB below AIN+ = AIN−. Offset error is
defined as the deviation of the actual transition from
that point.
EQUATION 8-1:
P
S
SNR = 10log -------
P
N
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value at across the TMIN to TMAX range.
The value is normalized by the reference voltage and
expressed in µV/oC or ppm/oC.
SNR is either given in units of dBc (dB to carrier), when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale), when the power
of the fundamental is extrapolated to the converter
full-scale range.
Maximum Conversion Rate
Signal-to-Noise and Distortion (SINAD)
The maximum clock rate at which parametric testing is
performed.
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
2019 Microchip Technology Inc.
DS20006219A-page 53
MCP33151D/41D-XX
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
EQUATION 8-4:
P
S
THD = 10log -------
P
D
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 8-5:
2
2
2
3
2
4
2
n
V + V + V + + V
THD = –20log-----------------------------------------------------------------
2
V
1
Where:
V1 = RMS amplitude of the
fundamental frequency
V1 through Vn = Amplitudes of the second
through nth harmonics
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The common-mode signal can be
an AC or DC signal or a combination of the two. CMRR
is measured using the ratio of the differential signal
gain to the common-mode signal gain and expressed in
dB with Equation 8-6:
EQUATION 8-6:
A
DIFF
CMRR = 20log ------------------
A
CM
Where:
ADIFF = Output Code/Differential Voltage
ADIFF = Output Code/Common-Mode Voltage
DS20006219A-page 54
2019 Microchip Technology Inc.
MCP33151D/41D-XX
9.0
9.1
PACKAGING INFORMATION
Package Marking Information
10-Lead MSOP (3 × 3 mm)
Example
Part Number
Code
MCP33151D-10-E/MS
MCP33151D-05-E/MS
MCP33141D-10-E/MS
MCP33141D-05-E/MS
51D-10
51D-10
922256
51D-05
41D-10
41D-05
Note:
Applies to 10-Lead MSOP.
10-Lead TDFN (3 × 3 × 0.8 mm)
Example
Part Number
Code
MCP33151D-10-E/MN
MCP33151D-05-E/MN
MCP33141D-10-E/MN
MCP33141D-05-E/MN
51D1
51D0
41D1
41D0
XXXX
YYWW
NNN
PIN 1
51D1
1922
256
NNN
Note:
Applies to 10-Lead TDFN.
PIN 1
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
e
3
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20006219A-page 55
MCP33151D/41D-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 H
D
D
2
A
N
E
2
E1
2
E1
E
0.20 H
0.25 C
1
2
e
B
8X b
0.13
C A B
TOP VIEW
H
C
A2
A
SEATING
PLANE
8X
0.10 C
A1
SEE DETAIL A
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-021D Sheet 1 of 2
DS20006219A-page 56
2019 Microchip Technology Inc.
MCP33151D/41D-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
4X Ĭ1
c
C
SEATING
PLANE
Ĭ
L
(L1)
4X Ĭ1
DETAIL A
Units
MILLIMETERS
Dimension Limits
MIN
NOM
MAX
Number of Pins
Pitch
N
e
10
0.50 BSC
Overall Height
Molded Package Thickness
Standoff
Overall Width
Molded Package Width
Overall Length
Foot Length
A
-
-
1.10
0.95
0.15
A2
A1
E
E1
D
0.75
0.00
0.85
-
4.90 BSC
3.00 BSC
3.00 BSC
0.60
L
0.40
0.80
Footprint
L1
0.95 REF
Mold Draft Angle
Foot Angle
Lead Thickness
Lead Width
0°
5°
0.08
0.15
-
-
-
-
8°
15°
0.23
0.33
Ĭ
Ĭ1
c
b
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-021D Sheet 2 of 2
2019 Microchip Technology Inc.
DS20006219A-page 57
MCP33151D/41D-XX
10-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
Z
C
G1
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
MILLIMETERS
Dimension Limits
MIN
NOM
0.50 BSC
4.40
MAX
Contact Pitch
E
C
Contact Pad Spacing
Overall Width
Contact Pad Width (X10)
Contact Pad Length (X10)
Distance Between Pads (X5)
Distance Between Pads (X8)
Z
X1
Y1
G1
G
5.80
0.30
1.40
3.00
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2021B
DS20006219A-page 58
2019 Microchip Technology Inc.
MCP33151D/41D-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006219A-page 59
MCP33151D/41D-XX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006219A-page 60
2019 Microchip Technology Inc.
MCP33151D/41D-XX
APPENDIX A: REVISION HISTORY
Revision A (June 2019)
• Initial release of this document
2019 Microchip Technology Inc.
DS20006219A-page 59
MCP33151D/41D-XX
NOTES:
2019 Microchip Technology Inc.
DS20006219A-page 60
MCP33151D/41D-XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
(1)
X
/XX
XX
[X]
PART NO.
X
a) MCP33151D-10-E/MS:
14-bit, 1 Msps,
10-LD MSOP package
Temperature Package
Range
Device Input Type Sample Rate Tape and Reel
Option
b) MCP33151D-10T-E/MS: 14-bit, 1 Msps,
Tape and Reel,
10-LD MSOP package
Device:
MCP33151D-10 = 1 Msps, 14-Bit Differential Input SAR ADC
MCP33141D-10 = 1 Msps, 12-Bit Differential Input SAR ADC
c) MCP33151D-10-E/MN:
14-bit, 1 Msps,
MCP33151D-05 = 500 kSPS, 14-Bit Differential Input SAR ADC
MCP33141D-05 = 500 kSPS, 12-Bit Differential Input SAR ADC
10-LD TDFN package
d) MCP33151D-10T-E/MN: 14-bit, 1 Msps,
Tape and Reel,
Input Type:
D
= Differential Input
10-LD TDFN package
e) MCP33141D-10-E/MS:
f) MCP33141D-10T-E/MS:
12-bit, 1 Msps,
10-LD MSOP package
Sample Rate:
10
05
= 1 Msps
= 500 kSPS
12-bit, 1 Msps,
Tape and Reel,
10-LD MSOP package
Tape and Reel
Option:
Blank
T
=
=
Standard packaging (tube or tray)
Tape and Reel (Note 1)
g) MCP33141D-10-E/MN:
12-bit, 1 Msps,
10-LD TDFN package
Temperature
Range:
E
=
-40C to +125C (Extended)
h) MCP33141D-10T-E/MN: 12-bit, 1 Msps,
Tape and Reel,
10-LD TDFN package
Package:
MS
MN
=
=
Plastic Micro Small Outline Package (MSOP),
10-Lead
i) MCP33151D-05-E/MS:
j) MCP33151D-05T-E/MS:
14-bit, 500 kSPS,
10-LD MSOP package
Thin Plastic Dual Flat No Lead Package (TDFN),
10-Lead (Note 2)
14-bit, 500 kSPS,
Tape and Reel,
10-LD MSOP package
k) MCP33151D-05T-E/MN: 14-bit, 500 kSPS,
Tape and Reel,
10-LD TDFN package
l) MCP33141D-05-E/MS:
12-bit, 500 kSPS,
10-LD MSOP package
m) MCP33141D-05T-E/MN: 12-bit, 500 kSPS,
Tape and Reel,
10-LD TDFN package
Note 1:
Tape and Reel identifier only appears in
the catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package.
Check with your Microchip Sales Office for
package availability with the Tape and Reel
option.
2:
Contact Microchip Technology Inc. for
availability.
2019 Microchip Technology Inc.
DS20006219A-page 61
MCP33151D/41D-XX
NOTES:
DS20006219A-page 62
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-522-4701-6
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2019 Microchip Technology Inc.
DS20006219A-page 63
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Australia - Sydney
Tel: 61-2-9868-6733
India - Bangalore
Tel: 91-80-3090-4444
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
China - Beijing
Tel: 86-10-8569-7000
India - New Delhi
Tel: 91-11-4160-8631
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
China - Chengdu
Tel: 86-28-8665-5511
India - Pune
Tel: 91-20-4121-0141
Finland - Espoo
Tel: 358-9-4520-820
China - Chongqing
Tel: 86-23-8980-9588
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Web Address:
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Fax: 31-416-690340
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Fax: 317-773-5453
Tel: 317-536-2380
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Tel: 86-756-3210040
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Tel: 631-435-6000
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Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006219A-page 64
2019 Microchip Technology Inc.
05/14/19
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