MCP37D21-80 [MICROCHIP]
80 Msps, 16/14-Bit High-Pr ecision Pipelined ADC;
| 型号： | MCP37D21-80 |
| 厂家： | 
MICROCHIP |
| 描述： | 80 Msps, 16/14-Bit High-Pr ecision Pipelined ADC |
| 文件： | 总141页 (文件大小：3534K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP37D31-80 AND MCP37D21-80
80 Msps, 16/14-Bit High-Precision Pipelined ADC
• Digital Signal Post-Processing (DSPP) Options:
- Decimation filters for improved SNR
- Fractional Delay Recovery (FDR) for time-
delay corrections in multi-channel operations
- Phase, Offset and Gain adjust of individual
channels
- Digital Down-Conversion (DDC)
- Continuous wave beamforming for octal-
channel mode
Features
• Sample Rates:
- 80 Msps for single-channel operation
- 80 Msps/number of channels used
• SNR with fIN = 15 MHz and -1 dBFS:
- 73.9 dBFS (typical) at 80 Msps
• SFDR with fIN = 15 MHz and -1 dBFS:
- 93 dBc (typical) at 80 Msps
• Power Dissipation Excluding Digital I/O (80 Msps):
•
Serial Peripheral Interface (SPI)
- 229 mW
• Auto Sync Mode to synchronize multiple devices
to the same clock
• Power Dissipation with CMOS Digital I/O (80 Msps):
- MCP37D31-80: 257 mW
• TFBGA-121 Package
- MCP37D21-80: 253 mW
- Dimension: 8 mm x 8 mm x 1.08 mm
• Power Dissipation with LVDS Digital I/O (80 Msps):
- MCP37D31-80: 329 mW
- MCP37D21-80: 320 mW
• Power-Saving Modes:
- 79 mW during Standby
- Includes embedded decoupling capacitors for
reference pins and bandgap output pin
•
AEC-Q100 Qualified (Automotive Applications)
- Temperature Grade 1: -40°C to +125°C
- 22 mW during Shutdown
Typical Applications
• Supply Voltage:
- Digital Section: 1.2V, 1.8V
- Analog Section: 1.2V, 1.8V
• Selectable Full-Scale Input Range: up to 2.975 VP-P
• Communication Instruments
• Microwave Digital Radio
• Lidar and Radar
• Configurable 8-Channel Input MUX:
• High-Speed Test Equipment
- Single-Channel or Sequential Multi-Channel
Sampling
• Ultrasound and Sonar Imaging
• Scanners and Low-Power Portable Instruments
• Industrial and Consumer DataAcquisition Systems
• Input Channel Bandwidth: 500 MHz
• Output Data Format:
- Parallel CMOS, DDR LVDS
- Serialized DDR LVDS (16-bit, octal-channel mode)
• Optional Output Data Randomizer
•
Built-In ADC Linearity Calibration Algorithms:
- Harmonic Distortion Correction (HDC)
- DAC Noise Cancellation (DNC)
- Dynamic Element Matching (DEM)
- Flash Error Calibration
MCP37Dx1-80 Family Comparison(1):
Digital
Decimation
Digital
Down-Conversion
CW
Beamforming
Noise-Shaping
Requantizer
Part Number Sample Rate Resolution
(3)
(3)
(4)
(2)
(5)
MCP37D31-80
MCP37D21-80
MCP37D11-80
80 Msps
80 Msps
80 Msps
16
14
12
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
Yes
Note 1: All devices are pin-to-pin compatible.
2: Available in single and dual-channel modes.
3: Available in single and dual-channel modes, and octal-channel mode when CW beamforming is enabled.
4: Available in octal-channel mode.
5: 18-bit output is available in MCP37D31-80 with high-order decimation filter setting.
2020 Microchip Technology Inc.
DS20006382A-page 1
MCP37D31-80 AND MCP37D21-80
Functional Block Diagram
AVDD12
AVDD18
GND
DVDD12
DVDD18
Duty Cycle
Correction
DLL
PLL
CLK+
CLK-
Clock
Selection
DCLK+
DCLK-
Output Clock Control
Digital Signal Post-Processing:
(Selectable using Configuration Register Bits)
AIN0
+
- Digital Down-Converter (DDC)
- Decimation Filter
AIN0
-
Pipelined
ADC
- Fractional Delay Recovery (FDR)
- Continuous Wave (CW) Beamforming
- Phase/Offset/Gain Adjustment
AIN7
+
AIN7
-
VREF+
VREF-
WCK
OVR
Output Control:
(0.9V)
VCM
Output
- CMOS, DDR LVDS
Data
- Serialized LVDS
[15:0]
Q
Reference Generator
SENSE
Configuration Registers
DM1
DM2
Note 2
VBG
SYNC
SLAVE
REF1+ REF1-
REF0- SDIO SCLK CS
REF0+
Note 1
Note 1: All external circuit components for REF0/1 and V pins are already embedded in the TFBGA-121 package.
BG
Note 2: DM1 and DM2 are extra output data pins for the 18-bit output mode, which is only available with the MCP37D31-80.
DS20006382A-page 2
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Description
The MCP37D31-80 and MCP37D21-80 are 80 Msps,
16-bit and 14-bit high-precision analog-to-digital
converter, respectively, with configurable input MUX.
The ADC output data can be coded in two's
complement or offset binary representation, with or
without the data randomizer option. The output data is
available as full-rate CMOS or Double-Data-Rate
(DDR) LVDS. Additionally, a serialized LVDS option is
also available for the 16-bit octal-channel mode.
Abuilt-in 8-input multiplexer (MUX) is used to select the
active analog input(s) depending on the user
configuration. In single-channel operation, the MUX
can be configured to select one of the 8-inputs. In multi-
channel operation, the selected inputs are sequentially
sampled. The input channel selection and the channel
order are configured using the user-programmable
configuration register bits.
The device also includes various features designed to
maximize flexibility in the user’s applications and
minimize system cost, such as a programmable PLL
clock, output data rate control and phase alignment,
and programmable digital pattern generation. The
device’s operational modes and feature sets are
configured using the user-programmable registers.
The ADC core operates at up to an 80 Msps rate. In
single-channel operation, the analog input is sampled
at full speed. In multi-channel operation, the effective
sample rate per channel is the full speed divided by the
number of selected channels. For example, if all 8-input
channels are used, each input channel is sampled at
10 Msps when the ADC core is running at 80 Msps.
Similarly, if only 4-input channels are selected, each
input channel is sampled at 20 Msps when the ADC
core is running at 80 Msps.
AutoSync mode offers a great design flexibility when
multiple devices are used in applications. It allows
multiple devices to sample input synchronously at the
same clock source.
The high dynamic performance with built-in digital
signal post-processing (DSPP) features makes the
device ideal for various high-performance data
acquisition systems, including communication and test
equipment, ultrasound imaging equipment, Lidar,
Radar and portable instrumentation.
The device features harmonic distortion correction,
DAC noise cancellation, power-up calibration, and
always-on background calibration which enable high
performance to be maintained consistently across the
extended temperature range.
The device is available in a lead-free TFBGA-121
package. The device is AEC-Q100 qualified for
automotive applications and operates over the
extended temperature range of -40°C to +125°C.
In addition to the data conversion, the device offers
exceptional user-selectable built-in digital signal post-
processing (DSPP) features that include high-order
digital decimation filters, digital down-conversion
(DDC), fractional delay recovery (FDR), gain and offset
adjustment per channel, and continuous wave (CW)
beamforming capability.
Package Type
Bottom View
The output decimation filter option improves SNR
performance significantly up to 90’s dBFS with the
512x decimation setting. The built-in digital down-
conversion (DDC) option can offer great flexibility in
advanced RF and digital communication system
designs.
Gain, phase and DC offset can be adjusted
independently for each input channel, allowing for
simplified implementation of continuous wave (CW)
beamforming and ultrasound Doppler imaging
applications.
Dimension: 8 mm x 8 mm x 1.08 mm
Ball Pitch: 0.65 mm
Ball Diameter: 0.4 mm
In dual or octal-channel mode, the Fractional Delay
Recovery (FDR) feature digitally corrects the difference
in sampling instance between different channels, so
that all inputs appear to have been sampled at the
same time.
TFBGA-121 Package
The differential full-scale analog input range is
programmable up to 2.975 VP-P
.
The input is sampled on the rising edge of the clock.
The digital output code is available after 28 clock cycles
of data latency. Latency will increase if any of the digital
signal post-processing (DSPP) options are enabled.
2020 Microchip Technology Inc.
DS20006382A-page 3
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 4
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
1.0
PACKAGE PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Top View
(Not to Scale)
1
2
3
4
5
6
7
8
9
10
11
A
B
SDIO VCM
REF1+ REF1- VBG REF0+ REF0- GND
GND
AIN4-
AIN2+
SCLK
WCK/
CS
GND GND SENSE AVDD12 AVDD12 AVDD18 AVDD18 AIN4+
AIN2-
AIN0+
AIN0-
WCK/
OVR- OVR+
(WCK) (OVR)
GND GND AVDD12 AVDD12 AVDD12 GND
GND
AIN6-
C
D
E
F
Q14/Q7- Q15/Q7
+
GND GND AVDD12 AVDD12 AVDD12 GND
GND GND AVDD12 AVDD12 AVDD12 GND
GND
GND
AIN6+
Q12/Q6- Q13/Q6
+
AIN5+ AIN1+
Q10/Q5- Q11/Q5+ DVDD18 DVDD18 AVDD12 AVDD12 AVDD12 GND
GND
AIN5-
AIN1-
G
H
J
Q8/Q4- Q9/Q4+DVDD18 DVDD18 GND GND AVDD12 AVDD12 GND
AIN7-
AIN3+
AIN7+
AIN3-
Q6/Q3- Q7/Q3+ DVDD12 DVDD12 GND GND
Q4/Q2- Q5/Q2+ DVDD12 DVDD12 GND GND
GND
GND
GND
GND
GND
GND VCMIN
+
VCMIN
-
K
L
Q2/Q1- Q3/Q1+ DM1/DM+ DCLK- CAL
GND SLAVE ADR0 ADR1 GND
GND
Q0/Q0- Q1/Q0+ DM2/DM- DCLK+ RESET SYNC GND
CLK+
CLK-
GND AVDD18
Analog
Digital
All others: Supply Voltage
Notes:
• Die dimension: 8 mm x 8 mm x 1.08 mm.
• Ball dimension: (a) Ball Pitch = 0.65 mm, (b) Ball Diameter = 0.4 mm.
• Flip-chip solder ball composition: Sn with Ag 1.8%.
• Solder sphere composition: SAC-405 (Sn/Au 4%/Cu 0.5%).
FIGURE 1-1:
TFBGA-121 Package. See Table 1-1 for the pin descriptions and Table 1-2 for active
and inactive ADC output pins for various ADC resolution modes.
2020 Microchip Technology Inc.
DS20006382A-page 5
MCP37D31-80 AND MCP37D21-80
TABLE 1-1:
Ball No.
A1
PIN FUNCTION TABLE
Name
I/O Type
Description
SDIO
Digital Input/ SPI data input/output
Output
A2
VCM
Analog
Output
Common-mode output voltage (900 mV) for analog input signal
Connect a decoupling capacitor (0.1 µF)(1)
A3
A4
A5
REF1+
REF1-
VBG
Differential reference voltage 1 (+/-). Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
Internal bandgap output voltage
A decoupling capacitor (2.2 μF) is embedded in the TFBGA package. Leave
this pin floating.
A6
A7
A8
A9
REF0+
REF0-
GND
Differential reference 0 (+/-) voltage. Decoupling capacitors are embedded in
the TFBGA package. Leave these pins floating.
Supply
Common ground for analog and digital sections
Analog Input Channel 4 differential analog input (-)
A10
AIN4-
A11
B1
AIN2+
Channel 2 differential analog input (+)
Digital Input SPI serial clock input
SCLK
B2
B3
B4
B5
CS
SPI Chip Select input
GND
Supply
Common ground for analog and digital sections
SENSE
AVDD12
Analog
Input
Analog input range selection. See Table 4-2 for SENSE voltage settings.
Supply voltage input (1.2V) for analog section
B6
B7
B8
B9
Supply
AVDD18
Supply voltage input (1.8V) for analog section
Channel 4 differential analog input (+)
Channel 2 differential analog input (-)
B10
B11
AIN4+
AIN2-
Analog Input
C1
WCK/OVR-
(WCK)
Digital
Output
WCK: Word clock sync digital output
OVR: Input overrange indication digital output(2)
C2
WCK/OVR+
(OVR)
C3
C4
C5
C6
C7
C8
C9
GND
Supply
Common ground for analog and digital sections
Supply voltage input (1.2V) for analog section
AVDD12
GND
AIN6-
Common ground pin for analog and digital sections
Channel 6 differential analog input (-)
Channel 0 differential analog input (+)
Digital data output(3)
C10
Analog Input
C11
D1
AIN0+
Q14/Q7-
Digital
Output
CMOS = Q14
DDR LVDS = Q7- (Even bit first), Q15- (MSb byte first)
Serialized LVDS = Q- for the first selected channel (n = 1)
D2
Q15/Q7+
Digital data output(3)
CMOS = Q15
DDR LVDS = Q7+ (Even bit first), Q15+ (MSb byte first)
Serialized LVDS = Q+ for the first selected channel (n = 1)
DS20006382A-page 6
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 1-1:
Ball No.
PIN FUNCTION TABLE
Name
I/O Type
Description
D3
D4
D5
D6
D7
D8
D9
GND
Supply
Common ground for analog and digital sections
AVDD12
Supply
Supply voltage input (1.2V) for analog section
Common ground for analog and digital sections
GND
Channel 6 differential analog input (+)
Channel 0 differential analog input (-)
Digital data output(3)
D10
D11
E1
AIN6+
AIN0-
Analog Input
Q12/Q6-
Digital
Output
CMOS = Q12
DDR LVDS = Q6- (Even bit first), Q14- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 2
E2
Q13/Q6+
Digital data output(3)
CMOS = Q13
DDR LVDS = Q6+ (Even bit first), Q14+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 2
E3
E4
E5
E6
E7
E8
E9
GND
Supply
Common ground for analog and digital sections
AVDD12
Supply voltage input (1.2V) for analog section
GND
Common ground for analog and digital sections
Channel 5 differential analog input (+)
Channel 1 differential analog input (+)
Digital data output(3)
E10
E11
F1
AIN5+
AIN1+
Analog Input
Q10/Q5-
Digital
Output
CMOS = Q10
DDR LVDS = Q5- (Even bit first), Q13- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 3
F2
Q11/Q5+
Digital data output(3)
CMOS = Q11
DDR LVDS = Q5+ (Even bit first), Q13+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 3
F3
F4
F5
F6
F7
F8
F9
DVDD18
AVDD12
Supply
Supply voltage input (1.8V) for digital section.
All digital input pins are driven by the same DVDD18 potential.
Supply voltage input (1.2V) for analog section
GND
Common ground for analog and digital sections
Channel 5 differential analog input (-)
Channel 1 differential analog input (-)
F10
F11
AIN5-
AIN1-
Analog Input
2020 Microchip Technology Inc.
DS20006382A-page 7
MCP37D31-80 AND MCP37D21-80
TABLE 1-1:
Ball No.
G1
PIN FUNCTION TABLE
Name
I/O Type
Description
Q8/Q4-
Digital
Output
Digital data output(3)
CMOS = Q8
DDR LVDS = Q4- (Even bit first), Q12- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 4
G2
Q9/Q4+
Digital data output(3)
CMOS = Q9
DDR LVDS = Q4+ (Even bit first), Q12+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 4
G3
G4
G5
G6
DVDD18
GND
Supply
Supply voltage input (1.8V) for digital section
All digital input pins are driven by the same DVDD18 potential
Common ground for analog and digital sections
Supply voltage input (1.2V) for analog section
G7
G8
G9
AVDD12
Supply
GND
AIN7-
Common ground for analog and digital sections
Channel 7 differential analog input (-)
G10
G11
H1
Analog Input
AIN3+
Channel 3 differential analog input (+)
Digital data output(3)
CMOS = Q6
Q6/Q3-
Digital
Output
DDR LVDS = Q3- (Even bit first), Q11- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 5
H2
Q7/Q3+
Digital data output(3)
CMOS = Q7
DDR LVDS = Q3+ (Even bit first), Q11+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 5
H3
H4
H5
H6
H7
H8
H9
DVDD12
GND
Supply
Supply voltage input (1.2V) for digital section
Common ground for analog and digital sections
Channel 7 differential analog input (+)
Channel 3 differential analog input (-)
Digital data output(3)
H10
H11
J1
AIN7+
AIN3-
Analog Input
Q4/Q2-
Digital
Output
CMOS = Q4
DDR LVDS = Q2- (Even bit first), Q10- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 6
J2
Q5/Q2+
Digital data output(3)
CMOS = Q5
DDR LVDS = Q2+ (Even bit first), Q10+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 6
J3
J4
J5
J6
J7
J8
J9
DVDD12
GND
Supply
DC supply voltage input pin for digital section (1.2V)
Common ground for analog and digital sections
DS20006382A-page 8
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 1-1:
Ball No.
PIN FUNCTION TABLE
Name I/O Type
Description
VCMIN+
VCMIN-
Q2/Q1-
Analog Input Common-mode voltage input for auto-calibration(4)
These two pins should be tied together and connected to VCM voltage.
J10
J11
K1
Digital
Output
Digital data output(3)
CMOS = Q2
DDR LVDS = Q1- (Even bit first), Q9- (MSb byte first)
Serialized LVDS = Q- for channel order (n) = 7
K2
Q3/Q1+
Digital data output(3)
CMOS = Q3
DDR LVDS = Q1+ (Even bit first), Q9+ (MSb byte first)
Serialized LVDS = Q+ for channel order (n) = 7
K3
K4
K5
DM1/DM+
DCLK-
CAL
18-bit mode: Digital data output. DM1 and DM2 are the last two LSb bits(5)
Other modes: Not used
LVDS: Differential digital clock output (-)
CMOS: Not used (leave floating)
Calibration status flag digital output(6)
High: Calibration is complete
Digital
Output
Low: Calibration is not complete
K6
K7
GND
Supply
Common ground pin for analog and digital sections
)
Slave or Master selection pin in AutoSync (10 . If not used, tie to GND.
SLAVE
Digital Input
K8
K9
ADR0
ADR1
GND
SPI address selection pin (A0 bit). Tie to GND or DVDD18(7)
SPI address selection pin (A1 bit). Tie to GND or DVDD18(7)
Common ground for analog and digital sections
K10
K11
L1
Supply
Q0/Q0-
Digital
Output
Digital data output(3)
CMOS = Q0
DDR LVDS = Q0- (Even bit first), Q8- (MSb byte first)
Serialized LVDS = Q- for the last selected channel (n=8)
L2
Q1/Q0+
Digital data output(8)
CMOS = Q1
DDR LVDS = Q0+ (Even bit first), Q8+ (MSb byte first)
Serialized LVDS = Q+ for the last selected channel (n=8)
18-bit mode: Digital data output. DM1 and DM2 are the last two LSb bits(5
)
L3
L4
DM2/DM-
DCLK+
Other modes: Not used
LVDS: Differential digital clock output (+)
CMOS: Digital clock output(8)
L5
L6
RESET
SYNC
Digital Input Reset control input:
High: Normal operating mode
Low: Reset mode(9)
Digital Input/ Digital synchronization pin for AutoSync(10
)
Output
If not used, leave it floating.
L7
L8
L9
GND
CLK+
CLK-
GND
Supply
Common ground for analog and digital sections
Analog Input Differential clock input (+)
Differential clock input (-)
Supply
Common ground for analog and digital sections
L10
L11
AVDD18
Analog Input Supply voltage input (1.8V) for analog section
2020 Microchip Technology Inc.
DS20006382A-page 9
MCP37D31-80 AND MCP37D21-80
Notes:
1. When the VCM output is used for the Common-mode voltage of analog inputs (i.e. by connecting to the center-tap of
a balun), the VCM pin should be decoupled with a 0.1 µF capacitor, and should be directly tied to the VCMIN+ and VCMIN
-
pins.
2. CMOS output mode: WCK/OVR- is WCK and WCK/OVR+ is OVR.
DDR LVDS output mode: The rising edge of DCLK+ is WCK and the falling edge is OVR.
OVR: OVR will be held “High” when analog input overrange is detected. Digital signal post-processing will cause
OVR to assert early relative to the output data. See Figure 2-2 for LVDS timing of these bits.
WCK: WCK is normally “Low”. WCK is “High” while data from the first channel is sent out. In single-channel
mode, WCK stays “High” except when in I/Q output mode. In serialized LVDS (octal) output mode, the WCK out-
put is asserted “High” on the MSb bit. See Section 4.12.5 “Word Clock (WCK)” for further WCK description.
3. DDR LVDS: Two data bits are multiplexed onto each differential output pair. The output pins shown here are for
the “Even bit first”, which is the default setting of OUTPUT_MODE<1:0> in Address 0x62 (Register 5-20). The
even data bits (Q0, Q2, Q4, Q6, Q8, Q10, Q12, Q14) appear when DCLK+ is “High”. The odd data bits (Q1, Q3,
Q5, Q7, Q9, Q11, Q13, Q15) appear when DCLK+ is “Low”. See Addresses 0x65 (Register 5-23) and 0x68
(Register 5-26) for output polarity control. See Figures 2-2 to 2-6 for LVDS output timing diagrams.
4.
VCMIN is used for Auto-Calibration only. VCMIN+ and VCMIN- should be tied together always. There should be no
voltage difference between the two pins. Typically both VCMIN+ and VCMIN- are tied to the VCM output pin
together, but they can be tied to another Common-mode voltage if external VCM is used. This pin has High Z input
in Shutdown, Standby and Reset modes.
5. Available for the MCP37D31-80 device only.
Leave these pins floating (No Connect) if not used.
18-bit mode: DM1/DM+ and DM2/DM- are the last LSb bits. DM2/DM- is the LSb. In LVDS output, DM1/DM+ and
DM2/DM- are the LSb pair. DM1/DM+ appears at the falling edge and DM2/DM- is at the rising edge of the DCLK+.
Other than 18-bit mode: DM1/DM+ and DM2/DM- are High Z in LVDS mode.
6. CAL pin stays “Low” at power-up until the first power-up calibration is completed. When the first calibration has
completed, this pin has “High” output. It stays “High” until the internal calibration is restarted by hardware or a
soft reset command. In Reset mode, this pin is “Low”. In Standby and Shutdown modes, this pin will maintain the
prior condition.
7. If the SPI address is dynamically controlled, the Address pin must be held constant while CS is “Low”.
8. The phase of DCLK relative to the data output bits may be adjusted depending on the operating mode. This is
controlled differently depending on the configuration of the digital signal post-processing, PLL and/or DLL. See
also Addresses 0x52, 0x64 and 0x6D (Registers 5-7, 5-22 and 5-28) for more details.
9. The device is in Reset mode while this pin stays “Low”. On the rising edge of RESET, the device exits Reset
mode, initializes all internal user registers to default values, and begins power-up calibration.
10. (a) SLAVE = “High”: The device is selected as slave and the SYNC pin becomes input pin.
(b) SLAVE = “Low”: The device is selected as master and the SYNC pin becomes output pin. In SLAVE/SYNC
operation, master and slave devices are synchronized to the same clock.
DS20006382A-page 10
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 1-2:
DATA OUTPUT PINS FOR EACH RESOLUTION OPTION
Output Pin Name
ADC
Q15/ Q14/ Q13/ Q12/ Q11/ Q10/ Q9/ Q8/
Q7+ Q7- Q6+ Q6- Q5+ Q5- Q4+ Q4-
Q7/
Q3+
Q6/
Q3-
Q5/
Q4/
Q3/
Q2/
Q1-
Q1/
Q0/ DM1/ DM2
Resolution
Q2+ Q2- Q1+
Q0+ Q0- DM+ /DM-
Q15 pin is MSb (bit 17), and DM2 is LSb (bit 0)
Q15 pin is MSb, and Q0 is LSb
18-bit mode
16-bit mode
14-bit mode(1)
12-bit mode
10-bit mode
Notused(2)
Not used(2)
Not used(2)
Not used(2)
Q15 pin is MSb, and Q2 is LSb
Q15 pin is MSb, and Q4 is LSb
Q15 pin is MSb, and Q6 is LSb
Note 1: The MCP37D21-80 has the 14-bit mode option only, while the MCP37D31-80 has all listed resolution
options (from 10-bit to 18-bit).
2: Output condition at “not-used” output pin:
-
-
‘0’ in CMOS mode. Leave these pins floating.
High Z state in LVDS mode
2020 Microchip Technology Inc.
DS20006382A-page 11
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 12
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
2.0
2.1
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings†
Analog and Digital Supply Voltage (AV
Analog and Digital Supply Voltage (AV
DV
DV
)......................................................................................................-0.3V to 1.32V
)......................................................................................................-0.3V to 1.98V
DD12,
DD18,
DD12
DD18
All Inputs and Outputs with respect to GND....................................................................................................... -0.3V to AV
+ 0.3V
- GND|
DD18
Differential Input Voltage ................................................................................................................................................|AV
DD18
Current at Input Pins .................................................................................................................................................................... ±2 mA
Current at Output and Supply Pins ......................................................................................................................................... ±250 mA
Storage Temperature ................................................................................................................................................... -65°C to +150°C
Ambient Temperature with Power Applied (T )............................................................................................................ -55°C to +125°C
A
Maximum Junction Temperature (T )..........................................................................................................................................+150°C
J
ESD Protection on all Pins................................................................................................................................................... ≤2 kV HBM
Solder Reflow Profile...............................................................................................See Microchip Application Note AN233 (DS00233)
Notice†: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in
the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
2.2
Electrical Specifications
ELECTRICAL CHARACTERISTICS
TABLE 2-1:
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
DD18
A
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12 IN
DD12
DD12
amplitude of -1 dBFS, f = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Power Supply Requirements
Analog Supply Voltage
AVDD18
AVDD12
DVDD18
DVDD12
1.71
1.14
1.71
1.14
1.8
1.2
1.8
1.2
1.89
1.26
1.89
1.26
V
V
V
V
Note 1
Digital Supply Voltage
Analog Supply Current During Conversion
at AVDD18 pin
at AVDD12 pin
IDD_A18
IDD_A12
—
12.5
20
mA
mA
T
T
= -40°C to +85°C
= +85°C to +125°C
—
—
132
132
170
173
A
A
Digital Supply Current
T
T
= -40°C to +85°C
= +85°C to +125°C
During Conversion
at DVDD12 pin
IDD_D12
IDD_D18
—
—
58
58
105
149
mA
A
A
Digital I/O Current in
CMOS Output Mode
Measured at DVDD18 Pin, DCLK = 80 MHz, T = -40°C to +125°C
A
—
—
13
11
20
16
mA MCP37D31-80
MCP37D21-80
Digital I/O Current in
LVDS Mode
IDD_D18
MCP37D31-80, Measured at DVDD18 Pin, T = -40°C to +125°C
A
—
—
—
51
36
66
—
—
—
mA LVDS_IMODE<2:0> = 3.5 mA
LVDS_IMODE<2:0> =1.8mA
LVDS_IMODE<2:0> =5.4mA
MCP37D21-80, Measured at DVDD18 Pin, T = -40°C to +125°C
A
—
—
—
46
33
59
—
—
—
mA LVDS_IMODE<2:0> = 3.5 mA
LVDS_IMODE<2:0> =1.8mA
LVDS_IMODE<2:0> =5.4mA
DS20006382A-page 13
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
DD18
A
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12 IN
DD12
DD12
amplitude of -1 dBFS, f = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Supply Current during Power-Saving Modes
During Standby Mode
During Shutdown Mode
ISTANDBY_AN
ISTANDBY_DIG
IDD_SHDN
—
—
—
43
23
23
—
—
—
mA Address 0x00<4:3> = 1,1(2)
mA Address 0x00<7,0> = 1,1(3)
PLL Circuit
PLL Circuit Current
IDD_PLL
—
17
—
mA PLL enabled. Included in
analog supply current
specification.
Total Power Dissipation(4)
Power Dissipation
During Conversion,
Excluding Digital I/O
PDISS_ADC
PDISS_CMOS
PDISS_LVDS
—
229
—
mW
Total Power Dissipation
During Conversion with
CMOS Output Mode
—
—
257
253
—
—
mW MCP37D31-80
MCP37D21-80
@DCLK = 80 MHz
Total Power Dissipation
During Conversion with
LVDS Output Mode
—
—
329
320
—
—
mW MCP37D31-80
MCP37D21-80
@LVDS_IMODE<2:0> = 3.5 mA
(2)
Address 0x00<4:3> = 1,1
P
During Standby Mode
During Shutdown Mode
—
—
79
22
—
—
mW
DISS_STANDBY
(3)
Address 0x00<7,0> = 1,1
PDISS_SHDN
mW
Power-on Reset (POR) Voltage
Threshold Voltage
Hysteresis
VPOR
—
—
800
40
—
—
mV Applicable to AVDD12 only
VPOR_HYST
mV (POR tracks AVDD12)
SENSE Input(5,7)
SENSE Input Voltage
VSENSE
GND
—
—
AVDD12
—
V
VSENSE selects reference
To virtual ground at 0.55V.
SENSE Pin Input
Resistance
RIN_SENSE
500
400 mV < V
< 800 mV
SENSE
Current Sink into SENSE
Pin
ISENSE
—
—
—
4.5
636
-2
—
—
—
µA
SENSE = 1.2V
SENSE = 0.8V
SENSE = 0V
Reference and Common-Mode Voltages
Internal Reference Voltage
VREF
VREF1
VREF0
VBG
—
—
—
—
—
—
—
—
—
—
0.74
1.49
—
—
—
—
—
—
—
—
—
—
V
V
V
V
VSENSE = GND
(Selected by VSENSE
)
VSENSE = AVDD12
1.86 x VSENSE
400 mV < V
< 800 mV
< 800 mV
< 800 mV
SENSE
Reference Voltage
Output(7,8)
0.4
0.8
VSENSE = GND
SENSE = AVDD12
400 mV < V
V
0.4 - 0.8
0.7
SENSE
VSENSE = GND
1.4
VSENSE = AVDD12
0.7 - 1.4
0.55
400 mV < V
SENSE
Bandgap Voltage Output
Available at VBG pin
2020 Microchip Technology Inc.
DS20006382A-page 14
MCP37D31-80 AND MCP37D21-80
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
DD18
A
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12 IN
DD12
DD12
amplitude of -1 dBFS, f = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Common-Mode
Sym.
Min.
Typ.
Max.
Units
Conditions
VCM
—
0.9
—
V
Available at VCM pin
Voltage Output
Analog Inputs
Full-Scale Differential
Analog Input Range(5,7)
AFS
—
—
—
1.4875
2.975
—
—
—
VP-P VSENSE = GND
VSENSE = AVDD12
3.71875 x
VSENSE
400 mV < V
< 800 mV
SENSE
Analog Input Bandwidth
fIN_3dB
CIN
—
5
500
6
—
7
MHz AIN = -3 dBFS
Note 5, Note 9
Differential Input
Capacitance
pF
Analog Input Leakage
Current (AIN+, AIN- pins)
ILI_AH
ILI_AL
—
-1
—
—
+1
—
µA
µA
VIH = AVDD12
VIL = GND
)
ADC Conversion Rate(10
Conversion Rate
fS
—
—
80
Msps Optimized at 80 Msps
)
Clock Inputs (CLK+, CLK-)(11
Note 5
Note 5
Note 5
Clock Input Frequency
fCLK
—
300
—
80
—
250
800
—
MHz
mV
Differential Input Voltage
VCLK_IN
P
-P
Clock Jitter
Clock Input Duty Cycle(5)
CLKJITTER
175
50
f
SRMS
49
51
%
Duty cycle correction
disabled
30
—
50
—
70
%
Duty cycle correction
enabled
Input Leakage Current at
CLK input pin
ILI_CLKH
ILI_CLKL
+180
µA
µA
VIH = AVDD12
VIL = GND
T
T
= -40°C to +85°C
= +85°C to +125°C
-20
-30
—
—
—
—
A
A
Converter Accuracy(6)
ADC Resolution
(with no missing code)
—
—
—
—
—
—
—
—
—
—
—
—
16
14
—
—
—
—
—
—
—
—
bits MCP37D31-80
bits MCP37D21-80
LSb MCP37D31-80
Offset Error
OffsetER
±5
LSb
±1.25
±0.5
±2
MCP37D21-80
% of FS
Gain Error
GER
INL
Integral Nonlinearity
LSb MCP37D31-80
LSb MCP37D21-80
LSb MCP37D31-80
LSb MCP37D21-80
±0.5
±0.4
±0.1
70
Differential Nonlinearity
DNL
Analog Input
CMRRDC
dB
DC measurement
Common-Mode
Rejection Ratio
DS20006382A-page 15
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
DD18
A
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12 IN
DD12
DD12
amplitude of -1 dBFS, f = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
)
Dynamic Accuracy(6,14
Spurious Free Dynamic
Range
SFDR
76.2
93
—
dBc fIN = 15 MHz
MCP37D31-80, MCP37D21-80
Signal-to-Noise Ratio
SNR
fIN = 15 MHz
71
71
—
73.9
73.5
12
—
—
—
—
—
dBFS MCP37D31-80
dBFS MCP37D21-80
bits MCP37D31-80
bits MCP37D21-80
Effective Number of Bits
ENOB
fIN = 15 MHz
)
(ENOB)(12
—
11.9
-89
Total Harmonic Distortion
(for all resolutions, first 13
harmonics)
THD
-78
dBc
fIN = 15 MHz
MCP37D31-80, MCP37D21-80
Worst Second or
Third Harmonic Distortion
HD2 or HD3
IMD
—
—
-93
85
—
—
dBc fIN = 15 MHz
MCP37D31-80, MCP37D21-80
Two-Tone Intermodulation
Distortion
dBc
AIN = -7 dBFS,
with two input frequencies
f
f
IN1 = 17.6 MHz,
IN2 = 20.4 MHz
Digital Logic Input and Output (Except LVDS Output)
0.7 DV
Schmitt Trigger High-Level
Input Voltage
VIH
—
—
DV
V
V
V
DD18
DD18
Schmitt Trigger Low-Level
Input Voltage
VIL
GND
0.3 DV
DD18
—
Hysteresis of Schmitt
Trigger Inputs
VHYST
0.05 DVDD18
—
(All digital inputs)
Low-Level Output Voltage
High-Level Output Voltage
VOL
VOH
—
—
0.3
—
V
V
IOL = -3 mA, all digital I/O pins
IOL = +3 mA, all digital I/O pins
DVDD18 – 0.5
1.8
Input Leakage Current on Digital I/O Pins
V
= DV
DD18
Data Output Pins
ILI_DH
ILI_DL
—
—
+1
µA
µA
IH
IL
V
T
= GND
= -40°C to +85°C
-1
-1.2
—
—
—
—
A
T
= +85°C to +125°C
A
V
V
= DV
I/O Pins except Data
Output Pins
ILI_DH
ILI_DL
—
—
—
+6
—
µA
µA
IH
DD18
(13)
= GND
-35
IL
2020 Microchip Technology Inc.
DS20006382A-page 16
MCP37D31-80 AND MCP37D21-80
TABLE 2-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
DD18
A
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12 IN
DD12
DD12
amplitude of -1 dBFS, f = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Digital Data Output (CMOS Mode)
Maximum External Load
Capacitance
CLOAD
CINT
10
4
pF
pF
From output pin to GND
—
—
—
—
Note 5
Internal I/O Capacitance
Digital Data Output (LVDS Mode)(5)
LVDS High-Level
Differential Output Voltage
VH_LVDS
VL_LVDS
VCM_LVDS
CINT_LVDS
RLVDS
200
-400
1
300
-300
1.15
4
400
-200
1.4
—
mV 100 differential termination,
LVDS_IMODE<2:0> = 3.5 mA
LVDS Low-Level
Differential Output Voltage
mV 100 differential termination,
LVDS_IMODE<2:0> = 3.5 mA
LVDS Common-Mode
Voltage
V
Output Capacitance
—
pF
Internal capacitance from
output pin to GND
Differential Load
—
100
—
Across LVDS output pairs
Resistance (LVDS)
Notes:
1. This1.8V digitalsupplyvoltageis usedfor thedigitalI/Ocircuit, includingSPI, CMOSandLVDSdataoutputdrivers.
2. Standby Mode: Most of the internal circuits are turned off, except the internal reference, clock, bias circuits and
SPI interface.
3. Shutdown Mode: All circuits including reference and clock are turned off except the SPI interface.
4. Power dissipation (typical) is calculated by using the following equation:
(a) During operation:
PDISS = VDD18 x (IDD_A18 + IDD_D18) + VDD12 x (IDD_A12 + IDD_D12), where IDD_D18 is the digital I/O current for
LVDS or CMOS output. VDD18 = 1.8V and VDD12 = 1.2V are used for typical value calculation.
(b) During Standby mode:
P
DISS_STANDBY = (ISTANDBY_AN + ISTANDBY_DIG) x 1.2V
(c) During Shutdown mode:
DISS_SHDN = IDD_SHDN x 1.2V
P
5. This parameter is ensured by design, but not 100% tested in production.
6. This parameter is ensured by characterization, but not 100% tested in production.
7. See Table 4-2 for details.
8. Differential reference voltage output at REF1+/- and REF0+/- pins. VREF1 = VREF1+ – VREF1-.
VREF0 = VREF0+ – VREF0-. These references should not be driven.
9. Input capacitance refers to the effective capacitance between one differential input pin pair.
10. The ADC core conversion rate. In multi-channel mode, the conversion rate of an individual channel is fS/N, where
N is the number of input channels used.
11. See Figure 4-8 for the details of the clock input circuit.
12. ENOB = (SINAD - 1.76)/6.02.
13. This leakage current is due to the internal pull-up resistor.
14. Dynamic performance is characterized with CH(n)_DIG_GAIN<7:0> = 0011-1000.
DS20006382A-page 17
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 2-2:
TIMING REQUIREMENTS - LVDS AND CMOS OUTPUTS
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
A
DD18
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12 IN
DD12
DD12
amplitude of -1 dBFS, F = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA,
DCLK_PHDLY_DLL<2:0> = 000, +25°C is applied for typical value.
Parameter
Aperture Delay
Symbol
Min.
Typ.
Max.
Units
Conditions
Note 1
Note 1
Note 1
tA
—
—
—
—
1
1
—
—
—
—
ns
Clocks
%
Out-of-Range Recovery Time
Output Clock Duty Cycle
Pipeline Latency
tOVR
50
28
TLATENCY
Clocks Note 2, Note 4
System Calibration(1)
Power-Up Calibration Time
TPCAL
TBCAL
—
—
227
230
—
—
Clocks First 227 sample clocks after
power-up
Clocks Per 230 sample clocks after
Background Calibration Update
Rate
TPCAL
RESET Low Time
TRESET
5
—
—
ns
See Figure 2-8 for details(1)
AutoSync (1,6)
Sync Output Time Delay
TSYNC_OUT
—
—
1
—
—
Clocks
MHz
Maximum Recommended ADC
Clock Rate for AutoSync
80
)
LVDS Data Output Mode(1,5
Input Clock to
Output Clock Propagation Delay
tCPD
tDC
—
—
—
5.7
0.5
5.8
—
—
—
ns
ns
ns
Output Clock to
Data Propagation Delay
Input Clock to
tPD
Output Data Propagation Delay
CMOS Data Output Mode(1)
Input Clock to
Output Clock Propagation Delay
tCPD
tDC
—
—
—
3.8
0.7
4.5
—
—
—
ns
ns
ns
Output Clock to
Data Propagation Delay
Input Clock to
tPD
Output Data Propagation Delay
Note 1: This parameter is ensured by design, but not 100% tested in production.
2: This parameter is ensured by characterization, but not 100% tested in production.
3: RISE = approximately less than 10% of duty cycle.
t
4: Output latency is measured without using fractional delay recovery (FDR), decimation filter or digital
down-converter options.
5: The time delay can be adjusted with the DCLK_PHDLY_DLL<2:0> setting.
6: Characterized with a single slave device. The maximum ADC sample rate for AutoSync mode may be
reduced if multiple slave devices are used. See Figure 2-9 - Figure 2-11, and Figure 4-27 for details.(
2020 Microchip Technology Inc.
DS20006382A-page 18
MCP37D31-80 AND MCP37D21-80
S-1
Input Signal:
S+1
S+L
S+L-1
S
*S = Sample Point
tA
Latency = L Cycles
Input Clock:
CLK-
CLK+
tCPD
Digital Clock Output:
DCLK
tDC
tPD
Output Data:
Q<N:0>
S-L-1
S-L-1
S-L
S-1
S-1
S-L+1
S-L+1
S
S
Over-Range Output:
OVR
S-L
Note:
FIGURE 2-1:
If the output resolution is selected for less than 16-bit, unused bits are ‘0’s.
Timing Diagram - CMOS Output.
S-1
Input Signal:
S+1
S+L
S+L-1
S
*S = Sample Point
tA
Latency = L Cycles
Input Clock:
CLK-
CLK+
Digital Clock Output:
tCPD
DCLK-
DCLK+
tDC
tPD
Output Data:
Q-[N:0]
EVEN
S-L-1
ODD
S-L-1
EVEN ODD
EVEN
S-L+1
EVEN
S-1
ODD
S-1
EVEN
S
S-L
S-L
Q+[N:0]
Word-CLK/
Over-Range Output:
WCK/OVR-
WCK/OVR+
WCK
S-L-1
OVR
S-L-1
WCK
S-L
OVR
S-L
WCK
S-L+1
WCK
S-1
OVR
S-1
WCK
S
Note:
FIGURE 2-2:
If the output resolution is selected for less than 16-bit, unused bits are High Z.
Timing Diagram - LVDS Output with Even Bit First Option.
DS20006382A-page 19
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
S-1
Input Signal:
S+1
S+L
S+L-1
S
tA
Latency = L Cycles
Input Clock:
CLK Output:
CLK-
CLK+
tCPD
DCLK-
DCLK+
tDC
tPD
Output Data:
Q-[N:0]
b[15:8] b[7:0] b[15:8] b[7:0] b[15:8]
b[15:8] b[7:0] b[15:8]
S-L-1
S-L-1
S-L
S-L
S-L+1
S-1
S-1
S
Q+[N:0]
Word-CLK/
Over-Range Output:
WCK/OVR-
WCK
OVR
WCK
S-L
OVR
S-L
WCK
S-L+1
OVR
S-1
WCK
S
WCK
S-1
S-L-1 S-L-1
WCK/OVR+
FIGURE 2-3:
Timing Diagram - LVDS Output with MSb Byte First Option. This output option is
available for 16-bit mode only.
2020 Microchip Technology Inc.
DS20006382A-page 20
MCP37D31-80 AND MCP37D21-80
Ch.7
Input Signal:
Ch.1
Ch.0
tA
Ch.7
Ch.0
Latency = L Cycles
Input Clock:
CLK-
CLK+
CLK Output:
tCPD
DCLK-
DCLK+
tDC
tPD
Output Data:
Q-[0]
b[1]
b[0]
b[15]
b[14]
Ch.0
b[13]
Ch.0
b[1]
b[0]
b[15]
Ch.0
Ch.0
Ch.0
Ch.0
Ch.0
Ch.0
Q+[0]
Q-[1]
b[1]
Ch.1
b[0]
Ch.1
b[15]
Ch.1
b[14]
Ch.1
b[13]
Ch.1
b[1]
Ch.1
b[0]
Ch.1
b[15]
Ch.1
Q+[1]
Q-[7]
b[1]
Ch.7
b[0]
Ch.7
b[15]
Ch.7
b[14]
Ch.7
b[13]
Ch.7
b[1]
Ch.7
b[0]
Ch.7
b[15]
Ch.7
Q+[7]
Word-CLK/
Over-Range Output:
WCK/OVR-
WCK/OVR+
WCK
“1”
WCK
“1”
OVR
OVR
OVR
“0”
“0”
“0”
Note: Q+/Q-[7] is the first channel selected data, and Q+/Q-[0] is the last channel selected data.
FIGURE 2-4:
Timing Diagram - LVDS Serial Output in Octal-Channel Mode. This output is available
for octal-channel with 16-bit mode only. Note that although the eight input channels are sampled
sequentially (auto-scan with 1 cycle separation), all channels are output simultaneously with the MSb (bit
15) synchronized with the rising edge of WCK.
DS20006382A-page 21
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 2-3:
SPI SERIAL INTERFACE TIMING SPECIFICATIONS
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
A
DD18
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12
DD12
DD12 IN
amplitude of -1 dBFS, F = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value. All timings are measured at 50%.
Parameters
Symbol
Min.
Typ.
Max.
Units
Conditions
Serial Clock frequency, fSCK = 50 MHz
CS Setup Time
tCSS
10
20
20
2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
20
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
CS Hold Time
tCSH
tCSD
tSU
tHD
CS Disable Time
Data Setup Time
Data Hold Time
4
Serial Clock High Time
Serial Clock Low Time
Output Valid from SCK Low
Output Disable Time
tHI
8
tLO
8
tDO
—
—
tDIS
tCSD
CS
tSCK
tLO
tCSS
tCSH
tHI
SCLK
tHD
tSU
SDIO
(SDI)
MSb in
LSb in
FIGURE 2-5:
SPI Serial Input Timing Diagram.
CS
tSCK
tCSH
tHI
tLO
SCLK
tDO
tDIS
SDIO
MSb out
LSb out
(SDO)
FIGURE 2-6:
SPI Serial Output Timing Diagram.
2020 Microchip Technology Inc.
DS20006382A-page 22
MCP37D31-80 AND MCP37D21-80
Power-on Reset (POR)
AVDD12
227 cycles
(TPCAL
)
Power-Up calibration complete.
• Registers are initialized
• Device is ready for correct conversion
FIGURE 2-7:
POR-Related Events: Register Initialization and Power-Up Calibration.
RESET Pin
tRESET
Power-Up Calibration Time
(TPCAL
)
Stop ADC conversion
Start register initialization
and ADC recalibration
Recalibration complete:
• CAL Pin: High
• ADC_CAL_STAT = 1
FIGURE 2-8:
RESET Pin Timing Diagram.
A. Master Device (SLAVE Pin = 0)
POR (Power-On Reset)
(~ 220 clock cycles)
Toggle to High at the 2nd rising edge of Clock Input
TSYNC_OUT
SYNC Output
CAL Pin (Output)
TPCAL
Valid Data
Invalid Data
Data Output
Clock Input
1
2
B. Slave Device(s)
(SLAVE Pin = 1)
SYNC Input
CAL Pin (Output)
Data Output
TPCAL
Invalid Data
2
Valid Data
1
Clock Input
FIGURE 2-9:
Sync Timing Diagram with Power-On Reset.
DS20006382A-page 23
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
(SLAVE Pin = 0)
A. Master Device
RESET Pin
TSYNC_OUT
SYNC Output
CAL Pin (Output)
Data Output
TPCAL
Invalid Data
Valid Data
1
2
Clock Input
B. Slave Device(s)(SLAVE Pin = 1)
SYNC Input
CAL Pin (Output)
Data Output
TPCAL
Invalid Data
Valid Data
Clock Input
FIGURE 2-10:
Sync Timing Diagram with RESET Pin Operation.
A. Master Device (SLAVE Pin = 0)
POR
(~ 220 clock cycles)
Toggle to High at the 2nd rising edge of Clock Input after POR
Toggle to High at the 2nd rising edge of Clock Input
after SOFT_RESET = 1
SYNC Output
T
SYNC_OUT
SPI SOFT RESET Control
SOFT_RESET = 0
SOFT_RESET = 1
T
PCAL
CAL Pin (Output)
Data Output
T
PCAL
No Output
Invalid
Data
Valid
Data
Valid Data
Invalid Data
2
1
2
1
Clock Input
B. Slave Device(s)
(SLAVE Pin = 1)
SYNC Input
T
PCAL
CAL Pin (Output)
Data Output
T
PCAL
No Output
Valid
Data
Invalid
Data
Invalid Data
2
Valid Data
1
2
1
Clock Input
FIGURE 2-11:
Sync Timing Diagram with SOFT_RESET Bit Setting.
2020 Microchip Technology Inc.
DS20006382A-page 24
MCP37D31-80 AND MCP37D21-80
TABLE 2-4:
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise specified, all parameters apply for T = -40°C to +125°C, AV
= DV
= 1.8V,
A
DD18
DD18
AV
= DV
= 1.2V, GND = 0V, SENSE = AV
, Single-channel mode, Differential Analog Input (A ) = Sine wave with
DD12
DD12
DD12 IN
amplitude of -1 dBFS, F = 15 MHz, Clock Input = 80 MHz, f = 80 Msps (ADC Core), Resolution = 16-bit, PLL and decimation
IN
S
filters are disabled, Output load: CMOS data pin = 10 pF, LVDS = 100termination, LVDS driver current setting = 3.5 mA, +25°C is
applied for typical value.
Parameters
Temperature Ranges(1)
Sym.
Min.
Typ. Max. Units Conditions
Operating Temperature Range
TA
-40
—
+125
°C
Thermal Package Resistances(2)
Junction-to-Ambient Thermal Resistance
Junction-to-Case Thermal Resistance
JA
JC
—
—
40.2
8.4
—
—
°C/W
°C/W
Note 1: Maximum allowed power-dissipation (PDMAX) = (TJMAX - TA)/JA
.
2: This parameter value is achieved by package simulations.
DS20006382A-page 25
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
3.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise specified, all plots are at 25°C, AVDD18 = DVDD18 = 1.8V, AVDD12 = DVDD12 = 1.2V, GND = 0V,
SENSE = AVDD12, single-channel mode, differential analog input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 14.7 MHz,
clock input = 80 MHz, fS = 80 Msps (ADC Core), MCP37D31-80 (16-bit), PLL and decimation filters are disabled.
0
-20
0
-20
Mode = Single-Channel
Mode = Single-Channel
f
f
f
= 80 MHz
= 80 Msps
= 4.3 MHz @ -1.0 dBFS
CLK
f
f
f
= 80 MHz
= 80 Msps
= 4.3 MHz @ -4.0 dBFS
CLK
S
S
-40
IN
-40
IN
SNR = 73.7 dB (74.7 dBFS)
SFDR = 91.4 dBc
SNR = 71.0 dB (75 dBFS)
SFDR = 96.0 dBc
-60
THD = -90.2 dBc
-60
THD = -92.3 dBc
Resolution = 16-bit
Resolution = 16-bit
-80
-80
3
2
3
8
2
-100
-120
-100
-120
6
5
7
9
8
5
4
7
6
4
9
0
10
20
Frequency (MHz)
30
40
0
10
20
Frequency (MHz)
30
40
FIGURE 3-1:
Signal: fS = 80 Msps, Single-Ch., AIN = -1 dBFS.
FFT for 4.3 MHz Input
FIGURE 3-4:
Signal: fS = 80 Msps, Single-Ch., AIN = -4 dBFS.
FFT for 4.3 MHz Input
0
0
Mode = Dual-Channel
Mode = Dual-Channel
f
f
f
= 80 MHz
-20
-40
-20
-40
f
f
f
= 80 MHz
CLK
CLK
= 40 Msps
= 40 Msps
S
S
= 4.3 MHz @ -1.0 dBFS
= 4.3 MHz @ -4.0 dBFS
IN
IN
SNR = 73.9 dB (74.9 dBFS)
SFDR = 90.3 dBc
SNR = 70.9 dB (74.9 dBFS)
SFDR = 95.3 dBc
-60
-60
THD = -88.6 dBc
THD = -91.4 dBc
Resolution = 16-bit
Resolution = 16-bit
-80
-80
3
2
2
3
-100
-120
-100
-120
4
7
7
4
8
5
6
5
9
6
8
9
0
5
10
15
20
0
5
10
15
20
Frequency (MHz)
Frequency (MHz)
FIGURE 3-2:
FFT for 4.3 MHz Input
FIGURE 3-5:
FFT for 4.3 MHz Input
Signal: fS = 40 Msps, Dual-Ch., AIN = -1 dBFS.
Signal: fS = 40 Msps, Dual-Ch., AIN = -4 dBFS.
0
Mode = Quad-Channel
f
f
f
= 80 MHz
-20
-40
CLK
= 20 Msps
S
= 4.3 MHz @ -1.0 dBFS
IN
SNR = 73.6 dB (74.6 dBFS)
SFDR = 90.0 dBc
-60
THD = -87.9 dBc
Resolution = 16-bit
-80
3
2
4
-100
-120
7
9
6
8
5
0
2
4
6
8
10
Frequency (MHz)
FIGURE 3-3:
FFT for 4.3 MHz Input
FIGURE 3-6:
FFT for 4.3 MHz Input
Signal: fS = 20 Msps, Quad-Ch., AIN = -1 dBFS.
Signal: fS = 20 Msps, Quad-Ch., AIN = -4 dBFS.
2020 Microchip Technology Inc.
DS20006382A-page 26
MCP37D31-80 AND MCP37D21-80
0
0
-20
Mode = Octal-Channel
Mode = Octal-Channel
f
f
f
= 80 MHz
= 10 Msps
= 4.3 MHz @ -1.0 dBFS
-20
-40
CLK
f
f
f
= 80 MHz
= 10 Msps
= 4.3 MHz @ -4.0 dBFS
CLK
S
S
IN
-40
IN
SNR = 73.7 dB (74.7 dBFS)
SFDR = 90.5 dBc
SNR = 71.0 dB (75 dBFS)
SFDR = 95.8 dBc
-60
-60
THD = -88.3 dBc
THD = -91.8 dBc
Resolution = 16-bit
Resolution = 16-bit
-80
-80
3
2
8
6
3
4
2
-100
-120
-100
-120
6
5
7
8
9
5
9
7
4
0
1
2
3
4
5
0
1
2
3
4
5
Frequency (MHz)
Frequency (MHz)
FIGURE 3-7:
Signal: fS = 10 Msps, Octal-Ch., AIN = -1 dBFS.
FFT for 4.3 MHz Input
FIGURE 3-10:
Signal: fS = 10 Msps, Octal-Ch, AIN = -4 dBFS.
FFT for 4.3 MHz Input
0
Mode = Single-Channel
-20
-40
f
f
f
= 80 MHz
= 80 Msps
= 14.7 MHz @ -4.0 dBFS
CLK
S
IN
SNR = 70.3 dB (74.3 dBFS)
SFDR = 95.2 dBc
-60
THD = -94.0 dBc
Resolution = 16-bit
-80
2
9
-100
-120
6
7
8
3
4
0
10
20
30
40
Frequency (MHz)
FIGURE 3-8:
FFT for 14.7 MHz Input
FIGURE 3-11:
FFT for 14.7 MHz Input
Signal: fS = 80 Msps, Single-Ch., AIN = -1 dBFS.
Signal: fS = 80 Msps, Single-Ch., AIN = -4 dBFS.
0
0
Mode = Dual-Channel
Mode = Dual-Channel
f
f
f
= 80 MHz
= 40 Msps
= 14.7 MHz @ -1.0 dBFS
-20
-40
-20
-40
f
f
f
= 80 MHz
CLK
CLK
= 40 Msps
= 14.7 MHz @ -4.0 dBFS
S
S
IN
IN
SNR = 72.8 dB (73.8 dBFS)
SFDR = 92.3 dBc
SNR = 70.4 dB (74.4 dBFS)
SFDR = 97.2 dBc
-60
-60
THD = -90.0 dBc
THD = -95.9 dBc
Resolution = 16-bit
Resolution = 16-bit
-80
-80
2
3
5
2
-100
-120
-100
-120
9
3
5
7
6
4
9
7
8
6
0
5
10
Frequency (MHz)
15
20
0
5
10
Frequency (MHz)
15
20
FIGURE 3-9:
Signal: fS = 40 Msps, Dual-Ch., AIN = -1 dBFS.
FFT for 14.7 MHz Input
FIGURE 3-12:
Signal: fS = 40 Msps, Dual-Ch., AIN = -4 dBFS.
FFT for 14.7 MHz Input
DS20006382A-page 27
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Note: Unless otherwise specified, all plots are at 25°C, AVDD18 = DVDD18 = 1.8V, AVDD12 = DVDD12 = 1.2V, GND = 0V,
SENSE = AVDD12, single-channel mode, differential analog input (AIN) = sine wave with amplitude of -1 dBFS,
fIN = 14.7 MHz, clock input = 80 MHz, fS = 80 Msps (ADC Core), MCP37D21-80 (14-bit), PLL and decimation filters are
disabled.
0
-20
0
-20
Mode = Single-Channel
Mode = Single-Channel
f
f
f
= 80 MHz
= 80 Msps
f
= 80 MHz
CLK
CLK
f
f
= 80 Msps
= 4.3 MHz @ -1.0 dBFS
S
S
= 4.3 MHz @ -4.0 dBFS
-40
-40
IN
IN
SNR = 73.7 dB (74.7 dBFS)
SNR = 70.7 dB (74.7 dBFS)
SFDR = 93.8 dBc
THD = -92.6 dBc
Resolution = 14-bit
SFDR = 97.6 dBc
THD = -96.7 dBc
Resolution = 14-bit
-60
-60
-80
-80
3
5
-100
-120
2
3
-100
-120
4
9
2
4
7
6
5
6
8
7
8
9
0
10
20
Frequency (MHz)
30
40
0
10
20
Frequency (MHz)
30
40
FIGURE 3-13:
Signal: fS = 80 Msps, Single-Ch., AIN = -1 dBFS.
FFT for 4.3 MHz Input
FIGURE 3-16:
Signal: fS = 80 Msps, Single-Ch., AIN = -4 dBFS.
FFT for 4.3 MHz Input
0
0
-20
Mode = Dual-Channel
Mode = Dual-Channel
-20
-40
f
f
f
= 80 MHz
= 40 Msps
= 4.3 MHz @ -4.0 dBFS
f
f
f
= 80 MHz
= 40 Msps
= 4.3 MHz @ -1.0 dBFS
CLK
CLK
S
S
-40
IN
IN
SNR = 70.7 dB (74.7 dBFS)
SFDR = 97.5 dBc
SNR = 73.6 dB (74.6 dBFS)
SFDR = 92.1 dBc
-60
-60
THD = -93.2 dBc
THD = -91.0 dBc
Resolution = 14-bit
Resolution = 14-bit
-80
-80
3
3
6
2
5
-100
-120
2
-100
-120
9
4
8
7
6
8
4
7
9
5
0
5
10
Frequency (MHz)
15
20
0
5
10
15
20
Frequency (MHz)
FIGURE 3-14:
FFT for 4.3 MHz Input
FIGURE 3-17:
FFT for 4.3 MHz Input
Signal: fS = 40 Msps, Dual-Ch., AIN = -1 dBFS.
Signal: fS = 40 Msps, Dual-Ch., AIN = -4 dBFS.
FIGURE 3-15:
FFT for 4.3 MHz Input
FIGURE 3-18:
FFT for 4.3 MHz Input
Signal: fS = 20 Msps, Quad-Ch., AIN = -1 dBFS.
Signal: fS = 20 Msps, Quad-Ch., AIN = -4 dBFS.
2020 Microchip Technology Inc.
DS20006382A-page 28
MCP37D31-80 AND MCP37D21-80
0
0
-20
Mode = Octal-Channel
Mode = Octal-Channel
-20
-40
f
f
f
= 80 MHz
= 10 Msps
= 4.3 MHz @ -1.0 dBFS
CLK
f
f
f
= 80 MHz
CLK
S
= 10 Msps
= 4.3 MHz @ -4.0 dBFS
S
IN
-40
IN
SNR = 73.5 dB (74.5 dBFS)
SFDR = 91.7 dBc
SNR = 70.8 dB (74.8 dBFS)
SFDR = 97.0 dBc
-60
THD = -89.8 dBc
-60
THD = -95.0 dBc
Resolution = 14-bit
Resolution = 14-bit
-80
-80
3
4
8
7
6
-100
-120
2
5
9
3
4
-100
-120
8
2
5
9
7
6
0
1
2
3
4
5
0
1
2
3
4
5
Frequency (MHz)
Frequency (MHz)
FIGURE 3-19:
Signal: fS = 10 Msps, Octal-Ch., AIN = -1 dBFS.
FFT for 4.3 MHz Input
FIGURE 3-22:
Signal: fS = 10 Msps, Octal-Ch, AIN = -4 dBFS.
FFT for 4.3 MHz Input
Mode = Single-Channel
f
f
f
= 80 MHz
= 80 Msps
= 14.7 MHz @ -1.0 dBFS
-20
-40
CLK
S
IN
SNR = 72.5 dB (73.5 dBFS)
SFDR = 93.6 dBc
-60
THD = -90.1 dBc
Resolution = 14-bit
-80
2
3
5
-100
-120
7
4
9
8
6
10
20
Frequency (MHz)
30
40
FIGURE 3-20:
FFT for 14.7 MHz Input
FIGURE 3-23:
FFT for 14.7 MHz Input
Signal: fS = 80 Msps, Single-Ch., AIN = -1 dBFS.
Signal: fS = 80 Msps, Single-Ch., AIN = -4 dBFS.
0
-20
0
Mode = Dual-Channel
Mode = Dual-Channel
-20
f
f
f
= 80 MHz
f
f
f
= 80 MHz
CLK
CLK
= 40 Msps
= 14.7 MHz @ -4.0 dBFS
= 40 Msps
= 14.7 MHz @ -1.0 dBFS
S
S
-40
-40
-60
IN
IN
SNR = 70.0 dB (74.0 dBFS)
SFDR = 94.7 dBc
SNR = 72.7 dB (73.7 dBFS)
SFDR = 93.9 dBc
-60
THD = -93.6 dBc
THD = -90.9 dBc
Resolution = 14-bit
Resolution = 14-bit
-80
-80
2
3
2
5
7
-100
-120
-100
-120
5
3
4
9
4
8
6
7
6
9
0
5
10
Frequency (MHz)
15
20
0
5
10
Frequency (MHz)
15
20
FIGURE 3-21:
Signal: fS = 40 Msps, Dual-Ch., AIN = -1 dBFS.
FFT for 14.7 MHz Input
FIGURE 3-24:
Signal: fS = 40 Msps, Dual-Ch., AIN = -4 dBFS.
FFT for 14.7 MHz Input
DS20006382A-page 29
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Note: Unless otherwise specified, all plots are at 25°C, AVDD18 = DVDD18 = 1.8V, AVDD12 = DVDD12 = 1.2V, GND = 0V,
SENSE = AVDD12, single-channel mode, differential analog input (AIN) = sine wave with amplitude of -1 dBFS, fIN = 14.7 MHz,
clock input = 80 MHz, fS = 80 Msps (ADC Core), MCP37D31-80 (16-bit), PLL and decimation filters are disabled.
120
110
100
90
120
110
100
90
SFDR (dBFS)
SNR (dBFS)
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SFDR (dBc)
80
80
70
70
60
50
60
50
SNR (dBc)
SNR (dBc)
40
30
20
40
30
20
SENSE = 1.2V
= 14.7 MHz
SENSE = 1.2V
f = 4.3 MHz
IN
Resolution = 16-bit
f
IN
Resolution = 16-bit
10
10
-50
-40
-30
-20
-10
0
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-25:
SNR/SFDR vs. Analog Input
FIGURE 3-27:
SNR/SFDR vs. Analog Input
Amplitude: fS = 80 Msps, fIN = 14.7 MHz,
High-Reference Mode (SENSE = AVDD12).
Amplitude: fS = 80 Msps, fIN = 4.3 MHz,
High-Reference Mode (SENSE = AVDD12).
110
100
110
100
SFDR (dBFS)
SFDR (dBFS)
90
90
80
70
60
SFDR (dBc)
80
70
60
50
40
30
20
10
SFDR (dBc)
SNR (dBc)
SNR (dBFS)
SNR (dBFS)
50
40
30
20
10
SNR (dBc)
SENSE = 0V
= 4.3 MHz
SENSE = 0V
= 14.7 MHz
f
f
IN
IN
Resolution = 16-bit
Resolution = 16-bit
-40
-30
-20
-10
-50
-40
-30
-20
-10
0
Input Amplitude (dBFS)
Input Amplitude (dBFS)
FIGURE 3-26:
SNR/SFDR vs. Analog Input
FIGURE 3-28:
SNR/SFDR vs. Analog Input
Amplitude: fS = 80 Msps, fIN = 14.7 MHz,
Low-Reference Mode (SENSE = GND).
Amplitude: fS = 80 Msps, fIN = 4.3 MHz,
Low-Reference Mode (SENSE = GND).
2020 Microchip Technology Inc.
DS20006382A-page 30
MCP37D31-80 AND MCP37D21-80
78
115
110
105
100
95
76
SFDR (dBFS)
74
72
70
68
90
SNR (dBFS)
66
64
62
60
85
80
f
= 15.3 MHz @ -1 dBFS
75
IN
Resolution = 16-bit
0.8
SENSE Pin Voltage (V)
70
0
0.2
0.4
0.6
1
1.2
FIGURE 3-29:
Two-Tone FFT. MCP37D31-
FIGURE 3-32:
SNR/SFDR vs. SENSE Pin
80.
Voltage: fIN = 15.3 MHz.
120
110
100
90
76
105
100
95
SNR (dBFS)
75
73
71
69
67
65
SNR (dBFS)
74
72
70
68
SFDR (dBFS)
SFDR (dBFS)
90
80
85
80
70
fIN = 15.3 MHz @ -1 dBFS
Resolution = 16-bit
f
= 4.3 MHz @ -1 dBFS
IN
60
66
20
0
0.2
0.4
0.6
External V
0.8
(V)
1
30
40
50
60
70
80
90
100
Sample Rate (Msps)
CM
FIGURE 3-30:
Rate (Msps): fIN = 4.3 MHz.
SNR/SFDR vs. Sample
FIGURE 3-33:
Rate (Msps). fIN = 15.3 MHz.
SNR/SFDR vs. Sample
120
110
100
90
76
100
90
SNR (dBFS)
SFDR (dBFS)
75
75
73
SNR (dBFS)
74
80
71
69
67
65
SFDR (dBFS)
80
73
72
70
Sample Rate = 80 Msps
Input Amplitude = -1 dBFS
Resolution = 16-bit
70
f
= 15.3 MHz @ -1 dBFS
IN
Resolution = 16-bit
60
60
0
10
20
30
40
50
60
70
0
0.2
0.4
0.6
External V
0.8
(V)
1
Input Frequency (MHz)
CM
FIGURE 3-31:
Frequency: fS = 80 Msps.
SNR/SFDR vs. Input
FIGURE 3-34:
(Externally Applied): fS = 80 Msps, fIN = 15.3
MHz.
SNR/SFDR vs. VCM Voltage
DS20006382A-page 31
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
1.385
1.38
96
94
92
74.8
74.4
74
AV
AV
AV
= 1.9V
= 1.8V
= 1.7V
DD18
DD18
DD18
SFDR (dBFS)
SNR (dBFS)
1.375
1.37
90
88
86
84
73.6
73.2
72.8
72.4
f
= 14.7 MHz @ -1 dBFS
IN
Resolution = 16-bit
1.365
-55 -35 -15
5
25
45
65
85 105 125
-40 -25 -10
5
20
35
50
65
80
95 110 125
o
Temperature (°C)
Temperature ( C)
FIGURE 3-35:
SNR/SFDRvs.Temperature:
FIGURE 3-38:
VREF0 vs. Temperature.
fS = 80 Msps, fIN = 14.7 MHz, VSENSE = AVDD12
,
AIN = -1 dBFS.
-90
-92
74.2
74.1
95
94
93
92
91
SFDR (dBFS)
HD2 (dBFS)
-94
-96
SNR (dBFS)
74
73.9
73.8
HD3 (dBFS)
-98
f
= 14.7 MHz @ -1 dBFS
f
= 14.7 MHz @ -1 dBFS
IN
IN
-100
Resolution = 16-bit
Resolution = 16-bit
73.7
90
-102
1.08/1.62
1.14/1.71
1.2/1.8
1.26/1.89
1.32/1.98
1.08/1.62
1.14/1.71
1.2/1.8
1.26/1.89
1.32/1.98
Supply Voltage (V)
Supply Voltage (V)
FIGURE 3-36:
Voltage: fS = 80 Msps, fIN = 14.7 MHz.
SNR/SFDR vs. Supply
FIGURE 3-39:
Voltage: fS = 80 Msps, fIN = 14.7 MHz.
HD2/HD3 vs. Supply
0.5
0.4
0.3
0.2
5
4
3
2
0.1
1
0
0
-0.1
-1
-2
-3
Gain Error (%)
Offset (LSB)
-0.2
-0.3
-40 -25 -10
5
20 35 50 65 80 95 110 125
Temperature (°C)
FIGURE 3-37:
Gain and Offset Error Drifts
Vs. Temperature using Internal Reference, with
Respect to 25°C: fS = 80 Msps, fIN = 14.7 MHz,
V
A
SENSE = AVDD12, Resolution = 16-bit,
IN = -1dBFS.
2020 Microchip Technology Inc.
DS20006382A-page 32
MCP37D31-80 AND MCP37D21-80
FIGURE 3-40:
INL Error Vs. Output Code:
FIGURE 3-43:
DNL Error Vs. Output Code:
fS = 80 Msps, fIN = 4.3 MHz, AIN = -1dBFS,
MCP37D31-80.
fS = 80 Msps, fIN = 4.3 MHz, AIN = -1dBFS,
MCP37D31-80.
0.6
0.4
0.2
0
0.3
0.2
0.1
0
-0.2
-0.1
-0.4
-0.2
MCP37D21-80
12288 16384
MCP37D21-80
-0.6
-0.3
0
4096
8192
0
4096
8192
12288
16384
Output Code
Output Code
FIGURE 3-41:
INL Error Vs. Output Code:
FIGURE 3-44:
DNL Error Vs. Output Code:
fS = 80 Msps, fIN = 4.3 MHz, AIN = -1dBFS,
MCP37D21-80.
fS = 80 Msps, fIN = 4.3 MHz, AIN = -1dBFS,
MCP37D21-80.
FIGURE 3-45:
Shorted Input Histogram:
FIGURE 3-42:
Shorted Input Histogram:
fS = 80 Msps, MCP37D21-80.
fS = 80 Msps, MCP37D31-80.
DS20006382A-page 33
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
160
300
280
260
240
220
200
180
160
140
A
= -1 dBFS
IN
I
ꢀ
ꢈꢅ
DD_A12
140
120
100
80
Total Power for ADC Core
(Except I/O)
IDD_D18
60
ꢈꢁꢀ
ꢈꢁꢅ
40
IDD_D12
IDD_A18
20
0
20
30
40
50
60
70
80
90
100
ꢀ
ꢁꢀꢀ
ꢂꢀꢀ
ꢃꢀꢀ
ꢄꢀꢀ
ꢅꢀꢀ
ꢆꢀꢀ
ꢇꢀꢀ
Sample Rate (Msps)
)UHTXHQF\ꢉꢊ0+]ꢋ
FIGURE 3-46:
Input Bandwidth.
FIGURE 3-47:
Power Consumption vs.
Sample Rate (LVDS Mode).
2020 Microchip Technology Inc.
DS20006382A-page 34
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 35
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
The device samples the analog input on the rising edge
of the clock. The digital output code is available after
28 clock cycles of data latency. Latency will increase if
any of the digital signal post-processing (DSPP)
options are enabled.
4.0
THEORY OF OPERATION
The MCP37D31-80 and MCP37D21-80 device family
is high-precision 80 Msps, 16-bit and 14-bit,
a
respectively, analog-to-digital converter (ADC) with
built-in features including Harmonic Distortion
Correction (HDC), DAC Noise Cancellation (DNC),
Dynamic Element Matching (DEM) and flash error
calibration.
The output data can be coded in two’s complement or off-
set binary format, and randomized using the user option.
Data can be output using either the CMOS or LVDS (Low-
Voltage Differential Signaling) interface. Serialized LVDS
output is also available in 16-bit octal-channel mode. In
this mode, each input channel is output serially over a
unique LVDS pair.
In addition to the analog-to-digital data conversion, the
device offers various built-in digital signal post-
processing (DSPP) features, such as high-order FIR
decimation filters, Digital Down-Conversion (DDC),
Fractional Delay Recovery (FDR), continuous wave
(CW) beamforming, and digital gain and offset
corrections per individual channel. These built-in
advanced digital signal post-processing sub-blocks,
which are individually controlled using Configuration
register bit settings, can be used for various special
applications such as I/Q demodulation, digital down-
conversion, and ultrasound imaging.
4.1
ADC Core Architecture
Figure 4-1 shows the simplified block diagram of the
ADC core. The first stage consists of a 17-level flash
ADC, multi-level Digital-to-Analog Converter (DAC)
and a residue amplifier with a gain of 8. Stages 2 to 6
consist of a 9-level (3-bit) flash ADC, multi-level DAC
and a residue amplifier with a gain of 4. The last stage
is a 9-level 3-bit flash ADC. Dither is added in each of
the first three stages.The digital outputs from all seven
stages are combined in a digital error correction logic
block and digitally processed for the final output.
When the device is first powered-up, it performs an
internal power-up calibration by itself and runs with
default settings. From this point, the user can configure
the device registers using the SPI command.
The first three stages include patented digital
calibration features:
The input channel is selected by setting-up the user-
control configuration register bits. In single-channel
operation, one of the 8-analog inputs can be selected.
In multi-channel mode, the inputs are sequentially
multiplexed by the input MUX defined by the scan
order. The input channel selection and the sequential
scan order for the selected input channel are
programmed using the configuration register bits.
• Harmonic Distortion Correction (HDC) algorithm
that digitally measures and cancels ADC errors
arising from distortions introduced by the residue
amplifiers
• DAC Noise Cancellation (DNC) algorithm that
corrects DAC’s nonlinearity errors
REF0
Reference Generator
REF1
Clock Generation
REF1
REF1
REF1
REF0
REF1
REF1
REF1
AIN0
+
AIN0
-
Pipeline
3-bit Flash
Pipeline
Pipeline
Pipeline
Pipeline
Pipeline
Stage 6
(2-bit)
Stage 7
(3-bit)
Input
MUX
Stage 4
(2-bit)
Stage 5
(2-bit)
Stage 2
(2-bit)
Stage 3
(2-bit)
Stage 1
(3-bit)
AIN7
+
HDC1, DNC1
HDC2, DNC2
HDC3, DNC3
AIN7
-
Digital Error Correction
Programmable Digital Signal Post-Processing (DSPP)
User-Programmable Options
16-Bit Digital Output (MCP37D31-80)
14-Bit Digital Output (MCP37D21-80)
FIGURE 4-1:
ADC Core Block Diagram.
2020 Microchip Technology Inc.
DS20006382A-page 36
MCP37D31-80 AND MCP37D21-80
4.2
Supply Voltage (DV , AV , GND)
4.3
Input Sample Rate
DD
DD
The device operates from two sets of supplies and a
common ground:
In single-channel mode, the device samples the input
at full speed. In multi-channel mode, the core ADC is
multiplexed between the selected channels. The
resulting effective sample rate per channel is shown in
Equation 4-1.
• Digital Supplies (DVDD) for the digital section:
1.8V and 1.2V
• Analog Supplies (AVDD) for the analog section:
1.8V and 1.2V
For example, with 80 Msps operation, the input is
sampled at the full 80 Msps rate if a single channel is
used, or at 10 Msps per channel if all eight channels
are used.
• Ground (GND): Common ground for both digital
and analog sections.
The supply pins require an appropriate bypass
capacitor (ceramic) to attenuate the high-frequency
noise present in most application environments. The
ground pins provide the current return path. These
ground pins must be connected to the ground plane of
the PCB through a low-impedance connection. A ferrite
bead can be used to separate analog and digital supply
lines if a common power supply is used for both analog
and digital sections.
EQUATION 4-1:
SAMPLE RATE PER
CHANNEL
Full ADC Sample Ratefs
Number of Channel Used
Sample Rate/Channel= --------------------------------------------------------------------
4.4
Analog Input Channel Selection
The voltage regulators for each supply need to have
sufficient output current capabilities to support a stable
ADC operation.
The analog input is auto-multiplexed sequentially as
defined by the channel-order selection bit setting. The
user can configure the input MUX using the following
registers:
4.2.1
POWER-UP SEQUENCE
• SEL_NCH<2:0> in Address 0x01 (Register 5-2):
Select the total number of input channels to be
used.
Figure 2-7 shows the internal power-up sequence
events of the device. The power-up sequence of the
device is initiated by a Power-on Reset (POR) circuit
which monitors the analog 1.2V supply voltage
(AVDD12):
• Addresses 0x7D – 0x7F (Registers 5-37–5-39):
Select auto-scan channel order.
The user can select up to eight input channels. If all
eight input channels are to be used, SEL_NCH<2:0> is
set to 000and the input channel sampling order is set
using Addresses 0x7D – 0x7F (Registers 5-37–5-39).
(a) Once the AVDD12 reaches the Power-on Reset
threshold (~ 0.8V), there will be a Power-on Reset
stabilization period (218 clock cycles) before triggering
the power-up calibration (TPCAL).
Regardless of how many channels are selected, all
eight channels must be programmed in Addresses
(b) All other supply voltages (AVDD18
, DVDD18,
DVDD12) must be stabilized before or within the POR
stabilization period (TPOR-S). The order that these
supply voltages are applied and stabilized will not affect
the power-up sequence.
0x7D – 0x7F
(Registers 5-37–5-39)
without
duplication. Program the addresses of the selected
channels in sequential order, followed by the unused
channels. The order of the unused channels has no
effect. The device samples the first N-Channels listed
in Addresses 0x7D – 0x7F (Registers 5-37–5-39)
sequentially, where N is the total number of channels to
be used, defined by the SEL_NCH<2:0>. Table 4-1
shows examples of input channel selection using
Addresses 0x7D – 0x7F (Registers 5-37–5-39).
DS20006382A-page 37
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 4-1:
No. of
EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
Selected
Channel
Order(2)
Address 0x7F
Address 0x7E
Address 0x7D
Channels(1) Channels
b
7
b
0
b
7
b
0
b
7
b
0
Channel Order Bit Settings
5th Ch. 4th Ch. 6th Ch. 3rd Ch. 7th Ch. 2nd Ch. 8th Ch. 1st Ch.
[0 1 2 3 4 5 6 7] [0 1 2 3 4 5 6 7]
(Default)
1
0
0
0
1
1
1
0
1
0
1
0
1
1
0
0
0
1
1
1
1
0
0
0
8
[7 6 5 4 3 2 1 0] [7 6 5 4 3 2 1 0]
[0 2 4 6 1 3 5 7] [0 2 4 6 1 3 5 7]
[1 3 5 7 0 2 4 6] [1 3 5 7 0 2 4 6]
0
0
0
1
0
0
1
1
0
1
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
1
0
0
0
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
1
0
1
1
0
1
1
0
1
0
1
0
0
1
0
0
1
0
1
Channel Order Bit Settings
Unused 4th Ch. 5th Ch. 3rd Ch. 6th Ch. 2nd Ch. 7th Ch. 1st Ch.
7
6
5
[0 1 2 3 4 5 6] [0 1 2 3 4 5 6 7]
[0 2 4 6 1 3 5] [0 2 4 6 1 3 5 7]
1
1
1
1
1
1
0
1
1
1
1
0
1
0
0
0
0
1
0
1
1
0
0
0
1
0
0
1
1
1
0
0
0
1
1
0
1
1
1
0
0
1
0
0
0
0
0
0
Channel Order Bit Settings
Unused Unused 4th Ch. 3rd Ch. 5th Ch. 2nd Ch. 6th Ch. 1st Ch.
[0 1 2 3 4 5]
[0 2 4 6 1 3]
[0 1 2 3 4 5 6 7]
[0 2 4 6 1 3 5 7]
1
1
1
1
1
1
1
1
1
0
0
1
0
1
1
1
1
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
1
1
0
1
0
0
1
1
1
0
0
0
0
0
0
Channel Order Bit Settings
Unused Unused Unused 3rd Ch. 4th Ch. 2nd Ch. 5th Ch. 1st Ch.
[0 1 2 3 4]
[0 2 4 6 1]
[0 1 2 3 4 5 6 7]
[0 2 4 6 1 3 5 7]
1
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
0
0
0
0
Channel Order Bit Settings
Unused Unused Unused Unused 3rd Ch. 2nd Ch. 4th Ch. 1st Ch.
[0 1 2 3]
[4 5 6 7]
[0 2 4 6]
[1 3 5 7]
[0 1 2 3 4 5 6 7]
[4 5 6 7 0 1 2 3]
[0 2 4 6 1 3 5 7]
[1 3 5 7 0 2 4 6]
1
0
1
1
1
1
0
0
0
0
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
0
0
0
1
0
1
0
0
0
0
1
1
1
1
0
1
0
1
1
1
1
1
1
1
1
1
0
1
0
1
0
0
0
0
0
0
0
0
0
1
4
3
2
Channel Order Bit Settings
Unused Unused Unused Unused Unused 2nd Ch. 3rd Ch. 1st Ch.
[0 1 2]
[0 2 4]
[0 1 2 3 4 5 6 7]
[0 2 4 6 1 3 5 7]
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
0
1
1
1
1
0
1
1
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
Channel Order Bit Settings
Unused Unused Unused Unused Unused Unused 2nd Ch. 1st Ch.
[0 1]
[2 3]
[4 5]
[6 7]
[0 1 2 3 4 5 6 7]
[2 3 0 1 4 5 6 7]
[4 5 0 1 2 3 6 7]
[6 7 0 1 2 3 4 5]
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
0
Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.
2020 Microchip Technology Inc.
DS20006382A-page 38
MCP37D31-80 AND MCP37D21-80
TABLE 4-1:
No. of
EXAMPLE: CHANNEL ORDER SELECTION USING ADDRESSES 0X7D – 0X7F
Selected
Channel
Order(2)
Address 0x7F
Address 0x7E
Address 0x7D
Channels(1) Channels
b
7
b
0
b
7
b
0
b
7
b
0
Channel Order Bit Settings
Unused Unused Unused Unused Unused Unused Unused 1st Ch.
[0]
[1]
[2]
[0 1 2 3 4 5 6 7]
[1 0 2 3 4 5 6 7]
[2 0 1 3 4 5 6 7]
[3 0 1 2 4 5 6 7]
[4 0 1 2 3 5 6 7]
[5 0 1 2 3 4 6 7]
[6 0 1 2 3 4 5 7]
[7 0 1 2 3 4 5 6]
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
[3]
[4]
[5]
[6]
[7]
Note 1: Defined by SEL_NCH<2:0> in Address 0x01 (Register 5-2).
2: Individual channel order should not be repeated. Unused channels are still assigned after the selected channel
address. The order of the unused channel addresses has no meaning since they are not used.
DS20006382A-page 39
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
conversion and Common-mode application can be
accomplished by using an RF transformer or balun with
a center-tap. Additionally, one or more anti-aliasing
filters may be added for optimal noise performance and
should be tuned such that the corner frequency is
appropriate for the system.
4.5
Analog Input Circuit
The analog input (AIN) of all MCP37DX1-80 devices is
differential, CMOS switched capacitor
a
sample-and-hold circuit. Figure 4-2 shows the
equivalent input structure of the device.
The input impedance of the device is mostly governed
by the input sampling capacitor (CS = 6 pF) and input
sampling frequency (fS). The performance of the
device can be affected by the input signal conditioning
network (see Figure 4-3). The analog input signal
source must have sufficiently low output impedance to
charge the sampling capacitors (CS = 6 pF) within one
clock cycle. A small external resistor (e.g., 5Ω) in series
with each input is recommended, as it helps reduce
transient currents and dampens ringing behavior. A
small differential shunt capacitor at the chip side of the
resistors may be used to provide dynamic charging
currents and may improve performance. The resistors
form a low-pass filter with the capacitor and their values
must be determined by application requirements and
input frequency.
Figure 4-3 shows an example of the differential input
circuit with transformer. Note that the input-driving
circuits are terminated by 50 near the ADC side
through a pair of 25 resistors from each input to the
Common-mode (VCM) from the device. The RF
transformer must be carefully selected to avoid
artificially high harmonic distortion. The transformer
can be damaged if a strong RF input is applied or an RF
input is applied while the MCP37DX1-80 is powered-
off. The transformer has to be selected to handle
sufficient RF input power.
Figure 4-4 shows an input configuration example when
a differential output amplifier is used.
1
V
CM
0.1 µF
The VCM pin provides a Common-mode voltage
reference (0.9V), which can be used for a center-tap
voltage of an RF transformer or balun. If the VCM pin
voltage is not used, the user may create a Common-
mode voltage at mid-supply level (AVDD18/2).
AIN
+
5
Analog
Input
MABAES0060
100 pF
100 pF
25
0.1 µF
10
6
4
1
3
3
1
6.8 pF
3.3 pF
6
4
MABAES0060
MCP37DX1-80
10
25
AV
DD18
A
-
5
IN
FIGURE 4-3:
Configuration.
Transformer Coupled Input
Sample
Hold
AIN+
50
VCM
C
= 6 pF
S
50
0.1 µF
3 pF
VCM
High-Speed
Differential
Amplifier
100
AIN+
AV
DD18
+
CM
-
6.8 pF
Analog
Input
Hold
AIN-
Sample
AIN
-
100
C
= 6 pF
MCP6D11
S
50
3 pF
FIGURE 4-4:
DC-Coupled Input
Configuration with Preamplifier: the external
signal conditioning circuit and associated
component values are for reference only.
Typically, the amplifier manufacturer provides
reference circuits and component values.
FIGURE 4-2:
Equivalent Input Circuit.
4.5.1
ANALOG INPUT DRIVING CIRCUIT
Differential Input Configuration
4.5.1.1
4.5.1.2
Single-Ended Input Configuration
The device achieves optimum performance when the
input is driven differentially, where Common-mode
noise immunity and even-order harmonic rejection are
significantly improved. If the input is single-ended, it
must be converted to a differential signal in order to
properly drive the ADC input. The differential
Figure 4-5 shows an example of a single-ended input
configuration. This single-ended input configuration is
not recommended for the best performance. SNR and
SFDR performance degrades significantly when the
2020 Microchip Technology Inc.
DS20006382A-page 40
MCP37D31-80 AND MCP37D21-80
device is operated in a single-ended configuration. The
unused negative side of the input should be
AC-coupled to ground using a capacitor.
input full-scale range. A comparator detects the
SENSE pin voltage and configures the full-scale input
range into one of the three possible modes which are
summarized in Table 4-2. Figure 4-6 shows an
example of how the SENSE pin should be driven.
V
CM
The SENSE pin can sink or source currents as high as
500 µA across all operational conditions. Therefore, it
may require a driver circuit, unless the SENSE
reference source provides sufficient output current.
0.1 µF
10 µF
Analog
Input
1 k
AIN
+
R
V
0.1 µF
CM
50
C
MCP1700
1 k
0.1 µF
R1
AIN-
R
10 µF
0.1 µF
SENSE
R2
FIGURE 4-5:
Configuration.
Singled-Ended Input
0.1 µF
(Note 1)
Note 1: This voltage buffer can be removed if the SENSE
reference is coming from a stable source (such as
MCP1700) which can provide a sufficient output
current to the SENSE pin.
4.5.2
SENSE VOLTAGE AND INPUT
FULL-SCALE RANGE
FIGURE 4-6:
SENSE Pin Voltage Setup.
The device has a bandgap-based differential internal
reference voltage. The SENSE pin voltage is used to
select the reference voltage source and configure the
TABLE 4-2:
SENSE PIN VOLTAGE AND INPUT FULL-SCALE RANGE
Selected
SENSE Pin
Voltage
Full-Scale Input Voltage
LSb Size
Reference Voltage
Condition
Range (AFS
)
(Calculated with AFS)
(VSENSE
)
(VREF)
(1)
Tied to GND
0.7V
16-bit mode: 22.7 µV
14-bit mode: 90.8 µV
Adjustable
Low-Reference
Mode(4)
1.4875 VP-P
(2)
0.4V – 0.8V
0.7V – 1.4V
1.4V
1.4875 VP-P to 2.975 VP-P
Sense Mode(5)
(3)
Tied to AVDD12
2.975 VP-P
16-bit mode: 45.4 µV
High-Reference
Mode(4)
14-bit mode: 181.6 µV
Note 1: AFS = (17/16) x 1.4 VP-P = 1.487 VP-P
.
2: FS = (17/16) x 2.8 VP-P x (VSENSE)/0.8 = 1.4875 VP-P to 2.975 VP-P
A
.
3: AFS = (17/16) x 2.8 VP-P = 2.975 VP-P
.
4: Based on internal bandgap voltage.
5: Based on VSENSE
.
DS20006382A-page 41
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
• Low-Reference Mode
4.5.2.1
SENSE Selection Vs. SNR/SFDR
Performance
This mode is enabled by setting the SENSE pin to
ground. This mode is suitable for applications which have
a smaller input full-scale range. This mode provides
improved SFDR characteristics, but SNR is reduced by
-6 dB compared to the High-Reference Mode.
The SENSE pin is used to configure the full-scale input
range of the ADC. Depending on the application
conditions, the SNR, SFDR and dynamic range
performance are affected by the SENSE pin
configuration. Table 4-3 summarizes these settings.
Figure 3-32 shows SNR/SFDR performance versus
SENSE Pin Voltage.
• SENSE Mode
This mode is enabled by driving the SENSE pin with an
external voltage source between 0.4V and 0.8V. This
mode allows the user to adjust the input full-scale
range such that SNR and dynamic range are optimized
in a given application system environment.
•
High-Reference Mode
This mode is enabled by setting the SENSE pin to
AVDD12 (1.2V). This mode provides the highest input
full-scale range (2.975 VP-P) and the highest SNR
performance. Figure 3-25 and Figure 3-27 show
SNR/SFDR versus input amplitude in High-Reference
mode.
TABLE 4-3:
SENSE
High-Reference Mode
SENSE VS. SNR/SFDR PERFORMANCE
Descriptions
High-input full-scale range (2.975 VP-P) and optimized SNR
(SENSE pin = AVDD12
)
Low-Reference Mode
(SENSE pin = ground)
Low-input full-scale range (1.4875 VP-P) and reduced SNR, but optimized SFDR
Adjustable-input full-scale range (1.4875 VP-P - 2.975 VP-P). Dynamic trade-off
Sense Mode
(SENSE pin = 0.4V to 0.8V) between High-Reference and Low-Reference modes can be used.
2020 Microchip Technology Inc.
DS20006382A-page 42
MCP37D31-80 AND MCP37D21-80
4.5.3
INTERNAL VOLTAGE REFERENCE
AND BANDGAP OUTPUT
4.6
External Clock Input
For optimum performance, the MCP37DX1-80 requires
a low-jitter differential clock input at the CLK+ and
CLK− pins. Figure 4-8 shows the equivalent clock input
circuit.
4.5.3.1
Internal Voltage Reference Output
Pins (REF0 and REF1 Pins)
The device has two internal voltage references, and
these references are available at pins REF0 and REF1.
REF0 is the internal voltage reference for the ADC
input stage, and REF1 is for all remaining stages.
MCP37DX1-80
AVDD12
AVDD12
The decoupling capacitors for each reference pin are
already embedded in the device’s TFBGA-121
package. Figure 4-7 shows the embedded circuit for
the REF1 and REF0 pins. Therefore, no additional
external circuit is required on the customer’s
application PCB.
~300 fF
CLK+
300
100 fF
Clock
Buffer
AVDD12
2 pF
4.5.3.2
Bandgap Output Voltage Pin (VBG)
12 k
300
The bandgap circuit is a part of the reference circuit and
the output is available at the VBG pin. The package
includes a 2.2 µF decoupling capacitor for the VBG pin
as shown in Figure 4-7.
CLK-
100 fF
~300 fF
MCP37DX1-80 Silicon
VBG
REF0+ REF0-
REF1+ REF1-
FIGURE 4-8:
Equivalent Clock Input
Circuit.
2.2 µF
2.2 µF
2.2 µF
The clock input amplitude range is between 300 mVP-P
and 800 mVP-P. When a single-ended clock source is
used, an RF transformer or balun can be used to
convert the clock into a differential signal for the best
ADC performance. Figure 4-9 shows an example clock
input circuit. The Common-mode voltage is internally
generated and a center-tap is not required. The
back-to-back Schottky diodes across the transformer’s
secondary current limit the clock amplitude to
approximately 0.8 VP-P differential. This limiter helps
prevent large voltage swings of the input clock while
preserving the high slew rate that is critical for low jitter.
22 nF
22 nF
220nF
220 nF
220 nF
220 nF
TFBGA-121 Embedded External Circuit
FIGURE 4-7:
Embedded Decoupling
Circuit in TFBGA-121 Package for Voltage
Reference and VBG pins. No external circuit is
required on an application PCB.
CLK+
Clock
Coilcraft
Source
WBC1-1TL
6
4
1
3
Schottky
Diodes
(HSMS-2812)
50
0.1 µF
CLK-
FIGURE 4-9:
Transformer-Coupled
Differential Clock Input Configuration.
DS20006382A-page 43
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
4.6.1
CLOCK JITTER AND SNR
PERFORMANCE
In a high-speed pipelined ADC, the SNR performance
is directly limited by thermal noise and clock jitter.
Thermal noise is independent of input clock and
dominant term at low-input frequency. On the other
hand, the clock jitter becomes a dominant term as input
frequency increases. Equation 4-2 shows the SNR
jitter component, which is expressed in terms of the
input frequency (fIN) and the total amount of clock jitter
(TJitter), where TJitter is a sum of the following two
components:
• Input clock jitter (phase noise)
• Internal aperture jitter (due to noise of the clock
input buffer).
EQUATION 4-2:
SNR VS.CLOCK JITTER
SNR
dBc = –20 log 2 f
10
T
Jitter
IN
Jitter
where the total jitter term (Tjitter) is given by:
2
2
T
=
t
+ t
Jitter
Jitter, Clock Input
Aperture, ADC
The clock jitter can be minimized by using a high-
quality clock source and jitter cleaners as well as a
band-pass filter at the external clock input, while a
faster clock slew rate improves the ADC aperture jitter.
With a fixed amount of clock jitter, the SNR degrades
as the input frequency increases. This is illustrated in
Figure 4-10. If the input frequency increases from
10 MHz to 20 MHz, the maximum achievable SNR
degrades about 6 dB. For every decade (e.g. 10 MHz
to 100 MHz), the maximum achievable SNR due to
clock jitter is reduced by 20 dB.
160
Jitter = 0.0625 ps
140
Jitter = 0.125 ps
120
100
80
60
40
20
0
Jitter = 0.25 ps
Jitter = 0.5 ps
Jitter = 1 ps
1
10
100
1000
Input Frequency (fIN, MHz)
FIGURE 4-10:
SNR vs. Clock Jitter.
2020 Microchip Technology Inc.
DS20006382A-page 44
MCP37D31-80 AND MCP37D21-80
4.7
ADC Clock Selection
This section describes the ADC clock selection and
how to use the built-in Delay-Locked Loop (DLL) and
Phase-Locked Loop (PLL) blocks.
When the device is first powered-up, the external clock
input (CLK+/-) is directly used for the ADC timing as
default. After this point, the user can enable the DLL or
PLL circuit by setting the register bits. Figure 4-11
shows the clock control blocks. Table 4-4 shows an
example of how to select the ADC clock depending on
the operating conditions.
TABLE 4-4:
ADC CLOCK SELECTION (EXAMPLE)
Features
Operating Conditions
Control Bit Settings(1)
Input Clock Duty
Cycle Correction
DCLK Output Phase
Delay Control
CLK_SOURCE = 0 (Default)(2)
• DLL output is not used
• Decimation is not used
(Default)(3)
EN_DLL = 0
EN_DLL_DCLK = 0
EN_PHDLY = 0
Not Available
Not Available
Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 0
Available
Available
• DLL output is used
• Decimation is not used
EN_DLL = 1
EN_DLL_DCLK = 1
EN_PHDLY = 1
• DLL output is not used
• Decimation is used(4)
EN_DLL = 0
EN_DLL_DCLK = X
EN_PHDLY = 1
Not Available
Available
EN_DLL = 1
EN_DLL_DCLK = 0
EN_PHDLY = 1
CLK_SOURCE = 1(5)
• Decimation is not used
• Decimation is used(4)
EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 0
Not Available
Available
EN_DLL = X
EN_DLL_DCLK = X
EN_PHDLY = 1
Note 1: See Addresses 0x52, 0x53, and 0x64 for bit settings.
2: The sampling frequency (f ) of the ADC core comes directly from the input clock buffer
S
3: Output data is synchronized with the output data clock (DCLK), which comes directly from the input clock buffer.
4: While using decimation, output clock rate and phase delay are controlled by the digital clock output control block
5: The sampling frequency (f ) is generated by the PLL circuit. The external clock input is used as the reference input
S
clock for the PLL block.
DS20006382A-page 45
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
fS
EN_DLL
RESET_DLL
EN_DLL_DCLK = 0
Clock Input (fCLK): < 250 MHz
EN_DLL = 0
EN_PHDLY
DCLK
DLL Circuit
DCLK
if CLK_SOURCE = 0
Phase Delay
Duty Cycle Correction (DCC)
EN_DUTY
Input Clock Buffer
EN_CLK
DCLK_PHDLY_DLL<2:0>
EN_DLL_DCLK
DLL Block
See Address 0x52 and 0x64<7> for details
if digital decimation is used
See Address 0x7A, 0x7B, 0x7C, and 0x81
if CLK_SOURCE = 1
Digital Output
Clock Phase Delay Control
(when decimation filter is used)
DCLK
EN_PHDLY
DCLK_PHDLY_DEC<2:0>
Digital Output
Clock Rate Control
OUT_CLKRATE<3:0>
Digital Clock Output Control Block
See Address 0x64 and 0x02
for control parameters
fREF
(5 MHz to 250 MHz)
EN_PLL
EN_PLL_BIAS
Loop Filter Control Parameters:
if digital decimation is used
See Address 0x7A, 0x7B, 0x7C, and 0x81
C : PLL_CAP1<4:0>
1
C
C : PLL_CAP2<4:0>
2
C
C
2
1
3
C : PLL_CAP3<4:0>
3
R
1
R : PLL_RES<4:0>
1
PLL_REFDIV<9:0>
EN_PLL_REFDIV
fS
(80 MHz - 250 MHz)
÷R
EN_PLL_OUT
f
Q
Current
fVCO
DCLK
Loop Filter
(3rd Order)
Phase/Freq.
Detector
Output/Div
Charge
Pump
DCLK Delay
VCO
EN_PLL_CLK
PLL_OUTDIV<3:0>
DCLK_DLY_PLL<2:0>
Loop Filter Control
PLL_CHAGPUMP<3:0>
÷N
PLL Output Control Block
See Address 0x55 and 0x6D
for control parameters
PLL_PRE<11:0>
PLL Block
See Address 0x54 - 0x5D for Control Parameters
Note:
VCO output range is 1.075 GHz – 1.325 GHz by setting PLL_REFDIV<10:0> and PLL_PRE<11:0>, with f
= 5 MHz - 250 MHz range.
REF
N
R
f
= --- f
= 1.075 – 1.325 GHz
REF
VCO
FIGURE 4-11:
Timing Clock Control Blocks.
2020 Microchip Technology Inc.
DS20006382A-page 46
MCP37D31-80 AND MCP37D21-80
4.7.1
USING DLL MODE
Using the DLL block is the best option when output
clock phase control is needed while the clock
multiplication and digital decimation are not required.
When the DLL block is enabled, the user can control
the input clock Duty Cycle Correction (DCC) and the
output clock phase delay.
See the DLL block in Figure 4-11 for details. Table 4-5
summarizes the DLL control register bits. In addition,
see Table 4-21 for the output clock phase control.
TABLE 4-5:
DLL CONTROL REGISTER BITS
Control Parameter
Register
Descriptions
CLK_SOURCE
EN_DUTY
0x53
0x52
0x52
0x52
0x52
CLK_SOURCE = 0: external clock input becomes input of the DLL block
Input clock duty cycle correction control bit(1)
EN_DLL = 1: enable DLL block
EN_DLL
EN_DLL_DCLK
EN_PHDLY<2:0>
DLL output clock enable bit
Phase delay control bits of digital output clock (DCLK) when DLL or
decimation filter is used(2)
RESET_DLL
0x52
Reset control bit for the DLL block
Note 1: Duty cycle correction is not recommended when a high-quality external clock is used.
2: If decimation is used, the output clock phase delay is controlled using DCLK_PHDLY_DEC<2:0> in
Address 0x64.
4.7.1.1
Input Clock Duty Cycle Correction
4.7.1.2
DLL Block Reset Event
The ADC performance is sensitive to the clock duty
cycle. The ADC achieves optimum performance with
50% duty cycle, and all performance characteristics are
ensured when the duty cycle is 50% with ±1%
tolerance.
The DLL must be reset if the clock frequency is
changed. The DLL reset is controlled by using the
RESET_DLL bit in Address 0x52 (Register 5-7). The
DLL has an automatic reset with the following events:
• During power-up: Stay in reset until the
RESET_DLL bit is cleared.
When CLK_SOURCE = 0, the external clock is used
as the sampling frequency (fS) of the ADC core. When
the external input clock is not high-quality (for example,
duty cycle is not 50%), the user can enable the internal
clock duty cycle correction circuit by setting the
EN_DUTY bit in Address 0x52 (Register 5-7). When
duty cycle correction is enabled (EN_DUTY=1), only
the falling edge of the clock signal is modified (rising
edge is unaffected).
• When a SOFT_RESET command is issued while
the DLL is enabled: the RESET_DLL bit is
automatically cleared after reset.
Because the duty cycle correction process adds
additional jitter noise to the clock signal, this option is
recommended only when an asymmetrical input clock
source causes significant performance degradation or
when the input clock source is not stable.
Note: The clock duty cycle correction is only
applicable when the DLL block is enabled
(EN_DLL = 1). It is not applicable for the PLL
output.
DS20006382A-page 47
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
When the PLL is locked, it tracks the input frequency
(fREF) with the ratio of dividers (N/R). The PLL operat-
4.7.2
USING PLL MODE
The PLL block is mainly used when clock multiplication
is needed. When CLK_SOURCE = 1, the sampling
frequency (fS) of the ADC core is coming from the
ing status is monitored by the PLL status indication bits:
<PLL_VCOL_STAT> and <PLL_VCOH_STAT> in
Address 0xD1 (Register 5-80).
internal PLL block.
Equation 4-3 shows the VCO output frequency (fVCO) as
a function of the two dividers and reference frequency:
The external clock input is used as the PLL reference
frequency. The range of the clock input frequency is
from 5 MHz to 250 MHz.
EQUATION 4-3:
VCO OUTPUT
FREQUENCY
4.7.2.1
PLL Output Frequency and Output
Control Parameters
N
R
fVCO
=
--- fREF = 1.075 GHz to 1.325 GHz
Where:
The internal PLL can provide a stable timing output
ranging from 50 MHz to 250 MHz. Figure 4-11 shows the
PLL block using a charge-pump-based integer N PLL
and the PLL output control block. The PLL block
includes various user control parameters for the desired
output frequency. Table 4-6 summarizes the PLL control
register bits and Table 4-7 shows an example of register
bit settings for the PLL charge pump and loop filter.
N = 1 to 4095 controlled by PLL_PRE<11:0>
R = 1 to 1023 controlled by PLL_REFDIV<9:0>
See Addresses 0x54 to 0x57 (Registers 5-9 – 5-12)
for these bits settings.
The tuning range of the VCO is 1.075 GHz to
1.325 GHz. N and R values must be chosen so the
VCO is within this range. In general, lower values of the
VCO frequency (fVCO) and higher values of the charge
pump frequency (fQ) should be chosen to optimize the
clock jitter. Once the VCO output frequency is
determined to be within this range, set the final ADC
sampling frequency (fS) with the PLL output divider
using PLL_OUTDIV<3:0>. Equation 4-4 shows how to
obtain the ADC core sampling frequency:
The PLL block consists of:
• Reference Frequency Divider (R)
• Prescaler - which is a feedback divider (N)
• Phase/Frequency Detector (PFD)
• Current Charge Pump
• Loop Filter - a 3rd order RC low-pass filter
• Voltage-Controlled Oscillator (VCO)
The external clock at the CLK+ and CLK- pins is the
input frequency to the PLL. The range of input
frequency (fREF) is from 5 MHz to 250 MHz. This input
frequency is divided by the reference frequency
divider (R) which is controlled by the 10-bit-wide
PLL_REFDIV<9:0> setting. In the feedback loop, the
VCO frequency is divided by the prescaler (N) using
PLL_PRE<11:0>.
EQUATION 4-4:
SAMPLING FREQUENCY
fVCO
fS
=
------------------------------------- = 50 MHz to 250 MHz
PLL_OUTDIV
Table 4-8 shows an example of generating fS = 80 MHz
output using the PLL control parameters.
4.7.2.2
PLL Calibration
The ADC core sampling frequency (fS) is obtained
The PLL should be recalibrated following a change in
clock input frequency or in the PLL Configuration
register bit settings (Addresses 0x54
Registers 5-9 – 5-12).
after
the
output
frequency
divider
(PLL_OUTDIV<3:0>). For stable operation, the user
needs to configure the PLL with the following limits:
-
0x57;
•
•
Input clock frequency (f
)
= 5 MHz to 250 MHz
= 4 MHz to 50 MHz
REF
The PLL can be calibrated by toggling the PLL_-
CAL_TRIG bit in Address 0x6B (Register 5-27) or by
sending a SOFT_RESET command (See Address
0x00, Register 5-1). The PLL calibration status is
observed by the PLL_CAL_STAT bit in Address 0xD1
(Register 5-81).
Charge pump input frequency
(after PLL reference divider)
VCO output frequency
•
•
= 1.075 to1.325 GHz
= 50 MHz to 250 MHz
PLL output frequency after
output divider
4.7.2.3
Monitoring of PLL Drifts
The charge pump is controlled by the PFD, and forces
sink (DOWN) or source (UP) current pulses onto the
loop filter. The charge pump bias current is controlled
by the PLL_CHAGPUMP<3:0> bits, approximately
25 µA per step. The loop filter consists of a 3rd order
passive RC filter. Table 4-7 shows the recommended
settings of the charge pump and loop filter parameters,
depending on the charge pump input frequency range
(output of the reference frequency divider).
The PLL drifts can be monitored using the status
monitoring bits in Address 0xD1 (Register 5-81).
Under normal operation, the PLL maintains a lock
across all temperature ranges. It is not necessary to
actively monitor the PLL unless extreme variations in
the supply voltage are expected or if the input
reference clock frequency has been changed.
2020 Microchip Technology Inc.
DS20006382A-page 48
MCP37D31-80 AND MCP37D21-80
TABLE 4-6:
PLL CONTROL REGISTER BITS
Control Parameter
Register
Descriptions
PLL Global Control Bits
EN_PLL
0x59
0x5F
0x5F
0x59
Master enable bit for the PLL circuit
EN_PLL_OUT
Master enable bit for the PLL output
Master enable bit for the PLL bias
EN_PLL_BIAS
EN_PLL_REFDIV
PLL Block Setting Bits
PLL_REFDIV<9:0>
PLL_PRE<11:0>
Master enable bit for the PLL reference divider
0x54-0x55 PLL reference divider (R) (See Table 4-8)
0x56-0x57 PLL prescaler (N) (See Table 4-8)
PLL_CHAGPUMP<3:0>
PLL_RES<4:0>
0x58
0x5A
0x5B
0x5D
0x5C
PLL charge pump bias current control: from 25 µA to 375 µA, 25 µA per step
PLL loop filter resistor value selection (See Table 4-7)
PLL_CAP3<4:0>
PLL loop filter capacitor 3 value selection (See Table 4-7)
PLL loop filter capacitor 2 value selection (See Table 4-7)
PLL loop filter capacitor 1 value selection (See Table 4-7)
PLL_CAP2<4:0>
PLL_CAP1<4:0>
PLL Output Control Bits
PLL_OUTDIV<3:0>
DCLK_DLY_PLL<2:0>
EN_PLL_CLK
0x55
0x6D
0x6D
PLL output divider (See Table 4-8)
Delay DCLK output up to 15 cycles of VCO clocks
EN_PLL_CLK = 1enable PLL output clock to the ADC circuits
PLL Drift Monitoring Bits
PLL_VCOL_STAT
PLL_VCOH_STAT
PLL Block Calibration Bits
PLL_CAL_TRIG
0xD1
0xD1
PLL drift status monitoring bit
PLL drift status monitoring bit
0x6B
0x00
0xD1
Forcing recalibration of the PLL
SOFT_RESET
PLL is calibrated when exiting soft reset mode
PLL auto-calibration status indication
PLL_CAL_STAT
DS20006382A-page 49
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 4-7:
RECOMMENDED PLL CHARGE PUMP AND LOOP FILTER BIT SETTINGS
fQ = fREF/PLL_REFDIV
PLL Charge Pump and Loop Filter
Parameter
fQ<5 MHz
5 MHz ≤ fQ < 25 MHz
fQ ≥ 25 MHz
PLL_CHAGPUMP<3:0>
PLL_RES<4:0>
0x04
0x1F
0x07
0x07
0x07
0x04
0x1F
0x02
0x01
0x01
0x04
0x07
0x07
0x08
0x08
PLL_CAP3<4:0>
PLL_CAP2<4:0>
PLL_CAP1<4:0>
TABLE 4-8:
EXAMPLE OF PLL CONTROL BIT SETTINGS FOR fS = 80 MHz WITH fREF = 40 MHz
PLL Control Parameter
Value
Descriptions
fREF
40 MHZ
80 MHZ
1.2 GHZ
10 MHZ
4
fREF is coming from the external clock input
ADC sampling frequency
( )
1
Target fS
( )
2
Target fVCO
Range of fVCO = 1.0375 GHz – 1.325 GHz
fQ = fREF/PLL_REFDIV (See Table 4-7)
PLL_REFDIV<9:0> = 0x004
( )
3
Target fQ
PLL Reference Divider (R)
PLL Prescaler (N)
120
PLL_PRE<11:0> = 0x078
PLL Output Divider
15
PLL_OUTDIV<3:0> = 0xF
Note 1: fS = fVCO/PLL_OUTDIV = 1.2 GHz/15 = 80 MHz
2: fVCO = (N/R) x fREF = (30) x 40 MHz = 1.2 GHz
3:
fQ should be maximized for the best noise performance.
2020 Microchip Technology Inc.
DS20006382A-page 50
MCP37D31-80 AND MCP37D21-80
4.8
Digital Signal Post-Processing
(DSPP) Options
While the device converts the analog input signals to
digital output codes, the user can enable various digital
signal post-processing (DSPP) options for special
applications. These options are individually enabled or
disabled by setting the Configuration bits. Table 4-9
summarizes the digital signal post-processing (DSPP)
options that are available for each device family.
TABLE 4-9:
DIGITAL SIGNAL POST PROCESSING (DSPP) OPTIONS
Digital Signal Post Processing Option
Available Operating Mode
Fractional Delay Recovery (FDR)
FIR Decimation Filters
Dual and octal-channel modes
• Single and dual-channel modes
• CW octal-channel mode
• DDC for I and Q data
Digital Gain and Offset correction per channel
Digital-Down Conversion (DDC)
Available for all channels
• Single and dual-channel modes
• CW octal-channel mode
CW octal-channel mode
Continuous Wave (CW) Beamforming
4.8.1
FRACTIONAL DELAY RECOVERY
FOR DUAL- AND OCTAL-CHANNEL
MODES
ADC Output for
dual- or octal-channel
FIR
The fractional delay recovery (FDR) feature is available
in dual and octal-channel modes only. When FDR is
enabled, the built-in high-order, band-limited
interpolation filter compensates for the time delay
between input samples of different channels. Due to
the finite bandwidth of the interpolation filter, the
fractional delay recovery is not guaranteed for input
frequencies near the Nyquist frequency (fS/2). For
example, in dual-channel mode, FDR can operate
correctly for input frequencies in the range from 0 to
0.45*fS (or from 0.55*fs to fS if the input is in the 2nd
Nyquist band). In octal-channel mode, FDR can
operate correctly for input frequencies in the range
from 0 to 0.38*fS. See Table 4-11 for the summary of
the input bandwidth requirement for FDR. The FDR
process takes place in the digital domain and requires
59 clock cycles of processing time. Therefore, the
output data latency is also increased by 59 clock
periods.
Decimation Filters
Fractional Delay
Recovery
Digital
Down-Conversion (DDC)
(FDR)
Digital Gain/Offset
FDR Control
Correction per Channel
CW
Beamforming
ADC output data after
sampling time delay between
channels is removed.
FIGURE 4-12:
Simplified Block Diagram for
ADC Output Data Path with Fractional Delay
Recovery Option. Note that Fractional Delay
Recovery occurs prior to other DSPP features.
Figure 4-12 shows the simplified block diagram for the
ADC output data path with FDR. The related
Configuration register bits are listed in Table 4-10.
Table 4-11 shows the input bandwidth limits of the FDR
feature for distortion less than 0.1 mdB (0.1 × 10-3 dB),
where fS is the sampling frequency per channel.
Figures 4-13 and 4-14 show the responses of the dual-
channel and octal-channel FDRs, respectively.
DS20006382A-page 51
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 4-10: CONTROL PARAMETERS FOR FRACTIONAL DELAY RECOVERY (FDR)
Channel Operation
Control Parameter Register
Descriptions
Global control for both
dual and octal-channel
modes
EN_FDR = 1
0x7A
0x81
Enable FDR features
Select 1st or 2nd Nyquist band
FDR_BAND
Dual-channel
Octal-channel
SEL_FDR = 0
0x81
0x81
Select FDR for dual-channel mode
EN_DSPP_8 = 0
Select digital signal post-processing feature for
dual-channel mode
EN_DSPP_2 = 1
0x79
Enable all digital post-processing functions for
dual-channel operation
SEL_FDR = 1
0x81
0x81
Select FDR for octal-channel mode
EN_DSPP_8 = 1
Select digital signal post-processing feature for
octal-channel operation
TABLE 4-11: INPUT BANDWIDTH
REQUIREMENT FOR FDR
In-Band Ripple
0.0005
0
Bandwidth
in percentage
Nyquist Band (2)
-0.0005
0
fS/2
fS
(1)
of fS
Interpolation Filter Frequency Response
0
Dual-Channel Mode
st Nyquist Band (FDR_BAND = 0)
-30
0 – 45%
55 – 100%
45 – 55%
1
2
nd Nyquist Band (FDR_BAND = 1)
-60
-90
Avoid
Octal-Channel Mode
0 – 38%
1st Nyquist Band (FDR_BAND = 0)
-120
0
fS/2
Frequency
fS
Note 1: fs is sampling frequency per channel.
Distortion is less than 0.1 mdB.
FIGURE 4-13:
Response of the Dual-
2: See Address 0x81 for FDR_BAND bit
Channel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
setting
In-Band Ripple
0.0005
0
-0.0005
0
fS/2
fS
2×fS
Frequency
3×fS
4×fS
0
-30
-60
-90
-120
0
fS/2
fS
2×fS
Frequency
3×fS
4×fS
FIGURE 4-14:
Response of the Octal-
Channel Fractional Delay Recovery (1st Nyquist
Band). fS is the Sampling Frequency.
2020 Microchip Technology Inc.
DS20006382A-page 52
MCP37D31-80 AND MCP37D21-80
4.8.2
DECIMATION FILTERS
TABLE 4-12: DECIMATION RATE VS. SNR
PERFORMANCE
The decimation feature is available in single and dual-
channel modes and CW octal-channel mode.
Figure 4-15 shows a simplified decimation filter block,
and Table 4-13 shows the register settings. The
decimation rate is controlled by FIR_A<8:0> and
FIR_B<7:0> register settings (Addresses 0x7A –
0x7C: Registers 5-34 - ). These registers are
thermometer encoded.
SNR (dBFS)
Decimation
16-Bit Output
Mode
18-Bit Output
Rate
Mode(1)
1x
2x
74.5
76.7
79.5
82.3
84.8
87.1
89.2
91.0
92.0
92.3
74.5
76.7
79.5
82.3
84.8
87.4
89.7
91.8
93.2
93.5
4x
In single-channel mode, FIR B is disabled and only
FIR A is used. In this mode, the maximum
programmable decimation rate is 512x using nine
cascaded decimation stages.
8x
16x
32x
64x
128x
256x
512x
In dual-channel mode or when using the Digital Down-
Conversion (DDC) in I/Q mode, both FIR A and FIR B
are used (see Figure 4-15). In this case, both channels
are set to the same decimation rate. Note that stage
1A in FIR A is unused: the user must clear FIR_A<0>
in Address 0x7A (Registers 5-34). In dual-channel
mode, the maximum programmable decimation rate is
up to 256x, which is half the single-channel decimation
rate (512x).
Note 1: DM1DM2 bit is enabled.
The overall SNR performance can be improved with
higher decimation rate. In theory, 3 dB improvement is
expected with each successive stage of decimation
(2x per stage), but the actual improvement is
approximately 2.5 dB per stage due to finite
attenuation in the FIR filters.
When using a high decimation rate option (128x or
above) in 16-bit mode, the user may consider enabling
two additional LSb output bits using the DM1DM2 bit
setting in Address 0x68 (Register 5-26). This results in
18-bit resolution. The recommended decimation rates
for adding these two additional bits are 128x or above.
This option is available for 16-bit devices only
(MCP37D31-80).
Table 4-12 summarizes the decimation rate versus
SNR performance in 16-bit and 18-bit output modes.
The results indicate that the SNR is marginally
improved with higher decimation rates. Therefore, the
user may benefit from the 18-bit output mode when a
high decimation rate is used. When a low decimation
rate is used, there is no benefit to SNR or SFDR
performance although the 18-bit output is enabled.
Table 4-13 summarizes the related control parameters
for using decimation filters.
DS20006382A-page 53
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
4.8.2.1
Output Data Rate and Clock Phase
Control When Decimation is Used
When decimation is used, it also reduces the output
clock rate and output bandwidth by a factor equal to
the decimation rate applied: the output clock rate is
therefore no longer equal to the ADC sampling clock.
The user needs to adjust the output clock and data
rates in Address 0x02 (Register 5-3) based on the
decimation applied. This allows the output data to be
synchronized to the output data clock.
Phase shifts in the output clock can be achieved using
DCLK_PHDLY_DEC<2:0>
in
Address
0x64
(Register 5-22). Only four output sampling phases are
available when a decimation rate of 2x is used, while
all eight clock phases are available for other
decimation rates. See Section 4.12.9 “Output Data
and Clock Rates” for more details.
4.8.2.2
Using Decimation with CW
Beamforming and Digital Down-
Conversion
Decimation can be used in conjunction with CW octal-
channel mode or DDC. In CW octal-channel mode
operation, the eight input channels are summed into a
single channel prior to entering the decimation filters.
When DDC is enabled, the I and Q outputs can be
decimated using the same signal path for the dual-
channel mode: I and Q data are fed into Channel A
and B, respectively.
In DDC mode, the half-band filter already includes a
2x decimation rate. Therefore, the maximum
decimation rate setting for I/Q filtering is 128x for the
FIR_A<8:1> and FIR_B<7:0>. See Section 4.8.3
“Digital Down-Conversion” for details.
Note:
Fractional Delay Recovery, Digital
Gain/Offset adjustment and DDC for I/Q
data options occur prior to the decimation
filters if they are enabled.
2020 Microchip Technology Inc.
DS20006382A-page 54
MCP37D31-80 AND MCP37D21-80
TABLE 4-13: REGISTER CONTROL PARAMETERS FOR USING DECIMATION FILTERS
Control Parameter
Register
Descriptions
Decimation Filter Settings
FIR_A<8:0>
0x7A, 0x7B
0x7C
Channel A FIR configuration for single- or dual-channel mode
Channel B FIR configuration for single- or dual-channel mode
FIR_B<7:0>
Output Data Rate and Clock Rate Settings(1)
OUT_DATARATE<3:0>
0x02
Output data rate: Equal to decimation rate
Output clock rate: Equal to decimation rate
OUT_CLKRATE<3:0>
0x02
Output Clock Phase Control Settings(2)
EN_PHDLY
0x64
0x64
Enable digital output phase delay when decimation filter is used
Digital output clock phase delay control
DCLK_PHDLY_DEC<2:0>
Digital Signal Post-Processing (DSPP) Function Block Settings
EN_DSPP_2 = 1 0x79 Enable dual-channel decimation
Note 1: The output data and clock rates must be updated when decimation rates are changed.
2: Output clock (DCLK) phase control is used when the output clock is divided by OUT_CLKRATE<3:0>
bit settings.
I
D2
Single
D4
Single
D8
Single
Single-channel operation
Single
Ch.
Input
Stage 9A
FIR
D512
Single
Stage 2A
FIR
Stage 3A
FIR
Stage 1A
FIR
2
2
2
2
2
2
(Note 1)
(Note 3)
Ch. A
Ch. B
Dual
Ch.
Input
Input
DeMUX
Stage 2B
FIR
Stage 9B
FIR
Output
MUX
Stage 3B
FIR
2
D256
Dual
(Note 2)
Dual-channel operation
Output
MUX
Output
MUX
Output
MUX
D4
Dual
D128
I/Q
D2
Dual
Ch. A
Ch. B
Input for DDC
Input
DeMUX
DDC I/Q filtering
Note 1: Stage 1A FIR is the first stage of the FIR A filter.
2: (a) Single-channel mode: Only Channel A is used and controlled by FIR_A<8:0>.
(b) Dual-channel mode or I/Q filtering in DDC mode: Both Channel A and Channel B are used: Channel A is used for
the first channel or I data, and Channel B is used for the second channel or Q data.
3: Maximum decimation rate:
(a) When I/Q filtering in DDC mode is not used: 512x for single-channel and 256x for dual-channel mode.
(b) I/Q filtering in DDC mode: 128x each for FIR_A<8:1> and FIR_B<7:0>.
FIGURE 4-15:
Simplified Block Diagram of Decimation Filters.
DS20006382A-page 55
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Example:
4.8.3
DIGITAL DOWN-CONVERSION
The Digital Down-Conversion (DDC) feature is
available in single, dual, and CW octal-channel modes.
This feature can be optionally combined with the
decimation filter and used to:
If the ADC is sampling an input at 80 Msps, but the user
is only interested in a 2.5 MHz span which is centered
at 20 MHz, the digital down-conversion may be used to
mix the sampled ADC data with 20 MHz to convert it to
DC. The resulting signal can then be decimated by 16x
such that the bandwidth of the ADC output
(corresponding to 5 MHz Nyquist bandwidth) is 2.5
MHz (80 Msps/16x decimation gives 5 Msps with 2.5
MHz Nyquist bandwidth). If fS/8 mode is selected, then
a single 10 Msps channel is output, where 2.5 MHz in
the output data corresponds to 20 MHz at the ADC
input. If I/Q mode is selected, then two 5 Msps
channels are output, where DC corresponds to 20 MHz
and the channels represent in-phase (I) and quadrature
(Q) components of the down-conversion.
• translate the input frequency spectrum to a lower
frequency band
• remove the unwanted out-of-band portion
• output the resulting signal as either I/Q data or as
a real signal centered at 25% of the output data
rate.
Figure 4-16 and Figure 4-17 show the DDC
configuration for single- and dual-channel DDC mode,
respectively. The DDC includes a 32-bit, complex
numerically controlled oscillator (NCO), a selectable
(high/low) half-band filter, optional decimation, and two
output modes (I/Q or fS/8).
4.8.3.1
Single-Channel DDC
shows the single-channel
Figure 4-16
DDC
Frequency translation is accomplished with the NCO.
The NCO frequency is programmable from 0 Hz to fS.
Phase and amplitude dither can be enabled to improve
spurious performance of the NCO.
configuration. Each of these processing sub-blocks are
individually controlled. Examples of setting registers for
selected output type are shown in Tables 4-14 and 4-15.
This DDC feature can be used in a variety of high-
speed signal-processing applications, including digital
radio, sonar, radar, cable modems, digital video, MRI
imaging, etc.
I or I
(Note 5)
DEC
Q or Q
DEC
FIR_A<8:1>
(Note 3)
I
FIR A
CH. A
ADC DATA
Decimation Filter
Half-Band Filter A
LP/HP
fS/8
NCO (
)
Q
FIR B
Decimation Filter
DER
Real
or
Real
EN_DDC_FS/8
DEC
COS
SIN
HBFILTER_A
FIR_B<7:0>
(Note 4)
EN_DDC2
EN_NCO
EN_DDC1
NCO (32-bit)
(Note 2)
(Note 1)
(Note 1)
Decimation and Output Frequency Translation
Down-Converting and Decimation
Note 1: See Address 0x80 - 0x81 (Registers 5-40 – 5-41) for the control parameters.
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A includes a single-stage decimation filter.
4: See Figure 4-15 for details.
5: Switches are closed if decimation filter is not used, and open if decimation filter is used.
FIGURE 4-16:
Simplified DDC Block Diagram for Single-Channel Mode. See Tables 4-14 and 4-15
for Using This DDC Block.
2020 Microchip Technology Inc.
DS20006382A-page 56
MCP37D31-80 AND MCP37D21-80
band filter is up-converted by fS/8 for each channel.
Otherwise, I/Q of each channel will be output
separately, similar to a four-channel input device with
the WCK output pin toggling synchronously with the I-
data of Channel A. Note that the NCO phase can be
adjusted uniquely for each of the two input channels
(see Figure 4-18). Examples of setting registers for
selected output type are shown in Tables 4-16 and 4-
17.
4.8.3.2
Dual-Channel DDC
shows the dual-channel
Figure 4-17
DDC
configuration. Each channel includes the same
processing elements as shown in the single-channel
DDC, however the I/Q outputs cannot be separately
decimated since the device only supports two
channels of decimation (four would be required for I/Q
of Channel A and I/Q of Channel B). The decimation
option can be used if the DDC output after the half-
I
A
Q
ADC
Data:
A
(Note 3)
I
A
Half-Band Filter A
LP/HP
CH. A
Q
A
Real
A
SIN
HBFILTER_A
COS
EN_NCO
NCO (32-bit)
(Note 2)
EN_DDC_FS/8
EN_DDC2
NCO (f /8)
S
SIN
COS
(Note 3)
CH. B
Q
I
B
Real
B
Half-Band Filter B
LP/HP
B
I
HBFILTER_B
B
EN_DDC1
Q
B
Down-Converting and Decimation (Note 1)
Note 1: See Address 0x80 – 0x81 for the Control Parameters.
Output Frequency Translation and Decimation (Note 1)
2: See Figure 4-18 for details of NCO control block.
3: Half-band Filter A and B include a single-stage decimation filter.
FIGURE 4-17:
Simplified DDC Block Diagram for Dual-Channel Mode. See Tables 4-16 and 4-17 for
Using this DDC Block.
DS20006382A-page 57
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Figure 4-18 shows the control signals associated with
the NCO. In octal- or dual-channel mode, the NCO
allows the output phase to be adjusted on a
per-channel basis.
4.8.3.3
Numerically Controlled Oscillator
(NCO)
The on-board Numerically Controlled Oscillator (NCO)
provides the frequency reference for the in-phase and
quadrature mixers in the digital down-converter (DDC).
Note: The NCO is only used for DDC or CW octal-
channel mode. It should be disabled when
not in use.
The NCO serves as a quadrature local oscillator,
capable of producing an NCO frequency of between 0
Hz and fS with a resolution of fS/232, where fS is the
ADC core sampling frequency.
EN_PHSDITH
EN_AMPDITH
Phase Offset Control
CH(n) NCO_PHASE<15:0>
Phase Dither
Amplitude Dither
EN_LFSR
EN_LFSR
Sine/Cosine
Signal Generator
NCO Tuning
EN_NCO
NCO Output
NCO_TUNE<31:0>
FIGURE 4-18:
NCO Block Diagram.
• NCO Frequency Control:
4.8.3.4
NCO Amplitude and Phase Dither
The EN_AMPDITH and EN_PHSDITH parameters in
Address 0x80 (Register 5-40) can be used for
amplitude and phase dithering, respectively. In
principle, these will dither the quantization error created
by the use of digital circuits in the mixer and local
oscillator, thus reducing spurs at the expense of noise.
In practice, the DDC circuitry has been designed with
sufficient noise and spurious performance for most
applications. In the worst-case scenario, the NCO has
an SFDR of greater than 116 dB when the amplitude
dither is enabled, and 112 dB when disabled. Although
the SNR (≈ 93 dB) of the DDC is not significantly
affected by the dithering option, using the NCO with
dithering options enabled is always recommended for
the best performance.
The NCO frequency is programmed from 0 Hz to fS,
using the 32-bit-wide unsigned register variable
NCO_TUNE<31:0>
in Addresses
0x82 – 0x85
(Registers 5-42 – 5-45).
The following equation is used to set the
NCO_TUNE<31:0> register:
EQUATION 4-5:
NCO FREQUENCY
ModfNCO fS
32
NCO_TUNE<31:0>= round 2 -----------------------------------
fS
Where:
f
=
=
=
sampling frequency (Hz)
S
f
desired NCO frequency (Hz)
gives the remainder of fNCO/fS
NCO
Mod (f
, f )
NCO
S
4.8.3.5
NCO for fS/8 and fS/(8xDER)
The output of the first down-conversion block (DDC1)
is a complex signal (comprising I and Q data) which can
then be optionally decimated further up to 128x to
provide both a lower output data rate and input channel
filtering. If fS/8 mode is enabled, a second mixer stage
(DDC2) will convert the I/Q signals to a real signal
centered at half of the current Nyquist frequency; i.e., if
the output data rate in I/Q mode is 10 Msps per channel
(5 MHz Nyquist), then in fS/8 mode the output data rate
would be 20 Msps (10 Msps each for I and Q), and the
signal would be re-centered around 5 MHz. In
single-channel mode, this is done at the output of the
decimation filters (if used). In dual-channel mode, this
must be done prior to the decimation.
Mod() is
a
remainder function. For example,
Mod(5,2) = 1 and Mod(1.999, 2) = 1.999.
Example 1:
If fNCO is 40 MHz and fS is 80 MHz:
Modf
f = Mod40 80= 40
S
NCO
32
Mod40 80
NCO_TUNE<31:0>= round 2 ---------------------------------
80
= 0x8000 0000
Example 2:
If fNCO is 79.99999994 MHz and fS is 80 MHz:
When decimation is enabled, the I/Q outputs are up-
converted by fS/(8xDER), where DER is the additional
decimation rate added by the FIR decimation filters.
This provides a decimated output signal centered at
fS/8 or fS/(8xDER) in the frequency domain.
Modf
f = Mod79.99999994 80= 79.99999994
S
NCO
32 Mod79.99999994 80
NCO_TUNE<31:0>= round 2 ----------------------------------------------------------------
80
= 0xFFFF FFFD
2020 Microchip Technology Inc.
DS20006382A-page 58
MCP37D31-80 AND MCP37D21-80
4.8.3.6
NCO Phase Offset Control
4.8.3.8
Half-Band Filter
The frequency translation is followed by a half-band
digital filter, which is used to reduce the sample rate by
a factor of two while rejecting aliases that fall into the
band of interest.
The user can add phase offset to the NCO frequency
using the NCO phase offset control registers
(Addresses 0x86 to 0x95, Registers 5-46 – 5-61).
CH(n)_NCO_PHASE<15:0> is the 16-bit-wide NCO
phase offset control parameter for Channel n. A
0x0000 value in the register corresponds to no offset,
and a 0xFFFF corresponds to an offset of 359.995°.
The phase offset can be controlled with 0.005° per
step. The following equation is used to program the
NCO phase offset register:
The user can select high- or low-pass half-band filter
using the HBFILTER_A and HBFILTER_B bits in
Address 0x80 (Register 5-40). These filters provide
greater than 90 dB of attenuation in the attenuation
band and less than 1 mdB (10-3 dB) of ripple in the
passband region of 20% of the input sampling rate.
For example, for an ADC sample rate of 80 MSPS,
these filters provide less than 1 mdB of ripple over a
bandwidth of 16 MHz.
EQUATION 4-6:
NCO PHASE OFFSET
Offset Value (
CH(n)_NCO_PHASE<15:0>= 216 ---------------------------------------
The filter responses shown in Figures 4-15 and 4-16
indicate a ripple of 0.5 mdB and an alias rejection of
90 dB. The output of the half-band filter is a DC-cen-
tered complex signal (I and Q). This I and Q signal is
then carried to the next down-conversion stage
(DDC2) for frequency translation (up-conversion), if
the DDC is enabled.
360
Where:
n
=
=
channel number
Offset Value ()
desired phase offset value in
degrees
A decimal number is used for the binary contents of
CH(n)_NCO_PHASE<15:0>.
Note:
The half-band filter delays the data output
by 80 clock cycles: 2 (due to decimation) x
40 cycles (due to group delay)
4.8.3.7
In-Phase and Quadrature Signals
When the first down-conversion is enabled, it produces
In-phase (I) and Quadrature (Q) components as shown
in Equation 4-7:
In-Band Ripple
0.0005
0
-0.0005
0
0.1
0.2
0.3
0.4
0.5
EQUATION 4-7:
I AND Q SIGNALS
Half-Band Filter Frequency Response
0
I = ADC COS2fNCOt +
Q = ADC SIN2fNCOt +
(a)
(b)
-30
-60
-90
where:
CH(n)_NCO_PHASE<15:0>
(c)
= 360 ----------------------------------------------------------------------
216
-120
0
= 0.005493164 CH(n)_NCO_PHASE<15:0>
where:
0.1
0.2
0.3
0.4
0.5
Fraction of Input Sample Rate
FIGURE 4-19:
of Half-Band Filter.
High-Pass (HP) Response
ADC
=
=
output of the ADC block
NCO phase offset of selected channel, which
is defined by CH(n)_NCO_PHASE<15:0> in
Addresses 0x86 - 0x95
In-Band Ripple
0.0005
0
t
=
=
k/f , with k =1, 2, 3,..., n
S
-0.0005
f
NCO frequency
NCO
0
0.1
0.2
0.3
0.4
0.5
Half-Band Filter Frequency Response
0
I and Q outputs are interleaved where I data is output
on the rising edge of the WCK. If I and Q outputs are
selected in dual-channel mode with DDC enabled, I
data of Channel 0 is output at the rising edge of WCK,
followed by Q data of Channel 0, then I and Q data of
Channel 1 in the same way.
-30
-60
-90
-120
0
0.1
0.2
0.3
0.4
0.5
Fraction of Input Sample Rate
FIGURE 4-20:
Low-Pass (LP) Response of
Half-Band Filter.
DS20006382A-page 59
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
4.8.4
EXAMPLES OF REGISTER
SETTINGS FOR USING DDC AND
DECIMATION
The following tables show examples of setting registers
for using decimation and digital down-conversion
(DDC) depending on the output type selection.
TABLE 4-14: REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS
FOR SINGLE-CHANNEL MODE – EXAMPLE
Dual-Channel
DSPP Control
FIR A Filter
FIR B Filter DDC1
DDC2
DDC
Mode
Addr.
0x02
Output
(2)
0
8
Disabled
Disabled
0x00
0x33
0
1
0x00
0x00
0x00
0,0,0
0,0,0
0,0,0
0,0,0
0
0
ADC
0x03
ADC with decimation
(÷8)
512
Disabled
0x99
1
0xFF
0x00
0,0,0
0,0,0
0
ADC with decimation
(÷512)
(5)
0
8
0
I/Q
I/Q
0x00
0x33
0
0
0
0x00
0x07
0x00
0x00
0x07
0x00
1,0,1
1,0,1
1,1,1
0,0,0
0,0,0
0,0,0
0
0
0
I/Q Data
Decimated I/Q (÷8)
(6)
f /8
0x11
Real without
S
additional decimation
8
f /8
0x44
0
0x07
0x07
1,0,1
1,0,0
0
Real with decimation
(÷16)
S
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-I/Q option actually has 16x decimation with 8x provided by the decimation filter
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
5: Each of I/Q has 1/2 of f bandwidth. The combined bandwidth is the same as the f bandwidth. Therefore the data rate
S
S
adjustment is not needed.
6: The Half-Band Filter A includes decimation of 2.
2020 Microchip Technology Inc.
DS20006382A-page 60
MCP37D31-80 AND MCP37D21-80
TABLE 4-15: OUTPUT TYPE VS. CONTROL PARAMETERS FOR SINGLE-CHANNEL DDC
(EXAMPLE)
Output Type
Control Parameter
Register
Descriptions
Complex: I and Q EN_DDC1 = 1
EN_NCO = 1
0X80
0X80
0X80
0X80
0X81
0X7B
0X7C
0X02
0X80
0X80
0X80
0X80
0X81
0X7B
0X7C
0X02
0X80
0X80
0X80
0X80
Enable DDC1 block
Enable 32-bit NCO
HBFILTER_A = 1
Enable Half-Band Filter A, includes 2x decimation
NCO(fS/8/DER) is disabled
EN_DDC_FS/8 = 0
EN_DDC2 = 0
DDC2 is disabled
FIR_A<8:1> = 0x00
FIR_B<7:0> = 0x00
OUT_CLKRATE<3:0>
FIR A decimation filter is disabled
FIR B decimation filter is disabled
Output clock rate is not affected (no need to change)
Enable DDC1 block
Decimated I and
Q:IDEC, QDEC
EN_DDC1 = 1
EN_NCO = 1
Enable 32-bit NCO
HBFILTER_A = 1
EN_DDC_FS/8 = 0
EN_DDC2 = 0
FIR_A<8:1>
Enable Half-Band Filter A, includes 2x decimation
NCO(fS/8/DER) is disabled
DDC2 is disabled
Program FIR A filter for extra decimation(1)
Program FIR B filter for extra decimation(1)
Adjust the output clock rate to the decimation rate
Enable DDC1 block
FIR_B<7:0>
OUT_CLKRATE<3:0>
EN_DDC1 = 1
EN_NCO = 1
Real: Real after
DDC(fS/8/DER)
without using
A
Enable 32-bit NCO
HBFILTER_A = 1
EN_DDC_FS/8 = 1
Enable Half-Band Filter A, includes 2x decimation
Decimation Filter
NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8(2)
EN_DDC2 = 1
0X81
0X7B
0X7C
0X02
DDC2 is enabled
FIR_A<8:1> = 0x00
FIR_B<7:0> = 0x00
Decimation filter FIR A is disabled
Decimation filter FIR B is disabled
Adjust the output clock rate to divided by 2(3)
OUT_CLKRATE<3:0>
= 0001
Decimated Real: EN_DDC1 = 1
0X80
0X80
0X80
0X80
Enable DDC1 block
Real
after Decimation
Filter and
A_DEC
EN_NCO = 1
Enable 32-bit NCO
HBFILTER_A = 1
EN_DDC_FS/8 = 1
Enable Half-Band Filter A, includes 2x decimation
NCO(fS/8/DER) is enabled. This translates the input signal
from dc to fS/8/DER(2)
DDC(fS/8/DER)
EN_DDC2 = 1
FIR_A<8:1>
0X81
0X7B
0X7C
0X02
DDC2 is enabled
Program FIR B filter for extra decimation(4)
Program FIR B filter for extra decimation(4)
FIR_B<7:0>
OUT_CLKRATE<3:0>
Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
Note 1: For I/Q decimation, the maximum decimation rate for the FIR A and FIR B filters is 128x each since the
input is already decimated by 2x in the Half-Band Filter. See Figure 4-15 for details.
2: DER is the decimation rate setting of the FIR A and FIR B filters.
3: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
4: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
DS20006382A-page 61
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
TABLE 4-16: REGISTER SETTINGS FOR DECIMATION AND DDC OPTIONS FOR DUAL-CHANNEL
MODE EXAMPLE
Dual-Channel
FIR A Filter
FIR B Filter DDC1
DDC2
DSPP
Control
Output
0
8
Disabled
Disabled
Disabled
I/Q
0x00
0x33
0x88
0
0
0
0
0
0x00
0x00
0x07
0xFF
0x00
0x00
0,0,0 0,0,0
0,0,0 0,0,0
0,0,0 0,0,0
1,0,1 0,0,0
1,1,1 0,0,0
0
0
0
1
1
ADC
0x07
0xFF
0x00
0x00
ADC with decimation (÷8)
ADC with decimation (÷256)
I/Q data
256
0
(5)
0x00
0x11
(6)
0
f /8
Real without additional
decimation
S
(7)
8
f /8
0x44
0
0x0E
0x0E
1,1,1 0,0,0
1
Real with decimation filter
(÷16)
S
Note 1: When DDC is used, the actual total decimation is 2x larger since 2x is included from the DDC Half-Band Filter.
Example: Decimation = 8x with DDC-f /2 option actually has 16x decimation with 8x provided by the decimation filter
S
and 2x from the DDC Half-Band Filter.
2: Output data and clock rate control register.
3: 0x80<5,1,0> = <EN_NCO, EN_DDC_FS/8, EN_DDC1>.
4: 0x81<6,3,2> = <EN_DDC2, EN_DSPP_8, 8CH_CW>.
5: Each of I/Q has 1/2 of f bandwidth. The combined bandwidth is the same as the f bandwidth. Therefore the data rate
S
S
adjustment is not needed.
6: The Half-Band Filter A/B includes decimation of 2.
7: 0x0E takes into account the stages 1 and 2 are bypassed. See Figure 4-15 for “dual-channel Input” for DDC.
2020 Microchip Technology Inc.
DS20006382A-page 62
MCP37D31-80 AND MCP37D21-80
TABLE 4-17: OUTPUT TYPE VS. CONTROL PARAMETERS FOR DUAL-CHANNEL DDC EXAMPLE
Output Type
Control Parameter Register
Descriptions
Complex: I and Q
EN_DSPP_2 = 1
0X79
Enable all digital post-processing functions for dual-channel
operations
EN_DDC1 = 1
0X80
0X80
0X80
0X80
0X80
0X81
Enable DDC1 block
EN_NCO = 1
Enable 32-bit NCO
HBFILTER_A = 1
HBFILTER_B = 1
EN_DDC_FS/8 = 0
EN_DDC2 = 0
Enable Half-Band Filter A, includes 2x decimation
Enable Half-Band Filter B, includes 2x decimation
NCO(fS/8/DER) is disabled
DDC2 is disabled
FIR_A<8:1> = 0x00
FIR_B<7:0> = 0x00
OUT_CLKRATE<3:0>
EN_DSPP_2 = 1
0X7B FIR A decimation filter is disabled
0X7C
0X02
0X79
FIR B decimation filter is disabled
Output clock rate is not affected (no need to change)
Real: RealA for
Channel A
Enable all digital post-processing functions for dual-channel
operations
and RealB for
Channel B after
NCO(fS/8/DER)
Without Using
Decimation Filter
EN_DDC1 = 1
0X80
0X80
0X80
0X80
0X80
Enable DDC1 block
EN_NCO = 1
Enable 32-bit NCO
HBFILTER_A = 1
HBFILTER_B = 1
EN_DDC_FS/8 = 1
Enable Half-Band Filter A, includes 2x decimation
Enable Half-Band Filter B, includes 2x decimation
NCO(fS/8/DER) is enabled. This translates the input signal
from DC to fS/8(1)
EN_DDC2 = 1
0X81
DDC2 is enabled
FIR_A<8:1> = 0x00
FIR_B<7:0> = 0x00
0X7B Decimation filter FIR A is disabled
0X7C
0X02
Decimation filter FIR B is disabled
Adjust the output clock rate to divided by 2(2)
OUT_CLKRATE<3:0>
= 0001
Decimated Real:
RealA_DEC for
EN_DSPP_2 = 1
0X79
Enable all digital signal post-processing functions for dual-
channel operation
Channel A and
RealB_DEC for
Channel B after
NCO(fS/8/DER)and
Decimation Filter
EN_DDC1 = 1
0X80
0X80
0X80
0X80
0X80
Enable DDC1 block
EN_NCO = 1
Enable 32-bit NCO
HBFILTER_A = 1
HBFILTER_B = 1
EN_DDC_FS/8 = 1
Enable Half-Band Filter A, includes 2x decimation
Enable Half-Band Filter B, includes 2x decimation
NCO(fS/8/DER) is enabled. This translates the input signal
from DC to fS/8/DER(1)
EN_DDC2 = 1
FIR_A<8:1>
0X81
DDC2 is enabled
0X7B Program FIR A filter for extra decimation(3)
FIR_B<7:0>
0X7C
0X02
Program FIR B filter for extra decimation(3)
OUT_CLKRATE<3:0>
Adjust the output clock rate to the total decimation rate
including the 2x decimation by the Half-Band Filter A
Note 1: DER is the decimation rate setting of the FIR A and FIR B filters.
2: Divided by 2 is due to the 2x decimation included in the Half-Band Filter A.
3: When this filter is used, the up-conversion frequency is reduced by the extra decimation rates (DER).
DS20006382A-page 63
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
4.9.2
DIGITAL GAIN SETTINGS
4.9
Digital Offset and Digital Gain
Settings
CH(N)_DIG_GAIN<7:0> in Addresses 0x96 – 0x9D
(Registers 5-62 – 5-69) is used to adjust the digital gain
per channel.
Figure 4-21 shows a simplified block diagram of the
digital offset and gain settings. Offset is applied prior to
the gain. Offset and gain adjustments occur prior to
DDC, Decimation or FDR when these features are
used.
Note 1: Digital Offset Setting: Register mapping
(0x9E – 0xA7) to the corresponding
channel is not sequential to the channel
order defined by CH_ORDER<23:0>,
except for the octal-channel mode. See
Table 4-18 for details.
4.9.1
DIGITAL OFFSET SETTINGS
The offset can be corrected using a 16-bit-wide global
offset correction register (0x66) for all channels, offset
correction registers for individual channels (0x9E-
0xA7) or by combining both global and individual offset
correction registers. The offset control for individual
channels can be used with DIG_OFFSET_WEIGHT
<1:0> in 0xA7. The corresponding registers for each
correction are shown in Figure 4-21.
2: Gain and NCO Phase Offset: Register
mapping to the corresponding channel is
sequential to the channel order defined
by CH_ORDER<23:0>.
Note that, except for the octal-channel mode, the offset
setting registers for individual channels, 0x9E-0xA7
(Registers 5-70 – 5-78),
do
not
sequentially
correspond to the channel order defined by
CH_ORDER<23:0>. Table 4-18 shows the details of
the offset registers that correspond to the actual
channels, depending on the number of channels used.
Corrected
ADC Output
ADC
Output
Global Digital Offset Control
for all channels
Digital Offset Control
for individual channel
Digital Gain Control
for individual channel
CH(n)_DIG_GAIN<7:0>
(See Addresses 0x96 – 0x9D)
DIG_OFFSET_GLOBAL<15:0>
(See Address 0x66)
CH(n)_DIG_OFFSET<7:0>
(See Addresses 0x9E – 0xA5)
DIG_OFFSET_WEIGHT<1:0>
(See Address 0xA7)
FIGURE 4-21:
Simplified Block Diagram for Digital Offset and Gain Settings.
TABLE 4-18: REGISTER ASSIGNMENT FOR OFFSET SETTING
Register Address for Offset Setting
st
nd
rd
th
th
th
th
th
1
Channel
2
Channel
3
Channel
4
Channel
5
Channel
6
Channel
7
Channel
8
Channel
1
2
3
4
5
6
7
8
0x9F
0xA0
0xA1
0xA2
0xA3
0xA4
0xA5
0x9E
─
─
─
─
─
─
─
─
─
─
─
0x9F
0x9F
0x9F
0x9F
0x9F
0x9F
0x9F
─
─
0xA0
0xA0
0xA0
0xA0
0xA0
0xA0
─
─
─
─
─
0xA1
0xA1
0xA1
0xA1
0xA1
─
─
─
─
0xA2
0xA2
0xA2
0xA2
─
─
─
0xA3
0xA3
0xA3
─
─
0xA4
0xA4
─
0xA5
2020 Microchip Technology Inc.
DS20006382A-page 64
MCP37D31-80 AND MCP37D21-80
Along with beamforming, many modern medical
4.10 Continuous Wave (CW)
Beamforming and Ultrasound
Doppler Signal Processing Using
CW Octal-Channel Mode
ultrasound devices support Doppler imaging, which
processes phase information in addition to the classical
magnitude detection (for brightness imaging).
Ultrasound Doppler signal processing is used to
determine movement in the body as represented by
blood flow, which can help diagnose the functioning of
a heart valve or blood vessel, etc. In a traditional
ultrasound system, all of these functions are typically
accomplished with discrete components. Figure 4-23
shows an example of an ultrasound system
implementation using various specialized components.
In modern ultrasound medical applications, large
numbers of transducers are often used. The signals
from these sensors are then coherently combined for
higher transducer gain and directivity. The signals from
each sensor arrive at the detection device with a
different time delay. Also, in multi-channel scanning
operations using the MUX, there is a time delay
between acquiring input signals (see Section 4.8.1
“Fractional Delay Recovery for Dual- and Octal-
Channel Modes”). These time delays may need to be
corrected before all input signals are combined for the
signal processing.
The device has a built-in feature that can perform some
of the functions that are done traditionally using extra
components. Continuous wave (CW) digital
beamforming and Doppler signal processing features
are available, but these are offered in octal-channel
operation only.
Digital beamforming is a digital signal processing
technique that requires summing all input signals from
different channels after correcting for time delay. The
time-delay correction involves the phase alignment of
the detected signals with respect to a reference.
Figure 4-22 shows a simplified block diagram for the
ultrasound CW beamforming with DDC I/Q decimation.
Note that the sub-blocks shown after the MUX are
commonly used for all input channels.
Beamformer Central
Control Processor
HV
Amp
Isolation
DAC
LNA-VGA-ADC Array (up to 256 Channels)
AAF
HV MUX and
T/R Switches
T/R
Switcher
ADC
LNA
VGA
Digital RX Beamformer
Clocks
Transducer
Array
Amp
Amp
ADC
ADC
Image and
Motion
Processing
(B Mode)
Color
CW
Doppler
I/Q
Processing
Doppler
Video
Compression
Processing
(F Mode)
Processing
Video DAC/
Video Encoder
Amp/
Filter
Audio
DAC
Amp
FIGURE 4-22:
Example of Ultrasound System Building Block.
DS20006382A-page 65
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
4.10.1
BEAMFORMING
4.10.2
ULTRASOUND DOPPLER SIGNAL
PROCESSING
Beamforming is achieved by scanning all inputs while
correcting the phase of each channel with respect to a
reference. This can be done using:
Doppler shift measurement requires summing the input
signals from multiple transducer channels and mixing
them with a phase-controlled local oscillator frequency.
The resulting low-frequency output is then centered
near DC and can measure a Doppler shift produced by
moving objects, such as blood flow and changes in
blood pressure in arteries, etc. In traditional Doppler
measurement, many discrete analog components are
typically used along with a high-resolution ADC.
• Fractional Delay Recovery (FDR)
• Phase offset settings of each individual channel
• Gain setting per channel
While the CW input channel is multiplexed sequentially,
the phase offset can be added to the NCO output (each
channel individually). CH(n)_NCO_PHASE<15:0>, in
Addresses 0x86 to 0x95 (Registers 5-46 – 5-61),
corrects the time delay of the incoming signals with
respect to the reference.
This device has unique built-in features that are
suitable for ultrasound Doppler shift measurements. By
utilizing these features, system engineers can reduce
many discrete components which are otherwise
necessary for an ultrasound Doppler measurement
system.
The phase-compensated input signal is then down-
converted by a wide dynamic range I/Q demodulator.
The digital beamforming of the inputs is then obtained
by summing I and Q data from individual channels. The
combined I and Q data are fed to the half-band filter.
Equation 4-8 shows the I and Q data of an individual
channel with phase correction (phase offset), and the
resulting digital beamforming signal.
The following built-in digital signal post-processing
(DSPP) features can be effectively used for the
ultrasound Doppler signal processing applications:
• Fractional Delay Recovery (FDR): Correct the
time delay of signal sampled between channels.
See details in Section 4.8.1 “Fractional Delay
Recovery for Dual- and Octal-Channel
Modes”.
The processing blocks after the digital beamforming
are the same as the sub-blocks used in single-channel
operation described in Section 4.8.3.1 “Single-
Channel DDC”, except only limited decimation rates of
the FIR A and FIR B filters are used due to the
processing time requirement for summing the input
signals from all channels.
• Digital Gain and Offset adjustment for each
channel: See details in Section 4.9 “Digital
Offset and Digital Gain Settings”.
• Down-Conversion for each channel with a
unique phase of the same NCO frequency prior to
summing the eight channels as shown in
Figure 4-23.
EQUATION 4-8:
BEAMFORMING SIGNALS
ICHn = ADC COS2fNCOt + n
• After down-conversion by the DDC, the resulting
signal can then be decimated to achieve very high
SNR in a narrow bandwidth.
QCHn = ADC SIN2fNCOt + n
N
I =
I
CHn
n = 0
N
Q =
Q
CHn
n = 0
CH(n)_NCO_PHASE<15:0>
n = 360 ----------------------------------------------------------------------
216
= 0.005493164 CH(n)_NCO_PHASE<15:0>
Where:
(n) = NCO phase offset of channel n
ADC = the output of the ADC block
The NCO phase offset can be controlled by
0.005493164° per step. See Section 4.8.3.6 “NCO
Phase Offset Control” for details.
2020 Microchip Technology Inc.
DS20006382A-page 66
MCP37D31-80 AND MCP37D21-80
I
I or IDEC
Q or QDEC
(67)
MUX
FIR_A<8:1>
HBFILTER_A
ICH(n)
ADC
Data:
FIR A
Decimation Filter
fS/8
Half-Band Filter A
LP/HP
CH. 0
CH. 1
CH. 2
NCO (
)
FIR B
Decimation Filter
DER
Real
or
EN_DDC_FS/8
QCH(n)
COS
SIN
RealDEC
FIR_B<7:0>
EN_DDC2
EN_AMPDITH
EN_LFSR
NCO Amplitude Dither
Decimation and Output Frequency Translation
Sine/Cosine
Signal Generator
EN_PHSDITH
EN_LFSR
NCO Phase Dither
CH. 7
NCO Phase Offset Control
EN_NCO
CH(n) NCO_PHASE<15:0>
NCO (32-bit)
NCO_TUNE<31:0>
EN_DDC1
Channel Multiplexing/Down-Converting/Digital Beamforming/Decimation (2x)(2)
Note 1: Switches are closed if a decimation filter is not used, and open if a decimation filter is used.
2: Digital Gain and Offset adjustments are applied prior to the Digital Down-Converter and
are not shown here.
FIGURE 4-23:
Simplified Block Diagram of CW Beamforming and I/Q Signal Processing.
DS20006382A-page 67
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Table 4-19 shows the relationship between the analog
4.11 Output Data format
input voltage, the digital data output bits and the
overrange bit. By default, the output data format is
two’s complement.
The device can output the ADC data in offset binary or
two’s complement. The data format is selected by the
DATA_FORMAT bit in Address 0x62 (Register 5-20).
TABLE 4-19: ADC OUTPUT CODE VS. INPUT VOLTAGE (16-BIT MODE)
Input Range
IN > AFS
Offset Binary(1)
Two’s Complement(1)
Overrange (OVR)
A
1111-1111-1111-1111
1111-1111-1111-1111
1111-1111-1111-1110
1111-1111-1111-1100
0111-1111-1111-1111
0111-1111-1111-1111
0111-1111-1111-1110
0111-1111-1111-1100
1
0
0
0
AIN = AFS
A
IN = AFS – 1 LSb
AIN = AFS – 2 LSb
•
•
AIN = AFS/2
AIN = 0
1100-0000-0000-0000
1000-0000-0000-0000
0011-1111-1111-1111
0100-0000-0000-0000
0000-0000-0000-0000
1011-1111-1111-1111
0
0
0
AIN = -AFS/2
•
•
AIN = -AFS + 2 LSb
AIN = -AFS + 1 LSb
AIN = -AFS
0000-0000-0000-0010
0000-0000-0000-0001
0000-0000-0000-0000
0000-0000-0000-0000
1000-0000-0000-0010
1000-0000-0000-0001
1000-0000-0000-0000
1000-0000-0000-0000
0
0
0
1
AIN < -AFS
Note 1: MSb is sign bit
4.12.2
DOUBLE DATA RATE LVDS MODE
4.12
Digital Output
In double-data-rate LVDS mode, the output is a
parallel data stream which changes on each edge of
the output clock. See Figure 2-2 for details.
The device can operate in one of the following three
digital output modes:
• Full-Rate CMOS
• Double-Data-Rate (DDR) LVDS
• Serialized DDR LVDS: Available in octal-channel
with 16-bit mode only)
• Even-bit first option: Available for all resolution
options including 18-bit option. See Figure 2-2 for
details.
• MSb-first option: Available for the 16-bit option
only. See Figure 2-3 for details.
The outputs are powered by DVDD18 and GND. The
digital
output
mode
is
selected
by
the
In multi-channel configuration, the data is output
sequentially with the WCK that is synchronized to the
first sampled channel.
OUTPUT_MODE<1:0> bits in Address 0x62
(Register 5-20). Figures 2-1 – 2-6 show the timing
diagrams of the digital output.
The device outputs the following LVDS output pairs:
4.12.1
FULL RATE CMOS MODE
• Output Data:
In full-rate CMOS mode, the data outputs (Q15 to Q0,
DM1 and DM2), overrange indicator (OVR), word
clock (WCK) and the data output clock (DCLK+,
DCLK–) have CMOS output levels. The digital output
should drive minimal capacitive loads. If the load
capacitance is larger than 10 pF, a digital buffer should
be used.
- 16-/18-bit mode: Q7+/Q7- through Q0+/Q0-
- DM+/DM- (18-bit mode only)
- 14-bit mode: Q6+/Q6- through Q0+/Q0-
• OVR/WCK
• DCLK+/DCLK-
A 100Ω differential termination resistor is required for
each LVDS output pin pair. See <LVDS_LOAD> bit
option in Register 0x63 for using internal terminator.
The termination resistor should be located as close as
possible to the LVDS receiver. By default, the outputs
are standard LVDS levels: 3.5 mA output current with
a 1.15V output Common-mode voltage on a 100 dif-
ferential load. See Address 0x63 (Register 5-21) for
more details of the LVDS mode control.
2020 Microchip Technology Inc.
DS20006382A-page 68
MCP37D31-80 AND MCP37D21-80
multiplexed with the OVR bit. See Address 0x07
(Register 5-5) and Address 0x68 (Register 5-26) for
OVR and WCK control options.
Note:
Output Data Rate in LVDS Mode: In
octal-channel mode, the input sample rate
per channel is fS/8. Therefore, the output
data rate required to shift out all 16 bits in
DDR is still equivalent to fS. For example,
if fS = 80 Msps, each channel’s sample
rate is fS/8 = 10 Msps, and the output
clock rate (DCLK) for 16-bit DDR output is
80 MHz.
4.12.6
LVDS OUTPUT POLARITY
CONTROL
In LVDS mode, the output polarity can be controlled
independently for each LVDS pair. Table 4-20
summarizes the LVDS output polarity control register bits.
TABLE 4-20: LVDS OUTPUT POLARITY
CONTROL
4.12.3
SERIALIZED LVDS MODE
Control
Parameter
This output mode is only available for octal-channel
operation with 16-bit data output, and uses eight output
lanes: a single LVDS pair for each channel output as
shown in Figure 2-6.
Register
Descriptions
POL_LVDS<7:0>
0x65
Control polarity of LVDS
data pairs
POL_WCK_OVR
POL_DM1DM2
0x68
0x68
Control polarity of WCK
and OVR bit pair
Each channel’s data is serialized by the data serializer,
and the outputs are available through eight LVDS
output lanes. Each differential LVDS output pair holds
a single input channel's data, and clocks out data with
double data rate (DDR), which is synchronized with
WCK/OVR bit:
Control polarity of DM+
and DM- pair
4.12.7
PROGRAMMABLE LVDS OUTPUT
• Q7+/Q7- pair: 1st channel selected
In LVDS mode, the default output driver current is
3.5 mA. This current can be adjusted by using the
LVDS_IMODE<2:0> bit setting in Address 0x63
(Register 5-20). Available output drive currents are
1.8 mA, 3.5 mA, 5.4 mA and 7.2 mA.
• Q6+/Q6- pair: 2nd channel selected
•
•
• Q0+/Q0- pair: last channel selected
4.12.8
OPTIONAL LVDS DRIVER
INTERNAL TERMINATION
4.12.4
OVERRANGE BIT (OVR)
The input overrange status bit is asserted (logic high)
when the analog input has exceeded the full-scale
range of the ADC in either the positive or negative
direction. In LVDS DDR Output mode, the OVR bit is
multiplexed with the word clock (WCK) output bit such
that OVR is output on the falling edge of the data output
clock and WCK on the rising edge.
In most cases, using an external 100Ω termination
resistor will give excellent LVDS signal integrity. In
addition, an optional internal 100Ω termination resistor
can be enabled by setting the LVDS_LOAD bit in
Address 0x63 (Register 5-21). The internal termination
helps absorb any reflections caused by imperfect
impedance termination at the receiver.
The OVR bit has the same pipeline latency as the
ADC data bits. In multi-channel mode, the OVR is out-
put independently for each input channel and is syn-
chronized to the data. In serialized LVDS mode (for
16-bit octal channel), the MSb is asserted coincident
with the WCK rising edge. OVR will be asserted if any
of the channels are overranged, but it does not specify
which channel is overranged. See Address 0x68
(Register 5-26) for OVR and WCK control options.
4.12.9
OUTPUT DATA AND CLOCK RATES
The user can reduce output data and output clock rates
using Address 0x02 (Register 5-3). When decimation
or digital down-conversion (DDC) is used, the output
data rate has to be reduced to synchronize with the
reduced output clock rate.
4.12.10 PHASE SHIFTING OF OUTPUT
CLOCK (DCLK)
If DSPP options are enabled, OVR pipeline latency will
be unaffected; however, the data will incur additional
delay. This has the effect of allowing the OVR indicator
to precede the affected data.
In full-rate CMOS mode, the data output bit transition
occurs at the rising edge of DCLK+, so the falling edge
of DCLK+ can be used to latch the output data.
In double-data-rate LVDS mode, the data transition
occurs at both the rising and falling edges of DCLK+.
For adequate setup and hold time when latching the
data into the external host device, the user can shift the
phase of the digital clock output (DCLK+/DCLK-)
relative to the data output bits.
4.12.5
WORD CLOCK (WCK)
The word clock output bit indicates the start of a new
data set. In single-channel mode, this bit is disabled
except for I/Q output mode. In DDR output with multi-
channel mode, it is always asserted coincidentally with
the data from the first sampled channel, and
DS20006382A-page 69
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
The output phase shift (delay) is controlled by each
unique register depending on which timing source is
used or if decimation is used. Table 4-21 shows the
output clock phase control registers for each
Configuration mode: (a) when DLL is used, (b) when
decimation is used, and (c) when PLL is used.
Figure 4-24 shows an example of the output clock
phase delay control using the DCLK_PHD-
LY_DLL<2:0> when DLL is used.
TABLE 4-21: OUTPUT CLOCK (DCLK) PHASE CONTROL PARAMETERS
Control Parameter
Register
Operating Condition(1)
When DLL is used:
EN_PHDLY
0x64
0x52
EN_PHDLY = 1: Enable output clock phase delay control
DCLK phase delay control when DLL is used. Decimation is not used.
When decimation is used:
DCLK_PHDLY_DLL<2:0>
EN_PHDLY
0x64
EN_PHDLY = 1: Enable output clock phase delay control
DCLK_PHDLY_DEC<2:0>
DCLK phase delay control when decimation filter is used. The phase delay
is controlled in digital clock output control block.
When PLL is used:
DCLK_DLY_PLL<2:0>
0x6D
DCLK delay control when PLL is used.
Note 1: See Figure 4-11 for details.
LVDS Data Output:
Phase Shift:
DCLK_PHDLY_DLL<2:0>
0° (Default)(1)
=
0
0
0
0
0
0
0
1
1
1
0
1
45° + Default
90° + Default
135° + Default
Output Clock
(DCLK+)
180° + Default
1
1
1
1
0
0
1
1
0
1
0
1
225° + Default
270° + Default
315° + Default
Note 1: Default value may not be 0° in all operations.
Example of Phase Shifting of Digital Output Clock (DCLK+) When DLL is Used.
FIGURE 4-24:
2020 Microchip Technology Inc.
DS20006382A-page 70
MCP37D31-80 AND MCP37D21-80
To decode the randomized data, the reverse operation
4.12.11 DIGITAL OUTPUT RANDOMIZER
is applied: an exclusive-OR operation is applied
between the LSb (D0) and all other bits. The DCLK,
OVR, WCK, DM1, DM2 and LSb (D0) outputs are not
affected. Figure 4-25 shows the block diagram of the
data randomizer and decoder logic. The output ran-
domizer is enabled by setting the EN_OUT_RANDOM
bit in Address 0x07 (Register 5-5).
Depending on PCB layout considerations and power
supply coupling, SFDR may be improved by
decorrelating the ADC input from the ADC digital output
data. The device includes an output data randomizer
option. When this option is enabled, the digital output is
randomized by applying an exclusive-OR logic
operation between the LSb (D0) and all other data
output bits.
MCP37D31/21-80
Data Acquisition Device
DCLK
OVR
WCK
Q0
DCLK
OVR
WCK
DCLK
OVR
WCK
Q15
Q15
Q15
Q14
Q14 Q0
Q14
Q2 Q0
Q2
Q2
Q1
Q1
Q0
Q1
EN_OUT_RANDOM
Enable
Q0
Q0
Q0
(b) Data Decoder
(a) Data Randomizer
FIGURE 4-25:
Logic Diagram for Digital Output Randomizer and Decoder (16-Bit mode).
4.12.12 OUTPUT DISABLE
The digital output can be disabled by setting
OUTPUT_MODE<1:0>
=
00 in Address 0x62
(Register 5-20). All digital outputs are disabled,
including OVR, WCK, DCLK, etc.
4.12.13 OUTPUT TEST PATTERNS
To facilitate testing of the I/O interface, the device can
produce various predefined or user-defined patterns on
the digital outputs. See TEST_PATTERNS<2:0> in
Address 0x62 (Register 5-20) for the predefined test
patterns. For the user-defined patterns, Addresses
0x74 – 0x77 (Registers 5-29 – 5-32) can be pro-
grammed using the SPI interface. When an output test
mode is enabled, the ADC’s analog section can still be
operational, but does not drive the digital outputs. The
outputs are driven only with the selected test pattern.
DS20006382A-page 71
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
4.12.13.1 Pseudo-random Number (PN)
Sequence Output
4.13 System Calibration
The built-in system calibration algorithm includes:
• Harmonic Distortion Correction (HDC)
• DAC Noise Cancellation (DNC)
When TEST_PATTERNS<2:0> = 111, the device out-
puts a pseudo-random number (PN) sequence which is
defined by the polynomial of degree 16, as shown in
Equation 4-9. Figure 4-26 shows the block diagram of
a 16-bit Linear Feedback Shift Register (LFSR) for the
PN sequence.
• Dynamic Element Matching (DEM)
HDC and DNC correct the nonlinearity in the residue
amplifier and DAC, respectively. The system
calibration is performed by:
• Power-up calibration, which takes place during
the Power-on Reset sequence (requires 227 clock
cycles)
EQUATION 4-9:
POLYNOMIAL FOR PN
Px= 1 + x4 + x13 + x15 + x16
• Background calibration, which takes place during
normal operation (per 230 clock cycles).
• 16-Bit Mode:
The output PN[15:0] is directly applied to the output pins
Qn[15:0]. In addition to the output at the Qn[15:0] pins, the
two MSbs, PN[15] and PN[14], are copied to OVR and
WCK pins, respectively. The two LSbs, PN[1] and PN[0],
are also copied to DM1 and DM2 pins, respectively.
Background calibration time is invisible to the user,
and primarily affects the ADC's ability to track
variations in ambient temperature.
The calibration status is monitored by the CAL pin or
the ADC_CAL_STAT bit in Address 0xC0 (Register 5-
79). See Address 0x07 (Register 5-5) and 0x1E
(Register 5-6) for time delay control of the auto-
calibration. Table 4-22 shows the calibration time for
various ADC core sample rates.
• 14-Bit Mode:
The output PN[15:2] is directly applied to the output
pins Qn[13:0]. In addition to the output at the Qn[13:0]
pins, the two MSbs, PN[15] and PN[14], are copied to
OVR and WCK pins, respectively.
TABLE 4-22: CALIBRATION TIME VS. ADC
CORE SAMPLE RATE
In CMOS output mode, the pattern is always applied to
all CMOS I/O pins, regardless whether or not they are
enabled. In LVDS output mode, the pattern is only
applied to the LVDS pairs that are enabled.
f
(Msps)
90
80
70
60
50
S
Power-Up
Calibration Time (sec)
1.5
1.7
1.9
2.2
2.7
1
Refresh Time (sec) of
Background Calibration
11.9 13.4 15.3 17.9 21.5
2
PN[3]
PN[12]
PN[14]
PN[15]
Note 1: It takes 227 clock cycles.
Z-4
Z-9
Z-2
Z-1
2: It takes place every 230 clock cycles by itself during
normal operation.
4.13.1
RESET COMMAND
XOR
Although the background calibration will track changes
in temperature or supply voltage, changes in clock
frequency or register configuration should be followed
FIGURE 4-26:
for Pseudo-Random Number (PN) Sequence for
Block Diagram of 16-Bit LFSR
by
a
recalibration of the ADC. This can be
accomplished via either the Hard or Soft Reset
command. The recalibration time is the same as the
power-up calibration time (227 clock cycles). Resetting
the device is highly recommended when exiting from
Shutdown or Standby mode after an extended amount
of time. During the reset, the device has the following
state:
Output Test Pattern.
• No ADC output
• No change in power-on condition of internal
reference
• Most of the internal clocks are not distributed
• Contents of internal user registers:
- Not affected by Soft Reset
- Reset to default values by Hardware Reset
• Current consumption of the digital section is
negligible, but no change in the analog section.
2020 Microchip Technology Inc.
DS20006382A-page 72
MCP37D31-80 AND MCP37D21-80
This will perform a fast recalibration of the ADC. The
contents of the internal registers are not affected by the
Soft Reset.
4.13.1.1
Hardware Reset
A hard reset is triggered by toggling the RESET pin. On
the rising edge, all internal calibration registers and
user registers are initialized to their default states and
recalibration of the ADC begins. The recalibration time
is the same as the power-up calibration time. See
Figure 2-8 for the timing details of the hardware
RESET pin.
In Standby mode, most of the internal circuitry is
disabled except for the reference, clock and SPI
interface. If the device has been in standby for an
extended period of time, the current calibration value
may not be accurate. Therefore, when exiting from
Standby mode, executing the device Soft Reset at the
same time is highly recommended.
4.13.1.2
Soft Reset
The user can issue a Soft Reset command for a fast
recalibration of the ADC by setting the SOFT_RESET
bit to ‘0’ in Address 0x00 (Register 5-1). During Soft
Reset, all internal calibration registers are initialized to
their initial default states. User registers are unaffected.
When exiting the Soft Reset (changing from ‘0’ to ‘1’),
an automatic device calibration takes place.
4.15 AutoSync Mode: Synchronizing
Multiple ADCs at the same Clock
using Master and Slave
Configuration
AutoSync allows multiple devices to sample analog
inputs synchronously at the same clock edge. Output
data is also presented synchronously if they are using
the same digital post-processing options. Figure 4-27
shows the system configuration using the AutoSync
feature. Three examples with timing diagram are
shown in Figure 2-9 – Figure 2-11.
4.14 Power Dissipation and Power
Savings
The power dissipation of the ADC core is proportional
to the sample rate (fS). The digital power dissipation of
the CMOS outputs are determined primarily by the
strength of the digital drivers and the load condition on
each output pin. The maximum digital load current
(ILOAD) can be calculated as:
Once the devices are synchronized, each device
performs internal calibration (TPCAL) before sending out
valid data output. Any ADC data output before the
calibration is complete should be ignored.
Note that the calibration time varies slightly from device
to device, and the internal calibration status can be
monitored using the CAL pin or ADC_CAL_STAT bit in
the Register Address 0xC0.
EQUATION 4-10: CMOS OUTPUT LOAD
CURRENT
ILOAD = DVDD1.8 fDCLK N CLOAD
The valid synchronized output is available when all
devices complete their own internal calibration. For
this reason, the user has two options for the
synchronized output: (a) monitor the calibration status
of individual devices and wait until all devices
complete calibrations or (b) use an external AND gate
as shown in Figure 4-26. Master and all Slave devices
are synchronized when the AND gate output toggles
to “High”.
Where:
N = Number of bits
C
= Capacitive load of output pin
LOAD
The capacitive load presented at the output pins needs
to be minimized to minimize digital power consumption.
The output load current of the LVDS output is constant,
since it is set by LVDS_IMODE<2:0> in Address 0x63
(Register 5-21).
The AutoSync feature can be used with the following
steps:
• Master device is selected by setting SLAVE pin to
“GND”: SYNC pin becomes output pin.
4.14.1
POWER-SAVING MODES
This device has two power-saving modes:
• Slave device is selected by setting SLAVE pin to
“High” (or tie to DVDD): SYNC pin becomes input
pin.
• Shutdown
• Standby
• Feed the Master’s SYNC pin output to Slave’s
SYNC pin.
They are set by the SHUTDOWN and STANDBY bits in
Address 0x00 (Register 5-1).
• Use AutoSync mode using (a) Power-On Reset
(Figure 2-9), (b) RESET Pin (Figure 2-10), or (c)
SOFT RESET bit (Figure 2-11).
In Shutdown mode, most of the internal circuitry,
including the reference and clock, are turned off with
the exception of the SPI interface. During Shutdown,
the device consumes 23 mA (typical), primarily due to
digital leakage. When exiting from Shutdown, issuing a
Soft Reset at the same time is highly recommended.
DS20006382A-page 73
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
DV
DD18
Pull-up
(> 360
DV
DD18
)
SYNC Pin Output
SLAVE
SYNC
CAL
SYNC
SLAVE
CAL
MCP37Dx1-80
MCP37Dx1-80
Master
Slave 1
DV
DD18
SYNC
SLAVE
CAL
MCP37Dx1-80
Slave 2
DV
DD18
“High” when
all devices
complete
SYNC
SLAVE
CAL
calibration
MCP37Dx1-80
Slave N
AND Gate
Note:
For optimum operation, it is highly recommended to use the same digital supply voltage (DVDD18,
DVDD12) (i.e., tie all DVDD12 together and tie all DVDD18 together) for Master and Slave devices.
FIGURE 4-27:
Synchronizing Multiple ADCs Using AutoSync Feature.
2020 Microchip Technology Inc.
DS20006382A-page 74
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 75
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
5.0
SERIAL PERIPHERAL
INTERFACE (SPI)
TABLE 5-1:
SPI PIN FUNCTIONS
Descriptions
Pin
Name
The user can configure the ADC for specific functions
or optimized performance by setting the device’s
internal registers through the serial peripheral interface
(SPI). The SPI communication uses three pins: CS,
SCLK and SDIO. Table 5-1 summarizes the SPI pin
functions. The SCLK is used as a serial timing clock
and can be used up to 50 MHz. SDIO (Serial Data
Input/Output) is a dual-purpose pin that allows data to
be sent or read from the internal registers. The Chip
Select pin (CS) enables SPI communication when
active-low. The falling edge of CS followed by a rising
edge of SCLK determines the start of the SPI
communication. When CS is tied to high, SPI
communication is disabled and the SPI pins are placed
in high-impedance mode. The internal registers are
accessible by their address.
Chip Select pin. SPI mode is initiated at
the falling edge. It needs to maintain
active-low for the entire period of the
SPI communication. The device exits the
SPI communication at the rising edge.
CS
Serial clock input pin.
• Writing to the device: Data is latched
at the rising edge of SCLK
SCLK
• Reading from the device: Data is
latched at the falling edge of SCLK
Serial data input/output pin. This pin is
initially an input pin (SDI) during the first
16-bit instruction header. After the
instruction header, its I/O status can be
changed depending on the R/W bit:
Figures 5-1 and 5-2 show the SPI data communication
protocols for this device with MSb-first and LSb-first
options, respectively. It consists of:
SDIO
• if R/W = 0: Data input pin (SDI) for
writing
• if R/W = 1: Data output pin (SDO) for
reading
• 16-bit wide instruction header + Data byte 1 +
Data byte 2 + . . . + Data Byte N
Table 5-2 summarizes the bit functions. The R/W bit of
the instruction header indicates whether the command
is a read (‘1’) or a write (‘0’):
TABLE 5-2:
SPI DATA PROTOCOL BIT
FUNCTIONS
Bit Name
R/W
Descriptions
• If the R/W bit is ‘1’, the SDIO pin changes
direction from an input (SDI) to an output (SDO)
after the 16-bit wide instruction header.
1= Read Mode
0= Write Mode
By selecting the R/W bit, the user can write the register
or read back the register contents. The W1 and W2 bits
in the instruction header indicate the number of data
bytes to transmit or receive in the following data frame.
W1, W0
(Data
Length)
00= Data for one register (1 byte)
01= Data for two registers (2 bytes)
10= Data for three registers (3 bytes)
11= Continuous reading or writing by
)
clocking SCLK(1
Bits A2 – A0 are the SPI device address bits. These
bits are used when multiple devices are used in the
same SPI bus. A2 is internally hardcoded to ‘0’. Bits A1
and A0 correspond to the logic level of the ADR1 and
ADR0 pins, respectively.
A2 - A0
Device SPI Address for multiple
devices in SPI bus
A2: Internally hardcoded to ‘0’
A1: Logic level of ADR1 pin
A0: Logic level of ADR0 pin
The R9 – R0 bits represent the starting address of the
Configuration register to write or read. The data bytes
following the instruction header are the register data.
All register data is eight bits wide. Data can be sent in
MSb-first mode (default) or in LSb-first mode, which is
determined by the <LSb_ FIRST> bit setting in Address
0x00 (Register 5-1). In Write mode, the data is clocked
in at the rising edge of the SCLK. In the Read mode, the
data is clocked out at the falling edge of the SCLK.
R9 - R0
D7 - D0
Address of starting register
Register data. MSb or LSb first,
depending on the LSb_FIRST bit
setting in 0x00
Note 1: The register address counter is incremented
by one per step. The counter does not
automatically reset to 0x00 after reaching the
last address (0x15D). Be aware that the user
registers are not sequentially allocated.
2020 Microchip Technology Inc.
DS20006382A-page 76
MCP37D31-80 AND MCP37D21-80
CS
SCLK
SDIO
R/W W1 W0 A2 A1 A0 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
D2
D1 D0
Register Data N
Register Data 2
Address of
Starting Register
Register Data of
starting register
defined by R9 - R0
Device Address
16-Bit Instruction Header
Register Data
FIGURE 5-1:
SPI Serial Data Communication Protocol with MSb-first. See Figures 2-5 and 2-6 for
Timing Specifications.
CS
SCLK
SDIO
R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 A0 A1 A2 W0 W1 R/W D0 D1 D2 D3 D4
D6 D7 D0 D1 D2 D3 D4
D6 D7
D5
D5
D5 D6
D7
Address of
Starting Register
Register Data N
Register Data 2
Register Data of
starting register
defined by R9 - R0
Device Address
16-Bit Instruction Header
Register Data
FIGURE 5-2:
SPI Serial Data Communication Protocol - with LSb-First. See Figures 2-5 and 2-6 for
Timing Specifications.
5.1
Register Initialization
Note 1: All address and bit locations that are not
included in the following register map
table should not be written or modified by
the user.
The internal Configuration registers are initialized to
their default values under two different conditions:
• After 220 clock cycles of delay from the Power-on
Reset (POR).
2: Some registers include factory-controlled
• Resetting the hardware reset pin (RESET).
Figures 2-5 and 2-6 show the timing details.
bits (FCB). Do not overwrite these bits.
5.2
Configuration Registers
The internal registers are mapped from Addresses
0x00 0x15D. These user registers are not
–
sequentially located. Some user Configuration
registers include factory-controlled bits. The factory-
controlled bits should not be overwritten by the user.
All user Configuration registers are read/write, except
for the last four registers, which are read-only. Each
register is made of an 8-bit-wide volatile memory, and
their default values are loaded during the power-up
sequence or by using the hardware RESET pin. All
registers are accessible by the SPI command using the
register address. Table 5-3 shows the user-register
memory map, and Registers 5-1 – 5-82 show the
details of the register bit functions.
DS20006382A-page 77
2020 Microchip Technology Inc.
TABLE 5-3:
REGISTER MAP TABLE
Bits
Default
Value
Addr.
Register Name
b7
b6
b5
b4
b3
b2
b1
b0
0x00 SPI Bit Ordering and ADC
Mode Selection
SHUTDOWN
LSb-FIRST
SOFT_RESET
STANDBY
1= Standby
STANDBY
SOFT_RESET
0=Soft Reset
LSb-FIRST
SHUTDOWN
0x24
1= Shutdown
1= LSb first
0= MSb first
0= Soft Reset
1= Standby
1= LSb first
0= MSb first
1= Shutdown
0x01 No. of Channel Selection and
Independency Control of
EN_DATCLK_IND
FCB<3> = 0
SEL_NCH<2:0>
FCB<2:0> = 111
0x0F
0x00
Output Data and Clock Divider
0x02 Output Data and
Clock Rate Control
OUT_DATARATE<3:0>
OUT_CLKRATE<3:0>
0x04 SPI SDO Timing Control
SDO_TIME
POL_WCK
FCB<6:0> = 0011111
FCB<4:0> = 10001
0x9F
0x62
0x07 Output Randomizer
and WCK Polarity Control
EN_AUTOCAL_
TIMEDLY
EN_OUT_
RANDOM
0x1E Auto-Calibration
Time Delay Control
AUTOCAL_TIMEDLY<7:0>
0x80
0x52
DLL Control
EN_DUTY
DCLK_PHDLY_DLL<2:0>
EN_DLL_DCLK
EN_DLL
EN_CLK
RESET_DLL
0x0A
0x45
0x00
0x48
0x53 Clock Source Selection
0x54 PLL Reference Divider
FCB<6:4>= 010
CLK_SOURCE
PLL_REFDIV<7:0>
FCB<3:0>= 0101
0x55 PLL Output and
Reference Divider
PLL_OUTDIV<3:0>
FCB<1:0> = 10
PLL_REFDIV<9:8>
0x56 PLL Prescaler (LSb)
0x57 PLL Prescaler (MSb)
0x58 PLL Charge Pump
PLL_PRE (LSB)<7:0>
0x78
0x40
0x12
0x41
0x2F
0x27
0x27
0x27
0xF1
0x10
FCB<3:0> = 0100
FCB<2:0> = 000
PLL_PRE (MSB)<11:8>
PLL_CHAGPUMP<3:0>
PLL_BIAS
0x59 PLL Enable Control 1
0x5A PLL Loop Filter Resistor
0x5B PLL Loop Filter Cap3
0x5C PLL Loop Filter Cap1
0x5D PLL Loop Filter Cap2
0x5F PLL Enable Control 2
U
U
U
U
U
FCB<4:3> = 10
FCB<1:0> = 01
FCB<1:0> = 01
FCB<1:0> = 01
FCB<1:0> = 01
FCB<5:2> = 1111
EN_PLL_REFDIV
FCB<2:1> = 00
PLL_RES<4:0>
EN_PLL
FCB<0> = 1
PLL_CAP3<4:0>
PLL_CAP1<4:0>
PLL_CAP2<4:0>
EN_PLL_BIAS
EN_PLL_OUT
OUTPUT_MODE<1:0>
FCB<1:0> = 01
0x62 Output Data Format and
Output Test Pattern
U
LVDS_8CH
DATA_FORMAT
TEST_PATTERNS<2:0>
0x63 ADC Output Bits
(Resolution) and LVDS
Output Load
OUTPUT_BIT<3:0>
LVDS_LOAD
LVDS_IMODE<2:0>
0x01
0x03
0x00
0x64 Output Clock Phase
Control when Decimation
Filter is used
EN_PHDLY
DCLK_PHDLY_DEC<2:0>
FCB<3:0> = 0011
0x65 LVDS Output Polarity Control
POL_LVDS<7:0>
1 = bit is set 0 = bit is cleared
Legend:
2:
U = Unimplemented bit, read as ‘0’
Read-only register. Preprogrammed at the factory for internal use.
FCB = Factory-Controlled Bits. Do not program
x = bit is unknown
TABLE 5-3:
REGISTER MAP TABLE (CONTINUED)
Bits
Default
Value
Addr.
Register Name
b7
b6
b5
b4
b3
b2
b1
b0
0x66 Digital Offset
Correction - Lower Byte
DIG_OFFSET_GLOBAL<7:0>
DIG_OFFSET_GLOBAL<15:8>
0x00
0x00
0x67 Digital Offset
Correction - Upper Byte
0x68 WCK/OVR and DM1/DM2
0x6B PLL Calibration
FCB<3:0> = 0010
POL_WCK_OVR
EN_WCK_OVR
PLL_CAL_TRIG
DM1DM2
POL_DM1DM2
0x24
0x08
0x00
FCB<6:2> = 00001
FCB<1:0> = 00
0x6D PLL Output and Output Clock
Phase
U<1:0>
EN_PLL_CLK
FCB<1> = 0
PATTERN A<7:0>
DCLK_DLY_PLL<2:0>
FCB<0> = 0
0x74 User-Defined Output
Pattern A - Lower Byte
0x00
0x00
0x00
0x00
0x75 User-Defined Output
Pattern A - Upper Byte
PATTERN A<15:8>
PATTERN B<7:0>
PATTERN B<15:8>
0x76 User-Defined Output
Pattern B - Lower Byte
0x77 User-Defined Output
Pattern B - Upper Byte
0x79 Dual-Channel DSPP Control
0x7A FDR and FIR_A0
0x7B FIR A Filter
EN_DSPP_2
FCB<6:0> = 000 0000
0x00
0x00
0x00
0x00
0x78
FCB<5> = 0
FIR_A<0>
EN_FDR
FCB<4:0> = 00000
FIR_A<8:1>
FIR_B<7:0>
0x7C FIR B Filter
0x7D Auto-Scan Channel Order -
Lower Byte
CH_ORDER<7:0>
0x7E Auto-Scan Channel Order -
Middle Byte
CH_ORDER<15:8>
CH_ORDER<23:16>
0xAC
0x8E
0x00
0x00
0x00
0x7F Auto-Scan Channel Order -
Upper Byte
0x80 Digital Down-Converter
Control 1
HBFILTER_B
FDR_BAND
HBFILTER_A
EN_DDC2
EN_NCO
EN_AMPDITH
SEL_FDR
NCO_TUNE<7:0>
EN_PHSDITH
EN_LFSR
8CH_CW
EN_DDC_FS/8
EN_DDC1
0x81 Digital Down-Converter
Control 2
GAIN_HBF_DDC
EN_DSPP_8
GAIN_8CH<1:0>
0x82 Numerically Controlled
Oscillator (NCO) Tuning -
Lower Byte
0x83 Numerically Controlled
Oscillator (NCO) Tuning -
Middle Lower Byte
NCO_TUNE<15:8>
NCO_TUNE<23:16>
0x00
0x00
0x84 Numerically Controlled
Oscillator (NCO) Tuning -
Middle Upper Byte
Legend:
2:
U = Unimplemented bit, read as ‘0’
Read-only register. Preprogrammed at the factory for internal use.
FCB = Factory-Controlled Bits. Do not program
1 = bit is set
0 = bit is cleared
x = bit is unknown
TABLE 5-3:
REGISTER MAP TABLE (CONTINUED)
Bits
Default
Value
Addr.
Register Name
b7
b6
b5
b4
NCO_TUNE<31:24>
b3
b2
b1
b0
0x85 Numerically Controlled
Oscillator (NCO) Tuning -
Upper Byte
0x00
0x86 CH0 NCO Phase Offset in CW
or DDC Mode - Lower Byte
CH0_NCO_PHASE<7:0>
CH0_NCO_PHASE<15:8>
CH1_NCO_PHASE<7:0>
CH1_NCO_PHASE<15:8>
CH2_NCO_PHASE<7:0>
CH2_NCO_PHASE<15:8>
CH3_NCO_PHASE<7:0>
CH3_NCO_PHASE<15:8>
CH4_NCO_PHASE<7:0>
CH4_NCO_PHASE<15:8>
CH5_NCO_PHASE<7:0>
CH5_NCO_PHASE<15:8>
CH6_NCO_PHASE<7:0>
CH6_NCO_PHASE<15:8>
CH7_NCO_PHASE<7:0>
CH7_NCO_PHASE<15:8>
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x87 CH0 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x88 CH1 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x89 CH1 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x8A CH2 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x8B CH2 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x8C CH3 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x8D CH3 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x8E CH4 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x8F CH4 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x90 CH5 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x91 CH5 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x92 CH6 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x93 CH6 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x94 CH7 NCO Phase Offset in CW
or DDC Mode - Lower Byte
0x95 CH7 NCO Phase Offset in CW
or DDC Mode - Upper Byte
0x96 CH0 Digital Gain
0x97 CH1 Digital Gain
0x98 CH2 Digital Gain
0x99 CH3 Digital Gain
CH0_DIG_GAIN<7:0>
CH1_DIG_GAIN<7:0>
CH2_DIG_GAIN<7:0>
CH3_DIG_GAIN<7:0>
0x3C
0x3C
0x3C
0x3C
Legend:
2:
U = Unimplemented bit, read as ‘0’
Read-only register. Preprogrammed at the factory for internal use.
FCB = Factory-Controlled Bits. Do not program
1 = bit is set
0 = bit is cleared
x = bit is unknown
TABLE 5-3:
REGISTER MAP TABLE (CONTINUED)
Bits
Default
Value
Addr.
Register Name
b7
b6
b5
b4
b3
b2
b1
b0
0x9A CH4 Digital Gain
0x9B CH5 Digital Gain
0x9C CH6 Digital Gain
0x9D CH7 Digital Gain
0x9E CH0 Digital Offset
0x9F CH1 Digital Offset
0xA0 CH2 Digital Offset
0xA1 CH3 Digital Offset
0xA2 CH4 Digital Offset
0xA3 CH5 Digital Offset
0xA4 CH6 Digital Offset
0xA5 CH7 Digital Offset
0xA7 Digital Offset Weight Control
CH4_DIG_GAIN<7:0>
CH5_DIG_GAIN<7:0>
CH6_DIG_GAIN<7:0>
CH7_DIG_GAIN<7:0>
0x3C
0x3C
0x3C
0x3C
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x47
─
CH0_DIG_OFFSET<7:0>
CH1_DIG_OFFSET<7:0>
CH2_DIG_OFFSET<7:0>
CH3_DIG_OFFSET<7:0>
CH4_DIG_OFFSET<7:0>
CH5_DIG_OFFSET<7:0>
CH6_DIG_OFFSET<7:0>
CH7_DIG_OFFSET<7:0>
DIG_OFFSET_WEIGHT<1:0>
FCB<6:0> = 000-0000
FCB<5:3> = 010
FCB<2:0> = 111
0xC0 Calibration Status
Indication (Read only)
ADC_CAL_STAT
0xD1 PLL Calibration Status
and PLL Drift Status Indication
(Read only)
FCB<4:3> = xx
PLL_CAL_STAT
FCB<2:1> = xx
PLL_VCOL_STAT PLL_VCOH_STAT
FCB<0> = x
─
0x15C CHIP ID - Lower Byte(2)
(Read only)
0x15D CHIP ID - Upper Byte(2)
(Read only)
CHIP_ID<7:0>
CHIP_ID<15:8>
─
─
Legend:
2:
U = Unimplemented bit, read as ‘0’
Read-only register. Preprogrammed at the factory for internal use.
FCB = Factory-Controlled Bits. Do not program
1 = bit is set
0 = bit is cleared
x = bit is unknown
MCP37D31-80 AND MCP37D21-80
)
REGISTER 5-1:
ADDRESS 0X00 – SPI BIT ORDERING AND ADC MODE SELECTION(1
R/W-0
R/W-0
LSb_FIRST
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
SHUTDOWN
bit 0
SHUTDOWN
bit 7
SOFT_RESET
STANDBY
STANDBY
SOFT_RESET
LSb_FIRST
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘0’ = Bit is cleared
x = Bit is unknown
(2)
bit 7
bit 6
bit 5
SHUTDOWN: Shutdown mode setting for power-saving
1= ADC in Shutdown mode
0= Not in Shutdown mode (Default)
LSb_FIRST: Select SPI communication bit order
1= Start SPI communication with LSb first
0= Start SPI communication with MSb first (Default)
(3)
SOFT_RESET: Soft Reset control bit
1= Not in Soft Reset mode (Default)
0= ADC in Soft Reset
(4)
(4)
bit 4
bit 3
bit 2
STANDBY: Send the device into a power-saving Standby mode
1= ADC in Standby mode
0= Not in Standby mode (Default)
STANDBY: Send the device into a power-saving Standby mode
1= ADC in Standby mode
0= Not in Standby mode (Default)
(3)
SOFT_RESET: Soft Reset control bit
1= Not in Soft Reset mode (Default)
0= ADC in Soft Reset
bit 1
bit 0
LSb_FIRST: Select SPI communication bit order
1= Start SPI communication with LSb first
0= Start SPI communication with MSb first (Default)
(2)
SHUTDOWN: Shutdown mode setting for power-saving
1= ADC in Shutdown mode
0= Not in Shutdown mode (Default)
Note 1:
2:
Upper and lower nibble are mirrored, which makes the MSb- or LSb-first mode interchangeable. The lower nibble (bit <3:0>)
has a higher priority when the mirrored bits have different values.
During Shutdown mode, most of the internal circuits including the reference and clock are turned-off except for the SPI
interface. When exiting from Shutdown (changing from ‘1’ to ‘0’), executing the device Soft Reset simultaneously is highly
recommended for a fast recalibration of the ADC. The internal user registers are not affected.
This bit forces the device into Soft Reset mode, which initializes the internal calibration registers to their initial default states.
The user-registers are not affected. When exiting Soft Reset mode (changing from ‘0’ to ‘1’), the device performs an automatic
device calibration including PLL calibration if PLL is enabled. DLL is reset if enabled. During Soft Reset, the device has the
following states:
3:
-
-
no ADC output
no change in power-on condition of internal reference
- most of the internal clocks are not distributed
- power consumption: (a) digital section - negligible, (b) analog section - no change
During Standby mode, most of the internal circuits are turned off except for the reference, clock and SPI interface. When exiting
from Standby mode (changing from ‘1’ to ‘0’) after an extended amount of time, executing Soft Reset simultaneously is highly
recommended. The internal user registers are not affected.
4:
2020 Microchip Technology Inc.
DS20006382A-page 82
MCP37D31-80 AND MCP37D21-80
REGISTER 5-2:
ADDRESS 0X01 – NUMBER OF CHANNELS, INDEPENDENCY CONTROL OF OUTPUT
DATA AND CLOCK DIVIDER
R/W-0
EN_DATCLK_IND
bit 7
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
FCB<3>
SEL_NCH<2:0>
FCB<2:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7
EN_DATCLK_IND: Enable data and clock divider independently
1= Enabled
0= Disabled (Default)
bit 6
FCB<3>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
(2)
bit 5-3
SEL_NCH<2:0>: Select the total number of input channels to be used
111= 7 inputs
110= 6 inputs
101= 5 inputs
100= 4 inputs
011= 3 inputs
010= 2 inputs
001= 1 input (Default)
000= 8 inputs
bit 2-0
FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1:
2:
EN_DATCLK_IND = 1enables OUT_CLKRATE<3:0> settings in Address 0x02 (Register 5-3).
See Addresses 0x7D – 0x7F (Registers 5-37 – 5-39) for selecting the input channel order.
DS20006382A-page 83
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-3:
ADDRESS 0X02 – OUTPUT DATA AND CLOCK RATE CONTROL(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
OUT_DATARATE<3:0>
OUT_CLKRATE<3:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
OUT_DATARATE<3:0>: Output data rate control bits
1111= Output data is all 0’s
1110= Output data is all 0’s
1101= Output data is all 0’s
(2)
1100= Internal test only
1011= Internal test only
1010= Internal test only
(2)
(2)
1001= Full speed divided by 512
1000= Full speed divided by 256
0111= Full speed divided by 128
0110= Full speed divided by 64
0101= Full speed divided by 32
0100= Full speed divided by 16
0011= Full speed divided by 8
0010= Full speed divided by 4
0001= Full speed divided by 2
0000= Full-speed rate (Default)
(3,4)
bit 3-0
OUT_CLKRATE<3:0>: Output clock rate control bits
1111= Full-speed rate
1110= No clock output
1101= No clock output
1100= No clock output
1011= No clock output
1010= No clock output
1001= Full speed divided by 512
1000= Full speed divided by 256
0111= Full speed divided by 128
0110= Full speed divided by 64
0101= Full speed divided by 32
0100= Full speed divided by 16
0011= Full speed divided by 8
0010= Full speed divided by 4
0001= Full speed divided by 2
0000= No clock output (Default)
Note 1:
2:
This register should be used to realign the output data and clock when the decimation or digital down-conversion (DDC) option
is used.
1100 - 1010: Do not reprogram. These settings are used for the internal test only. If these bits are reprogrammed with differ-
ent settings, the outputs will be in an undefined state.
3:
4:
Bits <3:0> become active if EN_DATCLK_IND = 1in Address 0x01 (Register 5-2).
When no clock output is selected (Bits 1110 - 1010): clock output is not available at the DCLK+/DCLK- pins.
2020 Microchip Technology Inc.
DS20006382A-page 84
MCP37D31-80 AND MCP37D21-80
REGISTER 5-4:
ADDRESS 0X04 – SPI SDO OUTPUT TIMING CONTROL
R/W-1
SDO_TIME
bit 7
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
FCB<6:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
SDO_TIME: SPI SDO output timing control bit
1= SDO output at the falling edge of clock (Default)
0= SDO output at the rising edge of clock
bit 6-0
FCB<6:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
REGISTER 5-5:
ADDRESS 0X07 – OUTPUT RANDOMIZER AND WCK POLARITY CONTROL
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
POL_WCK
EN_AUTOCAL_-
TIMEDLY
FCB<4:0>
EN_OUT_RANDOM
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
(1)
bit 7
bit 6
POL_WCK: WCK polarity control bit
1= Inverted
0= Not inverted (Default)
(2)
EN_AUTOCAL_TIMEDLY: Auto-calibration starter time delay counter control bit
1= Enabled (Default)
0= Disabled
bit 5-1
bit 0
FCB<4:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
EN_OUT_RANDOM: Output randomizer control bit
1= Enabled: ADC data output is randomized
0= Disabled (Default)
Note 1:
2:
See Address 0x68 (Register 5-26) for WCK/OVR pair control.
This bit enables the AUTOCAL_TIMEDLY<7:0> settings. See Address 0x1E (Register 5-6).
DS20006382A-page 85
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-6:
ADDRESS 0X1E – AUTOCAL TIME DELAY CONTROL(1)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
AUTOCAL_TIMEDLY<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-0
AUTOCAL_TIMEDLY<7:0>: Auto-calibration start time delay control bits
1111-1111= Maximum value
• • •
1000-0000= (Default)
• • •
0000-0000= Minimum value
Note 1:
EN_AUTOCAL_TIMEDLY in Address 0x07 (Register 5-5) enables this register setting. This register controls the time delay
before the auto-calibration starts. The value increases linearly with the bit settings, from minimum to maximum values.
REGISTER 5-7:
ADDRESS 0X52 – DLL CONTROL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
R/W-0
EN_DUTY
DCLK_PHDLY_DLL<2:0>
EN_DLL_DCLK
EN_DLL
EN_CLK
RESET_DLL
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
EN_DUTY: Enable DLL circuit for duty cycle correction (DCC) of input clock
1= Correction is ON
0= Correction is OFF (Default)
(1)
bit 6-4
DCLK_PHDLY_DLL<2:0>: Select the phase delay of the digital clock output when using DLL
111= +315° phase-shifted from default
110= +270° phase-shifted from default
101= +225° phase-shifted from default
100= +180° phase-shifted from default
011= +135 phase-shifted from default
010= +90° phase-shifted from default
001= +45° phase-shifted from default
000= (Default)
bit 3
bit 2
bit 1
EN_DLL_DCLK: Enable DLL digital clock output
1= Enabled (Default)
0= Disabled: DLL digital clock is turned off. ADC output is not available when DLL is used.
EN_DLL: Enable DLL circuitry to provide a selectable phase clock to digital output clock.
1= Enabled
0= Disabled. DLL block is disabled (Default)
EN_CLK: Enable clock input buffer
1= Enabled (Default).
0= Disabled. No clock is available to the internal circuits, ADC output is not available.
(2)
bit 0
RESET_DLL: DLL circuit reset control
1= DLL is active
0= DLL circuit is held in reset (Default)
Note 1:
2:
These bits have an effect only if EN_PHDLY = 1 and decimation is not used.
DLL reset control procedure: Set this bit to ‘0’ (reset) and then to ‘1’.
2020 Microchip Technology Inc.
DS20006382A-page 86
MCP37D31-80 AND MCP37D21-80
REGISTER 5-8:
ADDRESS 0X53 – CLOCK SOURCE SELECTION
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-1
FCB<6:4>
CLK_SOURCE
FCB<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
FCB<6:4>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
CLK_SOURCE: Select internal timing source
1= PLL output is selected as timing source
0= External clock input is selected as timing source (Default)
bit 3-0
FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
REGISTER 5-9:
ADDRESS 0X54 – PLL REFERENCE DIVIDER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLL_REFDIV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
PLL_REFDIV<7:0>: PLL Reference clock divider control bits
1111-1111= PLL reference divided by 255 (if PLL_REFDIV<9:8> = 00)
1111-1110= PLL reference divided by 254 (if PLL_REFDIV<9:8> = 00)
• • •
0000-0011= PLL reference divided by 3 (if PLL_REFDIV<9:8> = 00)
0000-0010= Do not use (No effect)
0000-0001= PLL reference divided by 1 (if PLL_REFDIV<9:8> = 00)
0000-0000= PLL reference not divided (if PLL_REFDIV<9:8> = 00) (Default)
Note 1:
PLL_REFDIV is a 10-bit wide setting. See Address 0x55 (Register 5-10) for the upper two bits and Table 5-4 for PLL_REF-
DIV<9:0> bit settings. This setting controls the clock division ratio of the PLL reference clock (external clock input at the CLK
pin) before the PLL phase-frequency detector circuitry. Note that the divider value of 2 is not supported. EN_PLL_REFDIV in
Address 0x59 (Register 5-14) must be set.
DS20006382A-page 87
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-10:
ADDRESS 0X55 – PLL OUTPUT AND REFERENCE DIVIDER
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
FCB<1:0>
R/W-0
R/W-0
PLL_OUTDIV<3:0>
PLL_REFDIV<9:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-4
PLL_OUTDIV<3:0>: PLL output divider control bits
1111= PLL output divided by 15
1110= PLL output divided by 14
• • •
0100= PLL output divided by 4 (Default)
0011= PLL output divided by 3
0010= PLL output divided by 2
0001= PLL output divided by 1
0000= PLL output not divided
bit 3-2
bit 1-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(2)
PLL_REFDIV<9:8>: Upper two MSb bits of PLL_REFDIV<9:0>
00= see Table 5-4. (Default)
Note 1:
2:
PLL_OUTDIV<3:0> controls the PLL output clock divider: VCO output is divided by the PLL_OUTDIV<3:0> setting.
See Address 0x54 (Register 5-9) and Table 5-4 for PLL_REFDIV<9:0> settings. EN_PLL_REFDIV in Address 0x59
(Register 5-14) must be set.
TABLE 5-4:
EXAMPLE – PLL REFERENCE DIVIDER BIT SETTINGS VS. PLL REFERENCE INPUT
FREQUENCY
PLL_REFDIV<9:0>
PLL Reference Frequency
11-1111-1111
11-1111-1110
─
00-0000-0011
00-0000-0010
00-0000-0001
00-0000-0000
Reference frequency divided by 1023
Reference frequency divided by 1022
─
Reference frequency divided by 3
Do not use (not supported)
Reference frequency divided by 1
Reference frequency divided by 1
2020 Microchip Technology Inc.
DS20006382A-page 88
MCP37D31-80 AND MCP37D21-80
REGISTER 5-11:
ADDRESS 0X56 – PLL PRESCALER (LSB)
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
bit 0
PLL_PRE<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
(1)
bit 7-0
PLL_PRE<7:0>: PLL prescaler selection
1111-1111= VCO clock divided by 255 (if PLL_PRE<11:8> = 0000)
• • •
0111-1000= VCO clock divided by 120 (if PLL_PRE<11:8> = 0000) (Default)
• • •
0000-0010= VCO clock divided by 2 (if PLL_PRE<11:8> = 0000)
0000-0001= VCO clock divided by 1 (if PLL_PRE<11:8> = 0000)
0000-0000= VCO clock not divided (if PLL_PRE<11:8> = 0000)
Note 1:
PLL_PRE is a 12-bit-wide setting. The upper four bits (PLL_PRE<11:8>) are defined in Address 0x57. See Table 5-5 for the
PLL_PRE<11:0> settings. The PLL Prescaler is used to divide down the VCO output clock in the PLL phase-frequency detector
loop circuit.
REGISTER 5-12:
ADDRESS 0X57 – PLL PRESCALER (MSB)
R/W-0
R/W-1
FCB<3:0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PLL_PRE<11:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-4
bit 3-0
FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
PLL_PRE<11:8>: PLL prescaler selection
12
1111= 2 - 1 (max), if PLL_PRE<7:0> = 0xFF
• • •
0000= Default)
Note 1:
PLL_PRE is a 12-bit-wide setting. See the lower eight bit settings (PLL_PRE<7:0>) in Address 0x56 (Register 5-11). See
Table 5-5 for the PLL_PRE<11:0> settings for PLL feedback frequency.
TABLE 5-5:
Example: PLL Prescaler Bit Settings and PLL Feedback Frequency
PLL_PRE<11:0>
PLL Feedback Frequency
12
1111-1111-1111
1111-1111-1110
─
VCO clock divided by 4095 (2 - 1)
12
VCO clock divided by 4094 (2 - 2)
─
0000-0000-0011
0000-0000-0010
0000-0000-0001
0000-0000-0000
VCO clock divided by 3
VCO clock divided by 2
VCO clock divided by 1
VCO clock divided by 1
DS20006382A-page 89
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-13:
ADDRESS 0X58 – PLL CHARGE-PUMP
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
FCB<2:0>:
PLL_BIAS
PLL_CHAGPUMP<3:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-5
bit 4
FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
PLL_BIAS: PLL charge-pump bias source selection bit
1= Self-biasing coming from AV (Default)
DD
0 = Bandgap voltage from the reference generator (1.2V)
(1)
bit 3-0
PLL_CHAGPUMP<3:0>: PLL charge pump bias current control bits
1111= Maximum current
• • •
0010= (Default)
• • •
0000= Minimum current
Note 1:
PLL_CHAGPUMP<3:0> should be set based on the phase detector comparison frequency. The bias current amplitude
increases linearly with increasing the bit setting values. The increase is from approximately 25 µA to 375 µA, 25 µA per step.
See Section 4.7.2.1, "PLL Output Frequency and Output Control Parameters" for more details of the PLL block.
REGISTER 5-14:
ADDRESS 0X59 – PLL ENABLE CONTROL 1
U-0
—
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
FCB<4:3>
EN_PLL_REFDIV
FCB<2:1>
EN_PLL
FCB<0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
bit 4
FCB<4:3>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
EN_PLL_REFDIV: Enable PLL Reference Divider (PLL_REFDIV<9:0>).
1= Enabled
0= Reference divider is bypassed (Default)
bit 3-2
bit 1
FCB<2:1>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
EN_PLL: Enable PLL circuit.
1= Enabled
0= Disabled (Default)
bit 0
FCB<0>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
2020 Microchip Technology Inc.
DS20006382A-page 90
MCP37D31-80 AND MCP37D21-80
REGISTER 5-15:
ADDRESS 0X5A – PLL LOOP FILTER RESISTOR
U-0
—
R/W-0
R/W-1
FCB<1:0>
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
PLL_RES<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
bit 4-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
PLL_RES<4:0>: Resistor value selection bits for PLL loop filter
11111= Maximum value
• • •
01111= (Default)
• • •
00000= Minimum value
Note 1:
PLL_RES<4:0> should be set based on the phase detector comparison frequency. The resistor value increases linearly with the
bit settings, from minimum to maximum values. See the PLL loop filter section in Section 4.7, "ADC Clock Selection".
REGISTER 5-16:
ADDRESS 0X5B – PLL LOOP FILTER CAP3
U-0
—
R/W-0
R/W-1
FCB<1:0>
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
PLL_CAP3<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
bit 4-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
PLL_CAP3<4:0>: Capacitor 3 value selection bits for PLL loop filter
11111= Maximum value
• • •
00111= (Default)
• • •
00000= Minimum value
Note 1:
This capacitor is in series with the shunt resistor, which is set by PLL_RES<4:0>. The capacitor value increases linearly with the
bit settings, from minimum to maximum values. This setting should be set based on the phase detector comparison frequency.
DS20006382A-page 91
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-17:
ADDRESS 0X5C – PLL LOOP FILTER CAP1
U-0
—
R/W-0
R/W-1
FCB<1:0>
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
PLL_CAP1<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
bit 4-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
PLL_CAP1<4:0>: Capacitor 1 value selection bits for PLL loop filter
11111= Maximum value
• • •
00111= (Default)
• • •
00000= Minimum value
Note 1:
This capacitor is located between the charge pump output and ground, and in parallel with the shunt resistor which is defined by
the PLL_RES<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting
should be set based on the phase detector comparison frequency.
REGISTER 5-18:
ADDRESS 0X5D – PLL LOOP FILTER CAP2
U-0
—
R/W-0
R/W-1
FCB<1:0>
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
PLL_CAP2<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
Unimplemented: Not used.
bit 6-5
bit 4-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
PLL_CAP2<4:0>: Capacitor 2 value selection bits for PLL loop filter
11111= Maximum value
• • •
00111= (Default)
• • •
00000= Minimum value
Note 1:
This capacitor is located between the charge pump output and ground, and in parallel with CAP1 which is defined by the PLL_-
CAP1<4:0>. The capacitor value increases linearly with the bit settings, from minimum to maximum values. This setting should
be set based on the phase detector comparison frequency.
2020 Microchip Technology Inc.
DS20006382A-page 92
MCP37D31-80 AND MCP37D21-80
REGISTER 5-19:
ADDRESS 0X5F – PLL ENABLE CONTROL 2(1)
R/W-1
R/W-1
FCB<5:2>
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
EN_PLL_OUT EN_PLL_BIAS
FCB<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
FCB<5:2>: Factory-Controlled Bits. This is not for the user. Do not change the default settings.
EN_PLL_OUT: Enable PLL output.
1= Enabled
0= Disabled (Default)
bit 2
EN_PLL_BIAS: Enable PLL bias
1= Enabled
0= Disabled (Default)
bit 1-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1:
To enable PLL output, EN_PLL_OUT, EN_PLL_BIAS and EN_PLL in Address 0x59 (Register 5-14) must be set.
DS20006382A-page 93
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-20:
ADDRESS 0X62 – OUTPUT DATA FORMAT AND OUTPUT TEST PATTERN
U-0
—
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
bit 0
LVDS_8CH
DATA_FORMAT
OUTPUT_MODE<1:0>
TEST_PATTERNS<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
bit 6
Unimplemented: Not used.
(1)
LVDS_8CH: LVDS data stream type selection for octal-channel mode
1= Serialized data stream
0= Interleaved with parallel data stream (Default)
(2)
(3)
bit 5
DATA_FORMAT: Output data format selection
1= Offset binary (unsigned)
0= Two’s complement (Default)
(4)
bit 4-3
OUTPUT_MODE<1:0>: Output mode selection
(5)
11= DDR LVDS output mode with MSb byte first
(6)
10= DDR LVDS output mode with even bit first (Default)
01= CMOS output mode
00= Output disabled
bit 2-0
TEST_PATTERNS<2:0>: Test output data pattern selection
111= Output data is pseudo-random number (PN) sequence
(7)
110= Sync Pattern for LVDS output.
18-bit mode: '11111111 00000000 10'
16-bit mode: '11111111 00000000'
14-bit mode: '11111111 000000'
12-bit mode: '11111111 0000'
10-bit mode: '11111111 00'
101= Alternating Sequence for LVDS mode
16-bit mode: ‘01010101 10101010’
14-bit mode: ‘01010101 101010’
100= Alternating Sequence for CMOS.
Output: ‘11111111 11111111’ alternating with ‘00000000 00000000’
011= Alternating Sequence for CMOS.
Output: ‘01010101 01010101’ alternating with ‘10101010 10101010’
010= Ramp Pattern. Output is incremented by:
18-bit mode: 1 LSb per clock cycle
16-bit mode: 1 LSb per 4 clock cycles
14-bit mode: 1 LSb per 16 clock cycles
001= Double Custom Patterns.
Output: Alternating custom pattern A (see Addresses 0X74 – 0X75 - Registers 5-29 – 5-30) and custom
(8)
pattern B (see Address 0X76 - 0X77 - Registers 5-31 – 5-32)
000= Normal Operation. Output: ADC data (Default)
Note 1:
2:
This bit setting is valid for the octal-channel mode only. See Addresses 0x7D-0x7F (Registers 5-37 – 5-39) for channel order selection.
Serialized LVDS is available in octal-channel with 16-bit mode only: Each LVDS output pair holds a single input channel's data
and outputs in a serial data stream (synchronized with WCK): Q7+/Q7- is for the first channel’s selected data, and Q0+/Q0- is for
the last channel’s selected data. This bit function is enabled only when EN_DSPP_8 = 1in Address 0x81 (Register 5-41). See
Figure 2-4 for the timing diagram.
3:
The output is in parallel data stream. The first sampled data bit is clocked out first in parallel LVDS output pins, followed by the
next sampled channel data bit. See Figures 2-2 and 2-3 for the timing diagram.
See Figures 2-1 – 2-4 for the timing diagram.
4:
5:
Only 16-bit mode is available for this option.
Rising edge: Q15 - Q8.
Falling edge: Q7 - Q0
6:
Rising edge: Q14, Q12, Q10,.... Q0.
Falling edge: Q15, Q13, Q11,... Q1.
7:
8:
Pseudo-random number (PN) code is generated by the linear feedback shift register (LFSR).
The alternating patterns A and B are applied to Q<15:0>. Pattern A<15:14> and Pattern B<15:14> are also applied to OVR and
WCK pins, respectively. Pattern A<1:0> and Pattern B<1:0> are also applied to DM1/DM+ and DM2/DM-.
2020 Microchip Technology Inc.
DS20006382A-page 94
MCP37D31-80 AND MCP37D21-80
REGISTER 5-21:
ADDRESS 0X63 – ADC OUTPUT BIT (RESOLUTION) AND LVDS LOAD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
bit 0
OUTPUT_BIT
LVDS_LOAD
LVDS_IMODE<2:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
16-Bit Device (MCP37D31-80):
(1)
OUTPUT_BIT<3:0>: Select number of output data bits
1111= 15
1110= 14
1101= 13
1100= 12
1011= 11
1010= 10
1001= 9
1000= 8
0111= 7
0110= 6
0101= 5
0100= 4
0011= 3
0010= 2
0001= 1
0000= 16-bit (Default)
14-Bit Device (MCP37D21-80):
(2)
OUTPUT_BIT<3:0>: These bits have no effect
bit 3
LVDS_LOAD: Internal LVDS load termination
1= Enable internal load termination
0= Disable internal load termination (Default)
bit 2-0
LVDS_IMODE<2:0>: LVDS driver current control bits
111= 7.2 mA
011= 5.4 mA
001= 3.5 mA (Default)
000= 1.8 mA
Do not use the following settings
(3)
:
110, 101, 100, 010
Note 1:
These bits are applicable for the 16-bit device only. See Address 0x68 (Register 5-26) for additional DM1 and DM2 bits.
In the 14-bit device, ADC resolution is not user selectable.
These settings can result in unknown output currents.
2:
3:
DS20006382A-page 95
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-22:
ADDRESS 0X64 – OUTPUT CLOCK PHASE CONTROL WHEN DECIMATION FILTER IS USED
R/W-0
EN_PHDLY
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
DCLK_PHDLY_DEC<2:0>
FCB<3:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
EN_PHDLY: Enable digital output clock phase delay control when DLL or decimation filter is used.
1= Enabled
0= Disabled (Default)
(2)
bit 6-4
DCLK_PHDLY_DEC<2:0>: Digital output clock phase delay control when decimation filter is used
(2)
111= +315° phase-shifted from default
110= +270° phase-shifted from default
101= +225° phase-shifted from default
(2)
100= +180° phase-shifted from default
011= +135° phase-shifted from default
(2)
010= +90° phase-shifted from default
(2)
001= +45° phase-shifted from default
(3)
000= Default
bit 3-0
FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1:
2:
These bits have an effect only if EN_PHDLY = 1. See Address 0x52 (Register 5-7) for the same feature when DLL is used.
Only available when the decimation filter setting is greater than 2. When FIR_A/B <8:1> = 0’s (default) and FIR_A<6> = 0, only 4-
phase shifts are available (+45°, +135°, +225°, +315°) from default. See Addresses 0x7A, 0x7B and 0x7C (Registers 5-34 – 5-36).
See Addresses 0x6D and 0x52 (Registers 5-28 and 5-7) for DCLK phase shift for other modes.
3:
The phase delay for all other settings is referenced to this default phase.
REGISTER 5-23:
ADDRESS 0X65 – LVDS OUTPUT POLARITY CONTROL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POL_LVDS<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
(1)
bit 7-0
POL_LVDS<7:0>: Control polarity of LVDS data pairs (Q7+/Q7- – Q0+/Q0-)
1111-1111= Invert all LVDS pairs
1111-1110= Invert all LVDS pairs except the LSb pair
• • •
1000-0000= Invert MSb LVDS pair
• • •
0000-0001= Invert LSb LVDS pair
0000-0000= No inversion of LVDS bit pairs (Default)
Note 1:
(a) 14-bit mode: The LSb bit has no effect. (b) 12-bit mode: The last two LSb bits have no effect.
2020 Microchip Technology Inc.
DS20006382A-page 96
MCP37D31-80 AND MCP37D21-80
REGISTER 5-24:
ADDRESS 0X66 – DIGITAL OFFSET CORRECTION (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIG_OFFSET_GLOBAL<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
DIG_OFFSET_GLOBAL<7:0>: Lower byte of DIG_OFFSET_GLOBAL<15:0> for all channels
0000-0000= Default
Note 1:
Offset is added to the ADC output. Setting is two’s complement using two combined registers (16-bits wide).
Setting range: (-2 to 2 - 1) x step size. Step size of each bit setting:
15
15
-
-
-
-
12-bit mode: 0.125 LSb
14-bit mode: 0.25 LSb
16-bit mode: 0.5 LSb
18-bit mode: 1 LSb.
REGISTER 5-25:
ADDRESS 0X67 – DIGITAL OFFSET CORRECTION (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
DIG_OFFSET_GLOBAL<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
DIG_OFFSET_GLOBAL<15:8>: Upper byte of DIG_OFFSET_GLOBAL<15:0> for all channels
0000-0000= Default
Note 1:
See Note 1 in Address 0x66 (Register 5-24)
DS20006382A-page 97
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-26:
ADDRESS 0X68 – WCK/OVR AND DM1/DM2
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
FCB<3:0>
POL_WCK_OVR
EN_WCK_OVR
DM1DM2
POL_DM1DM2
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
bit 3
FCB<3:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
POL_WCK_OVR: Polarity control for WCK and OVR bit pair in LVDS mode
1= Inverted
0= Not inverted (Default)
bit 2
EN_WCK_OVR: Enable WCK and OVR output bit pair
1= Enabled (Default)
0= Disabled
(1)
bit 1
DM1DM2: Add two additional LSb bits (DM1/DM+ and DM2/DM- bits) to the output
1= Added
0= Not added (Default)
(1)
bit 0
POL_DM1DM2: Polarity control for DM1/DM+ and DM2/DM- pair in LVDS mode
1= Inverted
0= Not inverted (Default)
Note 1:
Applicable for 16-bit mode only: When this bit is set and the decimation is used, two additional LSb bits (DM1/DM+ and DM2/DM-,
DM2/DM- is the LSb) can be added and result in 18-bit resolution. See Addresses 0x7B and 0x7C (Registers 5-35 and 5-36) for the
decimation filter settings. See Address 0x63 (Register 5-21) for the output bit control.
2020 Microchip Technology Inc.
DS20006382A-page 98
MCP37D31-80 AND MCP37D21-80
REGISTER 5-27:
ADDRESS 0X6B – PLL CALIBRATION
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
FCB<6:2>
PLL_CAL_TRIG
FCB<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-3
bit 2
FCB<6:2>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
PLL_CAL_TRIG: Manually force recalibration of the PLL at the state of bit transition
Toggle from “1” to “0”, or “0” to “1” = Start PLL calibration
bit 1-0
FCB<1:0>: Factory-Controlled Bits. This is not for the user. Do not program.
See PLL_CAL_STAT in Address 0xD1 (Register 5-80) for calibration status indication.
Note 1:
REGISTER 5-28:
U-0 U-0
ADDRESS 0X6D – PLL OUTPUT AND OUTPUT CLOCK PHASE(1)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
─
EN_PLL_CLK
FCB<1>
DCLK_DLY_PLL<2:0>
FCB<0>
bit 0
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7-6
bit 5
Unimplemented: Not used
EN_PLL_CLK: Enable PLL output clock
1= PLL output clock is enabled to the ADC core
0= PLL clock output is disabled (Default)
bit 4
FCB<1>: Factory-Controlled Bit. This is not for the user. Do not change default settings.
(2)
bit 3-1
DCLK_DLY_PLL<2:0>: Output clock is delayed by the number of VCO clock cycles from the nominal PLL output
111= Delay of 15 cycles
110= Delay of 14 cycles
• • •
001= Delay of one cycle
000= No delay (Default)
bit 0
FCB<0>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
Note 1: This register has effect only when the PLL clock is selected by the CLK_SOURCE bit in Address 0x53
(Register 5-8) and PLL circuit is enabled by EN_PLL bit in Address 0x59 (Register 5-14).
2: This bit setting enables the output clock phase delay. This phase delay control option is applicable when PLL is
used as the clock source and the decimation is not used.
DS20006382A-page 99
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-29:
ADDRESS 0X74 – USER-DEFINED OUTPUT PATTERN A (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_A<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
PATTERN_A<7:0>: Lower byte of PATTERN_A<15:0>
Note 1:
See PATTERN_A<15:8> in Address 0x75 (Register 5-30) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20). If ADC
resolution is less than 16-bit, some LSbs are not used. Unused LSb = 16-n, where n = resolution. Leave the unused LSb bits as 0s.
REGISTER 5-30:
ADDRESS 0X75 – USER-DEFINED OUTPUT PATTERN A (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_A<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
PATTERN_A<15:8>: Upper byte of PATTERN_A<15:0>
Note 1:
See PATTERN_A<7:0> in Address 0x74 (Register 5-29) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
REGISTER 5-31:
ADDRESS 0X76 – USER-DEFINED OUTPUT PATTERN B (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_B<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
PATTERN_B<7:0>: Lower byte of PATTERN_B<15:0>
Note 1:
See PATTERN_B<15:8> in Address 0x77 (Register 5-32) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20). If ADC
resolution is less than 16-bit, some LSbs are not used. Unused LSb = 16-n, where n = resolution. Leave the unused LSb bits as 0s.
REGISTER 5-32:
ADDRESS 0X77 – USER-DEFINED OUTPUT PATTERN B (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PATTERN_B<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
PATTERN_B<15:8>: Upper byte of PATTERN_B<15:0>
Note 1:
See PATTERN_B<7:0> in Address 0x76 (Register 5-31) and TEST_PATTERNS<2:0> in Address 0x62 (Register 5-20).
2020 Microchip Technology Inc.
DS20006382A-page 100
MCP37D31-80 AND MCP37D21-80
REGISTER 5-33:
R/W-0
ADDRESS 0X79 – DUAL-CHANNEL DIGITAL SIGNAL POST-PROCESSING CONTROL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EN_DSPP_2
bit 7
FCB<6:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
EN_DSPP_2: Enable all digital post-processing functions for dual-channel operations
1= Enabled
0= Disabled (Default)
bit 6-0
FCB<6:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
REGISTER 5-34:
ADDRESS 0X7A – FRACTIONAL DELAY RECOVERY AND FIR_A0(1)
R/W-0
R/W-0
FIR_A<0>
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FCB<5>
EN_FDR
FCB<4:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
FCB<5>: Factory-Controlled Bit. This is not for the user. Do not change default setting.
(2)
FIR_A<0>: Enable the first 2x decimation (Stage 1A in FIR A) in single-channel mode
1= Enabled
0= Disabled (Default)
bit 5
EN_FDR: Enable fractional delay recovery (FDR) option
1= Enabled (with delay of 59 clock cycles).
0= Disabled (Default)
bit 4-0
FCB<4:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1:
2:
This register is used only for single and dual-channel modes.
This is the LSb for the FIR A filter settings. For the first 2x decimation, set FIR_A<0> = 1for single-channel operation, and
FIR_A<0> = 0for dual-channel operation. See Address 0x7B (Register 5-35) for FIR_A<8:1> settings.
DS20006382A-page 101
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-35:
ADDRESS 0X7B – FIR A FILTER(1,5)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIR_A<8:1>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(2)
bit 7-0
FIR_A<8:1>: Decimation Filter FIR A settings for Channel A (or I)
Single-Channel Mode:
(3)
FIR_A<8:0> =
1-1111-1111= Stage 1 - 9 filters (decimation rate: 512)
0-1111-1111= Stage 1 - 8 filters
0-0111-1111= Stage 1 - 7 filters
0-0011-1111= Stage 1 - 6 filters
0-0001-1111= Stage 1 - 5 filters
0-0000-1111= Stage 1 - 4 filters
0-0000-0111= Stage 1 - 3 filters (decimation rate = 8)
0-0000-0011= Stage 1 - 2 filters (decimation rate = 4)
0-0000-0001= Stage 1 filter (decimation rate = 2)
0-0000-0000= Disabled all FIR A filters. (Default)
(4)
Dual-Channel Mode:
FIR_A<8:0> =
1-1111-1110= Stage 2 - 9 filters (decimation rate: 256)
0-1111-1110= Stage 2 - 8 filters
0-0111-1110= Stage 2 - 7 filters
0-0011-1110= Stage 2 - 6 filters
0-0001-1110= Stage 2 - 5 filters
0-0000-1110= Stage 2 - 4 filters
0-0000-0110= Stage 2 - 3 filters
0-0000-0010= Stage 2 filter (decimation rate = 2)
0-0000-0000= Disabled all FIR A filters. (Default)
Note 1:
This register is used only for single and dual-channel modes. The register values are thermometer encoded.
FIR_A<0> is placed in Address 0x7A (Register 5-34).
In single-channel mode, the 1st stage filter is selected by FIR_A<0> = 1in Address 0x7A (Register 5-34).
In dual-channel mode, the 1st stage filter is disabled by setting FIR_A<0> = 0in Address 0x7A.
SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation rate for the single-channel mode is 512, and 256 for the dual-channel mode.
2:
3:
4:
5:
2020 Microchip Technology Inc.
DS20006382A-page 102
MCP37D31-80 AND MCP37D21-80
REGISTER 5-36:
ADDRESS 0X7C – FIR B FILTER(1,2)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
FIR_B<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(3)
bit 7-0
FIR_B<7:0>:Decimation Filter FIR B settings for Channel B (or Q)
1111-1111= Stage 2 - 9 filters (decimation rate = 256)
0111-1111= Stage 2 - 8 filters
0011-1111= Stage 2 - 7 filters
0001-1111= Stage 2 - 6 filters
0000-1111= Stage 2 - 5 filters
0000-0111= Stage 2 - 4 filters
0000-0011= Stage 2 - 3 filters
0000-0001= Stage 2 filter (decimation rate = 2)
0000-0000= Disabled all FIR B Filters. (Default)
Note 1:
This register is used for the dual-channel mode only. The register values are thermometer encoded.
EN_DSPP_2 bit in Address 0x79 (Register 5-34) must be set when using decimation in dual-channel mode.
SNR is improved by approximately 2.5 dB per each filter stage, and output data rate is reduced by a factor of two per stage. The
data and clock rates in Address 0X02 (Register 5-3) need to be updated accordingly. Address 0x64 (Register 5-22) setting is
also affected. The maximum decimation factor for the dual-channel mode is 256.
2:
3:
REGISTER 5-37:
ADDRESS 0X7D – AUTO-SCAN CHANNEL ORDER (LOWER BYTE)
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
R/W-0
CH_ORDER<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH_ORDER<7:0>: Lower byte of CH_ORDER<31:0>
0111-1000= Default
Note 1:
See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-38:
ADDRESS 0X7E – AUTO-SCAN CHANNEL ORDER (MIDDLE BYTE)
R/W-1
R/W-0
R/W-1
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
CH_ORDER<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH_ORDER<15:8>: Middle byte of CH_ORDER<31:0>
1010-1100= Default
Note 1:
See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
DS20006382A-page 103
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-39:
ADDRESS 0X7F – AUTO-SCAN CHANNEL ORDER (UPPER BYTE)
R/W-1
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-0
CH_ORDER<23:16>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH_ORDER<23:16>: Upper byte of CH_ORDER<31:0>
1000-1110= Default
Note 1:
See Table 5-3 for the channel order selection. See SEL_NCH<2:0> in Address 0x01 (Register 5-2) for the number of channels
to be selected.
REGISTER 5-40:
ADDRESS 0X80 – DIGITAL DOWN-CONVETER CONTROL 1(1)
R/W-0
R/W-0
HBFILTER_A
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EN_DDC1
bit 0
HBFILTER_B
bit 7
EN_NCO
EN_AMPDITH
EN_PHSDITH
EN_LFSR
EN_DDC_FS/8
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(2)
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
HBFILTER_B: Select half-bandwidth filter at DDC output of channel B in dual-channel mode
1= Select High-Pass filter at DDC output
0= Select Low-Pass filter at DDC output (Default)
(2)
HBFILTER_A: Select half-bandwidth filter at DDC output of channel A
1= Select High-Pass filter at DDC output
0= Select Low-Pass filter at DDC output (Default)
EN_NCO: Enable NCO of DDC1
1= Enabled
0= Disabled (Default)
(3, 4)
EN_AMPDITH: Enable amplitude dithering for NCO
1= Enabled
0= Disabled (Default)
(3, 4)
EN_PHSDITH: Enable phase dithering for NCO
1= Enabled
0= Disabled (Default)
EN_LFSR: Enable linear feedback shift register (LFSR) for amplitude and phase dithering for NCO
1= Enabled
0= Disabled (Default)
(5)
EN_DDC_FS/8: Enable NCO for the DDC2 to center the DDC output signal to be around f /8/DER
S
1= Enabled
0= Disabled (Default)
EN_DDC1: Enable digital down converter 1 (DDC1)
(6)
1= Enabled
0= Disabled (Default)
Note 1:
2:
This register is used for single-, dual- and octal-channel modes when CW feature is enabled (8CH_CW = 1).
This filter includes a decimation of 2.
-Single-channel mode: HBFILTER_A is used.
-Dual-channel mode: Both HBFILTER_A and HBFILTER_B are used.
This requires the LFSR to be enabled: EN_LFSR=1
EN_AMPDITH = 1and EN_PHSDITH = 1are recommended for the best performance.
DER is the decimation rate defined by FIR A or FIR B filter. If up-converter is not enabled (disabled), output is I/Q data.
DDC and NCO are enabled. For DDC function, bits 0, 2 and 5 need to be enabled all together.
3:
4:
5:
6:
2020 Microchip Technology Inc.
DS20006382A-page 104
MCP37D31-80 AND MCP37D21-80
REGISTER 5-41:
ADDRESS 0X81 – DIGITAL DOWN-CONVERTER CONTROL 2
R/W-0
FDR_BAND
bit 7
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
EN_DDC2
GAIN_HBF_DDC
SEL_FDR
EN_DSPP_8
8CH_CW
GAIN_8CH<1:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
FDR_BAND: Select 1st or 2nd Nyquist band
1= 2nd Nyquist band
0= 1st Nyquist band (Default)
EN_DDC2: Enable DDC2 after the digital half-band filter (HBF) in DDC.
1= Enabled
0= Disabled (Default)
(1)
GAIN_HBF_DDC: Gain selection for the output of the digital half-band filter (HBF) in DDC
1= x2
0= x1 (Default)
SEL_FDR: Select fractional delay recovery (FDR)
1= FDR for 8-channel
0= FDR for dual-channel (Default)
(2)
EN_DSPP_8: Enable digital signal post-processing (DSPP) features for 8-channel operation
1= Enabled
0= Disabled (Default)
(2, 3)
8CH_CW: Enable CW mode in octal-channel mode
1= Enabled
0= Disabled (Default)
GAIN_8CH<1:0>: Select gain factor for CW signal in octal-channel modes.
11= x8, 10= x4, 01= x2, 00= x1 (Default)
Note 1:
2:
See Section 4.8.2, "Decimation Filters".
By enabling this bit, the phase offset corrections in Addresses 0x086 – 0x095 (Registers 5-46 – 5-61) are also enabled.
EN_DSPP_8 is a global setting bit to enable SEL_FDR and LVDS_8CH bits (Address 0x62 - Register 5-20).
When CW mode is enabled, the ADC output is the result of the summation (addition) of all eight channels’ data after each
3:
channel’s digital phase offset, digital gain, and digital offset are controlled using the Addresses 0x86 - 0xA7 (Registers 5-46 to
5-78). The result is similar to the beamforming in the phased-array sensors.
DS20006382A-page 105
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-42:
ADDRESS 0X82 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<7:0>
bit 7
bit 0
bit 0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
NCO_TUNE <7:0>: Lower byte of NCO_TUNE<31:0>
0000-0000= DC (0 Hz) when NCO_TUNE<31:0> = 0x00000000(Default)
Note 1:
See Note 1 and Note 2 in Address 0x85 (Register 5-45).
REGISTER 5-43:
ADDRESS 0X83 – NUMERICALLY CONTROLLED OSCILLATOR TUNING
(MIDDLE-LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<15:8>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
NCO_TUNE<15:8>: Middle lower byte of NCO_TUNE<31:0>
0000-0000= Default
Note 1:
See Note 1 and Note 2 in Address 0x85 (Register 5-45).
REGISTER 5-44:
ADDRESS 0X84 – NUMERICALLY CONTROLLED OSCILLATOR TUNING
(MIDDLE-UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<23:16>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
NCO_TUNE<23:16>: Middle upper byte of NCO_TUNE<31:0>
0000-0000= Default
Note 1:
See Note 1 and Note 2 in Address 0x85 (Register 5-45).
2020 Microchip Technology Inc.
DS20006382A-page 106
MCP37D31-80 AND MCP37D21-80
REGISTER 5-45:
ADDRESS 0X85 – NUMERICALLY CONTROLLED OSCILLATOR TUNING (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
NCO_TUNE<31:24>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
NCO_TUNE<31:24>: Upper byte of NCO_TUNE<31:0>
1111-1111= f if NCO_TUNE<31:0> = 0xFFFF FFFF
S
• • •
0000-0000= Default
Note 1:
2:
This Register is used only when DDC is enabled: EN_DDC1 = 1in Address 0x80 (Register 5-40). See Section 4.8.3.3,
"Numerically Controlled Oscillator (NCO)" for the details of NCO.
32
NCO frequency = (NCO_TUNE<31:0>/2 ) x f , where f is the sampling clock frequency.
S
S
REGISTER 5-46:
ADDRESS 0X86 – CH0 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2,3)
bit 7-0
CH0_NCO_PHASE<7:0>: Lower byte of CH0_NCO_PHASE<15:0>
1111-1111= 1.4° when CH0_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
This register has an effect when the following modes are used:
- CW with DDC mode in octal-channel mode
- Single and dual-channel mode with DDC.
st
2:
3:
CH0 is the 1 channel selected by CH_ORDER<23:0>.
16
CH(n)_NCO_PHASE<15:0> = 2 x Phase Offset Value/360.
DS20006382A-page 107
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-47:
ADDRESS 0X87: CH0 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH0_NCO_PHASE<15:8>: Upper byte of CH0_NCO_PHASE<15:0>
1111-1111= 359.995° when CH0_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH0_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46.
REGISTER 5-48:
ADDRESS 0X88 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH1_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH1_NCO_PHASE<7:0>: Lower byte of CH1_NCO_PHASE<15:0>
1111-1111= 1.4° when CH1_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-49:
ADDRESS 0X89 – CH1 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH1_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH1_NCO_PHASE <15:8>: Upper byte of CH1_NCO_PHASE<15:0>
1111-1111= 359.995° when CH1_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH1_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH1 is the 2nd channel selected by CH_ORDER<23:0> bits.
2020 Microchip Technology Inc.
DS20006382A-page 108
MCP37D31-80 AND MCP37D21-80
REGISTER 5-50:
ADDRESS 0X8A – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH2_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH2_NCO_PHASE<7:0>: Lower byte of CH2_NCO_PHASE<15:0>
1111-1111= 1.4° when CH2_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH2_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-51:
ADDRESS 0X8B – CH2 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH2_NCO_PHASE<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH2_NCO_PHASE <15:8>: Upper byte of CH2_NCO_PHASE<15:0>
1111-1111= 359.995° when CH2_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH2_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH2 is the 3rd channel selected by CH_ORDER<23:0> bits.
REGISTER 5-52:
ADDRESS 0X8C – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH3_NCO_PHASE<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH3_NCO_PHASE<7:0>: Lower byte of CH3_NCO_PHASE<15:0>
1111-1111= 1.4° when CH3_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH3_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
DS20006382A-page 109
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-53:
ADDRESS 0X8D – CH3 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH3_NCO_PHASE<15:8>
bit 7
bit 0
bit 0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH3_NCO_PHASE <15:8>: Upper byte of CH3_NCO_PHASE<15:0>
1111-1111= 359.995° when CH3_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH3_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH3 is the 4th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-54:
ADDRESS 0X8E – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH4_NCO_PHASE<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH4_NCO_PHASE<7:0>: Lower byte of CH4_NCO_PHASE<15:0>
1111-1111= 1.4° when CH4_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH4_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH4 is the 5th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-55:
ADDRESS 0X8F – CH4 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH4_NCO_PHASE<15:8>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH4_NCO_PHASE <15:8>: Upper byte of CH4_NCO_PHASE<15:0>
1111-1111= 359.995° when CH4_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH4_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH4 is the 5th channel selected by CH_ORDER<23:0> bits.
2020 Microchip Technology Inc.
DS20006382A-page 110
MCP37D31-80 AND MCP37D21-80
REGISTER 5-56:
ADDRESS 0X90 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH5_NCO_PHASE<7:0>
bit 7
bit 0
bit 0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH5_NCO_PHASE<7:0>: Lower byte of CH5_NCO_PHASE<15:0>
1111-1111= 1.4° when CH5_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-57:
ADDRESS 0X91 – CH5 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH5_NCO_PHASE<15:8>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH5_NCO_PHASE <15:8>: Upper byte of CH5_NCO_PHASE<15:0>
1111-1111= 359.995° when CH5_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH5_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH5 is the 6th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-58:
ADDRESS 0X92 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH6_NCO_PHASE<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH6_NCO_PHASE<7:0>: Lower byte of CH6_NCO_PHASE<15:0>
1111-1111= 1.4° when CH6_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits.
DS20006382A-page 111
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-59:
ADDRESS 0X93 – CH6 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH6_NCO_PHASE<15:8>
bit 7
bit 0
bit 0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH6_NCO_PHASE <15:8>: Upper byte of CH6_NCO_PHASE<15:0>
1111-1111= 359.995° when CH6_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH6_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH6 is the 7th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-60:
ADDRESS 0X94 – CH7 NCO PHASE OFFSET IN CW OR DDC MODE (LOWER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH7_NCO_PHASE<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH7_NCO_PHASE<7:0>: Lower byte of CH7_NCO_PHASE<15:0>
1111-1111= 1.4° when CH7_NCO_PHASE<15:0> = 0x00FF
• • •
0000-0000= 0° when CH7_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1:
See Note 1 - Note 3 in Register 5-46. CH7 is the 8th channel selected by CH_ORDER<23:0> bits.
REGISTER 5-61:
ADDRESS 0X95 – CH7 NCO PHASE OFFSET IN CW OR DDC MODE (UPPER BYTE)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH7_NCO_PHASE<15:8>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH7_NCO_PHASE <15:8>: Upper byte of CH7_NCO_PHASE<15:0>
1111-1111= 359.995° when CH7_NCO_PHASE<15:0> = 0xFFFF
• • •
0000-0000= 0° when CH7_NCO_PHASE<15:0> = 0x0000 (Default)
Note 1: See Note 1 - Note 3 in Register 5-46. CH7 is the 8th channel selected by CH_ORDER<23:0> bits.
2020 Microchip Technology Inc.
DS20006382A-page 112
MCP37D31-80 AND MCP37D21-80
REGISTER 5-62:
ADDRESS 0X96 – CH0 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH0_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH0_DIG_GAIN<7:0>: Digital gain setting for channel 0
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
st
Note 1:
2:
CH0 is the 1 channel selected by CH_ORDER<23:0>.
Max = 0x7F(3.96875), Min = 0x80 (-4), Step size = 0x01 (0.03125). Bits from 0x81-0xFF are two’s complementary of 0x00-
0x80. Negative gain setting inverts output. See Addresses 0x7D - 0x7F (Registers 5-37 – 5-39) for channel selection.
DS20006382A-page 113
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-63:
ADDRESS 0X97 – CH1 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH1_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH1_DIG_GAIN<7:0>: Digital gain setting for channel 1
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
nd
Note 1:
2:
CH1 is the 2 channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
2020 Microchip Technology Inc.
DS20006382A-page 114
MCP37D31-80 AND MCP37D21-80
REGISTER 5-64:
ADDRESS 0X98 – CH2 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH2_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH2_DIG_GAIN<7:0>: Digital gain setting for channel 2
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
rd
Note 1:
2:
CH2 is the 3 channel selected by CH_ORDER<23:0> bits.
See Note 2 in Register 5-62.
DS20006382A-page 115
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-65:
ADDRESS 0X99 – CH3 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH3_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH3_DIG_GAIN<7:0>: Digital gain setting for channel 3
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
th
Note 1: CH3 is the 4 channel selected by CH_ORDER<23:0> bits.
2: See Note 2 in Register 5-62.
2020 Microchip Technology Inc.
DS20006382A-page 116
MCP37D31-80 AND MCP37D21-80
REGISTER 5-66:
ADDRESS 0X9A – CH4 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH4_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH4_DIG_GAIN<7:0>: Digital gain setting for channel 4
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
th
Note 1:
2:
CH4 is the 5 channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
DS20006382A-page 117
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-67:
ADDRESS 0X9B – CH5 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH5_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH5_DIG_GAIN<7:0>: Digital gain setting for channel 5
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
th
Note 1:
2:
CH5 is the 6 channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
2020 Microchip Technology Inc.
DS20006382A-page 118
MCP37D31-80 AND MCP37D21-80
REGISTER 5-68:
ADDRESS 0X9C – CH6 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH6_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH6_DIG_GAIN<7:0>: Digital gain setting for channel 6
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
th
Note 1:
2:
CH6 is the 7 channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
DS20006382A-page 119
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-69:
ADDRESS 0X9D – CH7 DIGITAL GAIN
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-0
R/W-0
CH7_DIG_GAIN<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1,2)
bit 7-0
CH7_DIG_GAIN<7:0>: Digital gain setting for channel 7
1111-1111= -0.03125
1111-1110= -0.0625
1111-1101= -0.09375
1111-1100= -0.125
• • •
1000-0011= -3.90625
1000-0010= -3.9375
1000-0001= -3.96875
1000-0000= -4
0111-1111= 3.96875 (MAX)
0111-1110= 3.9375
0111-1101= 3.90625
0111-1100= 3.875
• • •
0011-1100= 1.875 (Default)
• • •
0000-0011= 0.09375
0000-0010= 0.0625
0000-0001= 0.03125
0000-0000= 0.0
th
Note 1:
2:
CH7 is the 8 channel selected by CH_ORDER<23:0>.
See Note 2 in Register 5-62.
2020 Microchip Technology Inc.
DS20006382A-page 120
MCP37D31-80 AND MCP37D21-80
REGISTER 5-70:
ADDRESS 0X9E – CH0 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH0_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH0_DIG_OFFSET <7:0>: Digital offset setting bits for channel 0
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1:
See Table 4-18 for the corresponding channel. Offset value is two’s complement. This value is multiplied by DIG_OFFSET_-
WEIGHT<1:0> in Address 0xA7 (Register 5-78).
REGISTER 5-71:
ADDRESS 0X9F – CH1 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH1_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH1_DIG_OFFSET <7:0>: Digital offset setting bits for channel 1
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1:
See Note 1 in Register 5-70.
REGISTER 5-72:
ADDRESS 0XA0 – CH2 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH2_DIG_OFFSET<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH2_DIG_OFFSET <7:0>: Digital offset setting bits for channel 2
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1:
See Note 1 in Register 5-70.
DS20006382A-page 121
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-73:
ADDRESS 0XA1 – CH3 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH3_DIG_OFFSET<7:0>
bit 7
bit 0
bit 0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH3_DIG_OFFSET <7:0>: Digital offset setting bits for channel 3
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1:
See Note 1 in Register 5-70.
REGISTER 5-74:
ADDRESS 0XA2 – CH4 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH4_DIG_OFFSET<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH4_DIG_OFFSET <7:0>: Digital offset setting bits for channel 4
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1: See Note 1 in Register 5-70.
REGISTER 5-75:
ADDRESS 0XA3 – CH5 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH5_DIG_OFFSET<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH5_DIG_OFFSET <7:0>: Digital offset setting bits for channel 5
1111-1111= 0x01 x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0xFF x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1: See Note 1 in Register 5-70.
2020 Microchip Technology Inc.
DS20006382A-page 122
MCP37D31-80 AND MCP37D21-80
REGISTER 5-76:
ADDRESS 0XA4 – CH6 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
CH6_DIG_OFFSET<7:0>
bit 7
bit 0
bit 0
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH6_DIG_OFFSET <7:0>: Digital offset setting bits for channel 6
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1:
See Note 1 in Register 5-70.
REGISTER 5-77:
ADDRESS 0XA5 – CH7 DIGITAL OFFSET
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CH7_DIG_OFFSET<7:0>
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CH7_DIG_OFFSET <7:0>: Digital offset setting bits for channel 7
1111-1111= 0xFF x DIG_OFFSET_WEIGHT<1:0>
• • •
0000-0001= 0x01 x DIG_OFFSET_WEIGHT<1:0>
0000-0000= 0 (Default)
Note 1:
See Note 1 in Register 5-70.
REGISTER 5-78:
ADDRESS 0XA7 – DIGITAL OFFSET WEIGHT CONTROL
R/W-0
R/W-1
FCB<5:3>
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
DIG_OFFSET_WEIGHT<1:0>
FCB<2:0>
bit 7
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
-n = Value at POR
x = Bit is unknown
bit 7-5
bit 4-3
FCB<5:3>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
(1)
DIG_OFFSET_WEIGHT<1:0>: Control the weight of the digital offset settings
11= 2 LSb x Digital Gain
10= LSb x Digital Gain
01= LSb/2 x Digital Gain
00= LSb/4 x Digital Gain, (Default)
bit 2-0
FCB<2:0>: Factory-Controlled Bits. This is not for the user. Do not change default settings.
Note 1:
This bit setting is used for the digital offset setting registers in Addresses 0x9E - 0xA7 (Registers 5-70 – 5-78).
DS20006382A-page 123
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
REGISTER 5-79:
ADDRESS 0XC0 – CALIBRATION STATUS INDICATION
R-0
ADC_CAL_STAT
bit 7
R-0
R-0
R-0
R-0
R-0
R-0
R-0
FCB<6:0>
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 7
ADC_CAL_STAT: Power-up auto-calibration status indication flag bit
1= Device power-up calibration is completed
0= Device power-up calibration is not completed
bit 6-0
FCB<6:0>: Factory-Controlled Bits. These bits are read only, and have no meaning for the user.
REGISTER 5-80:
ADDRESS 0XD1 – PLL CALIBRATION STATUS AND PLL DRIFT STATUS INDICATION
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
FCB<0>
bit 0
FCB<4:3>
PLL_CAL_STAT
FCB<2:1>
PLL_VCOL_STAT
PLL_VCOH_STAT
bit 7
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-6
bit 5
FCB<4:3>: Factory-controlled bits. These bits are read only, and have no meaning for the user.
(1)
PLL_CAL_STAT: PLL auto-calibration status indication flag bit
1=
0=
Complete: PLL auto-calibration is completed
Incomplete: PLL auto-calibration is not completed
bit 4-3
bit 2
FCB<2:1>: Factory-controlled bits. These bits are read only, and have no meaning for the user.
PLL_VCOL_STAT: PLL drift status indication bit
1= PLL drifts out of lock with low VCO frequency
0= PLL operates as normal
bit 1
PLL_VCOH_STAT: PLL drift status indication bit
1= PLL drifts out of lock with high VCO frequency
0= PLL operates as normal
bit 0
FCB<0>: Factory-Controlled Bit. This bit is readable, but has no meaning for the user.
Note 1: See PLL_CAL_TRIG bit setting in Address 0x6B (Register 5-27).
2020 Microchip Technology Inc.
DS20006382A-page 124
MCP37D31-80 AND MCP37D21-80
REGISTER 5-81:
ADDRESS 0X15C – CHIP ID (LOWER BYTE)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
CHIP_ID<7:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CHIP_ID<7:0>: Device identification number. Lower byte of the CHIP ID<15:0>
Note 1:
Read-only register. Preprogrammed at the factory for internal use.
Example: MCP37D31-80: ‘0000 1010 0110 0000’
MCP37D21-80: ‘0000 1010 0100 0000’
MCP37D11-80: ‘0000 1010 0010 0000’
REGISTER 5-82:
ADDRESS 0X15D – CHIP ID (UPPER BYTE)
R-x
R-x
R-x
R-x
R-x
R-x
R-x
R-x
CHIP_ID<15:8>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
(1)
bit 7-0
CHIP_ID<15:8>: Device identification number. Lower byte of the CHIP ID<15:0>
Note 1:
See Note 1 in Register 5-81.
DS20006382A-page 125
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Graphical User Interface (GUI) software for ADC
configuration and evaluation. Figure 6-1 and Figure 6-
2 show this evaluation tool. This evaluation platform
allows users to quickly evaluate the ADC’s
performance for their specific application requirements.
6.0
DEVELOPMENT SUPPORT
Microchip offers a high-speed ADC evaluation platform
which can be used to evaluate Microchip’s high-speed
ADC products. The platform consists of an MCP37D31/
21-80 evaluation board (EV55U36A), an FPGA-based
data capture card board (ADM00506), and PC-based
More
information
is
available
at
http://
www.microchip.com.
80 MHz Clock Signal Source
ADM00506
(High-Speed Pipelined ADC Data Capture Card)
EV55U36A
(MCP37D31/21-80 EV Board)
FIGURE 6-1:
MCP37D31-80 Evaluation Kit.
FIGURE 6-2:
PC-Based Graphical User Interface Software.
2020 Microchip Technology Inc.
DS20006382A-page 126
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 127
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Pipeline Delay (LATENCY)
7.0
TERMINOLOGY
LATENCY is the number of clock cycles between the
initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is
available after the pipeline delay plus the output delay
after that sample is taken. New data is available at
every clock cycle, but the data lags the conversion by
the pipeline delay plus the output delay. Latency is
increased if digital signal post-processing is used.
Analog Input Bandwidth (Full-Power
Bandwidth)
The analog input frequency at which the spectral power
of the fundamental frequency (as determined by FFT
analysis) is reduced by 3 dB.
Aperture Delay or Sampling Delay
This is the time delay between the rising edge of the
input sampling clock and the actual time at which the
sampling occurs.
Clock Pulse Width and Duty Cycle
The clock duty cycle is the ratio of the time the clock
signal remains at a logic high (clock pulse width) to one
clock period. Duty cycle is typically expressed as a
percentage. A perfect differential sine-wave clock
results in a 50% duty cycle.
Aperture Uncertainty
The sample-to-sample variation in aperture delay.
Aperture Delay Jitter
Differential Nonlinearity
(DNL, No Missing Codes)
The variation in the aperture delay time from
conversion to conversion. This random variation will
result in noise when sampling an AC input. The
signal-to-noise ratio due to the jitter alone will be:
An ideal ADC exhibits code transitions that are exactly
1 LSb apart. DNL is the deviation from this ideal value.
No missing codes to 16-bit resolution indicates that all
65,536 codes must be present over all the operating
conditions.
EQUATION 7-1:
SNR
= –20log2 f t
IN JITTER
Integral Nonlinearity (INL)
JITTER
INL is the maximum deviation of each individual code
from an ideal straight line drawn from negative full
scale through positive full scale.
Calibration Algorithms
This device utilizes two patented analog and digital
calibration algorithms, Harmonic Distortion Correction
(HDC) and DAC Noise Cancellation (DNC), to improve
the ADC performance. The algorithms compensate
various sources of linear impairments such as
capacitance mismatch, charge injection error and finite
gain of operational amplifiers. These algorithms
execute in both power-up sequence (foreground) and
background mode:
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the power of the fundamental (PS) to
the noise floor power (PN), below the Nyquist frequency
and excluding the power at DC and the first nine
harmonics.
EQUATION 7-2:
P
• Power-Up Calibration: The calibration is
conducted within the first 227 clock cycles after
power-up. The user needs to wait this Power-Up
Calibration period after the device is powered-up
for an accurate ADC performance.
S
SNR = 10log -------
P
N
SNR is either given in units of dBc (dB to carrier) when
the absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
the fundamental is extrapolated to the converter
full-scale range.
• Background Calibration: This calibration is
conducted in the background while the ADC
performs conversions. The update rate is about
every 230 clock cycles.
Channel Crosstalk
This is a measure of the internal coupling of a signal
from an adjacent channel into the channel of interest in
the multi-channel mode. It is measured by applying a
full-scale input signal in the adjacent channel.
Crosstalk is the ratio of the power of the coupling signal
(as measured at the output of the channel of interest)
to the power of the signal applied at the adjacent
channel input. It is typically expressed in dBc.
2020 Microchip Technology Inc.
DS20006382A-page 128
-
SFDR is the ratio of the power of the fundamental to the
highest other spectral component (either spur or
harmonic). SFDR is typically given in units of dBc (dB
to carrier) or dBFS.
MCP37D31-80 AND MCP37D21-80
Signal-to-Noise and Distortion (SINAD)
Maximum Conversion Rate
SINAD is the ratio of the power of the fundamental (PS)
to the power of all the other spectral components
including noise (PN) and distortion (PD) below the
Nyquist frequency, but excluding DC:
The maximum clock rate at which parametric testing is
performed.
Minimum Conversion Rate
The minimum clock rate at which parametric testing is
performed.
EQUATION 7-3:
P
S
SINAD = 10log ---------------------
P
+ P
Spurious-Free Dynamic Range (SFDR)
D
N
SNR
–---------
10
THD
–------------
10
= –10log 10
– 10
SINAD is either given in units of dBc (dB to carrier)
when the absolute power of the fundamental is used as
the reference, or dBFS (dB to full-scale) when the
power of the fundamental is extrapolated to the
converter full-scale range.
Total Harmonic Distortion (THD)
THD is the ratio of the power of the fundamental (PS) to
the summed power of the first 13 harmonics (PD).
Effective Number of Bits (ENOB)
EQUATION 7-5:
P
The effective number of bits for a sine wave input at a
given input frequency can be calculated directly from its
measured SINAD using the following formula:
S
THD = 10log -------
P
D
THD is typically given in units of dBc (dB to carrier).
THD is also shown by:
EQUATION 7-4:
SINAD – 1.76
ENOB = ----------------------------------
6.02
EQUATION 7-6:
2
2
2
3
2
4
2
n
V + V + V + + V
Gain Error
THD = –20log-----------------------------------------------------------------
2
V
Gain error is the deviation of the ADC’s actual input
full-scale range from its ideal value. The gain error is
given as a percentage of the ideal input full-scale
range.
1
Where:
V1 = RMS amplitude of the
fundamental frequency
Gain error is usually expressed in LSb or as a
percentage of full-scale range (%FSR).
V1 through Vn = Amplitudes of the second
through nth harmonics
Gain-Error Drift
Two-Tone Intermodulation Distortion
(Two-Tone IMD, IMD3)
Gain-error drift is the variation in gain-error due to a
change in ambient temperature, typically expressed in
ppm/°C.
Two-tone IMD is the ratio of the power of the
fundamental (at frequencies fIN1 and fIN2) to the power
of the worst spectral component at either frequency
2fIN1 – fIN2 or 2fIN2 – fIN1. Two-tone IMD is a function of
the input amplitudes and frequencies (fIN1 and fIN2). It
is either given in units of dBc (dB to carrier) when the
absolute power of the fundamental is used as the
reference, or dBFS (dB to full-scale) when the power of
the fundamental is extrapolated to the ADC full-scale
range.
Offset Error
The major carry transition should occur for an analog
value of 50% LSb below AIN+ = AIN−. Offset error is
defined as the deviation of the actual transition from
that point.
Temperature Drift
The temperature drift for offset error and gain error
specifies the maximum change from the initial (+25°C)
value to the value across the TMIN to TMAX range.
DS20006382A-page 129
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
Common-Mode Rejection Ratio (CMRR)
Common-mode rejection is the ability of a device to
reject a signal that is common to both sides of a
differential input pair. The Common-mode signal can
be an AC or DC signal or a combination of the two.
CMRR is measured using the ratio of the differential
signal gain to the Common-mode signal gain and
expressed in dB with the following equation:
EQUATION 7-7:
A
DIFF
CMRR = 20log ------------------
A
CM
Where:
ADIFF = Output Code/Differential Voltage
ADIFF = Output Code/Common-mode Voltage
2020 Microchip Technology Inc.
DS20006382A-page 130
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 131
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
8.0
8.1
PACKAGING INFORMATION
Package Marking Information
128-Ball TFBGA
Examples:
Microchip
MCP37D21
80/TE
1
3
e
YYWWNNN
Microchip
MCP37D31
80/TE
^1
e
3
YYWWNNN
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
1
3
e
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
1
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2020 Microchip Technology Inc.
DS20006382A-page 132
MCP37D31-80 AND MCP37D21-80
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
NOTE 1
E
(DATUM B)
(DATUM A)
2X
0.15 C
2X
0.15 C
TOP VIEW
A
0.10 C
C
SEATING
PLANE
A2
A1
0.10 C
SIDE VIEW
D1
eD
L
K
J
H
G
F
eE
E1
E
D
C
B
A
NOTE 1
1
2
3
4
5
6
7
8
9 10 11
DETAIL A
A1 BALL PAD CORNER
BOTTOM VIEW
Microchip Technology Drawing C04-212-TE Rev C Sheet 1 of 2
DS20006382A-page 133
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
121X Øb
0.15
0.08
C A B
C
DETAIL A
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Terminals
Pitch
Pitch
Overall Height
Standoff
Cap Thickness
Overall Width
Overall Pitch
Overall Length
Overall Pitch
Terminal Diameter
N
eE
eD
A
A1
A2
E
E1
D
D1
b
121
0.65 BSC
0.65 BSC
-
0.32
0.45
8.00 BSC
6.50 BSC
8.00 BSC
6.50 BSC
0.40
-
1.08
-
0.50
0.21
0.40
0.35
0.45
Notes:
1. Terminal A1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-212-TE Rev C Sheet 2 of 2
2020 Microchip Technology Inc.
DS20006382A-page 134
MCP37D31-80 AND MCP37D21-80
121-Ball Thin Fine Pitch Ball Grid Array (TE) - 8x8 mm Body [TFBGA]
System In Package
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E
C2
121X ØB
E
C1
SILK SCREEN
RECOMMENDED LAND PATTERN
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Contact Pitch
Contact Pad Spacing
Contact Pad Spacing
E
C1
C2
0.65 BSC
6.50
6.50
Contact Pad Diameter (X121)
B
0.35
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2212-TE Rev C
DS20006382A-page 135
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
APPENDIX A: REVISION HISTORY
Revision A (June 2020)
• Original release of this document.
2020 Microchip Technology Inc.
DS20006382A-page 136
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 137
2020 Microchip Technology Inc.
MCP37D31-80 AND MCP37D21-80
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
Examples:
-XXX
X
/XX
PART NO.
[X]
a) MCP37D31-80E/TE:
121 LD TFBGA,
Tube or Tray
Extended temperature,
80 Msps, 16-bit
Sample Temperature Package
Rate
Device Tape and Reel
Option
Range
b) MCP37D31T-80E/TE:
c) MCP37D21-80E/TE:
d) MCP37D21T-80E/TE:
121 LD TFBGA,
Tape and Reel,
Extended temperature,
80 Msps, 16-bit
Device:
MCP37D31-80: 16-Bit, 80 Msps High-Precision Pipelined ADC
with Configurable 8-Channel Input MUX, and
with built-in Digital Signal Post Processing
features that include Digital Down-Converter
(DDC), Decimation Filter, Phase/Gain/Offset
Adjustment per Channel, and CW
121 LD TFBGA,
Tube or Tray
Extended temperature,
80 Msps, 14-bit
Beamforming.
121 LD TFBGA,
Tape and Reel,
Extended temperature,
80 Msps, 14-bit
MCP37D21-80: 14-Bit, 80 Msps High-Precision Pipelined ADC
with Configurable 8-Channel Input MUX, and
with built-in Digital Signal Post Processing
features that include Digital Down-Converter
(DDC), Decimation Filter, Phase/Gain/Offset
Adjustment per Channel, and CW
Beamforming.
Tape and
Reel Option:
Blank
T
=
=
Standard packaging (tube or tray)
Tape and Reel(1)
Sample Rate: 80
= 80 Msps
Temperature
Range:
E
= -40C to +125C (Extended)
Package:
TE
=
Ball Plastic Thin Profile Fine Pitch Ball Grid Array -
8x8x1.08 mm Body (TFBGA), 121-Lead
Note 1:
Tape and Reel identifier appears only in the catalog part number
description. This identifier is used for ordering purposes and is not
printed on the device package. Check with your Microchip Sales
Office for package availability with the Tape and Reel option.
2020 Microchip Technology Inc.
DS20006382A-page 138
MCP37D31-80 AND MCP37D21-80
NOTES:
DS20006382A-page 139
2020 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
are registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
APT, ClockWorks, The Embedded Control Solutions Company,
EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2020, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-6323-8
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2020 Microchip Technology Inc.
DS20006382A-page 140
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
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Tel: 91-80-3090-4444
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Tel: 45-4485-5910
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Tel: 358-9-4520-820
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Web Address:
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Fax: 317-773-5453
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Tel: 86-756-3210040
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Fax: 44-118-921-5820
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20006382A-page 141
2020 Microchip Technology Inc.
02/28/20
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