MCP39F511N [MICROCHIP]
Dual-Channel, Single-Phase Power-Monitoring IC with Calculation;
| 型号： | MCP39F511N |
| 厂家： | 
MICROCHIP |
| 描述： | Dual-Channel, Single-Phase Power-Monitoring IC with Calculation 监控 |
| 文件： | 总61页 (文件大小：889K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP39F511N
Dual-Channel, Single-Phase Power-Monitoring IC with Calculation
Features
Description
• Power Monitoring of Two Loads with accuracy of
0.5% across 4000:1 Dynamic Range
The MCP39F511N is a highly integrated, complete
dual-channel single-phase power-monitoring IC
designed for real-time measurement of input power for
dual-socket wall outlets, power strips, and consumer
and industrial applications. It includes dual-channel
• Built-in Calculations on Fast 16-bit Processing
Core:
- Active, Reactive, Apparent Power
- True RMS Current, RMS Voltage
- Line Frequency, Power Factor
24-bit
Delta-Sigma ADCs
for
dual-current
measurements,
a
10-bit SAR ADC for voltage
measurement, a 16-bit calculation engine, EEPROM
and a flexible two-wire interface. An integrated low-drift
voltage reference with 10 ppm/°C in addition to 94.5 dB
of SINAD performance on each measurement channel
allow for better than 0.5% accurate designs across a
4000:1 dynamic range.
• 64-bit Wide Import and Export Active Energy
Accumulation Registers Per Channel
• 64-bit Four Quadrant Reactive Energy
Accumulation Registers Per Channel
• Signed Active and Reactive Power Outputs
• Dedicated Zero Crossing Detection (ZCD) Pin
Output with Less than 200 µs Latency
Package Types
MCP39F511N
5x5 QFN*
• Dedicated PWM Output Pin with Programmable
Frequency and Duty Cycle
• Automatic Event Pin Control through Fast Voltage
Surge Detection
- Less than 5 ms Delay
• Two-Wire Serial Protocol with Selectable Baud
Rate up to 115.2 kbps using Universal
Asynchronous Receiver/Transmitter (UART)
28 27 26 25 24 23 22
1
2
3
4
AGND
EVENT1
21
NC
NC
20 V+
19 I2+
• Fast Calibration Routines and Simplified
Command Protocol
• 512 Bytes User-Accessible EEPROM through
Page Read/Write Commands
EP
29
UART_RX
COMMONA
18
I2-
5
6
7
17 I1-
• Low-Drift Internal Voltage Reference, 10 ppm/°C
Typical
I1+
16
15
OSCI
EVENT2
OSCO
• 28-lead 5x5 QFN Package
8
9
10 11 12
13 14
• Extended Temperature Range: -40°C to +125°C
Applications
• Wall Socket (Dual Plug) Power Monitoring
• Power Monitoring for Home Automation
• Industrial Lighting Power Monitoring
*Includes Exposed Thermal Pad (EP); see Table 3-1.
• Real-Time Measurement of Input Power for
AC-DC Supplies
• Intelligent Power Distribution Units
2015-2018 Microchip Technology Inc.
DS20005473B-page 1
MCP39F511N
Functional Block Diagram
A
AV
D
DV
DD
GND
DD
GND
Timing
OSCI
Generation
OSCO
Internal
Oscillator
UART_TX
UART_RX
UART
Serial
Interface
24-bit Delta-Sigma
Multi-level
Modulator ADC
I1+
I1-
+
-
PGA
16-BIT
PWM
CORE
FLASH
24-bit Delta-Sigma
Multi-level
Modulator ADC
I2+
I2-
EVENT1
EVENT2
+
-
PGA
Calculation
Engine
(CE)
Digital Outputs
ZCD
10-bit SAR
ADC
V+
2015-2018 Microchip Technology Inc.
DS20005473B-page 2
MCP39F511N
Typical Application
+3.3V
N
L
10
0.1 µF
1 µF
1 k
0.1 µF
AV
2 m
DV
RESET
DD
DD
I1-
REFIN/OUT+
33 nF
0.1 µF
1 k
I1+
I2-
UART_TX
to MCU
UART
33 nF
2 m
1 k
UART_RX
33 nF
to MCU
UART
1 k
(OPTIONAL)
I2+
V+
MCP39F511N
33 nF
+3.3V
NC
NC
NC
NC
N.C. Leave Floating
Connect on PCB
51 k
47µ F
499 k 499 k
5.1 k
1 k
DR
51 k
33 nF
COMMON
A,B
33 nF
EVENT1
EVENT2
N
L
ZCD
OSCO
OSCI
PWM
8 MHz
A
D
GND
GND
22 pF
22 pF
(OPTIONAL)
+3.3V
0.47µF
470
MCP1754
0.01 µF
470 µF
A
GND
D
GND
Note:
The external sensing components shown here, the 2 mΩ shunts, two 499 kΩ and 5.1 kΩ resistor for the
200:1 voltage divider, are specifically chosen to match the default values for the calibration registers
defined in Section 6.0 “Register Descriptions”. By choosing low-tolerance components of these
values (e.g. 1% tolerance), measurement accuracy in the 2-3% range can be achieved with zero
calibration. See Section 9.0 “MCP39F511N Calibration” for more information.
2015-2018 Microchip Technology Inc.
DS20005473B-page 3
MCP39F511N
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operation listings of this specification is
not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
DV ..................................................................-0.3 to +4.5V
DD
AV ...................................................................-0.3 to +4.0V
DD
Digital inputs and outputs w.r.t. A
...............-0.3V to +4.0V
GND
Analog Inputs (I+,I-,V+,V-) w.r.t. A
....................-2V to +2V
GND
V
input w.r.t. A
......................... ....-0.6V to AV +0.6V
REF
GND DD
Maximum Current out of D
pin ............................. 300 mA
GND
Maximum Current into DV pin ................................ 250 mA
DD
Maximum Output Current Sunk by Digital IO ............... 25 mA
Maximum Current Sourced by Digital IO...................... 25 mA
Storage temperature..................................... -65°C to +150°C
Ambient temperature with power applied ..... -40°C to +125°C
Soldering temperature of leads (10 seconds)............. +300°C
ESD on the analog inputs (HBM,MM) ................ 4.0 kV, 200V
ESD on all other pins (HBM,MM) ....................... 4.0 kV, 200V
1.1
Specifications
ELECTRICAL CHARACTERISTICS
TABLE 1-1:
Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AV
DV = 2.7 to 3.6V,
DD
DD,
T
= -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
A
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Power Measurement
Active Power (Note 1)
P
—
±0.5
—
%
4000:1 Dynamic Range
on Current Channel
(Note 2)
Reactive Power (Note 1)
Apparent Power (Note 1)
Current RMS (Note 1)
Voltage RMS (Note 1)
Q
S
—
—
—
—
±0.5
±1
—
—
—
—
%
%
%
%
4000:1 Dynamic Range
on Current Channel
(Note 2)
4000:1 Dynamic Range
on Current Channel
(Note 2)
IRMS
±1
4000:1 Dynamic Range
on Current Channel
(Note 2)
VRMS
±1
4000:1 Dynamic Range
on Voltage Channel
(Note 2)
Power Factor (Note 1)
Line Frequency (Note 1)
—
—
±1
±1
—
—
%
%
LF
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 16 line cycles, channel 1 or channel 2.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or
TCAL = 320 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: VIN = 1 VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and UART only.
2015-2018 Microchip Technology Inc.
DS20005473B-page 4
MCP39F511N
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AV
DV = 2.7 to 3.6V,
DD
DD,
T
= -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
A
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
Calibration, Calculation and Event Detection Times
2N x (1/fLINE
see
)
Auto-Calibration Time
tCAL
—
—
—
—
ms
ms
Note 3
Note 4
Minimum Time
for Voltage Surge/Sag
Detection
tAC_SASU
Section 7.0
24-Bit Delta-Sigma ADC Performance
Analog Input
Absolute Voltage
VIN
-1
—
1
+1
—
V
Analog Input
Leakage Current
AIN
—
nA
mV
Differential Input
Voltage Range
(I1+ – I1-), -600/GAIN
(I2+ – I2-)
—
+600/GAIN
VREF = 1.2V,
proportional to VREF
Offset Error
VOS
GE
ZIN
-1
—
—
0.5
—
+1
—
+4
—
—
—
—
—
—
—
—
mV
µV/°C
%
Offset Error Drift
Gain Error
-4
Note 5
Gain Error Drift
—
1
ppm/°C
k
Differential Input
Impedance
232
142
72
38
36
33
92
—
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
Note 6
—
k
—
k
—
k
—
k
—
k
Signal-to-Noise
SINAD
94.5
dB
and Distortion Ratio
Total Harmonic Distortion
Signal-to-Noise Ratio
THD
SNR
—
92
—
-106.5
95
-103
—
dBc
dB
Note 6
Note 6
Note 6
Spurious Free
SFDR
111
—
dB
Dynamic Range
Crosstalk
CTALK
—
—
-122
-73
—
—
dB
dB
AC Power
AC PSRR
AVDD and
Supply Rejection Ratio
DVDD = 3.3V + 0.6VPP
,
100 Hz, 120 Hz, 1 kHz
DC Power
Supply Rejection Ratio
DC PSRR
DC CMRR
—
—
-73
—
—
dB
dB
AVDD and DVDD = 3.0 to
3.6V
DC Common
-105
VCM varies
Mode Rejection Ratio
from -1V to +1V
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 16 line cycles, channel 1 or channel 2.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or
T
CAL = 320 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: VIN = 1 VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and UART only.
2015-2018 Microchip Technology Inc.
DS20005473B-page 5
MCP39F511N
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AV
DV = 2.7 to 3.6V,
DD
DD,
T
= -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
A
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
10-Bit SAR ADC Performance for Voltage Measurement
Resolution
NR
VIN
RIN
—
DGND - 0.3
—
10
—
—
—
DVDD + 0.3
2.5
bits
V
Absolute Input Voltage
Recommended
k
Impedance of
Analog Voltage Source
Integral Nonlinearity
Differential Nonlinearity
Gain Error
INL
—
—
—
—
±1
±1
±1
±1
±2
±1.5
±3
LSb
LSb
LSb
LSb
DNL
GERR
EOFF
Offset Error
±2
Clock and Timings
UART Baud Rate
UDB
fMCLK
1.2
-2%
—
—
8
115.2
+2%
15
kbps See Section 3.2 for
protocol details
Master Clock
and Crystal Frequency
MHz
Capacitive Loading
on OSCO pin
COSC2
fINT_OSC
—
2
pF
%
When an external clock is
used to drive the device
Internal Oscillator
Tolerance
—
—
-40°C to +85°C only
(Note 7)
Internal Voltage Reference
Internal Voltage
Reference Tolerance
VREF
-2%
—
1.2
10
+2%
—
V
Temperature Coefficient
TCVREF
ppm/°C TA = -40°C to +85°C,
VREFEXT = 0
Output Impedance
Current, VREF
ZOUTVREF
AIDDVREF
—
—
2
—
—
k
40
µA
Voltage Reference Input
Input Capacitance
—
—
—
10
pF
V
A
+ 1.1V
A
+ 1.3V
GND
Absolute Voltage on
VREF+ Pin
VREF+
GND
Power Specifications
Operating Voltage
AVDD, DVDD
VPOR
2.7
DGND
—
—
3.6
0.7
V
V
DVDD Start Voltage
to Ensure Internal
Power-On Reset Signal
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 16 line cycles, channel 1 or channel 2.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or
TCAL = 320 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6:
VIN = 1 VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and UART only.
2015-2018 Microchip Technology Inc.
DS20005473B-page 6
MCP39F511N
TABLE 1-1:
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply across both channels at AV
DV = 2.7 to 3.6V,
DD
DD,
T
= -40°C to +125°C, MCLK = 4 MHz, PGA GAIN = 1.
A
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
DVDD Rise Rate to
Ensure Internal
SDVDD
0.05
—
—
V/ms 0 – 3.3V in 0.1s, 0 – 2.5V
in 60 ms
Power-on Reset Signal
AVDD Start Voltage to
Ensure Internal
Power-on Reset Signal
VPOR
SAVDD
IDD
AGND
0.042
—
—
—
15
2.1
—
V
AVDD Rise Rate to
Ensure Internal Power-on
Reset Signal
V/ms 0 – 2.4V in 50 ms
Operating Current
Data EEPROM Memory
Cell Endurance
—
mA
EPS
TIWD
100,000
—
—
4
—
—
E/W
ms
Self-Timed
Write Cycle Time
10,000,000
Number of Total
Write/Erase Cycles
Before Refresh
RREF
—
—
E/W
Characteristic Retention
TRETDD
IDDPD
40
—
—
7
—
—
Years Provided no other
specifications are violated
Supply Current during
Programming
mA
Note 1: Calculated from reading the register values with no averaging, single computation cycle with accumulation
interval of 16 line cycles, channel 1 or channel 2.
2: Specification by design and characterization; not production tested.
3: N = Value in the Accumulation Interval Parameter register. The default value of this register is 4 or
TCAL = 320 ms for 50 Hz line.
4: Applies to Voltage Sag and Voltage Surge events only.
5: Applies to all gains. Offset and gain errors depend on the PGA gain setting. See Section 2.0 “Typical
Performance Curves” for typical performance.
6: VIN = 1 VPP = 353 mVRMS @ 50/60 Hz.
7: Variation applies to internal clock and UART only.
2015-2018 Microchip Technology Inc.
DS20005473B-page 7
MCP39F511N
TABLE 1-2:
SERIAL DC CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6 V,
TA = -40°C to +125°C, MCLK = 4 MHz
Characteristic
Sym.
Min.
Typ.
Max.
Units
Test Conditions
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
VIH
VIL
0.8 DVDD
—
—
DVDD
0.2 DVDD
—
V
V
0
VOH
VOL
ILI
3
—
V
IOH = -3.0 mA, VDD = 3.6V
IOL = 4.0 mA, VDD = 3.6V
—
—
—
—
0.4
V
—
1
µA
µA
0.050
0.100
Digital Output pins only
(ZCD, PWM, EVENT1,
EVENT2)
TABLE 1-3:
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD, DVDD = 2.7 to 3.6V.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max.
Units
Conditions
Operating Temperature Range
Storage Temperature Range
TA
TA
-40
-65
—
—
+125
+150
°C
°C
Thermal Package Resistance
Thermal Resistance, 28LD 5x5 QFN
JA
—
36.9
—
°C/W
2015-2018 Microchip Technology Inc.
DS20005473B-page 8
MCP39F511N
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range), and therefore outside the warranted range.
Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz,
channel 1 or channel 2.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
0.50%
0.40%
0.30%
0.20%
0.10%
0.00%
-0.10%
-0.20%
-0.30%
-0.40%
-0.50%
fIN = -60 dBFS @ 60 Hz
fD = 3.9 ksps
16384 pt FFT
OSR = 256
0.01
0.1
1
10
100
)
1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Frequency (Hz)
Current Channel Input Amplitude (mVPEAK
FIGURE 2-1:
Active Power, Gain = 1.
FIGURE 2-4:
Spectral Response.
0.100%
0.050%
0.000%
-0.050%
-0.100%
0.1
1
10
100
1000
Input Voltage RMS (mVPP
)
Total Harmonic Distortion (-dBc)
FIGURE 2-2:
RMS Current, Gain = 1.
FIGURE 2-5:
THD Histogram.
1
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
0
-10
G = 1
G = 8
G = 2
G = 4
G = 16
G = 32
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-1
-50
-25
0
25
50
75
100 125 150
1
10
100
1000
10000 100000
Temperature (°C)
Energy Accumulation (Watt-Hours)
FIGURE 2-3:
Energy, Gain = 8.
FIGURE 2-6:
THD vs. Temperature.
2015-2018 Microchip Technology Inc.
DS20005473B-page 9
MCP39F511N
Note: Unless otherwise indicated, AVDD = 3.3V, DVDD = 3.3V, TA = +25°C, GAIN = 1, VIN = -0.5 dBFS at 60 Hz,
channel 1 or channel 2.
1.2008
1.2007
1.2006
1.2005
1.2004
1.2003
1.2002
1.2001
1.2000
1.1999
94.2 94.3 94.5 94.6 94.8 94.9 95.1 95.2 95.4 95.5
Signal-to-Noise and Distortion Ratio (dB)
-50
0
50
100
150
Temperature (°C)
FIGURE 2-7:
SNR Histogram.
FIGURE 2-10:
Internal Voltage Reference
vs. Temperature.
100
90
80
70
60
50
40
30
20
10
0
G = 1
G = 8
G = 2
G = 4
G = 16
G = 32
-50 -25
0
25
50
75 100 125 150
Temperature (°C)
FIGURE 2-8:
SINAD vs. Temperature.
5
4
3
2
1
0
-1
-2
-3
-4
G = 1
G = 2
G = 4
G = 8
G = 16
G = 32
-5
-50 -25
0
25
50
75
100 125 150
Temperature (°C)
FIGURE 2-9:
Gain Error vs. Temperature.
2015-2018 Microchip Technology Inc.
DS20005473B-page 10
MCP39F511N
3.0
PIN DESCRIPTION
The pin descriptions are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Symbol
MCP39F511N
5x5 QFN
Function
1
EVENT1
NC
Event 1 Output pin
2, 3, 8, 9
No Connect (must be left floating)
UART Communication RX pin
4
5
6
7
UART_RX
COMMONA
OSCI
Common pin A, to be connected to pin 13 (COMMONB)
Oscillator Crystal Connection pin or External Clock Input pin
Oscillator Crystal Connection pin
OSCO
10
11
RESET
AVDD
Reset pin for Delta-Sigma ADCs
Analog Power Supply pin
12
UART_TX
COMMONB
PWM
UART Communication TX pin
13
Common pin B, to be connected to pin 5 (COMMONA)
Pulse-Width Modulation (PWM) Output pin
Event 2 Output pin
14
15
EVENT2
I1+
16
Non-Inverting Current Channel 1 Input for 24-bit ADC
Inverting Current Channel 1 Input for 24-bit ADC
Inverting Voltage Channel 2 Input for 24-bit ADC
Non-Inverting Current Channel 2 Input for 24-bit ADC
Non-Inverting Voltage Channel Input for 10-bit SAR ADC
Analog Ground pin, return path for internal analog circuitry
Zero Crossing Detection Output
17
I1-
18
I2-
19
I2+
20
V+
21
AGND
22
ZCD
23
REFIN+/OUT
Non-Inverting Voltage Reference Input and Internal Reference Output pin
24, 27
DGND
DVDD
Digital Ground pin, return path for internal digital circuitry
Digital Power Supply pin
25
26
Master Clear for device
MCLR
28
29
DR
EP
Data Ready (must be left floating)
Exposed Thermal Pad (to be connected to pins 24 and 27 (DGND))
2015-2018 Microchip Technology Inc.
DS20005473B-page 11
MCP39F511N
3.1
Event Output Pins (EVENTn)
3.9
24-Bit Delta-Sigma ADC
Differential Current Channel
Input Pins (I1+/I1-/I2+/I2-)
These digital output pins can be configured to act as
output flags based on various internal raise conditions.
Control is modified through the Event Configuration
register.
(I1-, I1+), (I2-, I2+) are the two fully-differential
current-channel pair inputs for the Delta-Sigma ADCs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±600 mVPEAK/GAIN
with VREF = 1.2V.
3.2
UART Communication Pins
(UART_RX, UART_TX)
The MCP39F511N device contains an asynchronous
full-duplex UART. The UART communication is eight
bits with the Start and Stop bits. See Section 4.3
“UART Settings” for more information.
The maximum absolute voltage, with respect to AGND
,
for each In+/- input pin is ±1V with no distortion and
±2V with no breaking after continuous voltage.
3.3
Common Pins (COMMON A and B)
3.10 Voltage Analog Input (V+)
The COMMONA and COMMONB pins are internal
connections for the MCP39F511N. These two pins
should be connected together in the application.
This is the non-inverting input to the SAR ADC for
voltage measurement input. This input is used as the
voltage measurement for both channel 1 and channel
2. A DC offset of DVDD/2 and no more than 1 VRMS AC
input signal should be applied on the pin as shown in
the typical application schematic.
3.4
Oscillator Pins (OSCI/OSCO)
OSCI and OSCO provide the master clock for the
device. Appropriate load capacitance should be
connected to these pins for proper operation. An
optional 8 MHz crystal can be connected to these pins.
If a crystal or external clock source is not detected, the
device will clock from the internal 8 MHz oscillator.
3.11 Analog Ground Pin (A
)
GND
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, voltage reference, POR). If an
analog ground pin is available on the PCB, it is
recommended that this pin be tied to that plane.
3.5
Reset Pin (RESET)
3.12 Zero Crossing Detection (ZCD)
This pin is active-low and places the Delta-Sigma
ADCs, PGA, internal VREF and other blocks associated
with the analog front-end in a Reset state when pulled
low. This input is Schmitt-triggered.
This digital output pin is the output of the zero crossing
detection circuit of the IC. The output here will be a
logic output with edges that transition at each zero
crossing of the voltage channel input. For more
information see Section 5.10 “Zero Crossing
Detection (ZCD)”.
3.6
Master Clear Pin (MCLR)
This pin places the SAR, ADC, Calculation Engine,
UART serial interface and digital outputs in a Reset
state when pulled low. This input is Schmitt-triggered.
3.13 Non-Inverting Reference
Input/Internal Reference Output
Pin (REFIN+/OUT)
3.7
Analog Power Supply Pin (AV
)
DD
This pin is the non-inverting side of the differential
voltage reference input for the Delta-Sigma ADCs or
the internal voltage reference output.
AVDD is the power supply pin for the analog circuitry
within the MCP39F511N.
This pin requires appropriate bypass capacitors and
should be maintained to 2.7V and 3.6V for specified
operation. It is recommended to use 0.1 µF ceramic
capacitors.
For optimal performance, bypass capacitances should
be connected between this pin and AGND at all times,
even when the internal voltage reference is used.
However, these capacitors are not mandatory to
ensure proper operation.
3.8
Pulse-Width Modulator (PWM)
This digital output is a dedicated PWM output that can
be controlled through the PWM Frequency and PWM
Duty-Cycle Registers. See Section 8.0 “Pulse-Width
modulation (PWM)” for more information.
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MCP39F511N
3.14 Digital Ground Connection Pins
(D
)
GND
DGND is the ground connection to internal digital
circuitry (SINC filters, oscillator, serial interface). If a
digital ground plane is available, it is recommended to
tie this pin to the digital plane of the PCB. This plane
should also reference all other digital circuitry
components in the system.
3.15 Digital Power Supply Pin (DV
)
DD
DVDD is the power supply pin for the digital circuitry
within the MCP39F511N. This pin requires appropriate
bypass capacitors and should be maintained between
2.7V and 3.6V for specified operations. It is
recommended to use 0.1 µF ceramic capacitors.
3.16 Data Ready Pin (DR)
The Data Ready pin indicates if a new Delta-Sigma A/D
conversion result is ready to be processed. This pin is
for indication only and should be left floating. After each
conversion is finished, a low pulse will take place on the
Data Ready pin to indicate the conversion result is
ready and an interrupt is generated in the calculation
engine (CE). This pulse is synchronous with the line
frequency to ensure an integer number of samples for
each line cycle.
Note:
This pin is internally connected to the IRQ
of the calculation engine and should be
left floating.
3.17 Exposed Thermal Pad (EP)
This pin is the exposed thermal pad. It must be
connected to DGND
.
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MCP39F511N
NOTES:
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MCP39F511N
4.0
COMMUNICATION PROTOCOL
Note:
If a custom communication protocol is
desired, please contact a Microchip sales
office.
All communication to the device occurs in frames. Each
frame consists of a header byte, the number of bytes in
the frame, a command packet (or command packets)
and a checksum. It is important to note that the maxi-
mum number of bytes in either a Receive or Transmit
frame is 35.
Frame
Header Byte (0xA5) Number of Bytes Command Packet1 Command Packet2 Command Packet n
Checksum
..
Command
BYTE0
BYTE N
BYTE N
BYTE1 BYTE2
FIGURE 4-1: MCP39F511N Communication Frame.
This approach allows for single, secure transmission
from the host processor to the MCP39F511N with
either a single command or multiple commands. No
command in a frame is processed until the entire frame
is complete and the checksum and number of bytes are
validated.
4.2
Checksum
The checksum is generated using simple byte addition
and taking the modulus to find the remainder after
dividing the sum of the entire frame by 256. This oper-
ation is done to obtain an 8-bit checksum. All the bytes
of the frame are included in the checksum, including
the header byte and the number of bytes. If a frame
includes multiple command packets, none of the com-
mands will be issued if the frame checksum fails. In this
instance, the MCP39F511N will respond with a CSFAIL
response of 0x51.
The number of bytes in an individual command packet
depends on the specific command. For example, to set
the instruction pointer, three bytes are needed in the
packet: the command byte and two bytes for the
address you want to set to the pointer. The first byte in
a command packet is always the command byte.
On commands that are requesting data back from the
MCP39F511N, the frame and checksum are created in
the same way, with the header byte becoming an
Acknowledge (0x06). Communication examples are
given in Section 4.5 “Example Communication
Frames and MCP39F511N Responses”.
4.1
Device Responses
After the reception of a communication frame, the
MCP39F511N has three possible responses, which are
returned with or without data, depending on the frame
received. These responses are either:
4.3
UART Settings
• Acknowledge (ACK, 0x06): Frame received with
success; commands understood and commands
executed with success.
The default baud rate is 115.2 kbps and can be
changed using the UART bits in the System
Configuration Register. Note that the baud rate is
changed only at system power-up, so when changing
the baud rate, a Save To Flashcommand followed
by a power-on cycle is required.
• Negative Acknowledge (NAK, 0x15): Frame
received with success; however, commands not
executed with success, commands not understood
or some other error in the command bytes.
• Checksum Fail (CSFAIL, 0x51): Frame received
with success; however, the checksum of the
frame did not match the bytes in the frame.
The UART operates in 8-bit mode, plus one start bit
and one stop bit, for a total of 10 bits per byte, as
shown in Figure 4-1.
Note:
There is one unique device ID response
used to determine which MCP39FXXX
device is present: [NAK(0x15) + ID_BYTE].
If the device is interrogated with 0x5A, i.e.
it receives 0x5A as the first byte instead of
the standard 0xA5 first header byte, a
special NAK is returned followed by an
ID_BYTE. For the MCP39F511N the
ID_BYTE is 0x03.
START
IDLE
D0 D1 D2 D3 D4 D5 D6 D7 STOP IDLE
FIGURE 4-1:
UART Transmission, N-8-1.
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MCP39F511N
4.4
Command List
The following table is a list of all accepted command
bytes for the MCP39F511N. There are 10 possible
accepted commands for the MCP39F511N.
TABLE 4-1:
MCP39F511N INSTRUCTION SET
Successful
Number
Command
#
Command
Instruction
Parameter
Command
Response
ID
ofbytes
UART_TX
1
Register Read, N bytes
0x4E
Number of bytes
2
ACK, Data,
Checksum
2
3
4
5
Register Write, N bytes
Set Address Pointer
Save Registers To Flash
Page Read EEPROM
0x4D
0x41
0x53
0x42
Number of bytes
ADDRESS
None
1+N
3
ACK
ACK
ACK
1
PAGE
2
ACK, Data,
Checksum
6
7
Page Write EEPROM
0x50
0x4F
0x5A
0x7A
0x76
PAGE
None
Channel Selection (1)
Channel Selection (1)
None
18
1
ACK
ACK
Bulk Erase EEPROM
8
Auto-Calibrate Gain
Note 2
9
Auto-Calibrate Reactive Gain
Auto-Calibrate Frequency
Note 2
Note 2
10
Note 1: Each bit in the instruction parameter byte refers to the corresponding channel that is being calibrated with
the command. For example, if bits 0 and 1 are high, both channels 1 and 2 will be calibrated. A NAK or
ACK will be returned. If a NAK is returned, refer to the Calibration Status bits in the Event Configuration
Register for more information.
2: See Section 9.0 “MCP39F511N Calibration” for more information on calibration.
4.5
Example Communication Frames
and MCP39F511N Responses
Tables 4-2 to 4-11 show exact hexadecimal
communication frames as they are recommended to be
sent to the MCP39F511N from the system MCU. The
values here can be used as direct examples for writing
the code to communicate to the MCP39F511N.
TABLE 4-2:
Byte #
REGISTER READ, N BYTES COMMAND (Note 1)
Value
Description
Response from MCP39F511N
1
2
3
4
5
6
7
8
0xA5
0x08
0x41
0x00
0x02
0x4E
0x20
0x5E
Header Byte
Number of Bytes in Frame
Command (Set Address Pointer)
Address High
Address Low
Command (Register Read, N Bytes)
Number of Bytes to Read (32)
Checksum
ACK + Number of Bytes (35) + 32 bytes +
Checksum
Note 1: This example Register Read, N bytesframe, as it is written here, can be used to poll a subset of the
output data, starting at the top, address 0x02, and reading 32 data bytes back or 35 bytes total in the frame.
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MCP39F511N
TABLE 4-3:
Byte #
REGISTER WRITE, N- BYTES COMMAND (Note 1)
Value
Description
Response from MCP39F511N
1
2
0xA5
0x17
Header Byte
Number of Bytes in Frame (23)
Command (Set Address Pointer)
Address High
3
0x41
4
0x00
5
0xB1
Address Low
6
0x4D
Command (Register Write, N Bytes)
Number of Bytes to Write (15)
Data Bytes (15 total data bytes)
Checksum
7
0x0F
8-22
23
*Data*
Checksum
ACK
Note 1: This Register Write, N Bytesframe, as shown here, is writing channel 1 range and calibration target
values, starting at address 0xB1 (the second byte in the Channel 1 Range register) and then writing 15
bytes of data to consecutive addresses to complete the setup of channel 1 registers prior to calibration.
Note these are not the calibration registers, but the calibration targets which need to be written prior to
issuing the auto-calibration target commands. See Section 9.0 “MCP39F511N Calibration” for more
information.
TABLE 4-4:
Byte #
SET ADDRESS POINTER COMMAND (Note 1)
Value
Description
Response from MCP39F511N
1
2
3
4
5
6
0xA5
0x06
0x41
0x00
0x02
0xEE
Header Byte
Number of Bytes in Frame
Command (Set Address Pointer)
Address High
Address Low
Checksum
ACK
Note 1: The Set Address Pointercommand is typically included inside of a frame that includes a read or write
command, as shown in Tables 4-2 and 4-3. There is typically no reason for this command to have its own
frame, but is shown here as an example.
TABLE 4-5:
Byte #
SAVE TO FLASH COMMAND
Value
Description
Response from MCP39F511N
1
2
3
4
0xA5
0x04
0x53
0xFC
Header Byte
Number of Bytes in Frame
Command (Save To Flash)
Checksum
ACK
TABLE 4-6:
Byte #
PAGE READ EEPROM COMMAND
Value
Description
Header Byte
Response from MCP39F511N
1
2
3
4
5
0xA5
0x05
0x42
0x01
0xED
Number of Bytes in Frame
Command (Page Read EEPROM)
Page Number (e.g. 1)
Checksum
ACK + EEPROM Page Data + Checksum
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MCP39F511N
TABLE 4-7:
Byte #
PAGE WRITE EEPROM COMMAND
Value
Description
Response from MCP39F511N
1
2
0xA5
0x15
Header Byte
Number of Bytes in Frame
Command (Page Write EEPROM)
Page Number (e.g. 1)
EEPROM Data (16 bytes/Page)
Checksum
3
0x50
4
0x01
5-20
21
*Data*
Checksum
ACK
TABLE 4-8:
Byte #
BULK ERASE EEPROM COMMAND
Value
Description
Response from MCP39F511N
1
2
3
4
0xA5
0x04
0x4F
0xF8
Header Byte
Number of Bytes in Frame
Command (Bulk Erase EEPROM)
Checksum
ACK
TABLE 4-9:
Byte #
AUTO-CALIBRATE GAIN COMMAND
Value
Description
Response from MCP39F511N
1
2
3
4
0xA5
0x05
0x5A
0x03
Header Byte
Number of Bytes in Frame
Command (Auto-Calibrate Gain)
Instruction Parameter (Channel Instruction,
calibrate both channels 1 and 2)
5
0x07
Checksum
ACK (or NAK if unable to
calibrate)(1)
Note 1: See Section 9.0 “MCP39F511N Calibration” for more information.
TABLE 4-10: AUTO-CALIBRATE REACTIVE GAIN COMMAND
Byte #
Value
Description
Response from MCP39F511N
1
2
3
0xA5
0x05
0x7A
Header Byte
Number of Bytes in Frame
Command (Auto-Calibrate Reactive
Gain)
4
5
0x01
0x25
Instruction Parameter (Channel Instruction,
calibrate channel 1 only)
Checksum
ACK (or NAK if unable to
calibrate)(1)
Note 1: See Section 9.0 “MCP39F511N Calibration” for more information.
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MCP39F511N
Response from
TABLE 4-11: AUTO-CALIBRATE FREQUENCY COMMAND
Byte #
Value
Description
1
2
3
4
0xA5
0x04
0x76
0x1F
Header Byte
Number of Bytes in Frame
Command (Auto-Calibrate Frequency)
Checksum
ACK (or NAK if unable to calibrate)(1)
Note 1: See Section 9.0 “MCP39F511N Calibration” for more information.
4.6.5
PAGE READ EEPROM (0x42)
4.6
Command Descriptions
The Page Read EEPROMcommand returns 16 bytes
of data that are stored in an individual page on the
MCP39F511N. A more complete description of the
memory organization of the EEPROM can be found in
Section 10.0 “EEPROM”. This command is expecting
the EEPROM page as the command parameter or the
following byte. The response to this command is an
Acknowledge, 16-bytes of data and CRC Checksum.
4.6.1
REGISTER READ, N BYTES (0x4E)
The Register Read, N Bytescommand returns
the N bytes that follow whatever the current address
pointer is set to. It should typically follow a Set
Address Pointer command and can be used in
conjunction with other read commands. An
Acknowledge, Data and Checksum is the response for
this command. The maximum number of bytes that can
be read with this command is 32. If there are other read
commands within a frame, the maximum number of
bytes that can be read is 32 minus the number of bytes
being read in the frame. With this command, the data is
returned LSB first.
4.6.6
PAGE WRITE EEPROM (0x50)
The Page Write EEPROM command is expecting
17 additional bytes in the command parameters, which
are the EEPROM page plus 16 bytes of data. A more
complete description of the memory organization of the
EEPROM can be found in Section 10.0 “EEPROM”.
The response to this command is an Acknowledge.
4.6.2
REGISTER WRITE, N BYTES (0x4D)
Bytes command is
The Register Write,
N
4.6.7
BULK ERASE EEPROM (0x4F)
followed by N bytes that will be written to whatever the
current address pointer is set to. It should typically
follow a Set Address Pointercommand and can
be used in conjunction with other write commands. An
Acknowledge is the response for this command. The
maximum number of bytes that can be written with this
command is 32. If there are other write commands
within a frame, the maximum number of bytes that can
be written is 32 minus the number of bytes being
written in the frame. With this command, the data is
written LSB first.
The Bulk Erase EEPROM command will erase the
entire EEPROM array and return it to a state of 0xFFFF
for each memory location of EEPROM. A more
complete description of the memory organization of the
EEPROM can be found in Section 10.0 “EEPROM”.
The response to this command is Acknowledge.
4.6.8
AUTO-CALIBRATE GAIN (0x5A)
The Auto-Calibrate Gain command initiates the
single-point calibration that is all that is typically
required for the system. This command calibrates the
RMS current, RMS voltage and Active power based on
the target values written in the corresponding registers.
The instruction parameter for this command selects if
you are calibrating channel 1, 2 or both. Bit 0
corresponds to channel 1 and bit 1 corresponds to
channel 2. See Section 9.0 “MCP39F511N
Calibration” for more information on device
calibration. The response to this command is
Acknowledge.
4.6.3
SET ADDRESS POINTER (0x41)
This command is used to set the address pointer for all
read and write commands. This command is expecting
the address pointer as the command parameter in the
following two bytes: Address High Byte followed by
Address Low Byte. The address pointer is two bytes in
length. If the address pointer is within the acceptable
addresses of the device, an Acknowledge will be
returned.
4.6.4
SAVE REGISTERS TO FLASH (0x53)
The Save Registers To Flashcommand makes
a copy of all the calibration and configuration registers
to flash. This includes all R/W registers in the register
set. The response to this command is an Acknowledge.
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MCP39F511N
4.6.9
AUTO-CALIBRATE REACTIVE
POWER GAIN (0x7A)
The Auto-Calibrate Reactive Gain command
initiates single-point calibration to match the
a
measured Reactive power to the target Reactive
power. The instruction parameter for this command
selects if you are calibrating channel 1, 2, or both. Bit 0
corresponds to channel 1 and bit 1 corresponds to
channel 2. This is typically done at PF = 0.5. See
section Section 9.0 “MCP39F511N Calibration” for
more information on device calibration.
4.6.10
AUTO-CALIBRATE FREQUENCY
(0x76)
For applications not using an external crystal and
running the MCP39F511N off the internal oscillator, a
gain calibration to the line frequency indication is
required. The Gain Line Frequency register is set such
that the frequency indication matches what is set in the
Line Frequency Reference register. See Section 9.0
“MCP39F511N Calibration” for more information on
device calibration.
4.7
Notation for Register Types
The following notation has been adopted for describing
the various registers used in the MCP39F511N:
TABLE 4-12: SHORT-HAND NOTATION
FOR REGISTER TYPES
Notation
Description
u64
u32
s32
u16
s16
b32
Unsigned, 64-bit register
Unsigned, 32-bit register
Signed, 32-bit register
Unsigned, 16-bit register
Signed, 16-bit register
32-bit register containing discrete
Boolean bit settings
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MCP39F511N
frequency calibration (see section Section 9.6.1
5.0
5.1
CALCULATION ENGINE (CE)
DESCRIPTION
“Using the Auto-Calibrate
Frequency
Command”. Note that the resolution of the Line
Frequency Output register is fixed, and the resolution is
1 mHz.
Computation Cycle Overview
The MCP39F511N uses a coherent sampling algorithm
to phase lock the sampling rate to the line frequency on
the voltage channel input with an integer number of
samples per line cycle, and reports all power output
quantities at a 2N number of line cycles. This is defined
as a computation cycle and is dependent on the line
frequency, so any change in the line frequency will
change the update rate of the power outputs.
5.2
Accumulation Interval Parameter
The accumulation interval is defined as a 2N number of
line cycles, where N is the value in the Accumulation
Interval Parameter register. This is identical for both
calculation channels.
5.3
Raw Voltage and Currents Signal
Conditioning
There are two separate computation paths, using two
currents from two separate channels (channel 1 and
channel 2) referenced below as IN and V. Therefore
each current, power, and energy output is duplicated,
one for each calculation channel.
The first set of signal conditioning that occurs inside the
MCP39F511N is shown in Figure 5-1. All conditions set
in this diagram affect all of the output registers (RMS
current, RMS voltage, Active power, Reactive power,
apparent power, etc.). The gain of the PGA, the
Shutdown and Reset status of the 24-bit ADCs are all
controlled through the System Configuration Register.
In addition, there are duplicate calibration registers
(offset, gain, phase, etc.) for each calculation channel.
5.1.1
LINE FREQUENCY
To compensate for any external phase error between
the current and voltage channels, the Phase
Compensation register can be used.
The coherent sampling algorithm is also used to
calculate the Line Frequency Output register, which is
updated every computation cycle. The correction factor
for line frequency measurement is the Gain Line
Frequency register, which is used during the line
See Section 9.0 “MCP39F511N Calibration” for
more information on device calibration.
24-bit ADC
Multi-Level
Modulator
IN+
IN-
+
-
PGA
iN
HPF (1)
+
+
CHANNEL IN
SystemConfiguration:b32
PhaseCompensation1:s16
V+
10-bit SAR ADC
v
HPF (1)
CHANNEL V
Note 1: High-Pass Filters (HPFs) are automatically disabled in the absence of an AC signal on the voltage channel.
FIGURE 5-1:
Channels 1 or 2 (IN and V) Input-Signal Flow.
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MCP39F511N
5.4
RMS Current, RMS Voltage and
Apparent Power (S)
The MCP39F511N device provides true RMS
measurements. The MCP39F511N device has two
simultaneous sampling 24-bit A/D converters for the
current measurements. The root mean square
calculations are performed on 2N current and voltage
samples, where
N is defined by the register
Accumulation Interval Parameter.
EQUATION 5-1:
RMS CURRENT AND
VOLTAGE
N
N
2
– 1
2 – 1
2
2
i
v
n
n
n = 0
n = 0
I
=
-----------------------------
V
=
------------------------------
RMS
RMS
N
N
2
2
Range:b32
2N-1
N
÷ 2
÷2RANGE
CurrentRMS1,2:u32
i
0
X
N
X
+
ACCU
+
GainCurrentRMS1,2:u16
OffsetCurrentRMS1,2:s32
ApparentPower1,2:u32
GainVoltageRMS:u16
X
2
N-1
N
÷ 2
÷2RANGE
v
VoltageRMS:u16
0
X
X
ACCU
Range:b32
FIGURE 5-2:
RMS Current (Channel 1 or 2), Apparent Power (Channel 1 and 2) and Voltage
Calculation Signal Flow.
Because AppPowerDivisorDigits registers can be
higher than 4, it may result in a 32-bit divisor. To
improve the speed of this part of the calculation engine,
a method that uses only multiplications and right-bit
shifts was implemented. Therefore the following
equation applies:
5.4.1
APPARENT POWER (S)
This 32-bit register is the output register for the final
apparent power indication. It is the product of RMS
current and RMS voltage as shown in Equation 5-2.
EQUATION 5-2:
APPARENT POWER (S)
V
EQUATION 5-3:
APPARENT POWER (S)
S = I
RMS
RMS
I
V
RMS
RMS
ApparentPower = ---------------------------------------------------------------------
10AppPowerDivisorDigits
5.4.2
The
APPARENT POWER DIVISOR
DIGITS
registers
AppPowerDivisorDigits1
and
AppPowerDivisorDigits2 are configurable by the user
depending on the precision of the RMS indications and
the desired precision for ApparentPower1 or
ApparentPower2.
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MCP39F511N
5.5
Power and Energy
The MCP39F511N offers signed power numbers for
active and reactive power, import and export registers
for active energy, and four-quadrant reactive power
measurement. For this device, import power or energy
is considered positive (power or energy being
consumed by the load), and export power or energy is
considered negative (power or energy being delivered
by the load). The following figure represents the
measurements obtained by the MCP39F511N.
Import Reactive Power
Generate, Inductive
Consume, Inductive
+P, +Q
-P, +Q
Quadrant I
Quadrant II
S
Q
P
Import Active Power
Export Active Power
Quadrant III
Quadrant IV
Generate, Capacitive
-P, -Q
Consume, Capacitive
+P, -Q
Export Reactive Power
The Power Circle and Triangle (S = Apparent, P = Active, Q = Reactive).
FIGURE 5-3:
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MCP39F511N
5.6
Energy Accumulation
5.7
Active Power (P)
Energy accumulation for all four energy registers
(import/export, active/reactive) occurs at the end of
each computation cycle if the energy accumulation has
been turned on. See Section 6.5 “System
Configuration Register” for the energy-control bits.
The accumulation of energy occurs in one of eight
64-bit energy counters, four for each channel (import
and export counters for both active and reactive
power).
The MCP39F511N has three simultaneous sampling
A/D converters monitoring two individual currents and
two individual active powers. For the Active Power cal-
culations, the instantaneous currents and voltage are
multiplied together to create instantaneous power. This
instantaneous power is then converted to Active Power
by averaging or calculating the DC component.
Equation 5-5 controls the number of samples used in
this accumulation prior to updating the Active Power
output register.
5.6.1
NO-LOAD THRESHOLD
Please note that although this register is unsigned, the
direction of the Active power (import or export) can be
determined by the Active Power Sign bit located in the
System Status Register.
The no-load threshold is set by modifying the value in
the No-Load Threshold register. The unit for this
register is power with a default resolution of 0.01W. The
default value is 100 or 1.00W. Any power that is below
1W will not be accumulated into any of the energy
registers.
EQUATION 5-5:
ACTIVE POWER
N
For scaling of the apparent power indication, the calcu-
lation engine uses the Apparent Power Divisor register.
This is described in the following register operations,
per Equation 5-4.
k = 2 – 1
1
N
2
P = ------
V I
k
k
k = 0
EQUATION 5-4:
APPARENT POWER (S)
CurrentRMS VoltageRMS
S = --------------------------------------------------------------------
ApparentPowerDivisor
10
GainActivePower1,2:u16
i
N
Range1,2:b32
N
2
-1
÷ 2N
÷2RANGE
ActivePower1,2:u32
X
X
0
+
ACCU
+
OffsetActivePower1,2:s32
v
FIGURE 5-4:
Channel 1 or Channel 2 Active Power Calculation Signal Flow.
2015-2018 Microchip Technology Inc.
DS20005473B-page 24
MCP39F511N
5.8
Power Factor (PF)
Power factor is calculated by the ratio of P to S, or
Active power divided by Apparent power.
EQUATION 5-6:
POWER FACTOR
P
PF = ---
S
The Power Factor Reading is stored in two signed
16-bit registers (Power Factor), one for each channel.
This register is a signed, two's complement register
with the MSB representing the polarity of the power
factor. Positive power factor means import power,
negative power factor means export power. The sign of
the Reactive power component can be used to
determine if the load is inductive (positive) or capacitive
(negative).
Each LSB is then equivalent to a weight of 2-15. A
maximum register value of 0x7FFF corresponds to a
power factor of 1. The minimum register value of
0x8000 corresponds to a power factor of -1.
5.9
Reactive Power (Q)
In the MCP39F511N, Reactive Power is calculated
using a 90 degree phase shift in the voltage channel.
The same accumulation principles apply as with Active
power where ACCU acts as the accumulator. Any light
load or residual power can be removed by using the
Offset Reactive Power register. Gain is corrected by
the Gain Reactive Power register. The final output is an
unsigned 32-bit value located in the Reactive Power
register.
Please note that although this register is unsigned, the
direction of the power can be determined by the
Reactive Power Sign bit in the System Status Register.
GainReactivePower1,2:u16
i
N
Range1,2:b32
N
2
-1
÷ 2N
÷2RANGE
X
X
0
+
ACCU1
-
ReactivePower1,2:u32
OffsetReactivePower1,2:s32
v
HPF (+90deg.)
FIGURE 5-5:
Channel 1 or Channel 2 Reactive Power Calculation Signal Flow.
2015-2018 Microchip Technology Inc.
DS20005473B-page 25
MCP39F511N
5.10 Zero Crossing Detection (ZCD)
The zero crossing detection block generates a logic
pulse output on the ZCD pin that is coherent with the
zero crossing of the input AC signal present on voltage
input pin (V+). The ZCD pin can be enabled and
disabled by the corresponding bit in the System
Configuration Register. When enabled, this produces a
square wave with a frequency that is the same as the
AC signal present on the voltage input. Figure 5-6
represents the signal on the ZCD pin superimposed
with the AC signal present on the voltage input in this
mode.
<200 µs
FIGURE 5-6:
Zero Crossing Detection
Operation (Non-Inverted, Non-Pulse).
A
second mode is available that produces a
100 µs pulse. The frequency here is twice that of the
AC signal on the voltage channel input, at each zero
crossing, as shown in Figure 5-7.
<200 µs
FIGURE 5-7:
Zero Crossing Detection
Operation (Non-Inverted, Pulsed).
Switching modes is done by setting the corresponding
bit in the System Configuration Register.
In addition, either the toggling of this pin, or the pulse,
can be inverted. The ZCD Inversion bit is also in the
System Configuration register.
There are two bits in the System Configuration register
that can be used to modify the zero crossing. The zero
crossing output can be inverted by setting the inversion
bit, or the zero crossing can be a 100 µs pulse at each
zero crossing by setting the pulse bit.
Note that a low-pass filter is included in the signal path
that allows the zero crossing detection circuit to filter
out the fundamental frequency. An internal
compensation circuit is then used to gain back the
phase delay introduced by the low-pass filter resulting
in a latency of less than ±200 µs.
2015-2018 Microchip Technology Inc.
DS20005473B-page 26
MCP39F511N
6.0
6.1
REGISTER DESCRIPTIONS
Complete Register Map
The following table describes the registers for the MCP39F511N device.
TABLE 6-1:
Address
MCP39F511N REGISTER MAP
Section Read/ Data
Number Write type
Register Name
Description
Output Registers
0x0000 Instruction Pointer
0x0002 System Status
0x0004 System Version
6.2
6.3
6.4
R
R
R
u16 Address pointer for read or write commands
b16 System Status Register
u16 System version date code information for
MCP39F511N, set at the Microchip factory;
format YMDD
0x0006 Voltage RMS
0x0008 Line Frequency
0x000A Power Factor1
0x000C Power Factor2
0x000E Current RMS1
0x0012 Current RMS2
0x0016 Active Power1
0x001A Active Power2
0x001E Reactive Power1
0x0022 Reactive Power2
0x0026 Apparent Power1
0x002A Apparent Power2
5.4
5.1.1
5.8
5.8
5.4
5.4
5.7
5.7
5.9
5.9
5.4
5.4
5.6
R
R
R
R
R
R
R
R
R
R
R
R
R
u16 RMS Voltage output
u16 Line Frequency output
s16 Power Factor output from channel 1
s16 Power Factor output from channel 2
u32 RMS Current output from channel 1
u32 RMS Current output from channel 2
u32 Active Power output from channel 1
u32 Active Power output from channel 2
u32 Reactive Power output from channel 1
u32 Reactive Power output from channel 2
u32 Apparent Power output from channel 1
u32 Apparent Power output from channel 2
0x002E Import Energy Active
Counter 1
u64 Accumulator for Active Energy, Import,
channel 1
0x0036 Import Energy Active
Counter 2
5.6
5.6
5.6
5.6
5.6
5.6
5.6
R
R
R
R
R
R
R
u64 Accumulator for Active Energy, Import,
channel 2
0x003E Export Energy Active
Counter 1
u64 Accumulator for Active Energy, Export,
channel 1
0x0046 Export Energy Active
Counter 2
u64 Accumulator for Active Energy, Export,
channel 2
0x004E Import Energy Reactive
Counter 1
u64 Accumulator for Reactive Energy, Import,
channel 1
0x0056 Import Energy Reactive
Counter 2
u64 Accumulator for Reactive Energy, Import,
channel 2
0x005E Export Energy Reactive
Counter 1
u64 Accumulator for Reactive Energy, Export
channel 1
0x0066 Export Energy Reactive
Counter 2
u64 Accumulator for Reactive Energy, Export,
channel 2
Calibration Registers
0x006E Calibration Registers Delimiter
9.7
5.4
5.4
5.4
R/W
R/W
R/W
R/W
u16 May be used to initiate loading of the default
factory calibration coefficients at start-up
0x0070 Gain Current RMS1
0x0072 Gain Current RMS2
0x0074 Gain Voltage RMS
u16 Gain Calibration Factor for RMS Current
channel 1
u16 Gain Calibration Factor for RMS Current
channel 2
u16 Gain Calibration Factor for RMS Voltage
2015-2018 Microchip Technology Inc.
DS20005473B-page 27
MCP39F511N
TABLE 6-1:
Address
MCP39F511N REGISTER MAP (CONTINUED)
Section Read/ Data
Register Name
Description
Number Write type
0x0076 Gain Active Power1
0x0078 Gain Active Power2
0x007A Gain Reactive Power1
0x007C Gain Reactive Power2
0x007E Gain Line Frequency
0x0080 Offset Current RMS1
0x0084 Offset Current RMS2
0x0088 Offset Active Power1
0x008C Offset Active Power2
0x0090 Offset Reactive Power1
0x0094 Offset Reactive Power2
5.7
5.7
5.9
5.9
5.1.1
5.4
5.4
5.7
5.7
5.9
5.9
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
u16 Gain Calibration Factor for Active Power,
channel 1
u16 Gain Calibration Factor for Active Power,
channel 2
u16 Gain Calibration Factor for Reactive Power,
channel 1
u16 Gain Calibration Factor for Reactive Power,
channel 2
u16 Gain Calibration Factor for the Line
Frequency
s32 Offset Calibration Factor for RMS Current,
channel 1
s32 Offset Calibration Factor for RMS Current,
channel 2
s32 Offset Calibration Factor for Active Power,
channel 1
s32 Offset Calibration Factor for Active Power,
channel 2
s32 Offset Calibration Factor for Reactive Power,
channel 1
s32 Offset Calibration Factor for Reactive Power,
channel 2
0x0098 Phase Compensation1
0x009A Phase Compensation2
0x009C Apparent Power Divisor1
5.3
5.3
R/W
R/W
R/W
s16 Phase Compensation, channel 1
s16 Phase Compensation, channel 2
5.4.2
u16 Number of Digits for apparent power divisor
to match IRMS and VRMS resolution,
channel 1
0x009E Apparent Power Divisor2
5.4.2
R/W
u16 Number of Digits for apparent power divisor
to match IRMS and VRMS resolution,
channel 2
Design Configuration Registers
0x00A0 System Configuration
6.5
7.5
R/W
R/W
R/W
R/W
R/W
b32 Control for device configuration, including
ADC configuration
0x00A4 Event Configuration
b32 Settings for the Event pins including Relay
Control
0x00A8 Accumulation Interval
Parameter
5.2
u16 N for 2N number of line cycles to be used
during a single computation cycle
0x00AA Calibration Voltage
9.3.1
9.6.1
u16 Target Voltage to be used during single-point
calibration
0x00AC Calibration Line Frequency
u16 Reference Value for the nominal line
frequency
0x00AE Range1
6.6
R/W
R/W
b32 Scaling factor for Outputs, channel 1
0x00B2 Calibration Current1
9.3.1
u32 Target Current to be used during single-point
calibration, channel 1
0x00B6 Calibration Power Active1
0x00BA Calibration Power Reactive1
0x00BE Range2
9.3.1
9.3.1
6.6
R/W
R/W
R/W
u32 Target Active Power to be used during
single-point calibration, channel 1
u32 Target Active Power to be used during
single-point calibration, channel 1
b32 Scaling factor for Outputs, channel 2
2015-2018 Microchip Technology Inc.
DS20005473B-page 28
MCP39F511N
TABLE 6-1:
Address
MCP39F511N REGISTER MAP (CONTINUED)
Section Read/ Data
Register Name
Description
Number Write type
0x00C2 Calibration Current2
0x00C6 Calibration Power Active2
0x00CA Calibration Power Reactive2
0x00CE Voltage Sag Limit
9.3.1
9.3.1
9.3.1
7.2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
u32 Target Current to be used during single-point
calibration, channel 2
u32 Target Active Power to be used during
single-point calibration Channel 2
u32 Target Active Power to be used during
single-point calibration, channel 2
u16 RMS Voltage Sag threshold at which an
event flag is recorded
0x00D0 Voltage Surge Limit
0x00D2 Over Current1 Limit
0x00D6 Over Current2 Limit
0x00DA OverPower1 Limit
0x00DE OverPower2 Limit
7.2
u16 RMS Voltage Surge threshold at which an
event flag is recorded
7.2
u32 RMS Over Current threshold for channel 1 at
which an event flag is recorded
7.2
u32 RMS Over Current threshold for channel 2 at
which an event flag is recorded
7.2
u32 Over Power threshold for channel 1 at which
an event flag is recorded
7.2
u32 Over Power threshold for channel 2 at which
an event flag is recorded
Control Registers for Peripherals
0x00E2 PWM Period
8.2
8.3
—
R/W
R/W
—
u16 Input register controlling PWM Frequency
u16 Input register controlling PWM Duty Cycle
u16 Reserved
0x00E4 PWM Duty Cycle
0x00E6 Reserved
0x00E8 Reserved
—
—
u16 Reserved
0x00EA VoltagePhaseCompFreqCoef
—
—
u16 Phase Compensation Frequency Coefficient
0x00EC RangeVoltageChPhaseComp-
Freq
—
—
u16 Voltage Channel Phase Frequency
Compensation Range
0x00EE GainActivePowerCompFre-
qCoef
—
—
—
—
u16 Active Power Gain Frequency
Compensation Coefficient
0x00F0 RangeGainActivePowerComp-
Freq
u16 Active Power Gain Frequency
Compensation Range
0x00F2 GainReactivePowerCompFreq
—
—
u16 Reactive Power Gain Frequency
Compensation Coefficient
0x00F4 RangeGainReactivePower-
CompFreq
—
—
u16 Reactive Power Gain Frequency
Compensation Range
0x00F6 GainVoltageRMSCompFre-
qCoef
—
—
u16 RMS Voltage Gain Frequency
Compensation Coefficient
0x00F8 RangeGainVoltageRMSComp-
Freq
—
—
u16 RMS Voltage Gain Frequency
Compensation Range
0x00FA GainCurrentRMSCompFre-
qCoef
—
—
u16 RMS Current Gain Frequency
Compensation Coefficient
0x00FC RangeGainCurrentRMSComp-
Freq
—
—
u16 RMS Current Gain Frequency
Compensation Range
0x00FE No Load Threshold
5.6.1
R/W
u16 No Load Threshold for Energy Counting
(both channels, all registers)
2015-2018 Microchip Technology Inc.
DS20005473B-page 29
MCP39F511N
6.2
Address Pointer Register
This unsigned 16-bit register contains the address to
which all read and write instructions occur. This register
is only written through the Set Address Pointer
command and is otherwise outside the writable range
of register addresses.
6.3
System Status Register
The System Status register is a read-only register and
can be used to detect the various states of pin levels as
defined in Register 6-1.
REGISTER 6-1:
SYSTEM STATUS REGISTER
U-0
—
U-0
U-0
—
R-x
R-n
R-n
R-x
R-n
—
AC_STATUS
OVER-
POW2
OVERCURR2
EVENT2
EVENT1
bit 15
bit 8
R-n
R-n
R-n
R-n
R-n
R-n
R-n
R-n
SIGN_PR SIGN_PA_ SIGN_PR_C SIGN_PA_C OVERPOW1
OVER-
CURR1
VSURGE
VSAG
_CH2
CH2
H1
H1
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-13
bit 12
Unimplemented: Read as ‘0’
AC_STATUS: AC Detection Status
1= AC Detection failed.
0= AC Detection successful.
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
EVENT2: State of Event2 Detection algorithm. This bit is latched and must be cleared.
1= Event 2 has occurred.
0= Event 2 has not occurred.
EVENT1: State of Event1 Detection algorithm. This bit is latched and must be cleared.
1= Event 1 has occurred.
0= Event 1 has not occurred.
OVERPOW2: Over Power, channel 2. An over power event has occurred on channel 2.
1= Over Power threshold has been broken
0= Over Power threshold has not been broken
OVERCURR2: Over Current, channel 2. An over current event has occurred on channel 2.
1= Over current threshold has been broken
0= Over current threshold has not been broken
SIGN_PR_CH2: Sign of Reactive Power Channel 2 (inductive/capacitive state of the reactive power)
1= Reactive Power is inductive and is in quadrants 1,2
0= Reactive Power is capacitive and is in quadrants 3,4
SIGN_PA_CH2: Sign of Active Power Channel 2 (import/export sign of active power)
1= Active Power is positive (import) and is in quadrants 1,4
0= Active Power is negative (export) and is in quadrants 2,3
2015-2018 Microchip Technology Inc.
DS20005473B-page 30
MCP39F511N
REGISTER 6-1:
SYSTEM STATUS REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
SIGN_PR_CH1: Sign of Reactive Power Channel 1 (inductive/capacitive state of the reactive power)
1= Reactive Power is inductive and is in quadrants 1,2
0= Reactive Power is capacitive and is in quadrants 3,4
SIGN_PA_CH1: Sign of Active Power Channel 1 (import/export sign of active power)
1= Active Power is positive (import) and is in quadrants 1,4
0= Active Power is negative (export) and is in quadrants 2,3
OVERPOW1: Over Power, channel 1. An over power event has occurred on channel 1.
1= Over Power threshold has been broken
0= Over Power threshold has not been broken
OVERCURR1: Over Current, channel 1. An over current event has occurred on channel 1.
1= Over current threshold has been broken
0= Over current threshold has not been broken
VSURGE: Voltage Surge. State of Voltage Surge Detection algorithm. This bit is latched and must be
cleared
1= Surge threshold has been broken
0= Surge threshold has not been broken
bit 0
VSAG: Voltage Sag.State of Voltage Sag Detection algorithm. This bit is latched and must be cleared
1= Sag threshold has been broken
0= Sag threshold has not been broken
The PGA block can be used to amplify very low signals,
but the differential input range of the Delta-Sigma
6.4
System Version Register
The System Version register is hard-coded by
Microchip Technology Incorporated and contains
calculation-engine date-code information. The System
Version register is a date code in the YMDDformat, with
year and month in hex, day in decimal (e.g. 0xFB20 =
2015, Nov. 20th).
modulator must not be exceeded. The PGA is
controlled by the PGA_CHn<2:0> bits in Register 6-2:
the System Configuration register. Table 6-2
represents the gain settings for the PGAs.
TABLE 6-2:
PGA CONFIGURATION
SETTING (Note 1)
6.5
System Configuration Register
Gain
Gain
Gain
(dB)
VIN Range
(V)
PGA_CHn<2:0> (V/V)
The System Configuration register contains bits for the
following control:
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
2
0
±0.6
• PGA setting
6
±0.3
• ADC Reset State
4
12
18
24
30
±0.15
• ADC Shutdown State
• Voltage Reference Trim
• Single Wire Auto-Transmission
8
±0.075
±0.0375
±0.01875
16
32
These options are described in the following sections.
Note 1: This table is defined with VREF = 1.2V.
The two undefined settings, 110and 111
are G = 1.
6.5.1
PROGRAMMABLE GAIN
AMPLIFIERS (PGA)
The two Programmable Gain Amplifiers (PGAs) reside
at the front-end of each 24-bit Delta-Sigma ADC. They
have two functions:
• translate the common mode of the input from
AGND to an internal level between AGND and AVDD
• amplify the input differential signal
The translation of the common mode does not change
the differential signal, but enters the common mode so
that the input signal can be properly amplified.
2015-2018 Microchip Technology Inc.
DS20005473B-page 31
MCP39F511N
6.5.2
24-BIT ADC RESET MODE
(SOFT RESET MODE)
24-bit ADC Reset mode (also called Soft Reset) can
only be entered by setting high the RESET<1:0> bits in
the System Status Register. This mode is defined as
the condition where the converters are active but their
output is forced to ‘0’.
6.5.3
ADC SHUTDOWN MODE
ADC Shutdown mode is defined as a state where the
converters and their biases are OFF, consuming only
leakage current. When the Shutdown bit is reset to ‘0’,
the analog biases will be enabled, as well as the clock
and the digital circuitry.
Each converter can be placed in Shutdown mode
independently. This mode is only available through
programming of the SHUTDOWN<1:0> bits in the
System Status Register.
6.5.4
VREF TEMPERATURE
COMPENSATION
The internal voltage reference comprises a proprietary
circuit and algorithm to compensate first-order and
second-order
temperature
coefficients.
The
compensation allows very low temperature coefficients
(typically 10 ppm/°C) on the entire range of
temperatures from -40°C to +125°C. This temperature
coefficient varies from part to part.
The default value of this register is set to 0x42. The
typical variation of the temperature coefficient of the
internal voltage reference, with respect to VREFCAL
register code, is shown in Figure 6-1.
60
50
40
30
20
10
0
0
64
128
192
256
VREFCAL Register Trim Code (decimal)
FIGURE 6-1:
VREF Tempco vs. VREFCAL
Trimcode Chart.
2015-2018 Microchip Technology Inc.
DS20005473B-page 32
MCP39F511N
REGISTER 6-2:
SYSTEM CONFIGURATION REGISTER
U-0
—
U-0
—
R/W-0
R/W-1
R/W-1
R/W-0
U-0
R/W-1
R/W-1
PGA_CH2<2:0>
PGA_CH1<2:0>
bit 31
bit 24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
bit 23
bit 16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ENERGY1
bit 8
UART<2:0>
ZCD_INV
ZCD_PULS ZCD_OUTPUT_DIS
ENERGY2
bit 15
R/W-0
PWM
R/W-0
R/W-0
R/W-0
R/W-0
U-0
—
U-0
—
RESET<1:0>
SHUTDOWN<1:0>
VREFEXT
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-30
bit 29-27
Unimplemented: Read as ‘0’
PGA_CH2 <2:0>: PGA Setting for channel 2
111= Reserved (Gain = 1)
110= Reserved (Gain = 1)
101= Gain is 32
100= Gain is 16
011= Gain is 8 (Default)
010= Gain is 4
001= Gain is 2
000= Gain is 1
bit 26-24
PGA_CH1 <2:0>: PGA Setting for channel 1
111= Reserved (Gain = 1)
110= Reserved (Gain = 1)
101= Gain is 32
100= Gain is 16
011= Gain is 8 (Default)
010= Gain is 4
001= Gain is 2
000= Gain is 1
bit 23-16
bit 15-13
Unimplemented: Read as ‘0’
UART<2:0>: UART Baud Rate bits
111= 1200
110= 2400
101= 4800
100= 9600
011= 19200
010= 38400
001= 57600
000= 115200 (Default)
bit 12
ZCD_INV: Zero Crossing Detection Output Inverse
1= ZCD is inverted
0= ZCD is not inverted (Default)
2015-2018 Microchip Technology Inc.
DS20005473B-page 33
MCP39F511N
REGISTER 6-2:
SYSTEM CONFIGURATION REGISTER (CONTINUED)
bit 11
bit 10
bit 9
ZCD_PULS: Zero Crossing Detection Pulse mode
1= ZCD output is 200 µs pulses on zero crossings
0= ZCD output changes logic state on zero crossings (Default)
ZCD_OUTPUT_DIS: Disable the Zero Crossing output pin
1= ZCD output is disabled
0= ZCD output is enabled (Default)
ENERGY2: Energy counting control, channel 2
1= Energy Counting for channel 2 is enabled
0= Energy Counting for channel 2 is reset and disabled (Default)
bit 8
ENERGY1: Energy counting control, channel 1
1= Energy Counting for channel 1 is enabled
0= Energy Counting for channel 1 is reset and disabled (Default)
bit 7
PWM: PWM Control
1= PWM Output is enabled
0= PWM Output is disabled (Default)
bit 6-5
RESET <1:0>: Reset mode setting for current measurement ADCs
11= Both I1 and I2 are in Reset mode
10= I2 ADC is in Reset mode
01= I1 ADC is in Reset mode
00= Neither ADC is in Reset mode (Default)
bit 4-3
SHUTDOWN <1:0>: Shutdown mode setting for current measurement ADCs
11= Both I1 and I2 are in Shutdown
10= I2 ADC is in Shutdown
01= I1 ADC is in Shutdown
00= Neither ADC is in Shutdown (Default)
bit 2
VREFEXT: Internal Voltage Reference Shutdown Control
1= Internal Voltage Reference Disabled
0= Internal Voltage Reference Enabled (Default)
bit 1-0
Unimplemented: Read as ‘0’
2015-2018 Microchip Technology Inc.
DS20005473B-page 34
MCP39F511N
The purpose of this register is two-fold: the number of
right-bit shifting (division by 2RANGE) must be:
6.6
Range Registers
The range registers are 32-bit registers that contain the
number of right-bit shifts for the following outputs,
divided into separate bytes defined below across the
two registers:
• high enough to prevent overflow in the output
register
• low enough to allow for the desired output
resolution.
• RMS Voltage
It is the user’s responsibility to set this register correctly
to ensure proper output operation for a given meter
design.
• RMS Current, Channel 1
• Power, Channel 1
• RMS Current, Channel 2
• Power, Channel 2
For further information and example usage, see
Section 9.3 “Single-Point Gain Calibrations at
Unity Power Factor”.
Note that the Power Range byte operates across both
the active and reactive output registers and sets the
same scale.
REGISTER 6-3:
RANGE1 REGISTER
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
bit 31
bit 24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POWER1[7] POWER1[6] POWER1[5] POWER1[4] POWER1[3] POWER1[2] POWER1[1] POWER1[0]
bit 23 bit 16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CUR-
CUR-
CUR-
CUR-
CUR-
CUR-
CUR-
CUR-
RENT1[7]
RENT1[6]
RENT1[5]
RENT1[4]
RENT1[3]
RENT1[2]
RENT1[1]
RENT[0]
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VOLTAGE[7] VOLTAGE[6] VOLTAGE[5] VOLTAGE[4] VOLTAGE[3] VOLTAGE[2] VOLTAGE[1] VOLTAGE[0]
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24
bit 23-16
Unimplemented: Read as ‘0‘
POWER1[7:0]: Sets the number of right-bit shifts for the Active and Reactive Power output registers,
channel 1.
bit 15-8
bit 7-0
CURRENT1[7:0]: Sets the number of right-bit shifts for the Current RMS output register, channel 1.
VOLTAGE[7:0]: Sets the number of right-bit shifts for the Voltage RMS output register.
2015-2018 Microchip Technology Inc.
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MCP39F511N
REGISTER 6-4:
RANGE2 REGISTER
U-0
—
U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
—
bit 31
bit 24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
POWER2[7] POWER2[6] POWER2[5] POWER2[4] POWER2[3] POWER2[2] POWER2[1] POWER2[0]
bit 23 bit 16
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CUR-
CUR-
CUR-
CUR-
CUR-
CUR-
CUR-
CUR-
RENT2[7]
RENT2[6]
RENT2[5]
RENT2[4]
RENT2[3]
RENT2[2]
RENT2[1]
RENT2[0]
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 31-24
bit 23-16
Unimplemented: Read as ‘0‘
POWER2[7:0]: Sets the number of right-bit shifts for the Active and Reactive Power output registers,
channel 2
bit 15-8
bit 7-0
CURRENT2[7:0]: Sets the number of right-bit shifts for the Current RMS output register, channel 2.
Unimplemented: Read as ‘0‘
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MCP39F511N
Therefore, at each data-ready occurrence, the value of
VSA is compared to the programmable threshold set in
the Voltage Sag Limit register and Voltage Surge Limit
register to determine if a flag should be set. If either of
these events are masked to either the Event1 or
Event2 pin, a logic-high interrupt will be given on these
pins.
7.0
7.1
EVENT OUTPUT PINS/EVENT
CONFIGURATION REGISTER
Event Pins
The MCP39F511N device has two event pins that can
be configured in three possible configurations. These
configurations are:
The Sag or Surge events can be used to quickly
determine if a power failure has occurred in the system.
1. No event is mapped to the pin
2. Voltage Surge, Voltage Sag, Over Current or
Over Power event is mapped to the pin. More
than one event can be mapped to the same pin.
7.4
Calibration Status Events
The Event register contains eight bits that correspond
to the pass/fail of a calibration attempt issued through
the Auto-Calibrate Gaincommands.
3. Manual control of two pins, independently. Pos-
sible only when no event is mapped to the pin.
These three configurations allow for the control of
external interrupts or hardware that is dependent on
the measured power, current or voltage. The Event
Configuration Register below describes how these
events and pins can be configured.
These commands can be used to calibrate all
single-point calibration outputs for both channels:
• Line Frequency
• Voltage
• Channel 1 Current
• Channel 1 Active Power
• Channel 1 Reactive Power
• Channel 2 Current
• Channel 2 Active Power
• Channel 2 Reactive Power
7.2
Limits
There are 6 limit registers associated with these
events:
• Voltage Sag Limit
• Voltage Surge Limit
Bits 31-24 are status bits with a 1 representing a
calibration fail. These bits are reset to 0 when a
calibration command is successful for whichever
channel (or both) is being calibrated. For more
• Over Current Limit, channel 1
• Over Power Limit, channel 1
• Over Current Limit, channel 2
• Over Power Limit, channel 2
information
on
calibration,
see
Section 9.3
“Single-Point Gain Calibrations at Unity Power
Factor”.
Each of these limits are compared to the respective
output registers of voltage, current and power, and
should have the same unit, e.g. 0.1V, 0.01W, etc.
7.3
Voltage Sag and Voltage Surge
Detection
The event alarms for Voltage Sag and Voltage Surge
work differently compared to the Over Current and
Over Power events, which are tested against every
computation cycle. These two event alarms are
designed to provide a much faster interrupt if the con-
dition occurs. Note that neither of these two events
have a respective Hold register associated with them,
since the detection time is less than one line cycle.
The calculation engine keeps track of a trailing mean
square of the input voltage, as defined by Equation 7-1:
EQUATION 7-1:
2
2 f
0
LINE
V
= -------------------------
V
SA
n
f
SAMPLE
f
SAMPLE
n = – ------------------------- – 1
2 f
LINE
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MCP39F511N
7.5
Event Configuration Register
The Event Configuration register is used to control the
event operations and the event pins and to give event
and calibration status.
REGISTER 7-1:
EVENT CONFIGURATION REGISTER
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
CAL_PR2
CAL_PR1
CAL_PA2
CAL_PA1
CAL_CURR CAL_CURR CAL_VOLT
CAL_LF
2
1
bit 31
bit 24
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
OVER-
POW_PIN2
OVER-
CUR_PIN2
VSURGE_PI VSAG_PIN2
N2
OVER-
POW_PIN1 CUR_PIN1
OVER-
VSURGE_PI VSAG_PIN1
N1
bit 23
bit 16
R/W-0
R/W-0
U-0
—
U-0
—
R/W-0
R/W-0
R/W-0
R/W-0
EVENT2_MA EVENT1_MA
OVER-
CUR_CL
OVER-
POW_CL
VSURGE_C VSAG_CL
L
NU
NU
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
VSUR_LA
VSAG_LA
OVER-
OVER-
VSUR_TST VSAG_TST
OVER-
OVER-
POW_LA
CUR_LA
POW_TST
CUR_TST
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
-n = Value at POR
bit 31
bit 30
bit 29
bit 28
bit 27
bit 26
bit 25
CAL_PR2: Single-Point Calibration Result for Reactive Power, channel 2
1 = Calibration Failed
0 = Calibration Successful
CAL_PR1: Single-Point Calibration Result for Reactive Power, channel 1
1 = Calibration Failed
0 = Calibration Successful
CAL_PA2: Single-Point Calibration Result for Active Power, channel 2
1 = Calibration Failed
0 = Calibration Successful
CAL_PA1: Single-Point Calibration Result for Active Power, channel 1
1 = Calibration Failed
0 = Calibration Successful
CAL_CURR2: Single-Point Calibration Result for RMS Current, channel 2
1 = Calibration Failed
0 = Calibration Successful
CAL_CURR1: Single-Point Calibration Result for RMS Current, channel 1
1 = Calibration Failed
0 = Calibration Successful
CAL_VOLT: Single-Point Calibration Result for RMS Voltage
1 = Calibration Failed
0 = Calibration Successful
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MCP39F511N
REGISTER 7-1:
EVENT CONFIGURATION REGISTER (CONTINUED)
bit 24
bit 23
bit 22
bit 21
bit 20
bit 19
bit 18
bit 17
bit 16
bit 15
bit 14
CAL_LF: Single-Point Calibration Result for Line Frequency
1 = Calibration Failed
0 = Calibration Successful
OVERPOW_PIN2: Event pin 2 operation for the Over Power event
1 = Event mapped to Event pin 2 only
0 = Event not mapped to a pin (Default)
OVERCUR_PIN2: Event pin 2 operation for the Over Current event
1 = Event mapped to Event pin 2 only
0 = Event not mapped to a pin (Default)
VSURGE_PIN2: Event pin 2 operation for the Voltage Surge event
1 = Event mapped to Event pin 2 only
0 = Event not mapped to a pin (Default)
VSAG_PIN2: Event pin 2 operation for the Voltage Sag event
1 = Event mapped to Event pin 2 only
0 = Event not mapped to a pin (Default)
OVERPOW_PIN1: Event pin 1 operation for the Over Power event
1 = Event mapped to Event pin 1 only
0 = Event not mapped to a pin (Default)
OVERCUR_PIN1: Event pin 1 operation for the Over Current event
1 = Event mapped to Event pin 1 only
0 = Event not mapped to a pin (Default)
VSURGE_PIN1: Event pin 1 operation for the Voltage Surge event
1 = Event mapped to Event pin 1 only
0 = Event not mapped to a pin (Default)
VSAG_PIN1: Event pin 1 operation for the Voltage Sag event
1 = Event mapped to Event pin 1 only
0 = Event not mapped to a pin (Default)
EVENT2_MANU Manual control of the Event2 pin
1 = Pin is logic high
0 = Pin is logic low (Default)
EVENT1_MANU Manual control of the Event1 pin
1 = Pin is logic high
0 = Pin is logic low (Default)
bit 13-12
bit 11
Unimplemented: Read as ‘0‘
OVERCUR_CL: Reset or clear bit for the Over Current event
1 = Event is cleared
0 = Event is not cleared (Default)
bit 10
bit 9
bit 8
bit 7
bit 6
OVERPOW_CL: Reset or clear bit for the Over Power event
1 = Event is cleared
0 = Event is not cleared (Default)
VSURGE_CL: Reset or clear bit for the Voltage Surge event
1 = Event is cleared
0 = Event is not cleared (Default)
VSAG_CL: Reset or clear bit for the Voltage Sag event
1 = Event is cleared
0 = Event is not cleared (Default)
VSUR_LA: Latching control of the Voltage Surge event
1 = Event is latched and needs to be cleared
0 = Event is not latched (Default)
VSAG_LA: Latching control of the Voltage Sag event
1 = Event is latched and needs to be cleared
0 = Event is not latched (Default)
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MCP39F511N
REGISTER 7-1:
EVENT CONFIGURATION REGISTER (CONTINUED)
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
OVERPOW_LA: Latching control of the Over Power event
1 = Event is latched and needs to be cleared
0 = Event is not latched (Default)
OVERCUR_LA: Latching control of the Over Current event
1 = Event is latched and needs to be cleared
0 = Event is not latched (Default)
VSUR_TST: Test control of the Voltage Surge event
1 = Simulated event is turned on
0 = Simulated event is turned off (Default)
VSAG_TST: Test control of the Voltage Sag event
1 = Simulated event is turned on
0 = Simulated event is turned off (Default)
OVERPOW_TST: Test control of the Over Power event
1 = Simulated event is turned on
0 = Simulated event is turned off (Default)
OVERCUR_TST: Test control of the Over Current event
1 = Simulated event is turned on
0 = Simulated event is turned off (Default)
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MCP39F511N
The output of the PWM is active only when the PWM
Control register has a value of 0x0001. The PWM out-
put is turned off when the register has a value of
0x0000.
8.0
8.1
PULSE-WIDTH MODULATION
(PWM)
Overview
The PWM output (see Figure 8-1) has a time base
(period) and a time that the output stays high (duty
cycle). The frequency of the PWM is the inverse of the
period (1/period).
The PWM output pin gives up to a 10-bit resolution of a
pulse-width modulated signal. The PWM output is con-
trolled by an internal timer inside the MCP39F511N,
FTIMER described in this section, with a base frequency
of 32 MHz.
The base period is defined as PTIMER and is
1/[32 MHz]. This 32 MHz time base is fixed due to the
8 MHz internal oscillator or 8 MHz external crystal.
Period
Duty Cycle
FIGURE 8-1:
PWM Output.
There are two registers that control the PWM output,
PWM Period and PWM Duty Cycle.
The 8-bit PWM Period is controlled by a 16-bit register
that contains the period bits and also the prescaler bits.
The PWM period bits are the most significant eight bits
in the register, and the prescaler value is represented
by the two least significant bits. These two values
together create the PWM Period (see Figure 8-2).
Prescaler
Period
255
PWM PERIOD
(8-bit)
1111111100000010
PWM Period Register
MSB
LSB
1023
PWM DUTY
(10-bit)
1111111100000010
PWM duty-cycle Register
FIGURE 8-2:
PWM Period and
Duty-Cycle Registers.
The 10-bit PWM Duty Cycle is controlled by a 16-bit
register where the eight most significant bits are the 8
MSB and the 2 LSB, corresponding to the 2 LSBs of the
10-bit value.
An example of the register’s values are shown in
Figure 8-2 with 255 for PWM Frequency (8-bit value)
and 1023 for the Duty cycle (10-bit value), with the
prescaler set to divide by 16 (1:0).
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MCP39F511N
8.2
PWM Period
The PWM period is specified by writing the PWM
Period bits of the PWM Period register. The PWM
period can be calculated using the following formula:
Equation 8-1:
PWM Period = [(PWM_Frequency) + 1] × 2 × PTIMER × (Prescale Value)
The PWM Period is defined as 1/[PWM frequency].
When PTIMER is equal to PWM Period, the following
two events occur on the next increment cycle:
• the PWM timer is cleared
• the PWM pin is set. Exception: If the PWM Duty
Cycle equals 0%, the PWM pin will not be set.
8.3
PWM Duty Cycle
The PWM duty cycle is specified by writing to the PWM
Duty-Cycle register. Up to 10-bit resolution is available.
The PWM Duty-Cycle register contains the eight MSbs
and the two LSbs. The following equations are used to
calculate the PWM duty cycle as a percentage or as
time:
EQUATION 8-1:
PWM Duty Cycle (%) = (PWM_DUTY CYCLE>)/(4 × PWM_FREQUENCY)
PWM Duty Cycle (time in s) = (PWM_DUTY_CYCLE) × PWM_TIMER_PERIOD/2 × (Prescale Value)
The PWM Duty-Cycle register can be written to at any
time, but the duty-cycle value is not latched until after a
period is complete.
The PWM registers and a two-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitch-less PWM
operation.
The maximum PWM resolution (bits) for a given PWM
frequency is shown in Equation 8-2.
EQUATION 8-2:
MAXIMUM PWM
RESOLUTION BASED ON
A FUNCTION OF PWM
FREQUENCY
2 FTIMER
log -------------------------
FPWM
PWM Resolution (max)
= --------------------------------------- b i t s
log2
Note:
If the PWM duty-cycle value is longer than
the PWM period, the PWM pin will not be
cleared.
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MCP39F511N
TABLE 8-2:
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS WITH
PWM_TIMER_FREQ = 32 MHz (DEFAULT)
PWM Frequency
1.95 kHz
31.25 kHz
62.5 kHz
125 kHz
2.67 MHz
4 MHz
Timer Prescaler
16
FFh
10
1
1
7Fh
9
1
3Fh
4
1
02h
3
1
01h
2
PWM Frequency Value
Maximum Resolution (bits)
FFh
10
REGISTER 8-1:
PWM PERIOD REGISTER
R/W-0
R/W-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
PWM_P<7:0>
bit 15
bit 8
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0 R/W-0
PRE<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-2
bit 1-0
PWM_P<7:0>: 8-bit PWM period value
Unimplemented: Read as ‘0‘
PRE<1:0>: PWM Prescaler
11= Unused
10= 1:16
01= 1:4
00= 1:1 (Default)
REGISTER 8-2:
PWM DUTY-CYCLE REGISTER
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
bit 8
DUTY<9:2>
bit 15
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R/W-0
DUTY<1:0>
bit 7
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 15-8
bit 7-2
bit 1-0
DUTY<9:2>: Upper 8 bits of 10-bit duty-cycle value
Unimplemented: Read as ‘0‘
DUTY<1:0>: Lower 2 bits of 10-bit duty-cycle value
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NOTES:
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MCP39F511N
9.3.1
USING THE AUTO-CALIBRATION
GAIN COMMAND
9.0
9.1
MCP39F511N CALIBRATION
Overview
By applying stable reference voltages and currents that
are equivalent to the values that reside in the target
Calibration Current, Calibration Voltage and Calibration
Active Power registers, the Auto-Calibration
Gaincommand can then be issued to the device.
Calibration compensates for ADC gain error,
component tolerances and overall noise in the system.
The device provides an on-chip calibration algorithm
that allows simple system calibration to be performed
quickly. The excellent analog performance of the A/D
converters on the MCP39F511N allows for
single-point calibration and single calibration
command to achieve accurate measurements.
After a successful calibration (response = ACK), a
Save Registers to Flashcommand can then be
issued to save the calibration constants calculated by
the device.
a
a
The following registers are set when the
Auto-Calibration Gaincommand is issued:
Calibration can be done by either using the predefined
auto-calibration commands, or by writing directly to the
calibration registers. If additional calibration points are
required (AC offset, Phase Compensation, DC offset),
the corresponding calibration registers are available to
the user and will be described separately in this
section.
• Gain Current RMS Channel 1
• Gain Current RMS Channel 2
• Gain Voltage RMS
• Gain Active Power Channel 1
• Gain Active Power Channel 2
9.2
Calibration Order
The channels can be calibrated individually or simulta-
neously depending on the instruction parameter byte
following the command byte.
The proper steps for calibration need to be maintained.
If the device runs on the internal oscillator, the line
frequency should be calibrated first using the
Auto-Calibrate Frequency command.
When this command is issued, the MCP39F511N
attempts to match the expected values to the mea-
sured values for all three output quantities by changing
the gain register based on the following formula:
The single-point Gain Calibration at Unity Power Factor
should be performed next. This can be done for an
individual channel or for both channels at the same
time, depending on the user’s calibration setup.
EQUATION 9-1:
Expected
Measured
GAIN
= GAIN
-------------------------
If non-unity displacement power factor measurements
are a concern, then the next step should be Phase
calibration followed by Reactive power gain calibration.
NEW
OLD
The same formula applies for Voltage RMS,
Current RMS and Active power. Since the gain
registers for all three quantities are 16-bit numbers,
the ratio of the expected value to the measured value
(which can be modified by changing the Range
register) and the previous gain must be such that the
equation yields a valid number. Here the limits are set
to be from 25,000 to 65,535. A new gain within this
range for all three limits will return an ACK for a
successful calibration, otherwise the command returns
a NAK for a failed calibration attempt.
Here is a summary on the order of calibration steps:
1. Line Frequency Calibration
2. Gain Calibration at PF = 1 for a single channel
or both
3. Phase Calibration at PF 1 for a single channel
or both (optional)
4. Reactive Gain Calibration at PF 1 for a single
channel or both (optional)
If calibrating a single channel at a time, repeat steps
2-4 for the second channel.
It is the user’s responsibility to ensure that the proper
range settings, PGA settings and hardware design
settings are correct to allow for successful calibration
using this command.
9.3
Single-Point Gain Calibrations at
Unity Power Factor
When using the device in AC mode with the high-pass
filters turned on, most offset errors are removed and
only a single-point gain calibration is required.
Setting the gain registers to properly produce the
desired outputs can be done manually by writing to the
appropriate register. The alternative method is to use
the auto-calibration commands described in this
section.
2015-2018 Microchip Technology Inc.
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MCP39F511N
issue. The best approach is to choose a range value
that places the new gain in the middle of the bounds of
the gain registers described above.
9.3.2
EXAMPLE OF RANGE SELECTION
FOR VALID CALIBRATION
In this example, the user applies a calibration current
of 1A to an uncalibrated system. The indicated value
in the Current RMS register is 2300 with the system's
specific shunt value, PGA gain, etc. The user expects
to see a value of 1000 in the Current RMS register
when 1A current is applied, meaning 1.000A with
1 mA resolution. Other given values are:
In a second example, when applying 1A, the user
expects an output of 1.0000A with 0.1 mA resolution.
The example is starting with the same initial values:
EQUATION 9-4:
Expected
--------------------------= 33480 --------------= 145565
OLD
10000
2300
GAIN
= GAIN
NEW
145565 65535
Measured
• the existing value for Gain Current RMS is 33480
• the existing value for Range is 12
By using Equation 9-1, the calculation for GainNEW
yields:
The GainNEW is much larger than the 16-bit limit of
65535, so fewer right-bit shifts must be introduced to
get the measured value closer to the expected value.
The user needs to compute the number of bit shifts
that will give a value lower than 65535. To estimate
this number:
EQUATION 9-2:
Expected
Measured
1000
2300
GAIN
= GAIN
--------------------------= 33480 -----------= 14556
NEW
OLD
14556 25 000
EQUATION 9-5:
When using the Auto-Calibration
Gain
145565
----------------- = 2.2
65535
command, the result is a failed calibration or a NAK
returned form the MCP39F511N, because the
resulting GainNEW is less than 25,000.
2.2 rounds to the closest integer value of 2. The range
value changes to 12 – 2 = 10; there are two less
right-bit shifts.
The new measured value will be 2300 x 22 = 9200.
The solution is to use the Range register to bring the
measured value closer to the expected value, such
that a new gain value can be calculated within the
limits specified above.
The Range register specifies the number of right-bit
shifts (equivalent to divisions by 2) after the
multiplication with the Gain Current RMS register.
Refer to Section 5.0 “Calculation Engine (CE)
Description” for information on the Range register.
EQUATION 9-6:
Expected
--------------------------= 33480 --------------= 36391
OLD
10000
9200
GAIN
= GAIN
NEW
Measured
25 000 36391 65535
Incrementing the Range register by 1 unit, performing
an additional right-bit shift or dividing in half is included
in the calculation. Increasing the current range from 12
to 13 yields the new measured Current RMS register
value of 2300/2 = 1150. The expected (1000) and
measured (1150) values are much closer now, so the
expected new gain should be within the limits:
The resulting new gain is within the limits, and the
device successfully calibrates Current RMS and
returns an ACK.
EQUATION 9-3:
Expected
Measured
1000
1150
GAIN
= GAIN
--------------------------= 33480 -----------= 29113
NEW
OLD
25 000 29113 65535
The resulting new gain is within the limits and the
device successfully calibrates Current RMS and
returns an ACK.
Notice that the range can be set to 14 and the result-
ing new gain will still be within limits
(GainNEW = 58226). However, since this gain value is
close to the limit of the 16-bit Gain register, variations
from system to system (component tolerances, etc.)
might create a scenario where the calibration is not
successful on some units and there would be a yield
2015-2018 Microchip Technology Inc.
DS20005473B-page 46
MCP39F511N
Based on Equation 9-9, the maximum angle in degrees
that can be compensated is ±3.2 degrees. If a larger
phase shift is required, contact your local Microchip
sales office.
9.4
Calibrating the Phase
Compensation Register
Phase compensation is provided to adjust for any
phase delay between the current and voltage paths.
Channel 1 and channel 2 both have independent phase
compensation registers. This procedure requires
sinusoidal current and voltage waveforms with a
significant phase shift between them, and significant
amplitudes. The recommended displacement power
factor for calibration is 0.5. The procedure for
calculating the phase compensation register is as
follows:
1. Determine what the difference is between the
angle corresponding to the measured power
factor (PFMEAS) and the angle corresponding to
the expected power factor (PFEXP), in degrees.
EQUATION 9-7:
Active Power
PFMEAS = ------------------------------------------------------------------
Calibration Power Active
180
ANGLEMEAS = acosPFMEAS --------
180
ANGLEEXP = acosPFEXP --------
2. Convert this from degrees to the resolution
provided in Equation 9-8.
There are 56 samples per line cycle. One line cycle is
360 degrees, so for each sample, the angle is 360
degrees/56 samples = 6.4257..degrees/sample.
Since the phase compensation has a bit of sign, the
maximum angle error that can be compensated is only
half, that is +/- 3.21..degrees.
Converting the angle to 8-bit resolution gives 256/6.42
degrees = 39.82..with 40 as an approximation.
EQUATION 9-8:
= ANGLE
– ANGLE
40
MEAS
EXP
3. Combine this additional phase compensation to
whatever value is currently in the phase
compensation and update the register. It is
recommended that Equation 9-9 be computed
in terms of an 8-bit two's complement-signed
value. The 8-bit result is placed in the least
significant byte of the 16-bit Phase
Compensation register.
EQUATION 9-9:
PhaseCompensation
= PhaseCompensation
+
OLD
NEW
2015-2018 Microchip Technology Inc.
DS20005473B-page 47
MCP39F511N
9.5
Offset/No-Load Calibrations
During offset calibrations, it is recommended that no
current be applied to the system. The system should be
in a no-load condition.
9.5.1
AC OFFSET CALIBRATION
There are three registers associated with the AC Offset
Calibration:
• Offset Current RMS Channel 1
• Offset Current RMS Channel 2
• Offset Active Power Channel 1
• Offset Active Power Channel 2
• Offset Reactive Power Channel 1
• Offset Reactive Power Channel 2
When computing the AC offset values, the respective
gain and range registers should be taken into
consideration according to the block diagrams in
Figures 5-2 and 5-4.
After
a
successful offset calibration,
a
Save
Registers to Flash command can then be issued
to save the calibration constants calculated by the
device.
2015-2018 Microchip Technology Inc.
DS20005473B-page 48
MCP39F511N
9.6
Calibrating the Line Frequency
Register
The Line Frequency register contains a 16-bit number
with a value equivalent to the input-line frequency as it
is measured on the voltage channel.
The measurement of the line frequency is only valid
from 45 to 65 Hz.
9.6.1
USING THE AUTO-CALIBRATE
FREQUENCY COMMAND
By applying a stable reference voltage with a constant
line frequency that is equivalent to the value that
resides in the LineFrequencyRef register, the
Auto-Calibrate Frequency command can then
be issued to the device.
After a successful calibration (response = ACK), a
Save Registers to Flashcommand can then be
issued to save the calibration constants calculated by
the device.
The
following
register
is
set
when
the
Auto-Calibrate Frequency command is issued:
• Gain Line Frequency
The formula used to calculate the new gain is shown in
Equation 9-1.
9.7
Retrieving Factory-Default
Calibration Values
After user calibration and a Save to Flashcommand
has been issued, it is possible to retrieve the
factory-default calibration values. This can be done by
writing 0xA5A5 to the Calibration Delimiter register,
issuing a Save to Flash, and then resetting the part.
This
procedure
will
retrieve
all
factory
default-calibration values and will remain in this state
until calibration has been performed again, and a Save
to Flashcommand has been issued.
2015-2018 Microchip Technology Inc.
DS20005473B-page 49
MCP39F511N
There are three commands that support access to the
EEPROM array.
10.0 EEPROM
The data EEPROM is organized as 16-bit wide
memory. Each word is directly addressable, and is
readable and writable across the entire VDD range. The
MCP39F511N has 256 16-bit words of EEPROM that is
organized in 32 pages for a total of 512 bytes.
• EEPROM Page Read(0x42)
• EEPROM Page Write(0x50)
• EEPROM Bulk Erase(0x4F)
TABLE 10-1: EXAMPLE EEPROM COMMANDS AND DEVICE RESPONSE
Command
Command ID BYTE 0
BYTE 1-N
# Bytes Successful Response
Page Read EEPROM
Page Write EEPROM
Bulk Erase EEPROM
0x42
0x50
0x4F
PAGE
PAGE + 16 BYTES OF DATA
None
2
18
1
ACK, Data, Checksum
ACK
ACK
TABLE 10-2: MCP39F511N EEPROM ORGANIZATION
Page
00
02
04
06
08
0A
0C
0E
0
0000
0010
0020
0030
0040
0050
0060
0070
0080
0090
00A0
00B0
00C0
00D0
00E0
00F0
0100
0110
0120
0130
0140
0150
0160
0170
0180
0190
01A0
01B0
01C0
01D0
01E0
01F0
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
FFFF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
2015-2018 Microchip Technology Inc.
DS20005473B-page 50
MCP39F511N
NOTES:
2015-2018 Microchip Technology Inc.
DS20005473B-page 51
MCP39F511N
11.0 PACKAGING INFORMATION
11.1 Package Marking Information
28-Lead QFN (5x5x0.9 mm)
Example
PIN 1
PIN 1
39F511N
XXXXXXX
XXXXXXX
YYWWNNN
-E/MQ
e
3
1549256
Legend: XX...X Customer-specific information
Y
Year code (last digit of calendar year)
YY
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2015-2018 Microchip Technology Inc.
DS20005473B-page 52
MCP39F511N
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
A
B
E
N
NOTE 1
1
2
(DATUM B)
(DATUM A)
2X
0.10 C
2X
TOP VIEW
0.10 C
0.10 C
A1
C
A
SEATING
PLANE
28X
A3
0.08 C
0.10
SIDE VIEW
C A B
0.10
D2
C A B
E2
28X K
2
1
NOTE 1
28X L
N
28X b
0.10
0.05
C A B
C
e
BOTTOM VIEW
Microchip Technology Drawing C04-140C Sheet 1 of 2
2015-2018 Microchip Technology Inc.
DS20005473B-page 53
MCP39F511N
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x0.9 mm Body [QFN]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
MILLIMETERS
NOM
MIN
MAX
Number of Pins
Pitch
Overall Height
Standoff
Contact Thickness
Overall Width
Exposed Pad Width
Overall Length
Exposed Pad Length
Contact Width
Contact Length
Contact-to-Exposed Pad
N
28
0.50 BSC
0.90
e
A
A1
A3
E
E2
D
D2
b
L
0.80
0.00
1.00
0.05
0.02
0.20 REF
5.00 BSC
3.25
5.00 BSC
3.25
0.25
0.40
-
3.15
3.35
3.15
0.18
0.35
0.20
3.35
0.30
0.45
-
K
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-140C Sheet 2 of 2
2015-2018 Microchip Technology Inc.
DS20005473B-page 54
MCP39F511N
28-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5 mm Body [QFN] Land Pattern
With 0.55 mm Contact Length
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Microchip Technology Drawing C04-2140A
2015-2018 Microchip Technology Inc.
DS20005473B-page 55
MCP39F511N
APPENDIX A: REVISION HISTORY
Revision B (January 2018)
• Removed all references to DC monitoring.
• Minor typographical changes.
Revision A (December 2015)
• Original release of this document.
2015-2017 Microchip Technology Inc.
DS20005473B-page 56
MCP39F511N
NOTES:
DS20005473B-page 57
2015-2017 Microchip Technology Inc.
MCP39F511N
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
(1)
[X]
PART NO.
Device
X
/XX
Examples:
a) MCP39F511N-E/MQ: Extended temperature,
28LD 5x5 QFN package
Tape and Temperature Package
Reel
Range
b) MCP39F511NT-E/MQ: Tape and Reel,
Extended temperature,
28LD 5x5 QFN package
Device:
MCP39F511N: Dual-Channel Single-Phase
Power-Monitoring IC with Calculation
Tape and Reel Option: Blank
= Standard packaging (tube or tray)
T
= Tape and Reel (1)
Note 1: Tape and Reel identifier only appears in the
catalog part number description. This identi-
fier is used for ordering purposes and is not
printed on the device package. Check with
your Microchip sales office for package
availability for the Tape and Reel option.
Temperature Range:
Package:
E
= -40°C to +125°C
MQ
= Plastic Quad Flat, No Lead Package
5x5x0.9 mm body (QFN), 28-lead
2015-2017 Microchip Technology Inc.
DS20005473B-page 58
MCP39F511N
NOTES:
2015-2017 Microchip Technology Inc.
DS20005473B-page 59
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BeaconThings, BitCloud, chipKIT, chipKIT
logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR,
Heldo, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, LINK
MD, maXStylus, maXTouch, MediaLB, megaAVR, MOST, MOST
logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32
logo, Prochip Designer, QTouch, RightTouch, SAM-BA, SpyNIC,
SST, SST Logo, SuperFlash, tinyAVR, UNI/O, and XMEGA are
registered trademarks of Microchip Technology Incorporated in
the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoCompanion, CryptoController,
dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM,
ECAN, EtherGREEN, In-Circuit Serial Programming, ICSP, Inter-
Chip Connectivity, JitterBlocker, KleerNet, KleerNet logo, Mindi,
MiWi, motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PureSilicon, QMatrix,
RightTouch logo, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENAare trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip Technology
Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2017, Microchip Technology Incorporated, All Rights Reserved.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
ISBN: 978-1-5224-2585-4
== ISO/TS 16949 ==
2017 Microchip Technology Inc.
Advance Information
DS20005473B-page 60
Worldwide Sales and Service
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DS20005473B-page 61
2017 Microchip Technology Inc.
10/25/17
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