MCP4024T-103E/OT_技术文档

MCP4021/2/3/4

Low-Cost NV Digital POT with WiperLock™ Technology

Package Types

Features

MCP4021

MCP4022

• Non-volatile Digital Potentiometer in SOT-23,

SOIC, MSOP and DFN packages

SOIC, MSOP, DFN

Potentiometer

SOT-23-6

Rheostat

• 64 Taps: 63 Resistors with Taps to terminal A and

terminal B

V

A

8

7

6

5

U/D

1

2

3

4

1

2

3

6

5

4

DD

A

W

• Simple Up/Down (U/D) Protocol

V

W

CS

NC

B

SS

A

SS

• Power-on Recall of Saved Wiper Setting

• Resistance Values: 2.1 kΩ, 5 kΩ, 10 kΩ or 50 kΩ

• Low Tempco:

A

B

U/D

B

W

CS

- Absolute (Rheostat): 50 ppm (0°C to 70°C typ.)

- Ratiometric (Potentiometer): 10 ppm (typ.)

• Low Wiper Resistance: 75Ω (typ.)

MCP4023

MCP4024

SOT-23-6

Potentiometer

SOT-23-5

Rheostat

A

V

W

5

V

• WiperLock™ Technology to Secure the wiper

setting in non-volatile memory (EEPROM)

A

1

2

3

6

5

4

1

2

3

DD

W

V

W

CS

V

SS

W

B

A

• High-Voltage Tolerant Digital Inputs: Up to 12.5V

• Low-Power Operation: 1 µA Max Static Current

• Wide Operating Voltage: 2.7V to 5.5V

• Extended Temperature Range: -40°C to +125°C

• Wide Bandwidth (-3 dB) Operation:

U/D

CS

4

Block Diagram

A

- 4 MHz (typ.) for 2.1 kΩ device

V_DD

Power-Up

and

Brown-Out

Control

Description

V_SS

The MCP4021/2/3/4 devices are non-volatile, 6-bit

digital potentiometers that can be configured as either a

potentiometer or rheostat. The wiper setting is

controlled through a simple Up/Down (U/D) serial

interface.

2-Wire

Interface

and

Control

Logic

W

CS

U/D

These device’s implement Microchip’s WiperLock tech-

nology, which allows application-specific calibration

settings to be secured in the EEPROM without

requiring the use of an additional write-protect pin.

EEPROM and

WiperLock™

Technology

B

Device Features

Resistance (typical)

V_DD

Operating

Range

Wiper

Configuration

Memory

Type

# of

Steps

Control WiperLock™

Interface Technology

Device

Options (kΩ)

Wiper (Ω)

MCP4021 Potentiometer ⁽¹⁾

EE

2.1, 5.0, 10.0, 50.0

75

64 2.7V - 5.5V

64 2.7V- 5.5V

U/D

Yes

MCP4022

MCP4023

MCP4024

Rheostat

Potentiometer

Rheostat

64 2.7V - 5.5V

Note 1: Floating either terminal (A or B) allows the device to be used in Rheostat mode.

.

DS21945E-page 1

MCP4021/2/3/4

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V_DD............................................................................................................. 6.5V

CS and U/D inputs w.r.t V_{SS....................................}-0.3V to 12.5V

A, B and W terminals w.r.t V_{SS....................}-0.3V to V_DD+ 0.3V

Current at Input Pins ..................................................±10 mA

Current at Supply Pins ...............................................±10 mA

Current at Potentiometer Pins ...................................±2.5 mA

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................-55°C to +125°C

ESD protection on all pins ...........≥ 4 kV (HBM), ≥ 400V (MM)

Maximum Junction Temperature (T_J)..........................+150°C

AC/DC CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.

T_A= -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD= 5.5V, V_SS= 0V,

T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Operating Voltage Range

CS Input Voltage

V_DD

V_CS

2.7

—

5.5

V

V_SS

12.5

The CS pin will be at one of three

input levels (V_IL, V_IHor V_IHH).

(Note 6)

Supply Current

I_DD

—

45

15

—

1

µA

5.5V, CS = V_SS, f_U/D= 1 MHz

2.7V, CS = V_SS, f_U/D= 1 MHz

Serial Interface Inactive

0.3

(CS = V_IH, U/D = V_IH

)

—

0.6

2.1

5

3

mA

kΩ

Taps

Ω

EE Write cycle, T_A= +25°C

-202 devices (Note 1)

-502 devices (Note 1)

-103 devices (Note 1)

-503 devices (Note 1)

No Missing Codes

Note 6

Resistance

(± 20%)

R_AB

1.68

4.0

2.52

6.0

8.0

10

50

12.0

60.0

40.0

Resolution

N

64

R_AB/ 63

Step Resistance

R_S

—

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS. (-202 devices V_A= 4V).

3: MCP4021/23 only, test conditions are: I_W= 1.9 mA, code = 00h.

4: MCP4022/24 only, test conditions are:

Current at Voltage

Comments

Device

Resistance

5.5V

2.7V

2.1 kΩ

5 kΩ

2.25 mA

1.4 mA

450 µA

90 µA

1.1 mA

450 µA

210 µA

40 µA

MCP4022 includes V_WZSE

MCP4024 includes V_WFSE

10 kΩ

50 kΩ

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and temperature. See

Section 6.0 “Resistor” for additional information.

8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.

DS21945E-page 2

MCP4021/2/3/4

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.

T_A= -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD= 5.5V, V_SS= 0V,

T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Wiper Resistance (Note 3, Note 4)

R_W

—

70

125

325

—

Ω

5.5V

2.7V

Nominal Resistance Tempco

Ratiometeric Tempco

ΔR/ΔT

50

ppm/°C T_A= -20°C to +70°C

ppm/°C T_A= -40°C to +85°C

ppm/°C T_A= -40°C to +125°C

100

150

10

—

ΔV_WA/ΔT

—

ppm/°C MCP4021 and MCP4023 only,

code = 1Fh

Full-Scale Error

V_WFSE

V_WZSE

N

-0.5

-0.1

+0.5

LSb

Bits

LSb

Code 3Fh (MCP4021/23 only)

Code 00h (MCP4021/23 only)

Zero-Scale Error

+0.1

Monotonicity

Yes

Potentiometer Integral Non-linearity

INL

-0.5

±0.25

+0.5

MCP4021/23 only (Note 2)

Potentiometer Differential

Non-linearity

DNL

Resistor Terminal Input Voltage

Range (Terminals A, B and W)

V_A,V_W,V_B

Vss

—

V_DD

V

Note 5, Note 6

Maximum current through A, W or B

Leakage current into A, W or B

I_W

—

100

75

2.5

—

mA

nA

Note 6

I_WL

MCP4021 A = W = B = V_SS

MCP4022/23 A = W = V_SS

MCP4024 W = V_SS

f =1 MHz, code = 1Fh

nA

Capacitance (P_A)

Capacitance (P_w)

Capacitance (P_B)

Bandwidth -3 dB

C_AW

C_W

pF

120

75

pF

C_BW

BW

pF

4

MHz

-202

Code = 1F,

devices

output load = 30 pF

—

2

1

—

MHz

kHz

-502

devices

-103

devices

200

-503

devices

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS. (-202 devices V_A= 4V).

3: MCP4021/23 only, test conditions are: I_W= 1.9 mA, code = 00h.

4: MCP4022/24 only, test conditions are:

Current at Voltage

Comments

Device

Resistance

5.5V

2.7V

2.1 kΩ

5 kΩ

2.25 mA

1.4 mA

450 µA

90 µA

1.1 mA

450 µA

210 µA

40 µA

MCP4022 includes V_WZSE

MCP4024 includes V_WFSE

10 kΩ

50 kΩ

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and temperature. See

Section 6.0 “Resistor” for additional information.

8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.

DS21945E-page 3

MCP4021/2/3/4

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.

T_A= -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD= 5.5V, V_SS= 0V,

T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat Integral Non-linearity

MCP4021 (Note 4, Note 8)

MCP4022 and MCP4024 (Note 4)

R-INL

-0.5

-8.5

±0.25

+4.5

+0.5

+8.5

LSb

-202

devices

(2.1 kΩ)

5.5V

2.7V (Note 7)

-0.5

-5.5

±0.25

+2.5

+0.5

+5.5

LSb

-502

devices

(5 kΩ)

5.5V

2.7V (Note 7)

-0.5

-3

±0.25

+1

+0.5

+3

LSb

-103

devices

(10 kΩ)

5.5V

2.7V (Note 7)

-0.5

-1

±0.25

+0.25

+0.5

+1

LSb

-503

devices

(50 kΩ)

5.5V

2.7V (Note 7)

Rheostat Differential Non-linearity

MCP4021 (Note 4, Note 8)

MCP4022 and MCP4024 (Note 4)

R-DNL

-0.5

-1

±0.25

+0.5

+2

LSb

-202

devices

(2.1 kΩ)

5.5V

2.7V (Note 7)

-0.5

-1

±0.25

+0.25

+0.5

LSb

-502

devices

(5 kΩ)

5.5V

+1.25

2.7V (Note 7)

-0.5

-1

±0.25

0

+0.5

+1

LSb

-103

devices

(10 kΩ)

5.5V

2.7V (Note 7)

-0.5

±0.25

0

+0.5

LSb

-503

devices

(50 kΩ)

5.5V

2.7V (Note 7)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS. (-202 devices V_A= 4V).

3: MCP4021/23 only, test conditions are: I_W= 1.9 mA, code = 00h.

4: MCP4022/24 only, test conditions are:

Current at Voltage

Comments

Device

Resistance

5.5V

2.7V

2.1 kΩ

5 kΩ

2.25 mA

1.4 mA

450 µA

90 µA

1.1 mA

450 µA

210 µA

40 µA

MCP4022 includes V_WZSE

MCP4024 includes V_WFSE

10 kΩ

50 kΩ

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and temperature. See

Section 6.0 “Resistor” for additional information.

8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.

DS21945E-page 4

MCP4021/2/3/4

AC/DC CHARACTERISTICS (CONTINUED)

Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges.

T_A= -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for V_DD= 5.5V, V_SS= 0V,

T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (CS, U/D)

Input High Voltage

V_IH

V_IL

0.7 V_DD

—

V

Input Low Voltage

0.3 V_DD

12.5⁽⁶⁾

High-Voltage Input Entry Voltage

V_IHH

8.5

Threshold for WiperLock™

Technology

High-Voltage Input Exit Voltage

CS Pull-up/Pull-down Resistance

CS Weak Pull-up/Pull-down Current

Input Leakage Current

CS and U/D Pin Capacitance

RAM (Wiper) Value

V_IHH

R_CS

—

-1

—

16

V_DD+0.8⁽⁶⁾

V

—

1

kΩ

µA

pF

V_DD= 5.5V, V_CS= 3V

V_IN= V_DD

I_PU

170

—

I_IL

C_IN, C_OUT

10

—

f_C= 1 MHz

Value Range

N

0h

—

3Fh

hex

EEPROM

Endurance

E_ndurance

—

1M

—

Cycles

hex

EEPROM Range

N

0h

3Fh

Initial Factory Setting

Power Requirements

1Fh

hex

WiperLock Technology = Off

Power Supply Sensitivity

(MCP4021 and MCP4023 only)

PSS

—

0.0015

0.0035

%/%

V_DD= 4.5V to 5.5V, V_A= 4.5V,

Code = 1Fh

V

_DD= 2.7V to 4.5V, V_A= 2.7V,

Code = 1Fh

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS. (-202 devices V_A= 4V).

3: MCP4021/23 only, test conditions are: I_W= 1.9 mA, code = 00h.

4: MCP4022/24 only, test conditions are:

Current at Voltage

Comments

Device

Resistance

5.5V

2.7V

2.1 kΩ

5 kΩ

2.25 mA

1.4 mA

450 µA

90 µA

1.1 mA

450 µA

210 µA

40 µA

MCP4022 includes V_WZSE

MCP4024 includes V_WFSE

10 kΩ

50 kΩ

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and temperature. See

Section 6.0 “Resistor” for additional information.

8: The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested.

DS21945E-page 5

MCP4021/2/3/4

t_CSHI

t_CSLO

CS

1/f_UD

t_LUC

t_LCUF

t_LUC

t_LO

t_LCUF

U/D

t_HI

t_LCUR

t_S

W

FIGURE 1-1:

Increment Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.

Extended (E): V_DD= +2.7V to 5.5V, T_A= -40°C to +125°C.

Parameters

CS Low Time

Sym

Min

Typ

Max

Units

Conditions

t_CSLO

t_CSHI

t_LUC

t_LCUF

t_LCUR

t_HI

5

500

3

—

5

—

1

µs

ns

CS High Time

U/D to CS Hold Time

CS to U/D Low Setup Time

CS to U/D High Setup Time

U/D High Time

ns

µs

500

—

ns

U/D Low Time

t_LO

ns

Up/Down Toggle Frequency

Wiper Settling Time

f_UD

MHz

µs

t_S

0.5

1

—

5

2.1 kΩ, C_L= 100 pF

µs

5 kΩ, C_L= 100 pF

10 kΩ, C_L= 100 pF

50 kΩ, C_L= 100 pF

2

µs

10

—

µs

Wiper Response on Power-up

Internal EEPROM Write Time

t_PU

twc

200

—

ns

—

ms

@25°C

—

10

-40°C to +125°C

DS21945E-page 6

MCP4021/2/3/4

t_CSHI

t_CSLO

CS

1/f_UD

t_LUC

t_LCUF

t_LUC

t_HI

U/D

t_LO

t_LCUR

t_S

W

FIGURE 1-2:

Decrement Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.

Extended (E): V_DD= +2.7V to 5.5V, T_A= -40°C to +125°C.

Parameters

CS Low Time

Sym

Min

Typ

Max

Units

Conditions

t_CSLO

t_CSHI

t_LUC

t_LCUF

t_LCUR

t_HI

5

500

3

—

5

—

1

µs

ns

CS High Time

U/D to CS Hold Time

CS to U/D Low Setup Time

CS to U/D High Setup Time

U/D High Time

ns

µs

500

—

ns

U/D Low Time

t_LO

ns

Up/Down Toggle Frequency

Wiper Settling Time

f_UD

MHz

µs

t_S

0.5

1

—

5

2.1 kΩ, C_L= 100 pF

µs

5 kΩ, C_L= 100 pF

10 kΩ, C_L= 100 pF

50 kΩ, C_L= 100 pF

2

µs

10

—

µs

Wiper Response on Power-up

Internal EEPROM Write Time

t_PU

twc

200

—

ns

—

ms

@25°C

—

10

-40°C to +125°C

DS21945E-page 7

MCP4021/2/3/4

t_CSHI

t_CSLO

12V

CS

5V

1/f_UD

t_HUCt_HCUF

t_HUC

t_LO

t_HCUF

U/D

t_HCUR

W

t_HI

t_S

FIGURE 1-3:

High-Voltage Increment Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.

Extended (E): V_DD= +2.7V to 5.5V, T_A= -40°C to +125°C.

Parameters

CS Low Time

Sym

Min

Typ

Max

Units

Conditions

t_CSLO

t_CSHI

t_HI

5

500

—

5

—

1

µs

ns

CS High Time

U/D High Time

ns

U/D Low Time

t_LO

ns

Up/Down Toggle Frequency

HV U/D to CS Hold Time

HV CS to U/D Low Setup Time

HV CS to U/D High Setup Time

Wiper Settling Time

f_UD

MHz

µs

t_HUC

t_HCUF

t_HCUR

t_S

1.5

8

—

5

µs

4.5

0.5

1

µs

2.1 kΩ, C_L= 100 pF

µs

5 kΩ, C_L= 100 pF

10 kΩ, C_L= 100 pF

50 kΩ, C_L= 100 pF

2

µs

10

—

µs

Wiper Response on Power-up

Internal EEPROM Write Time

t_PU

twc

200

—

ns

—

ms

@25°C

—

10

-40°C to +125°C

DS21945E-page 8

MCP4021/2/3/4

t_CSHI

t_CSLO

12V

5V

CS

1/f_UD

t_HUC

t_HCUF

t_HUC

t_HI

U/D

t_LO

t_HCUR

t_S

W

FIGURE 1-4:

High-Voltage Decrement Timing Waveform.

SERIAL TIMING CHARACTERISTICS

Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges.

Extended (E): V_DD= +2.7V to 5.5V, T_A= -40°C to +125°C.

Parameters

CS Low Time

Sym

Min

Typ

Max

Units

Conditions

t_CSLO

t_CSHI

t_HI

5

500

—

5

—

1

µs

ns

CS High Time

U/D High Time

ns

U/D Low Time

t_LO

ns

Up/Down Toggle Frequency

HV U/D to CS Hold Time

HV CS to U/D Low Setup Time

HV CS to U/D High Setup Time

Wiper Settling Time

f_UD

MHz

µs

t_HUC

t_HCUF

t_HCUR

t_S

1.5

8

—

5

µs

4.5

0.5

1

µs

2.1 kΩ, C_L= 100 pF

µs

5 kΩ, C_L= 100 pF

10 kΩ, C_L= 100 pF

50 kΩ, C_L= 100 pF

2

µs

10

—

µs

Wiper Response on Power-up

Internal EEPROM Write Time

t_PU

twc

200

—

ns

—

ms

@25°C

—

10

-40°C to +125°C

DS21945E-page 9

MCP4021/2/3/4

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 6L-SOT-23

Thermal Resistance, 8L-DFN (2x3)

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-SOIC

T_A

-40

-65

—

+125

+150

°C

θ_JA

—

255

230

85

—

°C/W

206

117

DS21945E-page 10

MCP4021/2/3/4

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

80

250

200

150

100

50

1000

800

600

400

200

0

2.7V -40°C

70

60

50

40

30

20

10

0

2.7V 25°C

2.7V 85°C

2.7V 125°C

5.5V -40°C

5.5V 25°C

5.5V 85°C

5.5V 125°C

I_CS

-200

-400

-600

-800

-1000

R_CS

0

0.20

0.40

0.60

0.80

1.00

9

8

7

6

5

V_CS(V)

4

3

2

1

f

_U/D(MHz)

FIGURE 2-1:

Device Current (I ) vs. U/D

FIGURE 2-4:

CS Pull-up/Pull-down

DD

Frequency (f ) and Ambient Temperature

Resistance (R ) and Current (I ) vs. CS Input

U/D

CS

(V = 2.7V and 5.5V).

Voltage (V ) (V = 5.5V).

DD

CS DD

600.0

500.0

400.0

300.0

200.0

100.0

0.0

12

10

8

1.8V Entry

2.7V Entry

5.5V Entry

1.8V Exit

2.7V Exit

5.5V Exit

V

_DD= 5.5V

6

4

V_DD= 2.7V

2

0

-40

25

85

125

-40 -20

0

20

40

60

80 100 120

Ambient Temperature (°C)

FIGURE 2-2:

Write Current (I

) vs.

FIGURE 2-5:

CS High Input Entry/Exit

WRITE

Ambient Temperature and V

.

Threshold vs. Ambient Temperature and V

.

DD

0.8

0.7

V_DD= 5.5V

0.6

0.5

0.4

0.3

0.2

0.1

0.0

V_DD= 2.7V

-40

25

85

125

Ambient Temperature (°C)

FIGURE 2-3:

Device Current (I

) vs.

SHDN

Ambient Temperature and V . (CS = V ).

DD

DS21945E-page 11

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

140

120

100

80

0.075

0.05

120

100

80

60

40

20

0

0.8

0.6

0.4

0.2

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

0.025

0

INL

DNL

60

-0.025

-0.05

-0.075

-0.1

40

DNL

RW

-0.2

-0.4

RW

20

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-6:

2.1 kΩ Pot Mode – R (Ω),

FIGURE 2-8:

2.1 kΩ Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

500

10

8

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

400

0.1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

400

300

200

100

0

300

200

100

0

0.05

0

INL

6

INL

4

DNL

RW

2

-0.05

-0.1

0

DNL

RW

-2

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-7:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

2.1 kΩ Pot Mode – R (Ω),

FIGURE 2-9:

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

2.1 kΩ Rheo Mode – R

W

DD

DS21945E-page 12

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

2080

2060

2500

2000

1500

1000

500

-40°C

25°C

85°C

125°C

V_DD= 5.5V

2040

2020

V_DD= 2.7V

2000

0

-40

0

40

80

120

0

8

16

24

32

40

Wiper Setting (decimal)

48

56

64

Ambient Temperature (°C)

FIGURE 2-10:

2.1 kΩ – Nominal

FIGURE 2-11:

2.1 kΩ – R

(Ω) vs. Wiper

WB

Resistance (Ω) vs. Ambient Temperature and

Setting and Ambient Temperature.

V

.

DD

DS21945E-page 13

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

WIPER

U/D

FIGURE 2-12:

2.1 kΩ – Low-Voltage

FIGURE 2-15:

2.1 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V).

Increment Wiper Settling Time (V = 2.7V).

DD

WIPER

U/D

WIPER

U/D

FIGURE 2-13:

2.1 kΩ – Low-Voltage

FIGURE 2-16:

2.1 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V).

Increment Wiper Settling Time (V = 5.5V).

DD

WIPER

V_DD

FIGURE 2-14:

2.1 kΩ – Power-Up Wiper

Response Time.

DS21945E-page 14

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

140

120

100

80

0.075

0.05

120

100

80

60

40

20

0

0.6

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.4

0.2

0

0.025

0

INL

DNL

60

-0.025

-0.05

-0.075

-0.1

-0.2

-0.4

-0.6

40

RW

20

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-17:

5 kΩ Pot Mode – R (Ω),

FIGURE 2-19:

5 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

Ambient Temperature (V = 5.5V)

DD

450

0.1

600

5

4

3

2

1

0

-1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

400

350

300

250

200

150

100

50

0.075

0.05

0.025

0

500

400

300

200

100

0

INL

DNL

-0.025

-0.05

-0.075

-0.1

RW

DNL

0

-0.125

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-18:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

5 kΩ Pot Mode – R (Ω),

FIGURE 2-20:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

5 kΩ Rheo Mode – R (Ω),

W

DD

DS21945E-page 15

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

4950

6000

5000

4000

3000

2000

1000

0

2.7V Vdd

-40°C

25°C

85°C

125°C

5.5V Vdd

4925

4900

4875

V_DD= 5.5V

4850

4825

V_DD= 2.7V

4800

-40 -20

0

20 40 60 80 100 120

0

8

16

24

32

40

48

56

64

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-21:

5 kΩ – Nominal Resistance

FIGURE 2-22:

5 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS21945E-page 16

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

WIPER

U/D

FIGURE 2-23:

5 kΩ – Low-Voltage

FIGURE 2-25:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V).

Increment Wiper Settling Time (V = 2.7V).

DD

WIPER

U/D

WIPER

U/D

FIGURE 2-24:

5 kΩ – Low-Voltage

FIGURE 2-26:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V).

Increment Wiper Settling Time (V = 5.5V).

DD

DS21945E-page 17

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

60

40

20

0

0.05

0.025

0

120

100

80

60

40

20

0

0.15

0.1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

DNL

INL

0.05

0

DNL

INL

-0.025

-0.05

-0.075

-0.1

-0.05

-0.1

-0.15

RW

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-27:

10 kΩ Pot Mode – R (Ω),

FIGURE 2-29:

10 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

450

0.05

500

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

2.5

400

350

300

250

200

150

100

50

0.025

0

400

300

200

100

0

DNL

INL

1.5

INL

-0.025

-0.05

-0.075

-0.1

0.5

DNL

-0.5

-1.5

-2.5

RW

0

-0.125

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-28:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

10 kΩ Pot Mode – R (Ω),

FIGURE 2-30:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

10 kΩ Rheo Mode – R (Ω),

W

DD

DS21945E-page 18

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

10250

10230

10210

10190

10170

10150

10130

12000

10000

8000

6000

4000

2000

0

-40°C

25°C

85°C

125°C

V_DD= 5.5V

10110

10090

10070

10050

V_DD= 2.7V

-40 -20

0

20 40 60 80 100 120

0

8

16

24

32

40

Wiper Setting (decimal)

48

56

64

Ambient Temperature (°C)

FIGURE 2-31:

10 kΩ – Nominal Resistance

FIGURE 2-32:

10 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS21945E-page 19

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

WIPER

U/D

FIGURE 2-33:

10 kΩ – Low-Voltage

FIGURE 2-35:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V).

Increment Wiper Settling Time (V = 2.7V).

DD

WIPER

U/D

WIPER

U/D

FIGURE 2-34:

10 kΩ – Low-Voltage

FIGURE 2-36:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V).

Increment Wiper Settling Time (V = 5.5V).

DD

DS21945E-page 20

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

200

160

120

80

0.1

200

150

100

50

0.15

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.05

0

0.1

INL

DNL

0.05

0

INL

-0.05

-0.1

-0.15

RW

40

-0.05

-0.1

DNL

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-37:

50 kΩ Pot Mode – R (Ω),

FIGURE 2-39:

50 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

600

0.05

0.025

0

600

1.5

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

500

400

300

200

100

0

500

400

300

200

100

0

RW

DNL

0.5

0

INL

DNL

-0.025

-0.05

-0.075

-0.1

INL

-0.5

-1

RW

-1.5

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

0

8

16 24 32 40 48 56

Wiper Setting (decimal)

FIGURE 2-38:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

50 kΩ Pot Mode – R (Ω),

FIGURE 2-40:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 2.7V).

50 kΩ Rheo Mode – R (Ω),

W

DD

DS21945E-page 21

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

60000

50000

40000

30000

20000

10000

0

49800

49600

49400

-40C

25C

85C

125C

V_DD= 5.5V

49200

49000

48800

48600

48400

48200

48000

V_DD= 2.7V

-40 -20

0

20 40 60 80 100 120

0

8

16

24

32

40

Wiper Setting (decimal)

48

56

64

Ambient Temperature (°C)

FIGURE 2-41:

50 kΩ – Nominal Resistance

FIGURE 2-42:

50 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS21945E-page 22

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

U/D

WIPER

FIGURE 2-43:

50 kΩ – Low-Voltage

FIGURE 2-46:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V).

Increment Wiper Settling Time (V = 2.7V).

DD

U/D

WIPER

FIGURE 2-44:

50 kΩ – Low-Voltage

FIGURE 2-47:

50 kΩ - Low-Voltage

Decrement Wiper Settling Time (V = 5.5V).

Increment Wiper Settling Time (V = 5.5V).

DD

WIPER

V_DD

FIGURE 2-45:

50 kΩ – Power-Up Wiper

Response Time.

DS21945E-page 23

MCP4021/2/3/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

4.5

A

2.1 k:

4

3.5

3

+5V

W

V_IN

V_OUT

+

~

2.5

2

5 k:

-

OFFSET

GND

DUT

1.5

1

10 k:

50 k:

B

0.5

0

2.5V DC

-40

25

125

Temperature (°C)

FIGURE 2-49:

-3 dB Bandwidth Test

FIGURE 2-48:

-3 dB Bandwidth vs.

Circuit.

Temperature.

DS21945E-page 24

MCP4021/2/3/4

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

Pin Number

Type

Buffer

Type

MCP4022

MCP4023

(SOT-23-6)

Symbol

Function

MCP4021

(SOIC-8)

MCP4024

(SOT-23-5)

1

2

3

4

5

6

7

8

1

2

1

2

V_DD

V_SS

A

P

—

Positive Power Supply Input

Ground

6

—

5

I/O

I

A

Potentiometer Terminal A

Potentiometer Wiper Terminal

Chip Select Input

5

W

A

4

CS

B

TTL

A

—

3

—

3

I/O

—

I

Potentiometer Terminal B

No Connection

NC

U/D

—

TTL

Increment/Decrement Input

Legend: TTL = TTL compatible input

A = Analog input

O = Output

I = Input

P = Power

3.1

Positive Power Supply Input (V_DD

)

3.4

Potentiometer Wiper (W) Terminal

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SSand can range

from 2.7V to 5.5V. A decoupling capacitor on V_DD(to

The terminal W pin is connected to the internal potenti-

ometer’s terminal W (the wiper). The wiper terminal is

the adjustable terminal of the digital potentiometer. The

terminal W pin does not have a polarity relative to

terminals A or B pins. The terminal W pin can support

both positive and negative current. The voltage on

V_SS

)

is recommended to achieve maximum

performance.

teminal W must be between V_SSand V_DD

.

3.2

Ground (V_SS)

The V_SSpin is the device ground reference.

3.5

Potentiometer Terminal B

The terminal B pin is connected to the internal potenti-

ometer’s terminal B (available on some devices). The

potentiometer’s terminal B is the fixed connection to the

0x00 terminal of the digital potentiometer.

3.3

Potentiometer Terminal A

The terminal A pin is connected to the internal potenti-

ometer’s terminal A (available on some devices). The

potentiometer’s terminal A is the fixed connection to the

0x3F terminal of the digital potentiometer.

The terminal B pin is available on the MCP4021 device.

The terminal B pin does not have a polarity relative to

the terminal W or A pins. The terminal B pin can

support both positive and negative current. The voltage

The terminal A pin is available on the MCP4021,

MCP4022 and MCP4023 devices. The terminal A pin

does not have a polarity relative to the terminal W or B

pins. The terminal A pin can support both positive and

negative current. The voltage on teminal A must be

on teminal B must be between V_SSand V_DD

.

The terminal B pin is not available on the MCP4022,

MCP4023 and MCP4024 devices.

between V_SSand V_DD

.

For the MCP4023 and MCP4024, the internal potenti-

The terminal A pin is not available on the MCP4024.

The potentiometer’s terminal A is internally floating.

ometer’s terminal B is internally connected to V_SS

.

Terminal B does not have a polarity relative to terminals

W or A. Terminal B can support both positive and

negative current.

For the MCP4022, terminal B is internally floating.

DS21945E-page 25

MCP4021/2/3/4

3.6

Chip Select (CS)

3.7

Increment/Decrement (U/D)

The CS pin is the chip select input. Forcing the CS pin

to V_ILenables the serial commands. These commands

can increment and decrement the wiper. Depending on

the command, the wiper may (or may not) be saved to

non-volatile memeory (EEPROM). Forcing the CS pin

to V_IHHenables the high-voltage serial commands.

These commands can increment and decrement the

wiper and enable or disable the WiperLock technology.

The wiper is saved to non-volatile memory (EEPROM).

The U/D pin input is used to increment or decrement

the wiper on the digital potentiometer. An increment

moves the wiper one step toward terminal A, while a

decrement moves the wiper one step toward

terminal B.

The CS pin has an internal pull-up resistor. The resistor

will become “disabled” when the voltage on the CS pin

is below the V_IHlevel. This means that when the CS pin

is “floating”, the CS pin will be pulled to the V_IHlevel

(serial communication (the U/D pin) is ignored). And

when the CS pin is driven low (V_IL), the resistance

becomes very large to reduce the device current

consumption when serial commands are occurring.

See Figure 2-4 for additional information.

DS21945E-page 26

MCP4021/2/3/4

EQUATION 4-1:

R CALCULATION

4.0

GENERAL OVERVIEW

S

R_AB

The MCP402X devices are general purpose digital

potentiometers intended to be used in applications

where a programmable resistance with moderate

bandwidth is desired.

R_S= ---------

63

EQUATION 4-2:

R

CALCULATION

WB

Applications generally suited for the MCP402X devices

include:

R_AB

R_WB= ------------- + R_W

63

N

• Set point or offset trimming

N = 0 to 63 (decimal)

• Sensor calibration

• Selectable gain and offset amplifier designs

• Cost-sensitive mechanical trim pot replacement

1 LSb is the ideal resistance difference between two

successive codes. If we use N = 1 and R_W= 0 in

Equation 4-2, we can calculate the step size for each

increment or decrement command.

The digital potentiometer is available in four nominal

resistances (R_AB), where the nominal resistance is

defined as the resistance between terminal A and

terminal B. The four nominal resistances are 2.1 kΩ,

5 kΩ, 10 kΩ and 50 kΩ.

The MCP4021 device offers

a voltage divider

(potentiometer) with all terminals available on pins.

The MCP4022 is a true rheostat, with terminal A and

the wiper (W) of the variable resistor available on pins.

There are 63 resistors in a string between terminal A

and terminal B. The wiper can be set to tap onto any of

these 63 resistors thus providing 64 possible settings

(including terminal A and terminal B).

The MCP4023 device offers a voltage divider (potenti-

ometer) with terminal B connected to ground.

The MCP4024 device is a rheostat device with terminal

A of the resistor floating, terminal B connected to

ground, and the wiper (W) available on pin.

Figure 4-1 shows a block diagram for the resistive

network of the device. Equation 4-1 shows the

calculation for the step resistance, while Equation 4-2

illustrates the calculation used to determine the

resistance between the wiper and terminal B.

The MCP4021 can be externally configured to

implement any of the MCP4022, MCP4023 or

MCP4024 configurations.

A

4.1

Serial Interface

3Fh

N = 63

(1)

A 2-wire synchronous serial protocol is used to

increment or decrement the digital potentiometer’s

wiper terminal. The Increment/Decrement (U/D)

protocol utilizes the CS and U/D input pins. Both inputs

are tolerant of signals up to 12.5V without damaging

the device. The CS pin can differenciate between two

high-voltage levels, V_IHand V_IHH. This enables

additional commands without requiring additional input

pins. The high-voltage commands (V_IHHon the CS pin)

are similar to the standard commands, except that they

control (enable, disable, ...) the state of the non-volatile

WiperLock technolgy feature.

R_W

R_S

N = 62

N = 61

3Eh

3Dh

(1)

R_W

W

N = 1

N = 0

01h

00h

The simple U/D protocol uses the state of the U/D pin

at the falling edge of the CS pin to determine if

Increment or Decrement mode is desired. Subsequent

rising edges of the U/D pin move the wiper.

(1)

R_W

R_S

The wiper value will not underflow or overflow. The new

wiper setting can be saved to EEPROM, if desired, by

selecting the state of the U/D pin during the rising edge

of the CS pin.

B

Analog

Mux

Note 1: The wiper resistance is tap dependent.

That is, each tap selection resistance

has a small variation. This variation

effects the smaller resistance devices

(2.1 kΩ) more.

The non-volatile wiper enables the MCP4021/2/3/4 to

operate stand alone (without microcontroller control).

FIGURE 4-1:

Resistor Block Diagram.

DS21945E-page 27

MCP4021/2/3/4

The default settings of the MCP4021/2/3/4 device’s

from the factory are shown in Table 4-1.

4.2

The WiperLock™ Technology

The MCP4021/2/3/4 device’s WiperLock technology

allows application-specific calibration settings to be

secured in the EEPROM without requiring the use of an

additional write-protect pin.

TABLE 4-1:

DEFAULT FACTORY

SETTINGS SELECTION

The WiperLock technology prevents the serial

commands from doing the following:

• Incrementing or decrementing the wiper setting

• Writing the wiper setting to the non-volatile

memory

-202

-502

-103

-503

Mid-scale

1Fh

Disabled

2.1 kΩ

5.0 kΩ

Enabling and disabling the WiperLock technology

feature requires high-voltage serial commands

(CS = V_IHH). Incrementing and decrementing the wiper

requires high-voltage commands when the feature is

enabled. The high-voltage threshold (V_IHH) is intended

to prevent the wiper setting from being altered by noise

or intentional transitions on the U/D and CS pins, while

still providing flexibility for production or calibration

environments.

Mid-scale

10.0 kΩ

50.0 kΩ

It is good practice in your manufacturing flow to

configure the device to your desired settings.

4.4

Brown Out

Both the CS and U/D input pins are tolerant of signals

up to 12V. This allows the flexibility to multiplex the

digital pot’s control signals onto application signals for

manufacturing/calibration.

If the device V_DDis below the specified minimum

voltage, care must be taken to ensure that the CS and

U/D pins do not “create” any of the serial commands.

When the device V_DDdrops below V_min(2.7V), the

electrical performance may not meet the data sheet

specifications (see Figure 4-2). The wiper may be

unknown or initialized to the value stored in the

EEPROM. Also the device may be capable of

incrementing, decrementing and writing to its EEPROM

if a valid command is detected on the CS and U/D pins.

4.3

Power-up

When the device powers up, the last saved wiper

setting is restored.

While V_DD< V_min(2.7V), the electrical performance

may not meet the data sheet specifications (see

Figure 4-2). The wiper may be unknown or initialized to

the value stored in the EEPROM. Also the device may

be capable of incrementing, decrementing and writing

to its EEPROM, if a valid command is detected on the

CS and U/D pins.

4.5

Serial Interface Inactive

The serial interface is inactive any time the CS pin is at

V_IHand all write cycles are completed.

EEPROM

Write

Protect

Outside

Specified AC/DC

Range

V_DD

2.7V

V_WP

V_SS

FIGURE 4-2:

Power-up and Brown-out.

DS21945E-page 28

MCP4021/2/3/4

5.2

Serial Commands

5.0

5.1

SERIAL INTERFACE

Overview

The MCP402X devices support 10 serial commands.

The commands can be grouped into the following

types:

The MCP4021/2/3/4 utilizes a simple 2-wire interface to

increment or decrement the digital potentiometer’s

wiper terminal (W), store the wiper setting in non-vola-

tile memory and turn the WiperLock technology feature

on or off. This interface uses the Chip Select (CS) pin,

while the U/D pin is the Up/Down input.

• Serial Commands

• High-voltage Serial Commands

All the commands are shown in Table 5-1.

The command type is determined by the voltage level

on the CS pin. The initial state that the CS pin must be

driven is V_IH. From V_IH, the two levels that the CS pin

can be driven are:

The Increment/Decrement protocol enables the device

to move one step at a time through the range of

possible resistance values. The wiper value is

initialized with the value stored in the internal EEPROM

upon power-up. A wiper value of 00h connects the

wiper to terminal B. A wiper value of 3Fh connects the

wiper to terminal A. Increment commands move the

wiper toward terminal A, but will not increment to a

value greater than 3Fh. Decrement commands move

the wiper toward terminal B, but will not decrement

below 00h.

• V_IL

• V_IHH

If the CS pin is driven from V_IHto V_IL, a serial

command is selected. If the CS pin is driven from V_IHto

V_IHH, a high-voltage serial command is selected.

High-voltage serial commands control the state of the

WiperLock technology. This is a unique feature, where

the user can determine whether or not to “lock” or

“unlock” the wiper state.

Refer to Section 1.0 “Electrical Characteristics”,

AC/DC Electrical Characteristics table for detailed input

threshold and timing specifications.

High-voltage serial commands increment/decrement

the wiper regardless of the status of the WiperLock

technology.

Communication is unidirectional. Therefore, the value

of the current wiper setting cannot be read out of the

MCP402X device.

TABLE 5-1:

COMMANDS

After

Command

Wiper is

“locked”/

”unlocked”

Saves

Wiper

Value in

EEPROM

High

Voltage

on CS

pin?

Works

when

Wiper is

“locked”?

Command Name

Increment without Writing Wiper Setting to EEPROM

Increment with Writing Wiper Setting to EEPROM

Decrement without Writing Wiper Setting to EEPROM

Decrement with Writing Wiper Setting to EEPROM

Write Wiper Setting to EEPROM

—

unlocked

locked

Note 1

Yes

—

Yes

—

High-Voltage Increment and Disable WiperLock Technology

High-Voltage Increment and Enable WiperLock Technology

High-Voltage Decrement and Disable WiperLock Technology

High-Voltage Decrement and Enable WiperLock Technology

Yes

unlocked

locked

Yes

Write Wiper Setting to EEPROM and Disable WiperLock

Technology

unlocked

Yes

Write Wiper Setting to EEPROM and Enable WiperLock

Technology

Yes

locked

Yes

Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled).

DS21945E-page 29

MCP4021/2/3/4

The EEPROM value has not been updated to this new

wiper value, so if the device voltage is lowered below

the RAM retention voltage of the device, once the

device returns to the operating range, the wiper will be

loaded with the wiper setting in the EEPROM.

5.2.1

INCREMENT WITHOUT WRITING

WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a

high state (V_IH) prior to achieving a low state (V_IL) on the

CS pin. Subsequent rising edges of the U/D pin

increment the wiper setting toward terminal A. This is

shown in Figure 5-1.

After the CS pin is driven to V_IH(from V_IL), any other

serial command may immediately be entered. This is

since an EEPROM write cycle (t_wc) is not active.

After the wiper is incremented to the desired position,

the CS pin should be forced to V_IHto ensure that

“unexpected” transitions (on the U/D pin do not cause

the wiper setting to increment. Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired increment occurs.

Note:

The wiper value will not overflow. That is,

once the wiper value equals 0x3F,

subsequent increment commands are

ignored.

V_IH

V_IL

CS

V_IH

6

1

2

3

4

5

U/D

V_IL

X

EEPROM

X+1 X+2

X+3 X+4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

Note: If WiperLock technology enabled, wiper will not move.

Increment without Writing Wiper Setting to EEPROM.

FIGURE 5-1:

DS21945E-page 30

MCP4021/2/3/4

To ensure that “unexpected” transitions on the U/D pin

do not cause the wiper setting to increment, the U/D pin

should be driven low and the CS pin forced to V_IHas

soon as possible (within device specifications) after the

last desired increment occurs.

5.2.2

INCREMENT WITH WRITING WIPER

SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a

high state (V_IH) prior to achieving a low state (V_IL) on the

CS pin. Subsequent rising edges of the U/D pin

increment the wiper setting toward terminal A. This is

shown in Figure 5-2.

After the CS pin is driven to V_IH(from V_IL), all other

serial commands are ignored until the EEPROM write

cycle (t_wc) completes.

After the wiper is incremented to the desired position,

the U/D pin should be driven low (V_IL). Then when the

CS pin is forced to V_IH, the wiper value is written to the

EEPROM. Therefore, if the device voltage is lowered

below the RAM retention voltage of the device, once

the device returns to the operating range, the wiper will

be loaded with this wiper setting (stored in the

EEPROM).

Note:

The wiper value will not overflow. That is,

once the wiper value equals 0x3F,

subsequent increment commands are

ignored.

V_IH

V_IL

CS

t_WC

V_IH

6

1

2

3

4

5

V_IL

U/D

X

X+4

EEPROM

X+1 X+2

X+3 X+4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

Note: If WiperLock technology enabled, wiper will not move.

Increment with Writing Wiper Setting to EEPROM.

FIGURE 5-2:

DS21945E-page 31

MCP4021/2/3/4

The EEPROM value has not been updated to this new

wiper value, so, if the device voltage is lowered below

the RAM retention voltage of the device, once the

device returns to the operating range, the wiper will be

loaded with the wiper setting in the EEPROM.

5.2.3

DECREMENT WITHOUT WRITING

WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a low

state (V_IL) prior to achieving a low state (V_IL) on the CS

pin. Subsequent rising edges of the U/D pin will

decrement the wiper setting toward terminal B. This is

shown in Figure 5-3.

After the CS pin is driven to V_IH(from V_IL), any other

serial command may immediately be entered, since an

EEPROM write cycle (t_WC) is not started.

After the wiper is decremented to the desired position,

the U/D pin should be forced low (V_IL) and the CS pin

should be forced to V_IH. This will ensure that

“unexpected” transitions on the U/D pin do not cause

the wiper setting to decrement. Driving the CS pin to

V_IHshould occur as soon as possible (within device

specifications) after the last desired increment occurs.

Note:

The wiper value will not underflow. That is,

once the wiper value equals 0x00,

subsequent decrement commands are

ignored.

V_IH

V_IL

CS

6

5

V_IH

1

2

3

4

V_IL

U/D

X

EEPROM

X

X-1

X-2

X-3

X-4

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

Note: If WiperLock technology enabled, wiper will not change.

FIGURE 5-3:

Decrement without Writing Wiper Setting to EEPROM.

DS21945E-page 32

MCP4021/2/3/4

To ensure that “unexpected” transitions on the U/D pin

do not cause the wiper setting to decrement, the U/D

pin should be driven low (V_IL) and the CS pin forced to

V_IHas soon as possible (within device specifications)

after the last desired increment occurs.

5.2.4

DECREMENT WITH WRITING

WIPER SETTING TO EEPROM

This mode is achieved by initializing the U/D pin to a

low state (V_IL) prior to achieving a low state (V_IL) on the

CS pin. Subsequent rising edges of the U/D pin

decrement the wiper setting (toward terminal B). This is

shown in Figure 5-4.

After the CS pin is driven to V_IH(from V_IL), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

After the wiper is decremented to the desired position,

the U/D pin should remain high (V_IH). Then when the

CS pin is raised to V_IH, the wiper value is written to the

EEPROM. Therefore, if the device voltage is lowered

below the RAM retention voltage of the device, once

the device returns to the operating range, the wiper will

be loaded with this wiper setting (stored in the

EEPROM).

Note:

The wiper value will not underflow. That is,

once the wiper value equals 0x00,

subsequent decrement commands are

ignored.

V_IH

V_IL

CS

t_WC

V_IH

1

2

3

4

5

6

V_IL

U/D

X

EEPROM

X-4

X-1

X-2

X-3

X-4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

Note: If WiperLock technology enabled, wiper will not change.

FIGURE 5-4:

Decrement with Writing Wiper Setting to EEPROM.

DS21945E-page 33

MCP4021/2/3/4

When the CS pin is forced to V_IH, the wiper value is

written to the EEPROM. Therefore, if the device

voltage is lowered below the RAM retention voltage of

the device, once the device returns to the operating

range, the wiper will be loaded with this wiper setting

(stored in the EEPROM).

5.2.5

WRITE WIPER SETTING TO

EEPROM

To write the current wiper setting to EEPROM, force

both the CS pin and U/D pin to V_IH. Then force the CS

pin to V_IL. Before there is a rising edge on the U/D pin,

force the CS pin to V_IH. This causes the wiper setting

value to be written to EEPROM.

To ensure that “unexpected” transitions on the U/D pin

do not cause the wiper setting to increment, force the

CS pin to V_IHas soon as possible (within device

specifications) after the U/D pin is forced to V_IL.

Note:

After the U/D pin is forced to V_IL, each

rising edge on the U/D pin will cause the

wiper to increment.

This is the same command as the “Incre-

ment with Writing Wiper Setting to

EEPROM“ command, but the U/D pin is

held at V_IL,so the wiper is not incre-

mented.

After the CS pin is driven to V_IH(from V_IL), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

V_IH

V_IL

CS

t_WC

V_IH

6

5

V_IL

U/D

X

EEPROM

X+4

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-5:

Write Wiper Setting to EEPROM.

DS21945E-page 34

MCP4021/2/3/4

After the CS pin is driven to V_IH(from V_IHH), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

5.2.6

HIGH-VOLTAGE INCREMENT AND

DISABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to a

high state (V_IH) prior to the CS pin being driven to V_IHH

.

Note:

The wiper value will not overflow. That is,

once the wiper value equals 0x3F,

subsequent increment commands are

ignored.

Subsequent rising edges of the U/D pin increment the

wiper setting toward terminal A. Set the U/D pin to the

high state (V_IH) prior to forcing the CS pin to V_IH. This

begins a write cycle and disables the WiperLock

Technology feature (See Figure 5-6).

V_IHH

V_IH

CS

t_WC

V_IH

6

1

2

3

4

5

U/D

V_IL

X

X+4

EEPROM

X+1 X+2

X+3 X+4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-6:

High-Voltage Increment and Disable WiperLock™ Technology.

DS21945E-page 35

MCP4021/2/3/4

After the CS pin is driven to V_IH(from V_IHH), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

5.2.7

HIGH-VOLTAGE INCREMENT AND

ENABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to a

high state (V_IH) prior to the CS pin being driven to V_IHH

.

Note:

The wiper value will not overflow. That is,

once the wiper value equals 0x3F,

subsequent increment commands are

ignored.

Subsequent rising edges of the U/D pin increment the

wiper setting toward terminal A. Set the U/D pin to the

low state (V_IL) prior to forcing the CS pin to V_IH. This

begins a write cycle and enables the WiperLock

Technology feature (See Figure 5-7).

V_IHH

V_IH

CS

t_WC

V_IH

6

1

2

3

4

5

V_IL

U/D

V_IL

X

X+4

EEPROM

X+1 X+2

X+3 X+4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-7:

High-Voltage Increment and Enable WiperLock™ Technology.

DS21945E-page 36

MCP4021/2/3/4

After the CS pin is driven to V_IH(from V_IHH), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

5.2.8

HIGH-VOLTAGE DECREMENT AND

DISABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to a

low state (V_IL) prior to the CS pin being driven to V_IHH

.

Note:

The wiper value will not underflow. That is,

once the wiper value equals 0x00,

subsequent decrement commands are

ignored.

Subsequent rising edges of the U/D pin decrement the

wiper setting toward terminal B. Set the U/D pin to the

low state (V_IL) prior to forcing the CS pin to V_IH. This

begins a write cycle and disables the WiperLock

Technology feature (See Figure 5-8).

V_IHH

V_IH

CS

t_WC

1

2

3

4

6 V_IH

5

V_IL

U/D

X

X-4

EEPROM

X-1

X-2

X-3

X-4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-8:

High-Voltage Decrement and Disable WiperLock™ Technology.

DS21945E-page 37

MCP4021/2/3/4

After the CS pin is driven to V_IH(from V_IHH), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

5.2.9

HIGH-VOLTAGE DECREMENT AND

ENABLE WiperLock TECHNOLOGY

This mode is achieved by initializing the U/D pin to the

low state (V_IL) prior to driving the CS pin to V_IHH

.

Note:

The wiper value will not underflow. That is,

once the wiper value equals 0x00,

subsequent decrement commands are

ignored.

Subsequent rising edges of the U/D pin decrement the

wiper setting toward terminal B. Set the U/D pin to a

high state (V_IH) prior to forcing the CS pin to V_IH. This

begins a write cycle and enables the WiperLock

Technology feature (See Figure 5-9).

V_IHH

V_IH

CS

t_WC

V_DD

V_IH

6

5

1

2

3

4

U/D

V_IL

X

X-4

EEPROM

X-1

X-2

X-3

X-4

X

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-9:

High-Voltage Decrement and Enable WiperLock™ Technology.

DS21945E-page 38

MCP4021/2/3/4

To ensure that “unexpected” transitions on the U/D pin

do not cause the wiper setting to change, force the CS

pin to V_IHas soon as possible (within device

5.2.10

WRITE WIPER SETTING TO

EEPROM AND DISABLE WiperLock

TECHNOLOGY

specifications) after the CS pin is forced to V_IHH

.

This mode is achieved by keeping the U/D pin static

(either at V_ILor at V_IH), while the CS pin is driven from

V_IHto V_IHHand then returned to V_IH. When the falling

edge of the CS pin occurs (from V_IHHto V_IH), the wiper

value is written to EEPROM and the WiperLock

Technology is disabled (See Figure 5-10).

After the CS pin is driven to V_IH(from V_IHH), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

V_IHH

V_IH

CS

V_IH

t_WC

V_IH

U/D

V_IL

X

EEPROM

X+4

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-10:

Write Wiper Setting to EEPROM and Disable WiperLock™ Technology.

DS21945E-page 39

MCP4021/2/3/4

To ensure that “unexpected” transitions on the U/D pin

do not cause the wiper setting to increment, force the

CS pin to V_IHas soon as possible (within device

specifications) after the U/D pin is forced to V_IL.

5.2.11

WRITE WIPER SETTING TO

EEPROM AND ENABLE WiperLock

TECHNOLOGY

This mode is achieved by initializing the U/D and CS

pins to a high state (V_IH) prior to the CS pin being driven

to V_IHH(from V_IH). Set the U/D pin to a low state (V_IL)

prior to forcing the CS pin to V_IH(from V_IHH). This

begins a write cycle and enables the WiperLock

Technology feature (See Figure 5-11).

After the CS pin is driven to V_IH(from V_IHH), all other

serial commands are ignored until the EEPROM write

cycle (t_WC) completes.

V_IHH

V_IH

CS

t_WC

V_IH

U/D

V_IL

X

EEPROM

X+4

Wiper

WiperLock Technology Enable

WiperLock Technology Disable

WiperLock™ Technology

FIGURE 5-11:

Write Wiper Setting to EEPROM and Enable WiperLock™ Technology.

DS21945E-page 40

MCP4021/2/3/4

The circuit in Figure 5-13 shows the method used on

the MCP402X Non-volatile Digital Potentiometer

Evaluation Board. This method requires that the

system voltage be approximately 5V. This ensures that

when the PIC10F206 enters a brown-out condition,

there is an insufficent voltage level on the CS pin to

change the stored value of the wiper. The MCP402X

Non-volatile Digital Potentiometer Evaluation Board

5.3

CS High Voltage

Depending on the requirements of the system, the use

of high voltage (V_IHH) on the CS pin, may or may not be

required during system operation. Table 5-2 shows

possible system applications, and whether a high

voltage (V_IHH) is required on the system.

The MCP402X supports six high-voltage commands

(the CS input voltage must meet the VIHH

specification).

User’s Guide (DS51546) contains

schematic.

a

complete

GP0 is a general purpose I/O pin, while GP2 can either

be a general purpose I/O pin or it can output the internal

clock.

TABLE 5-2:

HIGH-VOLTAGE

APPLICATIONS

For the serial commands, configure the GP2 pin as an

input (high impedence). The output state of the GP0 pin

will determine the voltage on the CS pin (V_ILor V_IH).

High

Voltage

System Operation

Production calibration only - system

should not update wiper setting

From

Calibration

Unit

For high-voltage serial commands, force the GP0

output pin to output a high level (V_OH) and configure the

GP2 pin to output the internal clock. This will form a

charge pump and increase the voltage on the CS pin

(when the system voltage is approximately 5V).

WiperLock™ Technogy disabled during

system operation

Not

Required

Wiper setting can be updated and

“locked” during system operation

Required

PIC10F206

R₁

5.3.1

TECHNIQUES TO FORCE THE CS

PIN TO V

GP0

IHH

MCP402X

The circuit in Figure 5-12 shows a method using the

TC1240A doubling charge pump. When the SHDN pin

is high, the TC1240A is off, and the level on the CS pin

is controlled by the PIC® microcontrollers (MCUs) IO2

pin.

GP2

CS

C₂

C₁

When the SHDN pin is low, the TC1240A is on and the

V_OUTvoltage is 2 * V_DD. The resistor R₁allows the CS

pin to go higher than the voltage such that the PIC

MCU’s IO2 pin “clamps” at approximately VDD.

FIGURE 5-13:

Digital Potentiometer Evaluation Board

MCP402X Non-volatile

(MCP402XEV) implementation to generate the

V

voltage.

IHH

TC1240A

V_IN

C+

PIC^®MCU

C₁

C-

SHDN

V_OUT

IO1

MCP402X

R₁

CS

IO2

C₂

FIGURE 5-12:

generate the V

Using the TC1240A to

voltage.

IHH

DS21945E-page 41

MCP4021/2/3/4

Step resistance (R_S) is the resistance from one tap

setting to the next. This value will be dependent on the

6.0

RESISTOR

Digital potentiometer applications can be divided into

two categories:

R_ABvalue that has been selected. Table 6-1 shows the

typical step resistances for each device.

• Rheostat configuration

The total resistance of the device has minimal variation

due to operating voltage (see Figure 2-6, Figure 2-17,

Figure 2-27 or Figure 2-37).

• Potentiometer (or voltage divider) configuration

Figure 6-1 shows a block diagram for the MCP402X

resistors.

TABLE 6-1:

Part Number

TYPICALSTEPRESISTANCES

Typical Resistance (Ω)

A

3Fh

N = 63

Total (R_AB

)

Step (R_S)

(1)

R_W

MCP402X-203E

MCP402X-503E

MCP402X-104E

MCP402X-504E

2100

5000

33.33

79.37

R_S

N = 62

N = 61

3Eh

3Dh

10000

50000

158.73

793.65

(1)

R_W

Terminal A and B, as well as the wiper W, do not have

a polarity. These terminals can support both positive

and negative current.

W

N = 1

N = 0

01h

00h

(1)

R_W

R_S

B

Analog

Mux

Note 1: The wiper resistance is tap dependent.

That is, each tap selection resistance

has a small variation. This variation

effects the smaller resistance devices

(2.1 kΩ) more.

FIGURE 6-1:

Resistor Block Diagram.

DS21945E-page 42

MCP4021/2/3/4

6.1.2

POTENTIOMETER

CONFIGURATION

6.1

Resistor Configurations

6.1.1

RHEOSTAT CONFIGURATION

When used as a potentiometer, all three terminals are

tied to different nodes in the circuit. This allows the

potentiometer to output a voltage proportional to the

input voltage. This configuration is sometimes called

voltage divider mode. The potentiometer is used to

provide a variable voltage by adjusting the wiper

position between the two endpoints as shown in

Figure 6-3. Reversing the polarity of the A and B

terminals will not affect operation.

When used as a rheostat, two of the three digital

potentiometer’s terminals are used as a resistive

element in the circuit. With terminal W (wiper) and

either terminal A or terminal B, a variable resistor is

created. The resistance will depend on the tap setting

of the wiper and the wiper’s resistance. The resistance

is controlled by changing the wiper setting.

The unused terminal (B or A) should be left floating.

Figure 6-2 shows the two possible resistors that can be

used. Reversing the polarity of the A and B terminals

will not affect operation.

V₁

A

V₃

W

A

B

R_AW

or

R_BW

V₂

W

B

FIGURE 6-3:

Potentiometer Configuration.

The temperature coefficient of the R_ABresistors is

minimal by design. In this configuration, the resistors all

change uniformally, so minimal variation should be

seen.

Resistor

Rheostat Configuration.

FIGURE 6-2:

This allows the control of the total resistance between

the two nodes. The total resistance depends on the

“starting” terminal to the wiper terminal. At the code

00h, the R_BWresistance is minimal (R_W), but the R_AW

resistance in maximized (R_AB+ R_W). Conversely, at the

code 3Fh, the R_AWresistance is minimal (R_W), but the

R_BWresistance in maximized (R_AB+ R_W).

The wiper resistor temperature coefficient is different

from the R_ABtemperature coefficient. The voltage at

node V₃(Figure 6-3) is not dependent on this wiper

resistance, just the ratio of the R_ABresistors, so this

temperature coefficient in most cases can be

ignored.

The resistance step size (R_S) equates to one LSb of the

resistor.

Note:

To avoid damage to the internal wiper

circuitry in this configuration, care should

be taken to insure the current flow never

exceeds 2.5 mA.

Note:

To avoid damage to the internal wiper

circuitry in this configuration, care should

be taken to insure the current flow never

exceeds 2.5 mA.

The change in wiper-to-end terminal resistance over

temperature is shown in Figure 2-6, Figure 2-17,

Figure 2-27 and Figure 2-37. The most variation over

temperature will occur in the first few codes due to the

wiper resistance coefficient affecting the total

resistance. The remaining codes are dominated by the

total resistance tempco R_AB

.

DS21945E-page 43

MCP4021/2/3/4

The slope of the resistance has a linear area (at the

higher voltages) and a non-linear area (at the lower

voltages), where resistance increases faster than the

voltage drop (at low voltages).

6.2

Wiper Resistance

Wiper resistance is the series resistance of the wiper.

This resistance is typically measured when the wiper is

positioned at either zero-scale (00h) or full-scale (3Fh).

The wiper resistance in potentiometer-generated

voltage divider applications is not a significant source

of error.

The wiper resistance in rheostat applications can

create significant non-linearity as the wiper is moved

toward zero-scale (00h). The lower the nominal

resistance, the greater the possible error.

R_W

Wiper resistance is significant depending on the

devices operating voltage. As the device voltage

decreases, the wiper resistance increases (see

Figure 6-4 and Table 6-2).

V_DD

Note:

The slope of the resistance has a linear

area (at the higher voltages) and a non-

linear area (at the lower voltages).

In a rheostat configuration, this change in voltage

needs to be taken into account, particularly for the

lower resistance devices. For the 2.1 kΩ device, the

maximum wiper resistance at 5.5V is approximately 6%

of the total resistance, while at 2.7V, it is approximately

15.5% of the total resistance.

FIGURE 6-4:

Resistance (R ) to Voltage

Relationship of Wiper

W

Since there is minimal variation of the total device

resistance over voltage, at a constant temperature (see

Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37),

the change in wiper resistance over voltage can have a

significant impact on the INL and DNL error.

In a potentiometer configuration, the wiper resistance

variation does not effect the output voltage seen on the

terminal W pin.

TABLE 6-2:

Typical

TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE

Resistance (Ω)

Wiper (R_W)

Step Max @ Max @

R_W/ R_S(%) ⁽¹⁾

R_W/ R_AB(%) ⁽²⁾

R_W

Typical

=

R_W= Max R_W= Max

@ 5.5V

R_W

=

R_W= Max R_W= Max

Total

@ 2.7V

Typical

@ 5.5V

@ 2.7V

Typical

(R_AB

)

(R_S)

5.5V

2.7V

2100

5000

33.33

79.37

75

125

325

225.0%

94.5%

47.25%

9.45%

375.0%

157.5%

78.75%

15.75%

975.0%

409.5%

204.75%

40.95%

3.57%

1.5%

5.95%

2.50%

1.25%

0.25%

15.48%

6.50%

3.25%

0.65%

10000 158.73

50000 793.65

0.75%

0.15%

Note 1: R_Sis the typical value. The variation of this resistance is minimal over voltage.

2: R_ABis the typical value. The variation of this resistance is minimal over voltage.

DS21945E-page 44

MCP4021/2/3/4

6.3.1.2

Differential Non-Linearity (DNL)

6.3

Operational Characteristics

DNL error is the measure of variations in code widths

from the ideal code width. A DNL error of zero would

imply that every code is exactly 1 LSb wide.

Understanding the operational characteristics of the

device’s resistor components is important to the system

design.

6.3.1

ACCURACY

6.3.1.1

Integral Non-Linearity (INL)

111

INL error for these devices is the maximum deviation

between an actual code transition point and its

corresponding ideal transition point after offset and

gain errors have been removed. These endpoints are

from 0x00 to 0x3F. Refer to Figure 6-5.

110

Actual

Transfer

Function

101

Digital

Input

Code

100

011

010

001

000

Ideal Transfer

Function

Positive INL means higher resistance than ideal.

Negative INL means lower resistance than ideal.

Wide Code, > 1 LSb

INL < 0

111

Narrow Code < 1 LSb

Actual

Transfer

Function

110

101

100

Digital Pot Output

FIGURE 6-6:

DNL Accuracy.

Digital

Input

6.3.1.3 Ratiometric Temperature Coefficient

Code

011

010

001

000

The ratiometric temperature coefficient quantifies the

error in the ratio R_AW/R_WBdue to temperature drift.

This is typically the critical error when using a

potentiometer device (MCP4021 and MCP4023) in a

voltage divider configuration.

Ideal Transfer

Function

6.3.1.4

Absolute Temperature Coefficient

INL < 0

The absolute temperature coefficient quantifies the

error in the end-to-end resistance (nominal resistance

R_AB) due to temperature drift. This is typically the

critical error when using a rheostat device (MCP4022

and MCP4024) in an adjustable resistor configuration.

Digital Pot Output

FIGURE 6-5:

INL Accuracy.

DS21945E-page 45

MCP4021/2/3/4

6.3.2

MONOTONIC OPERATION

Monotonic operation means that the device’s

resistance increases with every step change (from

terminal A to terminal B or terminal B to terminal A).

The wiper resistance is different at each tap location.

When changing from one tap position to the next (either

increasing or decreasing), the ΔR_Wis less than the

ΔR_S. When this change occurs, the device voltage and

temperature are “the same” for the two tap positions.

R_S63

0x3F

0x3E

R_S62

0x3D

R_S3

0x03

R_S1

0x02

R_S0

0x01

0x00

R_W

n = ?

(@ tap)

R_BW

=

R_Sn+ R_{W(@ Tap n}

)

n = 0

Resistance (R_BW

)

FIGURE 6-7:

Resistance, R

.

BW

DS21945E-page 46

MCP4021/2/3/4

7.2

Layout Considerations

7.0

DESIGN CONSIDERATIONS

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP402X’s performance.

Careful board layout will minimize these effects and

increase the Signal-to-Noise Ratio (SNR). Bench

testing has shown that a multi-layer board utilizing a

low-inductance ground plane, isolated inputs, isolated

outputs and proper decoupling are critical to achieving

the performance that the silicon is capable of providing.

Particularly harsh environments may require shielding

of critical signals.

In the design of a system with the MCP402X devices,

the following considerations should be taken into

account:

• The Power Supply

• The Layout

7.1

Power Supply Considerations

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 7-1 illustrates an

appropriate bypass strategy.

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (V_DD) as

possible.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

V_SSshould reside on the analog plane.

V_DD

0.1 µF

V_DD

0.1 µF

A

W

U/D

CS

B

V_SS

FIGURE 7-1:

Typical Microcontroller

Connections.

DS21945E-page 47

MCP4021/2/3/4

8.0

APPLICATIONS EXAMPLES

V_DD

R₁

Non-volatile digital potentiometers have a multitude of

practical uses in modern electronic circuits. The most

popular uses include precision calibration of set point

thresholds, sensor trimming, LCD bias trimming, audio

attenuation, adjustable power supplies, motor control

overcurrent trip setting, adjustable gain amplifiers and

offset trimming. The MCP4021/2/3/4 devices can be

used to replace the common mechanical trim pot in

applications where the operating and terminal voltages

are within CMOS process limitations (V_DD= 2.7V to

5.5V).

MCP4021

A

CS

W

V_OUT

U/D

B

R₂

8.1

Set Point Threshold Trimming

FIGURE 8-1:

Potentiometer to Set a Precise Output Voltage.

Using the Digital

Applications that need accurate detection of an input

threshold event often need several sources of error

eliminated. Use of comparators and operational

amplifiers (op amps) with low offset and gain error can

help achieve the desired accuracy, but in many applica-

tions, the input source variation is beyond the

designer’s control. If the entire system can be

calibrated after assembly in a controlled environment

(like factory test), these sources of error are minimized,

if not entirely eliminated.

8.1.1

TRIMMING A THRESHOLD FOR AN

OPTICAL SENSOR

If the application has to calibrate the threshold of a

diode, transistor or resistor, a variation range of 0.1V is

common. Often, the desired resolution of 2 mV or

better is adequate to accurately detect the presence of

a precise signal. A “windowed” voltage divider, utilizing

the MCP4021 or MCP4023, would be a potential

solution as shown in Figure 8-2.

Figure 8-1 illustrates a common digital potentiometer

configuration. This configuration is often referred to as

a “windowed voltage divider”. Note that R₁and R₂are

not necessary to create the voltage divider, but their

presence is useful when the desired threshold has

limited range. It is “windowed” because R₁and R₂can

narrow the adjustable range of V_TRIPto a value much

less than V_DD– V_SS. If the output range is reduced, the

magnitude of each output step is reduced. This

effectively increases the trimming resolution for a fixed

digital potentiometer resolution. This technique may

allow a lower-cost digital potentiometer to be utilized

(64 steps instead of 256 steps).

V_DD

V_CC+

R_sense

R₁

Comparator

MCP4021

CS

A

B

The MCP4021’s and

MCP4023’s low DNL

V_TRIP

W

performance is critical to meeting calibration accuracy

in production without having to use a higher precision

digital potentiometer.

MCP6021

V_CC–

U/D

0.1 µF

R₂

EQUATION 8-1:

CALCULATING THE

WIPER SETTING FROM

THE DESIRED V

TRIP

FIGURE 8-2:

Calibration.

Set Point or Threshold

R₂+ R_WB

⎛

⎝

⎞

⎠

----------------------------------

V_TRIP= V_DD

R₁+ R_AB+ R₂

R_AB= R_Nominal

D

63

⎛

⎝

⎞

⎠

-----

R_WB= R_AB

•

V_TRIP

⎛⎛

⎝⎝

⎞

⎠

⎞

--------------

D =

• ((R₁+ R_AB+ R₂) – R₂) • 63

⎠

V_DD

Where:

D = Digital Potentiometer Wiper Setting (0-63)

DS21945E-page 48

MCP4021/2/3/4

8.2

Operational Amplifier

Applications

V_DD

MCP6291

V_IN

+

Figure 8-3, Figure 8-4 and Figure 8-5 illustrate typical

amplifier circuits that could replace fixed resistors with

the MCP4021/2/3/4 to achieve digitally-adjustable

analog solutions.

Op Amp

–

V_DD

V_W

V_OUT

R₁

Figure 8-4 shows a circuit that allows a non-inverting

amplifier to have its’ offset and gain to be independently

trimmed. The MCP4021 is used along with resistors R1

and R2 to set the offset voltage. The sum of R1 + R2

resistance should be significantly greater (> 100 times)

the resistance value of the MCP4021. This allows each

increment or decrement in the MCP4021 to be a fine

adjustment of the offset voltage. The input voltage of

the op amp (V_IN) should be centered at the op amps V_W

voltage. The gain is adjusted by the MCP4022. If the

resistance value of the MCP4022 is small compared to

the resistance value of R3, then this is a fine

adjustment of the gain. If the resistance value of the

MCP4022 is equal (or large) compared to the

resistance value of R3, then this is a course adjustment

of the gain. In gerneral, trim the course adjustments

first and then trim the fine adjustments.

R₃

W

A

B

A

W

MCP4022

R₂

FIGURE 8-4:

Trimming Offset and Gain in

a Non-Inverting Amplifier.

MCP4021

R₃

R₄

B

A

W

Pot₂

V_DD

–

Op Amp

+

R₁

V_OUT

MCP4021

V_IN

R₃

R₄

MCP6021

B

A

B

V_IN

W

1

f_c= -----------------------------

Pot₁

MCP4022

2π ⋅ R ⋅ C

Eq

V_DD

–

R₂

Op Amp

+

R₁

V_OUT

Thevenin

Equivalent

MCP6001

||

R_Eq= (R₁+ R_AB– R_WB

)

(R₂+ R_WB) + R_w

A

B

W

FIGURE 8-5:

Programmable Filter.

R₂

FIGURE 8-3:

Trimming Offset and Gain in

an Inverting Amplifier.

DS21945E-page 49

MCP4021/2/3/4

8.3

Temperature Sensor Applications

V_DD

Thermistors are resistors with very predictable

variation with temperature. Thermistors are a popular

sensor choice when a low-cost, temperature-sensing

solution is desired. Unfortunately, thermistors have

non-linear characteristics that are undesirable, typically

requiring trimming in an application to achieve greater

accuracy. There are several common solutions to trim

and linearize thermistors. Figure 8-6 and Figure 8-7

are simple methods for linearizing a 3-terminal NTC

thermistor. Both are simple voltage dividers using a

Positive Temperature Coefficient (PTC) resistor (R₁)

with a transfer function capable of compensating for the

lineararity error in the Negative Temperature

Coefficient (NTC) thermistor.

R₁

NTC

Thermistor

MCP4021

V_OUT

R₂

The circuit, illustrated by Figure 8-6, utilizes a digital

rheostat for trimming the offset error caused by the

thermistor’s part-to-part variation. This solution puts the

digital potentiometer’s R_Winto the voltage divider

calculation. The MCP4021/2/3/4’s R_ABtemperature

coefficient is 50 ppm (-20°C to +70°C). R_W’s error is

substantially greater than R_AB’s error because R_W

varies with V_DD, wiper setting and temperature. For the

50 kΩ devices, the error introduced by R_Wis, in most

cases, insignificant as long as the wiper setting is > 6.

For the 2 kΩ devices, the error introduced by R_Wis

FIGURE 8-7:

a Digital Potentiometer in a Potentiometer

Configuration.

Thermistor Calibration using

8.4

Wheatstone Bridge Trimming

Another common configuration to “excite” a sensor

(such as a strain gauge, pressure sensor or thermistor)

is the wheatstone bridge configuration. The wheat-

stone bridge provides a differential output instead of a

significant because it is a higher percentage of R_WB

.

single-ended output. Figure 8-8 illustrates

a

For these reasons, the circuit illustrated in Figure 8-6 is

not the most optimum method for “exciting” and

linearizing a thermistor.

wheatstone bridge utilizing one to three digital

potentiometers. The digital potentiometers in this

example are used to trim the offset and gain of the

wheatstone bridge.

V_DD

R₁

NTC

Thermistor

V_OUT

R₂

2.1 kΩ

MCP4022

A

MCP4022

V_OUT

W

MCP4022

50 kΩ

MCP4022

50 kΩ

FIGURE 8-6:

a Digital Potentiometer in a Rheostat

Configuration.

Thermistor Calibration using

The circuit illustrated by Figure 8-7 utilizes a digital

potentiometer for trimming the offset error. This

solution removes R_Wfrom the trimming equation along

with the error associated with R_W. R₂is not required,

but can be utilized to reduce the trimming “window” and

reduce variation due to the digital potentiometer’s R_AB

part-to-part variability.

FIGURE 8-8:

Trimming.

Wheatstone Bridge

DS21945E-page 50

MCP4021/2/3/4

9.0

9.1

DEVELOPMENT SUPPORT

Evaluation/Demonstration Boards

Currently there are three boards that are available that

can be used to evaluate the MCP4021/2/3/4 family of

devices.

1. The MCP402X Digital Potentiomenter Evalua-

tion Board kit (MCP402XEV) contains a simple

demonstration board utilizing a PIC10F206, the

MCP4021 and a blank PCB, which can be

populated with any desired MCP4021/2/3/4

device in a SOT-23-5, SOT-23-6 or 150 mil

SOIC 8-pin package.

This board has two push buttons to control when

the PIC^®microcontroller generates MCP402X

serial commands. The example firmware dem-

onstrates the following commands:

• Increment

• Decrement

• High-Voltage Increment and Enable

WiperLock Technology

• High-Voltage Decrement and Enable

WiperLock Technology

• High-Voltage Increment and Disable

WiperLock Technology

• High-Voltage Decrement and Disable

WiperLock Technology

The populated board (with the MCP4021) can

be used to evaluate the other MCP402X devices

by appropriately jumpering the PCB pads.

2. The SOT-23-5/6 Evaluation Board (VSUPEV2)

can be used to evaluate the characteristics of

the MCP4022, MCP4023 and MCP4024

devices.

3. The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation

Board (SOIC8EV) can be used to evaluate the

characteristics of the MCP4021 device in either

the SOIC or MSOP package.

4. The MCP4XXX Digital Potentiometer Daughter

Board allows the system designer to quickly

evaluate the operation of Microchip Technol-

ogy's MCP42XXX and MCP402X Digital Poten-

tiometers. The board supports two MCP42XXX

devices and an MCP402X device, which can be

replaced with an MCP401X device.

The board also has a voltage doubler device

(TC1240A), which can be used to show the

WiperLock™ Technology feature of the

MCP4021.

These boards may be purchased directly from the

Microchip web site at www.microchip.com.

DS21945E-page 51

MCP4021/2/3/4

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

Example:

5-Lead SOT-23 (MCP4024)

XXNN

DP25

Part Number

Code

MCP4024T-202E/OT

MCP4024T-502E/OT

MCP4024T-103E/OT

MCP4024T-503E/OT

DPNN

DQNN

DRNN

DSNN

Note: Applies to 5-Lead SOT-23

Example:

6-Lead SOT-23 (MCP4022 / MCP4023)

XXNN

BA25

Code

MCP4022 MCP4023

Part Number

MCP402xT-202E/CH

MCP402xT-502E/CH

MCP402xT-103E/CH

MCP402xT-503E/CH

BANN

BBNN

BCNN

BDNN

BENN

BFNN

BGNN

BHNN

Note: Applies to 6-Lead SOT-23

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21945E-page 52

MCP4021/2/3/4

Package Marking Information

8-Lead DFN (2x3) (MCP4021)

Example:

XXX

YWW

NNN

AAA

530

256

Part Number

Code

MCP4021T-202E/MC

MCP4021T-502E/MC

MCP4021T-103E/MC

MCP4021T-503E/MC

AAA

AAB

AAC

AAD

Note: Applies to 8-Lead DFN

Example:

8-Lead MSOP (MCP4021)

XXXXXX

402122

YWWNNN

530256

8-Lead SOIC (150 mil) (MCP4021)

Example:

XXXXXXXX

402153E

e

3

XXXXYYWW

SN^^ 0530

NNN

256

Part Numbers

Code

8L-MSOP

8L-SOIC

MCP4021-202E/MS MCP4021-202E/SN

MCP4021-502E/MS MCP4021-502E/SN

MCP4021-103E/MS MCP4021-103E/SN

MCP4021-503E/MS MCP4021-503E/SN

22

52

13

53

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS21945E-page 53

MCP4021/2/3/4

5-Lead Plastic Small Outline Transistor (OT) (SOT-23)

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

B

p1

D

n

1

α

c

A

A2

φ

L

A1

β

Units

INCHES

NOM

*

MILLIMETERS

NOM

5

Dimension Limits

MIN

MAX

MIN

MAX

n

p

Number of Pins

Pitch

5

.038

0.95

p1

Outside lead pitch (basic)

Overall Height

.075

.046

.043

.003

.110

.064

.116

.018

1.90

A

A2

A1

E

.035

.057

0.90

1.18

1.45

1.30

0.15

3.00

1.75

3.10

0.55

Molded Package Thickness

Standoff

.035

.000

.102

.059

.110

.014

.051

.006

.118

.069

.122

.022

10

0.90

0.00

2.60

1.50

2.80

0.35

1.10

0.08

Overall Width

2.80

Molded Package Width

Overall Length

E1

D

1.63

2.95

Foot Length

L

f

0.45

Foot Angle

0

5

0

5

10

c

Lead Thickness

Lead Width

.004

.014

.006

.017

.008

.020

10

0.09

0.35

0.15

0.43

0.20

0.50

B

a

b

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

0

5

10

0

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

EIAJ Equivalent: SC-74A

Revised 09-12-05

Drawing No. C04-091

DS21945E-page 54

MCP4021/2/3/4

6-Lead Plastic Small Outline Transistor (CH) (SOT-23)

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

B

p1

D

n

1

α

c

A

φ

A2

A1

β

L

Units

INCHES

*

MILLIMETERS

Dimension Limits

MIN

NOM

MAX

MIN

NOM

6

MAX

n

p

Number of Pins

Pitch

6

.038 BSC

.075 BSC

0.95 BSC

1.90 BSC

1.18

1.10

0.08

2.80

1.63

2.95

0.45

5

p1

Outside lead pitch

Overall Height

A

A2

A1

E

.035

.000

.102

.059

.110

.014

.046

.043

.003

.110

.064

.116

.018

.057

0.90

1.45

Molded Package Thickness

Standoff

.051

.006

.118

.069

.122

.022

10

0.90

0.00

2.60

1.50

2.80

0.35

1.30

0.15

3.00

1.75

3.10

0.55

Overall Width

Molded Package Width

Overall Length

E1

D

Foot Length

L

φ

Foot Angle

0

5

0

10

c

Lead Thickness

Lead Width

.004

.014

.006

.017

.008

.020

10

0.09

0.35

0.15

0.43

5

0.20

0.50

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

0

10

5

*

Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side.

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

See ASME Y14.5M

JEITA (formerly EIAJ) equivalent: SC-74A

Drawing No. C04-120

Revised 09-12-05

DS21945E-page 55

MCP4021/2/3/4

8-Lead Plastic Dual-Flat No-Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

e

D

b

N

L

K

E

E2

EXPOSED PAD

NOTE 1

2

1

D2

TOP VIEW

BOTTOM VIEW

A

NOTE 2

Units

A1

A3

MILLIMETERS

Dimension Limits

NOM

8

MAX

MIN

Number of Pins

Pitch

N

e

0.50 BSC

0.90

0.80

0.00

Overall Height

Standoff

A

1.00

0.05

0.02

A1

A3

D

0.20 REF

2.00 BSC

3.00 BSC

—

Contact Thickness

Overall Length

Overall Width

E

1.30

1.50

0.18

0.30

0.20

Exposed Pad Length

Exposed Pad Width

Contact Width

D2

E2

b

1.75

1.90

0.30

0.50

—

0.25

0.40

Contact Length §

L

—

Contact-to-Exposed Pad §

K

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package may have one or more exposed tie bars at ends.

3. § Significant Characteristic

4. Package is saw singulated

5. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–123, Sept. 8, 2006

DS21945E-page 56

MCP4021/2/3/4

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

N

E

E1

NOTE 1

2

b

1

e

c

ϕ

A2

A

L1

L

A1

Units

MILLIMETERS

Dimension Limits

NOM

8

MAX

MIN

Number of Pins

Pitch

N

e

0.65 BSC

—

Overall Height

A

1.10

0.95

0.15

0.75

0.00

0.85

Molded Package Thickness

Standoff

A2

A1

E

—

4.90 BSC

3.00 BSC

0.60

Overall Width

Molded Package Width

Overall Length

Foot Length

E1

D

0.40

L

0.80

0.95 REF

—

Footprint

L1

0°

Foot Angle

ϕ

8°

0.08

0.22

—

Lead Thickness

Lead Width

c

0.23

0.40

—

b

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions

shall not exceed 0.15 mm per side.

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing No. C04–111, Sept. 8, 2006

DS21945E-page 57

MCP4021/2/3/4

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

Note:

For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

E

E1

p

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

MILLIMETERS

Dimension Limits

MIN

NOM

8

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

.050

1.27

Overall Height

A

.053

.061

.056

.007

.237

.154

.193

.015

.025

4

.069

1.35

1.32

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

0.10

5.79

3.71

4.80

0.25

0.48

0

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS21945E-page 58

MCP4021/2/3/4

APPENDIX A: REVISION HISTORY

Revision E (December 2006)

• Added device designators in conditions column to

associate units (MHz) in Bandwidth -3 dB

parameter in AC/DC Characteristics table

• Added device designations in conditions column

for R-INL and R-DNL specifications.

• Added disclaimers to package outline drawings.

Revision D (October 2006)

• Changed the EEPROM write cycle time (T_WC

)

from a maximum of 5 ms to a maximum of 10 ms

(overvoltage and temperature) with a typical of

5 ms

• For the 10 kΩ device, the rheostat differential

non-linearity specification at 2.7V was changed

from ±0.5 LSb to ±1.0 LSb

• Figure 2-9 in Section 2.0 “Typical Performance

Curves” was updated with the correct data.

• Added Figure 2-48 for -3 db Bandwidth

information.

• Updated available Development Tools.

• Added disclaimer to package outline drawings.

Revision C (November 2005)

• Enhanced Descriptions

• Reordered Sections

• Added 8-lead MSOP and DFN packages

Revision B (April 2005)

• Updated part numbers in Product Identifcation

Section (PIS)

• Added Appendix A: Revision History

Revision A (April 2005)

• Original Release of this Document

DS21945E-page 59

MCP4021/2/3/4

NOTES:

DS21945E-page 60

MCP4021/2/3/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

XXX

X

/XX

a)

b)

c)

d)

e)

f)

g)

h)

i)

MCP4021-103E/MS: 10 kΩ, 8-LD MSOP

Resistance Temperature Package

Version Range

MCP4021-103E/SN: 10 kΩ, 8-LD SOIC

MCP4021T-103E/MC: T/R, 10 kΩ, 8-LD DFN

MCP4021T-103E/MS: T/R, 10 kΩ, 8-LD MSOP

MCP4021T-103E/SN: T/R, 10 kΩ, 8-LD SOIC

MCP4021-202E/MS: 2.1 kΩ, 8-LD MSOP

MCP4021-202E/SN: 2.1 kΩ, 8-LD SOIC

MCP4021T-202E/MC: T/R, 2.1 kΩ, 8-LD DFN

MCP4021T-202E/MS: T/R, 2.1 kΩ, 8-LD MSOP

MCP4021T-202E/SN: T/R, 2.1 kΩ, 8-LD SOIC

MCP4021-502E/MS: 5 kΩ, 8-LD MSOP

MCP4021-502E/SN: 5 kΩ, 8-LD SOIC

Device:

MCP4021:

MCP4021T:

Single Potentiometer with U/D Interface

(Tape and Reel) (SOIC, MSOP)

Single Rheostat with U/D interface

(Tape and Reel) (SOT-23-6)

Single Potentiometer to GND with U/D

Interface

Single Potentiometer to GND with U/D

Interface (Tape and Reel) (SOT-23-6)

Single Rheostat to GND with U/D

Interface

MCP4022:

MCP4022T:

j)

k)

l)

MCP4023:

MCP4023T:

MCP4024:

MCP4024T:

m) MCP4021T-502E/MC: T/R, 5 kΩ, 8-LD DFN

n)

o)

p)

q)

r)

MCP4021T-502E/MS: T/R, 5 kΩ, 8-LD MSOP

MCP4021T-502E/SN: T/R, 5 kΩ, 8-LD SOIC

MCP4021-503E/MS: 50 kΩ, 8-LD MSOP

MCP4021-503E/SN: 50 kΩ, 8-LD SOIC

MCP4021T-503E/MC: T/R, 50 kΩ, 8-LD DFN

MCP4021T-503E/MS: T/R, 50 kΩ, 8-LD MSOP

MCP4021T-503E/SN: T/R, 50 kΩ, 8-LD SOIC

Single Rheostat to GND with U/D

Interface (Tape and Reel)(SOT-23-5)

s)

t)

a)

b)

c)

d)

MCP4022T-202E/CH 2.1 kΩ, 6-LD SOT-23

MCP4022T-502E/CH 5 kΩ, 6-LD SOT-23

MCP4022T-103E/CH 10 kΩ, 6-LD SOT-23

MCP4022T-503E/CH 50 kΩ, 6-LD SOT-23

Resistance Version:

202 = 2.1 kΩ

502 = 5 kΩ

103 = 10 kΩ

503 = 50 kΩ

a)

b)

c)

d)

MCP4023T-202E/CH 2.1 kΩ, 6-LD SOT-23

MCP4023T-502E/CH 5 kΩ, 6-LD SOT-23

MCP4023T-103E/CH 10 kΩ, 6-LD SOT-23

MCP4023T-503E/CH 50 kΩ, 6-LD SOT-23

Temperature Range:

Package:

E

=

-40°C to +125°C

CH

MC

MS

SN

OT

=

Plastic Small Outline Transistor, 6-lead

Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead

Plastic MSOP, 8-lead

Plastic SOIC, (150 mil Body), 8-lead

Plastic Small Outline Transistor, 5-lead

a)

b)

c)

d)

MCP4024T-202E/OT 2.1 kΩ, 5-LD SOT-23

MCP4024T-502E/OT 5 kΩ, 5-LD SOT-23

MCP4024T-103E/OT 10 kΩ, 5-LD SOT-23

MCP4024T-503E/OT 50 kΩ, 5-LD SOT-23

DS21945E-page 61

MCP4021/2/3/4

NOTES:

DS21945E-page 62

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, ECAN,

ECONOMONITOR, FanSense, FlexROM, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active

Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit,

PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal,

PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance, UNI/O, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona, Gresham, Oregon and Mountain View, California. The

Company’s quality system processes and procedures are for its PIC^®

8-bit MCUs, KEELOQ^®code hopping devices, Serial EEPROMs,

microperipherals, nonvolatile memory and analog products. In addition,

Microchip’s quality system for the design and manufacture of

development systems is ISO 9001:2000 certified.

DS21945E-page 63

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Habour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Gumi

Tel: 82-54-473-4301

Fax: 82-54-473-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Malaysia - Penang

Tel: 60-4-646-8870

Fax: 60-4-646-5086

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Shunde

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7250

Fax: 86-29-8833-7256

12/08/06

DS21945E-page 64


型号：	MCP4024T-103E/OT
厂家：	MICROCHIP
描述：	Low-Cost NV Digital POT with WiperLock⑩ Technology 低成本非易失数字电位器与WiperLock™技术电位器
文件：	总64页 (文件大小：3305K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4024T-103E/OT [MICROCHIP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E