MCP4231-103I/SN_技术文档

MCP413X/415X/423X/425X

7/8-Bit Single/Dual SPI Digital POT with Volatile Memory

Features

Description

• Single or Dual Resistor Network options

• Potentiometer or Rheostat configuration options

• Resistor Network Resolution

- 7-bit: 128 Resistors (129 Steps)

- 8-bit: 256 Resistors (257 Steps)

• R_ABResistances options of:

- 5 kΩ

The MCP41XX and MCP42XX devices offer a wide

range of product offerings using an SPI interface. This

family of devices support 7-bit and 8-bit resistor

networks, and Potentiometer and Rheostat pinouts.

Package Types (top view)

MCP41X1

MCP41X2

Single Potentiometer

- 10 kΩ

Single Rheostat

- 50 kΩ

CS

SCK

SDI

CS

SCK

SDI/SDO

1

2

3

4

V_DD

P0B

P0W

P0A

1

2

3

4

V

DD

8

7

6

5

8

7

6

5

SDO

P0B

P0W

- 100 kΩ

• Zero Scale to Full-Scale Wiper operation

• Low Wiper Resistance: 75Ω (typical)

• Low Tempco:

V_SS

V

SS

PDIP, SOIC, MSOP

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

CS

V_DD

1

2

8 V_DD

1

2

8

7

SCK

SDI/SDO

V_SS

P0B SCK

SDO

7

EP

9

EP

9

- Ratiometric (Potentiometer): 15 ppm typical

• SPI Serial Interface (10 MHz, modes 0,0 & 1,1)

- High-Speed Read/Writes to wiper registers

- SDI/SDO multiplexing (MCP41X1 only)

P0W

P0A

SDI

V_SS

P0B

3

4

6

5

3

4

6

5

P0W

3x3 DFN*

• Resistor Network Terminal Disconnect Feature

via:

MCP42X1 Dual Potentiometers

- Shutdown pin (SHDN)

- Terminal Control (TCON) Register

• Brown-out reset protection (1.5V typical)

• Serial Interface Inactive current (2.5 uA typical)

• High-Voltage Tolerant Digital Inputs: Up to 12.5V

• Supports Split Rail Applications

16 15 14 13

V_DD

SDO

CS

SCK

SDI

14

13

1

2

3

4

5

6

7

SCK

SDI

V_SS

WP

1

12

11

10

9

12 SHDN

NC

2

3

4

EP

17

V_SS

WP

11

10

9

P0B

P0W

P0B

P0W

P0A

P1B

P1W

P1A

• Internal weak pull-up on all digital inputs

• Wide Operating Voltage:

8

5

6

7

8

PDIP, SOIC, TSSOP

- 2.7V to 5.5V - Device Characteristics

Specified

4x4 QFN*

MCP42X2 Dual Rheostat

- 1.8V to 5.5V - Device Operation

• Wide Bandwidth (-3 dB) Operation:

- 2 MHz (typical) for 5.0 kΩ device

CS

V

DD

1

2

10

9

V_DD

CS

SCK

SDI

10

9

1

2

3

4

5

• Extended temperature range (-40°C to +125°C)

SDO

P0B

P0W

P1W

SCK

SDO

EP

11

8

SDI

V_SS

P0B

P0W

P1W

3

4

8

7

6

V_SS

7

6

P1B

P1B 5

MSOP, DFN

3x3 DFN*

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS22060B-page 1

MCP413X/415X/423X/425X

Device Block Diagram

V_DD

V_SS

Power-up/

Brown-out

Control

P0A

Resistor

Network 0

(Pot 0)

P0W

Wiper 0

& TCON

Register

CS

SCK

SDI

SPI Serial

Interface

Module &

Control

P0B

P1A

SDO

Logic

(WiperLock™

Technology)

Resistor

Network 1

(Pot 1)

NC

SHDN

P1W

P1B

For Dual Potentiometer

Devices Only

Wiper 1

& TCON

Register

Memory (4x9)

Wiper0

Wiper1

TCON

STATUS

For Dual Resistor Network

Devices Only

Device Features

Resistance (typical)

V_DD

Wiper

Configuration

Wiper

Device

Operating

Range ⁽²⁾

R

_ABOptions (kΩ)

- R_W

(Ω)

MCP4131 ⁽³⁾

MCP4132 ⁽³⁾

MCP4141

1

2

Potentiometer⁽¹⁾SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾SPI

Rheostat SPI

75

129 1.8V to 5.5V

129 2.7V to 5.5V

257 1.8V to 5.5V

257 2.7V to 5.5V

129 1.8V to 5.5V

129 2.7V to 5.5V

257 1.8V to 5.5V

257 2.7V to 5.5V

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4142

MCP4151 ⁽³⁾

MCP4152 ⁽³⁾

MCP4161

Potentiometer⁽¹⁾SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾SPI

Rheostat SPI

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4162

MCP4231 ⁽³⁾

MCP4232 ⁽³⁾

MCP4241

Potentiometer⁽¹⁾SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾SPI

Rheostat SPI

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4242

MCP4251 ⁽³⁾

MCP4252 ⁽³⁾

MCP4261

Potentiometer⁽¹⁾SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat SPI RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾SPI

Rheostat SPI

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4262

Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).

2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.

3: Please check Microchip web site for device release and availability.

DS22060B-page 2

MCP413X/415X/423X/425X

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on V_DDwith respect to V_SS............... -0.6V to +7.0V

Voltage on CS, SCK, SDI, SDI/SDO, and

may affect device reliability.

SHDN with respect to V_{SS ......................................}-0.6V to 12.5V

Voltage on all other pins (PxA, PxW, PxB, and

SDO) with respect to V_{SS ............................}-0.3V to V_DD+ 0.3V

Input clamp current, I_IK

(V_I< 0, V_I> V_DD, V_I> V_PPON HV pins)......................±20 mA

Output clamp current, I_OK

(V_O< 0 or V_O> V_DD) ..................................................±20 mA

Maximum output current sunk by any Output pin

......................................................................................25 mA

Maximum output current sourced by any Output pin

......................................................................................25 mA

Maximum current out of V_SSpin .................................100 mA

Maximum current into V_DDpin ....................................100 mA

Maximum current into PXA, PXW & PXB pins ............±2.5 mA

Storage temperature ....................................-65°C to +150°C

Ambient temperature with power applied

.....................................................................-40°C to +125°C

Total power dissipation (Note 1) ................................400 mW

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins .................................. ≥ 4 kV (HBM),

.......................................................................... ≥ 300V (MM)

Maximum Junction Temperature (T_J) .........................+150°C

Note 1: Power dissipation is calculated as follows:

Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL)

DS22060B-page 3

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

2.7

1.8

—

5.5

2.7

V

Serial Interface only.

CS, SDI, SDO,

SCK, SHDN pin

Voltage Range

V_HV

V_SS

12.5V

V_DD

4.5V

≥

The CS pin will be at one

of three input levels

(V_IL, V_IHor V_IHH). (Note 6)

V_SS

—

V_DD

8.0V

+

V

V_DD

<

4.5V

V_DDStart Voltage

to ensure Wiper

Reset

V_BOR

V_DDRR

T_BORD

1.65

RAM retention voltage (V_RAM) < V_BOR

V_DDRise Rate to

ensure Power-on

Reset

(Note 9)

V/ms

µs

Delay after device

exits the reset

state

—

10

20

(V_DD> V_BOR

)

Supply Current

I_DD

—

450

µA

Serial Interface Active,

(Note 10)

V_DD= 5.5V, CS = V_IL, SCK @ 5 MHz,

write all 0’s to volatile Wiper 0 (address

0h)

—

2.5

5

1

µA

Serial Interface Inactive,

CS = V_IH, V_DD= 5.5V

0.55

mA

Serial Interface Active,

V_DD= 5.5V, CS = V_IHH

,

SCK @ 5 MHz,

decrement volatile Wiper 0 (address 0h)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 4

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

-502 devices (Note 1)

Resistance

(± 20%)

R_AB

4.0

8.0

5

10

6.0

12.0

60.0

120.0

kΩ

-103 devices (Note 1)

-503 devices (Note 1)

-104 devices (Note 1)

40.0

80.0

50

100

257

129

R_AB

Resolution

N

Taps 8-bit

Taps 7-bit

No Missing Codes

Note 6

Step Resistance

R_S

—

/

—

Ω

8-bit

(256)

R_AB

(128)

/

Ω

7-bit

Note 6

Nominal

Resistance Match

|R_AB0- R_AB1

/ R_AB

|

0.2

1.25

1.5

%

MCP42X1 devices only

|R_BW0- R_BW1

|

0.25

MCP42X2 devices only,

/ R_BW

Code = Full-Scale

Wiper Resistance

(Note 3, Note 4)

R_W

—

75

160

300

—

Ω

V_DD= 5.5 V, I_W= 2.0 mA, code = 00h

V_DD= 2.7 V, I_W= 2.0 mA, code = 00h

Nominal

Resistance

Tempco

ΔR_AB/ΔT

50

ppm/°C T_A= -20°C to +70°C

ppm/°C T_A= -40°C to +85°C

ppm/°C T_A= -40°C to +125°C

ppm/°C Code = Midscale (80h or 40h)

100

150

15

—

Ratiometeric

Tempco

ΔV_WB/ΔT

—

Resistor Terminal

Input Voltage

Range (Terminals

A, B and W)

V_A,V_W,V_B

V_SS

—

V_DD

2.5

V

Note 5, Note 6

Maximum current

through A, W or B

I_W

—

mA

Note 6, Worst case current through

wiper when wiper is either Full-Scale or

Zero Scale.

Leakage current

into A, W or B

I_WL

—

100

—

nA

MCP4XX1 PxA = PxW = PxB = V_SS

MCP4XX2 PxB = PxW = V_SS

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 5

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Full-Scale Error

(MCP4XX1 only)

(8-bit code =

100h,

V_WFSE

-6.0

-4.0

-3.5

-2.0

-0.8

-0.5

—

-0.1

—

LSb

5 kΩ

8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

10 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

7-bit code = 80h)

-0.1

—

50 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

-0.1

—

100 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

-0.1

—

Zero-Scale Error

(MCP4XX1 only)

(8-bit code = 00h,

7-bit code = 00h)

V_WZSE

+0.1

±0.5

±0.25

+6.0

+3.0

+3.5

+2.0

+0.8

+0.5

+1

5 kΩ

8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

10 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

50 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

100 kΩ 8-bit 3.0V ≤ V_DD≤ 5.5V

7-bit 3.0V ≤ V_DD≤ 5.5V

—

Potentiometer

Integral

Non-linearity

INL

DNL

BW

-1

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

MCP4XX1 devices only

(Note 2)

-0.5

+0.5

Potentiometer

Differential

Non-linearity

-0.5

±0.25

+0.5

LSb

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

MCP4XX1 devices only

(Note 2)

-0.25

±0.125

+0.25

Bandwidth -3 dB

(See Figure 2-64,

load = 30 pF)

—

2

—

MHz 5 kΩ

8-bit Code = 80h

7-bit Code = 40h

MHz

1

MHz 10 kΩ 8-bit Code = 80h

1

MHz

kHz

7-bit Code = 40h

50 kΩ 8-bit Code = 80h

7-bit Code = 40h

200

100

100 kΩ 8-bit Code = 80h

7-bit Code = 40h

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 6

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat Integral

Non-linearity

MCP41X1

(Note 4, Note 8)

MCP4XX2

R-INL

-1.5

±0.5

+4.5

+1.5

LSb

5 kΩ

8-bit 5.5V, I_W= 900 µA

-8.25

+8.25

3.0V, I_W= 480 µA

(Note 7)

Section 2.0

1.8V

-1.125

-6.0

±0.5

+4.5

+1.125

+6.0

LSb

7-bit 5.5V, I_W= 900 µA

devices only

(Note 4)

3.0V, I_W= 480 µA

(Note 7)

Section 2.0

1.8V

-1.5

-5.5

±0.5

+2.5

+1.5

+5.5

LSb

10 kΩ 8-bit 5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

Section 2.0

1.8V

-1.125

-4.0

±0.5

+2.5

+1.125

+4.0

LSb

7-bit 5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

Section 2.0

1.8V

-1.5

-2.0

±0.5

+1

+1.5

+2.0

LSb

50 kΩ 8-bit 5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

Section 2.0

1.8V

-1.125

-1.5

±0.5

+1

+1.125

+1.5

LSb

7-bit 5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

Section 2.0

1.8V

-1.0

-1.5

±0.5

+1.0

+1.5

LSb

100 kΩ 8-bit 5.5V, I_W= 45 µA

+0.25

3.0V, I_W= 24 µA

(Note 7)

Section 2.0

1.8V

-0.8

±0.5

+0.8

+1.125

LSb

7-bit 5.5V, I_W= 45 µA

-1.125

+0.25

3.0V, I_W= 24 µA

(Note 7)

Section 2.0

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

1.8v

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 7

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Rheostat

R-DNL

-0.5

-1.0

±0.25

+0.5

+1.0

LSb

5 kΩ

8-bit 5.5V, I_W= 900 µA

3.0V (Note 7)

1.8V

Differential

Non-linearity

MCP41X1

(Note 4, Note 8)

MCP4XX2

devices only

(Note 4)

Section 2.0

-0.375

-0.75

±0.25

+0.5

+0.375

+0.75

LSb

7-bit 5.5V, I_W= 900 µA

3.0V (Note 7)

1.8V

Section 2.0

-0.5

-1.0

±0.25

+0.25

+0.5

+1.0

LSb

10 kΩ 8-bit 5.5V, I_W= 450 µA

3.0V (Note 7)

Section 2.0

1.8V

-0.375

-0.75

±0.25

+0.5

+0.375

+0.75

LSb

7-bit 5.5V, I_W= 450 µA

3.0V (Note 7)

Section 2.0

1.8V

-0.5

±0.25

+0.5

LSb

50 kΩ 8-bit 5.5V, I_W= 90 µA

3.0V (Note 7)

Section 2.0

1.8V

-0.375

±0.25

+0.375

LSb

7-bit 5.5V, I_W= 90 µA

3.0V (Note 7)

Section 2.0

1.8V

-0.5

±0.25

+0.5

LSb

100 kΩ 8-bit 5.5V, I_W= 45 µA

3.0V (Note 7)

Section 2.0

1.8V

-0.375

±0.25

+0.375

LSb

7-bit 5.5V, I_W= 45 µA

3.0V (Note 7)

+0.375

1.8V

Capacitance (P_A)

Capacitance (P_w)

Capacitance (P_B)

C_AW

C_W

—

75

120

75

—

pF

f =1 MHz, Code = Full-Scale

C_BW

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 8

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (CS, SDI, SDO, SCK, SHDN)

Schmitt Trigger

High Input

Threshold

V_IH

0.45 V_DD

—

V

2.7V ≤ V_DD≤ 5.5V

(Allows 2.7V Digital V_DDwith

5V Analog V_DD

)

0.5 V_DD

—

V

1.8V ≤ V_DD≤ 2.7V

Schmitt Trigger

Low Input

V_IL

0.2V_DD

Threshold

Hysteresis of

Schmitt Trigger

Inputs

V_HYS

—

0.1V_DD

—

V

High Voltage Limit

V_MAX

V_OL

—

V_SS

—

12.5 ⁽⁶⁾

0.3V_DD

V_DD

V

Pin can tolerate V_MAXor less.

I_OL= 5 mA, V_DD= 5.5V

I_OL= 1 mA, V_DD= 1.8V

I_OH= -2.5 mA, V_DD= 5.5V

I_OL= -1 mA, V_DD= 1.8V

Output Low

Voltage (SDO)

V_SS

V

Output High

Voltage (SDO)

V_OH

I_PU

0.7V_DD

—

V

V_DD

V

Weak Pull-up /

1.75

mA

Internal V_DDpull-up, V_IHHpull-down,

V_DD= 5.5V, V_CS= 12.5V

Pull-down Current

—

170

16

—

µA

CS pin, V_DD= 5.5V, V_CS= 3V

V_DD= 5.5V, V_CS= 3V

CS Pull-up /

Pull-down

R_CS

kΩ

Resistance

Input Leakage

Current

I_IL

-1

—

1

µA

pF

V_IN= V_DDand V_IN= V_SS

f_C= 20 MHz

Pin Capacitance

RAM (Wiper) Value

Value Range

C_IN, C_OUT

—

10

—

N

0h

—

1FFh

—

hex

8-bit device

7-bit device

8-bit device

7-bit device

POR/BOR Value

80h

40h

—

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 9

MCP413X/415X/423X/425X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Power Requirements

Power Supply

Sensitivity

(MCP41X2 and

MCP42X2 only)

PSS

—

0.0015 0.0035

%/% 8-bit

%/% 7-bit

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 80h

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 40h

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP41X2 and MCP42X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

DS22060B-page 10

MCP413X/415X/423X/425X

1.1

SPI Mode Timing Waveforms and Requirements

V_IHH

V_IH

84

CS

V_IL

70

72

SCK

83

71

80

78

79

MSb

LSb

SDO

SDI

BIT6 - - - - - -1

77

75, 76

MSb IN

74

BIT6 - - - -1

LSb IN

73

FIGURE 1-1:

SPI Timing Waveform (Mode = 11).

TABLE 1-1:

#

SPI REQUIREMENTS (MODE = 11)

Characteristic

Symbol

Min

Max Units

Conditions

SCK Input Frequency

F_SCK

—

10

1

MHz V_DD= 2.7V to 5.5V

MHz V_DD= 1.8V to 2.7V

ns

70 CS Active (V_ILor V_IHH) to SCK↑ input

71 SCK input high time

TcsA2scH

TscH

60

45

500

45

500

10

20

—

50

70

170

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

72 SCK input low time

TscL

73 Setup time of SDI input to SCK↑ edge

74 Hold time of SDI input from SCK↑ edge

77 CS Inactive (V_IH) to SDO output hi-impedance

80 SDO data output valid after SCK↓ edge

TDIV2scH

TscH2DIL

TcsH2DOZ

TscL2DOV

ns

ns Note 1

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ms V_DD= 1.8V to 2.7V

ns

83 CS Inactive (V_IH) after SCK↑ edge

TscH2csI

TcsA2csI

100

1

84 Hold time of CS Inactive (V_IH) to

50

—

CS Active (V_ILor V_IHH

)

Note 1: This specification by design.

DS22060B-page 11

MCP413X/415X/423X/425X

V_IHH

V_IH

82

V_IH

84

CS

V_IL

70

SCK

83

80

71

72

MSb

BIT6 - - - - - -1

LSb

SDO

SDI

75, 76

77

73

MSb IN

74

BIT6 - - - -1

LSb IN

FIGURE 1-2:

SPI Timing Waveform (Mode = 00).

TABLE 1-2:

#

SPI REQUIREMENTS (MODE = 00)

Characteristic

Symbol

Min

Max Units

Conditions

SCK Input Frequency

F_SCK

—

10

1

MHz V_DD= 2.7V to 5.5V

MHz V_DD= 1.8V to 2.7V

ns

70 CS Active (V_ILor V_IHH) to SCK↑ input

71 SCK input high time

TcsA2scH

TscH

60

45

500

45

500

10

20

—

50

70

170

70

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

72 SCK input low time

TscL

73 Setup time of SDI input to SCK↑ edge

74 Hold time of SDI input from SCK↑ edge

77 CS Inactive (V_IH) to SDO output hi-impedance

80 SDO data output valid after SCK↓ edge

TDIV2scH

TscH2DIL

TcsH2DOZ

TscL2DOV

ns

ns Note 1

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

82 SDO data output valid after

TssL2doV

TscH2csI

—

CS Active (V_ILor V_IHH

)

83 CS Inactive (V_IH) after SCK↓ edge

100

1

—

ns V_DD= 2.7V to 5.5V

ms V_DD= 1.8V to 2.7V

ns

84 Hold time of CS Inactive (V_IH) to

TcsA2csI

50

CS Active (V_ILor V_IHH

)

Note 1: This specification by design.

DS22060B-page 12

MCP413X/415X/423X/425X

(2)

TABLE 1-3:

SPIREQUIREMENTSFORSDI/SDOMULTIPLEXED(READOPERATIONONLY)

Characteristic

Symbol

Min

Max Units

Conditions

SCK Input Frequency

F_SCK

—

60

1.8

40

—

250 kHz V_DD= 2.7V to 5.5V

CS Active (V_ILor V_IHH) to SCK↑ input

SCK input high time

TcsA2scH

TscH

—

ns

us

SCK input low time

TscL

—

ns

Setup time of SDI input to SCK↑ edge

Hold time of SDI input from SCK↑ edge

CS Inactive (V_IH) to SDO output hi-impedance

SDO data output valid after SCK↓ edge

SDO data output valid after

TDIV2scH

TscH2DIL

TcsH2DOZ

TscL2DOV

TssL2doV

—

ns

—

ns

50

1.6

50

ns Note 1

—

us

ns

—

CS Active (V_ILor V_IHH

)

CS Inactive (V_IH) after SCK↓ edge

Hold time of CS Inactive (V_IH) to

TscH2csI

TcsA2csI

100

50

—

ns

CS Active (V_ILor V_IHH

)

Note 1: This specification by design.

2: This table is for the devices where the SPI’s SDI and SDO pins are multiplexed (SDI/SDO) and a Read

command is issued. This is NOT required for SDI/SDO operation with the Increment, Decrement, or Write

commands. This data rate can be increased by having external pull-up resistors to increase the rising

edges of each bit.

DS22060B-page 13

MCP413X/415X/423X/425X

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 8L-DFN (3x3)

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 10L-DFN (3x3)

Thermal Resistance, 10L-MSOP

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

Thermal Resistance, 16L-QFN

T_A

-40

-65

—

+125

+150

°C

θ_JA

—

84.5

211

89.3

149.5

57

—

°C/W

211

70

95.3

100

47

DS22060B-page 14

MCP413X/415X/423X/425X

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

650

600

250

200

150

100

50

1000

800

600

400

200

0

2.7V -40°C

2.7V 25°C

550

500

450

400

350

300

250

200

150

100

50

2.7V 85°C

2.7V 125°C

5.5V -40°C

5.5V 25°C

5.5V 85°C

5.5V 125°C

I_CS

-200

-400

-600

-800

-1000

R_CS

0

0.00

2.00

4.00

6.00

f_SCK(MHz)

8.00 10.00 12.00

2

3

4

5

6

7

8

9

10

V_CS(V)

FIGURE 2-1:

Frequency (f

Device Current (I ) vs. SPI

) and Ambient Temperature

FIGURE 2-3:

Resistance (R ) and Current (I ) vs. CS Input

CS Pull-up/Pull-down

DD

SCK

CS

(V = 2.7V and 5.5V).

Voltage (V ) (V = 5.5V).

DD

CS DD

3.0

2.5

2.0

1.5

1.0

0.5

0.0

12

10

8

5.5V Entry

5.5V Exit

5.5V

2.7V Entry

6

4

2.7V Exit

2.7V

2

0

-40

25

85

125

-40 -20

0

20

40

60

80

100 120

Ambient Temperature (°C)

FIGURE 2-2:

Device Current (I

) and

FIGURE 2-4:

CS High Input Entry/Exit

SHDN

V

. (CS = V ) vs. Ambient Temperature.

Threshold vs. Ambient Temperature and V

.

DD

DS22060B-page 15

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1.25

0.75

0.25

-0.25

-0.75

-1.25

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

DNL

-40°C

40

-40°C 25°C

R_W

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-5:

5 kΩ Pot Mode – R (Ω),

FIGURE 2-8:

5 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

6

260

220

180

140

100

60

260

220

180

140

100

60

INL

4

DNL

2

R_W

125°C

-0.1

-0.2

-0.3

0

-40°C

85°C

25°C

DNL

-40°C

125°C 85°C

20

-2

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-6:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

5 kΩ Pot Mode – R (Ω),

FIGURE 2-9:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

5 kΩ Rheo Mode – R (Ω),

W

DD

118

98

78

58

38

18

-2

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.5

0.4

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

2500

2000

1500

1000

500

2500

2000

1500

1000

500

INL

-0.1

-0.2

-0.3

DNL

RW

0

64

128

192

256

0

64

128

192

256

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-7:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

5 kΩ Pot Mode – R (Ω),

FIGURE 2-10:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

5 kΩ Rheo Mode – R (Ω),

W

DD

DS22060B-page 16

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

6000

5000

4000

3000

2000

1000

0

5300

5250

5200

5150

5100

5050

2.7V

5.5V

-40°C

25°C

85°C

125°C

1.8V

-40

0

40

80

120

0

32

64

96

128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-11:

5 kΩ – Nominal Resistance

FIGURE 2-12:

5 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22060B-page 17

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-13:

5 kΩ – Low-Voltage

FIGURE 2-16:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-14:

5 kΩ – Low-Voltage

FIGURE 2-17:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-15:

5 kΩ – Power-Up Wiper

Response Time (20 ms/Div).

DS22060B-page 18

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.5

0

INL

DNL

60

-0.1

-0.2

-0.3

-0.5

-1

DNL

40

-40°C

R_W

-40°C

25°C

85°C

85°C 25°C

R_W

125°C

20

0

25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-18:

10 kΩ Pot Mode – R (Ω),

FIGURE 2-21:

10 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

4

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

260

220

180

140

100

60

3

260

220

180

140

100

60

INL

DNL

2

1

0

-0.1

-0.2

-0.3

R_W

DNL

R_W

-1

-2

-40°C

25°C

85°C 25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

FIGURE 2-19:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

10 kΩ Pot Mode – R (Ω),

FIGURE 2-22:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

10 kΩ Rheo Mode – R (Ω),

W

DD

98

88

78

68

58

48

38

28

18

8

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.6

0.5

0.4

0.3

0.2

0.1

0

4000

3500

3000

2500

2000

1500

1000

500

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

4000

3500

3000

2500

2000

1500

1000

500

INL

DNL

-0.1

-0.2

-0.3

RW

64

DNL

RW

0

-2

0

64

128

192

256

0

128

192

256

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-20:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

10 kΩ Pot Mode – R (Ω),

FIGURE 2-23:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

10 kΩ Rheo Mode – R (Ω),

W

DD

DS22060B-page 19

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

12000

10000

8000

6000

4000

2000

0

10300

10250

10200

10150

10100

2.7V

10050

10000

-40°C

25°C

85°C

5.5V

9950

1.8V

9900

9850

125°C

-40

0

40

80

120

0

32

64

96 128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-24:

10 kΩ – Nominal Resistance

FIGURE 2-25:

10 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22060B-page 20

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-26:

10 kΩ – Low-Voltage

FIGURE 2-28:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-27:

10 kΩ – Low-Voltage

FIGURE 2-29:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

DS22060B-page 21

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40°C

40

-40°C

R_W

25°C

85°C

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-30:

50 kΩ Pot Mode – R (Ω),

FIGURE 2-33:

50 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.75

0.5

0.25

0

260

220

180

140

100

60

260

220

180

140

100

60

INL

DNL

-0.25

-0.5

-0.75

-1

R_W

-0.1

-0.2

-0.3

R_W

-40°C

25°C

85°C

25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-31:

50 kΩ Pot Mode – R (Ω),

FIGURE 2-34:

50 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

DD

15000

78.5

73.5

68.5

63.5

58.5

53.5

48.5

43.5

38.5

33.5

28.5

23.5

18.5

13.5

8.5

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

15000

0.5

0.4

0.3

0.2

0.1

0

14000

13000

12000

11000

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

14000

13000

12000

11000

10000

9000

8000

7000

6000

5000

4000

3000

2000

1000

0

RW

INL

DNL

-0.1

-0.2

-0.3

-0.4

-0.5

INL

RW

DNL

3.5

-1.5

0

64

128

192

256

0

25 50 75 100125150175200225250

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-35:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

50 kΩ Rheo Mode – R (Ω),

W

FIGURE 2-32:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

50 kΩ Pot Mode – R (Ω),

W

DD

DS22060B-page 22

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

52500

52000

51500

51000

50500

50000

49500

49000

60000

50000

40000

30000

20000

10000

0

1.8V

-40°C

25°C

85°C

125°C

2.7V

5.5V

-40

0

40

80

120

0

32

64

96 128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-36:

50 kΩ – Nominal Resistance

FIGURE 2-37:

50 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22060B-page 23

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-38:

50 kΩ – Low-Voltage

FIGURE 2-40:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-39:

50 kΩ – Low-Voltage

FIGURE 2-41:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

DS22060B-page 24

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

40

-40°C

R_W

25°C

85°C

R_W

85°C 25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-42:

100 kΩ Pot Mode – R (Ω),

FIGURE 2-45:

100 kΩ Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

0.6

0.4

0.2

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.2

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

260

220

180

140

100

60

0.15

0.1

260

220

180

140

100

60

INL

DNL

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.4

-0.6

R_W

-40°C

85°C 25°C

125°C

85°C

25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-43:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

100 kΩ Pot Mode – R (Ω),

FIGURE 2-46:

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

100 kΩ Rheo Mode – R

W

DD

59

54

49

44

39

34

29

24

19

14

9

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.25

-0.35

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

25000

20000

15000

10000

5000

0

25000

20000

15000

10000

5000

0

RW

INL

DNL

INL

RW

DNL

4

-1

0

64

128

192

256

0

64

128

192

256

Wiper Setting (decimal)

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

Note:

Refer to AN1080 for additional informa-

tion on the characteristics of the wiper

resistance (R_W) with respect to device

voltage and wiper setting value.

FIGURE 2-44:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

100 kΩ Pot Mode – R (Ω),

FIGURE 2-47:

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 1.8V).

100 kΩ Rheo Mode – R

W

DD

DS22060B-page 25

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120000

100000

80000

60000

40000

20000

0

103500

103000

102500

102000

101500

1.8V

101000

100500

-40°C

25°C

85°C

100000

2.7V

99500

99000

98500

5.5V

125°C

0

32

64

96 128 160 192 224 256

-40

0

40

80

120

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-48:

100 kΩ – Nominal

FIGURE 2-49:

100 kΩ – R

(Ω) vs. Wiper

WB

Resistance (Ω) vs. Ambient Temperature and

Setting and Ambient Temperature.

V

.

DD

DS22060B-page 26

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-50:

100 kΩ – Low-Voltage

FIGURE 2-52:

100 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-51:

100 kΩ – Low-Voltage

FIGURE 2-53:

100 kΩ – Power-Up Wiper

Decrement Wiper Settling Time (V = 2.7V)

Response Time (1 µs/Div).

DD

(1 µs/Div).

DS22060B-page 27

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

0.12

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

0.08

0.06

0.04

0.02

0

5.5V

3.0V

0

3.0V

-40

40

80

120

-40

0

40

Temperature (°C)

80

120

Temperature (°C)

FIGURE 2-54:

Resistor Network 0 to

FIGURE 2-56:

Resistor Network 0 to

Resistor Network 1 R (5 kΩ) Mismatch vs. V

and Temperature.

Resistor Network 1 R (50 kΩ) Mismatch vs.

AB

DD

AB

V

and Temperature.

DD

0.04

0.03

0.02

0.05

0.04

0.03

0.02

0.01

5.5V

0.01

0

-0.01

3.0V

0

3.0V

-0.02

-0.01

-0.02

-0.03

-0.04

-40

0

40

80

120

-40

10

60

110

Temperature (°C)

FIGURE 2-55:

Resistor Network 0 to

FIGURE 2-57:

Resistor Network 0 to

Resistor Network 1 R (10 kΩ) Mismatch vs.

Resistor Network 1 R (100 kΩ) Mismatch vs.

AB

V

and Temperature.

V

and Temperature.

DD

DS22060B-page 28

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

2.4

2.2

2

0

-5

5.5V

-10

-15

-20

-25

-30

-35

-40

-45

2.7V

1.8

1.6

1.4

1.2

1

5.5V

2.7V

-40

0

40

Temperature (°C)

80

120

-40

0

40

Temperature (°C)

80

120

FIGURE 2-58:

V

(SDI, SCK, CS, and

FIGURE 2-60:

I

(SDO) vs. V and

IH

OH

DD

SHDN) vs. V and Temperature.

Temperature.

DD

1.4

1.3

50

45

40

35

30

25

20

15

10

5

5.5V

1.2

1.1

1

0.9

2.7V

0.8

0.7

0.6

0

-40

0

40

Temperature (°C)

80

120

-40

0

40

Temperature (°C)

80

120

FIGURE 2-59:

V

(SDI, SCK, CS, and

FIGURE 2-61:

I

(SDO) vs. V and

IL

OL DD

SHDN) vs. V and Temperature.

Temperature.

DD

DS22060B-page 29

MCP413X/415X/423X/425X

Note: Unless otherwise indicated, T_A= +25°C,

V_DD= 5V, V_SS= 0V.

2.1

Test Circuits

1.2

+5V

1

5.5V

A

B

V_IN

0.8

0.6

0.4

0.2

0

W

V_OUT

+

-

2.7V

Offset

GND

2.5V DC

-40

0

40

80

120

Temperature (°C)

FIGURE 2-64:

Test.

-3 db Gain vs. Frequency

FIGURE 2-62:

and Temperature.

POR/BOR Trip point vs. V

DD

15.0

14.5

14.0

13.5

13.0

12.5

5.5V

2.7V

12.0

-40

0

40

80

120

Temperature (°C)

FIGURE 2-63:

SCK Input Frequency vs.

Voltage and Temperature.

DS22060B-page 30

MCP413X/415X/423X/425X

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follows.

TABLE 3-1:

PINOUT DESCRIPTION FOR THE MCP413X/415X/423X/425X

Weak

Single

Dual

Pot

Pull-up/

Standard Function

Buffer

Type

Rheo Pot ⁽¹⁾Rheo

Symbol

I/O

down ⁽²⁾

8L

10L

14L

16L

1

2

1

2

1

2

1

2

16

1

CS

I

HV w/ST “smart” SPI Chip Select Input

HV w/ST “smart” SPI Clock Input

SCK

3

—

3

2

SDI

HV w/ST “smart” SPI Serial Data Input

—

SDI/SDO

I/O HV w/ST “smart” SPI Serial Data Input/Output

(Note 1, Note 3)

4

—

5

4

5

4

5

3, 4 V_SS

—

A

P

—

No

Ground

—

5

6

P1B

P1W

P1A

Analog

Potentiometer 1 Terminal B

Potentiometer 1 Wiper Terminal

Potentiometer 1 Terminal A

Potentiometer 0 Terminal A

Potentiometer 0 Wiper Terminal

Potentiometer 0 Terminal B

—

6

A

—

7

A

—

8

P0A

A

5

6

9

P0W

P0B

A

6

7

8

10

12

13

14

11

—

10

13

14

15

A

—

8

—

9

SHDN

SDO

V_DD

I

HV w/ST “smart” Hardware Shutdown

7

O

—

O

P

No

—

SPI Serial Data Out

Positive Power Supply Input

No Connection

8

10

—

11

—

9

11,12 NC

17 EP

—

9

Exposed Pad (Note 4)

Legend:

HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)

A = Analog pins (Potentiometer terminals)

O = digital output

I = digital input (high Z)

I/O = Input / Output

P = Power

Note 1: The 8-lead Single Potentiometer devices are pin limited so the SDO pin is multiplexed with the SDI pin

(SDI/SDO pin). After the Address/Command (first 6-bits) are received, If a valid Read command has been

requested, the SDO pin starts driving the requested read data onto the SDI/SDO pin.

2: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and

shutdown current.

3: The SDO is an open drain output, which uses the internal “smart” pull-up. The SDI input data rate can be

at the maximum SPI frequency. the SDO output data rate will be limited by the “speed” of the pull-up,

customers can increase the rate with external pull-up resistors.

4: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively

connected to the die substrate, and therefore should be unconnected or connected to the same ground as

the device’s V_SSpin.

DS22060B-page 31

MCP413X/415X/423X/425X

3.1

Chip Select (CS)

3.7

Potentiometer Terminal A

The CS pin is the serial interface’s chip select input.

Forcing the CS pin to V_ILenables the serial commands.

Forcing the CS pin to V_IHHenables the high-voltage

serial commands.

The terminal A pin is available on the MCP4XX1

devices, and is connected to the internal

potentiometer’s terminal A.

The potentiometer’s terminal A is the fixed connection

to the Full-Scale wiper value of the digital

potentiometer. This corresponds to a wiper value of

0x100 for 8-bit devices or 0x80 for 7-bit devices.

3.2

Serial Data In (SDI)

The SDI pin is the serial interfaces Serial Data In pin.

This pin is connected to the Host Controllers SDO pin.

The terminal A pin does not have a polarity relative to

the terminal W or B pins. The terminal A pin can

support both positive and negative current. The voltage

3.3

Serial Data In / Serial Data Out

(SDI/SDO)

on terminal A must be between V_SSand V_DD

.

The terminal A pin is not available on the MCP4XX2

devices, and the internally terminal A signal is floating.

On the MCP41X1 devices, pin-out limitations do not

allow for individual SDI and SDO pins. On these

devices, the SDI and SDO pins are multiplexed.

MCP42X1 devices have two terminal A pins, one for

each resistor network.

The MCP41X1 serial interface knows when the pin

needs to change from being an input (SDI) to being an

output (SDO). The Host Controller’s SDO pin must be

properly protected from a drive conflict.

3.8

Shutdown (SHDN)

The SHDN pin is used to force the resistor network

terminals into the hardware shutdown state.

3.4

Ground (V_SS)

3.9

Serial Data Out (SDO)

The V_SSpin is the device ground reference.

The SDO pin is the serial interfaces Serial Data Out pin.

This pin is connected to the Host Controllers SDI pin.

3.5

Potentiometer Terminal B

This pin allows the Host Controller to read the digital

potentiometers registers, or monitor the state of the

command error bit.

The terminal B pin is connected to the internal

potentiometer’s terminal B.

The potentiometer’s terminal B is the fixed connection

to the Zero Scale wiper value of the digital

potentiometer. This corresponds to a wiper value of

0x00 for both 7-bit and 8-bit devices.

3.10 Positive Power Supply Input (V_DD

)

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SS

.

The terminal B pin does not have a polarity relative to

the terminal W or A pins. The terminal B pin can

support both positive and negative current. The voltage

While the device V_DD< V_min(2.7V), the electrical

performance of the device may not meet the data sheet

specifications.

on terminal B must be between V_SSand V_DD

.

MCP42XX devices have two terminal B pins, one for

each resistor network.

3.11 No Connection (NC)

These pins are not internally connected and should be

either connected to V_DDor V_SSto reduce possible

noise coupling.

3.6

Potentiometer Wiper (W) Terminal

The terminal W pin is connected to the internal

potentiometer’s terminal W (the wiper). The wiper

terminal is the adjustable terminal of the digital

potentiometer. The terminal W pin does not have a

polarity relative to terminals A or B pins. The terminal

W pin can support both positive and negative current.

The voltage on terminal W must be between V_SSand

3.12 Exposed Pad (EP)

This pad is conductively connected to the device's

substrate. This pad should be tied to the same potential

as the V_SSpin (or left unconnected). This pad could be

used to assist as a heat sink for the device when

connected to a PCB heat sink.

V_DD

.

MCP42XX devices have two terminal W pins, one for

each resistor network.

DS22060B-page 32

MCP413X/415X/423X/425X

4.1.2

BROWN-OUT RESET

4.0

FUNCTIONAL OVERVIEW

When the device powers down, the device V_DDwill

cross the V_POR/V_BORvoltage.

This Data Sheet covers a family of thirty-two Digital

Potentiometer and Rheostat devices that will be

referred to as MCP4XXX. The MCP4XX1 devices are

the Potentiometer configuration, while the MCP4XX2

devices are the Rheostat configuration.

Once the V_DDvoltage decreases below the V_POR/V_BOR

voltage the following happens:

• Serial Interface is disabled

As the Device Block Diagram shows, there are four

main functional blocks. These are:

If the V_DDvoltage decreases below the V_RAMvoltage

the following happens:

• POR/BOR Operation

• Memory Map

• Volatile wiper registers may become corrupted

• TCON register may become corrupted

• Resistor Network

• Serial Interface (SPI)

As the voltage recovers above the V_POR/V_BORvoltage

see Section 4.1.1 “Power-on Reset”.

The POR/BOR operation and the Memory Map are

discussed in this section and the Resistor Network and

SPI operation are described in their own sections. The

Device Commands commands are discussed in

Section 7.0.

Serial commands not completed due to a brown-out

condition may cause the memory location to become

corrupted.

4.2

Memory Map

The device memory is 16 locations that are 9-bits wide

(16x9 bits). This memory space contains four volatile

locations (see Table 4-1).

4.1

POR/BOR Operation

The Power-on Reset is the case where the device is

having power applied to it from V_SS. The Brown-out

Reset occurs when a device had power applied to it,

and that power (voltage) drops below the specified

range.

TABLE 4-1:

Address

MEMORY MAP

Function

Memory Type

00h

01h

02h

03h

04h

05h

Volatile Wiper 0

Volatile Wiper 1

RAM

—

The devices RAM retention voltage (V_RAM) is lower

than the POR/BOR voltage trip point (V_POR/V_BOR). The

maximum V_POR/V_BORvoltage is less then 1.8V.

Reserved

—

When V_POR/V_BOR< V_DD< 2.7V, the electrical

performance may not meet the data sheet

specifications. In this region, the device is capable of

incrementing, decrementing, reading and writing to its

volatile memory if the proper serial command is

executed.

Volatile TCON Register

Status Register

RAM

—

06h-0Fh Reserved

4.2.1 VOLATILE MEMORY (RAM)

4.1.1

POWER-ON RESET

There are four Volatile Memory locations. These are:

• Volatile Wiper 0

When the device powers up, the device V_DDwill cross

the V_POR/V_BORvoltage. Once the V_DDvoltage crosses

the V_POR/V_BORvoltage the following happens:

• Volatile Wiper 1

(Dual Resistor Network devices only)

• Volatile wiper register is loaded with the default

wiper value

• Status Register

• Terminal Control (TCON) Register

• The TCON register is loaded it’s default value

• The device is capable of digital operation

The volatile memory starts functioning at the RAM

retention voltage (V_RAM).

DS22060B-page 33

MCP413X/415X/423X/425X

The STATUS register is placed at Address 05h.

4.2.1.1

Status (STATUS) Register

This register contains 5 status bits. These bits show the

state of the Shutdown bit. The STATUS register can be

accessed via the READ commands. Register 4-1

describes each STATUS register bit.

REGISTER 4-1:

STATUS REGISTER

R-1

R-1 R-1

R-0

R-x

D8:D5

RESV

SHDN

RESV

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 8-5

bit 4-2

D8:D5: Reserved. Forced to “1”

RESV: Reserved

bit 1

SHDN: Hardware Shutdown pin Status bit (Refer to Section 5.3 “Shutdown” for further information)

This bit indicates if the Hardware shutdown pin (SHDN) is low. A hardware shutdown disconnects the

Terminal A and forces the wiper (Terminal W) to Terminal B (see Figure 5-2). While the device is in Hard-

ware Shutdown (the SHDN pin is low) the serial interface is operational so the STATUS register may be

read.

1= MCP4XXX is in the Hardware Shutdown state

0= MCP4XXX is NOT in the Hardware Shutdown state

bit 0

RESV: Reserved

DS22060B-page 34

MCP413X/415X/423X/425X

4.2.1.2

Terminal Control (TCON) Register

This register contains 8 control bits. Four bits are for

Wiper 0, and four bits are for Wiper 1. Register 4-2

describes each bit of the TCON register.

The state of each resistor network terminal connection

is individually controlled. That is, each terminal

connection (A, B and W) can be individually connected/

disconnected from the resistor network. This allows the

system to minimize the currents through the digital

potentiometer.

The value that is written to this register will appear on

the resistor network terminals when the serial

command has completed.

On a POR/BOR this register is loaded with 1FFh

(9-bits), for all terminals connected. The Host

Controller needs to detect the POR/BOR event and

then update the Volatile TCON register value.

DS22060B-page 35

MCP413X/415X/423X/425X

(1, 2)

REGISTER 4-2:

TCON BITS

R-1

D8

R/W-1

R1HW

R/W-1

R1W

R/W-1

R1B

R/W-1

R0HW

R/W-1

R0A

R/W-1

R0W

R/W-1

R0B

R1A

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

bit 7

D8: Reserved. Forced to “1”

R1HW: Resistor 1 Hardware Configuration Control bit

This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin

1= Resistor 1 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 1 is forced to the hardware pin “shutdown” configuration

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network

1= P1A pin is connected to the Resistor 1 Network

0= P1A pin is disconnected from the Resistor 1 Network

R1W: Resistor 1 Wiper (P1W pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network

1= P1W pin is connected to the Resistor 1 Network

0= P1W pin is disconnected from the Resistor 1 Network

R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network

1= P1B pin is connected to the Resistor 1 Network

0= P1B pin is disconnected from the Resistor 1 Network

R0HW: Resistor 0 Hardware Configuration Control bit

This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin

1= Resistor 0 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 0 is forced to the hardware pin “shutdown” configuration

R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network

1= P0A pin is connected to the Resistor 0 Network

0= P0A pin is disconnected from the Resistor 0 Network

R0W: Resistor 0 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network

1= P0W pin is connected to the Resistor 0 Network

0= P0W pin is disconnected from the Resistor 0 Network

R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network

1= P0B pin is connected to the Resistor 0 Network

0= P0B pin is disconnected from the Resistor 0 Network

Note 1: The hardware SHDN pin (when active) overrides the state of these bits. When the SHDN pin returns to the

inactive state, the TCON register will control the state of the terminals. The SHDN pin does not modify the

state of the TCON bits.

2: These bits do not affect the wiper register values.

DS22060B-page 36

MCP413X/415X/423X/425X

5.1

Resistor Ladder Module

5.0

RESISTOR NETWORK

The resistor ladder is a series of equal value resistors

(R_S) with a connection point (tap) between the two

resistors. The total number of resistors in the series

(ladder) determines the R_ABresistance (see

Figure 5-1). The end points of the resistor ladder are

connected to analog switches which are connected to

the device Terminal A and Terminal B pins. The R_AB

(and R_S) resistance has small variations over voltage

and temperature.

The Resistor Network has either 7-bit or 8-bit

resolution. Each Resistor Network allows zero scale to

full-scale connections. Figure 5-1 shows a block

diagram for the resistive network of a device.

The Resistor Network is made up of several parts.

These include:

• Resistor Ladder

• Wiper

• Shutdown (Terminal Connections)

For an 8-bit device, there are 256 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 256 resistors thus providing

257 possible settings (including terminal A and

terminal B).

Devices have either one or two resistor networks,

These are referred to as Pot 0 and Pot 1.

A

For a 7-bit device, there are 128 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 128 resistors thus providing

129 possible settings (including terminal A and

terminal B).

8-Bit

N =

257

7-Bit

N =

128

(100h)

(80h)

(1)

R_W

R_S

Equation 5-1 shows the calculation for the step

resistance.

256

(FFh)

127

(7Fh)

(1)

R_W

EQUATION 5-1:

R CALCULATION

255

(FEh)

126

(7Eh)

S

R_AB

R_S= -------------

8-bit Device

(256)

W

R_AB

R_S= -------------

(128)

7-bit Device

1

(01h)

(1)

R_W

R_S

0

(00h)

Analog Mux

B

Note 1: The wiper resistance is dependent on

several factors including, wiper code,

device V_DD, Terminal voltages (on A, B,

and W), and temperature.

Also for the same conditions, each tap

selection resistance has a small variation.

This R_Wvariation has greater effects on

some specifications (such as INL) for the

smaller resistance devices (5.0 kΩ)

compared to larger resistance devices

(100.0 kΩ).

FIGURE 5-1:

Resistor Block Diagram.

DS22060B-page 37

MCP413X/415X/423X/425X

A POR/BOR event will load the Volatile Wiper register

value with the default value. Table 5-2 shows the

default values offered. Custom POR/BOR options are

available. Contact the local Microchip Sales Office.

5.2

Wiper

Each tap point (between the R_Sresistors) is a

connection point for an analog switch. The opposite

side of the analog switch is connected to a common

signal which is connected to the Terminal W (Wiper)

pin.

TABLE 5-2:

DEFAULT FACTORY

SETTINGS SELECTION

A value in the volatile wiper register selects which

analog switch to close, connecting the W terminal to

the selected node of the resistor ladder.

Wiper Code

The wiper can connect directly to Terminal B or to

Terminal A. A zero-scale connections, connects the

Terminal W (wiper) to Terminal B (wiper setting of

000h). A full-scale connections, connects the Terminal

W (wiper) to Terminal A (wiper setting of 100h or 80h).

In these configurations the only resistance between the

Terminal W and the other Terminal (A or B) is that of the

analog switches.

8-bit

7-bit

-502

-103

-503

-104

5.0 kΩ

Mid-scale

80h

40h

10.0 kΩ

50.0 kΩ

100.0 kΩ

A wiper setting value greater than full-scale (wiper

setting of 100h for 8-bit device or 80h for 7-bit devices)

will also be a Full-Scale setting (Terminal W (wiper)

connected to Terminal A). Table 5-1 illustrates the full

wiper setting map.

Equation 5-2 illustrates the calculation used to deter-

mine the resistance between the wiper and terminal B.

EQUATION 5-2:

R

CALCULATION

WB

R_AB

N

R_WB= ------------- + R_W

8-bit Device

(256)

N = 0 to 256 (decimal)

R_AB

N

7-bit Device

R_WB= ------------- + R_W

(128)

N = 0 to 128 (decimal)

TABLE 5-1:

VOLATILE WIPER VALUE VS.

WIPER POSITION MAP

Wiper Setting

7-bit Pot 8-bit Pot

Properties

3FFh

081h

3FFh

101h

Reserved (Full-Scale (W = A)),

Increment and Decrement

commands ignored

080h

100h

Full-Scale (W = A),

Increment commands ignored

07Fh

041h

0FFh

081

W = N

040h

080h

W = N (Mid-Scale)

W = N

03Fh

001h

07Fh

001

000h

Zero Scale (W = B)

Decrement command ignored

DS22060B-page 38

MCP413X/415X/423X/425X

5.3.2

TERMINAL CONTROL REGISTER

(TCON)

5.3

Shutdown

Shutdown is used to minimize the device’s current

consumption. The MCP4XXX has two methods to

achieve this. These are:

The Terminal Control (TCON) register is a volatile

register used to configure the connection of each

resistor network terminal pin (A, B, and W) to the

Resistor Network. This register is shown in

Register 4-2.

• Hardware Shutdown Pin (SHDN)

• Terminal Control Register (TCON)

The Hardware Shutdown pin is backwards compatible

with the MCP42XXX devices.

The RxHW bits forces the selected resistor network

into the same state as the SHDN pin. Alternate

low-power configurations may be achieved with the

RxA, RxW, and RxB bits.

5.3.1

HARDWARE SHUTDOWN PIN

(SHDN)

Note:

When the RxHW bit forces the resistor

network into the hardware SHDN state,

the state of the TCON register RxA, RxW,

and RxB bits is overridden (ignored).

When the state of the RxHW bit no longer

forces the resistor network into the hard-

ware SHDN state, the TCON register RxA,

RxW, and RxB bits return to controlling the

terminal connection state. In other words,

the RxHW bit does not corrupt the state of

the RxA, RxW, and RxB bits.

The SHDN pin is available on the dual potentiometer

devices. When the SHDN pin is forced active (V_IL):

• The P0A and P1A terminals are disconnected

• The P0W and P1W terminals are simultaneously

connect to the P0B and P1B terminals,

respectively (see Figure 5-2)

• The Serial Interface is NOT disabled, and all

Serial Interface activity is executed

The Hardware Shutdown pin mode does NOT corrupt

the values in the Volatile Wiper Registers nor the

TCON register. When the Shutdown mode is exited

(SHDN pin is inactive (V_IH)):

5.3.3

INTERACTION OF SHDN PIN AND

TCON REGISTER

• The device returns to the Wiper setting specified

by the Volatile Wiper value

• The TCON register bits return to controlling the

terminal connection state

Figure 5-3 shows how the SHDN pin signal and the

RxHW bit signal interact to control the hardware

shutdown of each resistor network (independently).

Using the TCON bits allows each resistor network (Pot

0 and Pot 1) to be individually “shutdown” while the

hardware pin forces both resistor networks to be “shut-

down” at the same time.

A

W

SHDN (from pin)

To Pot x Hardware

Shutdown Control

RxHW

B

(from TCON register)

FIGURE 5-2:

Resistor Network Configuration.

Hardware Shutdown

FIGURE 5-3:

Interaction.

RxHW bit and SHDN pin

DS22060B-page 39

MCP413X/415X/423X/425X

NOTES:

DS22060B-page 40

MCP413X/415X/423X/425X

Typical SPI Interfaces are shown in Figure 6-1. In the

SPI interface, The Master’s Output pin is connected to

the Slave’s Input pin and the Master’s Input pin is

connected to the Slave’s Output pin.

6.0

SERIAL INTERFACE (SPI)

The MCP4XXX devices support the SPI serial protocol.

This SPI operates in the slave mode (does not

generate the serial clock).

The MCP4XXX SPI’s module supports two (of the four)

standard SPI modes. These are Mode 0,0and 1,1.

The SPI mode is determined by the state of the SCK

pin (V_IHor V_IL) on the when the CS pin transitions from

inactive (V_IH) to active (V_ILor V_IHH).

The SPI interface uses up to four pins. These are:

• CS - Chip Select

• SCK - Serial Clock

• SDI - Serial Data In

• SDO - Serial Data Out

All SPI interface signals are high-voltage tolerant.

Typical SPI Interface Connections

Host

MCP4XXX

Controller

( Master Out - Slave In (MOSI) )

( Master In - Slave Out (MISO) )

SDI

SDO

SCK

CS

SDO

SDI

SCK

I/O ⁽¹⁾

Typical MCP41X1 SPI Interface Connections (Host Controller Hardware SPI)

Host

MCP41X1

Controller

SDI/SDO

SDO

SDI

(2)

R₁

SDI

SDO

SCK

CS

I/O ⁽¹⁾

Alternate MCP41X1 SPI Interface Connections (Host Controller Firmware SPI)

Host

MCP41X1

Controller

SDI/SDO

I/O

SDI

(SDO/SDI)

SDO

I/O

SCK

CS

(SCK)

I/O ⁽¹⁾

Note 1: If High voltage commands are desired, some type of external circuitry needs to be

implemented.

2: R₁must be sized to ensure V_ILand V_IHof the devices are met.

FIGURE 6-1:

Typical SPI Interface Block Diagram.

DS22060B-page 41

MCP413X/415X/423X/425X

6.1.3

Note:

SDI/SDO

6.1

SDI, SDO, SCK, and CS Operation

MCP41X1 Devices Only .

The operation of the four SPI interface pins are

discussed in this section. These pins are:

For device packages that do not have enough pins for

both an SDI and SDO pin, the SDI and SDO

functionality is multiplexed onto a single I/O pin called

SDI/SDO.

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock)

• CS (Chip Select)

The SDO will only be driven for the command error bit

(CMDERR) and during the data bits of a read command

(after the memory address and command has been

received).

The serial interface works on either 8-bit or 16-bit

boundaries depending on the selected command. The

Chip Select (CS) pin frames the SPI commands.

6.1.3.1

SDI/SDO Operation

6.1.1

SERIAL DATA IN (SDI)

Figure 6-2 shows a block diagram of the SDI/SDO pin.

The SDI signal has an internal “smart” pull-up. The

value of this pull-up determines the frequency that data

can be read from the device. An external pull-up can be

added to the SDI/SDO pin to improve the rise time and

therefore improve the frequency that data can be read.

The Serial Data In (SDI) signal is the data signal into

the device. The value on this pin is latched on the rising

edge of the SCK signal.

6.1.2

SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

Note:

To support the High voltage requirement of

the SDI function, the SDO function is an

open drain output.

Once the CS pin is forced to the active level (V_ILor

V_IHH), the SDO pin will be driven. The state of the SDO

pin is determined by the serial bit’s position in the

command, the command selected, and if there is a

command error state (CMDERR).

Data written on the SDI/SDO pin can be at the

maximum SPI frequency.

Note:

Care must be take to ensure that a Drive

conflict does not exist between the Host

Controllers SDO pin (or software SDI/SDO

pin) and the MCP41x1 SDI/SDO pin (see

Figure 6-1).

On the falling edge of the SCK pin during the C0 bit

(see Figure 7-1), the SDI/SDO pin will start outputting

the SDO value. The SDO signal overrides the control of

the smart pull-up, such that whenever the SDI/SDO pin

is outputting data, the smart pull-up is enabled.

The SDI/SDO pin will change from an input (SDI) to an

output (SDO) after the state machine has received the

Address and Command bits of the Command Byte. If

the command is a Read command, then the SDI/SDO

pin will remain an output for the remainder of the

command. For any other command, the SDI/SDO pin

returns to an input.

“smart” pull-up

SDI/SDO

SDI

Open

Drain

Control

Logic

SDO

FIGURE 6-2:

Serial I/O Mux Block

Diagram.

DS22060B-page 42

MCP413X/415X/423X/425X

6.1.4

SERIAL CLOCK (SCK)

6.1.5

THE CS SIGNAL

(SPI FREQUENCY OF OPERATION)

The Chip Select (CS) signal is used to select the device

and frame a command sequence. To start a command,

or sequence of commands, the CS signal must

transition from the inactive state (V_IH) to an active state

(V_ILor V_IHH).

The SPI interface is specified to operate up to 10 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

TABLE 6-1:

SCK FREQUENCY

Command

Write,

Note:

There is a required delay after the CS pin

goes active to the 1st edge of the SCK pin.

Memory Type Access

Read

Increment,

Decrement

If an error condition occurs for an SPI command, then

the Command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (V_IL). To exit the

error condition, the user must take the CS pin to the V_IH

level.

Volatile

Memory

SDI, SDO

10 MHz

SDI/SDO⁽¹⁾250 kHz ⁽²⁾

Note 1: MCP41X1 devices only.

2: This is the maximum clock frequency

When the CS pin returns to the inactive state (V_IH) the

SPI module resets (including the address pointer).

While the CS pin is in the inactive state (V_IH), the serial

interface is ignored. This allows the Host Controller to

interface to other SPI devices using the same SDI,

SDO, and SCK signals.

without an external pull-up resistor.

The CS pin has an internal pull-up resistor. The resistor

is disabled when the voltage on the CS pin is at the V_IL

level. This means that when the CS pin is not driven,

the internal pull-up resistor will pull this signal to the V_IH

level. When the CS pin is driven low (V_IL), the

resistance becomes very large to reduce the device

current consumption.

The high voltage capability of the CS pin allows

MCP413X/415X/423X/425X devices to be used in

systems previously designed for the MCP414X/416X/

424X/426X devices.

DS22060B-page 43

MCP413X/415X/423X/425X

6.2

The SPI Modes

6.3

SPI Waveforms

The SPI module supports two (of the four) standard SPI

modes. These are Mode 0,0 and 1,1. The mode is

determined by the state of the SDI pin on the rising

edge of the 1st clock bit (of the 8-bit byte).

Figure 6-3 through Figure 6-8 show the different SPI

command waveforms. Figure 6-3 and Figure 6-4 are

read and write commands. Figure 6-5 and Figure 6-6

are read commands when the SDI and SDO pins are

multiplexed on the same pin (SDI/SDO). Figure 6-7

and Figure 6-8 are increment and decrement

commands.

6.2.1

MODE 0,0

In Mode 0,0: SCK idle state = low (V_IL), data is clocked

in on the SDI pin on the rising edge of SCK and clocked

out on the SDO pin on the falling edge of SCK.

6.2.2

MODE 1,1

In Mode 1,1: SCK idle state = high (V_IH), data is

clocked in on the SDI pin on the rising edge of SCK and

clocked out on the SDO pin on the falling edge of SCK.

(1)

V_IHH

V_IL

V_IH

CS

SCK

Write to

SSPBUF

CMDERR bit

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5

SDO

SDI

bit4 bit3 bit2 bit1

bit0

AD3 AD2 AD1 AD0

bit15 bit14 bit13 bit12

X

D8

D7

D6

D5

D4

D3

D2

D1

D0

bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

C1

C0

Input

Sample

Note 1: V_IHHis supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage

operation.

FIGURE 6-3:

16-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).

(1)

V_IH

V_IHH

V_IL

CS

SCK

Write to

SSPBUF

CMDERR bit

bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5

SDO

SDI

bit4 bit3 bit2 bit1

bit0

AD3 AD2 AD1 AD0

bit15 bit14 bit13 bit12

X

D8

D7

D6

D5

D4

D3

D2

D1

D0

bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

C1

C0

Input

Sample

Note 1: V_IHHis supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage

operation.

FIGURE 6-4:

16-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).

DS22060B-page 44

MCP413X/415X/423X/425X

(1)

V_IHH

V_IL

V_IH

CS

SCK

Write to

SSPBUF

CMDERR bit

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SDO

SDI

bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

AD3 AD2 AD1 AD0

bit15 bit14 bit13 bit12

C1

1

C0

1

(1)

Input

Sample

Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven.

2: V_IHHis supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage

operation.

FIGURE 6-5:

16-Bit Read Command for Devices with SDI/SDO multiplexed -

SPI Waveform (Mode 1,1).

(1)

V_IHH

V_IL

V_IH

CS

SCK

Write to

SSPBUF

CMDERR bit

D8

D7

D6

D5

D4

D3

D2

D1

D0

X

SDO

SDI

bit9

bit8 bit7 bit6 bit5

bit4 bit3 bit2 bit1

bit0

AD3 AD2 AD1 AD0

bit15 bit14 bit13 bit12

C1

1

C0

1

(1)

Input

Sample

Note 1: The SDI pin will read the state of the SDI pin which will be the SDO signal, unless overdriven.

2: V_IHHis supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage

operation.

FIGURE 6-6:

16-Bit Read Command for Devices with SDI/SDO multiplexed -

SPI Waveform (Mode 0,0).

DS22060B-page 45

MCP413X/415X/423X/425X

(1)

V_IHH

V_IL

V_IH

CS

SCK

Write to

SSPBUF

CMDERR bit

“1” = “Valid” Command/Address

“0” = “Invalid” Command/Address

SDO

SDI

bit6

bit2

bit5

bit4

bit1

bit0

bit7

bit3

AD1

AD2

X

AD0

C0

AD3

bit7

C1

X

bit0

Input

Sample

Note 1: V_IHHis supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage

operation.

FIGURE 6-7:

(Mode 1,1).

8-Bit Commands (Increment, Decrement, Modify - SPI Waveform with PIC MCU

(1)

V_IHH

V_IH

CS

V_IL

SCK

Write to

SSPBUF

CMDERR bit

“1” = “Valid” Command/Address

“0” = “Invalid” Command/Address

bit6

AD2

bit2

C0

bit5

bit4

AD0

bit1

bit0

SDO

SDI

bit7

bit3

C1

AD1

X

AD3

bit7

X

bit0

Input

Sample

Note 1: V_IHHis supported for compability with the MCP414X/6X and MCP424X/6X devices high voltage

operation.

FIGURE 6-8:

8-Bit Commands (Increment, Decrement, Modify - SPI Waveform with PIC MCU

(Mode 0,0).

DS22060B-page 46

MCP413X/415X/423X/425X

7.1

Command Byte

7.0

DEVICE COMMANDS

The Command Byte has three fields, the Address, the

Command, and 2 Data bits, see Figure 7-1. Currently

only one of the data bits is defined (D8). This is for the

Write command.

The MCP4XXX’s SPI command format supports 16

memory address locations and four commands. Each

command has two modes. These are:

• Normal Serial Commands

The device memory is accessed when the master

sends a proper Command Byte to select the desired

operation. The memory location getting accessed is

contained in the Command Byte’s AD3:AD0 bits. The

action desired is contained in the Command Byte’s

C1:C0 bits, see Table 7-1. C1:C0 determines if the

desired memory location will be read, written,

Incremented (wiper setting +1) or Decremented (wiper

setting -1). The Increment and Decrement commands

are only valid on the volatile wiper registers.

• High-Voltage Serial Commands

Normal serial commands are those where the CS pin is

driven to V_IL. High Voltage Serial Commands, CS pin is

driven to V_IHH, for compatibility with systems that also

support the MCP414X/416X/424X/426X devices. High

Voltage Serial Commands operate identically to their

corresponding Normal Serial Command. In each

mode, there are four possible commands. These

commands are shown in Table 7-1.

The 8-bit commands (Increment Wiper and Decre-

ment Wiper commands) contain a Command Byte,

see Figure 7-1, while 16-bit commands (Read Data

and Write Data commands) contain a Command Byte

and a Data Byte. The Command Byte contains two data

bits, see Figure 7-1.

As the Command Byte is being loaded into the device

(on the SDI pin), the device’s SDO pin is driving. The

SDO pin will output high bits for the first six bits of that

command. On the 7th bit, the SDO pin will output the

CMDERR bit state (see Section 7.3 “Error Condi-

tion”). The 8th bit state depends on the the command

selected.

Table 7-2 shows the supported commands for each

memory location and the corresponding values on the

SDI and SDO pins.

TABLE 7-1:

COMMAND BIT OVERVIEW

Table 7-3 shows an overview of all the SPI commands

and their interaction with other device features.

C1:C0 Bit

States

Command

# of Bits

Read Data

Write Data

Increment

Decrement

16-Bits

8-Bits

11

00

01

10

8-Bits

16-bit Command

Data Byte

8-bit Command

Command Byte

A A A A C C D D D D D D D D D D

D D D D 1 0 9 8 7 6 5 4 3 2 1 0

3 2 1 0

A A A A C C D D

D D D D 1 0 9 8

3 2 1 0

Command

Bits

C C

1 0

Data

Bits

0 0 = Write Data

0 1 = INCR

1 0 = DECR

Data

Bits

Command

Bits

Memory

Address

Memory

Address

Command

Bits

1 1 = Read Data

FIGURE 7-1:

General SPI Command Formats.

DS22060B-page 47

MCP413X/415X/423X/425X

TABLE 7-2:

MEMORY MAP AND THE SUPPORTED COMMANDS

Address

SPI String (Binary)

MOSI (SDI pin)

MISO (SDO pin) ⁽²⁾

Data

Command

(10-bits) ⁽¹⁾

Value

Function

00h

Volatile Wiper 0

Volatile Wiper 1

Write Data

Read Data

Increment Wiper

Decrement Wiper

Write Data

Read Data

Increment Wiper

Decrement Wiper

—

nn nnnn nnnn

0000 00nn nnnn nnnn

0000 11nn nnnn nnnn

0000 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

nn nnnn nnnn

—

0000 1000

1111 1111

01h

nn nnnn nnnn

0001 00nn nnnn nnnn

0001 11nn nnnn nnnn

0001 0100

1111 1111 1111 1111

1111 111n nnnn nnnn

1111 1111

nn nnnn nnnn

—

0001 1000

1111 1111

02h

03h

04h

Reserved

—

Volatile

Write Data

Read Data

—

nn nnnn nnnn

—

0100 00nn nnnn nnnn

0100 11nn nnnn nnnn

0101 11nn nnnn nnnn

—

1111 1111 1111 1111

1111 111n nnnn nnnn

—

TCON Register

05h

Status Register

06h-0Fh Reserved

Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device.

2: All these Address/Command combinations are valid, so the CMDERR bit is set. Any other Address/Command

combination is a command error state and the CMDERR bit will be clear.

DS22060B-page 48

MCP413X/415X/423X/425X

7.3.1

ABORTING A TRANSMISSION

7.2

Data Byte

All SPI transmissions must have the correct number of

SCK pulses to be executed. The command is not

executed until the complete number of clocks have

been received. If the CS pin is forced to the inactive

state (V_IH) the serial interface is reset. Partial com-

mands are not executed.

Only the Read Command and the Write Command use

the Data Byte, see Figure 7-1. These commands

concatenate the 8-bits of the Data Byte with the one

data bit (D8) contained in the Command Byte to form

9-bits of data (D8:D0). The Command Byte format

supports up to 9-bits of data so that the 8-bit resistor

network can be set to Full-Scale (100h or greater). This

allows wiper connections to Terminal A and to

Terminal B.

SPI is more susceptible to noise than other bus

protocols. The most likely case is that this noise

corrupts the value of the data being clocked into the

MCP4XXX or the SCK pin is injected with extra clock

pulses. This may cause data to be corrupted in the

device, or a command error to occur, since the address

and command bits were not a valid combination. The

extra SCK pulse will also cause the SPI data (SDI) and

clock (SCK) to be out of sync. Forcing the CS pin to the

inactive state (V_IH) resets the serial interface. The SPI

interface will ignore activity on the SDI and SCK pins

until the CS pin transition to the active state is detected

(V_IHto V_ILor V_IHto V_IHH).

The D9 bit is currently unused, and corresponds to the

position on the SDO data of the CMDERR bit.

7.3

Error Condition

The CMDERR bit indicates if the four address bits

received (AD3:AD0) and the two command bits

received (C1:C0) are

a valid combination (see

Table 4-1). The CMDERR bit is high if the combination

is valid and low if the combination is invalid.

SPI commands that do not have a multiple of 8 clocks

are ignored.

Note 1: When data is not being received by the

MCP4XXX, It is recommended that the

CS pin be forced to the inactive level (V_IL)

Once an error condition has occurred, any following

commands are ignored. All following SDO bits will be

low until the CMDERR condition is cleared by forcing

the CS pin to the inactive state (V_IH).

2: It is also recommended that long

continuous command strings should be

broken down into single commands or

shorter continuous command strings.

This reduces the probability of noise on

the SCK pin corrupting the desired SPI

commands.

DS22060B-page 49

MCP413X/415X/423X/425X

7.4

Continuous Commands

Note 1: It is recommended that while the CS pin is

active, only one type of command should

be issued. When changing commands, it

is recommended to take the CS pin

inactive then force it back to the active

state.

The device supports the ability to execute commands

continuously. While the CS pin is in the active state

(V_ILor V_IHH). Any sequence of valid commands may be

received.

The following example is a valid sequence of events:

2: It is also recommended that long

command strings should be broken down

into shorter command strings. This

reduces the probability of noise on the

SCK pin corrupting the desired SPI

command string.

1. CS pin driven active (V_ILor V_IHH).

2. Read Command.

3. Increment Command (Wiper 0).

4. Increment Command (Wiper 0).

5. Decrement Command (Wiper 1).

6. Write Command.

7. Write Command.

8. CS pin driven inactive (V_IH).

TABLE 7-3:

COMMANDS

Command Name

High Voltage

# of Bits

(V_IHH) on CS

pin?

Write Data

16-Bits

8-Bits

—

Read Data

Increment Wiper

—

Decrement Wiper

8-Bits

—

High Voltage Write Data

High Voltage Read Data

High Voltage Increment Wiper

16-Bits

8-Bits

Yes

High Voltage Decrement Wiper

8-Bits

DS22060B-page 50

MCP413X/415X/423X/425X

7.5.1

SINGLE WRITE

7.5

Write Data

Normal and High Voltage

The write operation requires that the CS pin be in the

active state (V_ILor V_IHH). Typically, the CS pin will be in

the inactive state (V_IH) and is driven to the active state

(V_IL). The 16-bit Write Command (Command Byte and

Data Byte) is then clocked in on the SCK and SDI pins.

Once all 16 bits have been received, the specified

volatile address is updated. A write will not occur if the

write command isn’t exactly 16 clocks pulses. This

protects against system issues from corrupting the

memory locations.

Note:

The High Voltage Write Data command is

supported for compatability with system

that also support MCP414X/416X/424X/

426X devices.

The Write command is a 16-bit command. The format

of the command is shown in Figure 7-2.

A Write command to a Volatile memory location

changes that location after a properly formatted Write

Command (16-clock) have been received.

Figure 6-3 and Figure 6-4 show possible waveforms

for a single write.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDI

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid Address/Command combination

Invalid Address/Command combination ⁽¹⁾

SDO

Note 1: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

FIGURE 7-2:

Write Command - SDI and SDO States.

DS22060B-page 51

MCP413X/415X/423X/425X

7.5.2

CONTINUOUS WRITES

Continuous writes are possible only when writing to the

volatile memory registers (address 00h, 01h, and 04h).

Figure 7-3 shows the sequence for three continuous

writes. The writes do not need to be to the same volatile

memory address.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDI

1

0

1

0

1*

1

SDO

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

1

0

1

0

1*

1

A

D

3

A

D

2

A

D

1

A

D

0

D

9

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

1

1*

1

Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be

driven low until the CS pin is driven inactive (V_IH).

FIGURE 7-3:

Continuous Write Sequence.

DS22060B-page 52

MCP413X/415X/423X/425X

7.6.1

SINGLE READ

7.6

Read Data

Normal and High Voltage

The read operation requires that the CS pin be in the

active state (V_ILor V_IHH). Typically, the CS pin will be in

the inactive state (V_IH) and is driven to the active state

(V_ILor V_IHH). The 16-bit Read Command (Command

Byte and Data Byte) is then clocked in on the SCK and

SDI pins. The SDO pin starts driving data on the 7th bit

(CMDERR bit) and the addressed data comes out on

the 8th through 16th clocks. Figure 6-3 through

Figure 6-6 show possible waveforms for a single read.

Note:

The High Voltage Read Data command is

supported for compatability with system

that also support MCP414X/416X/424X/

426X devices.

The Read command is a 16-bit command. The format

of the command is shown in Figure 7-4.

The first 6-bits of the Read command determine the

address and the command. The 7th clock will output

the CMDERR bit on the SDO pin. The remaining

9-clocks the device will transmit the 9 data bits (D8:D0)

of the specified address (AD3:AD0).

Figure 6-5 and Figure 6-6 show the single read

waveforms when the SDI and SDO signals are

multiplexed on the same pin. For additional information

on the multiplexing of these signals, refer to

Section 6.1.3 “SDI/SDO”.

Figure 7-4 shows the SDI and SDO information for a

Read command.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

0

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D Valid Address/Command combination

0

SDO

1

0

Attempted Memory Read of Reserved

Memory location.

READ DATA

Read Command - SDI and SDO States.

FIGURE 7-4:

DS22060B-page 53

MCP413X/415X/423X/425X

Figure 7-5 shows the sequence for three continuous

reads. The reads do not need to be to the same

memory address.

7.6.2

CONTINUOUS READS

Continuous reads allows the devices memory to be

read quickly. Continuous reads are possible to all

memory locations.

COMMAND BYTE

DATA BYTE

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

1*

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

SDO

A

D

3

A

D

2

A

D

1

A

D

0

1

X

1

1*

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

A

D

3

A

D

2

A

D

1

A

D

0

1

X

1

1*

D

8

D

7

D

6

D

5

D

4

D

3

D

2

D

1

D

0

Note 1: If a Command Error (CMDERR) occurs at this bit location (*), then all following SDO bits will be

driven low until the CS pin is driven inactive (V_IH).

FIGURE 7-5:

Continuous Read Sequence.

DS22060B-page 54

MCP413X/415X/423X/425X

7.7.1

SINGLE INCREMENT

7.7

Increment Wiper

Normal and High Voltage

Typically, the CS pin starts at the inactive state (V_IH),

but may be already be in the active state due to the

completion of another command.

Note:

The High Voltage Increment Wiper

command is supported for compatability

with system that also support MCP414X/

416X/424X/426X devices.

Figure 6-7 through Figure 6-8 show possible

waveforms for a single increment. The increment

operation requires that the CS pin be in the active state

(V_ILor V_IHH). Typically, the CS pin will be in the inactive

state (V_IH) and is driven to the active state (V_ILor V_IHH).

The 8-bit Increment Command (Command Byte) is

then clocked in on the SDI pin by the SCK pins. The

SDO pin drives the CMDERR bit on the 7th clock.

The Increment Command is an 8-bit command. The

Increment Command can only be issued to wiper

memory locations. The format of the command is

shown in Figure 7-6.

An Increment Command to the wiper memory location

changes that location after a properly formatted

command (8-clocks) have been received.

The wiper value will increment up to 100h on 8-bit

devices and 80h on 7-bit devices. After the wiper value

has reached Full-Scale (8-bit =100h, 7-bit =80h), the

wiper value will not be incremented further. If the Wiper

register has a value between 101h and 1FFh, the

Increment command is disabled. See Table 7-4 for

additional information on the Increment Command

versus the current volatile wiper value.

Increment commands provide a quick and easy

method to modify the value of the wiper location by +1

with minimal overhead.

COMMAND BYTE

(INCR COMMAND (n+1) )

The Increment operations only require the Increment

command byte while the CS pin is active (V_ILor V_IHH

for a single increment.

)

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

After the wiper is incremented to the desired position,

the CS pin should be forced to V_IHto ensure that

unexpected transitions on the SCK pin do not cause

the wiper setting to change. Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired increment occurs.

1

1*

0

1

0

Note 1, 2

Note 1, 3

SDO

Note 1: Only functions when writing the volatile

wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

TABLE 7-4:

INCREMENT OPERATION VS.

VOLATILE WIPER VALUE

3: Invalid Address/Command combination

all following SDO bits will be low until the

CMDERR condition is cleared.

(the CS pin is forced to the inactive

state).

Current Wiper

Setting

Increment

Wiper (W)

Command

Operates?

Properties

7-bit

Pot

8-bit

Pot

4: If a Command Error (CMDERR) occurs

at this bit location (*), then all following

SDO bits will be driven low until the CS

pin is driven inactive (V_IH).

3FFh

081h

3FFh Reserved

101h (Full-Scale (W = A))

No

080h

100h Full-Scale (W = A)

07Fh

041h

0FFh W = N

081

FIGURE 7-6:

SDI and SDO States.

Increment Command -

040h

080h W = N (Mid-Scale)

Yes

03Fh

001h

07Fh W = N

001

000h

000h Zero Scale (W = B)

DS22060B-page 55

MCP413X/415X/423X/425X

Increment commands can be sent repeatedly without

raising CS until a desired condition is met. The value in

the Volatile Wiper register can be read using a Read

Command.

7.7.2

CONTINUOUS INCREMENTS

Continuous Increments are possible only when writing

to the wiper registers.

Figure 7-7 shows a Continuous Increment sequence

for three continuous writes. The writes do not need to

be to the same volatile memory address.

When executing a continuous command string, The

Increment command can be followed by any other valid

command.

When executing an continuous Increment commands,

the selected wiper will be altered from n to n+1 for each

Increment command received. The wiper value will

increment up to 100h on 8-bit devices and 80h on 7-bit

devices. After the wiper value has reached Full-Scale

(8-bit =100h, 7-bit =80h), the wiper value will not be

incremented further. If the Wiper register has a value

between 101h and 1FFh, the Increment command is

disabled.

The wiper terminal will move after the command has

been received (8th clock).

After the wiper is incremented to the desired position,

the CS pin should be forced to V_IHto ensure that

unexpected transitions (on the SCK pin do not cause

the wiper setting to change). Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired increment occurs.

COMMAND BYTE

(INCR COMMAND (n+2) )

COMMAND BYTE

(INCR COMMAND (n+1) )

(INCR COMMAND (n+3) )

A

D

3

A

D

2

A

D

1

A

D

0

1

X

A

D

3

A

D

2

A

D

1

A

D

0

1

X

A

D

3

A

D

2

A

D

1

A

D

0

1

X

SDI

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

Note 1, 2

Note 3, 4

SDO

1

0

1

0

Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

3: Invalid Address/Command combination.

4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

FIGURE 7-7:

Continuous Increment Command - SDI and SDO States.

DS22060B-page 56

MCP413X/415X/423X/425X

7.8.1

SINGLE DECREMENT

7.8

Decrement Wiper

Normal and High Voltage

Typically the CS pin starts at the inactive state (V_IH), but

may be already be in the active state due to the

completion of another command.

Note:

The High Voltage Decrement Wiper

command is supported for compatability

with system that also support MCP414X/

416X/424X/426X devices.

Figure 6-7 through Figure 6-8 show possible

waveforms for a single Decrement. The decrement

operation requires that the CS pin be in the active state

(V_ILor V_IHH). Typically the CS pin will be in the inactive

state (V_IH) and is driven to the active state (V_ILor V_IHH).

Then the 8-bit Decrement Command (Command Byte)

is clocked in on the SDI pin by the SCK pins. The SDO

pin drives the CMDERR bit on the 7th clock.

The Decrement Command is an 8-bit command. The

Decrement Command can only be issued to wiper

memory locations. The format of the command is

shown in Figure 7-6.

An Decrement Command to the wiper memory location

changes that location after a properly formatted

command (8-clocks) have been received.

The wiper value will decrement from the wipers

Full-Scale value (100h on 8-bit devices and 80h on

7-bit devices). Above the wipers Full-Scale value

(8-bit =101h to 1FFh, 7-bit = 81h to FFh), the

decrement command is disabled. If the Wiper register

has a Zero Scale value (000h), then the wiper value will

not decrement. See Table 7-4 for additional information

on the Decrement Command vs. the current volatile

wiper value.

Decrement commands provide a quick and easy

method to modify the value of the wiper location by -1

with minimal overhead.

COMMAND BYTE

(DECR COMMAND (n+1))

The Decrement commands only require the Decrement

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

command byte, while the CS pin is active (V_ILor V_IHH

)

SDI

for a single decrement.

After the wiper is decremented to the desired position,

the CS pin should be forced to V_IHto ensure that

unexpected transitions on the SCK pin do not cause

the wiper setting to change. Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired decrement occurs.

1

1*

0

1

0

Note 1, 2

Note 1, 3

SDO

Note 1: Only functions when writing the volatile

wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

TABLE 7-5:

DECREMENT OPERATION VS.

VOLATILE WIPER VALUE

3: Invalid Address/Command combination

all following SDO bits will be low until the

CMDERR condition is cleared.

(the CS pin is forced to the inactive

state).

Current Wiper

Setting

Decrement

Wiper (W)

Command

Operates?

Properties

7-bit

Pot

8-bit

Pot

4: If a Command Error (CMDERR) occurs

at this bit location (*), then all following

SDO bits will be driven low until the CS

pin is driven inactive (V_IH).

3FFh

081h

3FFh Reserved

101h (Full-Scale (W = A))

No

080h

100h Full-Scale (W = A)

Yes

FIGURE 7-8:

SDI and SDO States.

Decrement Command -

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid-Scale)

Yes

No

03Fh

001h

07Fh W = N

001

000h

000h Zero Scale (W = B)

DS22060B-page 57

MCP413X/415X/423X/425X

Decrement commands can be sent repeatedly without

raising CS until a desired condition is met. The value in

the Volatile Wiper register can be read using a Read

Command.

7.8.2

CONTINUOUS DECREMENTS

Continuous Decrements are possible only when writing

to the wiper registers.

Figure 7-9 shows a continuous Decrement sequence

for three continuous writes. The writes do not need to

be to the same volatile memory address.

When executing a continuous command string, The

Decrement command can be followed by any other

valid command.

When executing an continuous Decrement commands,

the selected wiper will be altered from n to n-1 for each

Decrement command received. The wiper value will

decrement from the wipers Full-Scale value (100h on

8-bit devices and 80h on 7-bit devices). Above the

wipers Full-Scale value (8-bit =101h to 1FFh,

7-bit = 81h to FFh), the decrement command is

disabled. If the Wiper register has a Zero Scale value

(000h), then the wiper value will not decrement. See

Table 7-4 for additional information on the Decrement

Command vs. the current volatile wiper value.

The wiper terminal will move after the command has

been received (8th clock).

After the wiper is decremented to the desired position,

the CS pin should be forced to V_IHto ensure that

“unexpected” transitions (on the SCK pin do not cause

the wiper setting to change). Driving the CS pin to V_IH

should occur as soon as possible (within device

specifications) after the last desired decrement occurs.

COMMAND BYTE

(DECR COMMAND (n-1) )

COMMAND BYTE

(DECR COMMAND (n-1) )

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

A

D

3

A

D

2

A

D

1

A

D

0

1

0

X

SDI

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1*

0

1

0

Note 1, 2

Note 3, 4

SDO

1

0

1

0

Note 1: Only functions when writing the volatile wiper registers (AD3:AD0) 0h and 1h.

2: Valid Address/Command combination.

3: Invalid Address/Command combination.

4: If an Error Condition occurs (CMDERR = L), all following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the inactive state).

FIGURE 7-9:

Continuous Decrement Command - SDI and SDO States.

DS22060B-page 58

MCP413X/415X/423X/425X

8.0

APPLICATIONS EXAMPLES

5V

3V

Voltage

Digital potentiometers have a multitude of practical

uses in modern electronic circuits. The most popular

uses include precision calibration of set point thresh-

olds, sensor trimming, LCD bias trimming, audio atten-

uation, adjustable power supplies, motor control

overcurrent trip setting, adjustable gain amplifiers and

offset trimming. The MCP413X/415X/423X/425X

devices can be used to replace the common mechani-

cal trim pot in applications where the operating and

terminal voltages are within CMOS process limitations

(V_DD= 2.7V to 5.5V).

Regulator

MCP4XXX

PIC MCU

SDI

CS

SCK

SDI

CS

SCK

SHDN

SDO

SHDN

SDO

FIGURE 8-1:

System 1.

Example Split Rail

8.1

Split Rail Applications

All inputs that would be used to interface to a Host

Controller support High Voltage on their input pin. This

allows the MCP4XXX device to be used in split power

rail applications.

5V

Voltage

Regulator

3V

An example of this is a battery application where the

PIC^®MCU is directly powered by the battery supply

(4.8V) and the MCP4XXX device is powered by the

3.3V regulated voltage.

MCP4XXX

PIC MCU

SDI

CS

SCK

SDI

CS

SCK

For SPI applications, these inputs are:

• CS

SHDN

SDO

SHDN

SDO

• SCK

• SDI (or SDI/SDO)

• SHDN

FIGURE 8-2:

Example Split Rail

Figure 8-1 through Figure 8-2 show three example split

rail systems. In this system, the MCP4XXX interface

input signals need to be able to support the PIC MCU

output high voltage (V_OH).

System 2.

TABLE 8-1:

PIC ⁽¹⁾

V

- V COMPARISONS

OH

IH

MCP4XXX ⁽²⁾

In Example #1 (Figure 8-1), the MCP4XXX interface

input signals need to be able to support the PIC MCU

output high voltage (V_OH). If the split rail voltage delta

becomes too large, then the customer may be required

to do some level shifting due to MCP4XXX V_OHlevels

related to Host Controller V_IHlevels.

Comment

V_DDV_IHV_OHV_DDV_IH

V_OH

5.5

5.0

4.5

3.3

3.0

2.7

4.4

4.0

3.6

4.4

4.0

3.6

2.7 1.215 — ⁽³⁾

(3)

3.0 1.35

—

3.3 1.485 — ⁽³⁾

2.64 2.64 4.5 2.025 — ⁽³⁾

In Example #2 (Figure 8-2), the MCP4XXX interface

input signals need to be able to support the lower

voltage of the PIC MCU output high voltage level (V_OH).

(3)

2.4

5.0 2.25

—

2.16 2.16 5.5 2.475 — ⁽³⁾

Note 1: V_OHminimum = 0.8 * V_DD

;

Table 8-1 shows an example PIC microcontroller I/O

V_OLmaximum = 0.6V

voltage

specifications

and

the

MCP4XXX

V_IHminimum = 0.8 * V_DD

V_ILmaximum = 0.2 * V_DD

;

specifications. So this PIC MCU operating at 3.3V will

drive a V_OHat 2.64V, and for the MCP4XXX operating

at 5.5V, the V_IHis 2.47V. Therefore, the interface

signals meet specifications.

2: V_OHminimum (SDA only) =;

V_OLmaximum = 0.2 * V_DD

V_IHminimum = 0.45 * V_DD

V_ILmaximum = 0.2 * V_DD

;

3: The only MCP4XXX output pin is SDO,

which is Open-Drain (or Open-Drain with

Internal Pull-up) with High Voltage Support

DS22060B-page 59

MCP413X/415X/423X/425X

8.2

Techniques to force the CS pin to

V_IHH

PIC10F206

R₁

GP0

The circuit in Figure 8-3 shows a method using the

TC1240A doubling charge pump. When the SHDN pin

is high, the TC1240A is off, and the level on the CS pin

is controlled by the PIC® microcontrollers (MCUs) IO2

pin.

MCP4XXX

GP2

CS

C₁

When the SHDN pin is low, the TC1240A is on and the

V_OUTvoltage is 2 * V_DD. The resistor R₁allows the CS

pin to go higher than the voltage such that the PIC

MCU’s IO2 pin “clamps” at approximately VDD.

C₂

FIGURE 8-4:

MCP4XXX Non-Volatile

Digital Potentiometer Evaluation Board

(MCP402XEV) implementation to generate the

TC1240A

V_IN

V

voltage.

IHH

C+

PIC MCU

C₁

C-

SHDN

8.3

Using Shutdown Modes

V_OUT

IO1

Figure 8-5 shows a possible application circuit where

the independent terminals could be used.

Disconnecting the wiper allows the transistor input to

be taken to the Bias voltage level (disconnecting A and

or B may be desired to reduce system current).

Disconnecting Terminal A modifies the transistor input

by the R_BWrheostat value to the Common B.

Disconnecting Terminal B modifies the transistor input

by the R_AWrheostat value to the Common A. The

Common A and Common B connections could be

MCP402X

R₁

CS

IO2

C₂

FIGURE 8-3:

generate the V

Using the TC1240A to

voltage.

IHH

connected to V_DDand V_SS

.

The circuit in Figure 8-4 shows the method used on the

MCP402X Non-volatile Digital Potentiometer Evalua-

tion Board (Part Number: MCP402XEV). This method

requires that the system voltage be approximately 5V.

This ensures that when the PIC10F206 enters a

brown-out condition, there is an insufficient voltage

level on the CS pin to change the stored value of the

Common A

Input

wiper.

The

MCP402X

Non-volatile

Digital

A

Potentiometer Evaluation Board User’s Guide

(DS51546) contains a complete schematic.

GP0 is a general purpose I/O pin, while GP2 can either

be a general purpose I/O pin or it can output the internal

clock.

To base

of Transistor

(or Amplifier)

W

For the serial commands, configure the GP2 pin as an

input (high-impedance). The output state of the GP0

pin will determine the voltage on the CS pin (V_ILor V_IH).

For high-voltage serial commands, force the GP0

output pin to output a high level (V_OH) and configure the

GP2 pin to output the internal clock. This will form a

charge pump and increase the voltage on the CS pin

(when the system voltage is approximately 5V).

B

Input

Common B

Balance

Bias

Example Application Circuit

FIGURE 8-5:

using Terminal Disconnects.

DS22060B-page 60

MCP413X/415X/423X/425X

8.4.2

LAYOUT CONSIDERATIONS

8.4

Design Considerations

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP4XXX’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

In the design of a system with the MCP4XXX devices,

the following considerations should be taken into

account:

• Power Supply Considerations

• Layout Considerations

boards utilizing

a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

is capable of providing. Particularly harsh

environments may require shielding of critical signals.

8.4.1

POWER SUPPLY

CONSIDERATIONS

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-6 illustrates an

appropriate bypass strategy.

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

8.4.3

RESISTOR TEMPCO

Characterization curves of the resistor temperature

coefficient (Tempco) are shown in Figure 2-11,

Figure 2-24, Figure 2-36, and Figure 2-48.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (V_DD) as

possible.

These curves show that the resistor network is

designed to correct for the change in resistance as

temperature increases. This technique reduces the

end to end change is R_ABresistance.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

V_SSshould reside on the analog plane.

8.4.4

HIGH VOLTAGE TOLERANT PINS

High Voltage support (V_IHH) on the Serial Interface pins

supports two features. These are:

V_DD

• In-Circuit Accommodation of split rail applications

and power supply sync issues

0.1 µF

• Compatability with systems that also support

MCP414X/416X /424X/426X devices

V_DD

0.1 µF

A

W

U/D

CS

B

V_SS

FIGURE 8-6:

Typical Microcontroller

Connections.

DS22060B-page 61

MCP413X/415X/423X/425X

NOTES:

DS22060B-page 62

MCP413X/415X/423X/425X

9.2

Technical Documentation

9.0

9.1

DEVELOPMENT SUPPORT

Development Tools

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-2 shows

some of these documents.

Several development tools are available to assist in

your design and evaluation of the MCP4XXX devices.

The currently available tools are shown in Table 9-1.

These boards may be purchased directly from the

Microchip web site at www.microchip.com.

TABLE 9-1:

Board Name

DEVELOPMENT TOOLS

Part #

Supported Devices

MCP42XX Digital Potentiometer PICtail Plus Demo MCP42XXDM-PTPLS MCP42XX

Board

MCP4XXX Digital Potentiometer Daughter Board ⁽¹⁾

8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board

14-pin SOIC/MSOP/DIP Evaluation Board

MCP4XXXDM-DB

MCP42XXX, MCP42XX,

MCP4021, and MCP4011

SOIC8EV

Any 8-pin device in DIP, SOIC,

MSOP, or TSSOP package

SOIC14EV

Any 14-pin device in DIP, SOIC, or

MSOP package

Note 1: Requires the use of a PICDEM Demo board (see User’s Guide for details)

TABLE 9-2:

TECHNICAL DOCUMENTATION

Title

Application

Literature #

Note Number

AN1080

AN737

AN692

AN691

AN219

—

Understanding Digital Potentiometers Resistor Variations

Using Digital Potentiometers to Design Low Pass Adjustable Filters

Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect

Optimizing the Digital Potentiometer in Precision Circuits

Comparing Digital Potentiometers to Mechanical Potentiometers

Digital Potentiometer Design Guide

DS01080

DS00737

DS00692

DS00691

DS00219

DS22017

DS21825

—

Signal Chain Design Guide

DS22060B-page 63

MCP413X/415X/423X/425X

NOTES:

DS22060B-page 64

MCP413X/415X/423X/425X

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

8-Lead DFN (3x3)

Example:

Part Number

Code

Part Number

Code

MCP4131-502E/MF

DAAE

DAAF

DAAH

DAAG

DAAP

DAAQ

DAAS

DAAR

MCP4132-502E/MF

MCP4132-103E/MF

MCP4132-104E/MF

MCP4132-503E/MF

MCP4152-502E/MF

MCP4152-103E/MF

MCP4152-104E/MF

MCP4152-503E/MF

DAAY

DAAZ

DABB

DABA

DAAA

DABD

DAAD

DAAC

XXXX

DAAE

0817

256

MCP4131-103E/MF

YYWW

NNN

MCP4131-104E/MF

MCP4131-503E/MF

MCP4151-502E/MF

MCP4151-103E/MF

MCP4151-104E/MF

MCP4151-503E/MF

8-Lead MSOP

Example

Part Number

Code

Part Number

Code

MCP4131-502E/MS 413152 MCP4132-502E/MS 413252

MCP4131-103E/MS 413113 MCP4132-103E/MS 413213

MCP4131-104E/MS 413114 MCP4132-104E/MS 413214

MCP4131-503E/MS 413153 MCP4132-503E/MS 413253

MCP4151-502E/MS 415152 MCP4152-502E/MS 415252

MCP4151-103E/MS 415113 MCP4152-103E/MS 415213

MCP4151-104E/MS 415114 MCP4152-104E/MS 415214

MCP4151-503E/MS 415153 MCP4152-503E/MS 415253

XXXXXX

YWWNNN

413152

817256

8-Lead PDIP

Example

4131-502

XXXXXXXX

XXXXXNNN

YYWW

E/P

e

3

256

0817

8-Lead SOIC

Example

4131502E

SN^ ^0817

XXXXXXXX

XXXXYYWW

e3

^

256

NNN

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e

3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22060B-page 65

MCP413X/415X/423X/425X

Package Marking Information (Continued)

10-Lead DFN (3x3)

Example:

Part Number

Code

Part Number

Code

XXXX

YYWW

NNN

BAEH

0817

256

MCP4232-502E/MF

MCP4232-103E/MF

MCP4232-104E/MF

MCP4232-503E/MF

BAEH

BAEJ

BAEL

BAEK

MCP4252-502E/MF

MCP4252-103E/MF

MCP4252-104E/MF

MCP4252-503E/MF

BAES

BAET

BAEV

BAEU

10-Lead MSOP

Example

Part Number

Code

Part Number

Code

XXXXXX

YWWNNN

423252

817256

MCP4232-502E/MS 423252 MCP4252-502E/MS 425252

MCP4232-103E/MS 423213 MCP4252-103E/MS 425213

MCP4232-104E/MS 423214 MCP4252-104E/MS 425214

MCP4232-503E/MS 423253 MCP4252-503E/MS 425253

14-Lead PDIP

Example

MCP4251

XXXXXXXXXXXXXX

YYWWNNN

e

3

502E/P^^

0817256

14-Lead SOIC (.150”)

Example

MCP4251

502E/SL^

XXXXXXXXXXX

YYWWNNN

e3

^

0817256

14-Lead TSSOP

Example

4251502E

XXXXXXXX

YYWW

0817

256

NNN

16-Lead QFN

Example

XXXXX

XXXXXX

YWWNNN

4251

502

E/ML^

0817256

e3

^

DS22060B-page 66

MCP413X/415X/423X/425X

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DS22060B-page 67

MCP413X/415X/423X/425X

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DS22060B-page 68

MCP413X/415X/423X/425X

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ&'ꢁꢂꢋ'ꢃꢆꢕꢇꢗꢆMꢆꢘꢚꢚꢆ ꢋꢈꢆ!ꢒꢅ"ꢆ#ꢇꢍ&ꢇ$

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DS22060B-page 69

MCP413X/415X/423X/425X

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DS22060B-page 70

MCP413X/415X/423X/425X

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ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢝꢅꢕꢃꢐꢄꢃ$ꢃꢍꢇꢄ%ꢅ0ꢎꢇꢊꢇꢍ%ꢉꢊꢃ %ꢃꢍꢁ

+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ.ꢞ/

DS22060B-page 71

MCP413X/415X/423X/425X

ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ) ꢄꢈꢈꢆ*ꢎꢊꢈꢋ'ꢃꢆꢕ)ꢑꢗꢆMꢆꢑꢄ((ꢒ+ꢐꢆꢘꢛꢜꢚꢆ ꢆ!ꢒꢅ"ꢆ#)*&,$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22060B-page 72

MCP413X/415X/423X/425X

-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

e

b

N

L

K

E

E2

EXPOSED

PAD

NOTE 1

2

1

2

D2

BOTTOM VIEW

TOP VIEW

A

A1

A3

NOTE 2

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

ꢀꢚ

ꢚꢁ.ꢚꢅ/ꢕ0

ꢚꢁꢛꢚ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%

ꢕ%ꢇꢄ"ꢌ$$ꢅ

0ꢌꢄ%ꢇꢍ%ꢅꢗꢎꢃꢍ*ꢄꢉ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ5ꢉꢄꢐ%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ

6

ꢉ

ꢔ

ꢔꢀ

ꢔ+

ꢓ

ꢓꢏ

,

ꢚꢁ9ꢚ

ꢚꢁꢚꢚ

ꢀꢁꢚꢚ

ꢚꢁꢚ.

ꢚꢁꢚꢏ

ꢚꢁꢏꢚꢅꢘ,2

+ꢁꢚꢚꢅ/ꢕ0

ꢏꢁ+.

+ꢁꢚꢚꢅ/ꢕ0

ꢀꢁ.9

ꢚꢁꢏ.

ꢚꢁꢒꢚ

M

ꢏꢁꢏꢚ

ꢏꢁꢒ9

,#ꢑꢌ ꢉ"ꢅꢂꢇ"ꢅ<ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ<ꢃ"%ꢎ

0ꢌꢄ%ꢇꢍ%ꢅ5ꢉꢄꢐ%ꢎ

0ꢌꢄ%ꢇꢍ%ꢜ%ꢌꢜ,#ꢑꢌ ꢉ"ꢅꢂꢇ"

,ꢏ

(

5

ꢀꢁꢒꢚ

ꢚꢁꢀ9

ꢚꢁ+ꢚ

ꢚꢁꢏꢚ

ꢀꢁꢞ.

ꢚꢁ+ꢚ

ꢚꢁ.ꢚ

M

>

ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢂꢇꢍ*ꢇꢐꢉꢅ&ꢇꢋꢅꢎꢇꢆꢉꢅꢌꢄꢉꢅꢌꢊꢅ&ꢌꢊꢉꢅꢉ#ꢑꢌ ꢉ"ꢅ%ꢃꢉꢅ(ꢇꢊ ꢅꢇ%ꢅꢉꢄ" ꢁ

+ꢁ ꢂꢇꢍ*ꢇꢐꢉꢅꢃ ꢅ ꢇ)ꢅ ꢃꢄꢐ!ꢈꢇ%ꢉ"ꢁ

ꢒꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:+/

DS22060B-page 73

MCP413X/415X/423X/425X

-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆꢏꢈꢄꢊꢐꢆꢑꢒꢆꢂꢃꢄꢅꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕꢖꢏꢗꢆMꢆꢘꢙꢘꢙꢚꢛꢜꢆ ꢆ!ꢒꢅ"ꢆ#ꢍꢏꢑ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

DS22060B-page 74

MCP413X/415X/423X/425X

-ꢚꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢖꢋꢌ(ꢒꢆ) ꢄꢈꢈꢆ*ꢎꢊꢈꢋ'ꢃꢆꢇꢄꢌꢓꢄꢔꢃꢆꢕ.ꢑꢗꢆ#ꢖ)*ꢇ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

D

N

E

E1

NOTE 1

1

2

b

e

c

A

A2

φ

L

A1

L1

4ꢄꢃ%

ꢖꢙ55ꢙꢖ,ꢗ,ꢘꢕ

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢖꢙ6

67ꢖ

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

6

ꢉ

ꢀꢚ

ꢚꢁ.ꢚꢅ/ꢕ0

7ꢆꢉꢊꢇꢈꢈꢅ;ꢉꢃꢐꢎ%

ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅꢗꢎꢃꢍ*ꢄꢉ

ꢕ%ꢇꢄ"ꢌ$$ꢅ

7ꢆꢉꢊꢇꢈꢈꢅ<ꢃ"%ꢎ

ꢖꢌꢈ"ꢉ"ꢅꢂꢇꢍ*ꢇꢐꢉꢅ<ꢃ"%ꢎ

7ꢆꢉꢊꢇꢈꢈꢅ5ꢉꢄꢐ%ꢎ

2ꢌꢌ%ꢅ5ꢉꢄꢐ%ꢎ

ꢔ

M

ꢚꢁꢞ.

ꢚꢁꢚꢚ

M

ꢚꢁ9.

ꢀꢁꢀꢚ

ꢚꢁꢛ.

ꢚꢁꢀ.

ꢔꢏ

ꢔꢀ

,

,ꢀ

ꢓ

M

ꢒꢁꢛꢚꢅ/ꢕ0

+ꢁꢚꢚꢅ/ꢕ0

ꢚꢁ:ꢚ

5

ꢚꢁꢒꢚ

ꢚꢁ9ꢚ

2ꢌꢌ%ꢑꢊꢃꢄ%

2ꢌꢌ%ꢅꢔꢄꢐꢈꢉ

5ꢀ

ꢀ

ꢚꢁꢛ.ꢅꢘ,2

M

ꢚꢟ

9ꢟ

5ꢉꢇ"ꢅꢗꢎꢃꢍ*ꢄꢉ

5ꢉꢇ"ꢅ<ꢃ"%ꢎ

ꢍ

(

ꢚꢁꢚ9

ꢚꢁꢀ.

M

ꢚꢁꢏ+

ꢚꢁ++

ꢑꢒꢊꢃꢉ%

ꢀꢁ ꢂꢃꢄꢅꢀꢅꢆꢃ !ꢇꢈꢅꢃꢄ"ꢉ#ꢅ$ꢉꢇ%!ꢊꢉꢅ&ꢇꢋꢅꢆꢇꢊꢋ'ꢅ(!%ꢅ&! %ꢅ(ꢉꢅꢈꢌꢍꢇ%ꢉ"ꢅ)ꢃ%ꢎꢃꢄꢅ%ꢎꢉꢅꢎꢇ%ꢍꢎꢉ"ꢅꢇꢊꢉꢇꢁ

ꢏꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄ ꢅꢓꢅꢇꢄ"ꢅ,ꢀꢅ"ꢌꢅꢄꢌ%ꢅꢃꢄꢍꢈ!"ꢉꢅ&ꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢁꢅꢖꢌꢈ"ꢅ$ꢈꢇ ꢎꢅꢌꢊꢅꢑꢊꢌ%ꢊ! ꢃꢌꢄ ꢅ ꢎꢇꢈꢈꢅꢄꢌ%ꢅꢉ#ꢍꢉꢉ"ꢅꢚꢁꢀ.ꢅ&&ꢅꢑꢉꢊꢅ ꢃ"ꢉꢁ

+ꢁ ꢓꢃ&ꢉꢄ ꢃꢌꢄꢃꢄꢐꢅꢇꢄ"ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢃꢄꢐꢅꢑꢉꢊꢅꢔꢕꢖ,ꢅ-ꢀꢒꢁ.ꢖꢁ

/ꢕ01 /ꢇ ꢃꢍꢅꢓꢃ&ꢉꢄ ꢃꢌꢄꢁꢅꢗꢎꢉꢌꢊꢉ%ꢃꢍꢇꢈꢈꢋꢅꢉ#ꢇꢍ%ꢅꢆꢇꢈ!ꢉꢅ ꢎꢌ)ꢄꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ ꢁ

ꢘ,21 ꢘꢉ$ꢉꢊꢉꢄꢍꢉꢅꢓꢃ&ꢉꢄ ꢃꢌꢄ'ꢅ! !ꢇꢈꢈꢋꢅ)ꢃ%ꢎꢌ!%ꢅ%ꢌꢈꢉꢊꢇꢄꢍꢉ'ꢅ$ꢌꢊꢅꢃꢄ$ꢌꢊ&ꢇ%ꢃꢌꢄꢅꢑ!ꢊꢑꢌ ꢉ ꢅꢌꢄꢈꢋꢁ

ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚꢏꢀ/

DS22060B-page 75

MCP413X/415X/423X/425X

-/ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢆ&'ꢁꢂꢋ'ꢃꢆꢕꢇꢗꢆMꢆꢘꢚꢚꢆ ꢋꢈꢆ!ꢒꢅ"ꢆ#ꢇꢍ&ꢇ$

ꢑꢒꢊꢃ% 2ꢌꢊꢅ%ꢎꢉꢅ&ꢌ %ꢅꢍ!ꢊꢊꢉꢄ%ꢅꢑꢇꢍ*ꢇꢐꢉꢅ"ꢊꢇ)ꢃꢄꢐ 'ꢅꢑꢈꢉꢇ ꢉꢅ ꢉꢉꢅ%ꢎꢉꢅꢖꢃꢍꢊꢌꢍꢎꢃꢑꢅꢂꢇꢍ*ꢇꢐꢃꢄꢐꢅꢕꢑꢉꢍꢃ$ꢃꢍꢇ%ꢃꢌꢄꢅꢈꢌꢍꢇ%ꢉ"ꢅꢇ%ꢅ

ꢎ%%ꢑ133)))ꢁ&ꢃꢍꢊꢌꢍꢎꢃꢑꢁꢍꢌ&3ꢑꢇꢍ*ꢇꢐꢃꢄꢐ

N

NOTE 1

E1

3

1

2

D

E

A2

A

L

c

A1

b1

b

e

eB

4ꢄꢃ%

ꢓꢃ&ꢉꢄ ꢃꢌꢄꢅ5ꢃ&ꢃ%

ꢙ60;,ꢕ

67ꢖ

ꢀꢒ

ꢁꢀꢚꢚꢅ/ꢕ0

M

ꢖꢙ6

ꢖꢔ8

6!&(ꢉꢊꢅꢌ$ꢅꢂꢃꢄ

ꢂꢃ%ꢍꢎ

6

ꢉ

ꢔ

ꢗꢌꢑꢅ%ꢌꢅꢕꢉꢇ%ꢃꢄꢐꢅꢂꢈꢇꢄꢉ

M

ꢁꢏꢀꢚ

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ꢑꢒꢊꢃꢉ%

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DS22060B-page 76

MCP413X/415X/423X/425X

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ꢖꢃꢍꢊꢌꢍꢎꢃꢑ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢓꢊꢇ)ꢃꢄꢐ 0ꢚꢒꢜꢚ:./

DS22060B-page 77

MCP413X/415X/423X/425X

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DS22060B-page 78

MCP413X/415X/423X/425X

-/ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ01ꢋ'ꢆ)1(ꢋ'ꢓꢆ) ꢄꢈꢈꢆ*ꢎꢊꢈꢋ'ꢃꢆꢕ)0ꢗꢆMꢆ/ꢛ/ꢆ ꢆ!ꢒꢅ"ꢆ#0))*ꢇ$

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DS22060B-page 79

MCP413X/415X/423X/425X

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DS22060B-page 80

MCP413X/415X/423X/425X

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DS22060B-page 81

MCP413X/415X/423X/425X

NOTES:

DS22060B-page 82

MCP413X/415X/423X/425X

APPENDIX A: REVISION HISTORY

APPENDIX B: MIGRATING FROM

THE MCP41XXX AND

Revision B (December 2008)

MCP42XXX DEVICES

The following is the list of modifications:

This is intended to give an overview of some of the

differences to be aware of when migrating from the

MCP41XXX and MCP42XXX devices.

1. Updated I_PUspecifications to specify test

conditions and new limit.

2. Updated DFN package in “Package Types (top

view)”, including Exposed Thermal Pad sample

(EP).

B.1

MCP41XXX to MCP41XX

Differences

3. Added new descriptions in Section 3.0 “Pin

Descriptions”.

Here are some of the differences to be aware of:

1. SI pin is now SDI/SDO pin, and the contents of

the device memory can be read.

4. Added new Development Tool support items.

5. Updated Package Outline section.

2. Need to address the Terminal Connect Feature

(TCON register) of MCP41XX.

Revision A (September 2007)

3. MCP41XX supports software Shutdown mode.

4. New 5 kΩ version.

• Original Release of this Document.

5. MCP41XX have 7-bit resolution options.

6. Alternate pinout versions (for Rheostat

configuration).

7. Verify device’s electrical specifications.

8. Interface signals are now high voltage tolerant.

9. Interface signals now have internal pull-up

resistors.

B.2

MCP42XXX to MCP42XX

Differences

Here are some of the differences to be aware of:

1. Daisy chaining of devices is no longer

supported.

2. SDO pin allows contents of device memory to be

read.

3. Need to address the Terminal Connect Feature

(TCON register) of MCP42XX.

4. MCP42XX supports software Shutdown mode.

5. New 5 kΩ version.

6. MCP42XX have 7-bit resolution options.

7. Alternate package/pinout versions (for Rheostat

configuration).

8. Verify device’s electrical specifications.

9. Interface signals are now high voltage tolerant

10. Interface signals now have internal pull-up

resistors.

DS22060B-page 83

MCP413X/415X/423X/425X

NOTES:

DS22060B-page 84

MCP413X/415X/423X/425X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

XXX

X

/XX

a)

b)

c)

d)

e)

f)

MCP4131-502E/XX: 5 kΩ, 8LD Device

MCP4131T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4131-103E/XX: 10 kΩ, 8-LD Device

MCP4131T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4131-503E/XX: 50 kΩ, 8LD Device

MCP4131T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4131-104E/XX: 100 kΩ, 8LD Device

MCP4131T-104E/XX: T/R, 100 kΩ, 8LD Device

Resistance Temperature

Version

Package

Range

Device

MCP4131:

MCP4131T:

Single Volatile 7-bit Potentiometer

(Tape and Reel)

g)

h)

MCP4132:

MCP4132T:

Single Volatile 7-bit Rheostat

(Tape and Reel)

Single Volatile 8-bit Potentiometer

(Tape and Reel)

Single Volatile 8-bit Rheostat

(Tape and Reel)

Dual Volatile 7-bit Potentiometer

(Tape and Reel)

Dual Volatile 7-bit Rheostat

(Tape and Reel)

Dual Volatile 8-bit Potentiometer

(Tape and Reel)

Dual Volatile 8-bit Rheostat

(Tape and Reel)

a)

b)

c)

d)

e)

f)

MCP4132-502E/XX: 5 kΩ, 8LD Device

MCP4132T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4132-103E/XX: 10 kΩ, 8-LD Device

MCP4132T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4132-503E/XX: 50 kΩ, 8LD Device

MCP4132T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4132-104E/XX: 100 kΩ, 8LD Device

MCP4132T-104E/XX: T/R, 100 kΩ, 8LD Device

MCP4151:

MCP4151T:

MCP4152:

MCP4152T:

g)

h)

MCP4231:

MCP4231T:

a)

b)

c)

d)

e)

f)

MCP4151-502E/XX: 5 kΩ, 8LD Device

MCP4151T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4151-103E/XX: 10 kΩ, 8-LD Device

MCP4151T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4151-503E/XX: 50 kΩ, 8LD Device

MCP4151T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4151-104E/XX: 100 kΩ, 8LD Device

MCP4151T-104E/XX: T/R, 100 kΩ, 8LD Device

MCP4232:

MCP4232T:

MCP4251:

MCP4251T:

g)

h)

MCP4252:

MCP4252T:

a)

b)

c)

d)

e)

f)

MCP4152-502E/XX: 5 kΩ, 8LD Device

MCP4152T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4152-103E/XX: 10 kΩ, 8-LD Device

MCP4152T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4152-503E/XX: 50 kΩ, 8LD Device

MCP4152T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4152-104E/XX: 100 kΩ, 8LD Device

MCP4152T-104E/XX: T/R, 100 kΩ, 8LD Device

Resistance Version: 502

=

5 kΩ

10 kΩ

50 kΩ

103

503

104

g)

h)

100 kΩ

a)

b)

c)

d)

e)

f)

MCP4231-502E/XX: 5 kΩ, 8LD Device

MCP4231T-502E/XX: T/R, 5 kΩΩ, 8LD Device

MCP4231-103E/XX: 10 kΩ, 8-LD Device

MCP4231T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4231-503E/XX: 50 kΩ, 8LD Device

MCP4231T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4231-104E/XX: 100 kΩ, 8LD Device

MCP4231T-104E/XX: T/R, 100 kΩ, 8LD Device

Temperature Range

Package

I

E

= -40°C to +85°C (Industrial)

= -40°C to +125°C (Extended)

MF

ML

MS

P

SN

SL

ST

UN

=

Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead

Plastic Quad Flat No-lead (QFN), 16-lead

g)

h)

Plastic Micro Small Outline (MSOP), 8-lead

Plastic Dual In-line (PDIP) (300 mil), 8/14-lead

Plastic Small Outline (SOIC), (150 mil), 8-lead

Plastic Small Outline (SOIC), (150 mil), 14-lead

Plastic Thin Shrink Small Outline (TSSOP), 14-lead

Plastic Micro Small Outline (MSOP), 10-lead

a)

b)

c)

d)

e)

f)

MCP4232-502E/XX: 5 kΩ, 8LD Device

MCP4232T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4232-103E/XX: 10 kΩ, 8-LD Device

MCP4232T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4232-503E/XX: 50 kΩ, 8LD Device

MCP4232T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4232-104E/XX: 100 kΩ, 8LD Device

MCP4232T-104E/XX: T/R, 100 kΩ, 8LD Device

g)

h)

a)

b)

c)

d)

e)

f)

MCP4251-502E/XX: 5 kΩ, 8LD Device

MCP4251T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4251-103E/XX: 10 kΩ, 8-LD Device

MCP4251T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4251-503E/XX: 50 kΩ, 8LD Device

MCP4251T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4251-104E/XX: 100 kΩ, 8LD Device

MCP4251T-104E/XX: T/R, 100 kΩ, 8LD Device

g)

h)

a)

b)

c)

d)

e)

f)

MCP4252-502E/XX: 5 kΩ, 8LD Device

MCP4252T-502E/XX: T/R, 5 kΩ, 8LD Device

MCP4252-103E/XX: 10 kΩ, 8-LD Device

MCP4252T-103E/XX: T/R, 10 kΩ, 8LD Device

MCP4252-503E/XX: 50 kΩ, 8LD Device

MCP4252T-503E/XX: T/R, 50 kΩ, 8LD Device

MCP4252-104E/XX: 100 kΩ, 8LD Device

MCP4252T-104E/XX: T/R, 100 kΩ, 8LD Device

g)

h)

XX

=

MF for 8/10-lead 3x3 DFN

ML for 16-lead QFN

MS for 8-lead MSOP

P for 8/14-lead PDIP

SN for 8-lead SOIC

SL for 14-lead SOIC

ST for 14-lead TSSOP

UN for 10-lead MSOP

DS22060B-page 85

MCP413X/415X/423X/425X

NOTES:

DS22060B-page 86

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC³²logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22060B-page 87

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

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Tel: 852-2401-1200

Fax: 852-2401-3431

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Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

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Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/02/08

DS22060B-page 88


型号：	MCP4231-103I/SN
厂家：	MICROCHIP
描述：	7/8-Bit Single/Dual SPI Digital POT with Volatile Memory 7/8位单/双SPI数字电位器具有易失性存储器转换器电位器数字电位计存储光电二极管
文件：	总88页 (文件大小：2525K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4231-103I/SN [MICROCHIP]

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