MCP4452T-103E/ML [MICROCHIP]
7/8-Bit Volatile Quad Digital POT with I2C Interface;
| 型号： | MCP4452T-103E/ML |
| 厂家： | 
MICROCHIP |
| 描述： | 7/8-Bit Volatile Quad Digital POT with I2C Interface |
| 文件： | 总94页 (文件大小：6040K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP443X/5X
7/8-Bit Volatile Quad Digital POT
with I2C Interface
Package Types (Top View)
Features
• Quad Resistor Network
• Potentiometer or Rheostat Configuration Options
• Resistor Network Resolution:
7-bit – 128 Resistors (129 Taps)
8-bit – 256 Resistors (257 Taps)
• Four RAB Resistances options:
5 k
MCP44X1 Quad Potentiometers
P2A
P2W
P2B
P3A
P3W
P3B
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
V
A1
HVC/A0
SCL
DD
SDA
15 RESET
V
10 k
50 k
100 k
14 NC
SS
P0B
P0W
P0A
P1B
P1W
P1A
12
12
11
• Zero-scale to Full-scale Wiper Operation
• Low Wiper Resistance – 75 typical
• Low Tempco:
TSSOP
Absolute (Rheostat) – 50 ppm typical (0°-70°C)
Ratiometric (Potentiometer) – 15 ppm typical
• I2C Serial Interface Support:
100 kHz
17 16
18
19
20
15
V
DD
400 kHz
P3B
1
14 A1
3.4 MHz
HVC/A0
SCL
2
3
4
5
RESET
13
12
EP
21
• Serial Protocol Allows High-Speed Read/Write to
Wiper
NC
SDA
• Resistor Network Terminal Disconnect Feature
via Terminal Control (TCON) Register
P0B
11
V
SS
8
9 10
6
7
• Reset Input Pin
• Brown-out Reset Protection – 1.5V typical
• Serial Interface Inactive Current – 2.5 uA typical
• High-Voltage Tolerant Digital Inputs Up to 12.5V
• Supports Split Rail Applications
4x4 QFN
• Internal Weak Pull-up on All Digital Inputs, except
SCL and SDA
• Wide Operating Voltage:
MCP44X2 Quad Rheostat
2.7V to 5.5V - Device Characteristics Specified
1.8V to 5.5V - Device Operation
P2W
P2B
P3W
P3B
14
13
12
11
10
9
1
2
3
4
5
6
7
• Wide Bandwidth (-3 dB) Operation –
2 MHz typical for 5.0 k Device
• Extended Temperature Range (-40°C to +125°C)
V
A1
P0B
P0W
P1W
HVC/A0
SCL
DD
SDA
V
SS
• Three Package Types:
4x4 QFN-20
8
P1B
TSSOP
TSSOP-20
TSSOP-14
2010 Microchip Technology Inc.
DS22267A-page 1
MCP443X/5X
Device Block Diagram
VDD
VSS
Power-up/
Brown-out
Control
P0A
Resistor
Network 0
(Pot 0)
P0W
I2C Serial
Interface
Module &
Control
Wiper 0
& TCON0
Register
A1
HVC/A0
P0B
P1A
SCL
SDA
Logic
Resistor
Network 1
(Pot 1)
RESET
P1W
Wiper 1
& TCON0
Register
Memory (16x9)
Wiper0 (Vol)
Wiper1 (Vol)
Wiper2 (Vol)
Wiper3 (Vol)
P1B
P2A
Resistor
Network 2
(Pot 2)
TCON0
TCON1
P2W
Wiper 2
& TCON1
Register
P2B
P3A
Resistor
Network 3
(Pot 3)
P3W
P3B
Wiper 3
& TCON1
Register
Device Features
Resistance (typical)
Wiper
VDD
Wiper
Configuration
Device
Operating
Range(2)
RAB Options (k)
- RW
()
MCP4431
MCP4432
MCP4441
MCP4442
MCP4451
MCP4452
MCP4461
MCP4462
4
4
4
4
4
4
4
4
Potentiometer (1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0
Rheostat
I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0
Potentiometer (1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0
Rheostat
I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0
Potentiometer(1) I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0
Rheostat
I2C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0
Potentiometer(1) I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0
Rheostat
I2C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0
75
75
75
75
75
75
75
75
129 1.8V to 5.5V
129 1.8V to 5.5V
129 2.7V to 5.5V
129 2.7V to 5.5V
257 1.8V to 5.5V
257 1.8V to 5.5V
257 2.7V to 5.5V
257 2.7V to 5.5V
Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).
2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.
DS22267A-page 2
2010 Microchip Technology Inc.
MCP443X/5X
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device.
This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification
is not implied. Exposure to maximum rating conditions
for extended periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
Voltage on VDD with respect to VSS ..... -0.6V to +7.0V
Voltage on HVC/A0, A1, SCL, SDA, and RESET, with
respect to VSS ............................................... -0.6V to 12.5V
Voltage on all other pins (PxA, PxW, and PxB), with
respect to VSS ..................................... -0.3V to VDD + 0.3V
Input clamp current, IIK
(VI < 0, VI > VDD, VI > VPP ON HV pins)...........±20 mA
Output clamp current, IOK
(VO < 0 or VO > VDD) .......................................±20 mA
Maximum output current sunk by any Output pin
...........................................................................25 mA
Maximum output current sourced by any Output pin
...........................................................................25 mA
Maximum current out of VSS pin ......................100 mA
Maximum current into VDD pin .........................100 mA
Maximum current into PXA, PXW & PXB pins .±2.5 mA
Storage temperature .........................-65°C to +150°C
Ambient temperature with power applied
.......................................................... -40°C to +125°C
Package power dissipation (TA = +50°C, TJ = +150°C)
TSSOP-14 .................................................1000 mW
TSSOP-20 ..................................................1110 mW
QFN-20 (4x4).............................................2320 mW
Soldering temperature of leads (10 seconds).. +300°C
ESD protection on all pins 4 kV (HBM),
................................................................ 300V (MM)
Maximum Junction Temperature (TJ) .............. +150°C
2010 Microchip Technology Inc.
DS22267A-page 3
MCP443X/5X
AC/DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified)
Operating Temperature
–40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
2.7
Typ
—
Max
5.5
Units
Conditions
Supply Voltage
VDD
V
V
V
1.8
—
2.7
Serial Interface only.
HVC/A0, SDA,
SCL, A1, RESET
pin
VHV
VSS
—
12.5V
VDD
4.5V
The HVC/A0 pin will be at one
of three input levels
(VIL, VIH or VIHH). (Note 6)
VSS
—
—
—
VDD
+
V
V
VDD
4.5V
<
Voltage Range
8.0V
V
DD Start Voltage
to ensure Wiper
Reset
VBOR
VDDRR
TBORD
1.65
RAM retention voltage (VRAM) < VBOR
VDD Rise Rate to
ensure Power-on
Reset
(Note 9)
V/ms
µs
Delay after device
exits the Reset
state
—
—
—
—
10
20
600
250
5
(VDD > VBOR
)
Supply Current
(Note 10)
IDD
—
—
µA
µA
µA
Serial Interface Active,
HVC/A0 = VIH (or VIL) (Note 11)
Write all 0’s to volatile Wiper 0
VDD = 5.5V, FSCL @ 3.4 MHz
Serial Interface Active,
HVC/A0 = VIH (or VIL) (Note 11)
Write all 0’s to volatile Wiper 0
VDD = 5.5V, FSCL @ 100 kHz
2.5
Serial Interface Inactive,
(Stop condition, SCL = SDA = VIH),
Wiper = 0
VDD = 5.5V, HVC/A0 = VIH
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22267A-page 4
2010 Microchip Technology Inc.
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
-502 devices(Note 1)
-103 devices(Note 1)
-503 devices(Note 1)
-104 devices(Note 1)
Resistance
(± 20%)
RAB
4.0
8.0
5
10
6.0
12.0
60.0
120.0
k
k
k
k
40.0
80.0
50
100
257
129
RAB
Resolution
N
Taps 8-bit
Taps 7-bit
No Missing Codes
No Missing Codes
Note 6
Step Resistance
RS
—
—
/
—
—
8-bit
(256)
RAB
/
7-bit
Note 6
(128)
Nominal
Resistance Match
(| RABWC
-
—
—
—
—
—
—
—
—
—
—
—
—
—
—
0.2
1.50
1.25
1.0
%
%
%
%
%
%
%
%
5 k
MCP44X1 devices only
RABMEAN |) /
0.2
10 k
50 k
100 k
5 k
RABMEAN
0.2
0.2
1.0
(| RBWWC
RBWMEAN |) /
RBWMEAN
-
0.25
0.25
0.25
0.25
75
1.75
1.50
1.25
1.25
160
300
—
Code = Full Scale
10 k
50 k
100 k
Wiper Resistance
(Note 3, Note 4)
RW
VDD = 5.5 V, IW = 2.0 mA, code = 00h
VDD = 2.7 V, IW = 2.0 mA, code = 00h
75
Nominal
Resistance
Tempco
RAB/T
50
ppm/°C TA = -20°C to +70°C
ppm/°C TA = -40°C to +85°C
ppm/°C TA = -40°C to +125°C
ppm/°C Code = Midscale (80h or 40h)
100
150
15
—
—
Ratiometeric
Tempco
VWB/T
RTRACK
—
Resistance
Tracking
Section 2.0
ppm/°C See Typical Performance Curves
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2010 Microchip Technology Inc.
DS22267A-page 5
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
Resistor Terminal
Input Voltage
VA,VW,VB
VSS
—
VDD
V
Note 5, Note 6
Range (Terminals
A, B and W)
I
,
Maximum current
through A, W or B
(Note 6)
IW
—
—
—
—
—
—
2.5
2.5
2.5
mA
mA
mA
Terminal A
Terminal B
Terminal W
AW
W = Full Scale (FS)
I
,
BW
W = Zero Scale (ZS)
I
I
(W = FS) or
(W = ZS)
AW
BW
Maximum RAB
IAB
—
—
—
—
—
—
—
—
—
1.38
0.688
0.138
0.069
—
mA
mA
mA
mA
nA
VB = 0V, VA = 5.5V, RAB(MIN) = 4000
VB = 0V, VA = 5.5V, RAB(MIN) = 8000
VB = 0V, VA = 5.5V, RAB(MIN) = 40000
VB = 0V, VA = 5.5V, RAB(MIN) = 80000
MCP44X1 PxA = PxW = PxB = VSS
MCP44X2 PxB = PxW = VSS
current (IAB
)
(Note 6)
—
—
Leakage current
into A, W or B
IWL
100
100
100
—
nA
—
nA
Terminals Disconnected
(R0A = R0W = R0B = 0;
R1A = R1W = R1B = 0;
R2A = R2W = R2B = 0;
R3A = R3W = R3B = 0)
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22267A-page 6
2010 Microchip Technology Inc.
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
3.0V VDD 5.5V
Full Scale Error
(MCP44X1 only)
(8-bit code = 100h,
7-bit code = 80h)
VWFSE
-6.0
-4.0
-3.5
-2.0
-0.8
-0.5
-0.5
-0.5
—
-0.1
-0.1
—
—
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
LSb
5 k
8-bit
7-bit
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
3.0V VDD 5.5V
-0.1
—
10 k 8-bit
7-bit
-0.1
—
-0.1
—
50 k 8-bit
7-bit
-0.1
—
-0.1
—
100 k 8-bit
7-bit
-0.1
—
Zero Scale Error
(MCP44X1 only)
(8-bit code = 00h,
7-bit code = 00h)
VWZSE
+0.1
+0.1
+0.1
+0.1
+0.1
+0.1
+0.1
+0.1
±0.5
±0.25
+6.0
+3.0
+3.5
+2.0
+0.8
+0.5
+0.5
+0.5
+1
5 k
8-bit
7-bit
—
—
10 k 8-bit
7-bit
—
—
50 k 8-bit
7-bit
—
—
100 k 8-bit
7-bit
—
Potentiometer
Integral
Non-linearity
INL
DNL
BW
-1
8-bit
7-bit
3.0V VDD 5.5V
MCP44X1 devices only
(Note 2)
-0.5
+0.5
Potentiometer
Differential Non-
linearity
-0.5
±0.25
+0.5
LSb
LSb
8-bit
7-bit
3.0V VDD 5.5V
MCP44X1 devices only
(Note 2)
-0.25
±0.125
+0.25
Bandwidth -3 dB
(See Figure 2-90,
load = 30 pF)
—
—
—
—
—
—
—
—
2
2
—
—
—
—
—
—
—
—
MHz 5 k
8-bit
7-bit
Code = 80h
Code = 40h
Code = 80h
Code = 40h
Code = 80h
Code = 40h
Code = 80h
Code = 40h
MHz
1
MHz 10 k 8-bit
1
MHz
kHz
kHz
kHz
kHz
7-bit
50 k 8-bit
7-bit
200
200
100
100
100 k 8-bit
7-bit
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2010 Microchip Technology Inc.
DS22267A-page 7
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
Parameters
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Sym
Min
Typ
Max
Units
Conditions
5.5V, IW = 900 µA
Rheostat Integral
Non-linearity
MCP44X1
(Note 4, Note 8)
MCP44X2devices
only (Note 4)
R-INL
-1.5
±0.5
+4.5
+1.5
LSb
LSb
5 k
8-bit
7-bit
-8.25
+8.25
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V, IW = 190 µA
5.5V, IW = 900 µA
-1.125
-6.0
±0.5
+4.5
+1.125
+6.0
LSb
LSb
3.0V, IW = 480 µA
(Note 7)
Section 2.0
1.8V, IW = 190 µA
5.5V, IW = 450 µA
-1.5
-5.5
±0.5
+2.5
+1.5
+5.5
LSb
LSb
10 k 8-bit
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
5.5V, IW = 450 µA
-1.125
-4.0
±0.5
+2.5
+1.125
+4.0
LSb
LSb
7-bit
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
5.5V, IW = 90 µA
-1.5
-2.0
±0.5
+1
+1.5
+2.0
LSb
LSb
50 k 8-bit
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
5.5V, IW = 90 µA
-1.125
-1.5
±0.5
+1
+1.125
+1.5
LSb
LSb
7-bit
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
5.5V, IW = 45 µA
-1.0
-1.5
±0.5
+1.0
+1.5
LSb
LSb
100 k 8-bit
+0.25
3.0V, IW = 24 µA
(Note 7)
Section 2.0
1.8V, IW = 15 µA
5.5V, IW = 45 µA
-0.8
±0.5
+0.8
+1.125
LSb
LSb
7-bit
-1.125
+0.25
3.0V, IW = 24 µA
(Note 7)
Section 2.0
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
1.8V, IW = 15 µA
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22267A-page 8
2010 Microchip Technology Inc.
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
5.5V, IW = 900 µA
Rheostat
Differential Non-
linearity
R-DNL
-0.5
-1.0
±0.25
+0.5
+0.5
+1.0
LSb
LSb
5 k
8-bit
7-bit
3.0V, IW = 480 µA
(Note 7)
MCP44X1
Section 2.0
1.8V, IW = 190 µA
5.5V, IW = 900 µA
(Note 4, Note 8)
MCP44X2devices
only
-0.375
-0.75
±0.25
+0.5
+0.375
+0.75
LSb
LSb
3.0V, IW = 480 µA
(Note 7)
(Note 4)
Section 2.0
1.8V, IW = 190 µA
5.5V, IW = 450 µA
-0.5
-1.0
±0.25
+0.25
+0.5
+1.0
LSb
LSb
10 k 8-bit
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
5.5V, IW = 450 µA
-0.375
-0.75
±0.25
+0.5
+0.375
+0.75
LSb
LSb
7-bit
3.0V, IW = 240 µA
(Note 7)
Section 2.0
1.8V, IW = 150 µA
5.5V, IW = 90 µA
-0.5
-0.5
±0.25
±0.25
+0.5
+0.5
LSb
LSb
50 k 8-bit
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
5.5V, IW = 90 µA
-0.375
-0.375
±0.25
±0.25
+0.375
+0.375
LSb
LSb
7-bit
3.0V, IW = 48 µA
(Note 7)
Section 2.0
1.8V, IW = 30 µA
5.5V, IW = 45 µA
-0.5
-0.5
±0.25
±0.25
+0.5
+0.5
LSb
LSb
100 k 8-bit
3.0V, IW = 24 µA
(Note 7)
Section 2.0
1.8V, IW = 15 µA
5.5V, IW = 45 µA
-0.375
-0.375
±0.25
±0.25
+0.375
+0.375
LSb
LSb
7-bit
3.0V, IW = 24 µA
(Note 7)
Section 2.0
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
1.8V, IW = 15 µA
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2010 Microchip Technology Inc.
DS22267A-page 9
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Digital Inputs/Outputs (HVC/A0, A1, SDA, SCL, RESET)
Schmitt Trigger
High Input
VIH
0.45 VDD
—
—
V
All
2.7V VDD 5.5V
Inputs (Allows 2.7V Digital VDD with
Threshold
except 5V Analog VDD
)
SDA
and
0.5 VDD
—
—
V
1.8V VDD 2.7V
SCL
0.7 VDD
0.7 VDD
0.7 VDD
0.7 VDD
—
—
—
VMAX
VMAX
VMAX
VMAX
0.2VDD
0.3VDD
0.3VDD
0.3VDD
0.3VDD
—
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
100 kHz
400 kHz
1.7 MHz
3.4 Mhz
SDA
and
SCL
—
—
Schmitt Trigger
Low Input
Threshold
VIL
—
All inputs except SDA and SCL
100 kHz
-0.5
—
SDA
and
SCL
-0.5
—
400 kHz
-0.5
—
1.7 MHz
-0.5
—
3.4 Mhz
Hysteresis of
Schmitt Trigger
Inputs
VHYS
—
0.1VDD
—
All inputs except SDA and SCL
N.A.
—
VDD < 2.0V
100 kHz
N.A.
—
—
VDD 2.0V
VDD < 2.0V
SDA
0.1 VDD
0.05 VDD
0.1 VDD
0.1 VDD
9.0
—
—
and 400 kHz
—
—
VDD 2.0V
SCL
—
—
1.7 MHz
—
—
3.4 Mhz
High Voltage Input
Entry Voltage
VIHHEN
VIHHEX
—
12.5
(Note 6)
Threshold for WiperLock Technology
High Voltage Input
Exit Voltage
—
—
—
—
VDD
+
V
V
0.8V
(Note 6)
High Voltage Limit
VMAX
VOL
12.5
(Note 6)
Pin can tolerate VMAX or less.
Output Low
Voltage (SDA)
VSS
VSS
—
—
0.2VDD
0.4
V
V
VDD < 2.0V, IOL = 1 mA,
VDD ≥2.0V, IOL = 3 mA
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
DS22267A-page 10
2010 Microchip Technology Inc.
MCP443X/5X
AC/DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
DC Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Weak Pull-up
Current
IPU
—
—
1.75
mA
Internal VDD pull-up, VIHH pull-down,
VDD = 5.5V, VHVC = 12.5V
—
—
170
16
—
—
µA
HVC pin, VDD = 5.5V, VHVC = 3V
VDD = 5.5V, VHVC = 3V
HVC Pull-up /
Pull-down
RHVC
k
Resistance
RESET Pull-up
Resistance
RRESET
IIL
—
-1
16
—
—
1
k
VDD = 5.5V, VRESET = 0V
Input Leakage
Current
µA
VIN = VDD (all pins) and
VIN = VSS (all pins except RESET)
Pin Capacitance
Capacitance (PA)
Capacitance (Pw)
Capacitance (PB)
CIN, COUT
CAW
—
—
—
—
10
75
—
—
—
—
pF
pF
pF
pF
fC = 20 MHz
f =1 MHz, Code = Full Scale
f =1 MHz, Code = Full Scale
f =1 MHz, Code = Full Scale
CW
120
75
CBW
RAM (Wiper, TCON) Value
Value Range
N
0h
0h
—
—
1FFh
1FFh
hex
hex
hex
8-bit device
7-bit device
TCON POR/BOR
Setting
1FF
All Terminals connected
Power Requirements
Power Supply
Sensitivity
(MCP44X1)
PSS
—
—
0.0015 0.0035
0.0015 0.0035
%/% 8-bit
%/% 7-bit
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 80h
VDD = 2.7V to 5.5V,
VA = 2.7V, Code = 40h
Note 1: Resistance is defined as the resistance between terminal A to terminal B.
2: INL and DNL are measured at VW with VA = VDD and VB = VSS
.
3: MCP44X1 only.
4: MCP44X2 only, includes VWZSE and VWFSE
.
5: Polarity of resistor terminals A, W and B, with respect to each other, is not restricted.
6: This specification by design.
7: Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and
temperature.
8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.
9: POR/BOR is not rate dependent.
10: Supply current is independent of current through the resistor network.
11: When HVC/A0 = VIHH, the IDD current is less due to current into the HVC/A0 pin. See IPU specification.
2010 Microchip Technology Inc.
DS22267A-page 11
MCP443X/5X
2
1.1
I C Mode Timing Waveforms and Requirements
RESET
t
RSTD
t
RST
SCL
SDA
V
V
IH
IH
Wx
FIGURE 1-1:
RESET Waveforms.
RESET TIMING
TABLE 1-1:
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40°C TA +125°C (extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, 5 k, 10 k, 50 k, 100 k devices.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym
Min
Typ
Max
Units
Conditions
RESET pulse width
tRST
50
—
—
—
—
ns
ns
RESET rising edge
normal mode (Wiper
driving and I2C
tRSTD
20
interface operational)
DS22267A-page 12
2010 Microchip Technology Inc.
MCP443X/5X
VIHH
94
95
VIH
or VIL
VIH or VIL
HVC/A0
SCL
93
91
90
92
SDA
STOP
Condition
START
Condition
FIGURE 1-2:
I2C Bus Start/Stop Bits Timing Waveforms.
TABLE 1-2:
I2C BUS START/STOP BITS REQUIREMENTS
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
Symbol
No.
Characteristic
Standard Mode
Min
Max
Units
Conditions
FSCL
0
0
100
400
1.7
3.4
400
400
400
100
—
kHz Cb = 400 pF, 1.8V - 5.5V
Fast Mode
kHz Cb = 400 pF, 2.7V - 5.5V
High-Speed 1.7
High-Speed 3.4
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
0
MHz Cb = 400 pF, 4.5V - 5.5V
0
MHz Cb = 100 pF, 4.5V - 5.5V
D102
90
Cb
Bus capacitive
loading
—
pF
pF
pF
pF
—
—
—
TSU:STA START condition
Setup time
4700
600
160
160
4000
600
160
160
4000
600
160
160
4000
600
160
160
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Only relevant for repeated
START condition
—
—
—
91
THD:STA START condition
Hold time
—
After this period the first
clock pulse is generated
—
—
—
92
TSU:STO STOP condition
Setup time
—
—
—
—
93
THD:STO STOP condition
Hold time
—
—
—
—
94
95
THVCSU HVC to SCL Setup time
THVCHD SCL to HVC Hold time
—
uS High Voltage Commands
uS High Voltage Commands
25
—
2010 Microchip Technology Inc.
DS22267A-page 13
MCP443X/5X
103
102
100
101
109
SCL
90
106
91
92
107
SDA
In
110
109
SDA
Out
FIGURE 1-3:
I2C Bus Data Timing.
I2C BUS DATA REQUIREMENTS (SLAVE MODE)
TABLE 1-3:
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No.
Sym
Characteristic
Min
Max Units
Conditions
Clock hightime 100 kHz mode
400 kHz mode
4000
600
120
60
—
—
ns
ns
ns
ns
ns
ns
ns
ns
1.8V-5.5V
100
THIGH
2.7V-5.5V
4.5V-5.5V
4.5V-5.5V
1.8V-5.5V
2.7V-5.5V
4.5V-5.5V
4.5V-5.5V
1.7 MHz mode
3.4 MHz mode
—
—
—
101
TLOW
Clock low time 100 kHz mode
400 kHz mode
4700
1300
320
160
1.7 MHz mode
3.4 MHz mode
—
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the TAA 3.4 MHz specification test.
DS22267A-page 14
2010 Microchip Technology Inc.
MCP443X/5X
TABLE 1-3:
I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No.
Sym
Characteristic
Min
Max Units
Conditions
102A (5)
TRSCL
SCL rise time
100 kHz mode
400 kHz mode
1.7 MHz mode
—
20 + 0.1Cb
20
1000
300
80
ns
ns
ns
Cb is specified to be from
10 to 400 pF (100 pF
maximum for 3.4 MHz
mode)
1.7 MHz mode
20
160
ns
After a Repeated Start
condition or an
Acknowledge bit
3.4 MHz mode
3.4 MHz mode
10
10
40
80
ns
ns
After a Repeated Start
condition or an
Acknowledge bit
102B (5)
TRSDA
TFSCL
TFSDA
SDA rise time
SCL fall time
SDA fall time
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
100 kHz mode
—
1000
300
160
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
20 + 0.1Cb
20
10
103A (5)
—
300
300
80
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
20 + 0.1Cb
20
10
—
40
103B (5)
300
Cb is specified to be from
10 to 400 pF (100 pF max
for 3.4 MHz mode)
400 kHz mode 20 + 0.1Cb (4) 300
1.7 MHz mode
3.4 MHz mode
20
10
0
160
80
—
106
THD:DAT Data input hold 100 kHz mode
1.8V-5.5V, Note 6
2.7V-5.5V, Note 6
4.5V-5.5V, Note 6
4.5V-5.5V, Note 6
time
400 kHz mode
0
—
1.7 MHz mode
3.4 MHz mode
0
—
0
—
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the TAA 3.4 MHz specification test.
2010 Microchip Technology Inc.
DS22267A-page 15
MCP443X/5X
TABLE 1-3:
I2C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C AC Characteristics
Standard Operating Conditions (unless otherwise specified)
Operating Temperature –40C TA +125C (Extended)
Operating Voltage VDD range is described in AC/DC characteristics
Param.
No.
Sym
Characteristic
Min
Max Units
Conditions
107
TSU:DAT Data input setup 100 kHz mode
250
100
10
—
—
ns
ns
ns
ns
ns
ns
ns
Note 2
Note 1
time
400 kHz mode
1.7 MHz mode
3.4 MHz mode
—
10
—
109
TAA
Output valid
from clock
100 kHz mode
400 kHz mode
1.7 MHz mode
—
3450
900
150
—
—
Cb = 100 pF,
Note 1, Note 7
—
310
ns
Cb = 400 pF,
Note 1, Note 5
3.4 MHz mode
100 kHz mode
400 kHz mode
1.7 MHz mode
3.4 MHz mode
—
150
—
ns
ns
ns
ns
ns
ns
Cb = 100 pF, Note 1
110
TBUF
Bus free time
4700
1300
N.A.
N.A.
—
Time the bus must be free
before a new transmission
can start
—
—
—
TSP
Input filter spike 100 kHz mode
suppression
50
NXP specification states
N.A.
(SDA and SCL)
400 kHz mode
—
—
—
50
10
10
ns
ns
ns
1.7 MHz mode
3.4 MHz mode
Spike suppression
Spike suppression
Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the
requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not
stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,
it must output the next data bit to the SDA line
TR max.+tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before
the SCL line is released.
3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between VIH
and VIL of the falling edge of the SCL signal. This specification is not a part of the I2C specification, but
must be tested in order to ensure that the output data will meet the setup and hold specifications for the
receiving device.
4: Use Cb in pF for the calculations.
5: Not Tested.
6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do
not unintentionally create a Start or Stop condition.
7: Ensured by the TAA 3.4 MHz specification test.
DS22267A-page 16
2010 Microchip Technology Inc.
MCP443X/5X
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Temperature Ranges
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 14L-TSSOP
Thermal Resistance, 20L-QFN
Thermal Resistance, 20L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
JA
JA
JA
—
—
—
100
43
—
—
—
°C/W
°C/W
°C/W
90
2010 Microchip Technology Inc.
DS22267A-page 17
MCP443X/5X
NOTES:
DS22267A-page 18
2010 Microchip Technology Inc.
MCP443X/5X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
550
500
450
400
350
300
250
200
150
100
50
0
250
200
150
100
50
1000
800
600
400
200
0
3.4MHz, 5.5V
3.4MHz, 4.5V
IHVC
1.7MHz, 5.5V
1.7MHz, 4.5V
-200
-400
-600
-800
-1000
400kHz, 5.5V
100kHz, 5.5V
RHVC
400kHz, 2.7V
100kHz, 2.7V
0
-40
0
40
Temperature (°C)
80
120
2
3
4
5
6
7
8
9
10
V
HVC (V)
FIGURE 2-1:
Device Current (IDD) vs. I2C
FIGURE 2-3:
HVC/A0 Pull-up/Pull-down
Frequency (fSCL) and Ambient Temperature
(VDD = 2.7V and 5.5V).
Resistance (RHVC) and Current (IHVC) vs. HVC/
A0 Input Voltage (VHVC) (VDD = 5.5V).
3.0
12.0
10.0
2.5
5.5V
5.5V Entry
2.7V Entry
2.0
8.0
1.5
6.0
5.5V Exit
2.7V
2.7V Exit
1.0
0.5
0.0
4.0
2.0
0.0
-40
0
40
80
120
-40
0
40
80
120
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-2:
Device Current (ISHDN) and
FIGURE 2-4:
HVC/A0 High Input Entry/
VDD. (HVC/A0 = VDD) vs. Ambient Temperature.
Exit Threshold vs. Ambient Temperature and
VDD
.
2010 Microchip Technology Inc.
DS22267A-page 19
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
120
100
80
0.3
0.2
0.1
0
120
100
80
1.25
0.75
0.25
-0.25
-0.75
-1.25
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
INL
DNL
60
60
-0.1
-0.2
-0.3
DNL
-40°C
40
40
-40°C 25°C
RW
25°C
85°C
85°C
RW
125°C
125°C
20
20
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-5:
5 k Pot Mode – RW (),
FIGURE 2-8:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
Ambient Temperature (VDD = 5.5V).
300
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
300
260
220
180
140
100
60
0.3
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
6
260
220
180
140
100
60
0.2
0.1
0
INL
INL
4
DNL
2
RW
RW
125°C
-0.1
-0.2
-0.3
0
-40°C
85°C
25°C
25°C
DNL
-40°C
125°C 85°C
20
20
-2
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-6:
5 k Pot Mode – RW (),
FIGURE 2-9:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Ambient Temperature (VDD = 3.0V).
118
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.5
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
2500
2000
1500
1000
500
2500
2000
1500
1000
500
0.4
0.3
0.2
0.1
0
98
78
58
38
18
-2
INL
INL
-0.1
-0.2
-0.3
DNL
DNL
RW
RW
0
0
0
64
128
192
256
0
64
128
192
256
Wiper Setting (decimal)
Wiper Setting (decimal)
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-7:
5 k Pot Mode – RW (),
FIGURE 2-10:
5 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
Ambient Temperature (VDD = 1.8V, IW = 260 µA).
DS22267A-page 20
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
5300
5250
6000
5000
4000
3000
2000
1000
0
2.7V
5200
5150
-40C
+25C
+85C
+125C
5100
5.5V
5050
-40
0
40
80
120
0
32
64
96
128
160
192
224
256
Wiper Code
Ambient Temperature (°C)
FIGURE 2-11:
5 k – Nominal Resistance
FIGURE 2-12:
5 k – RWB () vs. Wiper
(RAB) () vs. Ambient Temperature and VDD
.
Setting and Ambient Temperature
(VDD = 5.5V, IW = 190 µA).
6000
5000
4000
3000
2000
1000
0
-40C
+25C
+85C
+125C
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE 2-13:
5 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 190 µA).
7000
6000
5000
4000
3000
2000
1000
0
-40C
+25C
+85C
+125C
0
32
64
96
128
160
192
224
256
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-14:
5 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 190 µA).
2010 Microchip Technology Inc.
DS22267A-page 21
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.50%
54
52
50
48
46
44
42
40
-40C
CH0
CH2
CH1
CH3
+25C
1.50%
+85C
+125C
0.50%
-0.50%
-1.50%
-2.50%
0
32
64
96
128
160
192
224
256
0
32
64
96 128 160 192 224 256
Wiper Code
Wiper Code
FIGURE 2-18:
5 k – RWB PPM/°C vs.
FIGURE 2-15:
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 190 µA).
5 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 190 µA).
100
2.50%
-40C
CH0
CH2
CH1
CH3
95
90
85
80
75
70
65
60
+25C
1.50%
+85C
+125C
0.50%
-0.50%
-1.50%
-2.50%
0
32
64
96
128
160
192
224
256
0
32
64
96
128 160 192 224 256
Wiper Code
Wiper Code
FIGURE 2-19:
5 k – RWB PPM/°C vs.
FIGURE 2-16:
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 190 µA).
5 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 190 µA).
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
500
0
-500
-1000
-4.00%
-5.00%
-40C
+25C
-1500
-2000
CH0
CH2
CH1
CH3
+85C
+125C
-6.00%
-7.00%
0
32
64
96
128
160
192
224
256
0
32
64
96
128 160 192 224 256
Wiper Code
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-17:
5 k – Worst Case RBW
FIGURE 2-20:
5 k – RWB PPM/°C vs.
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 190 µA).
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 190 µA).
DS22267A-page 22
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-21:
5 k – Low-Voltage
FIGURE 2-24:
5 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
(1 µs/Div).
FIGURE 2-22:
5 k – Low-Voltage
FIGURE 2-25:
5 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
(1 µs/Div).
FIGURE 2-23:
5 k – Power-Up Wiper
Response Time (20 ms/Div).
2010 Microchip Technology Inc.
DS22267A-page 23
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
120
100
80
0.3
0.2
0.1
0
120
100
80
1
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.5
0
INL
INL
DNL
60
60
-0.1
-0.2
-0.3
-0.5
-1
DNL
40
-40°C
40
-40°C
RW
25°C
85°C
85°C 25°C
RW
125°C
125°C
20
20
0
25 50 75 100 125150175200225 250
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-26:
10 k Pot Mode – RW (),
FIGURE 2-29:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
Ambient Temperature (VDD = 5.5V).
300
260
220
180
140
100
60
4
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
300
260
220
180
140
100
60
0.3
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
3
0.2
0.1
0
INL
INL
DNL
2
1
0
-0.1
-0.2
-0.3
RW
DNL RW
-1
-2
-40°C
-40°C
25°C
85°C 25°C
125°C
85°C
125°C
20
20
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
25 50 75 100 125 150 175 200 225 250
Wiper Setting (decimal)
FIGURE 2-27:
10 k Pot Mode – RW (),
FIGURE 2-30:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Ambient Temperature (VDD = 3.0V).
0.6
98
-40C Rw
125C Rw
85C INL
25C DNL
25C Rw
85C Rw
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
4000
3500
3000
2500
2000
1500
1000
500
4000
3500
3000
2500
2000
1500
1000
500
-40C INL
125C INL
85C DNL
25C INL
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
88
78
68
58
48
38
28
18
8
-40C DNL
125C DNL
INL
INL
DNL
RW
64
RW
DNL
0
0
-2
0
64
128
192
256
0
128
192
256
Wiper Setting (decimal)
Wiper Setting (decimal)
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-28:
10 k Pot Mode – RW (),
FIGURE 2-31:
10 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
Ambient Temperature (VDD = 1.8V, IW = 125 µA).
DS22267A-page 24
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
10250
10200
12000
10000
8000
6000
4000
2000
0
10150
2.7V
10100
-40C
5.5V
+25C
+85C
+125C
10050
10000
-40
0
40
80
120
0
32
64
96
128 160 192 224 256
Ambient Temperature (°C)
Wiper Code
FIGURE 2-32:
(RAB) () vs. Ambient Temperature and VDD
10 k – Nominal Resistance
FIGURE 2-33:
Setting and Ambient Temperature
(VDD = 5.5V, IW = 150 µA).
10 k – RWB () vs. Wiper
.
12000
10000
8000
6000
4000
2000
0
-40C
+25C
+85C
+125C
0
32
64
96
128 160 192 224 256
Wiper Code
FIGURE 2-34:
10 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 150 µA).
12000
10000
8000
6000
4000
2000
0
-40C
+25C
+85C
+125C
0
32
64
96
128 160 192 224 256
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-35:
10 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 150 µA).
2010 Microchip Technology Inc.
DS22267A-page 25
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
1.50%
50
45
40
35
30
25
20
15
10
-40C
+85C
+25C
+125C
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
CH0
CH2
CH1
CH3
0
32
64
96
128
160
192
224
256
0
32
64
96 128 160 192 224 256
Wiper Code
Wiper Code
FIGURE 2-39:
10 k – RWB PPM/°C vs.
FIGURE 2-36:
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 150 µA).
10 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 150 µA).
60
55
50
45
40
35
1.50%
-40C
+85C
+25C
+125C
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
30
CH0 CH1
CH2 CH3
25
20
0
32
64
96 128 160 192 224 256
Wiper Code
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE 2-40:
10 k – RWB PPM/°C vs.
FIGURE 2-37:
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 150 µA).
10 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 150 µA).
1.50%
200
0
-40C
+85C
+25C
+125C
1.00%
0.50%
0.00%
-0.50%
-1.00%
-1.50%
-200
-400
-600
-800
-1000
CH0
CH2
CH1
CH3
-1200
-1400
0
32
64
96
128
160
192
224
256
0
32 64 96 128 160 192 224 256
Wiper Code
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-41:
10 k – RWB PPM/°C vs.
FIGURE 2-38:
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 150 µA).
10 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 150 µA).
DS22267A-page 26
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-42:
10 k – Low-Voltage
FIGURE 2-44:
10 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
(1 µs/Div).
FIGURE 2-43:
10 k – Low-Voltage
FIGURE 2-45:
10 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
(1 µs/Div).
2010 Microchip Technology Inc.
DS22267A-page 27
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
120
100
80
0.3
0.2
0.1
0
120
100
80
0.3
0.2
0.1
0
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
INL
DNL
DNL
60
60
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
-40°C
40
40
-40°C
RW
25°C
85°C
25°C
85°C
RW
125°C
125°C
20
20
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-46:
50 k Pot Mode – RW (),
FIGURE 2-49:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
Ambient Temperature (VDD = 5.5V).
300
260
220
180
140
100
60
1
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
300
260
220
180
140
100
60
0.3
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.75
0.5
0.25
0
0.2
0.1
0
INL
INL
DNL
DNL
-0.25
-0.5
-0.75
-1
RW
-0.1
-0.2
-0.3
RW
-40°C
-40°C
25°C
25°C
85°C
85°C
125°C
125°C
20
20
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-47:
50 k Pot Mode – RW (),
FIGURE 2-50:
50 k Rheo Mode – RW (),
INL (LSb), DNL (LSb) vs. Wiper Setting and
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Ambient Temperature (VDD = 3.0V).
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
78.5
73.5
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL 68.5
63.5
15000
14000
13000
12000
11000
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
RW
INL
58.5
53.5
DNL
48.5
43.5
38.5
33.5
28.5
23.5
18.5
INL
RW
13.5
DNL
8.5
3.5
-1.5
0
64
128
192
256
0
64
128
192
256
Wiper Setting (decimal)
Wiper Setting (decimal)
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-51:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V, IW = 25 µA).
50 k Rheo Mode – RW (),
FIGURE 2-48:
INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
50 k Pot Mode – RW (),
DS22267A-page 28
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
50800
50600
50400
60000
50000
40000
30000
20000
10000
0
50200
2.7V
50000
5.5V
-40C
49800
+25C
+85C
+125C
49600
49400
-40
0
40
80
120
0
32
64
96
128 160 192 224 256
Ambient Temperature (°C)
Wiper Code
FIGURE 2-52:
(RAB) () vs. Ambient Temperature and VDD
50 k – Nominal Resistance
FIGURE 2-53:
Setting and Ambient Temperature
50 k – RWB () vs. Wiper
.
(VDD = 5.5V, IW = 90 µA).
60000
50000
40000
30000
20000
10000
0
-40C
+25C
+85C
+125C
0
32
64
96
128 160 192 224 256
Wiper Code
FIGURE 2-54:
50 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 48 µA).
60000
50000
40000
30000
20000
10000
0
-40C
+25C
+85C
+125C
0
32
64
96
128 160 192 224 256
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-55:
50 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 30 µA).
2010 Microchip Technology Inc.
DS22267A-page 29
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
7.00%
7
6
5
4
3
2
1
0
-40C
+85C
+25C
+125C
6.00%
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
CH0
CH2
CH1
CH3
-1
-2
-3
0
32
64
96
128
160
192
224
256
0
32
64
96 128 160 192 224 256
Wiper Code
Wiper Code
FIGURE 2-59:
50 k – RWB PPM/°C vs.
FIGURE 2-56:
50 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 90 µA).
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 90 µA).
12
10
8
4.00%
-40C
+25C
3.00%
2.00%
1.00%
0.00%
-1.00%
-2.00%
+85C
+125C
6
4
2
CH0 CH1
CH2 CH3
0
-2
0
32
64
96 128 160 192 224 256
Wiper Code
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE 2-60:
50 k – RWB PPM/°C vs.
FIGURE 2-57:
50 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 48 µA).
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 48 µA).
200
0
3.50%
-40C
+25C
+85C
+125C
2.50%
1.50%
0.50%
-0.50%
-1.50%
-200
-400
-600
-800
-1000
CH0 CH1
-1200
-1400
CH2 CH3
0
32 64 96 128 160 192 224 256
0
32
64
96
128
160
192
224
256
Wiper Code
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-61:
50 k – RWB PPM/°C vs.
FIGURE 2-58:
50 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 30 µA).
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 30 µA).
DS22267A-page 30
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-62:
50 k – Low-Voltage
FIGURE 2-64:
50 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
(1 µs/Div).
FIGURE 2-63:
50 k – Low-Voltage
FIGURE 2-65:
50 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
(1 µs/Div).
2010 Microchip Technology Inc.
DS22267A-page 31
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
120
100
80
0.2
0.1
0
120
100
80
0.3
0.2
0.1
0
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
INL
INL
DNL
DNL
60
60
-0.1
-0.2
-0.3
-0.1
-0.2
40
40
-40°C
-40°C
RW
25°C
85°C
RW
85°C 25°C
125°C
125°C
20
20
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-66:
100 k Pot Mode – RW (),
FIGURE 2-69:
100 k Rheo Mode – RW
INL (LSb), DNL (LSb) vs. Wiper Setting and
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 5.5V).
Ambient Temperature (VDD = 5.5V).
300
260
220
180
140
100
60
0.6
0.4
0.2
0
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
300
260
220
180
140
100
60
0.2
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.15
0.1
INL
INL
DNL
DNL
0.05
0
-0.05
-0.1
-0.15
-0.2
-0.2
-0.4
-0.6
RW
RW
-40°C
-40°C
85°C 25°C
85°C
25°C
125°C
125°C
20
20
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
0
32 64 96 128 160 192 224 256
Wiper Setting (decimal)
FIGURE 2-67:
100 k Pot Mode – RW (),
FIGURE 2-70:
100 k Rheo Mode – RW
INL (LSb), DNL (LSb) vs. Wiper Setting and
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 3.0V).
Ambient Temperature (VDD = 3.0V).
59
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
0.35
-40C Rw
-40C INL
-40C DNL
25C Rw
25C INL
25C DNL
85C Rw
85C INL
85C DNL
125C Rw
125C INL
125C DNL
54
49
44
39
34
29
24
19
14
9
25000
20000
15000
10000
5000
0
0.25
0.15
0.05
-0.05
-0.15
-0.25
-0.35
25000
20000
15000
10000
5000
0
RW
INL
DNL
INL
RW
DNL
4
-1
0
64
128
192
256
0
64
128
192
256
Wiper Setting (decimal)
Wiper Setting (decimal)
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-68:
100 k Pot Mode – RW (),
FIGURE 2-71:
100 k Rheo Mode – RW
INL (LSb), DNL (LSb) vs. Wiper Setting and
(), INL (LSb), DNL (LSb) vs. Wiper Setting and
Ambient Temperature (VDD = 1.8V).
Ambient Temperature (VDD = 1.8V, IW = 10 µA).
DS22267A-page 32
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
101500
101000
120000
100000
80000
60000
40000
20000
0
100500
2.7V
100000
-40C
5.5V
+25C
+85C
+125C
99500
99000
-40
0
40
80
120
0
32
64
96
128 160 192 224 256
Ambient Temperature (°C)
Wiper Code
FIGURE 2-72:
100 k – Nominal
FIGURE 2-73:
Setting and Ambient Temperature
(VDD = 5.5V, IW = 45 µA).
100 k – RWB () vs. Wiper
Resistance (RAB) () vs. Ambient Temperature
and VDD
.
120000
100000
80000
60000
40000
20000
0
-40C
+25C
+85C
+125C
0
32
64
96
128 160 192 224 256
Wiper Code
FIGURE 2-74:
100 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 3.0V, IW = 24 µA).
120000
100000
80000
60000
40000
20000
0
-40C
+25C
+85C
+125C
0
32
64
96
128 160 192 224 256
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-75:
100 k – RWB () vs. Wiper
Setting and Ambient Temperature
(VDD = 1.8V, IW = 15 µA).
2010 Microchip Technology Inc.
DS22267A-page 33
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
14.00%
16
14
12
10
8
13.00%
12.00%
11.00%
10.00%
9.00%
8.00%
7.00%
6.00%
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
-40C
+85C
+25C
+125C
6
4
CH0
CH2
CH1
CH3
2
0
0
32
64
96
128
160
192
224
256
0
32
64
96 128 160 192 224 256
Wiper Code
Wiper Code
FIGURE 2-79:
100 k – RWB PPM/°C vs.
FIGURE 2-76:
100 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 5.5V, IW = 45 µA).
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 5.5V, IW = 45 µA).
18
16
14
12
10
8
7.00%
-40C
+85C
+25C
+125C
6.00%
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
6
4
2
0
CH0
CH2
CH1
CH3
0
32
64
96
128
160
192
224
256
0
32
64
96
128 160 192 224 256
Wiper Code
Wiper Code
FIGURE 2-80:
100 k – RWB PPM/°C vs.
FIGURE 2-77:
100 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 3.0V, IW = 24 µA).
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 3.0V, IW = 24 µA).
200
0
6.00%
-40C
+85C
+25C
+125C
5.00%
4.00%
3.00%
2.00%
1.00%
0.00%
-1.00%
-200
-400
-600
-800
CH0 CH1
CH2 CH3
-1000
-1200
0
32 64 96 128 160 192 224 256
0
32
64
96
128
160
192
224
256
Wiper Code
Wiper Code
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
Note:
See Appendix B: for additional
information of RW resistance variation
characteristics for VDD > 2.7V.
FIGURE 2-81:
100 k – RWB PPM/°C vs.
FIGURE 2-78:
100 k – Worst Case RBW
Wiper Setting. (RBW(code=n, 125°C)-RBW(code=n, -
40°C) )/RBW(code = 256, 25°C)/165°C * 1,000,000)
(VDD = 1.8V, IW = 15 µA).
from Average RBW (RBW0-RBW3) Error (%) vs.
Wiper Setting and Temperature
(VDD = 1.8V, IW = 15 µA).
DS22267A-page 34
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
FIGURE 2-82:
100 k – Low-Voltage
FIGURE 2-84:
100 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 2.7V)
Increment Wiper Settling Time (VDD = 2.7V)
(1 µs/Div).
(1 µs/Div).
FIGURE 2-83:
100 k – Low-Voltage
FIGURE 2-85:
100 k – Low-Voltage
Decrement Wiper Settling Time (VDD = 5.5V)
Increment Wiper Settling Time (VDD = 5.5V)
(1 µs/Div).
(1 µs/Div).
2010 Microchip Technology Inc.
DS22267A-page 35
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
4
230
210
190
170
150
130
110
90
2.7V
5.5V
3.5
5.5V
3
2.5
2
2.7V
1.5
1
70
50
-40
0
40
Temperature (°C)
80
120
-40
0
40
80
120
Temperature (°C)
FIGURE 2-86:
VIH (SDA, SCL) vs. VDD and
FIGURE 2-88:
VOL (SDA) vs. VDD and
Temperature.
Temperature (IOL = 3 mA).
2
5.5V
2.7V
1.5
1
-40
0
40
80
120
Temperature (°C)
FIGURE 2-87:
VIL (SDA, SCL) vs. VDD and
Temperature.
DS22267A-page 36
2010 Microchip Technology Inc.
MCP443X/5X
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V.
2.1
Test Circuits
1.6
1.4
1.2
1.0
0.8
0.6
0.4
+5V
A
B
VIN
W
VOUT
+
-
Offset
GND
0.2
0.0
-40
0
40
80
120
2.5V DC
Temperature (°C)
FIGURE 2-89:
and Temperature.
POR/BOR Trip point vs. VDD
FIGURE 2-90:
-3 db Gain vs. Frequency
Test.
floating
VA
A
VW
W
IW
RBW = VW/IW
W = (VW-VA)/IW
B
R
VB
FIGURE 2-91:
RBW and RW Measurement.
2010 Microchip Technology Inc.
DS22267A-page 37
MCP443X/5X
NOTES:
DS22267A-page 38
2010 Microchip Technology Inc.
MCP443X/5X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
Additional descriptions of the device pins follows.
TABLE 3-1:
PINOUT DESCRIPTION FOR THE MCP443X/5X
Pin
Weak
Pull-up/
down
TSSOP
QFN
20L
Standard Function
Buffer
Type
Symbol
I/O
(Note 1)
14L
20L
P3A
P3W
P3B
HVC/A0
SCL
SDA
VSS
A
A
A
I
Analog
Analog
Analog
No
No
No
—
1
1
2
19
20
1
Potentiometer 3 Terminal A
Potentiometer 3 Wiper Terminal
Potentiometer 3 Terminal B
High Voltage Command / I2C Address 0
I2C Clock Input
2
3
HV w/ST “smart”
3
4
2
I
HV w/ST
HV w/ST
P
No
No
—
4
5
3
5
6
4
I2C Serial Data I/O. Open Drain output
I
—
A
A
A
A
A
A
I
6
7
5
Ground
P1B
P1W
P1A
P0A
P0W
P0B
NC
Analog
Analog
Analog
Analog
Analog
Analog
—
No
No
No
No
No
No
—
7
8
6
Potentiometer 1 Terminal B
Potentiometer 1 Wiper Terminal
Potentiometer 1 Terminal A
Potentiometer 0 Terminal A
Potentiometer 0 Wiper Terminal
Potentiometer 0 Terminal B
No Connect
8
9
7
—
—
9
10
11
12
13
14
15
16
17
18
19
20
—
8
9
10
11
12
13
14
15
16
17
18
21
10
—
—
11
12
13
14
—
—
RESET
A1
I
HV w/ST
Yes
Hardware Reset Pin
I2C Address 1
I
HV w/ST “smart”
VDD
—
A
A
A
—
P
—
No
No
No
—
Positive Power Supply Input
Potentiometer 2 Terminal B
Potentiometer 2 Wiper Terminal
Potentiometer 2 Terminal A
Exposed Pad. (Note 2)
P2B
P2W
P2A
EP
Analog
Analog
Analog
—
Legend: HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)
A = Analog pins (Potentiometer terminals) I = digital input (high Z)
O = digital output
P = Power
I/O = Input / Output
Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and
shut-down current.
2: The QFN package has a contact on the bottom of the package. This contact is conductively connected to
the die substrate, and therefore should be unconnected or connected to the same ground as the device’s
VSS pin.
2010 Microchip Technology Inc.
DS22267A-page 39
MCP443X/5X
3.1
High Voltage Command /
Address 0 (HVC/A0)
3.7
Potentiometer Terminal A
The terminal A pin is available on the MCP44X1
devices, and is connected to the internal
potentiometer’s terminal A.
The HVC/A0 pin is the Address 0 input for the I2C
interface as well as the High Voltage Command pin. At
the device’s POR/BOR the value of the A0 address bit
is latched. This input along with the A1 pin completes
the device address. This allows up to 4 MCP44XX
devices to be on a single I2C bus.
The potentiometer’s terminal A is the fixed connection
to the Full Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x100 for 8-bit devices or 0x80 for 7-bit devices.
During normal operation, the voltage on this pin
determines whether the I2C command is a normal
command or a High Voltage command (when HVC/A0
= VIHH).
The terminal A pin does not have a polarity relative to
the terminal W or B pins. The terminal A pin can
support both positive and negative current. The voltage
on terminal A must be between VSS and VDD
.
The terminal A pin is not available on the MCP44X2
devices, and the internally terminal A signal is floating.
3.2
Serial Clock (SCL)
The SCL pin is the serial interfaces Serial Clock pin.
This pin is connected to the Host Controllers SCL pin.
The MCP44XX is a slave device, so its SCL pin accepts
only external clock signals.
MCP44X1 devices have four terminal A pins, one for
each resistor network. Terminal A is not available on
the MCP44X2 devices.
3.8
Not Connected (NC)
3.3
Serial Data (SDA)
The NC pin is not used.
The SDA pin is the serial interfaces Serial Data pin.
This pin is connected to the Host Controllers SDA pin.
The SDA pin is an open-drain N-channel driver.
3.9
Reset (RESET)
The RESET pin is used to force the device into the
POR/BOR state.
3.4
Ground (V
)
SS
The VSS pin is the device ground reference.
3.10 Address 1 (A1)
The A1 pin is the I2C interface’s Address 1 pin. Along
with the A0 pins, up to 4 MCP44XX devices can be on
a single I2C bus.
3.5
Potentiometer Terminal B
The terminal B pin is connected to the internal
potentiometer’s terminal B.
3.11 Positive Power Supply Input (V
)
The potentiometer’s terminal B is the fixed connection
to the Zero Scale wiper value of the digital
potentiometer. This corresponds to a wiper value of
0x00 for both 7-bit and 8-bit devices.
DD
The VDD pin is the device’s positive power supply input.
The input power supply is relative to VSS
.
While the device VDD < Vmin (2.7V), the electrical
performance of the device may not meet the data sheet
specifications.
The terminal B pin does not have a polarity relative to
the terminal W or A pins. The terminal B pin can
support both positive and negative current. The voltage
on terminal B must be between VSS and VDD
.
3.12 No Connect (NC)
MCP44XX devices have four terminal B pins, one for
each resistor network.
These pins should be either connected to VDD or VSS
.
3.6
Potentiometer Wiper (W) Terminal
3.13 Exposed Pad (EP)
The terminal W pin is connected to the internal
potentiometer’s terminal W (the wiper). The wiper
terminal is the adjustable terminal of the digital
potentiometer. The terminal W pin does not have a
polarity relative to terminals A or B pins. The terminal
W pin can support both positive and negative current.
The voltage on terminal W must be between VSS and
This pad is conductively connected to the device's
substrate. This pad should be tied to the same potential
as the VSS pin (or left unconnected). This pad could be
used to assist as a heat sink for the device when
connected to a PCB heat sink.
VDD
.
MCP44XX devices have four terminal W pins, one for
each resistor network.
DS22267A-page 40
2010 Microchip Technology Inc.
MCP443X/5X
4.1.2
BROWN-OUT RESET
4.0
FUNCTIONAL OVERVIEW
When the device powers down, device VDD will cross
VPOR/VBOR voltage.
This data sheet covers a family of four volatile Digital
Potentiometer and Rheostat devices that will be
referred to as MCP44XX. The MCP44X1 devices are
the Potentiometer configuration, while the MCP44X2
devices are the Rheostat configuration.
When VDD voltage decreases below VPOR/VBOR
voltage, the serial Interface is disabled.
If the VDD voltage decreases below VRAM voltage, the
following events may occur:
As the Device Block Diagram shows, there are four
main functional blocks. These are:
• Volatile wiper registers could become corrupted
• TCON registers could become corrupted
• POR/BOR and RESET Operation
• Memory Map
As the voltage recovers above the VPOR/VBOR voltage,
the operation is the same as Power-on Reset, as dis-
cussed in the previous subsection.
• Resistor Network
• Serial Interface (I2C)
The POR/BOR operation and the Memory Map are
discussed in this section and the Resistor Network and
I2C operation are described in their own sections. The
Device Commands commands are discussed in
Section 7.0.
Serial commands that are not completed because of a
brown-out condition could cause the memory location
to become corrupted.
4.1.3
RESET PIN
The RESET pin can be used to force the device into
the POR/BOR state of the device. When the RESET
pin is forced Low, the device is forced into the Reset
state. This means that the TCON registers are forced
to their default values and the volatile wiper registers
are loaded with the default value. Also the I2C inter-
face is disabled.
4.1
POR/BOR and RESET Operation
The Power-on Reset is the case where the device is
having power applied to it from VSS. The Brown-out
Reset occurs when a device had power applied to it,
and that power (voltage) drops below the specified
range.
This feature allows a hardware method for all registers
to be updated at the same time.
The devices RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR). The
maximum VPOR/VBOR voltage is less then 1.8V.
4.1.4
INTERACTION OF RESET PIN AND
BOR/POR CIRCUITRY
When VPOR/VBOR < VDD < 2.7V, the electrical perfor-
mance may not meet the data sheet specifications. In
this region, the device is capable of incrementing, dec-
rementing, reading and writing to its volatile memory if
the proper serial command is executed.
Figure 4-1 shows how the RESET pin signal and the
POR/BOR signal interact to control the hardware Reset
state of the device.
When VDD < VPOR/VBOR or the RESET pin is Low, the
pin weak pull-ups are enabled.
RESET (from pin)
Device Reset
POR/BOR signal
4.1.1
POWER-ON RESET
When the device powers up, the device VDD crosses
the VPOR/VBOR voltage.
FIGURE 4-1:
RESET Pin Interaction.
POR/BOR Signal and
When the VDD voltage crosses the VPOR/VBOR voltage,
the following events occur:
• Volatile wiper register is loaded with the default
value
• TCON registers are loaded with their default value
• Device is capable of digital operation
2010 Microchip Technology Inc.
DS22267A-page 41
MCP443X/5X
The volatile memory starts functioning at the RAM
retention voltage (VRAM). The POR/BOR Wiper code is
shown in Table 4-1.
4.2
Memory Map
The device memory supports 16 locations that are 9-bit
wide (16x9 bits). This memory space contains only
volatile locations (see Table 4-2).
TABLE 4-1:
STANDARD SETTINGS
4.2.1
VOLATILE MEMORY (RAM)
Wiper
Code
Default
POR Wiper
Setting
Resistance Typical
There are six Volatile Memory locations. These are:
Code
RAB Value
8-bit 7-bit
• Volatile Wiper 0
• Volatile Wiper 1
-502
5.0 k
Mid scale
Mid scale
Mid scale
Mid scale
80h 40h
80h 40h
80h 40h
80h 40h
• Volatile Wiper 2
-103
-503
-104
10.0 k
50.0 k
100.0 k
• Volatile Wiper 3
• Terminal Control (TCON0) Register 0
• Terminal Control (TCON)1 Register 1
TABLE 4-2:
Address
MEMORY MAP AND THE SUPPORTED COMMANDS
Memory
Factory
Initialization
Function
Allowed Commands Disallowed Commands (1)
Type
00h
01h
Volatile Wiper 0
Volatile Wiper 1
RAM
Read, Write,
Increment, Decrement
—
—
8-bit
80h
40h
80h
40h
7-bit
8-bit
7-bit
RAM
Read, Write,
Increment, Decrement
02h
03h
04h
Reserved
Reserved
—
—
None
None
All
—
—
All
Volatile
RAM
Read, Write
Increment, Decrement
1FFh
TCON0 Register
05h
06h
Reserved
—
None
All
—
—
Volatile Wiper 2
RAM
Read, Write,
Increment, Decrement
8-bit
80h
40h
80h
40h
7-bit
8-bit
7-bit
07h
Volatile Wiper 3
RAM
Read, Write,
Increment, Decrement
—
08h
09h
0Ah
Reserved
Reserved
—
—
None
None
All
—
—
All
Volatile
RAM
Read, Write
Increment, Decrement
1FFh
TCON1 Register
0Bh - 0Fh Reserved
—
None
All
—
Note 1: This command on this address will generate an error condition. To exit the error condition, the user must
take the HVC pin to the VIH level and then back to the active state (VIL or VIHH).
DS22267A-page 42
2010 Microchip Technology Inc.
MCP443X/5X
The value that is written to the specified TCON register
will appear on the appropriate resistor network
terminals when the serial command has completed.
On a POR/BOR these registers are loaded with
1FFh (9-bit), for all terminals connected. The Host
Controller needs to detect the POR/BOR event and
then update the Volatile TCON register values.
4.2.1.1
Terminal Control (TCON) Registers
There are two Terminal Control (TCON) Registers.
These are called TCON0 and TCON1. Each register
contains 8 control bits, four bits for each Wiper.
Register 4-1 describes each bit of the TCON0 register,
while Register 4-2 describes each bit of the TCON1
register.
The state of each resistor network terminal connection
is individually controlled. That is, each terminal
connection (A, B and W) can be individually connected/
disconnected from the resistor network. This allows the
system to minimize the currents through the digital
potentiometer.
REGISTER 4-1:
TCON0 BITS (1)
R-1
D8
R/W-1
R1HW
R/W-1
R/W-1
R1W
R/W-1
R1B
R/W-1
R0HW
R/W-1
R0A
R/W-1
R0W
R/W-1
R0B
R1A
bit 8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 8
bit 7
D8: Reserved. Forced to ‘1’
R1HW: Resistor 1 Hardware Configuration Control bit
This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin
1= Resistor 1 is NOT forced to the hardware pin “shutdown” configuration
0= Resistor 1 is forced to the hardware pin “shutdown” configuration
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network
1= P1A pin is connected to the Resistor 1 Network
0= P1A pin is disconnected from the Resistor 1 Network
R1W: Resistor 1 Wiper (P1W pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network
1= P1W pin is connected to the Resistor 1 Network
0= P1W pin is disconnected from the Resistor 1 Network
R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit
This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network
1= P1B pin is connected to the Resistor 1 Network
0= P1B pin is disconnected from the Resistor 1 Network
R0HW: Resistor 0 Hardware Configuration Control bit
This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin
1= Resistor 0 is NOT forced to the hardware pin “shutdown” configuration
0= Resistor 0 is forced to the hardware pin “shutdown” configuration
R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network
1= P0A pin is connected to the Resistor 0 Network
0= P0A pin is disconnected from the Resistor 0 Network
R0W: Resistor 0 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network
1= P0W pin is connected to the Resistor 0 Network
0= P0W pin is disconnected from the Resistor 0 Network
R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit
This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network
1= P0B pin is connected to the Resistor 0 Network
0= P0B pin is disconnected from the Resistor 0 Network
Note 1: These bits do not affect the wiper register values.
2010 Microchip Technology Inc.
DS22267A-page 43
MCP443X/5X
REGISTER 4-2:
TCON1 BITS (1)
R-1
D8
R/W-1
R3HW
R/W-1
R3A
R/W-1
R3W
R/W-1
R3B
R/W-1
R2HW
R/W-1
R2A
R/W-1
R2W
R/W-1
R2B
bit 8
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared x = Bit is unknown
bit 8
bit 7
D8: Reserved. Forced to ‘1’
R3HW: Resistor 3 Hardware Configuration Control bit
This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin
1= Resistor 3 is NOT forced to the hardware pin “shutdown” configuration
0= Resistor 3 is forced to the hardware pin “shutdown” configuration
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network
1= P3A pin is connected to the Resistor 3 Network
0= P3A pin is disconnected from the Resistor 3 Network
R3W: Resistor 3 Wiper (P3W pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network
1= P3W pin is connected to the Resistor 3 Network
0= P3W pin is disconnected from the Resistor 3 Network
R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit
This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network
1= P3B pin is connected to the Resistor 3 Network
0= P3B pin is disconnected from the Resistor 3 Network
R2HW: Resistor 2 Hardware Configuration Control bit
This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin
1= Resistor 2 is NOT forced to the hardware pin “shutdown” configuration
0= Resistor 2 is forced to the hardware pin “shutdown” configuration
R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network
1= P2A pin is connected to the Resistor 2 Network
0= P2A pin is disconnected from the Resistor 2 Network
R2W: Resistor 2 Wiper (P0W pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network
1= P2W pin is connected to the Resistor 2 Network
0= P2W pin is disconnected from the Resistor 2 Network
R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit
This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network
1= P2B pin is connected to the Resistor 2 Network
0= P2B pin is disconnected from the Resistor 2 Network
Note 1: These bits do not affect the wiper register values.
DS22267A-page 44
2010 Microchip Technology Inc.
MCP443X/5X
5.1
Resistor Ladder Module
5.0
RESISTOR NETWORK
The resistor ladder is a series of equal value resistors
(RS) with a connection point (tap) between the two
resistors. The total number of resistors in the series
(ladder) determines the RAB resistance (see Figure 5-
1). The end points of the resistor ladder are connected
to analog switches which are connected to the device
Terminal A and Terminal B pins. The RAB (and RS)
resistance has small variations over voltage and
temperature.
The Resistor Network has either 7-bit or 8-bit
resolution. Each Resistor Network allows zero scale to
full scale connections. Figure 5-1 shows a block
diagram for the resistive network of a device.
The Resistor Network is made up of several parts.
These include:
• Resistor Ladder
• Wiper
• Shutdown (Terminal Connections)
For an 8-bit device, there are 256 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 256 resistors, thus
providing 257 possible settings (including terminal A
and terminal B).
Devices have four resistor networks. These are
referred to as Pot 0, Pot 1 Pot 2, and Pot 3.
A
For a 7-bit device, there are 128 resistors in a string
between terminal A and terminal B. The wiper can be
set to tap onto any of these 128 resistors, thus
providing 129 possible settings (including terminal A
and terminal B).
8-Bit
N =
7-Bit
N =
128
256
(100h)
(80h)
(1)
RW
RS
RS
RS
Equation 5-1 shows the calculation for the step
resistance.
255
(FFh)
127
(7Fh)
(1)
(1)
RW
RW
EQUATION 5-1:
RS CALCULATION
254
(FEh)
126
(7Eh)
RAB
RS = --------------
8-bit Device
RAB
256
W
RAB
RS = --------------
7-bit Device
128
1
1
(01h)
(01h)
(1)
(1)
RW
RW
RS
0
0
(00h)
(00h)
Analog Mux
B
Note 1:The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B,
and W), and temperature.
Also for the same conditions, each tap
selection resistance has a small variation.
This RW variation has greater effects on
some specifications (such as INL) for the
smaller resistance devices (5.0 k)
compared to larger resistance devices
(100.0 k).
FIGURE 5-1:
Resistor Block Diagram.
2010 Microchip Technology Inc.
DS22267A-page 45
MCP443X/5X
5.2
Wiper
5.3
Shutdown
Shutdown is used to minimize the device’s current
consumption. The MCP44XX has one method to
achieve this. This is:
Each tap point (between the RS resistors) is a
connection point for an analog switch. The opposite
side of the analog switch is connected to a common
signal which is connected to the Terminal W (Wiper)
pin.
• Terminal Control Register (TCON)
This is different from the MCP42XXX devices in that the
Hardware Shutdown Pin (SHDN) has been replaced by
a RESET pin. The Hardware Shutdown Pin function is
still available via software commands to the TCON
register.
A value in the volatile wiper register selects which
analog switch to close, connecting the W terminal to
the selected node of the resistor ladder.
The wiper can connect directly to Terminal B or to
Terminal A. A zero scale connections, connects the
Terminal W (wiper) to Terminal B (wiper setting of
000h). A full scale connection, connects the Terminal W
(wiper) to Terminal A (wiper setting of 100h or 80h). In
these configurations, the only resistance between the
Terminal W and the other Terminal (A or B) is that of the
analog switches.
5.3.1
TERMINAL CONTROL REGISTER
(TCON)
The Terminal Control (TCON) register is a volatile
register used to configure the connection of each
resistor network terminal pin (A, B, and W) to the
Resistor Network. These registers are shown in
Register 4-1 and Register 4-2.
The RxHW bits forces the selected resistor network
into the same state as the MCP42X1’s SHDN pin.
Alternate low power configurations may be achieved
with the RxA, RxW, and RxB bits.
A wiper setting value greater than full scale (wiper
setting of 100h for 8-bit device or 80h for 7-bit devices)
will also be a Full Scale setting (Terminal W (wiper)
connected to Terminal A). Table 5-1 illustrates the full
wiper setting map.
When the RxHW bit is ‘0’:
• The P0A, P1A, P2A, and P3A terminals are
disconnected
• The P0W, P1W, P2W, and P3W terminals are
simultaneously connect to the P0B, P1B, P2B,
and P3B terminals, respectively (see Figure 5-2)
Equation 5-2 illustrates the calculation used to
determine the resistance between the wiper and
terminal B.
EQUATION 5-2:
RWB CALCULATION
Note:
When the RxHW bit forces the resistor
network into the hardware SHDN state,
the state of the TCON0 or TCON1
register’s RxA, RxW, and RxB bits is
overridden (ignored). When the state of
the RxHW bit no longer forces the resistor
network into the hardware SHDN state,
the TCON0 or TCON1 register’s RxA,
RxW, and RxB bits return to controlling the
terminal connection state. In other words,
the RxHW bit does not corrupt the state of
the RxA, RxW, and RxB bits.
RAB
N
RWB = -------------- + R W
8-bit Device
256
N = 0 to 256 (decimal)
RAB
N
7-bit Device
RWB = -------------- + R W
128
N = 0 to 128 (decimal)
TABLE 5-1:
Wiper Setting
VOLATILE WIPER VALUE VS.
WIPER POSITION MAP
The RxHW bit does NOT corrupt the values in the
Volatile Wiper Registers nor the TCON register. When
the Shutdown mode is exited (RxHW bit = 1):
• The device returns to the Wiper setting specified
by the Volatile Wiper value
Properties
7-bit
8-bit
3FFh – 3FFh – Reserved (Full Scale (W = A)),
081h
101h Increment and Decrement
commands ignored
• The TCON register bits return to controlling the
terminal connection state
080h
100h Full Scale (W = A),
Increment commands ignored
A
07Fh – 0FFh – W = N
041h
081h
W
040h
080h W = N (Mid Scale)
03Fh – 07Fh – W = N
001h
001h
000h
000h Zero Scale (W = B)
Decrement command ignored
B
FIGURE 5-2:
Resistor Network Shutdown
State (RxHW = ‘0’).
DS22267A-page 46
2010 Microchip Technology Inc.
MCP443X/5X
2
6.1
Signal Descriptions
6.0
SERIAL INTERFACE (I C)
The I2C interface uses up to four pins (signals). These
are:
The MCP44XX devices support the I2C serial protocol.
The MCP44XX I2C’s module operates in Slave mode
(does not generate the serial clock).
Figure 6-1 shows a typical I2C Interface connection. All
I2C interface signals are high-voltage tolerant.
• SDA (Serial Data)
• SCL (Serial Clock)
• A0 (Address 0 bit)
• A1 (Address 1 bit)
The MCP44XX devices use the two-wire I2C serial
interface. This interface can operate in standard, fast or
High-Speed mode. A device that sends data onto the
bus is defined as transmitter, and a device receiving
data as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions. The MCP44XX device works as
slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated. Communication is
initiated by the master (microcontroller) which sends
the START bit, followed by the slave address byte. The
first byte transmitted is always the slave address byte,
which contains the device code, the address bits, and
the R/W bit.
6.1.1
SERIAL DATA (SDA)
The Serial Data (SDA) signal is the data signal of the
device. The value on this pin is latched on the rising
edge of the SCL signal when the signal is an input.
With the exception of the START and STOP conditions,
the high or low state of the SDA pin can only change
when the clock signal on the SCL pin is low. During the
high period of the clock, the SDA pin’s value (high or
low) must be stable. Changes in the SDA pin’s value
while the SCL pin is HIGH will be interpreted as a
START or a STOP condition.
6.1.2
SERIAL CLOCK (SCL)
The Serial Clock (SCL) signal is the clock signal of the
device. The rising edge of the SCL signal latches the
value on the SDA pin. The MCP44XX supports three
I2C interface clock modes:
Refer to the NXP I2C document for more details of the
I2C specifications.
Typical I2C Interface Connections
• Standard Mode: clock rates up to 100 kHz
• Fast Mode: clock rates up to 400 kHz
• High-Speed Mode (HS mode): clock rates up to
3.4 MHz
MCP4XXX
SCL
Host
Controller
SCL
The MCP44XX will not stretch the clock signal (SCL)
since memory read access occur fast enough.
SDA
SDA
I/O (1)
HVC/A0 (2)
A1 (2, 3)
Depending on the clock rate mode, the interface will
display different characteristics.
6.1.3
THE ADDRESS BITS (A1:A0)
Note 1: If High voltage commands are desired,
some type of external circuitry needs to
be implemented.
There are up to two hardware pins used to specify the
device address. The number of address pins is
determined by the part number.
2: These pins have internal pull-ups. If
faster rise times are required, then
external pull-ups should be added.
Address 0 is multiplexed with the High Voltage
Command (HVC) function. So the state of A0 is latched
on the MCP4XXX’s POR/BOR event.
3: This pin could be tied high, low, or
connected to an I/O pin of the Host
Controller.
The state of the A1 pin should be static, that is they
should be tied high or tied low.
6.1.3.1
The High Voltage Command (HVC)
Signal
FIGURE 6-1:
Typical I2C Interface Block
Diagram.
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode. High Voltage commands are
supported for compatibility with non-volatile devices.
The HVC pin has an internal resistor connection to the
MCP44XXs internal VDD signal.
2010 Microchip Technology Inc.
DS22267A-page 47
MCP443X/5X
2
6.2.1.3
Acknowledge (A) Bit
6.2
I C Operation
The MCP44XX’s I2C module is compatible with the
NXP I2C specification. The following lists some of the
modules features:
The A bit (see Figure 6-4) is typically a response from
the receiving device to the transmitting device.
Depending on the context of the transfer sequence, the
A bit may indicate different things. Typically the Slave
device will supply an A response after the Start bit and
8 “data” bits have been received. an A bit has the SDA
signal low.
• 7-bit slave addressing
• Supports three clock rate modes:
- Standard mode, clock rates up to 100 kHz
- Fast mode, clock rates up to 400 kHz
- High-speed mode (HS mode), clock rates up
to 3.4 MHz
• Support Multi-Master Applications
• General call addressing
• Internal weak pull-ups on interface signals
SDA
SCL
D0
A
8
9
The I2C 10-bit addressing mode is not supported.
FIGURE 6-4:
Acknowledge Waveform.
The NXP I2C specification only defines the field types,
field lengths, timings, etc. of a frame. The frame con-
tent defines the behavior of the device. The frame con-
tent for the MCP44XX is defined in Section 7.0.
Not A (A) Response
The A bit has the SDA signal high. Table 6-1 shows
some of the conditions where the Slave Device will
issue a Not A (A).
6.2.1
I2C BIT STATES AND SEQUENCE
Figure 6-8 shows the I2C transfer sequence. The serial
clock is generated by the master. The following defini-
tions are used for the bit states:
If an error condition occurs (such as an A instead of A),
then an START bit must be issued to reset the
command state machine.
• Start bit (S)
• Data bit
• Acknowledge (A) bit (driven low) /
No Acknowledge (A) bit (not driven low)
• Repeated Start bit (Sr)
• Stop bit (P)
TABLE 6-1:
MCP45XX/MCP46XX A / A
RESPONSES
Acknowledge
Comment
Event
Bit Response
General Call
A
A
A
A
Only if GCEN bit is
set
6.2.1.1
Start Bit
The Start bit (see Figure 6-2) indicates the beginning of
a data transfer sequence. The Start bit is defined as the
SDA signal falling when the SCL signal is “High”.
Slave Address
valid
Slave Address
not valid
Device Memory
Address and
specified
After device has
received address
and command
2nd Bit
1st Bit
SDA
SCL
command
S
(AD3:AD0 and
C1:C0) are an
invalid
FIGURE 6-2:
Start Bit.
6.2.1.2 Data Bit
combination
The SDA signal may change state while the SCL signal
is Low. While the SCL signal is High, the SDA signal
MUST be stable (see Figure 6-5).
Communica-
tion during
EEPROM write
cycle
A
After device has
received address
and command,
and valid
conditions for
EEPROM write
I2C Module
Resets, or a “Don’t
Care” if the
2nd Bit
1st Bit
SDA
SCL
Bus Collision
N.A.
Data Bit
collision occurs on
the Master’s “Start
bit”
FIGURE 6-3:
Data Bit.
DS22267A-page 48
2010 Microchip Technology Inc.
MCP443X/5X
6.2.1.4
Repeated Start Bit
6.2.1.5
Stop Bit
The Repeated Start bit (see Figure 6-5) indicates the
current Master Device wishes to continue communicat-
ing with the current Slave Device without releasing the
I2C bus. The Repeated Start condition is the same as
the Start condition, except that the Repeated Start bit
follows a Start bit (with the Data bits + A bit) and not a
Stop bit.
The Stop bit (see Figure 6-6) Indicates the end of the
I2C Data Transfer Sequence. The Stop bit is defined as
the SDA signal rising when the SCL signal is “High”.
A Stop bit resets the I2C interface of all MCP44XX
devices.
A / A
The Start bit is the beginning of a data transfer
sequence and is defined as the SDA signal falling when
the SCL signal is “High”.
SDA
SCL
P
Note 1: A bus collision during the Repeated Start
condition occurs if:
FIGURE 6-6:
Stop Condition Receive or
Transmit Mode.
•SDA is sampled low when SCL goes
from low to high.
6.2.2
CLOCK STRETCHING
•SCL goes low before SDA is asserted
low. This may indicate that another
master is attempting to transmit a
data ‘1’.
“Clock Stretching” is something that the receiving
Device can do, to allow additional time to “respond” to
the “data” that has been received.
The MCP44XX will not stretch the clock signal (SCL)
since memory read access occur fast enough.
6.2.3
ABORTING A TRANSMISSION
1st Bit
SDA
SCL
If any part of the I2C transmission does not meet the
command format, it is aborted. This can be intentionally
accomplished with a START or STOP condition. This is
done so that noisy transmissions (usually an extra
START or STOP condition) are aborted before they
corrupt the device.
Sr = Repeated Start
FIGURE 6-5:
Repeat Start Condition
Waveform.
SDA
SCL
S
1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A / A
P
FIGURE 6-7:
Typical 8-Bit I2C Waveform Format.
SDA
SCL
Data allowed
to change
Data or
A valid
STOP
Condition
START
Condition
FIGURE 6-8:
I2C Data States and Bit Sequence.
2010 Microchip Technology Inc.
DS22267A-page 49
MCP443X/5X
6.2.4
ADDRESSING
Slave Address
The address byte is the first byte received following the
START condition from the master device. The address
contains four (or more) fixed bits and (up to) three user
defined hardware address bits (pins A1 and A0). These
7-bits address the desired I2C device. The A6:A2
address bits are fixed to ‘01011’ and the device
appends the value of following two address pins (A1
and A0).
S
A6 A5 A4 A3 A2 A1 A0 R/W
A/A
‘0’‘1’ ‘0’‘1’ ‘1’
See Table 6-2
Start
bit
R/W bit
R/W = 0= write
R/W = 1= read
A bit (controlled by slave device)
Since there are address bits controlled by hardware
pins, there may be up to four MCP44XX devices on the
same I2C bus.
A = 0= Slave Device Acknowledges byte
A = 1= Slave Device does not Acknowledge byte
FIGURE 6-9:
Slave Address Bits in the
Figure 6-9 shows the slave address byte format, which
contains the seven address bits. There is also a read/
write (R/W) bit. Table 6-2 shows the fixed address for
device.
I2C Control Byte.
TABLE 6-2:
DEVICESLAVE ADDRESSES
Device
Address Comment
MCP44XX ‘0101 1’b + A1:A0 Supports up to 4
devices. (Note 1)
Hardware Address Pins
Note 1: A0 is used for High-Voltage commands
(HVC/A0) and the value is latched at
POR/BOR.
The hardware address bits (A1, and A0) correspond to
the logic level on the associated address pins. This
allows up to eight devices on the bus.
These pins have a weak pull-up enabled when the VDD
< VBOR. The weak pull-up utilizes the “smart” pull-up
technology and exhibits the same characteristics as the
High-voltage tolerant I/O structure.
6.2.5
SLOPE CONTROL
The MCP44XX implements slope control on the SDA
output.
As the device transitions from HS mode to FS mode,
the slope control parameter will change from the HS
specification to the FS specification.
The state of the A0 address pin is latch on POR/BOR.
This is required since High Voltage commands force
this pin (HVC/A0) to the VIHH level.
For Fast (FS) and High-Speed (HS) modes, the device
has a spike suppression and a Schmidt trigger at SDA
and SCL inputs.
DS22267A-page 50
2010 Microchip Technology Inc.
MCP443X/5X
After switching to the High-Speed mode, the next
transferred byte is the I2C control byte, which specifies
the device to communicate with, and any number of
data bytes plus acknowledgements. The Master
Device can then either issue a Repeated Start bit to
address a different device (at High-Speed) or a Stop bit
to return to Fast/Standard bus speed. After the Stop bit,
any other Master Device (in a Multi-Master system) can
arbitrate for the I2C bus.
6.2.6
HS MODE
The I2C specification requires that a high-speed mode
device must be ‘activated’ to operate in high-speed
(3.4 Mbit/s) mode. This is done by the Master sending
a special address byte following the START bit. This
byte is referred to as the high-speed Master Mode
Code (HSMMC).
The MCP44XX device does not acknowledge this byte.
However, upon receiving this command, the device
switches to HS mode. The device can now
communicate at up to 3.4 Mbit/s on SDA and SCL
lines. The device will switch out of the HS mode on the
next STOP condition.
See Figure 6-10 for illustration of HS mode command
sequence.
For more information on the HS mode, or other I2C
modes, please refer to the I2C specification.
The master code is sent as follows:
1. START condition (S)
6.2.6.1
Slope Control
The slope control on the SDA output is different
between the Fast/Standard Speed and the High-Speed
clock modes of the interface.
2. High-Speed Master Mode Code (0000 1XXX),
The XXXbits are unique to the high-speed (HS)
mode Master.
6.2.6.2
Pulse Gobbler
3. No Acknowledge (A)
The pulse gobbler on the SCL pin is automatically
adjusted to suppress spikes < 10 ns during HS mode.
F/S-mode
HS-mode
P
F/S-mode
S ‘0 0 0 0 1 X X X’b A Sr ‘Slave Address’R/W A
“Data”
A/A
HS-mode continues
Sr ‘Slave Address’R/W A
HS Select Byte
Control Byte
Command/Data Byte(s)
Control Byte
S = Start bit
Sr = Repeated Start bit
A = Acknowledge bit
A = Not Acknowledge bit
R/W = Read/Write bit
P = Stop bit (Stop condition terminates HS Mode)
FIGURE 6-10: HS Mode Sequence.
2010 Microchip Technology Inc.
DS22267A-page 51
MCP443X/5X
6.2.7
GENERAL CALL
TABLE 6-3:
7-bit
GENERALCALLCOMMANDS
Comment
The General Call is a method by which the “Master”
device can communicate with all other “Slave” devices.
In a Multi-Master application, the other Master devices
are operating in Slave mode. The General Call address
has two documented formats. These are shown in
Figure 6-11. We have added a MCP44XX format in this
figure as well.
This will allow customers to have multiple I2C Digital
Potentiometers on the bus and have them operate in a
synchronous fashion (analogous to the DAC Sync pin
functionality). If these MCP44XX 7-bit commands
conflict with other I2C devices on the bus, then the
customer will need two I2C busses and ensure that the
devices are on the correct bus for their desired
application functionality.
Command
(1, 2, 3)
‘100000d’b Write Next Byte (Third Byte) to Volatile
Wiper 0 Register
‘100100d’b Write Next Byte (Third Byte) to Volatile
Wiper 1 Register
‘110000d’b Write Next Byte (Third Byte) to TCON
Register
‘1000010’b Increment Wiper 0 Register
or
‘1000011’b
‘1001010’b Increment Wiper 1 Register
or
Dual Pot devices can not update both Pot0 and Pot1
from a single command. To address this, there are
General Call commands for the Wiper 0, Wiper 1, and
the TCON registers.
‘1001011’b
‘1000100’b Decrement Wiper 0 Register
or
‘1000101’b
Table 6-3 shows the General Call Commands. Three
commands are specified by the I2C specification and
are not applicable to the MCP44XX (so command is
Not Acknowledged). The MCP44XX General Call
Commands are Acknowledged. Any other command is
Not Acknowledged.
‘1001100’b Decrement Wiper 1 Register
or
‘1001101’b
Note 1: Any other code is Not Acknowledged.
These codes may be used by other
devices on the I2C bus.
Note:
Only one General Call command per issue
of the General Call control byte. Any
additional General Call commands are
ignored and Not Acknowledged.
2: The 7-bit command always appends a ‘0’
to form 8-bits.
3: “d” is the D8 bit for the 9-bit write value.
DS22267A-page 52
2010 Microchip Technology Inc.
MCP443X/5X
Second Byte
S
0
0
0
0
0
0
0
0
A
X
X
X
X
X
X
X
0
A P
General Call Address
“7-bit Command”
Reserved 7-bit Commands (by I2C Specification - NXP UM10204_3, Version 03 19, June 2007)
‘0000 011’b - Reset and write programmable part of slave address by hardware.
‘0000 010’b - Write programmable part of slave address by hardware.
‘0000 000’b - NOT Allowed
MCP44XX 7-bit Commands
‘1000 01x’b - Increment Wiper 0 Register.
‘1001 01x’b - Increment Wiper 1 Register.
‘1000 10x’b - Decrement Wiper 0 Register.
‘1001 10x’b - Decrement Wiper 1 Register.
The Following is a Microchip Extension to this General Call Format
Third Byte
Second Byte
S
0
0
0
0
0
0
0
0
A
X
X
X
X
X
X
d
0
A d
d
d
d
d
d
d
d A P
General Call Address
MCP44XX 7-bit Commands
“7-bit Command”
‘0’ for General Call Command
‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register.
‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register.
‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register.
The Following is a “Hardware General Call” Format
n occurrences of (Data + A)
A X X X X X X X X A P
Second Byte
S
0
0
0
0
0
0
0
0
A
X
X
X
X
X
X
X
1
General Call Address
“7-bit Command”
This indicates a “Hardware General Call”
MCP44XX will ignore this byte and
all following bytes (and A), until
a Stop bit (P) is encountered.
FIGURE 6-11:
General Call Formats.
2010 Microchip Technology Inc.
DS22267A-page 53
MCP443X/5X
NOTES:
DS22267A-page 54
2010 Microchip Technology Inc.
MCP443X/5X
7.1
Command Byte
7.0
DEVICE COMMANDS
The MCP44XX’s I2C command formats are specified in
this section. The I2C protocol does not specify how
commands are formatted.
The MCP44XX’s Command Byte has three fields: the
Address, the Command Operation, and 2 Data bits
(see Figure 7-1). Currently only one of the data bits is
defined (D8).
The MCP44XX supports four basic commands. The
location accessed determines the commands that are
supported.
The device memory is accessed when the Master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD3:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits, see Figure 7-1. C1:C0 determines if the
desired memory location will be read, written,
Incremented (wiper setting +1) or Decremented (wiper
setting -1). The Increment and Decrement commands
are only valid on the volatile wiper registers, and in
High Voltage commands to enable/disable WiperLock
Technology and Software Write Protect.
For the Volatile Wiper Registers, these commands are:
• Write Data
• Read Data
• Increment Data
• Decrement Data
For the TCON Register, these commands are:
• Write Data
• Read Data
These commands have formats for both a single
command or continuous commands. These commands
are shown in Table 7-1.
If the Address bits and Command bits are not a valid
combination, then the MCP44XX will generate a Not
Acknowledge pulse to indicate the invalid combination.
The I2C Master device must then force a Start
Condition to reset the MCP44XX’s I2C module.
Each command has two operational states. These
operational states are referred to as:
• Normal Serial Commands
• High-Voltage Serial Commands
D9 and D8 are the most significant bits for the digital
potentiometer’s wiper setting. The 8-bit devices utilize
D8 as their MSb while the 7-bit devices utilize D7 (from
the data byte) as their MSb.
Note:
High Voltage commands are supported for
compatibility with Non-Volatile devices in
the family.
COMMAND BYTE
TABLE 7-1:
I2C COMMANDS
Mode
A
A
D
3
A
D
2
A
D
1
A
D
0
C
1
C
0
D
9
D
8
A
Command
# of Bit Clocks
(1)
Operation
Write Data
Single
29
18n + 11
29
MSbits (Data)
MCP4XXX
Memory Address
Continuous
Single
Command Operation bits
Read Data
00= Write Data
01= Increment
10= Decrement
11= Read Data
Random
Continuous
Single
48
18n + 11
20
Increment
Decrement
Continuous
Single
9n + 11
20
FIGURE 7-1:
Command Byte Format.
Continuous
9n + 11
Note 1: “n” indicates the number of times the
command operation is to be repeated.
Normal serial commands are those where the HVC pin
is driven to VIH or VIL. With High-Voltage Serial
Commands, the HVC pin is driven to VIHH. In each
mode, there are four possible commands.
Table 7-2 shows the supported commands for each
memory location.
Table 7-3 shows an overview of all the device
commands and their interaction with other device
features.
2010 Microchip Technology Inc.
DS22267A-page 55
MCP443X/5X
TABLE 7-2:
MEMORY MAP AND THE SUPPORTED COMMANDS
Address
Data
(10-bits)
Command
Comment
(1)
Value
Function
Write Data
Read Data
nn nnnn nnnn
00h
Volatile Wiper 0
3
(
)
nn nnnn nnnn
Increment Wiper
Decrement Wiper
Write Data
—
—
nn nnnn nnnn
01h
Volatile Wiper 1
3
(
)
Read Data
nn nnnn nnnn
Increment Wiper
—
Decrement Wiper
—
—
—
—
02h
03h
Reserved
Reserved
—
(2)
Write Data
nn nnnn nnnn
nn nnnn nnnn
—
04h
Volatile
TCON 0 Register
3
(
)
Read Data
Read Data
(3)
(2)
—
Maps to Non-Volatile MCP444x/6x device’s
STATUS Register
05h
Write Data
Read Data
nn nnnn nnnn
06h
07h
Volatile Wiper 2
3
(
)
nn nnnn nnnn
Increment Wiper
Decrement Wiper
Write Data
—
—
nn nnnn nnnn
Volatile Wiper 3
3
(
)
Read Data
nn nnnn nnnn
Increment Wiper
—
Decrement Wiper
—
—
—
—
08h
09h
Reserved
Reserved
—
(2)
Write Data
nn nnnn nnnn
nn nnnn nnnn
—
0Ah
Volatile
TCON 1 Register
3
(
)
Read Data
—
0Bh - 0Fh Reserved
Note 1:
The Data Memory is only 9-bits wide, so the MSb is ignored by the device.
Increment or Decrement commands are invalid for these addresses.
2:
3:
I2C read operation will read 2 bytes, of which the 10-bits of data are contained within.
DS22267A-page 56
2010 Microchip Technology Inc.
MCP443X/5X
7.2
Data Byte
7.3
Error Condition
Only the Read Command and the Write Command
have Data Byte(s).
If the four address bits received (AD3:AD0), and the
two command bits received (C1:C0), are a valid
combination, the MCP44XX will Acknowledge the I2C
bus.
The Write command concatenates the 8 bits of the
Data Byte with the one data bit (D8) contained in the
Command Byte to form 9 bits of data (D8:D0). The
Command Byte format supports up to 9 bits of data so
that the 8-bit resistor network can be set to Full-Scale
(100h or greater). This allows wiper connections to
Terminal A and to Terminal B. The D9 bit is currently
unused.
If the address bits and command bits are an invalid
combination, then the MCP44XX will Not Acknowledge
the I2C bus.
When an error condition has occurred, any commands
that follow are ignored until the I2C bus is reset with a
Start Condition.
7.3.1
ABORTING A TRANSMISSION
A Restart or Stop condition in the expected data bit
position will abort the current command sequence and
data will not be written to the MCP44XX.
TABLE 7-3:
COMMANDS
High
Voltage
(VIHH) on
Command Name
# of Bits
HVC pin?
Write Data
29
29
20
20
29
29
20
20
—
—
Read Data
Increment Wiper
—
Decrement Wiper
—
High Voltage Write Data
High Voltage Read Data
High Voltage Increment Wiper
High Voltage Decrement Wiper
Yes
Yes
Yes
Yes
2010 Microchip Technology Inc.
DS22267A-page 57
MCP443X/5X
7.4.2
CONTINUOUS WRITES TO
VOLATILE MEMORY
7.4
Write Data
Normal and High Voltage
A continuous write mode of operation is possible when
writing to the volatile memory registers (address 00h,
01h, 04h, 06h, 07h, and 0Ah). This continuous write
mode allows writes without a Stop or Restart condition
or repeated transmissions of the I2C Control Byte.
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same volatile
memory address. The sequence ends with the master
sending a STOP or RESTART condition.
The Write Command format, see Figure 7-2, includes
the I2C Control Byte, an A bit, the MCP44XX Command
Byte, an A bit, the MCP44XX Data Byte, an A bit, and
a Stop (or Restart) condition. The MCP44XX generates
the A / A bits.
A Write command to a Volatile memory location
changes that location after a properly formatted Write
Command and the A / A clock have been received.
7.4.1
SINGLE WRITE TO VOLATILE
MEMORY
7.4.3
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
For volatile memory locations, data is written to the
MCP44XX after every byte transfer (during the
Acknowledge). If a Stop or Restart condition is
generated during a data transfer (before the A), the
data will not be written to the MCP44XX. After the A bit,
the master can initiate the next sequence with a Stop or
Restart condition.
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage operational state.
The HVC pin has an internal resistor connection to the
MCP44XXs internal VDD signal.
Refer to Figure 7-2 for the byte write sequence.
DS22267A-page 58
2010 Microchip Technology Inc.
MCP443X/5X
Write bit
Variable
Address
Device
Memory
Address
Fixed
Address
Write “Data” bits
Command
AD AD AD AD
S
0
1
0
1
1 A1 A0 0
A
0
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P
3
2
1
0
WRITE Command
Write Data bits
Control Byte
FIGURE 7-2:
I2C Write Sequence.
Write bit
Variable
Address
Device
Memory
Address
Fixed
Address
Write “Data” bits
Command
AD AD AD AD
S
0
1
0
1
1 A1 A0 0
A
0
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
3
2
1
0
WRITE Command Write Data bits
Control Byte
AD AD AD AD
0
0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
3
2
1
0
WRITE Command
Write Data bits
STOP bit
AD AD AD AD
0
0
x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A
P
3
2
1
0
WRITE Command Write Data bits
Note: Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and
07h) or the TCON registers (AD3:AD0 = 04h and 0Ah)
FIGURE 7-3:
I2C Continuous Volatile Wiper Write.
2010 Microchip Technology Inc.
DS22267A-page 59
MCP443X/5X
7.5.1
SINGLE READ
7.5
Read Data
Normal and High Voltage
Figure 7-4 show the waveforms for a single read.
For single reads the master sends a STOP or
RESTART condition after the data byte is sent from the
slave.
The Read Command format (see Figure 7-4), includes
the Start condition, I2C Control Byte (with R/W bit set to
‘0’), A bit, MCP44XX Command Byte, A bit, followed by
a Repeated Start bit, I2C Control Byte (with R/W bit set
to ‘1’), and the MCP44XX transmitting the requested
Data High Byte, and A bit, the Data Low Byte, the
Master generating the A, and Stop condition.
The I2C Control Byte requires the R/W bit equal to a
logic one (R/W = 1) to generate a read sequence. The
memory location read will be the last address
contained in a valid write MCP44XX Command Byte or
address 00h if no write operations have occurred since
the device was reset (Power-on Reset or Brown-out
Reset).
7.5.1.1
Random Read
Figure 7-5 shows the sequence for a Random Reads.
Refer to Figure 7-5 for the random byte read
sequence.
7.5.2
CONTINUOUS READS
Continuous reads allows the devices memory to be
read quickly. Continuous reads are possible to all
memory locations.
Figure 7-6 shows the sequence for three continuous
reads.
Read operations initially include the same address byte
sequence as the write sequence (shown in Figure 6-9).
This sequence is followed by another control byte
(including the Start condition and Acknowledge) with
the R/W bit equal to a logic one (R/W = 1) to indicate a
read. The MCP44XX will then transmit the data
contained in the addressed register. This is followed by
the master generating an A bit in preparation for more
data, or an A bit followed by a Stop. The sequence is
ended with the master generating a Stop or Restart
condition.
For continuous reads, instead of transmitting a Stop
or Restart condition after the data transfer, the master
reads the next data byte. The sequence ends with the
master Not Acknowledging and then sending a Stop or
Restart.
7.5.3
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode.
The internal address pointer is maintained.
The HVC pin has an internal resistor connection to the
MCP44XX’s internal VDD signal.
7.5.4
IGNORING AN I2C TRANSMISSION
AND “FALLING OFF” THE BUS
The MCP44XX expects to receive complete, valid I2C
commands and will assume any command not defined
as a valid command is due to a bus corruption and will
enter a passive high condition on the SDA signal. All
signals will be ignored until the next valid Start
condition and Control Byte are received.
DS22267A-page 60
2010 Microchip Technology Inc.
MCP443X/5X
Read bit
STOP bit
Variable
Address
Fixed
Address
Read Data bits
S
0
1
0
1
1 A1 A0 1 A 0
0
0
0 0
0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2
Read bits
P
Control Byte
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this
transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
3: The MCP44XX retains the last “Device Memory Address” that it has received. This is the
MCP44XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop
conditions.
4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.
FIGURE 7-4:
I2C Read (Last Memory Address Accessed).
Write bit
Device
Repeated Start bit
Variable
Address
Fixed
Address
Memory
Address
Command
AD AD AD AD
S
0
1
0
1
1 A1 A0 0
A
1
1
x X A Sr
3
2
1
0
READ Command
Control Byte
STOP bit
Read bit
Read Data bits
0
1
0
1
1 A1 A0 1 A 0
0
0
0 0
0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2
P
Control Byte
Read bits
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this
transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Mas-
ter Device can generate a Stop or Repeated Start condition.
3: The MCP44XX retains the last “Device Memory Address” that it has received. This is the
MCP44XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop
conditions.
FIGURE 7-5:
I2C Random Read.
2010 Microchip Technology Inc.
DS22267A-page 61
MCP443X/5X
Read bit
Variable
Address
Fixed
Address
Read Data bits
S
0
1
0
1
1 A1 A0 1
A
0
0
0
0
0
0
0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1
Read bits
Control Byte
Read Data bits
0
0
0
0 0
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A1
STOP bit
Read Data bits
0 D8 A1 D7 D6 D5 D4 D3 D2 D1 D0 A2
0
0
0
0 0
0
P
Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this
transfer and release the bus.
2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the
Master Device can generate a Stop or Repeated Start condition.
FIGURE 7-6:
I2C Continuous Reads.
DS22267A-page 62
2010 Microchip Technology Inc.
MCP443X/5X
TABLE 7-4:
INCREMENT OPERATION VS.
VOLATILE WIPER VALUE
7.6
Increment Wiper
Normal and High Voltage
Current Wiper
Setting
The Increment Command provides a quick and easy
method to modify the potentiometer’s wiper by +1 with
minimal overhead. The Increment Command will only
function on the volatile wiper setting memory locations
00h, 01h, 06h and 07h.
Increment
Wiper (W)
Command
Properties
7-bit
Pot
8-bit
Pot
Operates?
3FFh
081h
3FFh Reserved
101h (Full-Scale (W = A))
No
Note:
Table 7-4 shows the valid addresses for
the Increment Wiper command. Other
addresses are invalid.
080h
100h Full-Scale (W = A) No
07Fh
041h
0FFh W = N
081
When executing an Increment Command, the volatile
wiper setting will be altered from n to n+1 for each
Increment Command received. The value will
increment up to 100h max on 8-bit devices and 80h on
7-bit devices. If multiple Increment Commands are
received after the value has reached 100h (or 80h), the
value will not be incremented further. Table 7-4 shows
the Increment Command versus the current volatile
wiper value.
040h
080h W = N (Mid-Scale) Yes
03Fh
001h
07Fh W = N
001
000h
000h Zero Scale (W = B) Yes
7.6.1
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The Increment Command will most commonly be
performed on the Volatile Wiper locations until a
desired condition is met. The MCP44XX is responsible
for generating the A bits.
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode. Signals > VIHH (~8.5V) on the
HVC/A0 pin puts MCP44XX devices into High Voltage
mode.
Refer to Figure 7-7 for the Increment Command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Increment command can be followed by any
other valid command. This means that writes do not
need to be to the same volatile memory address.
Note:
There is a required delay after the HVC pin
is driven to the VIHH level to the 1st edge
of the SCL pin.
The HVC pin has an internal resistor connection to the
MCP44XX’s internal VDD signal.
Note:
The command sequence can go from an
increment to any other valid command for
the specified address.
The advantage of using an Increment Command
instead of a read-modify-write series of commands is
speed and simplicity. The wiper will transition after each
Command Acknowledge when accessing the volatile
wiper registers.
Write bit
Variable
Address
Device
Memory
Address
Fixed
Address
Command
AD AD AD AD
AD AD AD AD
(2)
S
0
1
0
1
1 A1 A0 0
A
0
1 x
X
A
0
1 x
X A P
3
2
1
0
4
3
2
1
INCR Command (n+1)
INCR Command (n+2)
Control Byte
Note1: Increment Command (INCR) only functions when accessing the volatile wiper
registers (AD3:AD0 = 00h, 01h, 06h, and 07h).
2: This command sequence does not need to terminate (using the Stop bit) and can
change to any other desired command sequence (Increment, Read, or Write).
FIGURE 7-7:
I2C Increment Command Sequence.
2010 Microchip Technology Inc.
DS22267A-page 63
MCP443X/5X
TABLE 7-5:
DECREMENT OPERATION VS.
VOLATILE WIPER VALUE
7.7
Decrement Wiper
Normal and High Voltage
Current Wiper
Setting
The Decrement Command provides a quick and easy
method to modify the potentiometer’s wiper by -1 with
minimal overhead. The Decrement Command will only
function on the volatile wiper setting memory locations
00h and 01h.
Decrement
Wiper (W)
Command
Properties
7-bit
Pot
8-bit
Pot
Operates?
3FFh
081h
3FFh Reserved
101h (Full-Scale (W = A))
No
Note:
Table 7-5 shows the valid addresses for
the Decrement Wiper command. Other
addresses are invalid.
080h
100h Full-Scale (W = A) Yes
07Fh
041h
0FFh W = N
081
When executing a Decrement Command, the volatile
wiper setting will be altered from n to n-1 for each
Decrement Command received. The value will
decrement down to 000h min. If multiple Decrement
Commands are received after the value has reached
000h, the value will not be decremented further.
Table 7-5 shows the Increment Command versus the
current volatile wiper value.
040h
080h W = N (Mid-Scale) Yes
03Fh
001h
07Fh W = N
001
000h
000h Zero Scale (W = B) No
7.7.1
THE HIGH VOLTAGE COMMAND
(HVC) SIGNAL
The Decrement Command will most commonly be
performed on the Volatile Wiper locations until a
desired condition is met. The MCP44XX is responsible
for generating the A bits.
The High Voltage Command (HVC) signal is
multiplexed with Address 0 (A0) and is used to indicate
that the command, or sequence of commands, are in
the High Voltage mode. Signals > VIHH (~8.5V) on the
HVC/A0 pin puts MCP44XX devices into High Voltage
mode.
Refer to Figure 7-8 for the Decrement Command
sequence. The sequence is terminated by the Stop
condition. So when executing a continuous command
string, the Increment command can be followed by any
other valid command. This means that writes do not
need to be to the same volatile memory address.
Note:
There is a required delay after the HVC pin
is driven to the VIHH level to the 1st edge
of the SCL pin.
The HVC pin has an internal resistor connection to the
MCP44XX’s internal VDD signal.
Note:
The command sequence can go from an
increment to any other valid command for
the specified address.
The advantage of using a Decrement Command
instead of a read-modify-write series of commands is
speed and simplicity. The wiper will transition after each
Command Acknowledge when accessing the volatile
wiper registers.
Write bit
Variable
Address
Device
Memory
Address
Fixed
Address
Command
AD AD AD AD
AD AD AD AD
S
0
1
0
1
1 A1 A0 0
A
1
0 X
X
A
1
0 X
X A
P (2)
3
2
1
0
4
3
2
1
DECR Command (n-1)
DECR Command (n-2)
Control Byte
Note1: Decrement Command (DECR) only functions when accessing the volatile wiper
registers (AD3:AD0 = 00h, 01h, 06h, and 07h).
2: This command sequence does not need to terminate (using the Stop bit) and can
change to any other desired command sequence (INCR, Read, or Write).
FIGURE 7-8:
I2C Decrement Command Sequence.
DS22267A-page 64
2010 Microchip Technology Inc.
MCP443X/5X
The circuit in Figure 8-2 shows the method used on the
MCP402X Nonvolatile Digital Potentiometer Evaluation
Board (Part Number: MCP402XEV). This method
requires that the system voltage be approximately 5V.
This ensures that when the PIC10F206 enters a brown-
out condition, there is an insufficient voltage level on
the HVC/A0 pin to change the stored value of the wiper.
The MCP402X Nonvolatile Digital Potentiometer Eval-
uation Board User’s Guide (DS51546) contains a
complete schematic.
8.0
APPLICATIONS EXAMPLES
Nonvolatile digital potentiometers have a multitude of
practical uses in modern electronic circuits. The most
popular uses include precision calibration of set point
thresholds, sensor trimming, LCD bias trimming, audio
attenuation, adjustable power supplies, motor control
overcurrent trip setting, adjustable gain amplifiers and
offset trimming. The MCP44XX devices can be used to
replace the common mechanical trim pot in
applications where the operating and terminal voltages
are within CMOS process limitations (VDD = 2.7V to
5.5V).
GP0 is a general purpose I/O pin, while GP2 can either
be a general purpose I/O pin or it can output the internal
clock.
For the serial commands, configure the GP2 pin as an
input (high impedance). The output state of the GP0 pin
will determine the voltage on the HVC/A0 pin (VIL or
VIH).
8.1
Techniques to Force the HVC/A0
Pin to V
IHH
The circuit in Figure 8-1 shows a method using the
TC1240A doubling charge pump. When the SHDN pin
is high, the TC1240A is off, and the level on the HVC/
A0 pin is controlled by the PIC® microcontrollers
(MCUs) IO2 pin.
For high-voltage serial commands, force the GP0
output pin to output a high level (VOH) and configure the
GP2 pin to output the internal clock. This will form a
charge pump and increase the voltage on the CS pin
(when the system voltage is approximately 5V).
When the SHDN pin is low, the TC1240A is on and the
VOUT voltage is 2 * VDD. The resistor R1 allows the
HVC/A0 pin to go higher than the voltage such that the
PIC MCU’s IO2 pin “clamps” at approximately VDD
.
PIC10F206
R1
GP0
TC1240A
VIN
MCP4XXX
C+
PIC MCU
C1
C-
SHDN
GP2
HVC/A0
VOUT
IO1
C1
C2
MCP4XXX
R1
HVC/A0
C2
IO2
FIGURE 8-2:
MCP4XXX Nonvolatile
Digital Potentiometer Evaluation Board
(MCP402XEV) implementation to generate the
VIHH voltage.
FIGURE 8-1:
Using the TC1240A to
Generate the VIHH Voltage.
2010 Microchip Technology Inc.
DS22267A-page 65
MCP443X/5X
8.2
Using Shutdown Modes
8.3
Software Reset Sequence
Figure 8-3 shows a possible application circuit where
the independent terminals could be used.
Disconnecting the wiper allows the transistor input to
be taken to the Bias voltage level (disconnecting A and
or B may be desired to reduce system current).
Disconnecting Terminal A modifies the transistor input
by the RBW rheostat value to the Common B.
Disconnecting Terminal B modifies the transistor input
by the RAW rheostat value to the Common A. The
Common A and Common B connections could be
Note:
This technique is documented in AN1028.
At times, it may become necessary to perform a
Software Reset Sequence to ensure the MCP44XX
device is in a correct and known I2C Interface state.
This technique only resets the I2C state machine.
This is useful if the MCP44XX device powers up in an
incorrect state (due to excessive bus noise, etc), or if
the Master Device is reset during communication.
Figure 8-4 shows the communication sequence to
software reset the device.
connected to VDD and VSS
.
S
‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’
S
P
Common A
Nine bits of ‘1’
Start bit
Start
bit
Input
Stop bit
A
FIGURE 8-4:
Software Reset Sequence
Format.
The 1st Start bit will cause the device to reset from a
state in which it is expecting to receive data from the
Master Device. In this mode, the device is monitoring
the data bus in Receive mode and can detect the Start
bit forces an internal Reset.
To base
of Transistor
(or Amplifier)
W
The nine bits of ‘1’ are used to force a Reset of those
devices that could not be reset by the previous Start bit.
This occurs only if the MCP44XX is driving an A bit on
the I2C bus, or is in output mode (from a Read
command) and is driving a data bit of ‘0’ onto the I2C
bus. In both of these cases, the previous Start bit could
not be generated due to the MCP44XX holding the bus
low. By sending out nine ‘1’ bits, it is ensured that the
device will see a A bit (the Master Device does not drive
the I2C bus low to acknowledge the data sent by the
MCP44XX), which also forces the MCP44XX to Reset.
B
Input
Common B
Balance
Bias
Example Application Circuit
FIGURE 8-3:
The 2nd Start bit is sent to address the rare possibility
of an erroneous write. This could occur if the Master
Device was reset while sending a Write command to
the MCP44XX, AND then as the Master Device returns
to normal operation and issues a Start condition while
the MCP44XX is issuing an Acknowledge. In this case,
if the 2nd Start bit is not sent (and the Stop bit was sent)
the MCP44XX could initiate a write cycle.
using Terminal Disconnects.
Note:
The potential for this erroneous write
ONLY occurs if the Master Device is reset
while sending a Write command to the
MCP44XX.
The Stop bit terminates the current I2C bus activity. The
MCP44XX waits to detect the next Start condition.
This sequence does not effect any other I2C devices
which may be on the bus, as they should disregard this
as an invalid command.
DS22267A-page 66
2010 Microchip Technology Inc.
MCP443X/5X
Figure 8-5 shows two I2C bus configurations. In many
cases, the single I2C bus configuration will be
adequate. For applications that do not want all the
MCP44XX devices to do General Call support or have
a conflict with General Call commands, the multiple I2C
bus configuration would be used.
8.4
Using the General Call Command
The use of the General Call Address Increment,
Decrement, or Write commands is analogous to the
“Load” feature (LDAC pin) on some DACs (such as the
MCP4921). This allows all the devices to “Update” the
output level “at the same time”.
For some applications, the ability to update the wiper
values “at the same time” may be a requirement, since
they delay from writing to one wiper value and then the
next may cause application issues. A possible example
would be a “tuned” circuit that uses several MCP44XX
in rheostat configuration. As the system condition
changes (temperature, load, etc.) these devices need
to be changed (incremented/decremented) to adjust for
the system change. These changes will either be in the
same direction or in opposite directions. With the
Potentiometer device, the customer can either select
the PxB terminals (same direction) or the PxA
terminal(s) (opposite direction).
Single I2C Bus Configuration
Device 1
Device n
Device 3
Host
Controller
Device 4
Device 2
Multiple I2C Bus Configuration
Device 1a
Bus a
Device na
Device 3a
Host
Figure 8-6 shows that the update of six devices takes
6*TI2CDLY time in “normal” operation, but only
1*TI2CDLY time in “General Call” operation.
Controller
Device 4a
Device 3b
Device 2a
Device 1b
Note:
The application system may need to
partition the I2C bus into multiple busses to
ensure that the MCP44XX General Call
commands do not conflict with the General
Call commands that the other I2C devices
may have defined. Also if only a portion of
the MCP44XX devices are to require this
synchronous operation, then the devices
that should not receive these commands
should be on the second I2C bus.
Device nb
Device nn
Bus b
Device 4b
Device 3n
Device 2b
Device 1n
Bus n
Device 4n
Device 2n
FIGURE 8-5:
Typical Application I2C Bus
Configurations.
Normal Operation
INC
INC
POT02
INC
POT03
INC
POT04
INC
POT05
INC
POT06
POT01
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
General Call Operation
INC
INC
INC
INC
INC
INC
POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
TI2CDLY
I2CDLY = Time from one I2C command completed to completing the next I2C command.
T
FIGURE 8-6:
Example Comparison of “Normal Operation” vs. “General Call Operation” Wiper
Updates.
2010 Microchip Technology Inc.
DS22267A-page 67
MCP443X/5X
EQUATION 8-1:
dB CALCULATIONS
(VOLTAGE)
8.5
Implementing Log Steps with a
Linear Digital Potentiometer
L = 20 * log10 (VOUT / VIN)
In audio volume control applications, the use of
logarithmic steps is desirable since the human ear
hears in a logarithmic manner. The use of a linear
potentiometer can approximate a log potentiometer,
but with fewer steps. An 8-bit potentiometer can
achieve fourteen 3 dB log steps plus a 100% (0 dB)
and a mute setting.
dB
VOUT / VIN Ratio
-3
-2
-1
0.70795
0.79433
0.89125
Figure 8-7 shows a block diagram of one of the
MCP44x1 resistor networks being used to attenuate an
input signal. In this case, the attenuation will be ground
referenced. Terminal B can be connected to a common
mode voltage, but the voltages on the A, B and Wiper
terminals must not exceed the MCP44x1’s VDD/VSS
voltage limits.
EQUATION 8-2:
dB CALCULATIONS
(RESISTANCE) - CASE 1
Terminal B connected to Ground (see Figure 8-7)
L = 20 * log10 (RBW / RAB
)
MCP44X1
EQUATION 8-3:
dB CALCULATIONS
(RESISTANCE) - CASE 2
P0A
Terminal B through RB2GND to Ground
P0W
P0B
L = 20 * log10 ( (RBW + RB2GND) / (RAB + RB2GND) )
Table 8-1 shows the codes that can be used for 8-bit
digital potentiometers to implement the log attenuation.
The table shows the wiper codes for -3 dB, -2 dB, and
-1 dB attenuation steps. This table also shows the
calculated attenuation based on the wiper code’s linear
step. Calculated attenuation values less than the
desired attenuation are shown with red text. At lower
wiper code values, the attenuation may skip a step, if
this occurs the next attenuation value is colored
magenta to highlight that a skip occurred. For example,
in the -3 dB column the -48 dB value is highlighted
since the -45 dB step could not be implemented (there
are no wiper codes between 2 and 1).
FIGURE 8-7:
Diagram - Ground Referenced.
Signal Attenuation Block
Equation 8-1 shows the equation to calculate voltage
dB gain ratios for the digital potentiometer, while
Equation 8-2 shows the equation to calculate
resistance dB gain ratios. These two equations assume
that the B terminal is connected to ground.
If terminal B is not directly resistively connected to
ground, then this terminal B to ground resistance
(RB2GND) must be included into the calculation.
Equation 8-3 shows this equation.
DS22267A-page 68
2010 Microchip Technology Inc.
MCP443X/5X
TABLE 8-1:
# of
LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS
-3 dB Steps -2 dB Steps -1 dB Steps
Calculated Calculated
Calculated
Desired
Wiper
Desired
Wiper
Desired
Wiper
Steps
Attenuation
Attenuation
Attenuation
Attenuation Code
Attenuation Code
Attenuation Code
(1)
(1)
(1)
0
0 dB
256
0 dB
0 dB
256
0 dB
0 dB
256
0 dB
1
-3 dB
181 -3.011 dB
128 -6.021 dB
91 -8.984 dB
64 -12.041 dB
46 -14.910 dB
32 -18.062 dB
23 -20.930 dB
16 -24.082 dB
11 -27.337 dB
-2 dB
203 -2.015 dB
162 -3.975 dB
128 -6.021 dB
102 -7.993 dB
81 -9.995 dB
64 -12.041 dB
51 -14.013 dB
41 -15.909 dB
32 -18.062 dB
26 -19.865 dB
20 -22.144 dB
16 -24.082 dB
13 -25.886 dB
10 -28.165 dB
-1 dB
228 -1.006 dB
203 -2.015 dB
181 -3.011 dB
162 -3.975 dB
144 -4.998 dB
128 -6.021 dB
114 -7.027 dB
102 -7.993 dB
91 -8.984 dB
81 -9.995 dB
72 -11.018 dB
64 -12.041 dB
57 -13.047 dB
51 -14.013 dB
46 - 14.910 dB
41 -15.909 dB
36 -17.039 dB
32 -18.062 dB
29 -18.917 dB
26 -19.865 dB
23 - 20.930 dB
20 -22.144 dB
18 -23.059 dB
16 -24.082 dB
14 -25.242 dB
13 -25.886 dB
11 -27.337 dB
10 -28.165 dB
2
-6 dB
-4 dB
-2 dB
3
-9dB
-6 dB
-3 dB
4
-12 dB
-15 dB
-18 dB
-21 dB
-24 dB
-27 dB
-30 dB
-33 dB
-36 dB
-39 dB
-42 dB
-48 dB
Mute
-8 dB
-4 dB
5
-10 dB
-12 dB
-14 dB
-16 dB
-18 dB
-20 dB
-22 dB
-24 dB
-26 dB
-28 dB
-30 dB
-32 dB
-34 dB
-36 dB
-38 dB
-42 dB
-48 dB
Mute
-5 dB
6
-6 dB
7
-7 dB
8
-8 dB
9
-9 dB
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
8
6
4
3
2
1
0
-30.103 dB
-32.602 dB
-36.124 dB
-38.622 dB
-42.144 dB
-48.165 dB
Mute
-10 dB
-11 dB
-12 dB
-13 dB
-14 dB
-15 dB
-16 dB
-17 dB
-18 dB
-19 dB
-20 dB
-21 dB
-22 dB
-23 dB
-24 dB
-25 dB
-26 dB
-27dB
-28 dB
-29 dB
-30 dB
-31 dB
-33 dB
-34 dB
-36 dB
-39 dB
-42 dB
-48 dB
Mute
8
6
5
4
3
2
1
0
-30.103 dB
-32.602 dB
-34.185 dB
-36.124 dB
-38.622 dB
-42.144 dB
-48.165 dB
Mute
9
8
7
6
5
4
3
2
1
0
-29.080 dB
-30.103 dB
-31.263 dB
-32.602 dB
-34.185 dB
-36.124 dB
-38.622 dB
-42.144 dB
-48.165 dB
Mute
Note 1: Attenuation values do not include errors from Digital Potentiometer errors, such as Full Scale Error or Zero
Scale Error.
2010 Microchip Technology Inc.
DS22267A-page 69
MCP443X/5X
8.6.2
LAYOUT CONSIDERATIONS
8.6
Design Considerations
Several layout considerations may be applicable to
your application. These may include:
In the design of a system with the MCP44XX devices,
the following considerations should be taken into
account:
• Noise
• Footprint Compatibility
• PCB Area Requirements
• Power Supply Considerations
• Layout Considerations
8.6.2.1
Noise
8.6.1
POWER SUPPLY
CONSIDERATIONS
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP44XX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multi-layer
The typical application will require a bypass capacitor
in order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity. Figure 8-8 illustrates an
appropriate bypass strategy.
boards utilizing
a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
In this example, the recommended bypass capacitor
value is 0.1 µF. This capacitor should be placed as
close (within 4 mm) to the device power pin (VDD) as
possible.
If low noise is desired, breadboards and wire-wrapped
boards are not recommended.
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
8.6.2.2
Footprint Compatibility
The specification of the MCP44XX pinouts was done to
allow systems to be designed to easily support the use
of either the dual (MCP46XX) or quad (MCP44XX)
device.
V
SS should reside on the analog plane.
VDD
Figure 8-9 shows how the dual pinout devices fit on the
quad device footprint. For the Rheostat devices, the
dual device is in the MSOP package, so the footprints
would need to be offset from each other.
0.1 µF
VDD
MCP44X1 Quad Potentiometers
0.1 µF
P2A
P2W
P2B
P3A
P3W
P3B
20
19
18
17
16
1
2
3
4
5
6
7
8
9
10
V
HVC/A0
SCL
DD
A1
SCL
SDA
15 RESET
A
SDA
HVC/A0
A1
14 WP
MCP42X1 Pinout (1)
V
SS
P0B
P0W
P0A
P1B
P1W
P1A
12
12
11
W
TSSOP
B
MCP44X2 Quad Rheostat
P2W
P2B
P3W
P3B
14
13
12
11
10
9
1
2
3
4
5
6
7
V
HVC/A0
SCL
DD
VSS
VSS
A1
SDA
P0B
P0W
P1W
MCP42X2 Pinout
V
SS
FIGURE 8-8:
Typical Microcontroller
8
P1B
Connections.
TSSOP
Note 1: Pin 15 (RESET) is the Address A2 (A2)
pin on the MCP46x1 device.
FIGURE 8-9:
Quad Pinout (TSSOP
Package) vs. Dual Pinout.
DS22267A-page 70
2010 Microchip Technology Inc.
MCP443X/5X
Figure 8-10 shows possible layout implementations for
an application to support the quad and dual options on
the same PCB.
8.6.2.3
PCB Area Requirements
In some applications, PCB area is a criteria for device
selection. Table 8-2 shows the package dimensions
and area for the different package options. The table
also shows the relative area factor compared to the
smallest area. For space critical applications, the QFN
package would be the suggested package.
Potentiometers Devices
MCP44X1
TABLE 8-2:
Package
PACKAGE FOOTPRINT (1)
Package Footprint
MCP46X1
Dimensions
(mm)
Type
Code
X
Y
Rheostat Devices
MCP46X2
14 TSSOP
ST
ML
ST
5.10 6.40 32.64 2.04
4.00 4.00 16.00
6.60 6.40 42.24 2.64
QFN
20
1
TSSOP
MCP44X2
Note 1: Does not include recommended land
pattern dimensions.
8.6.3
RESISTOR TEMPCO
Characterization curves of the resistor temperature
coefficient (Tempco) are shown in Figure 2-11,
Figure 2-32, Figure 2-52, and Figure 2-72.
FIGURE 8-10:
Dual Devices.
Layout to Support Quad and
These curves show that the resistor network is
designed to correct for the change in resistance as
temperature increases. This technique reduces the
end to end change is RAB resistance.
8.6.4
HIGH VOLTAGE TOLERANT PINS
High Voltage support (VIHH) on the Serial Interface pins
is for compatibility with the non-volatile devices.
2010 Microchip Technology Inc.
DS22267A-page 71
MCP443X/5X
NOTES:
DS22267A-page 72
2010 Microchip Technology Inc.
MCP443X/5X
9.2
Technical Documentation
9.0
9.1
DEVELOPMENT SUPPORT
Development Tools
Several additional technical documents are available to
assist you in your design and development. These
technical documents include Application Notes,
Technical Briefs, and Design Guides. Table 9-2 shows
some of these documents.
Several development tools are available to assist in
your design and evaluation of the MCP44XX devices.
The currently available tools are shown in Table 9-1.
These boards may be purchased directly from the
Microchip web site at www.microchip.com.
TABLE 9-1:
Board Name
DEVELOPMENT TOOLS
Part #
TSSOP20EV
Supported Devices
20-pin TSSOP and SSOP Evaluation Board
MCP44XX
MCP46XX
MCP46XX Digital Potentiometer PICtail Plus Demo MCP46XXDM-PTPLS
Board (1, 2)
MCP46XX Digital Potentiometer Evaluation Board (2) MCP46XXEV
MCP46X1
Note 1: Requires a PICDEM Demo board. See the User’s Guide for additional information and requirements.
2: Requires a PICkit Serial Analyzer. See the User’s Guide for additional information and requirements.
TABLE 9-2:
TECHNICAL DOCUMENTATION
Title
Application
Literature #
Note Number
AN1316
AN1080
AN737
AN692
AN691
AN219
—
Using Digital Potentiometers for Programmable Amplifier Gain
Understanding Digital Potentiometers Resistor Variations
Using Digital Potentiometers to Design Low-Pass Adjustable Filters
Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect
Optimizing the Digital Potentiometer in Precision Circuits
Comparing Digital Potentiometers to Mechanical Potentiometers
Digital Potentiometer Design Guide
DS01316
DS01080
DS00737
DS00692
DS00691
DS00219
DS22017
DS21825
—
Signal Chain Design Guide
2010 Microchip Technology Inc.
DS22267A-page 73
MCP443X/5X
NOTES:
DS22267A-page 74
2010 Microchip Technology Inc.
MCP443X/5X
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
14-Lead TSSOP
Example
4452502E
1035
XXXXXXXX
YYWW
NNN
256
20-Lead QFN (4x4)
Example
XXXXX
XXXXXX
4451
502EML
e
3
1035
256
XXXXXX
YYWWNNN
20-Lead TSSOP
XXXXXXXX
Example
4451502
256
NNN
XXXXX
EST
e3
YYWW
1035
Legend: XX...X Customer-specific information
Y
YY
WW
NNN
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2010 Microchip Technology Inc.
DS22267A-page 75
MCP443X/5X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22267A-page 76
2010 Microchip Technology Inc.
MCP443X/5X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2010 Microchip Technology Inc.
DS22267A-page 77
MCP443X/5X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22267A-page 78
2010 Microchip Technology Inc.
MCP443X/5X
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ꢒꢓꢋꢄꢣ >ꢌꢊꢀ&ꢎꢉꢀ'ꢌ!&ꢀꢍ"ꢊꢊꢉꢅ&ꢀꢒꢇꢍ+ꢇꢐꢉꢀ#ꢊꢇ*ꢄꢅꢐ!(ꢀꢒꢈꢉꢇ!ꢉꢀ!ꢉꢉꢀ&ꢎꢉꢀꢕꢄꢍꢊꢌꢍꢎꢄꢒꢀꢃꢇꢍ+ꢇꢐꢄꢅꢐꢀꢔꢒꢉꢍꢄ%ꢄꢍꢇ&ꢄꢌꢅꢀꢈꢌꢍꢇ&ꢉ#ꢀꢇ&ꢀ
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ꢁꢂ ꢃꢄꢅꢀꢁꢀꢆꢄ!"ꢇꢈꢀꢄꢅ#ꢉ$ꢀ%ꢉꢇ&"ꢊꢉꢀ'ꢇꢋꢀꢆꢇꢊꢋ(ꢀ)"&ꢀ'"!&ꢀ)ꢉꢀꢈꢌꢍꢇ&ꢉ#ꢀ*ꢄ&ꢎꢄꢅꢀ&ꢎꢉꢀꢎꢇ&ꢍꢎꢉ#ꢀꢇꢊꢉꢇꢂ
ꢏꢂ ꢃꢇꢍ+ꢇꢐꢉꢀꢄ!ꢀ!ꢇ*ꢀ!ꢄꢅꢐ"ꢈꢇ&ꢉ#ꢂ
5ꢂ ꢑꢄ'ꢉꢅ!ꢄꢌꢅꢄꢅꢐꢀꢇꢅ#ꢀ&ꢌꢈꢉꢊꢇꢅꢍꢄꢅꢐꢀꢒꢉꢊꢀꢓꢔꢕ6ꢀ7ꢁꢖꢂ8ꢕꢂ
;ꢔ<= ;ꢇ!ꢄꢍꢀꢑꢄ'ꢉꢅ!ꢄꢌꢅꢂꢀꢗꢎꢉꢌꢊꢉ&ꢄꢍꢇꢈꢈꢋꢀꢉ$ꢇꢍ&ꢀꢆꢇꢈ"ꢉꢀ!ꢎꢌ*ꢅꢀ*ꢄ&ꢎꢌ"&ꢀ&ꢌꢈꢉꢊꢇꢅꢍꢉ!ꢂ
ꢘ6>= ꢘꢉ%ꢉꢊꢉꢅꢍꢉꢀꢑꢄ'ꢉꢅ!ꢄꢌꢅ(ꢀ"!"ꢇꢈꢈꢋꢀ*ꢄ&ꢎꢌ"&ꢀ&ꢌꢈꢉꢊꢇꢅꢍꢉ(ꢀ%ꢌꢊꢀꢄꢅ%ꢌꢊ'ꢇ&ꢄꢌꢅꢀꢒ"ꢊꢒꢌ!ꢉ!ꢀꢌꢅꢈꢋꢂ
ꢕꢄꢍꢊꢌꢍꢎꢄꢒ ꢗꢉꢍꢎꢅꢌꢈꢌꢐꢋ ꢑꢊꢇ*ꢄꢅꢐ <ꢚꢖꢝꢁꢏO;
2010 Microchip Technology Inc.
DS22267A-page 79
MCP443X/5X
ꢒꢓꢋꢄꢣ >ꢌꢊꢀ&ꢎꢉꢀ'ꢌ!&ꢀꢍ"ꢊꢊꢉꢅ&ꢀꢒꢇꢍ+ꢇꢐꢉꢀ#ꢊꢇ*ꢄꢅꢐ!(ꢀꢒꢈꢉꢇ!ꢉꢀ!ꢉꢉꢀ&ꢎꢉꢀꢕꢄꢍꢊꢌꢍꢎꢄꢒꢀꢃꢇꢍ+ꢇꢐꢄꢅꢐꢀꢔꢒꢉꢍꢄ%ꢄꢍꢇ&ꢄꢌꢅꢀꢈꢌꢍꢇ&ꢉ#ꢀꢇ&ꢀ
ꢎ&&ꢒ=??***ꢂ'ꢄꢍꢊꢌꢍꢎꢄꢒꢂꢍꢌ'?ꢒꢇꢍ+ꢇꢐꢄꢅꢐ
DS22267A-page 80
2010 Microchip Technology Inc.
MCP443X/5X
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢉꢅꢊꢋꢌꢍꢇꢤꢥꢌꢦꢇꢧꢥꢨꢌꢦꢔꢇꢧꢞꢅꢉꢉꢇꢩꢏꢋꢉꢌꢦꢄꢇꢖꢧꢤꢘꢇꢙꢇꢚꢜꢚꢇꢞꢞꢇꢟꢓꢆꢠꢇꢡꢤꢧꢧꢩꢈꢢ
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D
N
E
E1
NOTE 1
1
2
e
b
c
φ
A2
A
L
A1
L1
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ꢘ6>= ꢘꢉ%ꢉꢊꢉꢅꢍꢉꢀꢑꢄ'ꢉꢅ!ꢄꢌꢅ(ꢀ"!"ꢇꢈꢈꢋꢀ*ꢄ&ꢎꢌ"&ꢀ&ꢌꢈꢉꢊꢇꢅꢍꢉ(ꢀ%ꢌꢊꢀꢄꢅ%ꢌꢊ'ꢇ&ꢄꢌꢅꢀꢒ"ꢊꢒꢌ!ꢉ!ꢀꢌꢅꢈꢋꢂ
ꢕꢄꢍꢊꢌꢍꢎꢄꢒ ꢗꢉꢍꢎꢅꢌꢈꢌꢐꢋ ꢑꢊꢇ*ꢄꢅꢐ <ꢚꢖꢝꢚLL;
2010 Microchip Technology Inc.
DS22267A-page 81
MCP443X/5X
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22267A-page 82
2010 Microchip Technology Inc.
MCP443X/5X
APPENDIX A: REVISION HISTORY
Revision A (November 2010)
• Original release of this document.
2010 Microchip Technology Inc.
DS22267A-page 83
MCP443X/5X
NOTES:
DS22267A-page 84
2010 Microchip Technology Inc.
MCP443X/5X
B.1
Low-Voltage Operation
APPENDIX B: CHARACTERIZATION
DATA ANALYSIS
This appendix gives an overview of CMOS
semiconductor characteristics at lower voltages. This is
important so that the 1.8V resistor network
characterization graphs of the MCP443X/5X devices
can be better understood.
Some designers may want to understand the device
operational characteristics outside of the specified
operating conditions of the device.
Applications where the knowledge of the resistor
network characteristics could be useful include battery
powered devices and applications that experience
brown-out conditions.
For this discussion, we will use the 5 k device data.
This data was chosen since the variations of wiper
resistance have much greater implications for devices
with smaller RAB resistances.
In battery applications, the application voltage decays
over time until new batteries are installed. As the
voltage decays, the system will continue to operate. At
some voltage level, the application will be below its
specified operating voltage range. This is dependent
on the individual components used in the design. It is
still useful to understand the device characteristics to
expect when this low-voltage range is encountered.
Unlike a microcontroller, which can use an external
supervisor device to force the controller into the Reset
state, a digital potentiometer’s resistance characteristic
is not specified. But understanding the operational
characteristics can be important in the design of the
applications circuit for this low-voltage condition.
Figure B-1 shows the worst case RBW error from the
average RBW as a percentage, while Figure B-2 shows
the RBW resistance versus the wiper code graph.
Non-linear behavior occurs at approximately wiper
code 160. This is better shown in Figure B-2, where the
RBW resistance changes from a linear slope. This
change is due to the change in the wiper resistance.
2.00%
1.00%
0.00%
-1.00%
-2.00%
-3.00%
Other
application
system
scenarios
where
-4.00%
-5.00%
understanding the low-voltage characteristics of the
resistor network could be important is for system brown
out conditions.
-40C
+25C
+85C
+125C
-6.00%
-7.00%
For the MCP443X/5X devices, the analog operation is
specified at a minimum of 2.7V. Device testing has Ter-
minal A connected to the device VDD (for the
potentiometer configuration only) and Terminal B
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE B-1:
1.8V Worst Case RBW Error
from Average RBW (RBW0-RBW3) vs. Wiper Code
and Temperature (VDD = 1.8V, IW = 190 µA).
connected to VSS
.
7000
6000
5000
4000
3000
-40C
+25C
2000
+85C
+125C
1000
0
0
32
64
96
128
160
192
224
256
Wiper Code
FIGURE B-2:
RBW vs. Wiper Code And
Temperature (VDD = 1.8V, IW = 190 µA).
2010 Microchip Technology Inc.
DS22267A-page 85
MCP443X/5X
Figure B-3 and Figure B-4 show the wiper resistance
for VDD voltages of 5.5, 3.0, 1.8 Volts. These graphs
show that as the resistor ladder wiper node voltage
(VWCn) approaches the VDD/2 voltage, the wiper
resistance increases. These graphs also show the
different resistance characteristics of the NMOS and
PMOS transistors that make up the wiper switch. This
is demonstrated by the wiper code resistance curve,
which does not mirror itself around the mid-scale code
(wiper code = 128).
The method in which the data was collected is
important to understand. Figure B-5 shows the
technique that was used to measure the RBW and RW
resistance. In this technique, Terminal A is floating and
Terminal B is connected to ground. A fixed current is
then forced into the wiper (IW) and the corresponding
wiper voltage (VW) is measured. Forcing a known
current through RBW (IW) and then measuring the
voltage difference between the wiper (VW) and
Terminal A (VA), the wiper resistance (RW) can be
calculated, see Figure B-5. Changes in IW current will
change the wiper voltage (VW). This may affect the
device’s wiper resistance (RW).
So why are the RW graphs showing the maximum
resistance at about mid-scale (wiper code = 128) and
the RBW graphs showing the issue at code 160?
This requires understanding low-voltage transistor
characteristics as well as how the data was measured.
floating
VA
A
VW
220
W
-40C @ 3.0V
-40C @5.5V
+25C @ 3.0V
+25C @ 5.5V
+85C @ 3.0V
+85C @ 5.5V
+125C @ 3.0V
+125C @ 5.5V
200
180
160
140
120
100
80
IW
RBW = VW/IW
B
RW = (VW-VA)/IW
VB
FIGURE B-5:
RBW and RW Measurement.
60
40
Figure B-6 shows a block diagram of the resistor
network where the RAB resistor is a series of 256 RS
resistors. These resistors are polysilicon devices. Each
wiper switch is an analog switch made up of an NMOS
and PMOS transistor. A more detailed figure of the
wiper switch is shown in Figure B-7. The wiper
resistance is influenced by the voltage on the wiper
switches nodes (VG, VW and VWCn). Temperature also
influences the characteristics of the wiper switch, see
Figure B-4.
20
0
64
128
Wiper Code
192
256
FIGURE B-3:
Wiper Resistance (RW) vs.
Wiper Code and Temperature
(VDD = 5.5V, IW = 900 µA; VDD = 3.0V,
IW = 480 µA).
The NMOS transistor and PMOS transistor have
different characteristics. These characteristics, as well
as the wiper switch node voltages, determine the RW
resistance at each wiper code. The variation of each
wiper switch’s characteristics in the resistor network is
greater then the variation of the RS resistors.
-40C @ 1.8V
2020
+25C @ 1.8V
+85C @ 1.8V
+125C @ 1.8V
1520
1020
520
20
The voltage on the resistor network node (VWCn) is
dependent upon the wiper code selected and the
voltages applied to VA, VB and VW. The wiper switch VG
voltage to VW or VWCn voltage determines how strongly
the transistor is turned on. When the transistor is
weakly turned on, the wiper resistance RW will be high.
When the transistor is strongly turned on, the wiper
resistance (RW) will be in the typical range.
0
64
128
192
256
Wiper Code
FIGURE B-4:
Wiper Code and Temperature
(VDD = 1.8V, IW = 260 µA).
Wiper Resistance (RW) vs.
DS22267A-page 86
2010 Microchip Technology Inc.
MCP443X/5X
So looking at the wiper voltage (VW) for the
3.0V and 1.8V data gives the graphs in Figure B-8 and
Figure B-9. In the 1.8V graph, as the VW approaches
0.8V, the voltage increases nonlinearly. Since V = I * R,
and the current (IW) is constant, it means that the
device resistance increased nonlinearly at around
wiper code 160.
A
VA
Nn
RS
(1)
(1)
RW
Nn-1
RS
1.2
1.0
0.8
0.6
DVG
RW
NMOS
PMOS
Nn-2
RS
VWC(n-2)
RAB
(1)
RW
Nn-3
0.4
0.2
0.0
-40C
+25C
+85C
+125C
W
VW
N1
RS
0
32
64
96 128 160 192 224 256
Wiper Code
(1)
RW
FIGURE B-8:
Wiper Code (VDD = 3.0V, IW = 190 µA).
Wiper Voltage (VW) vs.
N0
(1)
RW
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
VB
B
Note 1: The wiper resistance is dependent on
several factors including, wiper code,
device VDD, Terminal voltages (on A, B
and W), and temperature.
-40C
FIGURE B-6:
Resistor Network Block
+25C
+85C
+125C
Diagram.
The characteristics of the wiper are determined by the
characteristics of the wiper switch at each of the
resistor networks tap points. Figure B-7 shows an
example of a wiper switch. As the device operational
voltage becomes lower, the characteristics of the wiper
switch change due to a lower voltage on the VG signal.
0
32
64
96
128 160 192 224 256
Wiper Code
FIGURE B-9:
Wiper Code (VDD = 1.8V, IW = 190 µA).
Wiper Voltage (VW) vs.
Figure B-7 shows an implementation of a wiper switch.
When the transistor is turned off, the switch resistance
is in the Giga s. When the transistor is turned on, the
switch resistance is dependent on the VG, VW and
VWCn voltages. This resistance is referred to as RW.
(1)
RW
VG (VDD/VSS
)
“gate”
NMOS
PMOS
NWC
VWCn
Wiper
VW
“gate”
Note 1: Wiper Resistance (RW) depends on the
voltages at the wiper switch nodes
(VG, VW and VWCn).
FIGURE B-7:
Wiper Switch.
2010 Microchip Technology Inc.
DS22267A-page 87
MCP443X/5X
Using the simulation models of the NMOS and PMOS
devices for the MCP44XX analog switch (Figure B-10),
we plot the device resistance when the devices are
turned on. Figure B-11 and Figure B-12 show the
resistances of the NMOS and PMOS devices as the
VIN voltage is increased. The wiper resistance (RW) is
simply the parallel resistance on the NMOS and PMOS
devices (RW = RNMOS || RPMOS). Below the threshold
voltage for the NMOS ad PMOS devices, the
resistance becomes very large (Gigaohms). In the
transistors active region, the resistance is much lower.
For these graphs, the resistances are on different
scales. Figure B-13 and Figure B-14 only plot the
NMOS and PMOS device resistance for their active
region and the resulting wiper resistance. For these
graphs, all resistances are on the same scale.
7.00E+09
6.00E+09
5.00E+09
4.00E+09
3.00E+09
2.00E+09
1.00E+09
0.00E+00
160
140
120
100
80
RNMOS
RPMOS
RW
NMOS
Theshold
60
PMOS
Theshold
40
20
0
0.0
0.6
1.2
1.8
VIN Voltage
2.4
3.0
FIGURE B-12:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 1.8V).
RW
VG (VDD/VSS
)
“gate”
“gate”
300
250
200
NMOS
PMOS
VIN
VOUT
RNMOS
RPMOS
150
100
50
FIGURE B-10:
Analog Switch.
RW
3.00E+10
2.50E+10
2500
RW
RNMOS
0
0.0
0.6
1.2
1.8
2.4
3.0
2000
1500
1000
500
0
VIN Voltage
RPMOS
2.00E+10
1.50E+10
1.00E+10
5.00E+09
0.00E+00
FIGURE B-13:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 3.0V).
NMOS
PMOS
Theshold
Theshold
5000
4500
4000
3500
3000
0.0
0.3
0.6
0.9
VIN Voltage
1.2
1.5
1.8
FIGURE B-11:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 3.0V).
RNMOS
RPMOS
2500
2000
1500
1000
500
RW
0
0.0
0.3
0.6
0.9
IN Voltage
1.2
1.5
1.8
V
FIGURE B-14:
NMOS and PMOS
Transistor Resistance (RNMOS, RPMOS) and
Wiper Resistance (RW) VS. VIN
(VDD = 1.8V).
DS22267A-page 88
2010 Microchip Technology Inc.
MCP443X/5X
B.2
Optimizing Circuit Design for
Low-Voltage Characteristics
R1
The low-voltage nonlinear characteristics can be
minimized by application design. The section will show
two application circuits that can be used to control a
programmable reference voltage (VOUT).
VA
A
VW
W
VOUT
Minimizing the low-voltage nonlinear characteristics is
done by keeping the voltages on the wiper switch
nodes at a voltage where either the NMOS or PMOS
transistor is turned on.
B
VB
R2
An example of this is if we are using a digital
potentiometer for a voltage reference (VOUT). Let’s say
that we want VOUT to range from 0.5 * VDD to 0.6 * VDD
.
FIGURE B-15:
Example Implementation #1.
In example implementation #1 (Figure B-15), we
window the digital potentiometer using resistors R1 and
R2. When the wiper code is at full scale, the VOUT
voltage will be 0.6 * VDD, and when the wiper code is
TABLE B-1:
EXAMPLE #1 VOLTAGE
CALCULATIONS
Variation
at zero scale the VOUT voltage will be 0.5 * VDD
.
Min
Typ
Max
Remember that the digital potentiometers RAB variation
must be included. Table B-1 shows that the VOUT
voltage can be selected to be between 0.455 * VDD and
0.727 * VDD, which includes the desired range. With
respect to the voltages on the resistor network node, at
1.8V the VA voltage would range from 1.29V to 1.31V
while the VB voltage would range from 0.82V to 0.86V.
These voltages cause the wiper resistance to be in the
nonlinear region (see Figure B-12). In Potentiometer
mode, the variation of the wiper resistance is typically
not an issue, as shown by the INL/DNL graph
(Figure 2-6).
R1
12,000
20,000
8,000
12,000
20,000
12,000
20,000
R2
RAB
10,000
12,000
VOUT (@ FS) 0.714 VDD
VOUT (@ ZS) 0.476 VDD
0.70 VDD
0.50 VDD
0.70 VDD
0.50 VDD
0.727 VDD
0.455 VDD
0.727 VDD
0.455 VDD
VA
VB
0.714 VDD
0.476 VDD
Legend: FS – Full Scale, ZS – Zero Scale
In example implementation #2 (Figure B-16) we use
the digital potentiometer in Rheostat mode. The
resistor ladder uses resistors R1 and R2 with RBW at
the bottom of the ladder. When the wiper code is at full
scale, the VOUT voltage will be 0.6 * VDD and when
the wiper code is at full scale the VOUT voltage will be
0.5 * VDD. Remember that the digital potentiometers
RAB variation must be included. Table B-2 shows that
the VOUT voltage can be selected to be between 0.50 *
VDD and 0.687 * VDD, which includes the desired
range. With respect to the voltages on the resistor
network node, at 1.8V the VW voltage would range from
0.29V to 0.38V. These voltages cause the wiper
resistance to be in the linear region (see Figure B-12).
2010 Microchip Technology Inc.
DS22267A-page 89
MCP443X/5X
R1
VOUT
R2
W
VA
A
B
VW
VB
FIGURE B-16:
Example Implementation #2.
TABLE B-2:
EXAMPLE #2 VOLTAGE
CALCULATIONS
Variation
Min
Typ
Max
R1
10,000
10,000
8,000
10,000
10,000
10,000
10,000
10,000
12,000
R2
RBW (max)
VOUT (@ FS) 0.667 VDD 0.643 VDD 0.687 VDD
VOUT(@ ZS) 0.50 VDD 0.50 VDD 0.50 VDD
0.333 VDD 0.286 VDD 0.375 VDD
VSS VSS VSS
VW (@ FS)
VW (@ ZS)
Legend: FS – Full Scale, ZS – Zero Scale
DS22267A-page 90
2010 Microchip Technology Inc.
MCP443X/5X
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
PART NO.
Device
-XXX
X
/XX
a)
MCP4431-502E/XX: 5 k 20-LD Device
Resistance Temperature
Version
Package
b)
c)
d)
e)
f)
MCP4431T-502E/XX: T/R, 5 k20-LD Device
MCP4431-103E/XX: 10 k, 20-LD Device
MCP4431T-103E/XX: T/R, 10 k, 20-LD Device
MCP4431-503E/XX: 50 k, 20-LD Device
MCP4431T-503E/XX: T/R, 50 k, 20-LD Device
MCP4431-104E/XX: 100 k, 20-LD Device
MCP4431T-104E/XX: T/R, 100 k,
Range
Device
MCP4431:
MCP4431T:
Quad Volatile 7-bit Potentiometer
Quad Volatile 7-bit Potentiometer
(Tape and Reel)
Quad Volatile 7-bit Rheostat
Quad Volatile 7-bit Rheostat
(Tape and Reel)
Quad Volatile 8-bit Potentiometer
Quad Volatile 8-bit Potentiometer
(Tape and Reel)
Quad Volatile 8-bit Rheostat
Quad Volatile 8-bit Rheostat
(Tape and Reel)
g)
h)
MCP4432:
MCP4432T:
20-LD Device
a)
MCP4432-502E/XX: 5 k 14-LD Device
b)
c)
d)
e)
f)
MCP4432T-502E/XX: T/R, 5 k14-LD Device
MCP4432-103E/XX: 10 k, 14-LD Device
MCP4432T-103E/XX: T/R, 10 k, 14-LD Device
MCP4432-503E/XX: 50 k, 8LD Device
MCP4432T-503E/XX: T/R, 50 k, 14-LD Device
MCP4432-104E/XX: 100 k, 14-LD Device
MCP4432T-104E/XX: T/R, 100 k,
MCP4451:
MCP4451T:
MCP4452:
MCP4452T:
g)
h)
14-LD Device
Resistance Version: 502
=
=
=
=
5 k
a)
MCP4451-502E/XX: 5 k 20-LD Device
103
503
104
10 k
50 k
100 k
b)
c)
d)
e)
f)
MCP4451T-502E/XX: T/R, 5 k20-LD Device
MCP4451-103E/XX: 10 k, 20-LD Device
MCP4451T-103E/XX: T/R, 10 k, 20-LD Device
MCP4451-503E/XX: 50 k, 20-LD Device
MCP4451T-503E/XX: T/R, 50 k, 20-LD Device
MCP4451-104E/XX: 100 k, 20-LD Device
MCP4451T-104E/XX: T/R, 100 k,
Temperature Range
Package
E
=
-40C to +125C (Extended)
g)
h)
20-LD Device
ST
ML
=
=
Plastic Thin Shrink Small Outline (TSSOP),
14/20-lead
Plastic Quad Flat No-lead (4x4 QFN), 20-lead
a)
MCP4452-502E/XX: 5 k 14-LD Device
b)
c)
d)
e)
f)
MCP4452T-502E/XX: T/R, 5 k14-LD Device
MCP4452-103E/XX: 10 k, 14-LD Device
MCP4452T-103E/XX: T/R, 10 k, 14-LD Device
MCP4452-503E/XX: 50 k, 14-LD Device
MCP4452T-503E/XX: T/R, 50 k, 14-LD Device
MCP4452-104E/XX: 100 k, 14-LD Device
MCP4452T-104E/XX: T/R, 100 k,
g)
h)
14-LD Device
XX
=
=
ST for 14/20-lead TSSOP
ML for 20-lead QFN
2010 Microchip Technology Inc.
DS22267A-page 91
MCP443X/5X
NOTES:
DS22267A-page 92
2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
32
PIC logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-533-6
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2010 Microchip Technology Inc.
DS22267A-page 93
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08/04/10
DS22267A-page 94
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