MCP4462-502E/ST_技术文档

MCP444X/446X

7/8-Bit Quad I²C Digital POT with

Nonvolatile Memory

Package Types (Top View)

Features

• Quad Resistor Network

MCP44X1 Quad Potentiometers

• Potentiometer or Rheostat configuration options

• Resistor Network Resolution

- 7-bit: 128 Resistors (129 Taps)

- 8-bit: 256 Resistors (257 Taps)

• R_ABResistances options of:

- 5 kΩ

- 10 kΩ

- 50 kΩ

- 100 kΩ

P2A

P2W

P2B

P3A

P3W

P3B

20

19

18

17

16

15

1

2

3

V

HVC/A0

SCL

4

DD

A1

RESET

5

SDA

6

V

14 WP

7

SS

P0B

12

P1B

P1W

P1A

8

P0W

P0A

12

11

9

10

• Zero Scale to Full Scale Wiper operation

• Low Wiper Resistance: 75 Ω (typical)

• Low Tempco:

TSSOP

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

- Ratiometric (Potentiometer): 15 ppm typical

• Nonvolatile Memory

- Automatic Recall of Saved Wiper Setting

- WiperLock™ Technology

17 16

18

19

20

15

V

DD

P3B

1

2

3

4

5

14 A1

HVC/A0

SCL

RESET

13

12

EP

21

- 5 General Purpose Memory Locations

WP

SDA

• I²C Serial Interface

P0B

11

V

SS

- 100 kHz, 400 kHz, and 3.4 MHz support

• Serial protocol allows:

- High-Speed Read/Write to wiper

- Read/Write to EEPROM

8

9 10

6

7

- Write Protect to be enabled/disable

- WiperLock to be enabled/disabled

• Resistor Network Terminal Disconnect Feature

via Terminal Control (TCON) Register

• Reset input pin

4x4 QFN

MCP44X2 Quad Rheostat

P2W

P2B

P3W

P3B

14

13

12

11

10

9

1

2

3

4

5

6

7

• Write Protect Feature:

V

HVC/A0

SCL

DD

- Hardware Write Protect (WP) Control pin

- Software Write Protect (WP) Configuration bit

• Brown-out reset protection (1.5V typical)

• Serial Interface Inactive current (2.5 uA typical)

• High-Voltage Tolerant Digital Inputs: Up to 12.5V

• Supports Split Rail Applications

• Internal weak pull-up on all digital inputs

(except SCL and SDA)

A1

SDA

P0B

P0W

P1W

V

SS

8

P1B

TSSOP

• Wide Operating Voltage:

- 2.7V to 5.5V - Device Characteristics

Specified

- 1.8V to 5.5V - Device Operation

• Wide Bandwidth (-3 dB) Operation:

- 2 MHz (typical) for 5.0 kΩ device

• Extended temperature range (-40°C to +125°C)

• Package Types: 4x4 QFN-20, TSSOP-20 and

TSSOP-14

DS22265A-page 1

MCP444X/446X

Device Block Diagram

V_DD

V_SS

Power-up/

Brown-out

Control

P0A

Resistor

Network 0

(Pot 0)

P0W

I²C Serial

Interface

Module &

Control

Logic

(WiperLock™

Technology)

Wiper 0

& TCON0

Register

A1

HVC/A0

SCL

P0B

P1A

SDA

Resistor

Network 1

(Pot 1)

WP

RESET

P1W

Wiper 1

& TCON0

Register

Memory (16x9)

Wiper0 (V & NV)

Wiper1 (V & NV)

Wiper2 (V & NV)

Wiper3 (V & NV)

P1B

P2A

Resistor

Network 2

(Pot 2)

TCON0

TCON1

STATUS

P2W

Wiper 2

& TCON1

Register

Data EEPROM

(5 x 9-bits)

P2B

P3A

Resistor

Network 3

(Pot 3)

P3W

P3B

Wiper 3

& TCON1

Register

Device Features

Resistance (typical)

Wiper

V_DD

Wiper

Configuration

Device

Operating

Range⁽²⁾

R_ABOptions (kΩ)

- R_W

(Ω)

MCP4431⁽³⁾

MCP4432 ⁽³⁾

MCP4441

4

Potentiometer ⁽¹⁾I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat

I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer ⁽¹⁾I²C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0

Rheostat

I²C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat

I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾I²C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0

Rheostat

I²C EE Yes NV Wiper 5.0, 10.0, 50.0, 100.0

75

129 1.8V to 5.5V

129 2.7V to 5.5V

257 1.8V to 5.5V

257 2.7V to 5.5V

MCP4442

MCP4451⁽³⁾

MCP4452⁽³⁾

MCP4461

MCP4462

Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).

2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.

3: Please check Microchip web site for device release and availability.

DS22265A-page 2

MCP444X/446X

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on V with respect to V ................ -0.6V to +7.0V

DD

SS

Voltage on HVC/A0, A1, SCL, SDA, WP, and

RESET with respect to V

-0.6V to 12.5V

SS ...................................

Voltage on all other pins (PxA, PxW, and PxB)

with respect to V -0.3V to V + 0.3V

SS .........................................

DD

Input clamp current, I

IK

(V < 0, V > V , V > V ON HV pins)......................±20 mA

I

DD

I

PP

Output clamp current, I

OK

(V < 0 or V > V ) ..................................................±20 mA

O

DD

Maximum output current sunk by any Output pin

......................................................................................25 mA

Maximum output current sourced by any Output pin ed

......................................................................................25 mA

Maximum current out of V pin .................................100 mA

SS

Maximum current into V pin ....................................100 mA

DD

Maximum current into PXA, PXW & PXB pins ............±2.5 mA

Storage temperature ....................................-65°C to +150°C

Ambient temperature with power applied

..................................................................... -40°C to +125°C

Package power dissipation (T = +50°C, T = +150°C)

A

J

TSSOP-14.......................................................1000 mW

TSSOP-20.......................................................1110 mW

QFN-20 (4x4)..................................................2320 mW

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins ................................... ≥ 4 kV (HBM),

.......................................................................... ≥ 300V (MM)

Maximum Junction Temperature (T ) .........................+150°C

J

DS22265A-page 3

MCP444X/446X

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

2.7

1.8

—

5.5

2.7

V

Serial Interface only.

HVC/A0, SDA,

SCL, A1, WP,

RESET pin

V_HV

V_SS

12.5V

V_DD

4.5V

≥

The HVC/A0 pin will be at one

of three input levels

(V_IL, V_IHor V_IHH). (Note 6)

V_SS

—

V_DD

8.0V

+

V

V_DD

<

Voltage Range

4.5V

V_DDStart Voltage

to ensure Wiper

Reset

V_BOR

V_DDRR

T_BORD

1.65

RAM retention voltage (V_RAM) < V_BOR

V_DDRise Rate to

(Note 9)

V/ms

µs

ensure Power-on

Reset

Delay after device

exits the reset

state

—

10

20

(V_DD> V_BOR

)

Supply Current

(Note 10)

I_DD

—

600

250

575

µA

Serial Interface Active,

HVC/A0 = V_IH(or V_IL) (Note 11)

Write all 0’s to volatile Wiper 0

V_DD= 5.5V, F_SCL@ 3.4 MHz

Serial Interface Active,

HVC/A0 = V_IH(or V_IL) (Note 11)

Write all 0’s to volatile Wiper 0

V_DD= 5.5V, F_SCL@ 100 kHz

EE Write Current (Write Cycle)

(Nonvolatile device only),

V_DD= 5.5V, F_SCL= 400 kHz,

Write all 0’s to Nonvolatile Wiper 0

SCL = V_ILor V_IH

—

2.5

5

µA

Serial Interface Inactive,

(Stop condition, SCL = SDA = V_IH),

Wiper = 0

V_DD= 5.5V, HVC/A0 = V_IH

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 4

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

-502 devices (Note 1)

Resistance

(± 20%)

R_AB

4.0

8.0

5

10

6.0

12.0

60.0

120.0

kΩ

-103 devices (Note 1)

-503 devices (Note 1)

-104 devices (Note 1)

40.0

80.0

50

100

257

129

R_AB

Resolution

N

Taps 8-bit

Taps 7-bit

No Missing Codes

Note 6

Step Resistance

R_S

—

/

—

Ω

8-bit

(256)

R_AB

/

Ω

7-bit

Note 6

(128)

Nominal

(| R_ABWC

-

—

0.2

1.50

1.25

1.0

%

Ω

5 kΩ

MCP44X1 devices only

Resistance Match R_ABMEAN|) /

R_ABMEAN

0.2

10 kΩ

50 kΩ

100 kΩ

5 kΩ

10 kΩ

50 kΩ

100 kΩ

0.2

1.0

(| R_BWWC

R_BWMEAN|) /

R_BWMEAN

-

0.25

75

1.75

1.50

1.25

160

300

—

Code = Full Scale

Wiper Resistance

(Note 3, Note 4)

R_W

V_DD= 5.5 V, I_W= 2.0 mA, code = 00h

V_DD= 2.7 V, I_W= 2.0 mA, code = 00h

75

Ω

Nominal

Resistance

Tempco

ΔR_AB/ΔT

50

ppm/°C T_A= -20°C to +70°C

ppm/°C T_A= -40°C to +85°C

ppm/°C T_A= -40°C to +125°C

ppm/°C Code = Midscale (80h or 40h)

100

150

15

—

Ratiometeric

Tempco

ΔV_WB/ΔT

ΔR_TRACK

—

Resistance

Tracking

Section 2.0

ppm/°C See Typical Performance Curves

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 5

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

Resistor Terminal

Input Voltage

V_A,V_W,V_B

Vss

—

V_DD

V

Note 5, Note 6

Range (Terminals

A, B and W)

I

,

Maximum current

through A, W or B

(Note 6)

I_W

—

2.5

mA

Terminal A

Terminal B

Terminal W

AW

W = Full Scale (FS)

I

,

BW

W = Zero Scale (ZS)

I

(W = FS) or

(W = ZS)

AW

BW

Maximum R_AB

I_AB

—

1.38

0.688

0.138

0.069

—

mA

nA

V_B= 0V, V_A= 5.5V, R_AB(MIN)= 4000Ω

V_B= 0V, V_A= 5.5V, R_AB(MIN)= 8000Ω

V_B= 0V, V_A= 5.5V, R_AB(MIN)= 40000Ω

V_B= 0V, V_A= 5.5V, R_AB(MIN)= 80000Ω

MCP44X1 PxA = PxW = PxB = V_SS

MCP44X2 PxB = PxW = V_SS

current (I_AB

)

(Note 6)

—

Leakage current

into A, W or B

I_WL

100

—

nA

—

nA

Terminals Disconnected

(R0A = R0W = R0B = 0;

R1A = R1W = R1B = 0;

R2A = R2W = R2B = 0;

R3A = R3W = R3B = 0)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 6

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

3.0V ≤ V_DD≤ 5.5V

Full Scale Error

(MCP44X1 only)

(8-bit code = 100h,

7-bit code = 80h)

V_WFSE

-6.0

-4.0

-3.5

-2.0

-0.8

-0.5

—

-0.1

—

LSb

5 kΩ

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

-0.1

—

10 kΩ 8-bit

7-bit

-0.1

—

-0.1

—

50 kΩ 8-bit

7-bit

-0.1

—

-0.1

—

100 kΩ 8-bit

7-bit

-0.1

—

Zero Scale Error

(MCP44X1 only)

(8-bit code = 00h,

7-bit code = 00h)

V_WZSE

+0.1

±0.5

±0.25

+6.0

+3.0

+3.5

+2.0

+0.8

+0.5

+1

5 kΩ

8-bit

7-bit

—

10 kΩ 8-bit

7-bit

—

50 kΩ 8-bit

7-bit

—

100 kΩ 8-bit

7-bit

—

Potentiometer

Integral

Non-linearity

INL

DNL

BW

-1

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

MCP44X1 devices only

(Note 2)

-0.5

+0.5

Potentiometer

Differential Non-

linearity

-0.5

±0.25

+0.5

LSb

8-bit

7-bit

3.0V ≤ V_DD≤ 5.5V

MCP44X1 devices only

(Note 2)

-0.25

±0.125

+0.25

Bandwidth -3 dB

(See Figure 2-72,

load = 30 pF)

—

2

—

MHz 5 kΩ

MHz

8-bit

7-bit

Code = 80h

Code = 40h

Code = 80h

Code = 40h

Code = 80h

Code = 40h

Code = 80h

Code = 40h

1

MHz 10 kΩ 8-bit

1

MHz

kHz

7-bit

50 kΩ 8-bit

7-bit

200

100

100 kΩ 8-bit

7-bit

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 7

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

5.5V, I_W= 900 µA

Rheostat Integral

Non-linearity

MCP44X1

(Note 4, Note 8)

MCP44X2devices

only (Note 4)

R-INL

-1.5

±0.5

+4.5

+1.5

LSb

5 kΩ

8-bit

7-bit

-8.25

+8.25

3.0V, I_W= 480 µA

(Note 7)

-1.125

-6.0

±0.5

+4.5

+1.125

+6.0

LSb

5.5V, I_W= 900 µA

3.0V, I_W= 480 µA

(Note 7)

-1.5

-5.5

±0.5

+2.5

+1.5

+5.5

LSb

10 kΩ 8-bit

7-bit

5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-1.125

-4.0

±0.5

+2.5

+1.125

+4.0

LSb

5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-1.5

-2.0

±0.5

+1

+1.5

+2.0

LSb

50 kΩ 8-bit

7-bit

5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-1.125

-1.5

±0.5

+1

+1.125

+1.5

LSb

5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-1.0

-1.5

±0.5

+1.0

+1.5

LSb

100 kΩ 8-bit

7-bit

5.5V, I_W= 45 µA

+0.25

3.0V, I_W= 24 µA

(Note 7)

-0.8

±0.5

+0.8

LSb

5.5V, I_W= 45 µA

-1.125

+0.25

+1.125

3.0V, I_W= 24 µA

(Note 7)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 8

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

5.5V, I_W= 900 µA

Rheostat

Differential Non-

linearity

R-DNL

-0.5

-1.0

±0.25

+0.5

+1.0

LSb

5 kΩ

8-bit

7-bit

3.0V, I_W= 480 µA

(Note 7)

MCP44X1

-0.375

-0.75

±0.25

+0.5

+0.375

+0.75

LSb

5.5V, I_W= 900 µA

(Note 4, Note 8)

MCP44X2devices

only

3.0V, I_W= 480 µA

(Note 7)

-0.5

-1.0

±0.25

+0.25

+0.5

+1.0

LSb

10 kΩ 8-bit

7-bit

5.5V, I_W= 450 µA

(Note 4)

3.0V, I_W= 240 µA

(Note 7)

-0.375

-0.75

±0.25

+0.5

+0.375

+0.75

LSb

5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-0.5

±0.25

+0.5

LSb

50 kΩ 8-bit

7-bit

5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-0.375

±0.25

+0.375

LSb

5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-0.5

±0.25

+0.5

LSb

100 kΩ 8-bit

7-bit

5.5V, I_W= 45 µA

3.0V, I_W= 24 µA

(Note 7)

-0.375

±0.25

+0.375

LSb

5.5V, I_W= 45 µA

3.0V, I_W= 24 µA

(Note 7)

Capacitance (P_A)

Capacitance (P_w)

Capacitance (P_B)

C_AW

C_W

—

75

120

75

—

pF

f =1 MHz, Code = Full Scale

C_BW

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 9

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (HVC/A0, A1, SDA, SCL, WP, RESET)

Schmitt Trigger

High Input

V_IH

0.45 V_DD

—

V

All

2.7V ≤ V_DD≤ 5.5V

Inputs (Allows 2.7V Digital V_DDwith

Threshold

except 5V Analog V_DD

)

SDA

and

0.5 V_DD

—

V

1.8V ≤ V_DD≤ 2.7V

SCL

0.7 V_DD

—

V_MAX

0.2V_DD

0.3V_DD

—

V

100 kHz

400 kHz

1.7 MHz

3.4 Mhz

SDA

and

SCL

—

Schmitt Trigger

Low Input

Threshold

V_IL

—

All inputs except SDA and SCL

100 kHz

-0.5

—

SDA

and

SCL

-0.5

—

400 kHz

-0.5

—

1.7 MHz

-0.5

—

3.4 Mhz

Hysteresis of

Schmitt Trigger

Inputs

V_HYS

—

0.1V_DD

—

All inputs except SDA and SCL

N.A.

—

V_DD< 2.0V

100 kHz

N.A.

—

V_DD≥ 2.0V

V_DD< 2.0V

SDA

0.1 V_DD

0.05 V_DD

0.1 V_DD

9.0

—

and 400 kHz

—

V_DD≥ 2.0V

SCL

—

1.7 MHz

—

3.4 Mhz

High Voltage Input

Entry Voltage

V_IHHEN

V_IHHEX

—

12.5

(Note 6)

Threshold for WiperLock Technology

High Voltage Input

Exit Voltage

—

V_DD

+

V

0.8V

(Note 6)

High Voltage Limit

V_MAX

V_OL

12.5

(Note 6)

Pin can tolerate V_MAXor less.

Output Low

Voltage (SDA)

V_SS

—

0.2V_DD

0.4

V

V_DD< 2.0V, I_OL= 1 mA,

V_DD≥ 2.0V, I_OL= 3 mA

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 10

MCP444X/446X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Weak Pull-up

Current

I_PU

—

1.75

mA

Internal V_DDpull-up, V_IHHpull-down,

V_DD= 5.5V, V_HVC= 12.5V

—

170

16

—

µA

HVC pin, V_DD= 5.5V, V_HVC= 3V

V_DD= 5.5V, V_HVC= 3V

HVC Pull-up /

Pull-down

R_HVC

kΩ

Resistance

RESET Pull-up

Resistance

R_RESET

I_IL

—

-1

—

16

—

10

—

1

kΩ

µA

pF

V_DD= 5.5V, V_RESET= 0V

V_IN= V_DD(all pins) and

Input Leakage

Current

V_IN= V_SS(all pins except RESET)

Pin Capacitance

C_IN, C_OUT

—

f_C= 20 MHz

RAM (Wiper, TCON) Value

Value Range

N

0h

—

1FFh

hex

8-bit device

7-bit device

TCON POR/BOR

Setting

1FF

All Terminals connected

EEPROM

Endurance

E_ndurance

—

1M

—

Cycles

hex

EEPROM Range

N

0h

1FFh

Initial NV Wiper

POR/BOR Setting

080h

040h

000h

hex

8-bit

7-bit

WiperLock Technology = Off

hex

Initial EEPROM

N

hex

POR/BOR Setting

EEPROM

t_WC

—

3

10

ms

Programming

Write Cycle Time

Power Requirements

Power Supply

Sensitivity

(MCP44X1)

PSS

—

0.0015 0.0035

%/% 8-bit

%/% 7-bit

V

_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 80h

_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 40h

V

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP44X1 only.

4: MCP44X2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly over voltage and

temperature.

8: The MCP44X1 is externally connected to match the configurations of the MCP44X2, and then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network.

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification.

DS22265A-page 11

MCP444X/446X

2

1.1

I C Mode Timing Waveforms and Requirements

RESET

t

RSTD

t

RST

SCL

SDA

V

IH

Wx

FIGURE 1-1:

RESET Waveforms.

RESET TIMING

TABLE 1-1:

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

RESET pulse width

t_RST

50

—

ns

RESET rising edge

normal mode (Wiper

driving and I²C

t_RSTD

20

interface operational)

DS22265A-page 12

MCP444X/446X

V_IHH

94

95

V_IH

or V_IL

V_IHor V_IL

HVC/A0

SCL

93

91

90

92

SDA

STOP

Condition

START

Condition

FIGURE 1-2:

I²C Bus Start/Stop Bits Timing Waveforms.

TABLE 1-2:

I²C BUS START/STOP BITS REQUIREMENTS

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in AC/DC characteristics

Param.

Symbol

No.

Characteristic

Standard Mode

Min

Max

Units

Conditions

F_SCL

0

100

400

1.7

3.4

400

100

—

kHz C_b= 400 pF, 1.8V - 5.5V

Fast Mode

kHz C_b= 400 pF, 2.7V - 5.5V

High-Speed 1.7

High-Speed 3.4

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

0

MHz C_b= 400 pF, 4.5V - 5.5V

0

MHz C_b= 100 pF, 4.5V - 5.5V

D102

90

Cb

Bus capacitive

loading

—

pF

—

TSU:STA START condition

Setup time

4700

600

160

4000

600

160

4000

600

160

4000

600

160

25

ns

Only relevant for repeated

START condition

—

91

THD:STA START condition

Hold time

—

After this period the first

clock pulse is generated

—

92

TSU:STO STOP condition

Setup time

—

93

THD:STO STOP condition

Hold time

—

94

95

T_HVCSUHVC to SCL Setup time

T_HVCHDSCL to HVC Hold time

—

uS High Voltage Commands

25

—

DS22265A-page 13

MCP444X/446X

103

102

100

101

109

SCL

90

106

91

92

107

SDA

In

110

109

SDA

Out

FIGURE 1-3:

I²C Bus Data Timing.

I²C BUS DATA REQUIREMENTS (SLAVE MODE)

TABLE 1-3:

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max Units

Conditions

Clock hightime 100 kHz mode

400 kHz mode

4000

600

120

60

—

ns

1.8V-5.5V

100

THIGH

2.7V-5.5V

4.5V-5.5V

1.8V-5.5V

2.7V-5.5V

4.5V-5.5V

1.7 MHz mode

3.4 MHz mode

—

101

TLOW

Clock low time 100 kHz mode

400 kHz mode

4700

1300

320

160

1.7 MHz mode

3.4 MHz mode

—

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

T_Rmax.+t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V_IH

and V_ILof the falling edge of the SCL signal. This specification is not a part of the I²C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

7: Ensured by the T_AA3.4 MHz specification test.

DS22265A-page 14

MCP444X/446X

TABLE 1-3:

I²C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max Units

Conditions

102A ⁽⁵⁾

T_RSCL

SCL rise time

100 kHz mode

400 kHz mode

1.7 MHz mode

—

20 + 0.1Cb

20

1000

300

80

ns

Cb is specified to be from

10 to 400 pF (100 pF maxi-

mum for 3.4 MHz mode)

20

160

After a Repeated Start con-

dition or an Acknowledge

bit

3.4 MHz mode

10

40

80

ns

After a Repeated Start

condition or an Acknowl-

edge bit

102B ⁽⁵⁾

T_RSDA

T_FSCL

T_FSDA

SDA rise time

SCL fall time

SDA fall time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

—

1000

300

160

80

ns

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

20 + 0.1Cb

20

10

103A ⁽⁵⁾

—

300

80

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

20 + 0.1Cb

20

10

—

40

103B ⁽⁵⁾

300

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode 20 + 0.1Cb ⁽⁴⁾300

1.7 MHz mode

3.4 MHz mode

20

10

0

160

80

—

106

T_HD:DATData input hold 100 kHz mode

1.8V-5.5V, Note 6

2.7V-5.5V, Note 6

4.5V-5.5V, Note 6

time

400 kHz mode

0

—

1.7 MHz mode

3.4 MHz mode

0

—

0

—

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

T_Rmax.+t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V_IH

and V_ILof the falling edge of the SCL signal. This specification is not a part of the I²C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

7: Ensured by the T_AA3.4 MHz specification test.

DS22265A-page 15

MCP444X/446X

TABLE 1-3:

I²C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max Units

Conditions

107

T_SU:DATData input setup 100 kHz mode

250

100

10

—

ns

Note 2

Note 1

time

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

10

—

109

T_AA

Output valid

from clock

100 kHz mode

400 kHz mode

1.7 MHz mode

—

3450

900

150

—

Cb = 100 pF,

Note 1, Note 7

—

310

ns

Cb = 400 pF,

Note 1, Note 5

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

4700

1300

N.A.

—

150

—

ns

Cb = 100 pF, Note 1

110

TBUF

Bus free time

Time the bus must be free

before a new transmission

can start

—

T_SP

Input filter spike 100 kHz mode

50

10

Philips Spec states N.A.

suppression

(SDA and SCL)

400 kHz mode

—

1.7 MHz mode

—

Spike suppression

3.4 MHz mode

—

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

T_Rmax.+t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP44X1/MCP44X2 device must provide a data hold time to bridge the undefined part between V_IH

and V_ILof the falling edge of the SCL signal. This specification is not a part of the I²C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested.

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

7: Ensured by the T_AA3.4 MHz specification test.

DS22265A-page 16

MCP444X/446X

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 14L-TSSOP

Thermal Resistance, 20L-QFN

Thermal Resistance, 20L-TSSOP

T_A

-40

-65

—

+125

+150

°C

θ_JA

—

100

43

—

°C/W

90

DS22265A-page 17

MCP444X/446X

NOTES:

DS22265A-page 18

MCP444X/446X

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

550

500

450

400

350

300

250

200

150

100

50

0

250

200

150

100

50

1000

800

600

400

200

0

3.4MHz, 5.5V

3.4MHz, 4.5V

I_HVC

1.7MHz, 5.5V

1.7MHz, 4.5V

-200

-400

-600

-800

-1000

400kHz, 5.5V

100kHz, 5.5V

R_HVC

400kHz, 2.7V

100kHz, 2.7V

0

-40

0

40

Temperature (°C)

80

120

2

3

4

5

6

7

8

9

10

V

_HVC(V)

FIGURE 2-1:

Device Current (I_DD) vs. I²C

FIGURE 2-4:

HVC/A0 Pull-up/Pull-down

Frequency (f_SCL) and Ambient Temperature

(V_DD= 2.7V and 5.5V).

Resistance (R_HVC) and Current (I_HVC) vs. HVC/

A0 Input Voltage (V_HVC) (V_DD= 5.5V).

3.0

12.0

10.0

2.5

5.5V

5.5V Entry

2.7V Entry

2.0

8.0

1.5

6.0

5.5V Exit

2.7V

2.7V Exit

1.0

0.5

0.0

4.0

2.0

0.0

-40

0

40

80

120

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-2:

Device Current (I_SHDN) and

FIGURE 2-5:

HVC/A0 High Input Entry/

V_DD. (HVC/A0 = V_DD) vs. Ambient Temperature.

Exit Threshold vs. Ambient Temperature and

V_DD

.

500

400

300

200

100

0

5.5V

2.7V

-40

0

40

80

120

Ambient Temperature (°C)

FIGURE 2-3:

Write Current (I_WRITE) vs.

Ambient Temperature and V_DD

.

DS22265A-page 19

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1.25

0.75

0.25

-0.25

-0.75

-1.25

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

DNL

-40°C

40

-40°C 25°C

R_W

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-6:

5 kΩ Pot Mode – R_W(Ω),

FIGURE 2-8:

5 kΩ Rheo Mode – R_W(Ω),

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

300

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

260

220

180

140

100

60

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

6

260

220

180

140

100

60

0.2

0.1

0

INL

4

DNL

2

R_W

125°C

-0.1

-0.2

-0.3

0

-40°C

85°C

25°C

DNL

-40°C

125°C 85°C

20

-2

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-7:

5 kΩ Pot Mode – R_W(Ω),

FIGURE 2-9:

5 kΩ Rheo Mode – R_W(Ω),

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 3.0V).

DS22265A-page 20

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

5300

5250

6000

5000

4000

3000

2000

1000

0

2.7V

5200

5150

-40C

+25C

+85C

+125C

5100

5.5V

5050

-40

0

40

80

120

0

32

64

96

128

160

192

224

256

Wiper Code

Ambient Temperature (°C)

FIGURE 2-10:

5 kΩ – Nominal Resistance

FIGURE 2-11:

5 kΩ – R_WB(Ω) vs. Wiper

(R_AB) (Ω) vs. Ambient Temperature and V_DD

.

Setting and Ambient Temperature

(V_DD= 5.5V, I_W= 190 µA).

6000

5000

4000

3000

2000

1000

0

-40C

+25C

+85C

+125C

0

32

64

96

128

160

192

224

256

Wiper Code

FIGURE 2-12:

5 kΩ – R_WB(Ω) vs. Wiper

Setting and Ambient Temperature

(V_DD= 3.0V, I_W= 190 µA).

DS22265A-page 21

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

2.50%

54

52

50

48

46

44

42

40

-40C

CH0

CH2

CH1

CH3

+25C

1.50%

+85C

+125C

0.50%

-0.50%

-1.50%

-2.50%

0

32

64

96

128

160

192

224

256

0

32

64

96 128 160 192 224 256

Wiper Code

FIGURE 2-15:

5 kΩ – R_WBPPM/°C vs.

FIGURE 2-13:

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 5.5V, I_W= 190 µA).

5 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 5.5V, I_W= 190 µA).

100

2.50%

-40C

CH0

CH2

CH1

CH3

95

90

85

80

75

70

65

60

+25C

1.50%

+85C

+125C

0.50%

-0.50%

-1.50%

-2.50%

0

32

64

96

128

160

192

224

256

0

32

64

96

128 160 192 224 256

Wiper Code

FIGURE 2-16:

5 kΩ – R_WBPPM/°C vs.

FIGURE 2-14:

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 3.0V, I_W= 190 µA).

5 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 3.0V, I_W= 190 µA).

DS22265A-page 22

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-17:

Decrement Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

5 kΩ – Low-Voltage

FIGURE 2-20:

5 kΩ – Low-Voltage

Increment Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

FIGURE 2-18:

5 kΩ – Low-Voltage

FIGURE 2-21:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V_DD= 5.5V)

Increment Wiper Settling Time (V_DD= 5.5V)

(1 µs/Div).

FIGURE 2-19:

5 kΩ – Power-Up Wiper

Response Time (20 ms/Div).

DS22265A-page 23

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.5

0

INL

DNL

60

-0.1

-0.2

-0.3

-0.5

-1

DNL

40

-40°C

40

-40°C

R_W

25°C

85°C

85°C 25°C

R_W

125°C

20

0

25 50 75 100 125150175200225 250

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-22:

10 kΩ Pot Mode – R_W(Ω),

FIGURE 2-24:

10 kΩ Rheo Mode – R_W(Ω),

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

300

260

220

180

140

100

60

4

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

260

220

180

140

100

60

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

3

0.2

0.1

0

INL

DNL

2

1

0

-0.1

-0.2

-0.3

R_W

DNL R_W

-1

-2

-40°C

25°C

85°C 25°C

125°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

FIGURE 2-23:

10 kΩ Pot Mode – R_W(Ω),

FIGURE 2-25:

10 kΩ Rheo Mode – R_W(Ω),

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 3.0V).

DS22265A-page 24

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

10250

10200

12000

10000

8000

6000

4000

2000

0

10150

2.7V

10100

-40C

5.5V

+25C

+85C

+125C

10050

10000

-40

0

40

80

120

0

32

64

96

128 160 192 224 256

Ambient Temperature (°C)

Wiper Code

FIGURE 2-26:

(R_AB) (Ω) vs. Ambient Temperature and V_DD

10 kΩ – Nominal Resistance

FIGURE 2-27:

Setting and Ambient Temperature

(V_DD= 5.5V, I_W= 150 µA).

10 kΩ – R_WB(Ω) vs. Wiper

.

12000

10000

8000

6000

4000

2000

0

-40C

+25C

+85C

+125C

0

32

64

96

128 160 192 224 256

Wiper Code

FIGURE 2-28:

10 kΩ – R_WB(Ω) vs. Wiper

Setting and Ambient Temperature

(V_DD= 3.0V, I_W= 150 µA).

DS22265A-page 25

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

1.50%

50

45

40

35

30

25

20

15

10

-40C

+85C

+25C

+125C

1.00%

0.50%

0.00%

-0.50%

-1.00%

-1.50%

CH0

CH2

CH1

CH3

0

32

64

96

128

160

192

224

256

0

32

64

96 128 160 192 224 256

Wiper Code

FIGURE 2-31:

10 kΩ – R_WBPPM/°C vs.

FIGURE 2-29:

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 5.5V, I_W= 150 µA).

10 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 5.5V, I_W= 150 µA).

60

55

50

45

40

35

1.50%

-40C

+85C

+25C

+125C

1.00%

0.50%

0.00%

-0.50%

-1.00%

-1.50%

30

CH0 CH1

CH2 CH3

25

20

0

32

64

96 128 160 192 224 256

Wiper Code

0

32

64

96

128

160

192

224

256

Wiper Code

FIGURE 2-32:

10 kΩ – R_WBPPM/°C vs.

FIGURE 2-30:

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 3.0V, I_W= 150 µA).

10 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 3.0V, I_W= 150 µA).

DS22265A-page 26

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-33:

Decrement Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

10 kΩ – Low-Voltage

FIGURE 2-35:

10 kΩ – Low-Voltage

Increment Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

FIGURE 2-34:

10 kΩ – Low-Voltage

FIGURE 2-36:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V_DD= 5.5V)

Increment Wiper Settling Time (V_DD= 5.5V)

(1 µs/Div).

DS22265A-page 27

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40°C

40

-40°C

R_W

25°C

85°C

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-37:

50 kΩ Pot Mode – R_W(Ω),

FIGURE 2-39:

50 kΩ Rheo Mode – R_W(Ω),

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

300

260

220

180

140

100

60

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

260

220

180

140

100

60

0.3

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.75

0.5

0.25

0

0.2

0.1

0

INL

DNL

-0.25

-0.5

-0.75

-1

R_W

-0.1

-0.2

-0.3

R_W

-40°C

25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-38:

50 kΩ Pot Mode – R_W(Ω),

FIGURE 2-40:

50 kΩ Rheo Mode – R_W(Ω),

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 3.0V).

DS22265A-page 28

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

50800

50600

50400

60000

50000

40000

30000

20000

10000

0

50200

2.7V

50000

5.5V

-40C

49800

+25C

+85C

+125C

49600

49400

-40

0

40

80

120

0

32

64

96

128 160 192 224 256

Ambient Temperature (°C)

Wiper Code

FIGURE 2-41:

(R_AB) (Ω) vs. Ambient Temperature and V_DD

50 kΩ – Nominal Resistance

FIGURE 2-42:

Setting and Ambient Temperature

(V_DD= 5.5V, I_W= 90 µA).

50 kΩ – R_WB(Ω) vs. Wiper

.

60000

50000

40000

30000

20000

10000

0

-40C

+25C

+85C

+125C

0

32

64

96

128 160 192 224 256

Wiper Code

FIGURE 2-43:

50 kΩ – R_WB(Ω) vs. Wiper

Setting and Ambient Temperature

(V_DD= 3.0V, I_W= 48 µA).

DS22265A-page 29

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

7.00%

7

6

5

4

3

2

1

0

-40C

+85C

+25C

+125C

6.00%

5.00%

4.00%

3.00%

2.00%

1.00%

0.00%

-1.00%

CH0

CH2

CH1

CH3

-1

-2

-3

0

32

64

96

128

160

192

224

256

0

32

64

96 128 160 192 224 256

Wiper Code

FIGURE 2-46:

50 kΩ – R_WBPPM/°C vs.

FIGURE 2-44:

50 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 5.5V, I_W= 90 µA).

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 5.5V, I_W= 90 µA).

12

10

8

4.00%

-40C

+25C

3.00%

2.00%

1.00%

0.00%

-1.00%

-2.00%

+85C

+125C

6

4

2

CH0 CH1

CH2 CH3

0

-2

0

32

64

96 128 160 192 224 256

Wiper Code

0

32

64

96

128

160

192

224

256

Wiper Code

FIGURE 2-47:

50 kΩ – R_WBPPM/°C vs.

FIGURE 2-45:

50 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 3.0V, I_W= 48 µA).

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 3.0V, I_W= 48 µA).

DS22265A-page 30

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-48:

Decrement Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

50 kΩ – Low-Voltage

FIGURE 2-50:

50 kΩ – Low-Voltage

Increment Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

FIGURE 2-49:

50 kΩ – Low-Voltage

FIGURE 2-51:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V_DD= 5.5V)

Increment Wiper Settling Time (V_DD= 5.5V)

(1 µs/Div).

DS22265A-page 31

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

40

-40°C

R_W

25°C

85°C

R_W

85°C 25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-52:

100 kΩ Pot Mode – R_W(Ω),

FIGURE 2-54:

100 kΩ Rheo Mode – R_W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 5.5V).

300

260

220

180

140

100

60

0.6

0.4

0.2

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

260

220

180

140

100

60

0.2

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.15

0.1

INL

DNL

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.4

-0.6

R_W

-40°C

85°C 25°C

85°C

25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-53:

100 kΩ Pot Mode – R_W(Ω),

FIGURE 2-55:

100 kΩ Rheo Mode – R_W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V_DD= 3.0V).

DS22265A-page 32

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

101500

101000

120000

100000

80000

60000

40000

20000

0

100500

2.7V

100000

-40C

5.5V

+25C

+85C

+125C

99500

99000

-40

0

40

80

120

0

32

64

96

128 160 192 224 256

Ambient Temperature (°C)

Wiper Code

FIGURE 2-56:

100 kΩ – Nominal

FIGURE 2-57:

Setting and Ambient Temperature

(V_DD= 5.5V, I_W= 45 µA).

100 kΩ – R_WB(Ω) vs. Wiper

Resistance (R_AB) (Ω) vs. Ambient Temperature

and V_DD

.

120000

100000

80000

60000

40000

20000

0

-40C

+25C

+85C

+125C

0

32

64

96

128 160 192 224 256

Wiper Code

FIGURE 2-58:

100 kΩ – R_WB(Ω) vs. Wiper

Setting and Ambient Temperature

(V_DD= 3.0V, I_W= 24 µA).

DS22265A-page 33

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

14.00%

16

14

12

10

8

13.00%

12.00%

11.00%

10.00%

9.00%

8.00%

7.00%

6.00%

5.00%

4.00%

3.00%

2.00%

1.00%

0.00%

-1.00%

-40C

+85C

+25C

+125C

6

4

CH0

CH2

CH1

CH3

2

0

32

64

96

128

160

192

224

256

0

32

64

96 128 160 192 224 256

Wiper Code

FIGURE 2-61:

100 kΩ – R_WBPPM/°C vs.

FIGURE 2-59:

100 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 5.5V, I_W= 45 µA).

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 5.5V, I_W= 45 µA).

18

16

14

12

10

8

7.00%

-40C

+85C

+25C

+125C

6.00%

5.00%

4.00%

3.00%

2.00%

1.00%

0.00%

-1.00%

6

4

2

0

CH0

CH2

CH1

CH3

0

32

64

96

128

160

192

224

256

0

32

64

96

128 160 192 224 256

Wiper Code

FIGURE 2-62:

100 kΩ – R_WBPPM/°C vs.

FIGURE 2-60:

100 kΩ – Worst Case R_BW

Wiper Setting. (R_{BW(code=n, 125°C)}-R_{BW(code=n, -}

_40°C))/R_{BW(code = 256, 25°C)}/165°C * 1,000,000)

(V_DD= 3.0V, I_W= 24 µA).

from Average R_BW(R_BW0-R_BW3) Error (%) vs.

Wiper Setting and Temperature

(V_DD= 3.0V, I_W= 24 µA).

DS22265A-page 34

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-63:

Decrement Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

100 kΩ – Low-Voltage

FIGURE 2-65:

100 kΩ – Low-Voltage

Increment Wiper Settling Time (V_DD= 2.7V)

(1 µs/Div).

FIGURE 2-64:

100 kΩ – Low-Voltage

FIGURE 2-66:

100 kΩ – Low-Voltage

Decrement Wiper Settling Time (V_DD= 5.5V)

Increment Wiper Settling Time (V_DD= 5.5V)

(1 µs/Div).

DS22265A-page 35

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

4

230

210

190

170

150

130

110

90

2.7V

5.5V

3.5

5.5V

3

2.5

2

2.7V

1.5

1

70

50

-40

0

40

Temperature (°C)

80

120

-40

0

40

80

120

Temperature (°C)

FIGURE 2-67:

V_IH(SDA, SCL) vs. V_DDand

FIGURE 2-69:

V_OL(SDA) vs. V_DDand

Temperature.

Temperature (I_OL= 3 mA).

2

5.5V

2.7V

1.5

1

-40

0

40

80

120

Temperature (°C)

FIGURE 2-68:

V_IL(SDA, SCL) vs. V_DDand

Temperature.

DS22265A-page 36

MCP444X/446X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

2.1

Test Circuits

4.5

4.0

3.5

+5V

2.7V

A

B

3.0

2.5

V_IN

W

V_OUT

+

-

5.5V

2.0

Offset

GND

1.5

-40

0

40

80

120

2.5V DC

Temperature (°C)

FIGURE 2-70:

Nominal EEPROM Write

Cycle Time vs. V_DDand Temperature.

FIGURE 2-72:

-3 db Gain vs. Frequency

Test.

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

floating

V_A

A

V_W

W

I_W

R_BW= V_W/I_W

_W= (V_W-V_A)/I_W

B

R

-40

0

40

80

120

V_B

Temperature (°C)

FIGURE 2-71:

POR/BOR Trip point vs. V_DD

and Temperature.

FIGURE 2-73:

R_BWand R_WMeasurement.

DS22265A-page 37

MCP444X/446X

NOTES:

DS22265A-page 38

MCP444X/446X

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follows.

TABLE 3-1:

PINOUT DESCRIPTION FOR THE MCP444X/446X

Weak

Pull-up/

down

TSSOP

QFN

20L

Standard Function

Buffer

Type

Symbol

I/O

(Note 1)

14L

20L

P3A

P3W

P3B

HVC/A0

SCL

SDA

V_SS

A

I

Analog

No

—

1

2

19

20

1

Potentiometer 3 Terminal A

Potentiometer 3 Wiper Terminal

Potentiometer 3 Terminal B

High Voltage Command / I²C Address 0

I²C Clock Input

2

3

HV w/ST “smart”

3

4

2

I

HV w/ST

P

No

—

4

5

3

5

6

4

I²C Serial Data I/O. Open Drain output

I

—

A

I

6

7

5

Ground

P1B

P1W

P1A

P0A

P0W

P0B

WP

Analog

No

7

8

6

Potentiometer 1 Terminal B

Potentiometer 1 Wiper Terminal

Potentiometer 1 Terminal A

Potentiometer 0 Terminal A

Potentiometer 0 Wiper Terminal

Potentiometer 0 Terminal B

Hardware EEPROM Write Protect

Hardware Reset Pin

8

9

7

—

9

10

11

12

13

14

15

16

17

18

19

20

—

8

9

10

11

12

13

14

15

16

17

18

21

10

—

11

12

13

14

—

HV w/ST “smart”

HV w/ST Yes

HV w/ST “smart”

RESET

A1

I

I²C Address 1

I

V_DD

—

A

—

P

—

No

—

Positive Power Supply Input

Potentiometer 2 Terminal B

Potentiometer 2 Wiper Terminal

Potentiometer 2 Terminal A

Exposed Pad. (Note 2)

P2B

P2W

P2A

EP

Analog

—

Legend:

HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)

A = Analog pins (Potentiometer terminals)

O = digital output

I = digital input (high Z)

I/O = Input / Output

P = Power

Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and

shut-down current.

2: The QFN package has a contact on the bottom of the package. This contact is conductively connected to

the die substrate, and therefore should be unconnected or connected to the same ground as the device’s

V_SSpin.

DS22265A-page 39

MCP444X/446X

3.1

High Voltage Command /

Address 0 (HVC/A0)

3.7

Potentiometer Terminal A

The terminal A pin is available on the MCP44X1

devices, and is connected to the internal

potentiometer’s terminal A.

The HVC/A0 pin is the Address 0 input for the I²C

interface as well as the High Voltage Command pin. At

the device’s POR/BOR the value of the A0 address bit

is latched. This input along with the A1 pin completes

the device address. This allows up to 4 MCP44XX

devices to be on a single I²C bus.

The potentiometer’s terminal A is the fixed connection

to the Full Scale wiper value of the digital

potentiometer. This corresponds to a wiper value of

0x100 for 8-bit devices or 0x80 for 7-bit devices.

During normal operation, the voltage on this pin

determines whether the I²C command is a normal

command or a High Voltage command (when HVC/A0

= V_IHH).

The terminal A pin does not have a polarity relative to

the terminal W or B pins. The terminal A pin can

support both positive and negative current. The voltage

on terminal A must be between V_SSand V_DD

.

The terminal A pin is not available on the MCP44X2

devices, and the internally terminal A signal is floating.

3.2

Serial Clock (SCL)

The SCL pin is the serial interfaces Serial Clock pin.

This pin is connected to the Host Controllers SCL pin.

The MCP44XX is a slave device, so its SCL pin accepts

only external clock signals.

MCP44X1 devices have four terminal A pins, one for

each resistor network. Terminal A is not available on

the MCP44X2 devices.

3.8

Write Protect (WP)

3.3

Serial Data (SDA)

The WP pin is used to force the nonvolatile memory to

be write protected.

The SDA pin is the serial interfaces Serial Data pin.

This pin is connected to the Host Controllers SDA pin.

The SDA pin is an open-drain N-channel driver.

3.9

Reset (RESET)

The RESET pin is used to force the device into the

POR/BOR state.

3.4

Ground (V

)

SS

The V_SSpin is the device ground reference.

3.10 Address 1 (A1)

3.5

Potentiometer Terminal B

The A1 pin is the I²C interface’s Address 1 pin. Along

with the A0 pins, up to 4 MCP44XX devices can be on

a single I²C bus.

The terminal B pin is connected to the internal

potentiometer’s terminal B.

The potentiometer’s terminal B is the fixed connection

to the Zero Scale wiper value of the digital

potentiometer. This corresponds to a wiper value of

0x00 for both 7-bit and 8-bit devices.

3.11 Positive Power Supply Input (V

)

DD

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SS

.

The terminal B pin does not have a polarity relative to

the terminal W or A pins. The terminal B pin can

support both positive and negative current. The voltage

While the device V_DD< V_min(2.7V), the electrical

performance of the device may not meet the data sheet

specifications.

on terminal B must be between V_SSand V_DD

.

MCP44XX devices have four terminal B pins, one for

each resistor network.

3.12 No Connect (NC)

These pins should be either connected to V_DDor V_SS

.

3.6

Potentiometer Wiper (W) Terminal

3.13 Exposed Pad (EP)

The terminal W pin is connected to the internal

potentiometer’s terminal W (the wiper). The wiper

terminal is the adjustable terminal of the digital

potentiometer. The terminal W pin does not have a

polarity relative to terminals A or B pins. The terminal

W pin can support both positive and negative current.

The voltage on terminal W must be between V_SSand

This pad is conductively connected to the device's

substrate. This pad should be tied to the same potential

as the V_SSpin (or left unconnected). This pad could be

used to assist as a heat sink for the device when

connected to a PCB heat sink.

V_DD

.

MCP44XX devices have four terminal W pins, one for

each resistor network.

DS22265A-page 40

MCP444X/446X

4.1.2

BROWN-OUT RESET

4.0

FUNCTIONAL OVERVIEW

When the device powers down, the device V_DDwill

cross the V_POR/V_BORvoltage.

This Data Sheet covers a family of four nonvolatile Dig-

ital Potentiometer and Rheostat devices that will be

referred to as MCP44XX. The MCP44X1 devices are

the Potentiometer configuration, while the MCP44X2

devices are the Rheostat configuration.

Once the V_DDvoltage decreases below the V_POR/V_BOR

voltage, the following happens:

• Serial Interface is disabled

As the Device Block Diagram shows, there are four

main functional blocks. These are:

• EEPROM Writes are disabled

If the V_DDvoltage decreases below the V_RAMvoltage,

the following happens:

• POR/BOR and RESET Operation

• Memory Map

• Volatile wiper registers may become corrupted

• TCON registers may become corrupted

• Resistor Network

• Serial Interface (I²C)

As the voltage recovers above the V_POR/V_BORvoltage,

The POR/BOR operation and the Memory Map are

discussed in this section and the Resistor Network and

I²C operation are described in their own sections. The

Device Commands commands are discussed in

Section 7.0.

see Section 4.1.1 “Power-on Reset”.

Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and

nonvolatile) to become corrupted.

4.1.3

RESET PIN

4.1

POR/BOR and RESET Operation

The RESET pin can be used to force the device into

the POR/BOR state of the device. When the RESET

pin is forced Low, the device is forced into the reset

state. This means that the TCON and STATUS

registers are forced to their default values and the

volatile wiper registers are loaded with the value in the

corresponding Nonvolatile wiper register. Also the I²C

interface is disabled. Any nonvolatile write cycle is not

interrupted, and allowed to complete.

The Power-on Reset is the case where the device is

having power applied to it from V_SS. The Brown-out

Reset occurs when a device had power applied to it,

and that power (voltage) drops below the specified

range.

The devices RAM retention voltage (V_RAM) is lower

than the POR/BOR voltage trip point (V_POR/V_BOR). The

maximum V_POR/V_BORvoltage is less then 1.8V.

This feature allows a hardware method for all registers

to be updated at the same time.

When V_POR/V_BOR< V_DD< 2.7V, the electrical

performance may not meet the data sheet

specifications. In this region, the device is capable of

reading and writing to its EEPROM and incrementing,

decrementing, reading and writing to its volatile

memory if the proper serial command is executed.

4.1.4

INTERACTION OF RESET PIN AND

BOR/POR CIRCUITRY

Figure 4-1 shows how the RESET pin signal and the

POR/BOR signal interact to control the hardware reset

state of the device.

When V_DD< V_POR/V_BORor the RESET pin is Low, the

pin weak pull-ups are enabled.

4.1.1

POWER-ON RESET

RESET (from pin)

Device reset

When the device powers up, the device V_DDwill cross

the V_POR/V_BORvoltage. Once the V_DDvoltage crosses

the V_POR/V_BORvoltage, the following happens:

POR/BOR signal

FIGURE 4-1:

RESET Pin Interaction.

POR/BOR Signal and

• The volatile wiper register is loaded with value in

the corresponding nonvolatile wiper register

• The TCON registers are loaded with their default

value

• The device is capable of digital operation

DS22265A-page 41

MCP444X/446X

4.2

Memory Map

The device memory has 16 locations that are 9-bit wide

(16x9 bits). This memory space contains both volatile

and nonvolatile locations (see Table 4-1).

TABLE 4-1:

Address

MEMORY MAP AND THE SUPPORTED COMMANDS

Memory

Type

Factory

Initialization

Function

Allowed Commands Disallowed Commands ⁽²⁾

—

00h

01h

02h

Volatile Wiper 0

Volatile Wiper 1

RAM

Read, Write,

Increment, Decrement

—

RAM

Read, Write,

Increment, Decrement

—

Nonvolatile Wiper 0 EEPROM

Nonvolatile Wiper 1 EEPROM

Read, Write ⁽¹⁾

Increment, Decrement

8-bit

7-bit

8-bit

7-bit

80h

40h

80h

40h

03h

04h

Read, Write ⁽¹⁾

Increment, Decrement

—

Volatile

TCON0 Register

RAM

Read, Write

Read

—

05h

06h

Status Register

Volatile Wiper 2

RAM

Write, Increment, Decrement

—

Read, Write,

Increment, Decrement

—

07h

08h

Volatile Wiper 3

RAM

Read, Write,

Increment, Decrement

—

Nonvolatile Wiper 2 EEPROM

Nonvolatile Wiper 3 EEPROM

Read, Write ⁽¹⁾

Read, Write

Increment, Decrement

8-bit

7-bit

8-bit

7-bit

80h

40h

80h

40h

09h

0Ah

Increment, Decrement

—

Volatile

RAM

TCON1 Register

0Bh

0Ch

0Dh

0Eh

0Fh

Data EEPROM

EEPROM

Read, Write ⁽¹⁾

Increment, Decrement

000h

Note 1: When an EEPROM write is active, these are invalid commands and will generate an error condition. The

user should use a read of the Status register to determine when the write cycle has completed. To exit the

error condition, the user must take the HVC pin to the V_IHlevel and then back to the active state (V_ILor

V_IHH).

2: This command on this address will generate an error condition. To exit the error condition, the user must

take the HVC pin to the V_IHlevel and then back to the active state (V_ILor V_IHH).

DS22265A-page 42

MCP444X/446X

4.2.1

NONVOLATILE MEMORY

(EEPROM)

4.2.1.4

Special Features

There are 5 nonvolatile bits that are not directly

mapped into the address space. These bits control the

following functions:

This memory can be grouped into two uses of

nonvolatile memory. These are:

• EEPROM Write Protect

• General Purpose Registers

• Nonvolatile Wiper Registers

• WiperLock Technology for Nonvolatile Wiper 0

• WiperLock Technology for Nonvolatile Wiper 1

• WiperLock Technology for Nonvolatile Wiper 2

• WiperLock Technology for Nonvolatile Wiper 3

The nonvolatile wipers start functioning below the

devices V_POR/V_BORtrip point.

4.2.1.1

General Purpose Registers

The operation of WiperLock Technology is discussed in

Section 5.3. The state of the WL0, WL1, WL2, WL3,

and WP bits is reflected in the STATUS register (see

Register 4-1).

These locations allow the user to store up to 5 (9-bit)

locations worth of information.

4.2.1.2

Nonvolatile Wiper Registers

These locations contain the wiper values that are

loaded into the corresponding volatile wiper register

whenever the device has a POR/BOR event. There are

four registers, one for each resistor network.

EEPROM Write Protect

All internal EEPROM memory can be Write Protected.

When EEPROM memory is Write Protected, Write

commands to the internal EEPROM are prevented.

The nonvolatile wiper register enables stand-alone

operation of the device (without Microcontroller control)

after being programmed to the desired value.

Write Protect (WP) can be enabled/disabled by two

methods. These are:

• External WP Hardware pin (MCP44X1 devices

only)

4.2.1.3

Factory Initialization of Nonvolatile

Memory (EEPROM)

• Nonvolatile configuration bit (WP)

The Nonvolatile Wiper values will be initialized to

mid-scale value. This is shown in Table 4-2.

High Voltage commands are required to enable and

disable the nonvolatile WP bit. These commands are

shown in Section 7.8 “Modify Write Protect or

WiperLock Technology (High Voltage)”.

The General purpose EEPROM memory will be

programmed to a default value of 0x000.

It is good practice in the manufacturing flow to

configure the device to your desired settings.

To write to EEPROM, both the external WP pin and the

internal WP EEPROM bit must be disabled. Write

Protect does not block commands to the volatile

registers.

TABLE 4-2:

DEFAULT FACTORY

SETTINGS SELECTION

4.2.2

VOLATILE MEMORY (RAM)

Wiper

Code

There are seven Volatile Memory locations. These are:

• Volatile Wiper 0

• Volatile Wiper 1

• Volatile Wiper 2

8-bit 7-bit

• Volatile Wiper 3

• Status Register

• Terminal Control (TCON0) Register 0

• Terminal Control (TCON)1 Register 1

-502

5.0 kΩ Mid scale 80h 40h Disabled

-103 10.0 kΩ Mid scale 80h 40h Disabled

-503 50.0 kΩ Mid scale 80h 40h Disabled

-104 100.0 kΩ Mid scale 80h 40h Disabled

The volatile memory starts functioning at the RAM

retention voltage (V_RAM).

DS22265A-page 43

MCP444X/446X

4.2.2.1

Status (STATUS) Register

This register contains 7 status bits. These bits show the

state of the WiperLock bits, the Write Protect bit, and if

an EEPROM write cycle is active. The STATUS register

can be accessed via the READ commands. Register 4-

1 describes each STATUS register bit.

The STATUS register is placed at Address 05h.

REGISTER 4-1:

STATUS REGISTER

R-1 R-1

R-1

D8:D7

bit 7

R-1

R-0

R-x

R-1

—

R-x

WP ⁽¹⁾

(1)

WL3

WL2

EEWA

WL1

WL0

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 8-7

bit 6

D8:D7: Reserved. Forced to “1”

WL3: WiperLock Status bit for Resistor Network 3 (Refer to Section 5.3 “WiperLock Technology” for

further information)

The WiperLock Technology bit (WL3) prevents the Volatile and Nonvolatile Wiper 3 addresses and the

TCON1 register bits R3HW, R3A, R3W, and R3B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON1 register bits R3HW, R3A, R3W, and R3B of Resistor Network 3 (Pot 3) are

“Locked” (Write Protected)

0= Wiper and TCON1 of Resistor Network 3 (Pot 3) can be modified

Note:

The WL3 bit always reflects the result of the last programming cycle to the nonvolatile WL3

bit. After a POR/BOR or RESET pin event, the WL3 bit is loaded with the nonvolatile WL3 bit

value.

bit 5

WL2: WiperLock Status bit for Resistor Network 2 (Refer to Section 5.3 “WiperLock Technology” for

further information)

The WiperLock Technology bit (WL2) prevents the Volatile and Nonvolatile Wiper 2 addresses and the

TCON1 register bits R2HW, R2A, R2W, and R2B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON1 register bits R2HW, R2A, R2W, and R2B of Resistor Network 2 (Pot 2) are

“Locked” (Write Protected)

0= Wiper and TCON1 of Resistor Network 2 (Pot 2) can be modified

Note:

The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0

bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the nonvolatile WL0 bit

value.

bit 4

EEWA: EEPROM Write Active Status bit

This bit indicates if the EEPROM Write Cycle is occurring.

1= An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory

locations are allowed (addresses 00h, 01h, 04h, and 05h)

0= An EEPROM Write cycle is NOT currently occurring

Note 1: Requires a High Voltage command to modify the state of this bit (for Nonvolatile devices only). This bit is

not directly written, but reflects the system state (for this feature).

DS22265A-page 44

MCP444X/446X

REGISTER 4-1:

bit 3

STATUS REGISTER (CONTINUED)

WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock Technology” for

further information)

The WiperLock Technology bit (WL1) prevents the Volatile and Nonvolatile Wiper 1 addresses and the

TCON0 register bits R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON0 register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are

“Locked” (Write Protected)

0= Wiper and TCON0 of Resistor Network 1 (Pot 1) can be modified

Note:

The WL1 bit always reflects the result of the last programming cycle to the nonvolatile WL1

bit. After a POR/BOR or RESET pin event, the WL1 bit is loaded with the nonvolatile WL1 bit

value.

bit 2

WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock Technology” for

further information)

The WiperLock Technology bit (WL0) prevents the Volatile and Nonvolatile Wiper 0 addresses and the

TCON0 register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON0 register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are

“Locked” (Write Protected)

0= Wiper and TCON0 of Resistor Network 0 (Pot 0) can be modified

Note:

The WL0 bit always reflects the result of the last programming cycle to the nonvolatile WL0

bit. After a POR/BOR or RESET pin event, the WL0 bit is loaded with the nonvolatile WL0 bit

value.

bit 1

bit 0

Reserved: Forced to “1”

WP: EEPROM Write Protect Status bit (Refer to Section “EEPROM Write Protect” for further

information)

This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is

enabled, writes to all nonvolatile memory are prevented. This includes the General Purpose EEPROM

memory, and the nonvolatile Wiper registers. Write Protect does not block modification of the volatile

wiper register values or the volatile TCON0 and TCON1 register values (via Increment, Decrement, or

Write commands).

This status bit is an OR of the devices Write Protect pin (WP) and the internal nonvolatile WP bit. High

Voltage commands are required to enable and disable the internal WP EEPROM bit.

1= EEPROM memory is Write Protected

0= EEPROM memory can be written

Note 1: Requires a High Voltage command to modify the state of this bit (for Nonvolatile devices only). This bit is

not directly written, but reflects the system state (for this feature).

DS22265A-page 45

MCP444X/446X

The value that is written to the specified TCON register

will appear on the appropriate resistor network

terminals when the serial command has completed.

4.2.2.2

Terminal Control (TCON) Registers

There are two Terminal Control (TCON) Registers.

These are called TCON0 and TCON1. Each register

contains 8 control bits, four bits for each Wiper.

Register 4-2 describes each bit of the TCON0 register,

while Register 4-3 describes each bit of the TCON1

register.

When the WL1 bit is enabled, writes to the TCON0

register bits R1HW, R1A, R1W, and R1B are inhibited.

When the WL0 bit is enabled, writes to the TCON0

register bits R0HW, R0A, R0W, and R0B are inhibited.

The state of each resistor network terminal connection

is individually controlled. That is, each terminal

connection (A, B and W) can be individually connected/

disconnected from the resistor network. This allows the

system to minimize the currents through the digital

potentiometer.

When the WL3 bit is enabled, writes to the TCON1

register bits R3HW, R3A, R3W, and R3B are inhibited.

When the WL2 bit is enabled, writes to the TCON1

register bits R2HW, R2A, R2W, and R2B are inhibited.

On a POR/BOR these registers are loaded with

1FFh (9-bit), for all terminals connected. The Host

Controller needs to detect the POR/BOR event and

then update the Volatile TCON register values.

DS22265A-page 46

MCP444X/446X

REGISTER 4-2:

TCON0 BITS ⁽¹⁾

R-1

D8

R/W-1

R1HW

R/W-1

R1W

R/W-1

R1B

R/W-1

R0HW

R/W-1

R0A

R/W-1

R0W

R/W-1

R0B

R1A

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

bit 7

D8: Reserved. Forced to “1”

R1HW: Resistor 1 Hardware Configuration Control bit

This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin

1= Resistor 1 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 1 is forced to the hardware pin “shutdown” configuration

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network

1= P1A pin is connected to the Resistor 1 Network

0= P1A pin is disconnected from the Resistor 1 Network

R1W: Resistor 1 Wiper (P1W pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network

1= P1W pin is connected to the Resistor 1 Network

0= P1W pin is disconnected from the Resistor 1 Network

R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network

1= P1B pin is connected to the Resistor 1 Network

0= P1B pin is disconnected from the Resistor 1 Network

R0HW: Resistor 0 Hardware Configuration Control bit

This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin

1= Resistor 0 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 0 is forced to the hardware pin “shutdown” configuration

R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network

1= P0A pin is connected to the Resistor 0 Network

0= P0A pin is disconnected from the Resistor 0 Network

R0W: Resistor 0 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network

1= P0W pin is connected to the Resistor 0 Network

0= P0W pin is disconnected from the Resistor 0 Network

R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network

1= P0B pin is connected to the Resistor 0 Network

0= P0B pin is disconnected from the Resistor 0 Network

Note 1: These bits do not affect the wiper register values.

DS22265A-page 47

MCP444X/446X

REGISTER 4-3:

TCON1 BITS ⁽¹⁾

R-1

D8

R/W-1

R3HW

R/W-1

R3W

R/W-1

R3B

R/W-1

R2HW

R/W-1

R2A

R/W-1

R2W

R/W-1

R2B

R3A

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

bit 7

D8: Reserved. Forced to “1”

R3HW: Resistor 3 Hardware Configuration Control bit

This bit forces Resistor 3 into the “shutdown” configuration of the Hardware pin

1= Resistor 3 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 3 is forced to the hardware pin “shutdown” configuration

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R3A: Resistor 3 Terminal A (P3A pin) Connect Control bit

This bit connects/disconnects the Resistor 3 Terminal A to the Resistor 3 Network

1= P3A pin is connected to the Resistor 3 Network

0= P3A pin is disconnected from the Resistor 3 Network

R3W: Resistor 3 Wiper (P3W pin) Connect Control bit

This bit connects/disconnects the Resistor 3 Wiper to the Resistor 3 Network

1= P3W pin is connected to the Resistor 3 Network

0= P3W pin is disconnected from the Resistor 3 Network

R3B: Resistor 3 Terminal B (P3B pin) Connect Control bit

This bit connects/disconnects the Resistor 3 Terminal B to the Resistor 3 Network

1= P3B pin is connected to the Resistor 3 Network

0= P3B pin is disconnected from the Resistor 3 Network

R2HW: Resistor 2 Hardware Configuration Control bit

This bit forces Resistor 2 into the “shutdown” configuration of the Hardware pin

1= Resistor 2 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 2 is forced to the hardware pin “shutdown” configuration

R2A: Resistor 2 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 2 Terminal A to the Resistor 2 Network

1= P2A pin is connected to the Resistor 2 Network

0= P2A pin is disconnected from the Resistor 2 Network

R2W: Resistor 2 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 2 Wiper to the Resistor 2 Network

1= P2W pin is connected to the Resistor 2 Network

0= P2W pin is disconnected from the Resistor 2 Network

R2B: Resistor 2 Terminal B (P2B pin) Connect Control bit

This bit connects/disconnects the Resistor 2 Terminal B to the Resistor 2 Network

1= P2B pin is connected to the Resistor 2 Network

0= P2B pin is disconnected from the Resistor 2 Network

Note 1: These bits do not affect the wiper register values.

DS22265A-page 48

MCP444X/446X

5.1

Resistor Ladder Module

5.0

RESISTOR NETWORK

The resistor ladder is a series of equal value resistors

(R_S) with a connection point (tap) between the two

resistors. The total number of resistors in the series

(ladder) determines the R_ABresistance (see Figure 5-

1). The end points of the resistor ladder are connected

to analog switches which are connected to the device

Terminal A and Terminal B pins. The R_AB(and R_S)

resistance has small variations over voltage and

temperature.

The Resistor Network has either 7-bit or 8-bit

resolution. Each Resistor Network allows zero scale to

full scale connections. Figure 5-1 shows a block

diagram for the resistive network of a device.

The Resistor Network is made up of several parts.

These include:

• Resistor Ladder

• Wiper

• Shutdown (Terminal Connections)

For an 8-bit device, there are 256 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 256 resistors, thus

providing 257 possible settings (including terminal A

and terminal B).

Devices have four resistor networks. These are

referred to as Pot 0, Pot 1 Pot 2, and Pot 3.

A

For a 7-bit device, there are 128 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 128 resistors, thus

providing 129 possible settings (including terminal A

and terminal B).

8-Bit

N =

7-Bit

N =

128

257

(100h)

(80h)

(1)

R_W

R_S

Equation 5-1 shows the calculation for the step

resistance.

256

(FFh)

127

(7Fh)

(1)

R_W

EQUATION 5-1:

R_SCALCULATION

255

(FEh)

126

(7Eh)

R_AB

R_S= -------------

8-bit Device

R_AB

(256)

W

R_AB

R_S= -------------

7-bit Device

(128)

1

(01h)

(1)

R_W

R_S

0

(00h)

Analog Mux

B

Note 1: The wiper resistance is dependent on

several factors including, wiper code,

device V_DD, Terminal voltages (on A, B,

and W), and temperature.

Also for the same conditions, each tap

selection resistance has a small variation.

This R_Wvariation has greater effects on

some specifications (such as INL) for the

smaller resistance devices (5.0 kΩ)

compared to larger resistance devices

(100.0 kΩ).

FIGURE 5-1:

Resistor Block Diagram.

DS22265A-page 49

MCP444X/446X

5.2

Wiper

5.3

WiperLock Technology

Each tap point (between the R_Sresistors) is a

connection point for an analog switch. The opposite

side of the analog switch is connected to a common

signal which is connected to the Terminal W (Wiper)

pin.

The MCP44XX device’s WiperLock technology allows

application-specific calibration settings to be secured in

the EEPROM without requiring the use of an additional

write-protect pin. There are four WiperLock Technology

configuration bits (WL0, WL1, WL2, and WL3). These

bits prevent the Nonvolatile and Volatile addresses and

bits for the specified resistor network from being writ-

ten.

A value in the volatile wiper register selects which

analog switch to close, connecting the W terminal to

the selected node of the resistor ladder.

The WiperLock technology prevents the serial

commands from doing the following:

The wiper can connect directly to Terminal B or to

Terminal A. A zero scale connections, connects the

Terminal W (wiper) to Terminal B (wiper setting of

000h). A full scale connection, connects the Terminal W

(wiper) to Terminal A (wiper setting of 100h or 80h). In

these configurations, the only resistance between the

Terminal W and the other Terminal (A or B) is that of the

analog switches.

• Changing a volatile wiper value

• Writing to the specified nonvolatile wiper memory

location

• Changing the related volatile TCON register bits

For either Resistor Network 0, Resistor Network 1,

Resistor Network 2, or Resistor Network 3 (Potx), the

WLx bit controls the following:

A wiper setting value greater than full scale (wiper

setting of 100h for 8-bit device or 80h for 7-bit devices)

will also be a Full Scale setting (Terminal W (wiper)

connected to Terminal A). Table 5-1 illustrates the full

wiper setting map.

• Nonvolatile Wiper Register

• Volatile Wiper Register

• Volatile TCON register bits RxHW, RxA, RxW, and

RxB

Equation 5-2 illustrates the calculation used to

determine the resistance between the wiper and

terminal B.

High Voltage commands are required to enable and

disable WiperLock. Please refer to the Modify Write

Protect or WiperLock Technology (High Voltage)

command for operation.

EQUATION 5-2:

R_WBCALCULATION

5.3.1

POR/BOR OPERATION WHEN

WIPERLOCK TECHNOLOGY

ENABLED

R_AB

N

R_WB= ------------- + R_W

8-bit Device

(256)

N = 0 to 256 (decimal)

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the

Volatile Wiper register value with the Nonvolatile Wiper

register value, refer to Section 4.1.

R_AB

N

7-bit Device

R_WB= ------------- + R_W

(128)

N = 0 to 128 (decimal)

TABLE 5-1:

Wiper Setting

VOLATILE WIPER VALUE VS.

WIPER POSITION MAP

Properties

7-bit

8-bit

3FFh – 3FFh – Reserved (Full Scale (W = A)),

081h

101h Increment and Decrement

commands ignored

080h

100h Full Scale (W = A),

Increment commands ignored

07Fh – 0FFh – W = N

041h

081h

040h

080h W = N (Mid Scale)

03Fh – 07Fh – W = N

001h

000h

000h Zero Scale (W = B)

Decrement command ignored

DS22265A-page 50

MCP444X/446X

The RxHW bit does NOT corrupt the values in the

Volatile Wiper Registers nor the TCON register. When

the Shutdown mode is exited (RxHW bit = “1”):

5.4

Shutdown

Shutdown is used to minimize the device’s current

consumption. The MCP44XX has one method to

achieve this. This is:

• The device returns to the Wiper setting specified

by the Volatile Wiper value

• The TCON register bits return to controlling the

terminal connection state

• Terminal Control Register (TCON)

This is different from the MCP42XXX devices in that the

Hardware Shutdown Pin (SHDN) has been replaced by

a RESET pin. The Hardware Shutdown Pin function is

still available via software commands to the TCON

register.

A

W

5.4.1

TERMINAL CONTROL REGISTER

(TCON)

The Terminal Control (TCON) register is a volatile

register used to configure the connection of each

resistor network terminal pin (A, B, and W) to the

Resistor Network. These registers are shown in

Register 4-2 and Register 4-3.

B

FIGURE 5-2:

Resistor Network Shutdown

State (RxHW = ‘0’).

The RxHW bits forces the selected resistor network

into the same state as the MCP42X1’s SHDN pin.

Alternate low power configurations may be achieved

with the RxA, RxW, and RxB bits.

When the RxHW bit is “0”:

• The P0A, P1A, P2A, and P3A terminals are

disconnected

• The P0W, P1W, P2W, and P3W terminals are

simultaneously connect to the P0B, P1B, P2B,

and P3B terminals, respectively (see Figure 5-2)

Note:

When the RxHW bit forces the resistor

network into the hardware SHDN state,

the state of the TCON0 or TCON1

register’s RxA, RxW, and RxB bits is

overridden (ignored). When the state of

the RxHW bit no longer forces the resistor

network into the hardware SHDN state,

the TCON0 or TCON1 register’s RxA,

RxW, and RxB bits return to controlling the

terminal connection state. In other words,

the RxHW bit does not corrupt the state of

the RxA, RxW, and RxB bits.

DS22265A-page 51

MCP444X/446X

NOTES:

DS22265A-page 52

MCP444X/446X

2

6.1

Signal Descriptions

6.0

SERIAL INTERFACE (I C)

The I²C interface uses up to four pins (signals). These

are:

The MCP44XX devices support the I²C serial protocol.

The MCP44XX I²C’s module operates in Slave mode

(does not generate the serial clock).

Figure 6-1 shows a typical I²C Interface connection. All

I²C interface signals are high-voltage tolerant.

• SDA (Serial Data)

• SCL (Serial Clock)

• A0 (Address 0 bit)

• A1 (Address 1 bit)

The MCP44XX devices use the two-wire I²C serial

interface. This interface can operate in standard, fast or

High-Speed mode. A device that sends data onto the

bus is defined as transmitter, and a device receiving

data as receiver. The bus has to be controlled by a

master device which generates the serial clock (SCL),

controls the bus access and generates the START and

STOP conditions. The MCP44XX device works as

slave. Both master and slave can operate as

transmitter or receiver, but the master device

determines which mode is activated. Communication is

initiated by the master (microcontroller) which sends

the START bit, followed by the slave address byte. The

first byte transmitted is always the slave address byte,

which contains the device code, the address bits, and

the R/W bit.

6.1.1

SERIAL DATA (SDA)

The Serial Data (SDA) signal is the data signal of the

device. The value on this pin is latched on the rising

edge of the SCL signal when the signal is an input.

With the exception of the START and STOP conditions,

the high or low state of the SDA pin can only change

when the clock signal on the SCL pin is low. During the

high period of the clock, the SDA pin’s value (high or

low) must be stable. Changes in the SDA pin’s value

while the SCL pin is HIGH will be interpreted as a

START or a STOP condition.

6.1.2

SERIAL CLOCK (SCL)

The Serial Clock (SCL) signal is the clock signal of the

device. The rising edge of the SCL signal latches the

value on the SDA pin. The MCP44XX supports three

I²C interface clock modes:

Refer to the Phillips I²C document for more details of

the I²C specifications.

Typical I²C Interface Connections

• Standard Mode: clock rates up to 100 kHz

• Fast Mode: clock rates up to 400 kHz

• High-Speed Mode (HS mode): clock rates up to

3.4 MHz

MCP4XXX

SCL

Host

Controller

SCL

The MCP44XX will not stretch the clock signal (SCL)

since memory read access occur fast enough.

SDA

I/O ⁽¹⁾

HVC/A0 ⁽²⁾

A1 ^{(2, 3)}

Depending on the clock rate mode, the interface will

display different characteristics.

6.1.3

THE ADDRESS BITS (A1:A0)

Note 1: If High voltage commands are desired,

some type of external circuitry needs to

be implemented.

There are up to two hardware pins used to specify the

device address. The number of address pins is

determined by the part number.

2: These pins have internal pull-ups. If

faster rise times are required, then

external pull-ups should be added.

Address 0 is multiplexed with the High Voltage

Command (HVC) function. So the state of A0 is latched

on the MCP4XXX’s POR/BOR event.

3: This pin could be tied high, low, or

connected to an I/O pin of the Host

Controller.

The state of the A1 pin should be static, that is they

should be tied high or tied low.

6.1.3.1

The High Voltage Command (HVC)

Signal

FIGURE 6-1:

Typical I²C Interface Block

Diagram.

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage mode. High Voltage commands allow

the device’s WiperLock Technology and write protect

features to be enabled and disabled.

The HVC pin has an internal resistor connection to the

MCP44XXs internal V_DDsignal.

DS22265A-page 53

MCP444X/446X

2

6.2.1.3

Acknowledge (A) Bit

6.2

I C Operation

The MCP44XX’s I²C module is compatible with the

Philips I²C specification. The following lists some of the

modules features:

The A bit (see Figure 6-4) is typically a response from

the receiving device to the transmitting device.

Depending on the context of the transfer sequence, the

A bit may indicate different things. Typically the Slave

device will supply an A response after the Start bit and

8 “data” bits have been received. an A bit has the SDA

signal low.

• 7-bit slave addressing

• Supports three clock rate modes:

- Standard mode, clock rates up to 100 kHz

- Fast mode, clock rates up to 400 kHz

- High-speed mode (HS mode), clock rates up

to 3.4 MHz

• Support Multi-Master Applications

• General call addressing

• Internal weak pull-ups on interface signals

SDA

SCL

D0

A

8

9

The I²C 10-bit addressing mode is not supported.

FIGURE 6-4:

Acknowledge Waveform.

The Philips I²C specification only defines the field

types, field lengths, timings, etc. of a frame. The frame

content defines the behavior of the device. The frame

content for the MCP44XX is defined in Section 7.0.

Not A (A) Response

The A bit has the SDA signal high. Table 6-1 shows

some of the conditions where the Slave Device will

issue a Not A (A).

6.2.1

I²C BIT STATES AND SEQUENCE

Figure 6-8 shows the I²C transfer sequence. The serial

clock is generated by the master. The following defini-

tions are used for the bit states:

If an error condition occurs (such as an A instead of A),

then an START bit must be issued to reset the

command state machine.

• Start bit (S)

• Data bit

• Acknowledge (A) bit (driven low) /

No Acknowledge (A) bit (not driven low)

• Repeated Start bit (Sr)

• Stop bit (P)

TABLE 6-1:

MCP45XX/MCP46XX A / A

RESPONSES

Acknowledge

Event

Bit

Comment

Response

6.2.1.1

Start Bit

General Call

A

Only if GCEN bit is

set

The Start bit (see Figure 6-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “High”.

Slave Address

valid

Slave Address

not valid

2nd Bit

1st Bit

SDA

SCL

Device Mem-

ory Address

and specified

command

After device has

received address

and command

S

FIGURE 6-2:

Start Bit.

(AD3:AD0 and

C1:C0) are an

invalid combi-

nation

6.2.1.2 Data Bit

The SDA signal may change state while the SCL signal

is Low. While the SCL signal is High, the SDA signal

MUST be stable (see Figure 6-5).

Communica-

tion during

EEPROM write

cycle

A

After device has

received address

and command,

and valid condi-

tions for EEPROM

write

2nd Bit

1st Bit

SDA

SCL

Bus Collision

N.A.

I²C Module

Resets, or a “Don’t

Care” if the colli-

sion occurs on the

Master’s “Start bit”

Data Bit

FIGURE 6-3:

Data Bit.

DS22265A-page 54

MCP444X/446X

6.2.1.4

Repeated Start Bit

6.2.1.5

Stop Bit

The Repeated Start bit (see Figure 6-5) indicates the

current Master Device wishes to continue communicat-

ing with the current Slave Device without releasing the

I²C bus. The Repeated Start condition is the same as

the Start condition, except that the Repeated Start bit

follows a Start bit (with the Data bits + A bit) and not a

Stop bit.

The Stop bit (see Figure 6-6) Indicates the end of the

I²C Data Transfer Sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is “High”.

A Stop bit resets the I²C interface of all MCP44XX

devices.

A / A

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “High”.

SDA

SCL

P

Note 1: A bus collision during the Repeated Start

condition occurs if:

FIGURE 6-6:

Stop Condition Receive or

Transmit Mode.

• SDA is sampled low when SCL goes

from low to high.

6.2.2

CLOCK STRETCHING

• SCL goes low before SDA is asserted

low. This may indicate that another

master is attempting to transmit a

data "1".

“Clock Stretching” is something that the receiving

Device can do, to allow additional time to “respond” to

the “data” that has been received.

The MCP44XX will not stretch the clock signal (SCL)

since memory read access occur fast enough.

6.2.3

ABORTING A TRANSMISSION

1st Bit

SDA

SCL

If any part of the I²C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a START or STOP condition. This is

done so that noisy transmissions (usually an extra

START or STOP condition) are aborted before they

corrupt the device.

Sr = Repeated Start

FIGURE 6-5:

Repeat Start Condition

Waveform.

SDA

SCL

S

1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A / A

P

FIGURE 6-7:

Typical 8-Bit I²C Waveform Format.

SDA

SCL

Data allowed

to change

Data or

A valid

STOP

Condition

START

Condition

FIGURE 6-8:

I²C Data States and Bit Sequence.

DS22265A-page 55

MCP444X/446X

6.2.4

ADDRESSING

Slave Address

The address byte is the first byte received following the

START condition from the master device. The address

contains four (or more) fixed bits and (up to) three user

defined hardware address bits (pins A1 and A0). These

7-bits address the desired I²C device. The A6:A2

address bits are fixed to “01011” and the device

appends the value of following two address pins (A1

and A0).

S

A6 A5 A4 A3 A2 A1 A0 R/W

A/A

“0”“1” “0”“1” “1”

See Table 6-2

Start

bit

R/W bit

R/W = 0= write

R/W = 1= read

A bit (controlled by slave device)

Since there are address bits controlled by hardware

pins, there may be up to four MCP44XX devices on the

same I²C bus.

A = 0= Slave Device Acknowledges byte

A = 1= Slave Device does not Acknowledge byte

FIGURE 6-9:

Slave Address Bits in the

Figure 6-9 shows the slave address byte format, which

contains the seven address bits. There is also a read/

write (R/W) bit. Table 6-2 shows the fixed address for

device.

I²C Control Byte.

TABLE 6-2:

DEVICESLAVE ADDRESSES

Device

Address Comment

MCP44XX ‘0101 1’b + A1:A0 Supports up to 4

devices. (Note 1)

Hardware Address Pins

Note 1: A0 is used for High-Voltage commands

(HVC/A0) and the value is latched at

POR/BOR.

The hardware address bits (A1, and A0) correspond to

the logic level on the associated address pins. This

allows up to eight devices on the bus.

These pins have a weak pull-up enabled when the V_DD

< V_BOR. The weak pull-up utilizes the “smart” pull-up

technology and exhibits the same characteristics as the

High-voltage tolerant I/O structure.

6.2.5

SLOPE CONTROL

The MCP44XX implements slope control on the SDA

output.

As the device transitions from HS mode to FS mode,

the slope control parameter will change from the HS

specification to the FS specification.

The state of the A0 address pin is latch on POR/BOR.

This is required since High Voltage commands force

this pin (HVC/A0) to the V_IHHlevel.

For Fast (FS) and High-Speed (HS) modes, the device

has a spike suppression and a Schmidt trigger at SDA

and SCL inputs.

DS22265A-page 56

MCP444X/446X

After switching to the High-Speed mode, the next

transferred byte is the I²C control byte, which specifies

the device to communicate with, and any number of

data bytes plus acknowledgements. The Master

Device can then either issue a Repeated Start bit to

address a different device (at High-Speed) or a Stop bit

to return to Fast/Standard bus speed. After the Stop bit,

any other Master Device (in a Multi-Master system) can

arbitrate for the I²C bus.

6.2.6

HS MODE

The I²C specification requires that a high-speed mode

device must be ‘activated’ to operate in high-speed

(3.4 Mbit/s) mode. This is done by the Master sending

a special address byte following the START bit. This

byte is referred to as the high-speed Master Mode

Code (HSMMC).

The MCP44XX device does not acknowledge this byte.

However, upon receiving this command, the device

switches to HS mode. The device can now

communicate at up to 3.4 Mbit/s on SDA and SCL

lines. The device will switch out of the HS mode on the

next STOP condition.

See Figure 6-10 for illustration of HS mode command

sequence.

For more information on the HS mode, or other I²C

modes, please refer to the Phillips I²C specification.

The master code is sent as follows:

1. START condition (S)

6.2.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

clock modes of the interface.

2. High-Speed Master Mode Code (0000 1XXX),

The XXXbits are unique to the high-speed (HS)

mode Master.

6.2.6.2

Pulse Gobbler

3. No Acknowledge (A)

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

F/S-mode

HS-mode

P

F/S-mode

S ‘0 0 0 0 1 X X X’b A Sr ‘Slave Address’R/W A

“Data”

A/A

HS-mode continues

Sr ‘Slave Address’R/W A

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

P = Stop bit (Stop condition terminates HS Mode)

FIGURE 6-10: HS Mode Sequence.

DS22265A-page 57

MCP444X/446X

6.2.7

GENERAL CALL

TABLE 6-3:

7-bit

GENERALCALLCOMMANDS

Comment

The General Call is a method that the “Master” device

can communicate with all other “Slave” devices. In a

Multi-Master application, the other Master devices are

operating in Slave mode. The General Call address

has two documented formats. These are shown in

Figure 6-11. We have added a MCP44XX format in this

figure as well.

This will allow customers to have multiple I²C Digital

Potentiometers on the bus and have them operate in a

synchronous fashion (analogous to the DAC Sync pin

functionality). If these MCP44XX 7-bit commands

conflict with other I²C devices on the bus, then the

customer will need two I²C busses and ensure that the

devices are on the correct bus for their desired

application functionality.

Command

(1, 2, 3)

‘100000d’b Write Next Byte (Third Byte) to Volatile

Wiper 0 Register

‘100100d’b Write Next Byte (Third Byte) to Volatile

Wiper 1 Register

‘110000d’b Write Next Byte (Third Byte) to TCON

Register

‘1000010’b Increment Wiper 0 Register

or

‘1000011’b

‘1001010’b Increment Wiper 1 Register

or

Dual Pot devices can not update both Pot0 and Pot1

from a single command. To address this, there are

General Call commands for the Wiper 0, Wiper 1, and

the TCON registers.

‘1001011’b

‘1000100’b Decrement Wiper 0 Register

or

‘1000101’b

Table 6-3 shows the General Call Commands. Three

commands are specified by the I²C specification and

are not applicable to the MCP44XX (so command is

Not Acknowledged) The MCP44XX General Call

Commands are Acknowledge. Any other command is

Not Acknowledged.

‘1001100’b Decrement Wiper 1 Register

or

‘1001101’b

Note 1: Any other code is Not Acknowledged.

These codes may be used by other

devices on the I²C bus.

Note:

Only one General Call command per issue

of the General Call control byte. Any

additional General Call commands are

ignored and Not Acknowledged.

2: The 7-bit command always appends a “0”

to form 8-bits.

3: “d” is the D8 bit for the 9-bit write value.

DS22265A-page 58

MCP444X/446X

Second Byte

S

0

A

X

0

A P

General Call Address

“7-bit Command”

Reserved 7-bit Commands (By I²C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000)

‘0000 011’b - Reset and write programmable part of slave address by hardware.

‘0000 010’b - Write programmable part of slave address by hardware.

‘0000 000’b - NOT Allowed

MCP44XX 7-bit Commands

‘1000 01x’b - Increment Wiper 0 Register.

‘1001 01x’b - Increment Wiper 1 Register.

‘1000 10x’b - Decrement Wiper 0 Register.

‘1001 10x’b - Decrement Wiper 1 Register.

The Following is a Microchip Extension to this General Call Format

Third Byte

Second Byte

S

0

A

X

d

0

A d

d

A

P

General Call Address

MCP44XX 7-bit Commands

“7-bit Command”

“0” for General Call Command

‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register.

‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register.

‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register.

The Following is a “Hardware General Call” Format

n occurrences of (Data + A)

A X X X X X X X X A P

Second Byte

S

0

A

X

1

General Call Address

“7-bit Command”

This indicates a “Hardware General Call”

MCP44XX will ignore this byte and

all following bytes (and A), until

a Stop bit (P) is encountered.

FIGURE 6-11:

General Call Formats.

DS22265A-page 59

MCP444X/446X

NOTES:

DS22265A-page 60

MCP444X/446X

Normal serial commands are those where the HVC pin

is driven to V_IHor V_IL. With High-Voltage Serial

Commands, the HVC pin is driven to V_IHH. In each

mode, there are four possible commands.

7.0

DEVICE COMMANDS

The MCP44XX’s I²C command formats are specified in

this section. The I²C protocol does not specify how

commands are formatted.

Additionally, there are two commands used to enable

or disable the special features (Write Protect and Wiper

Lock Technology) of the device. The commands are

special cases of the Increment and Decrement

High-Voltage Serial Command.

The MCP44XX supports four basic commands. The

location accessed determines the commands that are

supported.

For the Volatile Wiper Registers, these commands are:

Table 7-2 shows the supported commands for each

memory location.

• Write Data

• Read Data

• Increment Data

• Decrement Data

Table 7-3 shows an overview of all the device

commands and their interaction with other device

features.

For the Nonvolatile wiper EEPROM, general purpose

data EEPROM, and the TCON Register, these

commands are:

7.1

Command Byte

• Write Data

• Read Data

The MCP44XX’s Command Byte has three fields: the

Address, the Command Operation, and 2 Data bits

(see Figure 7-1). Currently only one of the data bits is

defined (D8).

These commands have formats for both a single

command or continuous commands. These commands

are shown in Table 7-1.

The device memory is accessed when the Master

sends a proper Command Byte to select the desired

operation. The memory location getting accessed is

contained in the Command Byte’s AD3:AD0 bits. The

action desired is contained in the Command Byte’s

C1:C0 bits, see Figure 7-1. C1:C0 determines if the

desired memory location will be read, written,

Incremented (wiper setting +1) or Decremented (wiper

setting -1). The Increment and Decrement commands

are only valid on the volatile wiper registers, and in

High Voltage commands to enable/disable WiperLock

Technology and Software Write Protect.

Each command has two operational states. The

operational state determines if the device commands

control the special features (Write Protect and

WiperLock Technology). These operational states are

referred to as:

• Normal Serial Commands

• High-Voltage Serial Commands

TABLE 7-1:

I²C COMMANDS

Command

Operates on

Volatile/

# of Bit

If the Address bits and Command bits are not a valid

combination, then the MCP44XX will generate a Not

Acknowledge pulse to indicate the invalid combination.

The I²C Master device must then force a Start

Condition to reset the MCP44XX’s I²C module.

Clocks⁽¹⁾Nonvolatile

memory

Operation

Mode

Write Data

Single

29

Both

Continuous 18n + 11 Volatile Only

D9 and D8 are the most significant bits for the digital

potentiometer’s wiper setting. The 8-bit devices utilize

D8 as their MSb while the 7-bit devices utilize D7 (from

the data byte) as their MSb.

Read Data

Single

29

48

Both

Random

Continuous 18n + 11 Both ⁽²⁾

Single 20 Volatile Only

Continuous 9n + 11 Volatile Only

20 Volatile Only

Increment

(3)

COMMAND BYTE

Decrement Single

(3)

A

D

3

A

D

2

A

D

1

A

D

0

C

1

C

0

D

9

D

8

A

Continuous 9n + 11 Volatile Only

Note 1: “n” indicates the number of times the

command operation is to be repeated.

MSbits (Data)

MCP4XXX

Memory Address

2: This command is useful to determine if a

nonvolatile memory write cycle has

completed.

Command Operation bits

00= Write Data

01= Increment

10= Decrement

11= Read Data

3: High Voltage Increment and Decrement

commands on select nonvolatile memory

locations enable/disable WiperLock

Technology and the software Write

Protect feature.

FIGURE 7-1:

Command Byte Format.

DS22265A-page 61

MCP444X/446X

TABLE 7-2:

MEMORY MAP AND THE SUPPORTED COMMANDS

Address

Data

(10-bits)

Command

Comment

(1)

Value

Function

Write Data

Read Data

nn nnnn nnnn

—

00h

Volatile Wiper 0

3

(

)

Increment Wiper

Decrement Wiper

Write Data

—

nn nnnn nnnn

—

01h

02h

03h

Volatile Wiper 1

NV Wiper 0

3

(

)

Read Data

Increment Wiper

Decrement Wiper

Write Data

—

nn nnnn nnnn

—

3

(

)

Read Data

4

(

)

High Voltage Increment

High Voltage Decrement

Write Data

Wiper Lock 0 Disable

Wiper Lock 0 Enable

(5)

—

nn nnnn nnnn

—

NV Wiper 1

3

(

)

Read Data

4

(

)

High Voltage Increment

High Voltage Decrement

Write Data

Wiper Lock 1 Disable

Wiper Lock 1 Enable

(5)

—

(2)

nn nnnn nnnn

—

04h

Volatile

TCON 0 Register

3

(

)

Read Data

Write Data

Read Data

3

(

(2)

)

05h

Status Register

Volatile Wiper 2

06h

07h

08h

09h

(3)

Increment Wiper

Decrement Wiper

Write Data

—

nn nnnn nnnn

—

Volatile Wiper 3

NV Wiper 2

(3)

Read Data

Increment Wiper

Decrement Wiper

Write Data

—

nn nnnn nnnn

—

(3)

Read Data

4

(

)

High Voltage Increment

High Voltage Decrement

Write Data

Wiper Lock 2 Disable

Wiper Lock 2 Enable

5

(

)

—

nn nnnn nnnn

—

NV Wiper 3

(3)

Read Data

4

(

)

High Voltage Increment

High Voltage Decrement

Write Data

Wiper Lock 3 Disable

Wiper Lock 3 Enable

5

(

)

—

(2)

nn nnnn nnnn

—

0Ah

Volatile

TCON 1 Register

(3)

Read Data

(2)

Write Data

0Bh

Data EEPROM

3

(

)

Read Data

Write Data

Read Data

Write Data

Read Data

Write Data

Read Data

Write Data

Read Data

(2)

0Ch

(3)

(2)

0Dh

3

(

)

(2)

0Eh

(3)

0Fh

3

(

)

4

(

)

High Voltage Increment

High Voltage Decrement

Write Protect Disable

Write Protect Enable

(5)

—

Note 1:

The Data Memory is only 9-bits wide, so the MSb is ignored by the device.

Increment or Decrement commands are invalid for these addresses.

2:

3:

4:

5:

I²C read operation will read 2 bytes, of which the 10-bits of data are contained within.

Disables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or disables Write Protect.

Enables WiperLock Technology for wiper 0, wiper 1, wiper 2, wiper3, or enables Write Protect.

DS22265A-page 62

MCP444X/446X

7.2

Data Byte

7.3

Error Condition

Only the Read Command and the Write Command

have Data Byte(s).

If the four address bits received (AD3:AD0) and the two

command bits received (C1:C0) are

a

valid

combination, the MCP44XX will Acknowledge the I²C

bus.

The Write command concatenates the 8 bits of the

Data Byte with the one data bit (D8) contained in the

Command Byte to form 9 bits of data (D8:D0). The

Command Byte format supports up to 9 bits of data so

that the 8-bit resistor network can be set to Full-Scale

(100h or greater). This allows wiper connections to

Terminal A and to Terminal B. The D9 bit is currently

unused.

If the address bits and command bits are an invalid

combination, then the MCP44XX will Not Acknowledge

the I²C bus.

Once an error condition has occurred, any following

commands are ignored until the I²C bus is reset with a

Start Condition.

7.3.1

ABORTING A TRANSMISSION

A Restart or Stop condition in the expected data bit

position will abort the current command sequence and

data will not be written to the MCP44XX.

TABLE 7-3:

COMMANDS

High

Voltage

Works

when

Wiper is

“locked”?

Writes

Value in

EEPROM

Impact on

WiperLock or

Write Protect

Operates on Volatile/

Command Name

Nonvolatile memory (V_IHH) on

HVC pin?

Write Data

Yes ⁽¹⁾

—

Both

—

unlocked ⁽¹⁾

unchanged

No

Yes

No

Yes

Read Data

Increment Wiper

—

Volatile Only

Both

—

Decrement Wiper

—

High Voltage Write Data

High Voltage Read Data

High Voltage Increment Wiper

High Voltage Decrement Wiper

Yes

—

Yes

Both

—

Volatile Only

Nonvolatile Only ⁽²⁾

—

(2)

Modify Write Protect or WiperLock

Technology (High Voltage) - Enable

—

locked/

protected ⁽²⁾

(3)

Modify Write Protect or WiperLock

Technology (High Voltage) - Disable

—

Nonvolatile Only ⁽³⁾

Yes

unlocked/

Yes

unprotected ⁽³⁾

Note 1: This command will only complete, if wiper is “unlocked” (WiperLock Technology is Disabled).

2: If the command is executed using address 02h, 03h 08h, or 09h; that corresponding wiper is locked or

if with address 0Fh, then Write Protect is enabled.

3: If the command is executed using with address 02h, 03h 08h, or 09h; that corresponding wiper is unlocked

or if with address 0Fh, then Write Protect is disabled.

DS22265A-page 63

MCP444X/446X

7.4.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

7.4

Write Data

Normal and High Voltage

A continuous write mode of operation is possible when

writing to the volatile memory registers (address 00h,

01h, 04h, 06h, 07h, and 0Ah). This continuous write

mode allows writes without a Stop or Restart condition

or repeated transmissions of the I²C Control Byte.

Figure 7-3 shows the sequence for three continuous

writes. The writes do not need to be to the same volatile

memory address. The sequence ends with the master

sending a STOP or RESTART condition.

The Write Command can be issued to both the Volatile

and Nonvolatile memory locations. The format of the

command, see Figure 7-2, includes the I²C Control

Byte, an A bit, the MCP44XX Command Byte, an A bit,

the MCP44XX Data Byte, an A bit, and a Stop (or

Restart) condition. The MCP44XX generates the A / A

bits.

A Write command to a Volatile memory location

changes that location after a properly formatted Write

Command and the A / A clock have been received.

7.4.4

CONTINUOUS WRITES TO

NONVOLATILE MEMORY

A Write command to a Nonvolatile memory location will

only start a write cycle after a properly formatted Write

Command have been received and the Stop condition

has occurred.

If a continuous write is attempted on Nonvolatile

memory, the missing Stop condition will cause the

command to be an error condition (A). A Start bit is

required to reset the command state machine.

Note:

Writes to certain memory locations will be

dependant on the state of the WiperLock

Technology bits and the Write Protect bit.

7.4.5

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage operational state. High Voltage

commands allow the device’s WiperLock Technology

and write protect features to be enabled and disabled.

7.4.1

SINGLE WRITE TO VOLATILE

MEMORY

For volatile memory locations, data is written to the

MCP44XX after every byte transfer (during the

Acknowledge). If a Stop or Restart condition is

generated during a data transfer (before the A), the

data will not be written to the MCP44XX. After the A bit,

the master can initiate the next sequence with a Stop or

Restart condition.

The HVC pin has an internal resistor connection to the

MCP44XXs internal V_DDsignal.

Refer to Figure 7-2 for the byte write sequence.

7.4.2

SINGLE WRITE TO NONVOLATILE

MEMORY

The sequence to write to a single nonvolatile memory

location is the same as a single write to volatile memory

with the exception that the EEPROM write cycle (t_wc) is

started after a properly formatted command, including

the Stop bit, is received. After the Stop condition

occurs, the serial interface may immediately be

re-enabled by initiating a Start condition.

During an EEPROM write cycle, access to the volatile

memory (addresses 00h, 01h, 04h, 05h, 06h, 07h, and

0Ah) is allowed when using the appropriate command

sequence. Commands that address nonvolatile

memory are ignored until the EEPROM write cycle (t_wc

)

completes. This allows the Host Controller to operate

on the Volatile Wiper registers, the TCON register, and

to Read the Status Register. The EEWA bit in the

Status register indicates the status of an EEPROM

Write Cycle.

Once a write command to a Nonvolatile memory

location has been received, no other commands should

be received before the Stop condition occurs.

Figure 7-2 shows the waveform for a single write.

DS22265A-page 64

MCP444X/446X

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Write “Data” bits

Command

AD AD AD AD

S

0

1

0

1

1 A1 A0 0

A

0 0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P

3

2

1

0

WRITE Command

Write Data bits

Control Byte

FIGURE 7-2:

I²C Write Sequence.

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Write “Data” bits

Command

AD AD AD AD

S

0

1

0

1

1 A1 A0 0

A

0

0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

3

2

1

0

WRITE Command Write Data bits

Control Byte

AD AD AD AD

0

0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

3

2

1

0

WRITE Command

Write Data bits

STOP bit

AD AD AD AD

0

x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

P

3

2

1

0

WRITE Command Write Data bits

Note: Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, 06h, and

07h) or the TCON registers (AD3:AD0 = 04h and 0Ah)

FIGURE 7-3:

I²C Continuous Volatile Wiper Write.

DS22265A-page 65

MCP444X/446X

7.5.2

CONTINUOUS READS

7.5

Read Data

Normal and High Voltage

Continuous reads allows the devices memory to be

read quickly. Continuous reads are possible to all

memory locations. If a nonvolatile memory write cycle

is occurring, then Read commands may only access

the volatile memory locations.

The Read Command can be issued to both the Volatile

and Nonvolatile memory locations. The format of the

command (see Figure 7-4), includes the Start condi-

tion, I²C Control Byte (with R/W bit set to “0”), A bit,

MCP44XX Command Byte, A bit, followed by a

Repeated Start bit, I²C Control Byte (with R/W bit set to

“1”), and the MCP44XX transmitting the requested

Data High Byte, and A bit, the Data Low Byte, the

Master generating the A, and Stop condition.

The I²C Control Byte requires the R/W bit equal to a

logic one (R/W = 1) to generate a read sequence. The

memory location read will be the last address

contained in a valid write MCP44XX Command Byte or

address 00h if no write operations have occurred since

the device was reset (Power-on Reset or Brown-out

Reset).

Figure 7-6 shows the sequence for three continuous

reads.

For continuous reads, instead of transmitting a Stop

or Restart condition after the data transfer, the master

reads the next data byte. The sequence ends with the

master Not Acknowledging and then sending a Stop or

Restart.

7.5.3

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage mode. High Voltage commands allow

the device’s WiperLock Technology and write protect

features to be enabled and disabled.

During a write cycle (Write or High Voltage Write to a

Nonvolatile memory location) the Read command can

only read the Volatile memory locations. By reading the

Status Register (05h), the Host Controller can

determine when the write cycle has completed (via the

state of the EEWA bit).

The HVC pin has an internal resistor connection to the

MCP44XX’s internal V_DDsignal.

Read operations initially include the same address byte

sequence as the write sequence (shown in Figure 6-9).

This sequence is followed by another control byte

(including the Start condition and Acknowledge) with

the R/W bit equal to a logic one (R/W = 1) to indicate a

read. The MCP44XX will then transmit the data

contained in the addressed register. This is followed by

the master generating an A bit in preparation for more

data, or an A bit followed by a Stop. The sequence is

ended with the master generating a Stop or Restart

condition.

7.5.4

IGNORING AN I²C TRANSMISSION

AND “FALLING OFF” THE BUS

The MCP44XX expects to receive complete, valid I²C

commands and will assume any command not defined

as a valid command is due to a bus corruption and will

enter a passive high condition on the SDA signal. All

signals will be ignored until the next valid Start

condition and Control Byte are received.

The internal address pointer is maintained. If this

address pointer is for a nonvolatile memory address

and the read control byte addresses the device during

a Nonvolatile Write Cycle (t_WC) the device will respond

with an A bit.

7.5.1

SINGLE READ

Figure 7-4 show the waveforms for a single read.

For single reads the master sends a STOP or

RESTART condition after the data byte is sent from the

slave.

7.5.1.1

Random Read

Figure 7-5 shows the sequence for a Random Reads.

Refer to Figure 7-5 for the random byte read

sequence.

DS22265A-page 66

MCP444X/446X

Read bit

STOP bit

Variable

Address

Fixed

Address

Read Data bits

S

0

1

0

1

1 A1 A0 1 A 0

0

0 0

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A²

Read bits

P

Control Byte

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this

transfer and release the bus.

2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the

Master Device can generate a Stop or Repeated Start condition.

3: The MCP44XX retains the last “Device Memory Address” that it has received. This is the

MCP44XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop

conditions.

4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.

FIGURE 7-4:

I²C Read (Last Memory Address Accessed).

Write bit

Device

Repeated Start bit

Variable

Address

Fixed

Address

Memory

Address

Command

AD AD AD AD

S

0

1

0

1

1 A1 A0 0

A

1

x X A Sr

3

2

1

0

READ Command

Control Byte

STOP bit

Read bit

Read Data bits

0

1

0

1

1 A1 A0 1 A 0

0

0 0

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A²

P

Control Byte

Read bits

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this

transfer and release the bus.

2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the Mas-

ter Device can generate a Stop or Repeated Start condition.

3: The MCP44XX retains the last “Device Memory Address” that it has received. This is the

MCP44XX does not “corrupt” the “Device Memory Address” after Repeated Start or Stop

conditions.

FIGURE 7-5:

I²C Random Read.

DS22265A-page 67

MCP444X/446X

Read bit

Variable

Address

Fixed

Address

Read Data bits

S

0

1

0

1

1 A1 A0 1

A

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A¹

Read bits

Control Byte

Read Data bits

0

0 0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A¹

STOP bit

Read Data bits

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A²

0

0 0

0

P

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP44XX will abort this

transfer and release the bus.

2: The Master Device will Not Acknowledge, and the MCP44XX will release the bus so the

Master Device can generate a Stop or Repeated Start condition.

FIGURE 7-6:

I²C Continuos Reads.

DS22265A-page 68

MCP444X/446X

The advantage of using an Increment Command

instead of a read-modify-write series of commands is

speed and simplicity. The wiper will transition after each

Command Acknowledge when accessing the volatile

wiper registers.

7.6

Increment Wiper

Normal and High Voltage

The Increment Command provides a quick and easy

method to modify the potentiometer’s wiper by +1 with

minimal overhead. The Increment Command will only

function on the volatile wiper setting memory locations

00h, 01h, 06h and 07h. The Increment Command to

Nonvolatile addresses will be ignored and will generate

a A.

TABLE 7-4:

INCREMENT OPERATION VS.

VOLATILE WIPER VALUE

Current Wiper

Setting

Increment

Wiper (W)

Command

Note:

Table 7-4 shows the valid addresses for

the Increment Wiper command. Other

addresses are invalid.

Properties

7-bit

Pot

8-bit

Pot

Operates?

3FFh

081h

3FFh Reserved

101h (Full-Scale (W = A))

No

When executing an Increment Command, the volatile

wiper setting will be altered from n to n+1 for each

Increment Command received. The value will

increment up to 100h max on 8-bit devices and 80h on

7-bit devices. If multiple Increment Commands are

received after the value has reached 100h (or 80h), the

value will not be incremented further. Table 7-4 shows

the Increment Command versus the current volatile

wiper value.

080h

100h Full-Scale (W = A) No

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid-Scale) Yes

03Fh

001h

07Fh W = N

001

000h

000h Zero Scale (W = B) Yes

The Increment Command will most commonly be

performed on the Volatile Wiper locations until a

desired condition is met. The value in the Volatile Wiper

register would need to be read using a Read operation

in order to write the new setting to the corresponding

Nonvolatile wiper memory using a Write operation. The

MCP44XX is responsible for generating the A bits.

7.6.1

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage mode. Signals > V_IHH(~8.5V) on the

HVC/A0 pin puts MCP44XX devices into High Voltage

mode. High Voltage commands allow the device’s

WiperLock Technology and write protect features to be

enabled and disabled.

Refer to Figure 7-7 for the Increment Command

sequence. The sequence is terminated by the Stop

condition. So when executing a continuous command

string, the Increment command can be followed by any

other valid command. This means that writes do not

need to be to the same volatile memory address.

Note:

There is a required delay after the HVC pin

is driven to the V_IHHlevel to the 1st edge

of the SCL pin.

Note:

The command sequence can go from an

increment to any other valid command for

the specified address. Issuing an

increment or decrement to a nonvolatile

location will cause an error condition (A

will be generated).

The HVC pin has an internal resistor connection to the

MCP44XX’s internal V_DDsignal.

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Command

AD AD AD AD

(2)

S

0

1

0

1

1 A1 A0 0

A

0

1 x

X

A

0

1 x

X A P

3

2

1

0

4

3

2

1

INCR Command (n+1)

INCR Command (n+2)

Control Byte

Note1: Increment Command (INCR) only functions when accessing the volatile wiper

registers (AD3:AD0 = 00h, 01h, 06h, and 07h).

2: This command sequence does not need to terminate (using the Stop bit) and can

change to any other desired command sequence (Increment, Read, or Write).

FIGURE 7-7:

I²C Increment Command Sequence.

DS22265A-page 69

MCP444X/446X

The advantage of using a Decrement Command

instead of a read-modify-write series of commands is

speed and simplicity. The wiper will transition after each

Command Acknowledge when accessing the volatile

wiper registers.

7.7

Decrement Wiper

Normal and High Voltage

The Decrement Command provides a quick and easy

method to modify the potentiometer’s wiper by -1 with

minimal overhead. The Decrement Command will only

function on the volatile wiper setting memory locations

00h and 01h. Decrement Commands to Nonvolatile

addresses will be ignored and will generate an A bit.

TABLE 7-5:

DECREMENT OPERATION VS.

VOLATILE WIPER VALUE

Current Wiper

Setting

Decrement

Wiper (W)

Note:

Table 7-5 shows the valid addresses for

the Decrement Wiper command. Other

addresses are invalid.

Command

Properties

7-bit

Pot

8-bit

Pot

Operates?

When executing a Decrement Command, the volatile

wiper setting will be altered from n to n-1 for each

Decrement Command received. The value will

decrement down to 000h min. If multiple Decrement

Commands are received after the value has reached

000h, the value will not be decremented further.

Table 7-5 shows the Increment Command versus the

current volatile wiper value.

3FFh

081h

3FFh Reserved

101h (Full-Scale (W = A))

No

080h

100h Full-Scale (W = A) Yes

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid-Scale) Yes

03Fh

001h

07Fh W = N

001

The Decrement Command will most commonly be

performed on the Volatile Wiper locations until a

desired condition is met. The value in the Volatile Wiper

register would need to be read using a Read operation

in order to write the new setting to the corresponding

Nonvolatile wiper memory using a Write operation. The

MCP44XX is responsible for generating the A bits.

000h

000h Zero Scale (W = B) No

7.7.1

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage mode. Signals > V_IHH(~8.5V) on the

HVC/A0 pin puts MCP44XX devices into High Voltage

mode. High Voltage commands allow the device’s

WiperLock Technology and write protect features to be

enabled and disabled.

Refer to Figure 7-8 for the Decrement Command

sequence. The sequence is terminated by the Stop

condition. So when executing a continuous command

string, the Increment command can be followed by any

other valid command. This means that writes do not

need to be to the same volatile memory address.

Note:

The command sequence can go from an

increment to any other valid command for

the specified address. Issuing an

increment or decrement to a nonvolatile

location will cause an error condition (A

will be generated).

Note:

There is a required delay after the HVC pin

is driven to the V_IHHlevel to the 1st edge

of the SCL pin.

The HVC pin has an internal resistor connection to the

MCP44XX’s internal V_DDsignal.

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Command

AD AD AD AD

S

0

1

0

1

1 A1 A0 0

A

1

0 X

X

A

1

0 X

X A

P ⁽²⁾

3

2

1

0

4

3

2

1

DECR Command (n-1)

DECR Command (n-2)

Control Byte

Note1: Decrement Command (DECR) only functions when accessing the volatile wiper

registers (AD3:AD0 = 00h, 01h, 06h, and 07h).

2: This command sequence does not need to terminate (using the Stop bit) and can

change to any other desired command sequence (INCR, Read, or Write).

FIGURE 7-8:

I²C Decrement Command Sequence.

DS22265A-page 70

MCP444X/446X

7.8.1

SINGLE MODIFY (ENABLE OR

DISABLE) WRITE PROTECT OR

WIPERLOCK TECHNOLOGY (HIGH

VOLTAGE)

7.8

Modify Write Protect or WiperLock

Technology (High Voltage)

Enable and Disable

These commands are special cases of the High

Voltage Decrement Wiper and the High Voltage

Increment Wiper commands to the nonvolatile

memory locations 02h, 03h, 08h, 09h, and 0Fh. This

command is used to enable or disable either the

software Write Protect, wiper 0 WiperLock Technology,

wiper 1 WiperLock Technology, wiper 2 WiperLock

Technology, or wiper 3 WiperLock Technology. Table 7-

6 shows the memory addresses, the High Voltage

command and the result of those commands on the

nonvolatile WP, WL0, or WL1 bits.

Figure 7-9 (Disable) and Figure 7-10 (Enable) show

the formats for a single Modify Write Protect or

Wiper-Lock Technology command.

A Modify Write Protect or WiperLock Technology

Command will only start an EEPROM write cycle (t_wc

)

after a properly formatted Command has been

received and the Stop condition occurs.

During an EEPROM write cycle, only serial commands

to Volatile memory (addresses 00h, 01h, 04h, and 05h)

are accepted. All other serial commands are ignored

until the EEPROM write cycle (t_wc) completes. This

allows the Host Controller to operate on the Volatile

Wiper registers and the TCON register, and to Read

the Status Register. The EEWA bit in the Status register

indicates the status of an EEPROM Write Cycle.

TABLE 7-6:

ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY

Commands and Results

Memory

Address

High Voltage Decrement Wiper

High Voltage Increment Wiper

00h

01h

Wiper 0 register is decremented

Wiper 1 register is decremented

WL0 is enabled

Wiper 0 register is incremented

Wiper 1 register is incremented

WL0 is disabled

02h

03h

WL1 is enabled

WL1 is disabled

04h ⁽¹⁾

05h ⁽¹⁾

06h

TCON0 register not changed

STATUS register not changed

Wiper 2 register is decremented

Wiper 3 register is decremented

WL2 is enabled

TCON0 register not changed

STATUS register not changed

Wiper 2 register is incremented

Wiper 3 register is incremented

WL2 is disabled

07h

08h

09h

WL3 is enabled

WL3 is disabled

0Ah ⁽¹⁾

0Bh - 0Eh ⁽¹⁾

0Fh

TCON1 register not changed

Reserved

TCON1 register not changed

Reserved

WP is enabled

WP is disabled

Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.

DS22265A-page 71

MCP444X/446X

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Command (Increment)

AD AD AD AD

P

X A

S

0

1

0

1

1 A1 A0 0

A

0

1 X

3

2

1

0

Disable Command

Control Byte

FIGURE 7-9:

I²C Disable Command Sequence.

Write bit

Device

Variable

Address

Fixed

Address

Memory

Address

Command (Decrement)

AD AD AD AD

P

0 X X A

S

0

1

0

1

1 A1 A0 0

A

1

3

2

1

0

Enable Command

Control Byte

I²C Enable Command Sequence.

FIGURE 7-10:

DS22265A-page 72

MCP444X/446X

The circuit in Figure 8-2 shows the method used on the

MCP402X Nonvolatile Digital Potentiometer Evaluation

Board (Part Number: MCP402XEV). This method

requires that the system voltage be approximately 5V.

This ensures that when the PIC10F206 enters a brown-

out condition, there is an insufficient voltage level on

the HVC/A0 pin to change the stored value of the wiper.

The MCP402X Nonvolatile Digital Potentiometer Eval-

uation Board User’s Guide (DS51546) contains a

complete schematic.

8.0

APPLICATIONS EXAMPLES

Nonvolatile digital potentiometers have a multitude of

practical uses in modern electronic circuits. The most

popular uses include precision calibration of set point

thresholds, sensor trimming, LCD bias trimming, audio

attenuation, adjustable power supplies, motor control

overcurrent trip setting, adjustable gain amplifiers and

offset trimming. The MCP44XX devices can be used to

replace the common mechanical trim pot in

applications where the operating and terminal voltages

are within CMOS process limitations (V_DD= 2.7V to

5.5V).

GP0 is a general purpose I/O pin, while GP2 can either

be a general purpose I/O pin or it can output the internal

clock.

For the serial commands, configure the GP2 pin as an

input (high impedance). The output state of the GP0 pin

will determine the voltage on the HVC/A0 pin (V_ILor

V_IH).

8.1

Techniques to Force the HVC/A0

Pin to V

IHH

The circuit in Figure 8-1 shows a method using the

TC1240A doubling charge pump. When the SHDN pin

is high, the TC1240A is off, and the level on the HVC/

A0 pin is controlled by the PIC® microcontrollers

(MCUs) IO2 pin.

For high-voltage serial commands, force the GP0

output pin to output a high level (V_OH) and configure the

GP2 pin to output the internal clock. This will form a

charge pump and increase the voltage on the CS pin

(when the system voltage is approximately 5V).

When the SHDN pin is low, the TC1240A is on and the

V_OUTvoltage is 2 * V_DD. The resistor R₁allows the

HVC/A0 pin to go higher than the voltage such that the

PIC10F206

R₁

PIC MCU’s IO2 pin “clamps” at approximately V_DD

.

GP0

MCP4XXX

TC1240A

V_IN

C+

PIC MCU

C₁

C-

GP2

HVC/A0

C₂

SHDN

V_OUT

C₁

IO1

MCP4XXX

FIGURE 8-2:

Digital Potentiometer Evaluation Board

(MCP402XEV) implementation to generate the

MCP4XXX Nonvolatile

R₁

HVC/A0

C₂

IO2

V

_IHHvoltage.

FIGURE 8-1:

Using the TC1240A to

Generate the V_IHHVoltage.

DS22265A-page 73

MCP444X/446X

8.2

Using Shutdown Modes

8.3

Software Reset Sequence

Figure 8-3 shows a possible application circuit where

the independent terminals could be used.

Disconnecting the wiper allows the transistor input to

be taken to the Bias voltage level (disconnecting A and

or B may be desired to reduce system current).

Disconnecting Terminal A modifies the transistor input

by the R_BWrheostat value to the Common B.

Disconnecting Terminal B modifies the transistor input

by the R_AWrheostat value to the Common A. The

Common A and Common B connections could be

Note:

This technique is documented in AN1028.

At times, it may become necessary to perform a

Software Reset Sequence to ensure the MCP44XX

device is in a correct and known I²C Interface state.

This technique only resets the I²C state machine.

This is useful if the MCP44XX device powers up in an

incorrect state (due to excessive bus noise, etc), or if

the Master Device is reset during communication.

Figure 8-4 shows the communication sequence to

software reset the device.

connected to V_DDand V_SS

.

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

S

P

Common A

Nine bits of ‘1’

Start bit

Start

bit

Input

Stop bit

A

FIGURE 8-4:

Software Reset Sequence

Format.

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master Device. In this mode, the device is monitoring

the data bus in Receive mode and can detect the Start

bit forces an internal Reset.

To base

of Transistor

(or Amplifier)

W

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP44XX is driving an A bit on

the I²C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I²C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP44XX holding the bus

low. By sending out nine ‘1’ bits, it is ensured that the

device will see a A bit (the Master Device does not drive

the I²C bus low to acknowledge the data sent by the

MCP44XX), which also forces the MCP44XX to reset.

B

Input

Common B

Balance

Bias

Example Application Circuit

FIGURE 8-3:

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the Master

Device was reset while sending a Write command to

the MCP44XX, AND then as the Master Device returns

to normal operation and issues a Start condition while

the MCP44XX is issuing an Acknowledge. In this case,

if the 2nd Start bit is not sent (and the Stop bit was sent)

the MCP44XX could initiate a write cycle.

using Terminal Disconnects.

Note:

The potential for this erroneous write

ONLY occurs if the Master Device is reset

while sending a Write command to the

MCP44XX.

The Stop bit terminates the current I²C bus activity. The

MCP44XX waits to detect the next Start condition.

This sequence does not effect any other I²C devices

which may be on the bus, as they should disregard this

as an invalid command.

DS22265A-page 74

MCP444X/446X

Figure 8-5 shows two I²C bus configurations. In many

cases, the single I²C bus configuration will be

adequate. For applications that do not want all the

MCP44XX devices to do General Call support or have

a conflict with General Call commands, the multiple I²C

bus configuration would be used.

8.4

Using the General Call Command

The use of the General Call Address Increment,

Decrement, or Write commands is analogous to the

“Load” feature (LDAC pin) on some DACs (such as the

MCP4921). This allows all the devices to “Update” the

output level “at the same time”.

For some applications, the ability to update the wiper

values “at the same time” may be a requirement, since

they delay from writing to one wiper value and then the

next may cause application issues. A possible example

would be a “tuned” circuit that uses several MCP44XX

in rheostat configuration. As the system condition

changes (temperature, load, etc.) these devices need

to be changed (incremented/decremented) to adjust for

the system change. These changes will either be in the

same direction or in opposite directions. With the

Potentiometer device, the customer can either select

the PxB terminals (same direction) or the PxA

terminal(s) (opposite direction).

Single I²C Bus Configuration

Device 1

Device n

Device 3

Host

Controller

Device 4

Device 2

Multiple I²C Bus Configuration

Device 1a

Bus a

Device na

Device 3a

Host

Figure 8-6 shows that the update of six devices takes

6*T_I2CDLYtime in “normal” operation, but only

1*T_I2CDLYtime in “General Call” operation.

Controller

Device 4a

Device 3b

Device 2a

Device 1b

Note:

The application system may need to

partition the I²C bus into multiple busses to

ensure that the MCP44XX General Call

commands do not conflict with the General

Call commands that the other I²C devices

may have defined. Also if only a portion of

the MCP44XX devices are to require this

synchronous operation, then the devices

that should not receive these commands

should be on the second I²C bus.

Device nb

Device nn

Bus b

Device 4b

Device 3n

Device 2b

Device 1n

Bus n

Device 4n

Device 2n

FIGURE 8-5:

Typical Application I²C Bus

Configurations.

Normal Operation

INC

POT02

INC

POT03

INC

POT04

INC

POT05

INC

POT06

POT01

T_I2CDLY

General Call Operation

INC

POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06

T_I2CDLY

_I2CDLY= Time from one I²C command completed to completing the next I²C command.

T

FIGURE 8-6:

Example Comparison of “Normal Operation” vs. “General Call Operation” Wiper

Updates.

DS22265A-page 75

MCP444X/446X

EQUATION 8-1:

dB CALCULATIONS

(VOLTAGE)

8.5

Implementing Log Steps with a

Linear Digital Potentiometer

L = 20 * log₁₀(V_OUT/ V_IN)

In audio volume control applications, the use of

logarithmic steps is desirable since the human ear

hears in a logarithmic manner. The use of a linear

potentiometer can approximate a log potentiometer,

but with fewer steps. An 8-bit potentiometer can

achieve fourteen 3 dB log steps plus a 100% (0 dB)

and a mute setting.

dB

V_OUT/ V_INRatio

-3

-2

-1

0.70795

0.79433

0.89125

Figure 8-7 shows a block diagram of one of the

MCP44x1 resistor networks being used to attenuate an

input signal. In this case, the attenuation will be ground

referenced. Terminal B can be connected to a common

mode voltage, but the voltages on the A, B and Wiper

terminals must not exceed the MCP44x1’s V_DD/V_SS

voltage limits.

EQUATION 8-2:

dB CALCULATIONS

(RESISTANCE) - CASE 1

Terminal B connected to Ground (see Figure 8-7)

L = 20 * log₁₀(R_BW/ R_AB

)

MCP44X1

EQUATION 8-3:

dB CALCULATIONS

(RESISTANCE) - CASE 2

P0A

Terminal B through R_B2GNDto Ground

P0W

P0B

L = 20 * log₁₀( (R_BW+ R_B2GND) / (R_AB+ R_B2GND) )

Table 8-1 shows the codes that can be used for 8-bit

digital potentiometers to implement the log attenuation.

The table shows the wiper codes for -3 dB, -2 dB, and

-1 dB attenuation steps. This table also shows the

calculated attenuation based on the wiper code’s linear

step. Calculated attenuation values less than the

desired attenuation are shown with red text. At lower

wiper code values, the attenuation may skip a step, if

this occurs the next attenuation value is colored

magenta to highlight that a skip occurred. For example,

in the -3 dB column the -48 dB value is highlighted

since the -45 dB step could not be implemented (there

are no wiper codes between 2 and 1).

FIGURE 8-7:

Diagram - Ground Referenced.

Signal Attenuation Block

Equation 8-1 shows the equation to calculate voltage

dB gain ratios for the digital potentiometer, while

Equation 8-2 shows the equation to calculate

resistance dB gain ratios. These two equations assume

that the B terminal is connected to ground.

If terminal B is not directly resistively connected to

ground, then this terminal B to ground resistance

(R_B2GND) must be included into the calculation.

Equation 8-3 shows this equation.

DS22265A-page 76

MCP444X/446X

TABLE 8-1:

# of

LINEAR TO LOG ATTENUATION FOR 8-BIT DIGITAL POTENTIOMETERS

-3 dB Steps -2 dB Steps -1 dB Steps

Calculated Calculated

Calculated

Desired

Wiper

Desired

Wiper

Desired

Wiper

Steps

Attenuation

Attenuation Code

(1)

0

0 dB

256

0 dB

256

0 dB

256

0 dB

1

-3 dB

181 -3.011 dB

128 -6.021 dB

91 -8.984 dB

64 -12.041 dB

46 -14.910 dB

32 -18.062 dB

23 -20.930 dB

16 -24.082 dB

11 -27.337 dB

-2 dB

203 -2.015 dB

162 -3.975 dB

128 -6.021 dB

102 -7.993 dB

81 -9.995 dB

64 -12.041 dB

51 -14.013 dB

41 -15.909 dB

32 -18.062 dB

26 -19.865 dB

20 -22.144 dB

16 -24.082 dB

13 -25.886 dB

10 -28.165 dB

-1 dB

228 -1.006 dB

203 -2.015 dB

181 -3.011 dB

162 -3.975 dB

144 -4.998 dB

128 -6.021 dB

114 -7.027 dB

102 -7.993 dB

91 -8.984 dB

81 -9.995 dB

72 -11.018 dB

64 -12.041 dB

57 -13.047 dB

51 -14.013 dB

46 - 14.910 dB

41 -15.909 dB

36 -17.039 dB

32 -18.062 dB

29 -18.917 dB

26 -19.865 dB

23 - 20.930 dB

20 -22.144 dB

18 -23.059 dB

16 -24.082 dB

14 -25.242 dB

13 -25.886 dB

11 -27.337 dB

10 -28.165 dB

2

-6 dB

-4 dB

-2 dB

3

-9dB

-6 dB

-3 dB

4

-12 dB

-15 dB

-18 dB

-21 dB

-24 dB

-27 dB

-30 dB

-33 dB

-36 dB

-39 dB

-42 dB

-48 dB

Mute

-8 dB

-4 dB

5

-10 dB

-12 dB

-14 dB

-16 dB

-18 dB

-20 dB

-22 dB

-24 dB

-26 dB

-28 dB

-30 dB

-32 dB

-34 dB

-36 dB

-38 dB

-42 dB

-48 dB

Mute

-5 dB

6

-6 dB

7

-7 dB

8

-8 dB

9

-9 dB

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

8

6

4

3

2

1

0

-30.103 dB

-32.602 dB

-36.124 dB

-38.622 dB

-42.144 dB

-48.165 dB

Mute

-10 dB

-11 dB

-12 dB

-13 dB

-14 dB

-15 dB

-16 dB

-17 dB

-18 dB

-19 dB

-20 dB

-21 dB

-22 dB

-23 dB

-24 dB

-25 dB

-26 dB

-27dB

-28 dB

-29 dB

-30 dB

-31 dB

-33 dB

-34 dB

-36 dB

-39 dB

-42 dB

-48 dB

Mute

8

6

5

4

3

2

1

0

-30.103 dB

-32.602 dB

-34.185 dB

-36.124 dB

-38.622 dB

-42.144 dB

-48.165 dB

Mute

9

8

7

6

5

4

3

2

1

0

-29.080 dB

-30.103 dB

-31.263 dB

-32.602 dB

-34.185 dB

-36.124 dB

-38.622 dB

-42.144 dB

-48.165 dB

Mute

Note 1: Attenuation values do not include errors from Digital Potentiometer errors, such as Full Scale Error or Zero

Scale Error.

DS22265A-page 77

MCP444X/446X

8.6.2

LAYOUT CONSIDERATIONS

8.6

Design Considerations

Several layout considerations may be applicable to

your application. These may include:

In the design of a system with the MCP44XX devices,

the following considerations should be taken into

account:

• Noise

• Footprint Compatibility

• PCB Area Requirements

• Power Supply Considerations

• Layout Considerations

8.6.2.1

Noise

8.6.1

POWER SUPPLY

CONSIDERATIONS

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP44XX’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-8 illustrates an

appropriate bypass strategy.

boards utilizing

a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

is capable of providing. Particularly harsh

environments may require shielding of critical signals.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (V_DD) as

possible.

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

8.6.2.2

Footprint Compatibility

The specification of the MCP44XX pinouts was done to

allow systems to be designed to easily support the use

of either the dual (MCP46XX) or quad (MCP44XX)

device.

V

_SSshould reside on the analog plane.

V_DD

Figure 8-9 shows how the dual pinout devices fit on the

quad device footprint. For the Rheostat devices, the

dual device is in the MSOP package, so the footprints

would need to be offset from each other.

0.1 µF

V_DD

MCP44X1 Quad Potentiometers

0.1 µF

P2A

P2W

P2B

P3A

P3W

P3B

20

19

18

17

16

1

2

3

4

5

6

7

8

9

10

V

HVC/A0

SCL

DD

A1

SCL

SDA

15 RESET

A

SDA

HVC/A0

A1

14 WP

MCP42X1 Pinout ⁽¹⁾

V

SS

P0B

P0W

P0A

P1B

P1W

P1A

12

11

W

TSSOP

B

MCP44X2 Quad Rheostat

P2W

P2B

P3W

P3B

14

13

12

11

10

9

1

2

3

4

5

6

7

V

HVC/A0

SCL

DD

V_SS

A1

SDA

P0B

P0W

P1W

MCP42X2 Pinout

V

SS

FIGURE 8-8:

Typical Microcontroller

8

P1B

Connections.

TSSOP

Note 1: Pin 15 (RESET) is the Address A2 (A2)

pin on the MCP46x1 device.

FIGURE 8-9:

Quad Pinout (TSSOP

Package) vs. Dual Pinout.

DS22265A-page 78

MCP444X/446X

Figure 8-10 shows possible layout implementations for

an application to support the quad and dual options on

the same PCB.

8.6.2.3

PCB Area Requirements

In some applications, PCB area is a criteria for device

selection. Table 8-2 shows the package dimensions

and area for the different package options. The table

also shows the relative area factor compared to the

smallest area. For space critical applications, the QFN

package would be the suggested package.

Potentiometers Devices

MCP44X1

TABLE 8-2:

Package

PACKAGE FOOTPRINT ⁽¹⁾

Package Footprint

MCP46X1

Dimensions

(mm)

Type

Code

X

Y

Rheostat Devices

MCP46X2

14 TSSOP

ST

ML

ST

5.10 6.40 32.64 2.04

4.00 4.00 16.00

6.60 6.40 42.24 2.64

QFN

20

1

TSSOP

MCP44X2

Note 1: Does not include recommended land

pattern dimensions.

8.6.3

RESISTOR TEMPCO

Characterization curves of the resistor temperature

coefficient (Tempco) are shown in Figure 2-10,

Figure 2-26, Figure 2-41, and Figure 2-56.

FIGURE 8-10:

Dual Devices.

Layout to Support Quad and

These curves show that the resistor network is

designed to correct for the change in resistance as

temperature increases. This technique reduces the

end to end change is R_ABresistance.

8.6.4

HIGH VOLTAGE TOLERANT PINS

High Voltage support (V_IHH) on the Serial Interface pins

supports two features. These are:

• In-Circuit Accommodation of split rail applications

and power supply sync issues

• User configuration of the Nonvolatile EEPROM,

Write Protect, and WiperLock feature

Note:

In many applications, the High Voltage will

only be present at the manufacturing

stage so as to “lock” the Nonvolatile wiper

value (after calibration) and the contents

of the EEPROM. This ensures that since

High Voltage is not present under normal

operating conditions, these values can not

be modified.

DS22265A-page 79

MCP444X/446X

9.2

Technical Documentation

9.0

9.1

DEVELOPMENT SUPPORT

Development Tools

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 9-2 shows

some of these documents.

Several development tools are available to assist in

your design and evaluation of the MCP44XX devices.

The currently available tools are shown in Table 9-1.

These boards may be purchased directly from the

Microchip web site at www.microchip.com.

TABLE 9-1:

Board Name

DEVELOPMENT TOOLS

Part #

TSSOP20EV

Supported Devices

20-pin TSSOP and SSOP Evaluation Board

MCP44XX

MCP46XX

MCP46XX Digital Potentiometer PICtail Plus Demo MCP46XXDM-PTPLS

Board ^{(1, 2)}

MCP46XX Digital Potentiometer Evaluation Board ⁽²⁾MCP46XXEV

MCP46X1

Note 1: Requires a PICDEM Demo board. See the User’s Guide for additional information and requirements.

2: Requires a PICkit Serial Analyzer. See the User’s Guide for additional information and requirements.

TABLE 9-2:

TECHNICAL DOCUMENTATION

Title

Application

Literature #

Note Number

AN1316

AN1080

AN737

AN692

AN691

AN219

—

Using Digital Potentiometers for Programmable Amplifier Gain

Understanding Digital Potentiometers Resistor Variations

Using Digital Potentiometers to Design Low-Pass Adjustable Filters

Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect

Optimizing the Digital Potentiometer in Precision Circuits

Comparing Digital Potentiometers to Mechanical Potentiometers

Digital Potentiometer Design Guide

DS01316

DS01080

DS00737

DS00692

DS00691

DS00219

DS22017

DS21825

—

Signal Chain Design Guide

DS22265A-page 80

MCP444X/446X

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

14-Lead TSSOP

Example

4462502E

1035

XXXXXXXX

YYWW

NNN

256

20-Lead QFN (4x4)

Example

XXXXX

XXXXXX

4461

502EML

e

3

1035

256

XXXXXX

^^

YYWWNNN

20-Lead TSSOP

XXXXXXXX

Example

4461502

256

NNN

XXXXX

EST

e3

^^

YYWW

1035

Legend: XX...X Customer-specific information

Y

YY

WW

NNN

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22265A-page 81

MCP444X/446X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22265A-page 82

MCP444X/446X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22265A-page 83

MCP444X/446X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22265A-page 84

MCP444X/446X

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DS22265A-page 85

MCP444X/446X

ꢒꢓꢋꢄꢣ >ꢌꢊꢅ&ꢎꢉꢅ'ꢌ!&ꢅꢍ"ꢊꢊꢉꢄ&ꢅꢒꢇꢍ+ꢇꢐꢉꢅ#ꢊꢇ*ꢃꢄꢐ!(ꢅꢒꢈꢉꢇ!ꢉꢅ!ꢉꢉꢅ&ꢎꢉꢅꢕꢃꢍꢊꢌꢍꢎꢃꢒꢅꢂꢇꢍ+ꢇꢐꢃꢄꢐꢅꢔꢒꢉꢍꢃ%ꢃꢍꢇ&ꢃꢌꢄꢅꢈꢌꢍꢇ&ꢉ#ꢅꢇ&ꢅ

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DS22265A-page 86

MCP444X/446X

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N

E

E1

NOTE 1

1

2

e

b

c

φ

A2

A

L

A1

L1

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ꢕꢃꢍꢊꢌꢍꢎꢃꢒ ꢗꢉꢍꢎꢄꢌꢈꢌꢐꢋ ꢑꢊꢇ*ꢃꢄꢐ <ꢚꢖꢝꢚLL;

DS22265A-page 87

MCP444X/446X

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS22265A-page 88

MCP444X/446X

APPENDIX A: REVISION HISTORY

Revision A (September 2010)

• Original Release of this Document.

DS22265A-page 89

MCP444X/446X

NOTES:

DS22265A-page 90

MCP444X/446X

B.1

Low-Voltage Operation

APPENDIX B: CHARACTERIZATION

DATA ANALYSIS

This appendix gives an overview of CMOS

semiconductor characteristics at lower voltages. This is

important so that the 1.8V resistor network

characterization graphs of the MCP444X/446X devices

can be better understood.

Some designers may want to understand the device

operational characteristics outside of the specified

operating conditions of the device.

Applications where the knowledge of the resistor

network characteristics could be useful include battery

powered devices and applications that experience

brown-out conditions.

For this discussion, we will use the 5 kΩ device data.

This data was chosen since the variations of wiper

resistance have much greater implications for devices

with smaller R_ABresistances.

In battery applications, the application voltage decays

over time until new batteries are installed. As the

voltage decays, the system will continue to operate. At

some voltage level, the application will be below its

specified operating voltage range. This is dependent

on the individual components used in the design. It is

still useful to understand the device characteristics to

expect when this low-voltage range is encountered.

Unlike a microcontroller, which can use an external

supervisor device to force the controller into the Reset

state, a digital potentiometer’s resistance characteristic

is not specified. But understanding the operational

characteristics can be important in the design of the

applications circuit for this low-voltage condition.

Figure B-1 shows the worst case R_BWerror from the

average R_BWas a percentage, while Figure B-2 shows

the R_BWresistance versus the wiper code graph.

Non-linear behavior occurs at approximately wiper

code 160. This is better shown in Figure B-2, where the

R_BWresistance changes from a linear slope. This

change is due to the change in the wiper resistance.

2.00%

1.00%

0.00%

-1.00%

-2.00%

-3.00%

Other

application

system

scenarios

where

-4.00%

-5.00%

understanding the low-voltage characteristics of the

resistor network could be important is for system brown

out conditions.

-40C

+25C

+85C

+125C

-6.00%

-7.00%

For the MCP444X/446X devices, the analog operation

is specified at a minimum of 2.7V. Device testing has

Terminal A connected to the device V_DD(for the

potentiometer configuration only) and Terminal B

0

32

64

96

128

160

192

224

256

Wiper Code

FIGURE B-1:

1.8V Worst Case R_BWError

from Average R_BW(R_BW0-R_BW3) vs. Wiper Code

and Temperature (V_DD= 1.8V, I_W= 190 µA).

connected to V_SS

.

7000

6000

5000

4000

3000

-40C

+25C

2000

+85C

+125C

1000

0

32

64

96

128

160

192

224

256

Wiper Code

FIGURE B-2:

R_BWvs. Wiper Code And

Temperature (V_DD= 1.8V, I_W= 190 µA).

DS22265A-page 91

MCP444X/446X

Figure B-3 and Figure B-4 show the wiper resistance

for V_DDvoltages of 5.5, 3.0, 1.8 Volts. These graphs

show that as the resistor ladder wiper node voltage

(V_WCn) approaches the V_DD/2 voltage, the wiper

resistance increases. These graphs also show the

different resistance characteristics of the NMOS and

PMOS transistors that make up the wiper switch. This

is demonstrated by the wiper code resistance curve,

which does not mirror itself around the mid-scale code

(wiper code = 128).

The method in which the data was collected is

important to understand. Figure B-5 shows the

technique that was used to measure the R_BWand R_W

resistance. In this technique, Terminal A is floating and

Terminal B is connected to ground. A fixed current is

then forced into the wiper (I_W) and the corresponding

wiper voltage (V_W) is measured. Forcing a known

current through R_BW(I_W) and then measuring the

voltage difference between the wiper (V_W) and

Terminal A (V_A), the wiper resistance (R_W) can be

calculated, see Figure B-5. Changes in I_Wcurrent will

change the wiper voltage (V_W). This may affect the

device’s wiper resistance (R_W).

So why are the R_Wgraphs showing the maximum

resistance at about mid-scale (wiper code = 128) and

the R_BWgraphs showing the issue at code 160?

This requires understanding low-voltage transistor

characteristics as well as how the data was measured.

floating

V_A

A

V_W

220

W

-40C @ 3.0V

-40C @5.5V

+25C @ 3.0V

+25C @ 5.5V

+85C @ 3.0V

+85C @ 5.5V

+125C @ 3.0V

+125C @ 5.5V

200

180

160

140

120

100

80

I_W

R_BW= V_W/I_W

B

R_W= (V_W-V_A)/I_W

V_B

FIGURE B-5:

R_BWand R_WMeasurement.

60

40

Figure B-6 shows a block diagram of the resistor

network where the R_ABresistor is a series of 256 R_S

resistors. These resistors are polysilicon devices. Each

wiper switch is an analog switch made up of an NMOS

and PMOS transistor. A more detailed figure of the

wiper switch is shown in Figure B-7. The wiper

resistance is influenced by the voltage on the wiper

switches nodes (V_G, V_Wand V_WCn). Temperature also

influences the characteristics of the wiper switch, see

Figure B-4.

20

0

64

128

Wiper Code

192

256

FIGURE B-3:

Wiper Code and Temperature

(V_DD= 5.5V, I_W= 900 µA; V_DD= 3.0V,

_W= 480 µA).

Wiper Resistance (R_W) vs.

I

The NMOS transistor and PMOS transistor have

different characteristics. These characteristics, as well

as the wiper switch node voltages, determine the R_W

resistance at each wiper code. The variation of each

wiper switch’s characteristics in the resistor network is

greater then the variation of the R_Sresistors.

-40C @ 1.8V

2020

1520

1020

520

+25C @ 1.8V

+85C @ 1.8V

+125C @ 1.8V

The voltage on the resistor network node (V_WCn) is

dependent upon the wiper code selected and the

voltages applied to V_A, V_Band V_W. The wiper switch V_G

voltage to V_Wor V_WCnvoltage determines how strongly

the transistor is turned on. When the transistor is

weakly turned on, the wiper resistance R_Wwill be high.

When the transistor is strongly turned on, the wiper

resistance (R_W) will be in the typical range.

20

0

64

128

192

256

Wiper Code

FIGURE B-4:

Wiper Code and Temperature

(V_DD= 1.8V, I_W= 260 µA).

Wiper Resistance (R_W) vs.

DS22265A-page 92

MCP444X/446X

So looking at the wiper voltage (V_W) for the

3.0V and 1.8V data gives the graphs in Figure B-8 and

Figure B-9. In the 1.8V graph, as the V_Wapproaches

0.8V, the voltage increases nonlinearly. Since V = I * R,

and the current (I_W) is constant, it means that the

device resistance increased nonlinearly at around

wiper code 160.

A

V_A

N_n

R_S

(1)

R_W

N_n-1

R_S

1.2

1.0

0.8

0.6

DV_G

R_W

NMOS

PMOS

N_n-2

R_S

V_WC(n-2)

R_AB

(1)

R_W

N_n-3

0.4

0.2

0.0

-40C

+25C

+85C

+125C

W

V_W

N₁

R_S

0

32

64

96 128 160 192 224 256

Wiper Code

(1)

R_W

FIGURE B-8:

Wiper Code (V_DD= 3.0V, I_W= 190 µA).

Wiper Voltage (V_W) vs.

N₀

(1)

R_W

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

V_B

B

Note 1: The wiper resistance is dependent on

several factors including, wiper code,

device V_DD, Terminal voltages (on A, B

and W), and temperature.

-40C

FIGURE B-6:

Resistor Network Block

+25C

+85C

+125C

Diagram.

The characteristics of the wiper are determined by the

characteristics of the wiper switch at each of the

resistor networks tap points. Figure B-7 shows an

example of a wiper switch. As the device operational

voltage becomes lower, the characteristics of the wiper

switch change due to a lower voltage on the V_Gsignal.

0

32

64

96

128 160 192 224 256

Wiper Code

FIGURE B-9:

Wiper Code (V_DD= 1.8V, I_W= 190 µA).

Wiper Voltage (V_W) vs.

Figure B-7 shows an implementation of a wiper switch.

When the transistor is turned off, the switch resistance

is in the Giga Ωs. When the transistor is turned on, the

switch resistance is dependent on the V_G, V_Wand

V_WCnvoltages. This resistance is referred to as R_W.

(1)

R_W

V_G(V_DD/V_SS

)

“gate”

NMOS

PMOS

N_WC

V_WCn

Wiper

V_W

“gate”

Note 1: Wiper Resistance (R_W) depends on the

voltages at the wiper switch nodes

(V_G, V_Wand V_WCn).

FIGURE B-7:

Wiper Switch.

DS22265A-page 93

MCP444X/446X

Using the simulation models of the NMOS and PMOS

devices for the MCP44XX analog switch (Figure B-10),

we plot the device resistance when the devices are

turned on. Figure B-11 and Figure B-12 show the

resistances of the NMOS and PMOS devices as the

V_INvoltage is increased. The wiper resistance (R_W) is

simply the parallel resistance on the NMOS and PMOS

devices (R_W= R_NMOS|| R_PMOS). Below the threshold

voltage for the NMOS ad PMOS devices, the

resistance becomes very large (Gigaohms). In the

transistors active region, the resistance is much lower.

For these graphs, the resistances are on different

scales. Figure B-13 and Figure B-14 only plot the

NMOS and PMOS device resistance for their active

region and the resulting wiper resistance. For these

graphs, all resistances are on the same scale.

7.00E+09

6.00E+09

5.00E+09

4.00E+09

3.00E+09

2.00E+09

1.00E+09

0.00E+00

160

140

120

100

80

R_NMOS

R_PMOS

R_W

NMOS

Theshold

60

PMOS

Theshold

40

20

0

0.0

0.6

1.2

1.8

V_INVoltage

2.4

3.0

FIGURE B-12:

NMOS and PMOS

Transistor Resistance (R_NMOS, R_PMOS) and

Wiper Resistance (R_W) VS. V_IN

(V_DD= 1.8V).

R_W

V_G(V_DD/V_SS

)

“gate”

300

250

200

NMOS

PMOS

V_IN

V_OUT

R_NMOS

R_PMOS

150

100

50

FIGURE B-10:

Analog Switch.

R_W

3.00E+10

2.50E+10

2500

R_W

R_NMOS

0

0.0

0.6

1.2

1.8

2.4

3.0

2000

1500

1000

500

0

V_INVoltage

R_PMOS

2.00E+10

1.50E+10

1.00E+10

5.00E+09

0.00E+00

FIGURE B-13:

NMOS and PMOS

Transistor Resistance (R_NMOS, R_PMOS) and

Wiper Resistance (R_W) VS. V_IN

(V_DD= 3.0V).

NMOS

PMOS

Theshold

5000

4500

4000

3500

3000

0.0

0.3

0.6

0.9

V_INVoltage

1.2

1.5

1.8

FIGURE B-11:

NMOS and PMOS

Transistor Resistance (R_NMOS, R_PMOS) and

Wiper Resistance (R_W) VS. V_IN

(V_DD= 3.0V).

R_NMOS

R_PMOS

2500

2000

1500

1000

500

R_W

0

0.0

0.3

0.6

0.9

_INVoltage

1.2

1.5

1.8

V

FIGURE B-14:

NMOS and PMOS

Transistor Resistance (R_NMOS, R_PMOS) and

Wiper Resistance (R_W) VS. V_IN

(V_DD= 1.8V).

DS22265A-page 94

MCP444X/446X

B.2

Optimizing Circuit Design for

Low-Voltage Characteristics

R1

The low-voltage nonlinear characteristics can be

minimized by application design. The section will show

two application circuits that can be used to control a

programmable reference voltage (V_OUT).

V_A

A

B

V_W

W

V_OUT

Minimizing the low-voltage nonlinear characteristics is

done by keeping the voltages on the wiper switch

nodes at a voltage where either the NMOS or PMOS

transistor is turned on.

V_B

R2

An example of this is if we are using a digital

potentiometer for a voltage reference (V_OUT). Let’s say

that we want V_OUTto range from 0.5 * V_DDto 0.6 * V_DD

.

FIGURE B-15:

Example Implementation #1.

In example implementation #1 (Figure B-15), we

window the digital potentiometer using resistors R1 and

R2. When the wiper code is at full scale, the V_OUT

voltage will be ≥ 0.6 * V_DD,and when the wiper code is

TABLE B-1:

EXAMPLE #1 VOLTAGE

CALCULATIONS

Variation

at zero scale the V_OUTvoltage will be ≤ 0.5 * V_DD

.

Min

Typ

Max

Remember that the digital potentiometers R_ABvariation

must be included. Table B-1 shows that the V_OUT

voltage can be selected to be between 0.455 * V_DDand

0.727 * V_DD, which includes the desired range. With

respect to the voltages on the resistor network node, at

1.8V the V_Avoltage would range from 1.29V to 1.31V

while the V_Bvoltage would range from 0.82V to 0.86V.

These voltages cause the wiper resistance to be in the

nonlinear region (see Figure B-12). In Potentiometer

mode, the variation of the wiper resistance is typically

not an issue, as shown by the INL/DNL graph

(Figure 2-7).

R1

12,000

20,000

8,000

12,000

20,000

12,000

20,000

R2

R_AB

10,000

12,000

V_OUT(@ FS) 0.714 V_DD

V_OUT(@ ZS) 0.476 V_DD

0.70 V_DD

0.50 V_DD

0.70 V_DD

0.50 V_DD

0.727 V_DD

0.455 V_DD

0.727 V_DD

0.455 V_DD

V_A

V_B

0.714 V_DD

0.476 V_DD

Legend: FS – Full Scale, ZS – Zero Scale

In example implementation #2 (Figure B-16) we use

the digital potentiometer in Rheostat mode. The

resistor ladder uses resistors R1 and R2 with R_BWat

the bottom of the ladder. When the wiper code is at full

scale, the V_OUTvoltage will be ≥ 0.6 * V_DDand when

the wiper code is at full scale the V_OUTvoltage will be

≤ 0.5 * V_DD. Remember that the digital potentiometers

R_ABvariation must be included. Table B-2 shows that

the V_OUTvoltage can be selected to be between 0.50 *

V_DDand 0.687 * V_DD, which includes the desired

range. With respect to the voltages on the resistor

network node, at 1.8V the V_Wvoltage would range from

0.29V to 0.38V. These voltages cause the wiper

resistance to be in the linear region (see Figure B-12).

DS22265A-page 95

MCP444X/446X

R1

V_OUT

R2

V_A

A

W

V_W

B

V_B

FIGURE B-16:

Example Implementation #2.

TABLE B-2:

EXAMPLE #2 VOLTAGE

CALCULATIONS

Variation

Min

Typ

Max

R1

10,000

8,000

10,000

12,000

R2

R_BW(max)

V_OUT(@ FS) 0.667 V_DD0.643 V_DD0.687 V_DD

V_OUT(@ ZS) 0.50 V_DD0.50 V_DD0.50 V_DD

0.333 V_DD0.286 V_DD0.375 V_DD

V_SSV_SSV_SS

V_W(@ FS)

V_W(@ ZS)

Legend: FS – Full Scale, ZS – Zero Scale

DS22265A-page 96

MCP444X/446X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

-XXX

X

/XX

a)

MCP4441-502E/XX: 5 kΩ, 20-LD Device

Resistance Temperature

Version

Package

b)

c)

d)

e)

f)

MCP4441T-502E/XX: T/R, 5 kΩ, 20-LD Device

MCP4441-103E/XX: 10 kΩ, 20-LD Device

MCP4441T-103E/XX: T/R, 10 kΩ, 20-LD Device

MCP4441-503E/XX: 50 kΩ, 20-LD Device

MCP4441T-503E/XX: T/R, 50 kΩ, 20-LD Device

MCP4441-104E/XX: 100 kΩ, 20-LD Device

MCP4441T-104E/XX: T/R, 100 kΩ,

Range

Device

MCP4441:

MCP4441T:

Quad Nonvolatile 7-bit Potentiometer

(Tape and Reel)

Quad Nonvolatile 7-bit Rheostat

(Tape and Reel)

Quad Nonvolatile 8-bit Potentiometer

(Tape and Reel)

Quad Nonvolatile 8-bit Rheostat

(Tape and Reel)

g)

h)

MCP4442:

MCP4442T:

20-LD Device

a)

MCP4442-502E/XX: 5 kΩ, 14-LD Device

b)

c)

d)

e)

f)

MCP4442T-502E/XX: T/R, 5 kΩ, 14-LD Device

MCP4442-103E/XX: 10 kΩ, 14-LD Device

MCP4442T-103E/XX: T/R, 10 kΩ, 14-LD Device

MCP4442-503E/XX: 50 kΩ, 8LD Device

MCP4442T-503E/XX: T/R, 50 kΩ, 14-LD Device

MCP4442-104E/XX: 100 kΩ, 14-LD Device

MCP4442T-104E/XX: T/R, 100 kΩ,

MCP4461:

MCP4461T:

MCP4462:

MCP4462T:

g)

h)

14-LD Device

Resistance Version: 502

=

5 kΩ

a)

MCP4461-502E/XX: 5 kΩ, 20-LD Device

103

503

104

10 kΩ

50 kΩ

100 kΩ

b)

c)

d)

e)

f)

MCP4461T-502E/XX: T/R, 5 kΩ, 20-LD Device

MCP4461-103E/XX: 10 kΩ, 20-LD Device

MCP4461T-103E/XX: T/R, 10 kΩ, 20-LD Device

MCP4461-503E/XX: 50 kΩ, 20-LD Device

MCP4461T-503E/XX: T/R, 50 kΩ, 20-LD Device

MCP4461-104E/XX: 100 kΩ, 20-LD Device

MCP4461T-104E/XX: T/R, 100 kΩ,

Temperature Range

Package

E

=

-40°C to +125°C (Extended)

g)

h)

20-LD Device

ST

ML

=

Plastic Thin Shrink Small Outline (TSSOP),

14/20-lead

Plastic Quad Flat No-lead (4x4 QFN), 20-lead

a)

MCP4462-502E/XX: 5 kΩ, 14-LD Device

b)

c)

d)

e)

f)

MCP4462T-502E/XX: T/R, 5 kΩ, 14-LD Device

MCP4462-103E/XX: 10 kΩ, 14-LD Device

MCP4462T-103E/XX: T/R, 10 kΩ, 14-LD Device

MCP4462-503E/XX: 50 kΩ, 14-LD Device

MCP4462T-503E/XX: T/R, 50 kΩ, 14-LD Device

MCP4462-104E/XX: 100 kΩ, 14-LD Device

MCP4462T-104E/XX: T/R, 100 kΩ,

g)

h)

14-LD Device

XX

=

ST for 14/20-lead TSSOP

ML for 20-lead QFN

DS22265A-page 97

MCP444X/446X

NOTES:

DS22265A-page 98

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

32

PIC logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-60932-533-6

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22265A-page 99

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China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Hsin Chu

Tel: 886-3-6578-300

Fax: 886-3-6578-370

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Fax: 886-7-330-9305

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Santa Clara

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

08/04/10

DS22265A-page 100


型号：	MCP4462-502E/ST
厂家：	MICROCHIP
描述：	7/8-Bit Quad I2C Digital POT with Nonvolatile Memory 光电二极管转换器电阻器
文件：	总100页 (文件大小：4837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4462-502E/ST [MICROCHIP]

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