MCP4641T-103E/ST_技术文档

MCP454X/456X/464X/466X

7/8-Bit Single/Dual I²C Digital POT with

Non-Volatile Memory

Features

Description

• Single or Dual Resistor Network options

• Potentiometer or Rheostat configuration options

• Resistor Network Resolution

- 7-bit: 128 Resistors (129 Steps)

- 8-bit: 256 Resistors (257 Steps)

• R_ABResistances options of:

- 5 kΩ

The MCP45XX and MCP46XX devices offer a wide

range of product offerings using an I²C interface. This

family of devices support 7-bit and 8-bit resistor

networks, Non-Volatile memory configurations, and

Potentiometer and Rheostat pinouts.

WiperLock Technology allows application-specific

calibration settings to be secured in the EEPROM.

- 10 kΩ

- 50 kΩ

- 100 kΩ

Package Types (top view)

MCP45X1

Single Potentiometer

MCP45X2

Single Rheostat

• Zero-Scale to Full-Scale Wiper operation

• Low Wiper Resistance: 75Ω (typ.)

• Low Tempco:

- Absolute (Rheostat): 50 ppm typical

(0°C to 70°C)

- Ratiometric (Potentiometer): 15 ppm typical

• Non-volatile Memory

- Automatic Recall of Saved Wiper Setting

- WiperLock™ Technology

- 10 General Purpose Memory Locations

• I²C Serial interface

- 100 kHz, 400 kHz and 3.4 MHz support

• Serial protocol allows:

- High-Speed Read/Write to wiper

- Read/Write to EEPROM

- Write Protect to be enabled/disabled

- WiperLock to be enabled/disabled

HVC / A0

V_DD

P0B

P0W

P0A

V_DD

1

2

3

4

1

2

3

4

8

7

6

5

8

7

6

5

A1

SCL

SDA

V_SS

SCL

SDA

V_SS

P0B

P0W

MSOP

HVC / A0

V_DDHVC / A0

V_DD

1

8

1

8

SCL

SDA

V_SS

A1

SCL

SDA

V_SS

A1

2

3

4

7

6

5

2

3

4

7

6

5

EP

9

EP

9

P0B

P0W

P0B

P0W

DFN 3x3 (MF) *

MCP46X1 Dual Potentiometers

DFN 3x3 (MF) *

V_DD

A1

12 A2

HVC/A0

SCL

14

13

1

2

3

4

5

6

7

• Resistor Network Terminal Disconnect Feature

via the Terminal Control (TCON) Register

SDA

V_SS

P1B

P1W

P1A

11

10

9

WP

16 15 14 13

P0B

P0W

P0A

SCL

SDA

V_SS

WP

NC

P0B

P0W

1

2

3

4

12

11

10

9

• Write Protect Feature:

- Hardware Write Protect (WP) Control pin

- Software Write Protect (WP) Configuration bit

• Brown-out reset protection (1.5V typical)

• Serial Interface Inactive current (2.5 uA typ.)

• High-Voltage Tolerant Digital Inputs: Up to 12.5V

• Wide Operating Voltage:

- 2.7V to 5.5V - Device Characteristics Specified

- 1.8V to 5.5V - Device Operation

• Wide Bandwidth (-3dB) Operation:

- 2 MHz (typ.) for 5.0 kΩ device

EP

17

8

TSSOP

5 6 7

8

QFN-16 4x4 (ML) *

MCP46X2 Dual Rheostat

HVC / A0

V

DD

1

10

V_DD

A1

P0B

P0W

P1W

HVC/A0

SCL

10

9

8

7

6

1

2

3

4

5

• Extended temperature range (-40°C to +125°C)

SCL

SDA

V_SS

A1

2

3

4

5

9

8

7

6

SDA

EP

11

P0B

P0W

P1W

V_SS

P1B

MSOP

DFN 3x3 (MF) *

* Includes Exposed Thermal Pad (EP); see Table 3-1.

DS22107A-page 1

MCP454X/456X/464X/466X

Device Block Diagram

V_DD

V_SS

Power-up/

Brown-out

Control

P0A

Resistor

Network 0

(Pot 0)

P0W

I²C Serial

Interface

Module &

Control

Logic

(WiperLock™

Technology)

Wiper 0

& TCON

Register

A2

A1

P0B

P1A

HVC/A0

SCL

SDA

I²C Interface

Resistor

Network 1

(Pot 1)

WP

P1W

P1B

Wiper 1

& TCON

Register

Memory (16x9)

Wiper0 (V & NV)

Wiper1 (V & NV)

TCON

STATUS

For Dual Resistor Network

Devices Only

Data EEPROM

(10 x 9-bits)

Device Features

Resistance (typical)

V_DD

Wiper

Configuration

Wiper

Device

Operating

Range ⁽²⁾

R

_ABOptions (kΩ)

- R_W

(Ω)

MCP4531 ⁽³⁾

MCP4532 ⁽³⁾

MCP4541

1

2

Potentiometer⁽¹⁾I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat

I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾I²C

Rheostat

I²C

75

129 1.8V to 5.5V

129 2.7V to 5.5V

257 1.8V to 5.5V

257 2.7V to 5.5V

129 1.8V to 5.5V

129 2.7V to 5.5V

257 1.8V to 5.5V

257 2.7V to 5.5V

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4542

MCP4551 ⁽³⁾

MCP4552 ⁽³⁾

MCP4561

Potentiometer⁽¹⁾I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat

I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾I²C

Rheostat

I²C

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4562

MCP4631 ⁽³⁾

MCP4632 ⁽³⁾

MCP4641

Potentiometer⁽¹⁾I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat

I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾I²C

Rheostat

I²C

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4642

MCP4651 ⁽³⁾

MCP4652 ⁽³⁾

MCP4661

Potentiometer⁽¹⁾I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Rheostat

I²C RAM No Mid-Scale 5.0, 10.0, 50.0, 100.0

Potentiometer⁽¹⁾I²C

Rheostat

I²C

EE

Yes NV Wiper 5.0, 10.0, 50.0, 100.0

MCP4662

Note 1: Floating either terminal (A or B) allows the device to be used as a Rheostat (variable resistor).

2: Analog characteristics only tested from 2.7V to 5.5V unless otherwise noted.

3: Please check Microchip web site for device release and availability

DS22107A-page 2

MCP454X/456X/464X/466X

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device. This is

a stress rating only and functional operation of the device at

those or any other conditions above those indicated in the

operational listings of this specification is not implied.

Exposure to maximum rating conditions for extended periods

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

Voltage on V_DDwith respect to V_SS............... -0.6V to +7.0V

Voltage on HVC/A0, A1, A2, SCL, SDA, and WP with

respect to V_{SS .............................................................}-0.6V to 12.5V

Voltage on all other pins (PxA, PxW, and PxB)

may affect device reliability.

with respect to V_{SS .........................................}-0.3V to V_DD+ 0.3V

Input clamp current, I_IK

(V_I< 0, V_I> V_DD, V_I> V_PPON HV pins)......................±20 mA

Output clamp current, I_OK

(V_O< 0 or V_O> V_DD) ..................................................±20 mA

Maximum output current sunk by any Output pin

......................................................................................25 mA

Maximum output current sourced by any Output pin

......................................................................................25 mA

Maximum current out of V_SSpin .................................100 mA

Maximum current into V_DDpin ....................................100 mA

Maximum current into PXA, PXW & PXB pins ............±2.5 mA

Storage temperature ....................................-65°C to +150°C

Ambient temperature with power applied

-40°C to +125°C

Total power dissipation (Note 1) ................................400 mW

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins .................................. ≥ 4 kV (HBM),

.......................................................................... ≥ 300V (MM)

Maximum Junction Temperature (T_J) .........................+150°C

Note 1: Power dissipation is calculated as follows:

P_DIS= V_DDx {I_DD- ∑ I_OH} + ∑ {(V_DD-V_OH) x I_OH} + ∑(V_OLx I_OL

)

DS22107A-page 3

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Supply Voltage

V_DD

2.7

1.8

—

5.5

2.7

V

Serial Interface only.

HVC pin Voltage

Range

V_HV

V_SS

12.5V

V_DD≥ The HVC pin will be at one

4.5V of three input levels

(V_IL, V_IHor V_IHH). (Note 6)

V_SS

—

V_DD

8.0V

+

V

V_DD<

4.5V

VDD Start Voltage

to ensure Wiper

Reset

V_BOR

V_DDRR

T_BORD

I_DD

1.65

RAM retention voltage (V_RAM) < V_BOR

VDD Rise Rate to

ensure Power-on

Reset

(Note 9)

10

V/ms

µs

Delay after device

exits the reset state

—

20

(V_DD> V_BOR

)

Supply Current

—

600

µA

Serial Interface Active,

(Note 10)

HVC/A0 = V_IH(or V_IL) (Note 11)

Write all 0’s to Volatile Wiper 0

V_DD= 5.5V, F_SCL= 3.4 MHz

—

250

575

µA

Serial Interface Active,

HVC/A0 = V_IH(or V_IL) (Note 11)

Write all 0’s to Volatile Wiper 0

V_DD= 5.5V, F_SCL= 100 kHz

EE Write Current (Write Cycle)

(Non-Volatile device only),

V_DD= 5.5V, F_SCL= 400 kHz,

Write all 0’s to NonVolatile Wiper 0

SCL = V_ILor V_IH

—

2.5

5

µA

Serial Interface Inactive,

(Stop condition, SCL = SDA = V_IH),

Wiper = 0

V_DD= 5.5V, HVC/A0 = V_IH

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 4

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

-502 devices (Note 1)

Resistance

(± 20%)

R_AB

4.0

8.0

5

10

6.0

12.0

60.0

120.0

kΩ

-103 devices (Note 1)

-503 devices (Note 1)

-104 devices (Note 1)

40.0

80.0

50

100

257

129

R_AB

Resolution

N

Taps 8-bit

Taps 7-bit

No Missing Codes

Note 6

Step Resistance

R_S

—

/

—

Ω

8-bit

(256)

R_AB

(128)

/

Ω

7-bit

Note 6

Nominal

Resistance Match

|R_AB0- R_AB1| /

R_AB

0.2

1.25

1.5

%

MCP46X1 devices only

|R_BW0- R_BW1

|

0.25

MCP46X2 devices only,

/ R_BW

Code = Full-Scale

Wiper Resistance

(Note 3, Note 4)

R_W

—

75

160

300

—

Ω

V_DD= 5.5 V, I_W= 2.0 mA, code = 00h

V_DD= 2.7 V, I_W= 2.0 mA, code = 00h

Nominal

Resistance

Tempco

ΔR_AB/ΔT

50

ppm/°C T_A= -20°C to +70°C

ppm/°C T_A= -40°C to +85°C

ppm/°C T_A= -40°C to +125°C

ppm/°C Code = Midscale (80h or 40h)

100

150

15

—

Ratiometeric

Tempco

ΔV_WB/ΔT

—

Resistor Terminal

Input Voltage

V_A,V_W,V_B

Vss

—

V_DD

V

Note 5, Note 6

Range (Terminals

A, B and W)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 5

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

I_AW

W = Full-Scale (FS)

I_BW

W = Zero Scale (ZS)

I_AWor I_BW

,

Maximum current

through Terminal

(A, W or B)

I_T

—

2.5

mA

Terminal A

Terminal B

Terminal W

,

—

2.5

mA

Note 6

,

W = FS or ZS

I_AB, V_B= 0V,

V_A= 5.5V,

1.38

R_AB(MIN)= 4000

I_AB, V_B= 0V,

V_A= 5.5V,

—

0.688

0.138

0.069

mA

Terminal A

and

Terminal B

R_AB(MIN)= 8000

I_AB, V_B= 0V,

V_A= 5.5V,

R_AB(MIN)= 40000

I_AB, V_B= 0V,

V_A= 5.5V,

R_AB(MIN)= 80000

Leakage current

into A, W or B

I_WL

—

100

—

nA

MCP4XX1 PxA = PxW = PxB = V_SS

MCP4XX2 PxB = PxW = V_SS

Terminals Disconnected

(R1HW = R0HW = 0)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 6

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

3.0V ≤ V_DD≤ 5.5V

Full-Scale Error

(MCP4XX1 only)

(8-bit code = 100h,

7-bit code = 80h)

V_WFSE

-6.0

-4.0

-3.5

-2.0

-0.8

-0.5

—

-0.1

—

LSb 5 kΩ

8-bit

7-bit

LSb

3.0V ≤ V_DD≤ 5.5V

-0.1

—

LSb 10 kΩ 8-bit

LSb 7-bit

LSb 50 kΩ 8-bit

LSb 7-bit

LSb 100 kΩ 8-bit

-0.1

—

-0.1

—

-0.1

—

-0.1

—

-0.1

—

LSb

7-bit

8-bit

7-bit

Zero-Scale Error

(MCP4XX1 only)

(8-bit code = 00h,

7-bit code = 00h)

V_WZSE

+0.1

±0.5

±0.25

+6.0

+3.0

+3.5

+2.0

+0.8

+0.5

+1

LSb 5 kΩ

LSb

—

LSb 10 kΩ 8-bit

LSb 7-bit

LSb 50 kΩ 8-bit

LSb 7-bit

LSb 100 kΩ 8-bit

—

LSb

7-bit

Potentiometer

Integral

Non-linearity

INL

-1

LSb 8-bit

LSb 7-bit

3.0V ≤ V_DD≤ 5.5V

MCP4XX1 devices only

(Note 2)

-0.5

+0.5

Potentiometer

Differential

Non-linearity

DNL

-0.5

±0.25

+0.5

LSb 8-bit

LSb 7-bit

3.0V ≤ V_DD≤ 5.5V

MCP4XX1 devices only

(Note 2)

-0.25

±0.125

+0.25

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 7

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Code = 80h

Bandwidth -3 dB

(See Figure 2-58,

load = 30 pF)

BW

—

2

—

MHz 5 kΩ

8-bit

7-bit

MHz

Code = 40h

Code = 80h

Code = 40h

Code = 80h

Code = 40h

Code = 80h

Code = 40h

1

MHz 10 kΩ 8-bit

MHz 7-bit

kHz 50 kΩ 8-bit

kHz 7-bit

kHz 100 kΩ 8-bit

kHz 7-bit

1

200

100

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 8

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym

Min

Typ

Max

Units

Conditions

5.5V, I_W= 900 µA

Rheostat Integral

Non-linearity

MCP45X1

(Note 4, Note 8)

MCP4XX2 devices

only (Note 4)

R-INL

-1.5

±0.5

+4.5

+1.5

LSb 5 kΩ

8-bit

7-bit

-8.25

+8.25

LSb

3.0V, I_W= 480 µA

(Note 7)

-1.125

-6.0

±0.5

+4.5

+1.125

+6.0

LSb

5.5V, I_W= 900 µA

3.0V, I_W= 480 µA

(Note 7)

-1.5

-5.5

±0.5

+2.5

+1.5

+5.5

LSb 10 kΩ 8-bit

5.5V, I_W= 450 µA

LSb

3.0V, I_W= 240 µA

(Note 7)

-1.125

-4.0

±0.5

+2.5

+1.125

+4.0

LSb

7-bit

5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-1.5

-2.0

±0.5

+1

+1.5

+2.0

LSb 50 kΩ 8-bit

5.5V, I_W= 90 µA

LSb

3.0V, I_W= 48 µA

(Note 7)

-1.125

-1.5

±0.5

+1

+1.125

+1.5

LSb

7-bit

5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-1.0

-1.5

±0.5

+1.0

+1.5

LSb 100 kΩ 8-bit

5.5V, I_W= 45 µA

+0.25

LSb

3.0V, I_W= 24 µA

(Note 7)

-0.8

±0.5

+0.8

LSb

7-bit

5.5V, I_W= 45 µA

-1.125

+0.25

+1.125

3.0V, I_W= 24 µA

(Note 7)

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 9

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

5.5V, I_W= 900 µA

Rheostat

R-DNL

-0.5

-1.0

±0.25

+0.5

+1.0

LSb 5 kΩ

8-bit

7-bit

Differential

Non-linearity

MCP45X1

(Note 4, Note 8)

MCP4XX2 devices

only

LSb

3.0V, I_W= 480 µA

(Note 7)

-0.375

-0.75

±0.25

+0.5

+0.375

+0.75

LSb

5.5V, I_W= 900 µA

3.0V, I_W= 480 µA

(Note 7)

(Note 4)

-0.5

-1.0

±0.25

+0.25

+0.5

+1.0

LSb 10 kΩ 8-bit

5.5V, I_W= 450 µA

LSb

3.0V, I_W= 240 µA

(Note 7)

-0.375

-0.75

±0.25

+0.5

+0.375

+0.75

LSb

7-bit

5.5V, I_W= 450 µA

3.0V, I_W= 240 µA

(Note 7)

-0.5

±0.25

+0.5

LSb 50 kΩ 8-bit

5.5V, I_W= 90 µA

LSb

3.0V, I_W= 48 µA

(Note 7)

-0.375

±0.25

+0.375

LSb

7-bit

5.5V, I_W= 90 µA

3.0V, I_W= 48 µA

(Note 7)

-0.5

±0.25

+0.5

LSb 100 kΩ 8-bit

5.5V, I_W= 45 µA

LSb

3.0V, I_W= 24 µA

(Note 7)

-0.375

±0.25

+0.375

LSb

7-bit

5.5V, I_W= 45 µA

3.0V, I_W= 24 µA

(Note 7)

Capacitance (P_A)

Capacitance (P_w)

Capacitance (P_B)

C_AW

C_W

—

75

120

75

—

pF

f =1 MHz, Code = Full-Scale

C_BW

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 10

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Digital Inputs/Outputs (SDA, SCK, HVC/A0, A1, A2, WP)

Schmitt Trigger

High Input

V_IH

0.45 V_DD

—

V

All

2.7V ≤ V_DD≤ 5.5V

Inputs (Allows 2.7V Digital V_DDwith

Threshold

except 5V Analog V_DD

SDA

and

)

0.5 V_DD

—

V

1.8V ≤ V_DD≤ 2.7V

SCL

0.7 V_DD

—

V_MAX

0.2V_DD

0.3V_DD

—

V

100 kHz

400 kHz

1.7 MHz

3.4 Mhz

SDA

and

SCL

—

Schmitt Trigger

Low Input

Threshold

V_IL

—

All inputs except SDA and SCL

100 kHz

-0.5

—

SDA

and

SCL

-0.5

—

400 kHz

-0.5

—

1.7 MHz

-0.5

—

3.4 Mhz

Hysteresis of

Schmitt Trigger

Inputs (Note 6)

V_HYS

—

0.1V_DD

—

All inputs except SDA and SCL

N.A.

—

V_DD< 2.0V

100 kHz

N.A.

—

V_DD≥ 2.0V

SDA

0.1 V_DD

0.05 V_DD

0.1 V_DD

8.5

—

V_DD< 2.0V

and 400 kHz

—

V_DD≥ 2.0V

SCL

—

1.7 MHz

—

12.5 ⁽⁶⁾

3.4 Mhz

High Voltage Input

Entry Voltage

V_IHHEN

V_IHHEX

V_MAX

—

Threshold for WiperLock™ Technology

High Voltage Input

Exit Voltage

—

V_DD

+

V

0.8V ⁽⁶⁾

12.5 ⁽⁶⁾

High Voltage Limit

Pin can tolerate V_MAXor less.

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 11

MCP454X/456X/464X/466X

AC/DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ T_A≤ +125°C (extended)

DC Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ devices.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Output Low

Voltage (SDA)

V_OL

V_SS

—

0.2V_DD

0.4

V

V_DD< 2.0V, I_OL= 1 mA

V_DD≥ 2.0V, I_OL= 3 mA

Weak Pull-up /

Pull-down Current

I_PU

1.75

mA

Internal V_DDpull-up, V_IHHpull-down

V_DD= 5.5V, V_IHH= 12.5V

—

170

16

—

µA

HVC pin, V_DD= 5.5V, V_HVC= 3V

V_DD= 5.5V, V_HVC= 3V

HVC Pull-up /

Pull-down

R_HVC

kΩ

Resistance

Input Leakage Cur-

rent

I_IL

-1

—

1

µA

pF

V_IN= V_DDand V_IN= V_SS

f_C= 3.4 MHz

Pin Capacitance

RAM (Wiper) Value

Value Range

C_IN, C_OUT

—

10

—

N

0h

—

1FFh

hex

8-bit device

7-bit device

TCON POR/BOR

Value

N_TCON

1FFh

All Terminals connected

EEPROM

Endurance

E_ndurance

—

1M

—

Cycles

hex

EEPROM Range

N

0h

1FFh

Initial Factory

Setting

80h

40h

5

hex

8-bit

7-bit

WiperLock Technology = Off

hex

EEPROM

t_WC

—

10

ms

Programming Write

Cycle Time

Power Requirements

Power Supply

Sensitivity

(MCP45X2 and

MCP46X2 only)

PSS

—

0.0015 0.0035

%/% 8-bit

%/% 7-bit

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 80h

V_DD= 2.7V to 5.5V,

V_A= 2.7V, Code = 40h

Note 1: Resistance is defined as the resistance between terminal A to terminal B.

2: INL and DNL are measured at V_Wwith V_A= V_DDand V_B= V_SS

.

3: MCP4XX1 only.

4: MCP4XX2 only, includes V_WZSEand V_WFSE

.

5: Resistor terminals A, W and B’s polarity with respect to each other is not restricted.

6: This specification by design.

7: Non-linearity is affected by wiper resistance (R_W), which changes significantly overvoltage and

temperature.

8: The MCP4XX1 is externally connected to match the configurations of the MCP45X2 and MCP46X2, and

then tested.

9: POR/BOR is not rate dependent.

10: Supply current is independent of current through the resistor network

11: When HVC/A0 = V_IHH, the I_DDcurrent is less due to current into the HVC/A0 pin. See I_PUspecification

DS22107A-page 12

MCP454X/456X/464X/466X

SCL

SDA

93

91

90

92

STOP

Condition

START

Condition

2

FIGURE 1-1:

I C Bus Start/Stop Bits Timing Waveforms.

2

TABLE 1-1:

I C BUS START/STOP BITS REQUIREMENTS

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage VDD range is described in AC/DC characteristics

Param.

Symbol

No.

Characteristic

Standard Mode

Min

Max

Units

Conditions

F_SCL

0

100

400

1.7

3.4

400

100

—

kHz C_b= 400 pF, 1.8V - 5.5V

Fast Mode

kHz C_b= 400 pF, 2.7V - 5.5V

High-Speed 1.7

High-Speed 3.4

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

0

MHz C_b= 400 pF, 4.5V - 5.5V

0

MHz C_b= 100 pF, 4.5V - 5.5V

D102

90

Cb

Bus capacitive

loading

—

pF

—

TSU:STA START condition

Setup time

4700

600

160

4000

600

160

4000

600

160

4000

600

160

ns

Only relevant for repeated

START condition

—

91

THD:STA START condition

Hold time

—

After this period the first

clock pulse is generated

—

92

TSU:STO STOP condition

Setup time

—

93

THD:STO STOP condition

Hold time

—

DS22107A-page 13

MCP454X/456X/464X/466X

103

102

100

101

SCL

90

106

91

92

107

SDA

In

110

109

SDA

Out

2

FIGURE 1-2:

I C Bus Data Timing.

2

TABLE 1-2:

I C BUS DATA REQUIREMENTS (SLAVE MODE)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max Units

Conditions

Clockhightime 100 kHz mode

400 kHz mode

4000

600

120

60

—

ns

1.8V-5.5V

100

THIGH

2.7V-5.5V

4.5V-5.5V

1.8V-5.5V

2.7V-5.5V

4.5V-5.5V

1.7 MHz mode

3.4 MHz mode

—

101

TLOW

Clock low time 100 kHz mode

400 kHz mode

4700

1300

320

160

1.7 MHz mode

3.4 MHz mode

—

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

T_Rmax.+t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V_IH

and V_ILof the falling edge of the SCL signal. This specification is not a part of the I²C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

7: Ensured by the T_AA3.4 MHz specification test.

DS22107A-page 14

MCP454X/456X/464X/466X

2

TABLE 1-2:

I C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature

–40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max Units

Conditions

102A ⁽⁵⁾

T_RSCL

SCL rise time

100 kHz mode

400 kHz mode

1.7 MHz mode

—

20 + 0.1Cb

20

1000

300

80

ns

Cb is specified to be from

10 to 400 pF (100 pF maxi-

mum for 3.4 MHz mode)

20

160

After a Repeated Start con-

dition or an Acknowledge

bit

3.4 MHz mode

10

40

80

ns

After a Repeated Start

condition or an Acknowl-

edge bit

102B ⁽⁵⁾

T_RSDA

T_FSCL

T_FSDA

SDA rise time

SCL fall time

SDA fall time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

—

1000

300

160

80

ns

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

20 + 0.1Cb

20

10

103A ⁽⁵⁾

—

300

80

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

20 + 0.1Cb

20

10

—

40

103B ⁽⁵⁾

300

Cb is specified to be from

10 to 400 pF (100 pF max

for 3.4 MHz mode)

400 kHz mode 20 + 0.1Cb ⁽⁴⁾300

1.7 MHz mode

3.4 MHz mode

20

10

0

160

80

—

106

T_HD:DATData input hold 100 kHz mode

1.8V-5.5V, Note 6

2.7V-5.5V, Note 6

4.5V-5.5V, Note 6

time

400 kHz mode

0

—

1.7 MHz mode

3.4 MHz mode

0

—

0

—

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

T_Rmax.+t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V_IH

and V_ILof the falling edge of the SCL signal. This specification is not a part of the I²C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

7: Ensured by the T_AA3.4 MHz specification test.

DS22107A-page 15

MCP454X/456X/464X/466X

2

TABLE 1-2:

I C BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)

I²C AC Characteristics

Standard Operating Conditions (unless otherwise specified)

Operating Temperature –40°C ≤ TA ≤ +125°C (Extended)

Operating Voltage V_DDrange is described in AC/DC characteristics

Param.

No.

Sym

Characteristic

Min

Max Units

Conditions

107

T_SU:DATData input setup 100 kHz mode

250

100

10

—

ns

Note 2

Note 1

time

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

109

T_AA

Output valid

from clock

100 kHz mode

400 kHz mode

1.7 MHz mode

3450

900

150

—

Cb = 100 pF,

Note 1, Note 7

—

310

ns

Cb = 400 pF,

Note 1, Note 5

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

4700

1300

N.A.

—

150

—

ns

Cb = 100 pF, Note 1

110

TBUF

Bus free time

Time the bus must be free

before a new transmission

can start

—

T_SP

Input filter spike 100 kHz mode

50

10

Philips Spec states N.A.

suppression

(SDA and SCL)

400 kHz mode

—

1.7 MHz mode

—

Spike suppression

3.4 MHz mode

—

Note 1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

2: A fast-mode (400 kHz) I²C-bus device can be used in a standard-mode (100 kHz) I²C-bus system, but the

requirement t_SU;DAT≥ 250 ns must then be met. This will automatically be the case if the device does not

stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal,

it must output the next data bit to the SDA line

T_Rmax.+t_SU;DAT= 1000 + 250 = 1250 ns (according to the standard-mode I²C bus specification) before

the SCL line is released.

3: The MCP46X1/MCP46X2 device must provide a data hold time to bridge the undefined part between V_IH

and V_ILof the falling edge of the SCL signal. This specification is not a part of the I²C specification, but

must be tested in order to ensure that the output data will meet the setup and hold specifications for the

receiving device.

4: Use Cb in pF for the calculations.

5: Not Tested

6: A Master Transmitter must provide a delay to ensure that difference between SDA and SCL fall times do

not unintentionally create a Start or Stop condition.

7: Ensured by the T_AA3.4 MHz specification test.

DS22107A-page 16

MCP454X/456X/464X/466X

TEMPERATURE CHARACTERISTICS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Sym

Min

Typ

Max

Units

Conditions

Temperature Ranges

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 8L-DFN (3x3)

Thermal Resistance, 8L-MSOP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 10L-DFN (3x3)

Thermal Resistance, 10L-MSOP

Thermal Resistance, 14L-MSOP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 16L-QFN

T_A

-40

-65

—

+125

+150

°C

θ_JA

—

60

211

145.5

57

—

°C/W

202

N/A

95.3

47

DS22107A-page 17

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 18

MCP454X/456X/464X/466X

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

250

200

150

100

50

1000

800

600

400

200

0

450

3.4MHz, 5.5V

400

350

300

250

200

150

100

50

3.4MHz, 2.7V

1.7MHz, 5.5V

I_HVC

1.7MHz, 2.7V

400kHz, 5.5V

-200

-400

-600

-800

-1000

100kHz, 5.5V

400kHz, 2.7V

100kHz, 2.7V

R_HVC

0

-40

0

40

Temperature (°C)

80

120

2

3

4

5

6

7

8

9

10

V

_HVC(V)

2

FIGURE 2-1:

Frequency (f

Device Current (I ) vs. I C

) and Ambient Temperature

FIGURE 2-4:

Resistance (R

HVC Pull-up/Pull-down

DD

) and Current (I ) vs. HVC

SCL

HVC

(V = 2.7V and 5.5V).

Input Voltage (V

) (V = 5.5V).

DD

HVC

DD

12

10

3

2.5

5.5V Entry

5.5V Exit

2.7V Entry

8

6

4

2

0

5.5V

2

1.5

1

2.7V Exit

2.7V

0.5

-40

0

40

Temperature (°C)

80

120

-40 -20

0

20

40

60

80 100 120

Ambient Temperature (°C)

FIGURE 2-2:

Device Current (I

) and

FIGURE 2-5:

HVC High Input Entry/Exit

SHDN

V

. (HVC = V ) vs. Ambient Temperature.

Threshold vs. Ambient Temperature and V

.

DD

420

400

380

360

5.5V

340

320

300

-40

0

40

80

120

Temperature (°C)

FIGURE 2-3:

Write Current (I

) vs.

WRITE

Ambient Temperature.

DS22107A-page 19

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1.25

0.75

0.25

-0.25

-0.75

-1.25

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

DNL

40

-40°C

-40°C 25°C

R_W

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-6:

5 kΩ Pot Mode – R (Ω),

FIGURE 2-8:

5 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

6

260

220

180

140

100

60

260

220

180

140

100

60

INL

4

DNL

2

R_W

125°C

-0.1

-0.2

-0.3

0

-40°C

85°C

25°C

DNL

-40°C

125°C 85°C

20

-2

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-7:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

5 kΩ Pot Mode – R (Ω),

FIGURE 2-9:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

5 kΩ Rheo Mode – R (Ω),

W

DD

DS22107A-page 20

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

6000

5000

4000

3000

2000

1000

0

5300

5250

5200

5150

5100

5050

2.7V

5.5V

-40°C

25°C

85°C

125°C

-40

0

40

80

120

0

32

64

96

128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-10:

5 kΩ – Nominal Resistance

FIGURE 2-11:

5 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22107A-page 21

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-12:

5 kΩ – Low-Voltage

FIGURE 2-15:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-13:

5 kΩ – Low-Voltage

FIGURE 2-16:

5 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-14:

5 kΩ – Power-Up Wiper

Response Time (20 ms/Div).

DS22107A-page 22

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.5

0

INL

DNL

60

-0.1

-0.2

-0.3

-0.5

-1

DNL

40

-40°C

R_W

-40°C

25°C

85°C

85°C 25°C

R_W

125°C

20

0

25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-17:

10 kΩ Pot Mode – R (Ω),

FIGURE 2-19:

10 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

4

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

260

220

180

140

100

60

3

260

220

180

140

100

60

INL

DNL

2

1

0

-0.1

-0.2

-0.3

R_W

DNL

R_W

-1

-2

-40°C

25°C

85°C 25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

25 50 75 100 125 150 175 200 225 250

Wiper Setting (decimal)

FIGURE 2-18:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

10 kΩ Pot Mode – R (Ω),

FIGURE 2-20:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

10 kΩ Rheo Mode – R (Ω),

W

DD

DS22107A-page 23

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

12000

10000

8000

6000

4000

2000

0

10300

10250

10200

10150

10100

2.7V

10050

10000

-40°C

25°C

85°C

5.5V

9950

1.8V

9900

9850

125°C

-40

0

40

80

120

0

32

64

96 128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-21:

10 kΩ – Nominal Resistance

FIGURE 2-22:

10 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22107A-page 24

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-23:

10 kΩ – Low-Voltage

FIGURE 2-26:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-24:

10 kΩ – Low-Voltage

FIGURE 2-27:

10 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-25:

10 kΩ – Power-Up Wiper

Response Time (1 µs/Div).

DS22107A-page 25

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.3

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

-0.3

-40°C

40

-40°C

R_W

25°C

85°C

25°C

85°C

R_W

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-28:

50 kΩ Pot Mode – R (Ω),

FIGURE 2-30:

50 kΩ Rheo Mode – R (Ω),

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

1

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

0.75

0.5

0.25

0

260

220

180

140

100

60

260

220

180

140

100

60

INL

DNL

-0.25

-0.5

-0.75

-1

R_W

-0.1

-0.2

-0.3

R_W

-40°C

25°C

85°C

25°C

85°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-29:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

50 kΩ Pot Mode – R (Ω),

FIGURE 2-31:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

50 kΩ Rheo Mode – R (Ω),

W

DD

DS22107A-page 26

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

52500

52000

51500

51000

50500

50000

49500

49000

60000

50000

40000

30000

20000

10000

0

1.8V

-40°C

25°C

85°C

125°C

2.7V

5.5V

-40

0

40

80

120

0

32

64

96 128 160 192 224 256

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-32:

50 kΩ – Nominal Resistance

FIGURE 2-33:

50 kΩ – R

(Ω) vs. Wiper

WB

(Ω) vs. Ambient Temperature and V

.

Setting and Ambient Temperature.

DD

DS22107A-page 27

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-34:

50 kΩ – Low-Voltage

FIGURE 2-37:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V = 5.5V)

DD

(1 µs/Div).

FIGURE 2-35:

50 kΩ – Low-Voltage

FIGURE 2-38:

50 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

FIGURE 2-36:

50 kΩ – Power-Up Wiper

Response Time (1 µs/Div).

DS22107A-page 28

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120

100

80

0.2

0.1

0

120

100

80

0.3

0.2

0.1

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

INL

DNL

60

-0.1

-0.2

-0.3

-0.1

-0.2

40

-40°C

R_W

25°C

85°C

R_W

85°C 25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-39:

100 kΩ Pot Mode – R (Ω),

FIGURE 2-41:

100 kΩ Rheo Mode – R

W

INL (LSb), DNL (LSb) vs. Wiper Setting and

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 5.5V).

DD

300

0.6

0.4

0.2

0

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

300

0.2

-40C Rw

-40C INL

-40C DNL

25C Rw

25C INL

25C DNL

85C Rw

85C INL

85C DNL

125C Rw

125C INL

125C DNL

260

220

180

140

100

60

0.15

0.1

260

220

180

140

100

60

INL

DNL

0.05

0

-0.05

-0.1

-0.15

-0.2

-0.4

-0.6

R_W

-40°C

85°C 25°C

125°C

85°C

25°C

125°C

20

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

0

32 64 96 128 160 192 224 256

Wiper Setting (decimal)

FIGURE 2-40:

INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

100 kΩ Pot Mode – R (Ω),

FIGURE 2-42:

(Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and

Ambient Temperature (V = 3.0V).

100 kΩ Rheo Mode – R

W

DD

DS22107A-page 29

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

120000

100000

80000

60000

40000

20000

0

103500

103000

102500

102000

101500

1.8V

101000

100500

-40°C

25°C

85°C

100000

2.7V

99500

99000

98500

5.5V

125°C

0

32

64

96 128 160 192 224 256

-40

0

40

80

120

Ambient Temperature (°C)

Wiper Setting (decimal)

FIGURE 2-43:

100 kΩ – Nominal

FIGURE 2-44:

100 kΩ – R

(Ω) vs. Wiper

WB

Resistance (Ω) vs. Ambient Temperature and

Setting and Ambient Temperature.

V

.

DD

DS22107A-page 30

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

FIGURE 2-45:

100 kΩ – Low-Voltage

FIGURE 2-47:

100 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 5.5V)

Increment Wiper Settling Time (V =5.5V)

DD

(1 µs/Div).

FIGURE 2-46:

100 kΩ – Low-Voltage

FIGURE 2-48:

100 kΩ – Low-Voltage

Decrement Wiper Settling Time (V = 2.7V)

Increment Wiper Settling Time (V = 2.7V)

DD

(1 µs/Div).

(1 µs/Div)

DS22107A-page 31

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

0.12

0.1

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

0.08

0.06

0.04

0.02

0

5.5V

3.0V

0

3.0V

-40

40

80

120

-40

0

40

Temperature (°C)

80

120

Temperature (°C)

FIGURE 2-49:

Resistor Network 0 to

FIGURE 2-51:

Resistor Network 0 to

Resistor Network 1 R (5 kΩ) Mismatch vs. V

and Temperature.

Resistor Network 1 R (50 kΩ) Mismatch vs.

AB

DD

AB

V

and Temperature.

DD

0.04

0.03

0.02

0.05

0.04

0.03

0.02

0.01

5.5V

0.01

0

-0.01

3.0V

0

3.0V

-0.02

-0.01

-0.02

-0.03

-0.04

-40

0

40

80

120

-40

10

60

110

Temperature (°C)

FIGURE 2-50:

Resistor Network 0 to

FIGURE 2-52:

Resistor Network 0 to

Resistor Network 1 R (10 kΩ) Mismatch vs.

Resistor Network 1 R (100 kΩ) Mismatch vs.

AB

V

and Temperature.

V

and Temperature.

DD

DS22107A-page 32

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C, V_DD= 5V, V_SS= 0V.

4

3.5

3

230

210

190

170

150

130

110

90

2.7V

5.5V

2.7V

2.5

2

1.5

1

70

50

-40

0

40

Temperature (°C)

80

120

-40

0

40

Temperature (°C)

80

120

FIGURE 2-53:

V

(SDA, SCL) vs. V and

FIGURE 2-55:

V

(SDA) vs. V and

OL DD

IH

DD

Temperature.

Temperature (I = 3 mA).

OL

2

5.5V

1.5

2.7V

1

-40

0

40

Temperature (°C)

80

120

FIGURE 2-54:

V (SDA, SCL) vs. V and

IL DD

Temperature.

DS22107A-page 33

MCP454X/456X/464X/466X

Note: Unless otherwise indicated, T_A= +25°C,

V_DD= 5V, V_SS= 0V.

2.1

Test Circuits

4.2

4.0

+5V

A

B

V

IN

3.8

3.6

3.4

3.2

3.0

W

V

+

-

OUT

Offset

GND

2.5V DC

-40

0

40

80

120

Temperature (°C)

FIGURE 2-58:

Test.

-3 db Gain vs. Frequency

FIGURE 2-56:

Cycle Time vs. V and Temperature.

Nominal EEPROM Write

DD

1.2

1

5.5V

0.8

0.6

0.4

0.2

0

2.7V

-40

0

40

80

120

Temperature (°C)

FIGURE 2-57:

POR/BOR Trip point vs. V

DD

and Temperature.

DS22107A-page 34

MCP454X/456X/464X/466X

3.0

PIN DESCRIPTIONS

The descriptions of the pins are listed in Table 3-1.

Additional descriptions of the device pins follows.

TABLE 3-1:

PINOUT DESCRIPTION FOR THE MCP454X/456X/464X/466X

Weak

Single

Dual

Pot

Pull-up/

Standard Function

Buffer

Type

Rheo Pot ⁽¹⁾Rheo

Symbol

I/O

down ⁽¹⁾

8L

10L

14L

16L

1

16

HVC/A0

I

HV w/ST “smart” High Voltage Command /

Address 0.

2

3

2

3

2

3

2

3

1

2

SCL

SDA

HV w/ST

No

I²C clock input.

I/O HV w/ST

I²C serial data I/O. Open Drain

output

4

—

5

4

5

4

5

3, 4

5

V_SS

P1B

P1W

P1A

P0A

P0W

P0B

WP

—

A

I

P

—

No

Ground

—

5

Analog

Potentiometer 1 Terminal B

Potentiometer 1 Wiper Terminal

Potentiometer 1 Terminal A

Potentiometer 0 Terminal A

Potentiometer 0 Wiper Terminal

Potentiometer 0 Terminal B

6

—

7

8

6

9

6

7

8

10

11

10

12

—

HV w/ST “smart” Hardware EEPROM Write

Protect

—

8

—

9

12

13

14

—

13

14

15

11

17

A2

A1

I

HV w/ST “smart” Address 2

HV w/ST “smart” Address 1

7

I

8

10

—

11

V_DD

NC

EP

—

P

—

Positive Power Supply Input

No Connection

—

9

—

9

Exposed Pad (Note 2)

Legend:

HV w/ST = High Voltage tolerant input (with Schmidtt trigger input)

A = Analog pins (Potentiometer terminals)

O = digital output

I = digital input (high Z)

I/O = Input / Output

P = Power

Note 1: The pin’s “smart” pull-up shuts off while the pin is forced low. This is done to reduce the standby and shut-

down current.

2: The DFN and QFN packages have a contact on the bottom of the package. This contact is conductively

connected to the die substrate, and therefore should be unconnected or connected to the same ground as

the device’s V_SSpin.

DS22107A-page 35

MCP454X/456X/464X/466X

3.1

High Voltage Command / Address 0

(HVC/A0)

3.7

Potentiometer Terminal A

The terminal A pin is available on the MCP4XX1

devices, and is connected to the internal potentiome-

ter’s terminal A.

The HVC/A0 pin is the Address 0 input for the I²C

interface as well as the High Voltage Command pin. At

the device’s POR/BOR the value of the A0 address bit

is latched. This input along with the A2 and A1 pins

completes the device address. This allows up to 8

MCP45xx/46xx devices can be on a single I²C bus.

The potentiometer’s terminal A is the fixed connection

to the Full-Scale wiper value of the digital potentiome-

ter. This corresponds to a wiper value of 0x100 for 8-bit

devices or 0x80 for 7-bit devices.

During normal operation the the voltage on this pin

determines if the I²C command is a normal command

or a High Voltage command (when HVC/A0 = V_IHH).

The terminal A pin does not have a polarity relative to

the terminal W or B pins. The terminal A pin can

support both positive and negative current. The voltage

on terminal A must be between V_SSand V_DD

.

3.2

Serial Clock (SCL)

The terminal A pin is not available on the MCP4XX2

devices, and the internally terminal A signal is floating.

The SCL pin is the serial interfaces Serial Clock pin.

This pin is connected to the Host Controllers SCL pin.

The MCP45XX/46XX is a slave device, so it’s SCL pin

accepts only external clock signals.

MCP46X1 devices have two terminal A pins, one for

each resistor network.

3.8

Write Protect (WP)

3.3

Serial Data (SDA)

The WP pin is used to force the non-volatile memory to

be write protected.

The SDA pin is the serial interfaces Serial Data pin.

This pin is connected to the Host Controllers SDA pin.

The SDA pin is an open-drain N-channel driver.

3.9

Address 2 (A2)

The A2 pin is the I²C interface’s Address 2 pin. Along

with the A1 and A0 pins, up to 8 MCP45XX/46XX

devices can be on a single I²C bus.

3.4

Ground (V_SS)

The V_SSpin is the device ground reference.

3.5

Potentiometer Terminal B

3.10 Address 1 (A1)

The A2 pin is the I²C interface’s Address 1 pin. Along

with the A2 and A0 pins, up to 8 MCP45XX/46XX

devices can be on a single I²C bus.

The terminal B pin is connected to the internal

potentiometer’s terminal B.

The potentiometer’s terminal B is the fixed connection

to the Zero Scale wiper value of the digital potentiome-

ter. This corresponds to a wiper value of 0x00 for both

7-bit and 8-bit devices.

3.11 Positive Power Supply Input (V_DD

)

The V_DDpin is the device’s positive power supply input.

The input power supply is relative to V_SS

The terminal B pin does not have a polarity relative to

the terminal W or A pins. The terminal B pin can

support both positive and negative current. The voltage

.

While the device V_DD< V_min(2.7V), the electrical

performance of the device may not meet the data sheet

specifications.

on terminal B must be between V_SSand V_DD

.

MCP46XX devices have two terminal B pins, one for

each resistor network.

3.12 No Connect (NC)

These pins should be either connected to V_DDor V_SS

.

3.6

Potentiometer Wiper (W) Terminal

The terminal W pin is connected to the internal potenti-

ometer’s terminal W (the wiper). The wiper terminal is

the adjustable terminal of the digital potentiometer. The

terminal W pin does not have a polarity relative to

terminals A or B pins. The terminal W pin can support

both positive and negative current. The voltage on

3.13 Exposed Pad (EP)

This pad is conductively connected to the device’s sub-

strate. This pad should be tied to the same potential as

the V_SSpin (or left unconnected). This pad could be

used to assist as a heat sink for the device when con-

nected to a PCB heat sink.

terminal W must be between V_SSand V_DD

.

MCP46XX devices have two terminal W pins, one for

each resistor network.

DS22107A-page 36

MCP454X/456X/464X/466X

4.1.2

BROWN-OUT RESET

4.0

FUNCTIONAL OVERVIEW

When the device powers down, the device V_DDwill

cross the V_POR/V_BORvoltage.

This Data Sheet covers a family of thirty-two Digital

Potentiometer and Rheostat devices that will be

referred to as MCP4XXX. The MCP4XX1 devices are

the Potentiometer configuration, while the MCP4XX2

devices are the Rheostat configuration.

Once the V_DDvoltage decreases below the V_POR/V_BOR

voltage the following happens:

• Serial Interface is disabled

As the Device Block Diagram shows, there are four

main functional blocks. These are:

• EEPROM Writes are disabled

If the V_DDvoltage decreases below the V_RAMvoltage

the following happens:

• POR/BOR Operation

• Memory Map

• Volatile wiper registers may become corrupted

• TCON register may become corrupted

• Resistor Network

• Serial Interface (I²C)

As the voltage recovers above the V_POR/V_BORvoltage

The POR/BOR operation and the Memory Map are

discussed in this section and the Resistor Network and

I²C operation are described in their own sections. The

Device Commands commands are discussed in

Section 7.0 “Device Commands”.

see Section 4.1.1 “Power-on Reset”.

Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and

non-volatile) to become corrupted.

4.2

Memory Map

4.1

POR/BOR Operation

The device memory is 16 locations that are 9-bits wide

(16x9 bits). This memory space contains both volatile

and non-volatile locations (see Table 4-1).

The Power-on Reset is the case where the device is

having power applied to it starting from the V_SSlevel.

The Brown-out Reset occurs when a device had power

applied to it, and that power (voltage) drops below the

specified range.

TABLE 4-1:

Address

MEMORY MAP

Function

Memory Type

The devices RAM retention voltage (V_RAM) is lower

than the POR/BOR voltage trip point (V_POR/V_BOR). The

maximum V_POR/V_BORvoltage is less than 1.8V.

00h

01h

02h

03h

04h

05h

06h

07h

08h

09h

0Ah

0Bh

0Ch

0Dh

0Eh

0Fh

Volatile Wiper 0

Volatile Wiper 1

RAM

When V_POR/V_BOR< V_DD< 2.7V, the electrical

performance may not meet the data sheet

specifications. In this region, the device is capable of

reading and writing to its EEPROM and incrementing,

decrementing, reading and writing to its volatile

memory if the proper serial command is executed.

Non-Volatile Wiper 0

Non-Volatile Wiper 1

Volatile TCON Register

Status Register

Data EEPROM

EEPROM

RAM

EEPROM

4.1.1

POWER-ON RESET

When the device powers up, the device V_DDwill cross

the V_POR/V_BORvoltage. Once the V_DDvoltage crosses

the V_POR/V_BORvoltage the following happens:

• Volatile wiper register is loaded with value in the

corresponding non-volatile wiper register

• The TCON register is loaded it’s default value

• The device is capable of digital operation

DS22107A-page 37

MCP454X/456X/464X/466X

4.2.1

NON-VOLATILE MEMORY

(EEPROM)

4.2.1.4

Special Features

There are 3 non-volatile bits that are not directly

mapped into the address space. These bits control the

following functions:

This memory can be grouped into two uses of non-vol-

atile memory. These are:

• EEPROM Write Protect

• General Purpose Registers

• Non-Volatile Wiper Registers

• WiperLock Technology for Non-Volatile Wiper 0

• WiperLock Technology for Non-Volatile Wiper 1

The non-volatile wipers starts functioning below the

devices V_POR/V_BORtrip point.

The operation of WiperLock Technology is discussed in

Section 5.3. The state of the WL0, WL1, and WP bits

is reflected in the STATUS register (see Register 4-1).

4.2.1.1

General Purpose Registers

These locations allow the user to store up to 10 (9-bit)

locations worth of information.

EEPROM Write Protect

All internal EEPROM memory can be Write Protected.

When EEPROM memory is Write Protected, Write

commands to the internal EEPROM are prevented.

4.2.1.2

Non-Volatile Wiper Registers

These locations contain the wiper values that are

loaded into the corresponding volatile wiper register

whenever the device has a POR/BOR event. There are

up to two registers, one for each resistor network.

Write Protect (WP) can be enabled/disabled by two

methods. These are:

• External WP Hardware pin (MCP46X1 devices

only)

The non-volatile wiper register enables stand-alone

operation of the device (without Microcontroller control)

after being programmed to the desired value.

• Non-Volatile configuration bit

High Voltage commands are required to enable and

disable the nonvolatile WP bit. These commands are

shown in Section 7.8 “Modify Write Protect or Wip-

erLock Technology (High Voltage)”.

4.2.1.3

Factory Initialization of Non-Volatile

Memory (EEPROM)

The Non-Volatile Wiper values will be initialized to

mid-scale value. This is shown in Table 4-2.

To write to EEPROM, both the external WP pin and the

internal WP EEPROM bit must be disabled. Write

Protect does not block commands to the volatile

registers.

The General purpose EEPROM memory will be

programmed to a default value of 0xFF.

It is good practice in the manufacturing flow to

configure the device to your desired settings.

4.2.2

VOLATILE MEMORY (RAM)

There are four Volatile Memory locations. These are:

• Volatile Wiper 0

TABLE 4-2:

DEFAULT FACTORY

SETTINGS SELECTION

• Volatile Wiper 1

(Dual Resistor Network devices only)

Wiper

Code

• Status Register

• Terminal Control (TCON) Register

The volatile memory starts functioning at the RAM

retention voltage (V_RAM).

8-bit 7-bit

-502

5.0 kΩ Mid-scale 80h 40h Disabled

-103 10.0 kΩ Mid-scale 80h 40h Disabled

-503 50.0 kΩ Mid-scale 80h 40h Disabled

-104 100.0 kΩ Mid-scale 80h 40h Disabled

DS22107A-page 38

MCP454X/456X/464X/466X

4.2.2.1

Status (STATUS) Register

This register contains 4 status bits. These bits show the

state of the WiperLock bits, the Write Protect bit, and if

an EEPROM write cycle is active. The STATUS register

can be accessed via the READ commands.

Register 4-1 describes each STATUS register bit.

The STATUS register is placed at Address 05h.

REGISTER 4-1:

STATUS REGISTER (ADDRESS = 0x05)

R-1

R-0

R-x

(1)

D8:D4

EEWA

WL1

WL0

WP ⁽¹⁾

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

-n = Value at POR

bit 8-4

bit 3

D8:D4: Reserved. Forced to “1”

EEWA: EEPROM Write Active Status bit

This bit indicates if the EEPROM Write Cycle is occurring.

1= An EEPROM Write cycle is currently occurring. Only serial commands to the Volatile memory

locations are allowed (addresses 00h, 01h, 04h, and 05h)

0= An EEPROM Write cycle is NOT currently occurring

bit 2

WL1: WiperLock Status bit for Resistor Network 1 (Refer to Section 5.3 “WiperLock™ Technology”

for further information)

WiperLock (WL) prevents the Volatile and Non-Volatile Wiper 1 addresses and the TCON register bits

R1HW, R1A, R1W, and R1B from being written to. High Voltage commands are required to enable and

disable WiperLock Technology.

1= Wiper and TCON register bits R1HW, R1A, R1W, and R1B of Resistor Network 1 (Pot 1) are

“Locked” (Write Protected)

0= Wiper and TCON of Resistor Network 1 (Pot 1) can be modified

Note:

The WL1 bit always reflects the result of the last programming cycle to the non-volatile WL1

bit. After a POR or BOR event, the WL1 bit is loaded with the non-volatile WL1 bit value.

bit 1

WL0: WiperLock Status bit for Resistor Network 0 (Refer to Section 5.3 “WiperLock™ Technology”

for further information)

The WiperLock Technology bits (WLx) prevents the Volatile and Non-Volatile Wiper 0 addresses and

the TCON register bits R0HW, R0A, R0W, and R0B from being written to. High Voltage commands are

required to enable and disable WiperLock Technology.

1= Wiper and TCON register bits R0HW, R0A, R0W, and R0B of Resistor Network 0 (Pot 0) are

“Locked” (Write Protected)

0= Wiper and TCON of Resistor Network 0 (Pot 0) can be modified

Note:

The WL0 bit always reflects the result of the last programming cycle to the non-volatile WL0

bit. After a POR or BOR event, the WL0 bit is loaded with the non-volatile WL0 bit value.

Note 1: Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is

Not directly written, but reflects the system state (for this feature).

DS22107A-page 39

MCP454X/456X/464X/466X

REGISTER 4-1:

STATUS REGISTER (ADDRESS = 0x05) (CONTINUED)

bit 0 WP: EEPROM Write Protect Status bit (Refer to Section “EEPROM Write Protect” for further infor-

mation)

This bit indicates the status of the write protection on the EEPROM memory. When Write Protect is

enabled, writes to all non-volatile memory are prevented. This includes the General Purpose EEPROM

memory, and the non-volatile Wiper registers. Write Protect does not block modification of the volatile

wiper register values or the volatile TCON register value (via Increment, Decrement, or Write

commands).

This status bit is an OR of the devices Write Protect pin (WP) and the internal non-volatile WP bit. High

Voltage commands are required to enable and disable the internal WP EEPROM bit.

1= EEPROM memory is Write Protected

0= EEPROM memory can be written

Note 1: Requires a High Voltage command to modify the state of this bit (for Non-Volatile devices only). This bit is

Not directly written, but reflects the system state (for this feature).

DS22107A-page 40

MCP454X/456X/464X/466X

4.2.2.2

Terminal Control (TCON) Register

This register contains 8 control bits. Four bits are for

Wiper 0, and four bits are for Wiper 1. Register 4-2

describes each bit of the TCON register.

The state of each resistor network terminal connection

is individually controlled. That is, each terminal

connection (A, B and W) can be individually connected/

disconnected from the resistor network. This allows the

system to minimize the currents through the digital

potentiometer.

The value that is written to this register will appear on

the resistor network terminals when the serial

command has completed.

When the WL1 bit is enabled, writes to the TCON

register bits R1HW, R1A, R1W, and R1B are inhibited.

When the WL0 bit is enabled, writes to the TCON

register bits R0HW, R0A, R0W, and R0B are inhibited.

On a POR/BOR this register is loaded with 1FFh

(9-bits), for all terminals connected. The Host

Controller needs to detect the POR/BOR event and

then update the Volatile TCON register value.

Additionally, there is a bit which enables the operation

of General Call commands.

DS22107A-page 41

MCP454X/456X/464X/466X

(1)

REGISTER 4-2:

TCON BITS (ADDRESS = 0x04)

R/W-1

GCEN

R/W-1

R1HW

R/W-1

R1A

R/W-1

R1W

R/W-1

R1B

R/W-1

R0HW

R/W-1

R0A

R/W-1

R0W

R/W-1

R0B

bit 8

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared x = Bit is unknown

bit 8

GCEN: General Call Enable bit

This bit specifies if I²C General Call commands are accepted

1= Enable Device to “Accept” the General Call Address (0000h)

0= The General Call Address is disabled

bit 7

R1HW: Resistor 1 Hardware Configuration Control bit

This bit forces Resistor 1 into the “shutdown” configuration of the Hardware pin

1= Resistor 1 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 1 is forced to the hardware pin “shutdown” configuration

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

R1A: Resistor 1 Terminal A (P1A pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal A to the Resistor 1 Network

1= P1A pin is connected to the Resistor 1 Network

0= P1A pin is disconnected from the Resistor 1 Network

R1W: Resistor 1 Wiper (P1W pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Wiper to the Resistor 1 Network

1= P1W pin is connected to the Resistor 1 Network

0= P1W pin is disconnected from the Resistor 1 Network

R1B: Resistor 1 Terminal B (P1B pin) Connect Control bit

This bit connects/disconnects the Resistor 1 Terminal B to the Resistor 1 Network

1= P1B pin is connected to the Resistor 1 Network

0= P1B pin is disconnected from the Resistor 1 Network

R0HW: Resistor 0 Hardware Configuration Control bit

This bit forces Resistor 0 into the “shutdown” configuration of the Hardware pin

1= Resistor 0 is NOT forced to the hardware pin “shutdown” configuration

0= Resistor 0 is forced to the hardware pin “shutdown” configuration

R0A: Resistor 0 Terminal A (P0A pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal A to the Resistor 0 Network

1= P0A pin is connected to the Resistor 0 Network

0= P0A pin is disconnected from the Resistor 0 Network

R0W: Resistor 0 Wiper (P0W pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Wiper to the Resistor 0 Network

1= P0W pin is connected to the Resistor 0 Network

0= P0W pin is disconnected from the Resistor 0 Network

R0B: Resistor 0 Terminal B (P0B pin) Connect Control bit

This bit connects/disconnects the Resistor 0 Terminal B to the Resistor 0 Network

1= P0B pin is connected to the Resistor 0 Network

0= P0B pin is disconnected from the Resistor 0 Network

Note 1: These bits do not affect the wiper register values.

DS22107A-page 42

MCP454X/456X/464X/466X

5.1

Resistor Ladder Module

5.0

RESISTOR NETWORK

The resistor ladder is a series of equal value resistors

(R_S) with a connection point (tap) between the two

resistors. The total number of resistors in the series

(ladder) determines the R_ABresistance (see

Figure 5-1). The end points of the resistor ladder are

connected to analog switches which are connected to

the device Terminal A and Terminal B pins. The R_AB

(and R_S) resistance has small variations over voltage

and temperature.

The Resistor Network has either 7-bit or 8-bit resolu-

tion. Each Resistor Network allows zero scale to

full-scale connections. Figure 5-1 shows a block dia-

gram for the resistive network of a device.

The Resistor Network is made up of several parts.

These include:

• Resistor Ladder

• Wiper

• Shutdown (Terminal Connections)

For an 8-bit device, there are 256 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 256 resistors thus providing

257 possible settings (including terminal A and terminal

B).

Devices have either one or two resistor networks,

These are referred to as Pot 0 and Pot 1.

A

For a 7-bit device, there are 128 resistors in a string

between terminal A and terminal B. The wiper can be

set to tap onto any of these 128 resistors thus providing

129 possible settings (including terminal A and terminal

B).

8-Bit

N =

257

7-Bit

N =

128

(100h)

(80h)

(1)

R_W

R_S

Equation 5-1 shows the calculation for the step

resistance.

256

(FFh)

127

(7Fh)

(1)

R_W

EQUATION 5-1:

R CALCULATION

255

(FEh)

126

(7Eh)

S

R_AB

R_S= -------------

8-bit Device

(256)

W

R_AB

R_S= -------------

(128)

7-bit Device

1

(01h)

(1)

R_W

R_S

0

(00h)

Analog Mux

B

Note 1: The wiper resistance is dependent on

several factors including, wiper code,

device V_DD, Terminal voltages (on A, B,

and W), and temperature.

Also for the same conditions, each tap

selection resistance has a small variation.

This R_Wvariation has greater effects on

some specifications (such as INL) for the

smaller resistance devices (5.0 kΩ)

compared to larger resistance devices

(100.0 kΩ).

FIGURE 5-1:

Resistor Block Diagram.

DS22107A-page 43

MCP454X/456X/464X/466X

5.2

Wiper

5.3

WiperLock™ Technology

Each tap point (between the R_Sresistors) is a

connection point for an analog switch. The opposite

side of the analog switch is connected to a common

signal which is connected to the Terminal W (Wiper)

pin.

The MCP4XXX device’s WiperLock technology allows

application-specific calibration settings to be secured in

the EEPROM without requiring the use of an additional

write-protect pin. There are two WiperLock Technology

configuration bits (WL0 and WL1). These bits prevent

the Non-Volatile and Volatile addresses and bits for the

specified resistor network from being written.

A value in the volatile wiper register selects which

analog switch to close, connecting the W terminal to

the selected node of the resistor ladder.

The WiperLock technology prevents the serial

commands from doing the following:

The wiper can connect directly to Terminal B or to

Terminal A. A zero-scale connections, connects the

Terminal W (wiper) to Terminal B (wiper setting of

000h). A full-scale connections, connects the Terminal

W (wiper) to Terminal A (wiper setting of 100h or 80h).

In these configurations the only resistance between the

Terminal W and the other Terminal (A or B) is that of

the analog switches.

• Changing a volatile wiper value

• Writing to a non-volatile wiper memory location

• Changing the volatile TCON register value

For either Resistor Network 0 or Resistor Network 1

(Potx), the WLx bit controls the following:

• Non-Volatile Wiper Register

• Volatile Wiper Register

• Volatile TCON register bits RxHW, RxA, RxW,

and RxB

A wiper setting value greater than full-scale (wiper

setting of 100h for 8-bit device or 80h for 7-bit devices)

will also be a Full-Scale setting (Terminal W (wiper)

connected to Terminal A). Table 5-1 illustrates the full

wiper setting map.

High Voltage commands are required to enable and

disable WiperLock. Please refer to the Modify Write

Protect or WiperLock Technology (High Voltage)

command for operation.

Equation 5-2 illustrates the calculation used to deter-

mine the resistance between the wiper and terminal B.

5.3.1

POR/BOR OPERATION WHEN

WIPERLOCK TECHNOLOGY

ENABLED

EQUATION 5-2:

R

CALCULATION

WB

R_AB

N

R_WB= ------------- + R_W

8-bit Device

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the

Volatile Wiper register value with the Non-Volatile

Wiper register value, refer to Section 4.1.

(256)

N = 0 to 256 (decimal)

R_AB

N

7-bit Device

R_WB= ------------- + R_W

(128)

N = 0 to 128 (decimal)

TABLE 5-1:

VOLATILE WIPER VALUE VS.

WIPER POSITION MAP

Wiper Setting

7-bit Pot 8-bit Pot

Properties

3FFh

081h

3FFh

101h

Reserved (Full-Scale (W = A)),

Increment and Decrement

commands ignored

080h

100h

Full-Scale (W = A),

Increment commands ignored

07Fh

041h

0FFh

081

W = N

040h

080h

W = N (Mid-Scale)

W = N

03Fh

001h

07Fh

001

000h

Zero Scale (W = B)

Decrement command ignored

DS22107A-page 44

MCP454X/456X/464X/466X

5.4.2

INTERACTION OF RxHW BIT AND

RxA, RxW, AND RxB BITS (TCON

REGISTER)

5.4

Shutdown

Shutdown is used to minimize the device’s current

consumption. The MCP4XXX achieves this through the

Terminal Control Register (TCON).

Using the TCON bits allows each resistor network (Pot

0 and Pot 1) to be individually “shutdown”.

5.4.1

TERMINAL CONTROL REGISTER

(TCON)

The state of the RxHW bit does NOT corrupt the other

bit values in the TCON register nor the value of the

Volatile Wiper Registers. When the Shutdown mode is

exited (RxHW changes state from “0” to “1”):

The Terminal Control (TCON) register is a volatile

register used to configure the connection of each

resistor network terminal pin (A, B, and W) to the

Resistor Network. This bits are described in

Register 4-2.

• The device returns to the Wiper setting specified

by the Volatile Wiper value

• The RxA, RxB, and RxW bits return to controlling

the terminal connection state of that resistor net-

work

When the RxHW bit is a “0”, the selected resistor net-

work is forced into the following state:

• The PxA terminal is disconnected

• The PxW terminal is simultaneously connected to

the PxB terminal (see Figure 5-2)

• The Serial Interface is NOT disabled, and all

Serial Interface activity is executed

• Any EEPROM write cycles are completed

Alternate low power configurations may be achieved

with the RxA, RxW, and RxB bits.

Note 1: The RxHW bits are identical to the RxHW

bits of the MCP41XX/42XX devices. The

MCP42XX devices also have a SHDN

pin which forces the resistor network into

the same state as that resistor networks

RxHW bit.

2: When RxHW = “0”, the state of the TCON

register RxA, RxW, and RxB bits is over-

ridden (ignored). When the state of the

RxHW bit returns to “1”, the TCON

register RxA, RxW, and RxB bits return to

controlling the terminal connection state.

In other words, the RxHW bit does not

corrupt the state of the RxA, RxW, and

RxB bits.

A

W

B

FIGURE 5-2:

Resistor Network Shutdown

Configuration.

DS22107A-page 45

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 46

MCP454X/456X/464X/466X

2

6.1

Signal Descriptions

6.0

SERIAL INTERFACE (I C)

The I²C interface uses up to five pins (signals). These

are:

The MCP45XX/46XX devices support the I²C serial

protocol. The MCP45XX/46XX I²C’s module operates

in Slave mode (does not generate the serial clock).

Figure 6-1 shows a typical I²C Interface connection. All

I²C interface signals are high-voltage tolerant.

• SDA (Serial Data)

• SCL (Serial Clock)

• A0 (Address 0 bit)

• A1 (Address 1 bit)

• A2 (Address 2 bit)

The MCP45XX/46XX devices use the two-wire I²C

serial interface. This interface can operate in standard,

fast or High-Speed mode. A device that sends data

onto the bus is defined as transmitter, and a device

receiving data as receiver. The bus has to be controlled

by a master device which generates the serial clock

(SCL), controls the bus access and generates the

START and STOP conditions. The MCP45XX/46XX

device works as slave. Both master and slave can

operate as transmitter or receiver, but the master

device determines which mode is activated. Communi-

cation is initiated by the master (microcontroller) which

sends the START bit, followed by the slave address

byte. The first byte transmitted is always the slave

address byte, which contains the device code, the

address bits, and the R/W bit.

6.1.1

SERIAL DATA (SDA)

The Serial Data (SDA) signal is the data signal of the

device. The value on this pin is latched on the rising

edge of the SCL signal when the signal is an input.

With the exception of the START and STOP conditions,

the high or low state of the SDA pin can only change

when the clock signal on the SCL pin is low. During the

high period of the clock the SDA pin’s value (high or

low) must be stable. Changes in the SDA pin’s value

while the SCL pin is HIGH will be interpreted as a

START or a STOP condition.

6.1.2

SERIAL CLOCK (SCL)

Refer to the Phillips I²C document for more details of

the I²C specifications.

The Serial Clock (SCL) signal is the clock signal of the

device. The rising edge of the SCL signal latches the

value on the SDA pin. The MCP45XX/46XX supports

three I²C interface clock modes:

Typical I²C Interface Connections

• Standard Mode: clock rates up to 100 kHz

• Fast Mode: clock rates up to 400 kHz

• High-Speed Mode (HS mode): clock rates up to

3.4 MHz

MCP4XXX

SCL

Host

Controller

SCL

SDA

The MCP4XXX will not strech the clock signal (SCL)

since memory read acceses occur fast enough.

I/O ⁽¹⁾

HVC/A0 ⁽²⁾

A1 ^{(2, 3)}

A2 ^{(2, 3)}

Depending on the clock rate mode, the interface will

display different characteristics.

6.1.3

THE ADDRESS BITS (A2:A1:A0)

There are up to three hardware pins used to specify the

device address. The number of adress pins is

determined by the part number.

Note 1: If High voltage commands are desired,

some type of external circuitry needs to

be implemented.

Address 0 is multiplexed with the High Voltage

Command (HVC) function. So the state of A0 is latched

on the MCP4XXX’s POR/BOR event.

2: These pins have internal pull-ups. If

faster rise times are required, then

external pull-ups should be added.

The state of the A2 and A1 pins should be static, that is

they should be tied high or tied low.

3: This pin could be tied high, low, or

connected to an I/O pin of the Host

Controller.

6.1.3.1

The High Voltage Command (HVC)

Signal

2

FIGURE 6-1:

Typical I C Interface Block

Diagram.

The High Voltage Command (HVC) signal is multi-

plexed with Address 0 (A0) and is used to indicate that

the command, or sequence of commands, are in the

High Voltage mode. High Voltage commands allow the

device’s WiperLock Technology and write protect

features to be enabled and disabled.

The HVC pin has an internal resistor connection to the

MCP45XX/46XXs internal V_DDsignal.

DS22107A-page 47

MCP454X/456X/464X/466X

I²C Operation

6.2.1.3

Acknowledge (A) Bit

6.2

The MCP45XX/46XX’s I²C module is compatible with

the Philips I²C specification. The following lists some of

the modules features:

The A bit (see Figure 6-4) is typically a response from

the receiving device to the transmitting device.

Depending on the context of the transfer sequence, the

A bit may indicate different things. Typically the Slave

device will supply an A response after the Start bit and

8 “data” bits have been received. an A bit has the SDA

signal low.

• 7-bit slave addressing

• Supports three clock rate modes:

- Standard mode, clock rates up to 100 kHz

- Fast mode, clock rates up to 400 kHz

- High-speed mode (HS mode), clock rates up

to 3.4 MHz

• Support Multi-Master Applications

• General call addressing

• Internal weak pull-ups on interface signals

SDA

SCL

D0

A

8

9

The I²C 10-bit addressing mode is not supported.

FIGURE 6-4:

Acknowledge Waveform.

The Philips I²C specification only defines the field

types, field lengths, timings, etc. of a frame. The frame

content defines the behavior of the device. The frame

content for the MCP4XXX is defined in Section 7.0.

Not A (A) Response

The A bit has the SDA signal high. Table 6-1 shows

some of the conditions where the Slave Device will

issue a Not A (A).

2

6.2.1

I C BIT STATES AND SEQUENCE

Figure 6-8 shows the I²C transfer sequence. The serial

clock is generated by the master. The following defini-

tions are used for the bit states:

If an error condition occurs (such as an A instead of A),

then an START bit must be issued to reset the

command state machine.

• Start bit (S)

• Data bit

TABLE 6-1:

MCP45XX/MCP46XX A / A

RESPONSES

• Acknowledge (A) bit (driven low) /

No Acknowledge (A) bit (not driven low)

• Repeated Start bit (Sr)

• Stop bit (P)

Acknowledge

Event

Bit

Comment

Response

6.2.1.1

Start Bit

General Call

A

Only if GCEN bit is

set

The Start bit (see Figure 6-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “High”.

Slave Address

valid

Slave Address

not valid

2nd Bit

1st Bit

SDA

SCL

Device Mem-

ory Address

and specified

command

After device has

received address

and command

S

FIGURE 6-2:

Start Bit.

(AD3:AD0 and

C1:C0) are an

invalid combi-

nation

6.2.1.2 Data Bit

The SDA signal may change state while the SCL signal

is Low. While the SCL signal is High, the SDA signal

MUST be stable (see Figure 6-5).

Communica-

tion during

EEPROM write

cycle

A

After device has

received address

and command,

and valid condi-

tions for EEPROM

write

2nd Bit

1st Bit

SDA

SCL

Bus Collision

N.A.

I²C Module

Resets, or a “Don’t

Care” if the colli-

sion occurs on the

Masters “Start bit”.

Data Bit

FIGURE 6-3:

Data Bit.

DS22107A-page 48

MCP454X/456X/464X/466X

6.2.1.4

Repeated Start Bit

6.2.1.5

Stop Bit

The Repeated Start bit (see Figure 6-5) indicates the

current Master Device wishes to continue communicat-

ing with the current Slave Device without releasing the

I²C bus. The Repeated Start condition is the same as

the Start condition, except that the Repeated Start bit

follows a Start bit (with the Data bits + A bit) and not a

Stop bit.

The Stop bit (see Figure 6-6) Indicates the end of the

I²C Data Transfer Sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is “High”.

A Stop bit resets the I²C interface of all MCP4XXX

devices.

A / A

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “High”.

SDA

SCL

P

Note 1: A bus collision during the Repeated Start

condition occurs if:

FIGURE 6-6:

Stop Condition Receive or

Transmit Mode.

• SDA is sampled low when SCL goes

from low to high.

6.2.2

CLOCK STRETCHING

• SCL goes low before SDA is asserted

low. This may indicate that another

master is attempting to transmit a

data "1".

“Clock Stretching” is something that the receiving

Device can do, to allow additional time to “respond” to

the “data” that has been received.

The MCP4XXX will not strech the clock signal (SCL)

since memory read acceses occur fast enough.

1st Bit

6.2.3

ABORTING A TRANSMISSION

SDA

If any part of the I²C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a START or STOP condition. This is

done so that noisy transmissions (usually an extra

START or STOP condition) are aborted before they

corrupt the device.

SCL

Sr = Repeated Start

FIGURE 6-5:

Repeat Start Condition

Waveform.

SDA

SCL

S

1st Bit 2nd Bit 3rd Bit 4th Bit 5th Bit 6th Bit 7th Bit 8th Bit A / A

P

2

FIGURE 6-7:

Typical 8-Bit I C Waveform Format.

SDA

SCL

Data allowed

to change

Data or

A valid

STOP

Condition

START

Condition

2

FIGURE 6-8:

I C Data States and Bit Sequence.

DS22107A-page 49

MCP454X/456X/464X/466X

6.2.4

ADDRESSING

Slave Address

The address byte is the first byte received following the

START condition from the master device. The address

contains four (or more) fixed bits and (up to) three user

defined hardware address bits (pins A2, A1, and A0).

These 7-bits address the desired I²C device. The

A7:A4 address bits are fixed to “0101” and the device

appends the value of following three address pins (A2,

A1, A0). Address pins that are not present on the

device are pulled up (a bit value of ‘1’).

S

A6 A5 A4 A3 A2 A1 A0 R/W

A/A

“0”“1” “0”“1”

See Table 6-2

Start

bit

R/W bit

R/W = 0= write

R/W = 1= read

A bit (controlled by slave device)

A = 0= Slave Device Acknowledges byte

A = 1= Slave Device does not Acknowledge byte

Since there are up to three adress bits controlled by

hardware pins, there may be up to eight MCP4XXX

devices on the same I²C bus.

FIGURE 6-9:

Slave Address Bits in the

2

I C Control Byte.

Figure 6-9 shows the slave address byte format, which

contains the seven address bits. There is also a read/

write bit. Table 6-2 shows the fixed address for device.

TABLE 6-2:

Device

DEVICESLAVEADDRESSES

Address Comment

MCP45X1 ‘0101 11’b + A0

Supports up to 2

devices. Note 1

Hardware Address Pins

The hardware address bits (A2, A1, and A0)

correspond to the logic level on the associated address

pins. This allows up to eight devices on the bus.

MCP45X2 ‘0101 1’b + A1:A0 Supports up to 4

devices. Note 1

MCP46X1 ‘0101’b + A2:A1:A0 Supports up to 8

devices. Note 1

These pins have a weak pull-up enabled when the V_DD

< V_BOR. The weak pull-up utilizes the “smart” pull-up

technology and exhibits the same characteristics as the

High-voltage tolerant I/O structure.

MCP46X2 ‘0101 1’b + A1:A0 Supports up to 4

devices. Note 1

Note 1: A0 is used for High-Voltage commands

and the value is latched at POR.

The state of the A0 address pin is latch on POR/BOR.

This is required since High Voltage commands force

this pin (HVC/A0) to the V_IHHlevel.

6.2.5

SLOPE CONTROL

The MCP45XX/46XX implements slope control on the

SDA output.

As the device transitions from HS mode to FS mode,

the slope control parmameter will change from the HS

specification to the FS specification.

For Fast (FS) and High-Speed (HS) modes, the device

has a spike suppression and a Schmidt trigger at SDA

and SCL inputs.

DS22107A-page 50

MCP454X/456X/464X/466X

After switching to the High-Speed mode, the next

transferred byte is the I²C control byte, which specifies

6.2.6

HS MODE

The I²C specification requires that a high-speed mode

device must be ‘activated’ to operate in high-speed

(3.4 Mbit/s) mode. This is done by the Master sending

a special address byte following the START bit. This

byte is referred to as the high-speed Master Mode

Code (HSMMC).

the device to communicate with, and any number of

data bytes plus acknowledgements. The Master

Device can then either issue a Repeated Start bit to

address a different device (at High-Speed) or a Stop bit

to return to Fast/Standard bus speed. After the Stop bit,

any other Master Device (in a Multi-Master system) can

arbitrate for the I²C bus.

The MCP45XX/46XX device does not acknowledge

this byte. However, upon receiving this command, the

device switches to HS mode. The device can now com-

municate at up to 3.4 Mbit/s on SDA and SCL lines.

The device will switch out of the HS mode on the next

STOP condition.

See Figure 6-10 for illustration of HS mode command

sequence.

For more information on the HS mode, or other I²C

modes, please refer to the Phillips I²C specification.

The master code is sent as follows:

1. START condition (S)

6.2.6.1

Slope Control

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

clock modes of the interface.

2. High-Speed Master Mode Code (0000 1XXX),

The XXXbits are unique to the high-speed (HS)

mode Master.

6.2.6.2

Pulse Gobbler

3. No Acknowledge (A)

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

F/S-mode

HS-mode

P

F/S-mode

S ‘0 0 0 0 1 X X X’b

Sr ‘Slave Address’R/W

“Data”

A

A/A

HS-mode continues

Sr ‘Slave Address’

R/W A

HS Select Byte

S = Start bit

Control Byte

Command/Data Byte(s)

Control Byte

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

P = Stop bit (Stop condition terminates HS Mode)

FIGURE 6-10: HS Mode Sequence.

DS22107A-page 51

MCP454X/456X/464X/466X

6.2.7

GENERAL CALL

TABLE 6-3:

7-bit

GENERALCALLCOMMANDS

Comment

The General Call is a method that the “Master” device

can communicate with all other “Slave” devices. In a

Multi-Master application, the other Master devices are

operating in Slave mode. The General Call address

has two documented formats. These are shown in

Figure 6-11. We have added a MCP45XX/46XX format

in this figure as well.

This will allow customers to have multiple I²C Digital

Potentiometers on the bus and have them operate in a

synchronous fashion (analogous to the DAC Sync pin

functionality). If these MCP45XX/46XX 7-bit com-

mands conflict with other I²C devices on the bus, then

the customer will need two I²C busses and ensure that

the devices are on the correct bus for their desired

application functionality.

Command

(1, 2, 3)

‘100000d’b Write Next Byte (Third Byte) to Volatile

Wiper 0 Register

‘100100d’b Write Next Byte (Third Byte) to Volatile

Wiper 1 Register

‘110000d’b Write Next Byte (Third Byte) to TCON

Register

‘1000010’b Increment Wiper 0 Register

or

‘1000011’b

‘1001010’b Increment Wiper 1 Register

or

Dual Pot devices can not update both Pot0 and Pot1

from a single command. To address this, there are

General Call commands for the Wiper 0, Wiper 1, and

the TCON registers.

‘1001011’b

‘1000100’b Decrement Wiper 0 Register

or

‘1000101’b

Table 6-3 shows the General Call Commands. Three

commands are specified by the I²C specification and

are not applicable to the MCP45XX/46XX (so com-

mand is Not Acknowledged) The MCP45XX/46XX

General Call Commands are Acknowledge. Any other

command is Not Acknowledged.

‘1001100’b Decrement Wiper 1 Register

or

‘1001101’b

Note 1: Any other code is Not Acknowledged.

These codes may be used by other

devices on the I²C bus.

Note:

Only one General Call command per issue

of the General Call control byte. Any addi-

tional General Call commands are ignored

and Not Acknowledged.

2: The 7-bit command always appends a “0”

to form 8-bits. .

3: “d” is the D8 bit for the 9-bit write value.

DS22107A-page 52

MCP454X/456X/464X/466X

Second Byte

S

0

A

X

X X 0 A P

General Call Address

“7-bit Command”

Reserved 7-bit Commands (By I²C Specification - Philips # 9398 393 40011, Ver. 2.1 January 2000)

‘0000 011’b - Reset and write programmable part of slave address by hardware.

‘0000 010’b - Write programmable part of slave address by hardware.

‘0000 000’b - NOT Allowed

MCP45XX/MCP46XX 7-bit Commands

‘1000 01x’b - Increment Wiper 0 Register.

‘1001 01x’b - Increment Wiper 1 Register.

‘1000 10x’b - Decrement Wiper 0 Register.

‘1001 10x’b - Decrement Wiper 1 Register.

The Following is a Microchip Extension to this General Call Format

Third Byte

Second Byte

S

0

A

X

d

0

A d

d

A

P

General Call Address

MCP45XX/MCP46XX 7-bit Commands

“7-bit Command”

“0” for General Call Command

‘1000 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 0 Register.

‘1001 00d’b - Write Next Byte (Third Byte) to Volatile Wiper 1 Register.

‘1100 00d’b - Write Next Byte (Third Byte) to TCON Register.

The Following is a “Hardware General Call” Format

n occurrences of (Data + A)

A X X X X X X X X A P

Second Byte

S

0

A

X

1

General Call Address

“7-bit Command”

This indicates a “Hardware General Call”

MCP45XX/MCP46XX will ignore this byte and

all following bytes (and A), until

a Stop bit (P) is encountered.

FIGURE 6-11:

General Call Formats.

DS22107A-page 53

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 54

MCP454X/456X/464X/466X

Normal serial commands are those where the HVC pin

is driven to V_IHor V_IL. With High-Voltage Serial Com-

mands, the HVC pin is driven to V_IHH. In each mode,

there are four possible commands.

7.0

DEVICE COMMANDS

The MCP4XXX’s I²C command formats are specified in

this section. The I²C protocol does not specify how

commands are formatted.

Additionally, there are two commands used to enable

or disable the special features (Write Protect and Wiper

Lock Technology) of the device. The commands are

special cases of the Increment and Decrement

High-Voltage Serial Command.

The MCP4XXX supports four basic commands.

Depending on the location accessed determines the

commands that are supported.

For the Volatile Wiper Registers, these commands are:

Table 7-2 shows the supported commands for each

memory location.

• Write Data

• Read Data

• Increment Data

• Decrement Data

Table 7-3 shows an overview of all the device com-

mands and their interaction with other device features.

For the Non-Volatile wiper EEPROM, general purpose

data EEPROM, and the TCON Register these com-

mands are:

7.1

Command Byte

The MCP4XXX’s Command Byte has three fields: the

Address, the Command Operation, and 2 Data bits,

see Figure 7-1. Currently only one of the data bits is

defined (D8).

• Write Data

• Read Data

These commands have formats for both a single

command or continuous commands. These commands

are shown in Table 7-1.

The device memory is accessed when the Master

sends a proper Command Byte to select the desired

operation. The memory location getting accessed is

contained in the Command Byte’s AD3:AD0 bits. The

action desired is contained in the Command Byte’s

C1:C0 bits, see Table 7-1. C1:C0 determines if the

desired memory location will be read, written,

Incremented (wiper setting +1) or Decremented (wiper

setting -1). The Increment and Decrement commands

are only valid on the volatile wiper registers, and in

High Voltage commands to enable/disable WiperLock

Technology and Software Write Protect.

Each command has two operational states. The

operational state determines if the device commands

control the special features (Write Protect and Wiper-

Lock Technology). These operational states are

referred to as:

• Normal Serial Commands

• High-Voltage Serial Commands

2

TABLE 7-1:

I C COMMANDS

Command

Operateson

Volatile/

If the Address bits and Command bits are not a valid

combination, then the MCP4XXX will generate a Not

Acknowledge pulse to indicate the invalid combination.

The I²C Master device must then force a Start Condi-

tion to reset the MCP4XXX’s ²C module.

# of Bit

Clocks ⁽¹⁾Non-Volatile

memory

Operation

Mode

Write Data

Single

29

Both

Continuous 18n + 11 Volatile Only

D9 and D8 are the most significant bits for the digital

potentiometer’s wiper setting. The 8-bit devices utilize

D8 as their MSb while the 7-bit devices utilize D7 (from

the data byte) as it’s MSb.

Read Data

Single

29

48

Both

Random

Continuous 18n + 11 Both ⁽²⁾

Increment

Single

Continuous 9n + 11 Volatile Only

20 Volatile Only

20

Volatile Only

(3)

COMMAND BYTE

Decrement Single

A

D

3

A

D

2

A

D

1

A

D

0

C

1

C

0

D

9

D

8

A

(3)

Continuous 9n + 11 Volatile Only

Note 1: “n” indicates the number of times the

command operation is to be repeated.

MSbits (Data)

MCP4XXX

Memory Address

2: This command is useful to determine if a

non-volatile memory write cycle has

completed.

Command Operation bits

00= Write Data

01= Increment

10= Decrement

11= Read Data

3: High Voltage Increment and Decrement

commands on select non-volatile memory

locations enable/disable WiperLock

Technology and the software Write

Protect feature.

FIGURE 7-1:

Command Byte Format.

DS22107A-page 55

MCP454X/456X/464X/466X

TABLE 7-2:

MEMORY MAP AND THE SUPPORTED COMMANDS

Address

Function

Data

Command Operation

Comment

(10-bits) ⁽¹⁾

Value

00h Volatile Wiper 0

Write Data

Read Data ⁽³⁾

nn nnnn nnnn

—

Increment Wiper

Decrement Wiper

Write Data

—

01h Volatile Wiper 1

nn nnnn nnnn

—

Read Data ⁽³⁾

Increment Wiper

Decrement Wiper

Write Data

—

02h Non Volatile Wiper 0

03h Non Volatile Wiper 1

nn nnnn nnnn

—

Read Data ⁽³⁾

High Voltage Increment

High Voltage Decrement

Write Data

Wiper Lock 0 Disable

Wiper Lock 0 Enable

—

nn nnnn nnnn

—

Read Data ⁽³⁾

High Voltage Increment

High Voltage Decrement

Wiper Lock 1 Disable

Wiper Lock 1 Enable

—

04h ⁽²⁾Volatile TCON Register Write Data

Read Data ⁽³⁾

nn nnnn nnnn

—

05h ⁽²⁾Status Register

06h ⁽²⁾Data EEPROM

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

07h ⁽²⁾Data EEPROM

08h ⁽²⁾Data EEPROM

09h ⁽²⁾Data EEPROM

0Ah ⁽²⁾Data EEPROM

0Bh ⁽²⁾Data EEPROM

0Ch ⁽²⁾Data EEPROM

0Dh ⁽²⁾Data EEPROM

0Eh ⁽²⁾Data EEPROM

0Fh Data EEPROM

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

Write Data

Read Data ⁽³⁾

High Voltage Increment

High Voltage Decrement

Write Protect Disable

Write Protect Enable

—

Note 1: The Data Memory is only 9-bits wide, so the MSb is ignored by the device.

2: Increment or Decrement commands are invalid for these addresses.

3: I²C read operation will read 2 bytes, of which the 10-bits of data are contained within.

DS22107A-page 56

MCP454X/456X/464X/466X

7.2

Data Byte

7.3

Error Condition

Only the Read Command and the Write Command

have Data Byte(s).

If the four address bits received (AD3:AD0) and the two

command bits received (C1:C0) are a valid combina-

tion, the MCP4XXX will Acknowledge the I²C bus.

The Write command concatenates the 8-bits of the

Data Byte with the one data bit (D8) contained in the

Command Byte to form 9-bits of data (D8:D0). The

Command Byte format supports up to 9-bits of data so

that the 8-bit resistor network can be set to Full-Scale

(100h or greater). This allows wiper connections to

Terminal A and to Terminal B. The D9 bit is currently

unused.

If the address bits and command bits are an invalid

combination, then the MCP4XXX will Not Acknowledge

the I²C bus.

Once an error condition has occurred, any following

commands are ignored until the I²C bus is reset with a

Start Condition.

7.3.1

ABORTING A TRANSMISSION

A Restart or Stop condition in the expected data bit

position will abort the current command sequence and

data will not be written to the MCP4XXX.

TABLE 7-3:

COMMANDS

Operates on

Volatile/

Non-Volatile

memory

High

Voltage

(V_IHH) on

HVC pin?

Works

when

Wiper is

“locked”?

Writes

Value in

EEPROM

Impact on

WiperLock or

Write Protect

Command Name

Write Data

Read Data

Yes ⁽¹⁾

—

Both

—

unlocked ⁽¹⁾

unchanged

No

Yes

No

Yes

Increment Wiper

—

Volatile Only

Both

—

Decrement Wiper

—

High Voltage Write Data

High Voltage Read Data

High Voltage Increment Wiper

High Voltage Decrement Wiper

Yes

—

Yes

Both

—

Volatile Only

—

(2)

Modify Write Protect or WiperLock

Technology (High Voltage) - Enable

—

Non-Volatile

Only ⁽²⁾

locked/

protected ⁽²⁾

(3)

Modify Write Protect or WiperLock

Technology (High Voltage) - Disable

—

Non-Volatile

Only ⁽³⁾

Yes

unlocked/

unprotected

Yes

(3)

Note 1: This command will only complete, if wiper is “unlocked” (WiperLock Technology is Disabled).

2: If the command is executed using address 02h or 03h, that corresponding wiper is locked or

if with address 0Fh, then Write Protect is enabled.

3: If the command is executed using with address 02h or 03h, that corresponding wiper is unlocked or

if with address 0Fh, then Write Protect is disabled.

DS22107A-page 57

MCP454X/456X/464X/466X

7.4.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

7.4

Write Data

Normal and High Voltage

A continuous write mode of operation is possible when

writing to the volatile memory registers (address 00h,

01h, and 04h). This continuous write mode allows

writes without a Stop or Restart condition or repeated

transmissions of the I²C Control Byte. Figure 7-3

shows the sequence for three continuous writes. The

writes do not need to be to the same volatile memory

address. The sequence ends with the master sending

a STOP or RESTART condition.

The Write Command can be issued to both the Volatile

and Non-Volatile memory locations. The format of the

command, see Figure 7-2, includes the I²C Control

Byte, an A bit, the MCP4XXX Command Byte, an A bit,

the MCP4XXX Data Byte, an A bit, and a Stop (or

Restart) condition. The MCP4XXX generates the A / A

bits.

A Write command to a Volatile memory location

changes that location after a properly formatted Write

Command and the A / A clock have been received.

7.4.4

CONTINUOUS WRITES TO

NON-VOLATILE MEMORY

A Write command to a Non-Volatile memory location

will only start a write cycle after a properly formatted

Write Command have been received and the Stop

condition has occurred.

If a continuous write is attempted on Non-Volatile

memory, the missing Stop condition will cause the com-

mand to be an error condition (A). A Start bit is required

to reset the command state machine.

Note:

Writes to certain memory locations will be

dependant on the state of the WiperLock

Technology bits and the Write Protect bit.

7.4.5

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage operational state. High Voltage

commands allow the device’s WiperLock Technology

and write protect features to be enabled and disabled.

7.4.1

SINGLE WRITE TO VOLATILE

MEMORY

For volatile memory locations, data is written to the

MCP4XXX after every byte transfer (during the

Acknowledge). If a Stop or Restart condition is gener-

ated during a data transfer (before the A), the data will

not be written to the MCP4XXX. After the A bit, the

master can initiate the next sequence with a Stop or

Restart condition.

The HVC pin has an internal resistor connection to the

MCP45XX/46XXs internal V_DDsignal.

Refer to Figure 7-2 for the byte write sequence.

7.4.2

SINGLE WRITE TO NON-VOLATILE

MEMORY

The sequence to write to a single non-volatile memory

location is the same as a single write to volatile memory

with the exception that the EEPROM write cycle (t_wc) is

started after a properly formatted command, including

the Stop bit, is received. After the Stop condition occurs

the serial interface may immediately be re-enabled by

initiating a Start condition.

During an EEPROM write cycle, access to volatile

memory (addresses 00h, 01h, 04h, and 05h) is allowed

when using the appropriate command sequence.

Commands that address non-volatile memory are

ignored until the EEPROM write cycle (t_wc) completes.

This allows the Host Controller to operate on the

Volatile Wiper registers, the TCON register, and to

Read the Status Register. The EEWA bit in the Status

register indicates the status of an EEPROM Write

Cycle.

Once a write command to a Non-Volatile memory

location has been received, No other commands

should be received before the Stop condition occurs.

Figure 7-2 show the waveform for a single write.

DS22107A-page 58

MCP454X/456X/464X/466X

Write bit

Device

Memory

Address

Variable

Address

Fixed

Address

Write “Data” bits

Command

AD AD AD AD

S

0

1

0

1

A2 A1 A0 0

A

0

0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A P

3

2

1

0

WRITE Command

Write Data bits

Control Byte

2

FIGURE 7-2:

I C Write Sequence.

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Write “Data” bits

Command

AD AD AD AD

S

0

1

0

1

A2 A1 A0 0

A

0

0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

3

2

1

0

WRITE Command Write Data bits

Control Byte

AD AD AD AD

0

0 x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

3

2

1

0

WRITE Command

Write Data bits

STOP bit

AD AD AD AD

0

x D8 A D7 D6 D5 D4 D3 D2 D1 D0 A

P

3

2

1

0

WRITE Command Write Data bits

Note:

Only functions when writing the volatile wiper registers (AD3:AD0 = 00h, 01h, and 04h)

or the TCON register

2

FIGURE 7-3:

I C Continuous Volatile Wiper Write.

DS22107A-page 59

MCP454X/456X/464X/466X

7.5.2

CONTINUOUS READS

7.5

Read Data

Normal and High Voltage

Continuous reads allows the devices memory to be

read quickly. Continuous reads are possible to all mem-

ory locations. If a non-volatile memory write cycle is

occurring, then Read commands may only access the

volatile memory locations.

The Read Command can be issued to both the Volatile

and Non-Volatile memory locations. The format of the

command, see Figure 7-4, includes the Start condition,

I²C Control Byte (with R/W bit set to “0”), A bit,

MCP4XXX Command Byte, A bit, followed by a

Repeated Start bit, I²C Control Byte (with R/W bit set to

“1”), and the MCP4XXX transmitting the requested

Data High Byte, and A bit, the Data Low Byte, the Mas-

ter generating the A, and Stop condition.

The I²C Control Byte requires the R/W bit equal to a

logic one (R/W = 1) to generate a read sequence. The

memory location read will be the last address

contained in a valid write MCP4XXX Command Byte or

address 00h if no write operations have occurred since

the device was reset (Power-on Reset or Brown-out

Reset).

Figure 7-6 shows the sequence for three continuous

reads.

For continuous reads, instead of transmitting a Stop

or Restart condition after the data transfer, the master

reads the next data byte. The sequence ends with the

master Not Acknowledging and then sending a Stop or

Restart.

7.5.3

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage mode. High Voltage commands allow

the device’s WiperLock Technology and write protect

features to be enabled and disabled.

During a write cycle (Write or High Voltage Write to a

Non-Volatile memory location) the Read command can

only read the Volatile memory locations. By reading the

Status Register (04h), the Host Controller can

determine when the write cycle has completed (via the

state of the EEWA bit).

The HVC pin has an internal resistor connection to the

MCP4XXXs internal V_DDsignal.

Read operations initially include the same address byte

sequence as the write sequence (shown in Figure 6-9).

This sequence is followed by another control byte

(including the Start condition and Ackowledge) with the

R/W bit equal to a logic one (R/W = 1) to indicate a

read. The MCP4XXX will then transmit the data con-

tained in the addressed register. This is followed by the

master generating an A bit in preparation for more data,

or an A bit followed by a Stop. The sequence is ended

with the master generating a Stop or Restart condition.

7.5.4

IGNORING AN I²C TRANSMISSION AND

“FALLING OFF” THE BUS

The MCP4XXX expects to receive entire, valid I²C

commands and will assume any command not defined

as a valid command is due to a bus corruption and will

enter a passive high condition on the SDA signal. All

signals will be ignored until the next valid Start

condition and Control Byte are received.

The internal address pointer is maintained. If this

address pointer is for a non-volatile memory address

and the read control byte addresses the device during

a Non-Volatile Write Cycle (t_WC) the device will respond

with an A bit.

7.5.1

SINGLE READ

Figure 7-4 show the waveforms for a single read.

For single reads the master sends a STOP or

RESTART condition after the data byte is sent from the

slave.

7.5.1.1

Random Read

Figure 7-5 shows the sequence for a Random Reads.

Refer to Figure 7-5 for the random byte read

sequence.

DS22107A-page 60

MCP454X/456X/464X/466X

Read bit

STOP bit

Variable

Address

Fixed

Address

Read Data bits

S

0

1

0

1

A2 A1 A0 1 A 0

0

0 0

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A²

Read bits

P

Control Byte

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will

abort this transfer and release the bus.

2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the

Master Device can generate a Stop or Repeated Start condition.

3: The MCP45xx/46xx retains the last “Device Memory Address” that it has received. This is the

MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or

Stop conditions.

4: The Device Memory Address pointer defaults to 00h on POR and BOR conditions.

2

FIGURE 7-4:

I C Read (Last Memory Address Accessed).

Write bit

Device

Repeated Start bit

Variable

Address

Fixed

Address

Memory

Address

Command

AD AD AD AD

S

0

1

0

1

A2 A1 A0 0

A

1

x X A Sr

3

2

1

0

READ Command

Control Byte

STOP bit

Read bit

Read Data bits

0

1

0

1

A2 A1 A0 1 A 0

0

0 0

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A²

Read bits

P

Control Byte

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will

abort this transfer and release the bus.

2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the

Master Device can generate a Stop or Repeated Start condition.

3: The MCP45XX/46XX retains the last “Device Memory Address” that it has received. This is

the MCP45XX/46XX does not “corrupt” the “Device Memory Address” after Repeated Start or

Stop conditions.

2

FIGURE 7-5:

I C Random Read.

DS22107A-page 61

MCP454X/456X/464X/466X

Read bit

Variable

Address

Fixed

Address

Read Data bits

S

0

1

0

1

A2 A1 A0 1

A

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A¹

Read bits

Control Byte

Read Data bits

0

0 0

0

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A¹

STOP bit

Read Data bits

0 D8 A¹D7 D6 D5 D4 D3 D2 D1 D0 A²

0

0 0

0

P

Note 1: Master Device is responsible for A / A signal. If a A signal occurs, the MCP45XX/46XX will

abort this transfer and release the bus.

2: The Master Device will Not Acknowledge, and the MCP45XX/46XX will release the bus so the

Master Device can generate a Stop or Repeated Start condition.

2

FIGURE 7-6:

I C Continuos Reads.

DS22107A-page 62

MCP454X/456X/464X/466X

The advantage of using an Increment Command

instead of a read-modify-write series of commands is

speed and simplicity. The wiper will transition after each

Command Acknowledge when accessing the volatile

wiper registers.

7.6

Increment Wiper

Normal and High Voltage

The Increment Command provide a quick and easy

method to modify the potentiometer’s wiper by +1 with

minimal overhead. The Increment Command will only

function on the volatile wiper setting memory locations

00h and 01h. The Increment Command to Non-Volatile

addresses will be ignored and will generate a A.

TABLE 7-4:

INCREMENT OPERATION VS.

VOLATILE WIPER VALUE

Current Wiper

Setting

Increment

Wiper (W)

Note:

Table 7-2 shows the valid addresses for

the Increment Wiper command. Other

addresses are invalid.

Command

Properties

7-bit

Pot

8-bit

Pot

Operates?

When executing an Increment Command, the volatile

wiper setting will be altered from n to n+1 for each

Increment Command received. The value will incre-

ment up to 100h max on 8-bit devices and 80h on 7-bit

devices. If multiple Increment Commands are received

after the value has reached 100h (or 80h), the value will

not be incremented further. Table 7-4 shows the

Increment Command versus the current volatile wiper

value.

3FFh

081h

3FFh Reserved

101h (Full-Scale (W = A))

No

080h

100h Full-Scale (W = A) No

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid-Scale) Yes

03Fh

001h

07Fh W = N

001

The Increment Command will most commonly be

performed on the Volatile Wiper locations until a

desired condition is met. The value in the Volatile Wiper

register would need to be read using a Read operation

in order to write the new setting to the corresponding

Non-Volatile wiper memory using a Write operation.

The MCP4XXX is responsible for generating the A bits.

000h

000h Zero Scale (W = B) Yes

7.6.1

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

The High Voltage Command (HVC) signal is multi-

plexed with Address 0 (A0) and is used to indicate that

the command, or sequence of commands, are in the

High Voltage mode. Signals > V_IHH(~8.5V) on the

HVC/A0 pin puts MCP45XX/46XX devices into High

Voltage mode. High Voltage commands allow the

device’s WiperLock Technology and write protect

features to be enabled and disabled.

Refer to Figure 7-7 for the Increment Command

sequence. The sequence is terminated by the Stop

condition. So when executing a continuous command

string, The Increment command can be followed by any

other valid command. this means that writes do not

need to be to the same volatile memory address.

Note:

The command sequence can go from an

increment to any other valid command for

the specified address. Issuing an incre-

ment or decrement to a non-volatile loca-

tion will cause an error condition (A will be

generated).

Note:

There is a required delay after the HVC pin

is driven to the V_IHHlevel to the 1st edge

of the SCL pin.

The HVC pin has an internal resistor connection to the

MCP45XX/46XXs internal V_DDsignal.

Write bit

Device

Memory

Address

Variable

Address

Fixed

Address

Command

AD AD AD AD

(2)

S

0

1

0

1

A2 A1 A0 0

A

0

1 x

X

A

0

1 x

X A P

3

2

1

0

4

3

2

1

INCR Command (n+1)

INCR Command (n+2)

Control Byte

Note 1: Increment Command (INCR) only functions when accessing the volatile wiper reg-

isters (AD3:AD0 = 0h and 1h).

2: This command sequence does not need to terminate (using the Stop bit) and can

change to any other desired command sequence (Increment, Read, or Write).

2

FIGURE 7-7:

I C Increment Command Sequence.

DS22107A-page 63

MCP454X/456X/464X/466X

The advantage of using an Decrement Command

instead of a read-modify-write series of commands is

speed and simplicity. The wiper will transition after each

Command Acknowledge when accessing the volatile

wiper registers.

7.7

Decrement Wiper

Normal and High Voltage

The Decrement Command provide a quick and easy

method to modify the potentiometer’s wiper by -1 with

minimal overhead. The Decrement Command will only

function on the volatile wiper setting memory locations

00h and 01h. Decrement Commands to Non-Volatile

addresses will be ignored and will generate an A bit.

TABLE 7-5:

DECREMENT OPERATION VS.

VOLATILE WIPER VALUE

Current Wiper

Setting

Decrement

Wiper (W)

Note:

Table 7-2 shows the valid addresses for

the Decrement Wiper command. Other

addresses are invalid.

Command

Properties

7-bit

Pot

8-bit

Pot

Operates?

When executing a Decrement Command, the volatile

wiper setting will be altered from n to n-1 for each

Decrement Command received. The value will

decrement down to 000h min. If multiple Decrement

Commands are received after the value has reached

000h, the value will not be decremented further.

Table 7-5 shows the Increment Command versus the

current volatile wiper value.

3FFh

081h

3FFh Reserved

101h (Full-Scale (W = A))

No

080h

100h Full-Scale (W = A) Yes

07Fh

041h

0FFh W = N

081

040h

080h W = N (Mid-Scale) Yes

03Fh

001h

07Fh W = N

001

The Decrement Command will most commonly be

performed on the Volatile Wiper locations until a

desired condition is met. The value in the Volatile Wiper

register would need to be read using a Read operation

in order to write the new setting to the corresponding

Non-Volatile wiper memory using a Write operation.

The MCP4XXX is responsible for generating the A bits.

000h

000h Zero Scale (W = B) No

7.7.1

THE HIGH VOLTAGE COMMAND

(HVC) SIGNAL

Refer to Figure 7-8 for the Decrement Command

sequence. The sequence is terminated by the Stop

condition. So when executing a continuous command

string, The Increment command can be followed by any

other valid command. this means that writes do not

need to be to the same volatile memory address.

The High Voltage Command (HVC) signal is

multiplexed with Address 0 (A0) and is used to indicate

that the command, or sequence of commands, are in

the High Voltage mode. Signals > V_IHH(~8.5V) on the

HVC/A0 pin puts MCP45XX/46XX devices into High

Voltage mode. High Voltage commands allow the

device’s WiperLock Technology and write protect

features to be enabled and disabled.

Note:

The command sequence can go from an

increment to any other valid command for

the specified address. Issuing an

increment or decrement to a non-volatile

location will cause an error condition (A

will be generated).

Note:

There is a required delay after the HVC pin

is driven to the V_IHHlevel to the 1st edge

of the SCL pin.

The HVC pin has an internal resistor connection to the

MCP45XX/46XXs internal V_DDsignal.

Write bit

Variable

Address

Device

Memory

Address

Fixed

Address

Command

AD AD AD AD

S

0

1

0

1

A2 A1 A0 0

A

1

0 X

X

A

1

0 X

X A

P ⁽²⁾

3

2

1

0

4

3

2

1

DECR Command (n-1)

DECR Command (n-2)

Control Byte

Note 1: Decrement Command (DECR) only functions when accessing the volatile wiper

registers (AD3:AD0 = 0h and 1h).

2: This command sequence does not need to terminate (using the Stop bit) and can

change to any other desired command sequence (INCR, Read, or Write).

2

FIGURE 7-8:

I C Decrement Command Sequence.

DS22107A-page 64

MCP454X/456X/464X/466X

7.8.1

SINGLE MODIFY (ENABLE OR

DISABLE) WRITE PROTECT OR

WIPERLOCK TECHNOLOGY (HIGH

VOLTAGE)

7.8

Modify Write Protect or WiperLock

Technology (High Voltage)

Enable and Disable

These commands are special cases of the High Volt-

age Decrement Wiper and the High Voltage Incre-

ment Wiper commands to the non-volatile memory

locations 02h, 03h, and 0Fh. This command is used to

enable or disable either the software Write Protect,

wiper 0 WiperLock Technology, or wiper 1 WiperLock

Technology. Table 7-6 shows the memory addresses,

the High Voltage command and the result of those

commands on the non-volatile WP, WL0, 0r WL1 bits.

Figure 7-9 (Disable) and Figure 7-10 (Enable) show

the formats for a single Modify Write Protect or Wiper-

Lock Technology command.

A Modify Write Protect or WiperLock Technology

Command will only start an EEPROM write cycle (t_wc

)

after a properly formatted Command has been

received and the Stop condition occurs.

During an EEPROM write cycle, only serial commands

to Volatile memory (addresses 00h, 01h, 04h, and 05h)

are accepted. All other serial commands are ignored

until the EEPROM write cycle (t_wc) completes. This

allows the Host Controller to operate on the Volatile

Wiper registers and the TCON register, and to Read

the Status Register. The EEWA bit in the Status register

indicates the status of an EEPROM Write Cycle.

TABLE 7-6:

ADDRESS MAP TO MODIFY WRITE PROTECT AND WIPERLOCK TECHNOLOGY

Command’s and Result

Memory

Address

High Voltage Decrement Wiper

High Voltage Increment Wiper

00h

01h

Wiper 0 register is incremented

Wiper 1 register is decremented

WL0 is enabled

Wiper 0 register is incremented

Wiper 1 register is incremented

WL0 is disabled

02h

03h

WL1 is enabled

WL1 is disabled

04h ⁽¹⁾

05h - 0Eh ⁽¹⁾

0Fh

TCON register not changed

Reserved

TCON register not changed

Reserved

WP is enabled

WP is disabled

Note 1: Reserved addresses: Increment or Decrement commands are invalid for these addresses.

Write bit

Device

Memory

Address

Variable

Address

Fixed

Address

Command (Increment)

AD AD AD AD

P

X A

S

0

1

0

1

A2 A1 A0 0

A

0

1 X

3

2

1

0

Disable Command

Control Byte

2

FIGURE 7-9:

I C Disable Command Sequence.

Write bit

Device

Memory

Address

Variable

Address

Fixed

Address

Command (Decrement)

AD AD AD AD

P

X A

S

0

1

0

1

A2 A1 A0 0

A

1

0

X

3

2

1

0

Enable Command

Control Byte

2

FIGURE 7-10:

I C Enable Command Sequence.

DS22107A-page 65

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 66

MCP454X/456X/464X/466X

The circuit in Figure 8-2 shows the method used on the

MCP402X Non-volatile Digital Potentiometer Evalua-

8.0

APPLICATIONS EXAMPLES

Non-volatile digital potentiometers have a multitude of

practical uses in modern electronic circuits. The most

popular uses include precision calibration of set point

thresholds, sensor trimming, LCD bias trimming, audio

attenuation, adjustable power supplies, motor control

overcurrent trip setting, adjustable gain amplifiers and

offset trimming. The MCP454X/456X/464X/466X

devices can be used to replace the common mechani-

cal trim pot in applications where the operating and

terminal voltages are within CMOS process limitations

(V_DD= 2.7V to 5.5V).

tion Board (Part Number: MCP402XEV). This method

requires that the system voltage be approximately 5V.

This ensures that when the PIC10F206 enters a

brown-out condition, there is an insufficient voltage

level on the HVC pin to change the stored value of the

wiper. The MCP402X Non-volatile Digital Potentiome-

ter Evaluation Board User’s Guide (DS51546) contains

a complete schematic.

GP0 is a general purpose I/O pin, while GP2 can either

be a general purpose I/O pin or it can output the internal

clock.

For the serial commands, configure the GP2 pin as an

input (high impedance). The output state of the GP0 pin

will determine the voltage on the HVC pin (V_ILor V_IH).

8.1

Techniques to force the HVC pin

to V_IHH

The circuit in Figure 8-1 shows a method using the

TC1240A doubling charge pump. When the SHDN pin

is high, the TC1240A is off, and the level on the HVC

pin is controlled by the PIC^®microcontrollers (MCUs)

IO2 pin.

For high-voltage serial commands, force the GP0

output pin to output a high level (V_OH) and configure the

GP2 pin to output the internal clock. This will form a

charge pump and increase the voltage on the HVC pin

(when the system voltage is approximately 5V).

When the SHDN pin is low, the TC1240A is on and the

V_OUTvoltage is 2 * V_DD. The resistor R₁allows the

HVC pin to go higher than the voltage such that the PIC

MCU’s IO2 pin “clamps” at approximately VDD.

PIC10F206

R₁

GP0

MCP4XXX

TC1240A

C+

GP2

PIC MCU

V_IN

HVC

C₂

C₁

C-

SHDN

C₁

V_OUT

IO1

FIGURE 8-2:

Digital Potentiometer Evaluation Board

(MCP402XEV) implementation to generate the

MCP4XXX Non-Volatile

MCP45XX

MCP46XX

R₁

HVC

IO2

C₂

V

voltage.

IHH

FIGURE 8-1:

generate the V

Using the TC1240A to

voltage.

IHH

DS22107A-page 67

MCP454X/456X/464X/466X

8.2

Using Shutdown

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

S

P

Figure 8-3 shows a possible application circuit where

the independent terminals could be used. Disconnect-

ing the wiper allows the transistor input to be taken to

the Bias voltage level (disconnecting A and or B may

be desired to reduce system current). Disconnecting

Terminal A modifies the transistor input by the R_BW

rheostat value to the Common B. Disconnecting

Terminal B modifies the transistor input by the R_AW

rheostat value to the Common A. The Common A and

Common B connections could be connected to V_DD

Nine bits of ‘1’

Start bit

Start

bit

Stop bit

FIGURE 8-4:

Format.

Software Reset Sequence

The 1st Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master Device. In this mode, the device is monitoring

the data bus in Receive mode and can detect the Start

bit forces an internal Reset.

and V_SS

.

Common A

The nine bits of ‘1’ are used to force a Reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP45XX/46XX is driving an A

bit on the I²C bus, or is in output mode (from a Read

command) and is driving a data bit of ‘0’ onto the I²C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP45XX/46XX holding

the bus low. By sending out nine ‘1’ bits, it is ensured

that the device will see a A bit (the Master Device does

not drive the I²C bus low to acknowledge the data sent

by the MCP45XX/46XX), which also forces the

MCP45XX/46XX to reset.

Input

A

To base

of Transistor

(or Amplifier)

W

The 2nd Start bit is sent to address the rare possibility

of an erroneous write. This could occur if the Master

Device was reset while sending a Write command to

the MCP45XX/46XX, AND then as the Master Device

returns to normal operation and issues a Start condition

while the MCP45XX/46XX is issuing an Acknowledge.

In this case, if the 2nd Start bit is not sent (and the Stop

bit was sent) the MCP45XX/46XX could initiate a write

cycle.

B

Input

Common B

Balance

Bias

Example Application Circuit

Note:

The potential for this erroneous write

ONLY occurs if the Master Device is reset

while sending a Write command to the

MCP45XX/46XX.

FIGURE 8-3:

using Terminal Disconnects.

The Stop bit terminates the current I²C bus activity. The

MCP45XX/46XX wait to detect the next Start condition.

8.3

Software Reset Sequence

This sequence does not effect any other I²C devices

which may be on the bus, as they should disregard this

as an invalid command.

Note:

This technique is documented in AN1028.

At times it may become necessary to perform a Soft-

ware Reset Sequence to ensure the MCP45XX/46XX

device is in a correct and known I²C Interface state.

This technique only resets the I²C state machine.

This is useful if the MCP45XX/46XX device powers up

in an incorrect state (due to excessive bus noise, ...), or

if the Master Device is reset during communication.

Figure 8-4 shows the communication sequence to soft-

ware reset the device.

DS22107A-page 68

MCP454X/456X/464X/466X

Figure 8-5 shows two I²C bus configurations. In many

8.4

Using the General Call Command

cases, the single I²C bus configuration will be

adequate. For applications that do not want all the

MCP45XX/46XX devices to do General Call support or

have a conflict with General Call commands, the

multiple I²C bus configuration would be used.

The use of the General Call Address Increment, Decre-

ment, or Write commands is analogous to the “Load”

feature (LDAC pin) on some DACs (such as the

MCP4921). This allows all the devices to “Update” the

output level “at the same time”.

For some applications, the ability to update the wiper

values “at the same time may be a requirement, since

they delay from writing to one wiper value and then the

next may cause application issues. A possible example

would be a “tuned” circuit that uses several MCP45XX/

46XX in rheostat configuration. As the system condition

changes (temperature, load, ...) these devices need to

be changed (incremented/decremented) to adjust for

the system change. These changes will either be in the

same direction or in opposite directions. With the

Potentiometer device the customer can either select

the PxB terminals (same direction) or the PxA

terminal(s) (opposite direction).

Single I²C Bus Configuration

Device 1

Device n

Device 3

Host

Controller

Device 4

Device 2

Multiple I²C Bus Configuration

Device 1a

Device na

Device nb

Device 3a

Host

Bus a

Figure 8-6 shows that the update of six devices takes

6*T_I2CDLYtime in “normal” operation, but only

1*T_I2CDLYtime in “General Call” operation.

Controller

Device 4a

Device 3b

Device 2a

Note:

The application system may need to

partition the I²C bus into multiple busses to

ensure that the MCP45XX/46XX General

Call commands do not conflict with the

General Call commands that the other I²C

devices may have defined. Also if only a

portion of the MCP45XX/46XX devices are

to require this synchronous operation,

then the devices that should not receive

these commands should be on the second

I²C bus.

Device 1b

Bus b

Device 4b

Device 3n

Device 2b

Device 1n

Device nn

Bus n

Device 4n

Device 2n

2

FIGURE 8-5:

Typical Application I C Bus

Configurations.

Normal Operation

INC

POT02

INC

POT03

INC

POT04

INC

POT05

INC

POT06

POT01

T_I2CDLY

General Call Operation

INC

POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06 POTs 01-06

T_I2CDLY

T_I2CDLY= Time from one I²C command completed to completing the next I²C command.

FIGURE 8-6: Example Comparison of “Normal Operation” vs. “General Call Operation” wiper

Updates.

DS22107A-page 69

MCP454X/456X/464X/466X

8.5.2

LAYOUT CONSIDERATIONS

8.5

Design Considerations

Inductively-coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP4XXX’s performance.

Careful board layout minimizes these effects and

increases the Signal-to-Noise Ratio (SNR). Multi-layer

In the design of a system with the MCP4XXX devices,

the following considerations should be taken into

account:

• Power Supply Considerations

• Layout Considerations

boards utilizing

a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon

is capable of providing. Particularly harsh environ-

ments may require shielding of critical signals.

8.5.1

POWER SUPPLY

CONSIDERATIONS

The typical application will require a bypass capacitor

in order to filter high-frequency noise, which can be

induced onto the power supply's traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-7 illustrates an

appropriate bypass strategy.

If low noise is desired, breadboards and wire-wrapped

boards are not recommended.

8.5.3

RESISTOR TEMPCO

Characterization curves of the resistor temperature

coefficient (Tempco) are shown in Figure 2-10,

Figure 2-21, Figure 2-32, and Figure 2-43.

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as

close (within 4 mm) to the device power pin (V_DD) as

possible.

These curves show that the resistor network is

designed to correct for the change in resistance as

temperature increases. This technique reduces the

end to end change is R_ABresistance.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

V_SSshould reside on the analog plane.

8.5.4

HIGH VOLTAGE TOLERANT PINS

High Voltage support (V_IHH) on the Serial Interface pins

supports user configuration of the Non-Volatile

EEPROM, Write Protect, and WiperLock feature.

V_DD

0.1 µF

Note:

In many applications, the High Voltage will

only be present at the manufacturing

stage so as to “lock” the Non-Volatile

wiper value (after calibration) and the con-

tents of the EEPROM. This ensures that

the since High Voltage is not present

under normal operating conditions, that

these values can not be modified.

V_DD

0.1 µF

A

W

SCL

SDA

B

V_SS

FIGURE 8-7:

Typical Microcontroller

Connections.

DS22107A-page 70

MCP454X/456X/464X/466X

9.0

DEVICE OPTIONS

Additional, custom devices are available. These

devices have weak pull-up resistors on the SDA and

SCL pins. This is useful for applications where the

wiper value is programmed durning manufacture and

not modified by the system during normal operation.

Please contact your local sales office for current infor-

mation and minimum volumn requirements.

9.1

Custom Options

The custom device will have a “P” (for Pull-up) after the

resistance version in the Product Identification System.

These device will not be available through Microchip’s

online Microchip Direct nor Microchip’s Sample sys-

tems.

Example part number:

MCP4641-103PE/ST

DS22107A-page 71

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 72

MCP454X/456X/464X/466X

10.2 Technical Documentation

10.0 DEVELOPMENT SUPPORT

10.1 Development Tools

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs, and Design Guides. Table 10-2

shows some of these documents.

Several development tools are available to assist in

your design and evaluation of the MCP45XX/46XX

devices. The currently available tools are shown in

Table 10-1.

These boards may be purchased directly from the

Microchip web site at www.microchip.com.

TABLE 10-1: DEVELOPMENT TOOLS

Board Name

Part #

Supported Devices

MCP42XX PICTail Plus Daughter Board ⁽²⁾

MCP42XXDM-PTPLS MCP42XX

MCP4XXX Digital Potentiometer Daughter Board ⁽¹⁾MCP4XXXDM-DB

MCP42XXX, MCP42XX, MCP46XX,

MCP4021, and MCP4011

8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board

14-pin SOIC/MSOP/DIP Evaluation Board

SOIC8EV

Any 8-pin device in DIP, SOIC,

MSOP, or TSSOP package

SOIC14EV

Any 14-pin device in DIP, SOIC, or

MSOP package

Note 1: Requires the use of a PICDEM Demo Board (see User’s Guide for details)

2: Requires the use of the PIC24 Explorer 16 Demo Board (see User’s Guide for details)

3: The desired MCP46XX device (in MSOP package) must be soldered onto the extra board.

TABLE 10-2: TECHNICAL DOCUMENTATION

Application

Title

Literature #

Note Number

AN1080

AN737

AN692

AN691

AN219

—

Understanding Digital Potentiometers Resistor Variations

Using Digital Potentiometers to Design Low Pass Adjustable Filters

Using a Digital Potentiometer to Optimize a Precision Single Supply Photo Detect

Optimizing the Digital Potentiometer in Precision Circuits

Comparing Digital Potentiometers to Mechanical Potentiometers

Digital Potentiometer Design Guide

DS01080

DS00737

DS00692

DS00691

DS00219

DS22017

DS21825

—

Signal Chain Design Guide

DS22107A-page 73

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 74

MCP454X/456X/464X/466X

11.0 PACKAGING INFORMATION

11.1 Package Marking Information

8-Lead DFN (3x3)

Example:

Part Number

Code

Part Number

Code

MCP4541-502E/MF

DACJ

DACK

DACM

DACL

DADB

DADC

DADE

DADD

MCP4542-502E/MF

MCP4542-103E/MF

MCP4542-104E/MF

MCP4542-503E/MF

MCP4562-502E/MF

MCP4562-103E/MF

MCP4562-104E/MF

MCP4562-503E/MF

DACP

DACQ

DACS

DACR

DADF

DADG

DADJ

DADH

XXXX

XYWW

NNN

DACJ

E841

256

MCP4541-103E/MF

MCP4541-104E/MF

MCP4541-503E/MF

MCP4561-502E/MF

MCP4561-103E/MF

MCP4561-104E/MF

MCP4561-503E/MF

8-Lead MSOP

Example

Part Number

Code

Part Number

Code

MCP4541-103E/MS 454113 MCP4542-103E/MS 454213

MCP4541-104E/MS 454114 MCP4542-104E/MS 454214

MCP4541-502E/MS 454152 MCP4542-502E/MS 454252

MCP4541-503E/MS 454153 MCP4542-503E/MS 454253

MCP4561-103E/MS 456113 MCP4562-103E/MS 456213

MCP4561-104E/MS 456114 MCP4562-104E/MS 456214

MCP4561-502E/MS 456152 MCP4562-502E/MS 456252

MCP4561-503E/MS 456153 MCP4562-503E/MS 456253

XXXXXX

YWWNNN

454113

841256

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

*

)

3

e

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS22107A-page 75

MCP454X/456X/464X/466X

Package Marking Information (Continued)

10-Lead DFN (3x3)

Example:

AAFA

Part Number

Code

Part Number

Code

XXXX

YYWW

NNN

MCP4642-502E/MF

MCP4642-103E/MF

MCP4642-104E/MF

MCP4642-503E/MF

AAFA

AAGA

AAJA

AAHA

MCP4662-502E/MF

MCP4662-103E/MF

MCP4662-104E/MF

MCP4662-503E/MF

AAQA

AARA

AATA

AASA

0841

256

10-Lead MSOP

Example

Part Number

Code

Part Number

Code

XXXXXX

YWWNNN

463252

841256

MCP4642-502E/UN 464252 MCP4662-502E/UN 466252

MCP4642-103E/UN 464213 MCP4662-103E/UN 466213

MCP4642-104E/UN 464214 MCP4662-104E/UN 466214

MCP4642-503E/UN 464253 MCP4662-503E/UN 466253

14-Lead TSSOP (MCP4641, MCP4661)

Example

4641502E

XXXXXXXX

YYWW

0841

256

NNN

16-Lead QFN (MCP4641, MCP4661)

Example

XXXXX

XXXXXX

YWWNNN

4641

502

E/ML^

841256

^

e3

DS22107A-page 76

MCP454X/456X/464X/466X

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ꢙꢁ !ꢃꢑꢌꢄꢇꢃꢕꢄꢇꢅ!ꢅꢉꢄꢋꢅ%ꢀꢅꢋꢕꢅꢄꢕꢏꢅꢃꢄꢖꢊꢈꢋꢌꢅꢑꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢁꢅ$ꢕꢊꢋꢅꢎꢊꢉꢇꢘꢅꢕꢐꢅꢜꢐꢕꢏꢐꢈꢇꢃꢕꢄꢇꢅꢇꢘꢉꢊꢊꢅꢄꢕꢏꢅꢌꢍꢖꢌꢌꢋꢅ6ꢁꢀ'ꢅꢑꢑꢅꢜꢌꢐꢅꢇꢃꢋꢌꢁ

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DS22107A-page 79

MCP454X/456X/464X/466X

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DS22107A-page 80

MCP454X/456X/464X/466X

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DS22107A-page 81

MCP454X/456X/464X/466X

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DS22107A-page 82

MCP454X/456X/464X/466X

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DS22107A-page 83

MCP454X/456X/464X/466X

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DS22107A-page 84

MCP454X/456X/464X/466X

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DS22107A-page 85

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 86

MCP454X/456X/464X/466X

APPENDIX A: REVISION HISTORY

Revision A (November 2008)

• Original Release of this Document.

DS22107A-page 87

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 88

MCP454X/456X/464X/466X

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

XXX

X

/XX

a)

b)

c)

d)

e)

MCP4541-502E/XX: 5 kΩ, 8LD Device

Resistance Temperature Package

Version Range

MCP4541-103E/XX: 10 kΩ, 8-LD Device

MCP4541-503E/XX: 50 kΩ, 8LD Device

MCP4541-104E/XX: 100 kΩ, 8LD Device

MCP4541T-104E/XX: T/R, 100 kΩ, 8LD Device

Device:

MCP4541:

MCP4541T:

Single Non-Volatile 7-bit Potentiometer

(Tape and Reel)

Single Non-Volatile 7-bit Rheostat

(Tape and Reel)

Single Non-Volatile 8-bit Potentiometer

(Tape and Reel)

Single Non-Volatile8-bit Rheostat

Single Non-Volatile 8-bit Rheostat

(Tape and Reel)

Dual Non-Volatile 7-bit Potentiometer

(Tape and Reel)

Dual Non-Volatile 7-bit Rheostat

(Tape and Reel)

Dual Non-Volatile 8-bit Potentiometer

(Tape and Reel)

Dual Non-Volatile8-bit Rheostat

Dual Non-Volatile 8-bit Rheostat

(Tape and Reel)

a)

b)

c)

d)

e)

MCP4542-502E/XX: 5 kΩ, 8LD Device

MCP4542-103E/XX: 10 kΩ, 8-LD Device

MCP4542-503E/XX: 50 kΩ, 8LD Device

MCP4542-104E/XX: 100 kΩ, 8LD Device

MCP4542T-104E/XX: T/R, 100 kΩ, 8LD Device

MCP4542:

MCP4542T:

a)

b)

c)

d)

e)

MCP4561-502E/XX: 5 kΩ, 8LD Device

MCP4561-103E/XX: 10 kΩ, 8-LD Device

MCP4561-503E/XX: 50 kΩ, 8LD Device

MCP4561-104E/XX: 100 kΩ, 8LD Device

MCP4561T-104E/XX: T/R, 100 kΩ, 8LD Device

MCP4561:

MCP4561T:

MCP4562:

MCP4562T:

a)

b)

c)

d)

e)

MCP4562-502E/XX: 5 kΩ, 8LD Device

MCP4562-103E/XX: 10 kΩ, 8-LD Device

MCP4562-503E/XX: 50 kΩ, 8LD Device

MCP4562-104E/XX: 100 kΩ, 8LD Device

MCP4562T-104E/XX: T/R, 100 kΩ, 8LD Device

MCP4641:

MCP4641T:

MCP4642:

MCP4642T:

a)

b)

c)

d)

e)

MCP4641-502E/XX: 5 kΩ, 8LD Device

MCP4641-103E/XX: 10 kΩ, 8-LD Device

MCP4641-503E/XX: 50 kΩ, 8LD Device

MCP4641-104E/XX: 100 kΩ, 8LD Device

MCP4641T-104E/XX: T/R, 100 kΩ, 8LD Device

MCP4661:

MCP4661T:

MCP4662:

MCP4662T:

a)

b)

c)

d)

e)

MCP4642-502E/XX: 5 kΩ, 8LD Device

MCP4642-103E/XX: 10 kΩ, 8-LD Device

MCP4642-503E/XX: 50 kΩ, 8LD Device

MCP4642-104E/XX: 100 kΩ, 8LD Device

MCP4642T-104E/XX: T/R, 100 kΩ, 8LD Device

Resistance Version:

502 = 5 kΩ

103 = 10 kΩ

503 = 50 kΩ

104 = 100 kΩ

a)

b)

c)

d)

e)

MCP4661-502E/XX: 5 kΩ, 8LD Device

MCP4661-103E/XX: 10 kΩ, 8-LD Device

MCP4661-503E/XX: 50 kΩ, 8LD Device

MCP4661-104E/XX: 100 kΩ, 8LD Device

MCP4661T-104E/XX: T/R, 100 kΩ, 8LD Device

Temperature Range:

Package:

E

=

-40°C to +125°C

a)

b)

c)

d)

e)

MCP4662-502E/XX: 5 kΩ, 8LD Device

MCP4662-103E/XX: 10 kΩ, 8-LD Device

MCP4662-503E/XX: 50 kΩ, 8LD Device

MCP4662-104E/XX: 100 kΩ, 8LD Device

MCP4662T-104E/XX: T/R, 100 kΩ, 8LD Device

MF

ML

MS

ST

=

Plastic Dual Flat No-lead (3x3 DFN), 8/10-lead

Plastic Quad Flat No-lead (QFN), 16-lead

Plastic Micro Small Outline (MSOP), 8-lead

Plastic Thin Shrink Small Outline (TSSOP), 14-lead

Plastic Micro Small Outline (MSOP), 10-lead

UN

XX

=

MF for 8/10-lead 3x3 DFN

ML for 16-lead QFN

MS for 8-lead MSOP

ST for 14-lead TSSOP

UN for 10-lead MSOP

DS22107A-page 89

MCP454X/456X/464X/466X

NOTES:

DS22107A-page 90

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,

PICSTART, rfPIC, SmartShunt and UNI/O are registered

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

FilterLab, Linear Active Thermistor, MXDEV, MXLAB,

SEEVAL, SmartSensor and The Embedded Control Solutions

Company are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, In-Circuit Serial

Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB

Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,

PICDEM.net, PICtail, PIC³²logo, PowerCal, PowerInfo,

PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total

Endurance, WiperLock and ZENA are trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC^®MCUs and dsPIC^®DSCs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS22107A-page 91

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Asia Pacific Office

Suites 3707-14, 37th Floor

Tower 6, The Gateway

Harbour City, Kowloon

Hong Kong

Tel: 852-2401-1200

Fax: 852-2401-3431

India - Bangalore

Tel: 91-80-4182-8400

Fax: 91-80-4182-8422

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

Denmark - Copenhagen

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-4160-8631

Fax: 91-11-4160-8632

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

India - Pune

Tel: 91-20-2566-1512

Fax: 91-20-2566-1513

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Japan - Yokohama

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

Korea - Daegu

Tel: 82-53-744-4301

Fax: 82-53-744-4302

Boston

China - Chengdu

Tel: 86-28-8665-5511

Fax: 86-28-8665-7889

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Korea - Seoul

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

China - Nanjing

Tel: 86-25-8473-2460

Fax: 86-25-8473-2470

Malaysia - Kuala Lumpur

Tel: 60-3-6201-9857

Fax: 60-3-6201-9859

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

UK - Wokingham

Tel: 44-118-921-5869

Fax: 44-118-921-5820

China - Qingdao

Tel: 86-532-8502-7355

Fax: 86-532-8502-7205

Malaysia - Penang

Tel: 60-4-227-8870

Fax: 60-4-227-4068

Detroit

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

Philippines - Manila

Tel: 63-2-634-9065

Fax: 63-2-634-9069

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Taiwan - Hsin Chu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

China - Wuhan

Tel: 86-27-5980-5300

Fax: 86-27-5980-5118

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Santa Clara

Santa Clara, CA

Tel: 408-961-6444

Fax: 408-961-6445

China - Xiamen

Tel: 86-592-2388138

Fax: 86-592-2388130

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

China - Xian

Tel: 86-29-8833-7252

Fax: 86-29-8833-7256

Thailand - Bangkok

Tel: 66-2-694-1351

Fax: 66-2-694-1350

China - Zhuhai

Tel: 86-756-3210040

Fax: 86-756-3210049

01/02/08

DS22107A-page 92


型号：	MCP4641T-103E/ST
厂家：	MICROCHIP
描述：	7/8-Bit Single/Dual I2C Digital POT with Non-Volatile Memory 7/8位单/双I2C数字电位器具有非易失性存储器电位器存储
文件：	总92页 (文件大小：2071K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP4641T-103E/ST [MICROCHIP]

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