MCP47CVB22-EMF_技术文档

MCP47CXBXX

8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL

Single/Dual Voltage Outputs with I²C Interface

Features

Package Types

MCP47CXBX1 (Single)

MSOP-10, DFN-10 (3x3)

• Memory Options:

- Volatile Memory: MCP47CVBXX

- Nonvolatile Memory: MCP47CMBXX

• Operating Voltage Range:

V

DD

1

2

3

10

SDA

A0

REF

OUT

9 SCL

- 2.7V to 5.5V – Full specifications

- 1.8V to 2.7V – Reduced device specifications

• Output Voltage Resolutions:

V

A1

8

V

7

4

SS

-

8-bit: MCP47CXB0X (256 steps)

NC 5

6 LAT/HVC

- 10-bit: MCP47CXB1X (1024 steps)

- 12-bit: MCP47CXB2X (4096 steps)

• Nonvolatile Memory (MTP) Size: 32 Locations

• 1 LSb Integral Nonlinearity (INL) Specification

• DAC Voltage Reference Source Options:

- Device V_DD

QFN-16 (3x3)

A0

1

2

3

4

12

SCL

V

11 A1

10 V

REF

(1)

- External V_REFpin (buffered or unbuffered)

- Internal band gap (1.214V typical)

• Output Gain Options:

17 EP

OUT

SS

NC

9

LAT/HVC

- 1x (Unity)

- 2x (available when not using internal V_DDas

voltage source)

MCP47CXBX2 (Dual)

MSOP-10, DFN-10 (3x3)

• Power-on/Brown-out Reset (POR/BOR)

Protection

V

DD

1

2

3

10

SDA

• Power-Down Modes:

A0

- Disconnects output buffer (high-impedance)

9 SCL

- Selection of V_OUTpull-down resistors

V

REF

A1

8

(100 k or 1 k)

V

OUT0

OUT1

V

7

4

5

SS

• I²C Interface:

(2)

V

6 LAT/HVC

- Slave address options: register-defined

address with two physical address select pins

(package dependent)

QFN-16 (3x3)

- Standard (100 kbps), Fast (400 kbps) and

High-Speed (up to 3.4 Mbps) modes

• Package Types:

A0

1

2

3

4

12

SCL

- Dual: 16-lead 3 x 3 QFN, 10-lead MSOP,

10-lead 3 x 3 DFN

V

11 A1

10 V

REF0

(1)

17 EP

OUT0

SS

- Single: 16-lead 3 x 3 QFN, 10-lead MSOP,

10-lead 3 x 3 DFN

V

9

LAT0/HVC

REF1

• Extended Temperature Range: -40°C to +125°C

Note 1: Exposed pad (substrate paddle).

2: This pin’s signal can be connected to DAC0

and/or DAC1.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 1

MCP47CXBXX

When the V_REFpin is used with an external voltage

reference, the user can select between a gain of 1 or 2

and can have the reference buffer enabled or disabled.

When the gain is 2, the V_REFpin voltage should be

limited to a maximum of V_DD/2.

These devices have a two-wire I²C compatible serial

interface for Standard (100 kHz), Fast (400 kHz) or

High-Speed (1.7 MHz and 3.4 MHz) modes.

General Description

The MCP47CXBXX devices are single and dual

channel 8-bit, 10-bit and 12-bit buffered voltage output

Digital-to-Analog Converters (DAC) with volatile or

MTP memory, and an I²C serial interface.

The MTP memory can be written by the user up to

32 times for each specific register. It requires a high-

voltage level on the HVC pin, typically 7.5V, in order to

successfully program the desired memory location.

The nonvolatile memory includes power-up output

values, device Configuration registers and general

purpose memory.

Applications

• Set Point or Offset Trimming

• Sensor Calibration

The V_REFpin, the device V_DDor the internal band gap

voltage can be selected as the DAC’s reference

voltage. When V_DDis selected, V_DDis internally

connected to the DAC reference circuit.

• Low-Power Portable Instrumentation

• PC Peripherals

• Data Acquisition Systems

MCP47CMBX1 Block Diagram (Single-Channel Output)

V_DD

Memory

VOLATILE (4x16)

Power-up/Brown-out Control

V_SS

DAC0

V_REF

POWER-DOWN

GAIN

I²C Serial Interface Module

SDA

and Control Logic

SCL

(WiperLock™ Technology)

STATUS

A0

ADDR6:ADDR0

A1

NONVOLATILE (13x16)

DAC0

V_REF

V_IHH

LAT/HVC

POWER-DOWN

GAIN/I²C ADDRESS

WiperLock™

LAT0

V_DD

PD1:PD0 and

VREF1:VREF0

V_BG

Band Gap

1.214V

GAIN

VREF1:VREF0

OP AMP

PD1:PD0

V_OUT0

V_REF0

V_DD

VREF1:VREF0

DS20006089B-page 2

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

MCP47CMBX2 Block Diagram (Dual Channel Output)

V_DD

Memory

Power-up/Brown-out Control

V_SS

VOLATILE (5x16)

DAC0 and DAC1

V_REF

POWER-DOWN

GAIN

I²C Serial Interface Module

SDA

and Control Logic

SCL

(WiperLock™ Technology)

STATUS

A0

A1

ADDR6:ADDR0

NONVOLATILE (14x16)

DAC0 and DAC1

V_REF

V_IHH

LAT0/HVC

POWER-DOWN

GAIN/I²C ADDRESS

WiperLock™

LAT0

V_DD

PD1:PD0 and

VREF1:VREF0

V_BG

Band Gap

1.214V

GAIN

VREF1:VREF0

OP AMP

V_OUT0

(2)

V_REF0

V_DD

PD1:PD0

VREF1:VREF0

(1)

LAT1⁽¹⁾

LAT0

V_DD

PD1:PD0 and

VREF1:VREF0

GAIN

V_BG

VREF1:VREF0

OP AMP

V_OUT1

(2)

V_REF1

V_DD

PD1:PD0

VREF1:VREF0

Note 1: On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to

LAT1 input of DAC1.

2: On dual output devices, except those in a QFN16 package, the V_REF0pin is internally connected to

V_REF1input of DAC1.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 3

MCP47CXBXX

Family Device Features

DAC Output

POR/BOR

Setting⁽¹⁾

Device

Package Type

MCP47CVB01

MCP47CVB11

MCP47CVB21

MSOP, QFN, DFN

QFN

1

2

1

2

8

7Fh

1FFh

7FFh

7Fh

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

RAM

MTP

—

8

10

12

8

MCP47CVB02

MCP47CVB12

MCP47CVB22

MSOP, DFN

QFN

8

7Fh

10

12

8

1FFh

7FFh

7Fh

MSOP, DFN

QFN

MSOP, DFN

MSOP, QFN, DFN

QFN

MCP47CMB01

MCP47CMB11

MCP47CMB21

10

12

8

1FFh

7FFh

7Fh

8

MCP47CMB02

MCP47CMB12

MCP47CMB22

MSOP, DFN

QFN

8

7Fh

8

10

12

1FFh

7FFh

8

MSOP, DFN

QFN

8

MSOP, DFN

8

Note 1: The factory default value.

2: Each nonvolatile memory location can be written 32 times. For subsequent writes to the MTP, the device

will ignore the commands and the memory will not be modified.

3: If the product is a dual device and the package has only one LAT pin, it is associated with both DAC0 and

DAC1.

DS20006089B-page 4

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Voltage on V_DDwith respect to V_SS......................................................................................................... -0.6V to +6.5V

Voltage on all pins with respect to V_SS............................................................................................. -0.6V to V_DD+ 0.3V

Input clamp current, I_IK(V_I< 0, V_I> V_DD, V_I> V_PPon HV pins) ..........................................................................±20 mA

Output clamp current, I_OK(V_O< 0 or V_O> V_DD)...................................................................................................±20 mA

Maximum current out of V_SSpin

(Single)..........................................................................................................50 mA

(Dual)...........................................................................................................100 mA

Maximum current into V_DDpin

(Single)..........................................................................................................50 mA

(Dual)...........................................................................................................100 mA

Maximum current sourced by the V_OUTpin ............................................................................................................20 mA

Maximum current sunk by the V_OUTpin..................................................................................................................20 mA

Maximum current source/sunk by the V_REF(0)pin (in Band Gap mode) .................................................................20 mA

Maximum current sunk by the V_REFxpin (when V_REFis in Unbuffered mode) ......................................................175 µA

Maximum current sourced by the V_REFxpin ............................................................................................................20 µA

Maximum current sunk by the V_REFpin.................................................................................................................125 µA

Maximum input current source/sunk by SDA, SCL pins ..........................................................................................2 mA

Maximum output current sunk by SDA output pin ..................................................................................................25 mA

Total power dissipation⁽¹⁾.....................................................................................................................................400 mW

ESD protection on all pins ±6 kV (HBM)

±400V (MM)

±2 kV (CDM)

Latch-up (per JEDEC JESD78A) at +125°C ......................................................................................................±100 mA

Storage temperature ...............................................................................................................................-65°C to +150°C

Ambient temperature with power applied ...............................................................................................-55°C to +125°C

Soldering temperature of leads (10 seconds)....................................................................................................... +300°C

Maximum Junction Temperature (T_J).................................................................................................................... +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Note 1: Power dissipation is calculated as follows:

P_DIS= V_DDx {I_DD–  I_OH} +  {(V_DD– V_OH) x I_OH} + (V_OLx I_OL

)

 2018-2019 Microchip Technology Inc.

DS20006089B-page 5

MCP47CXBXX

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Supply Voltage

Sym.

Min.

Typ.

Max.

Units

Conditions

V_DD

2.7

1.8

—

5.5

2.7

V

DAC operation (reduced analog

specifications) and serial interface

V

_DDVoltage

V_POR

—

1.75

1.61

V

RAM retention voltage: (V_RAM) < V_POR,

V_DDvoltages greater than the V_PORlimit

ensure that the device is out of Reset

(rising) to Ensure Device

Power-on Reset

V_DDVoltage

V_BOR

V_RAM

—

RAM retention voltage: (V_RAM) < V_BOR

(falling) to Ensure Device

Brown-out Reset

V_DDRise Rate to Ensure

V_DDRR

Note 3

V/ms

Power-on Reset

Power-on Reset to

T_POR2OD

—

130

145

µs V_DDrising, V_DD> V_POR, single output

µs V_DDrising, V_DD> V_POR, dual output

Output-Driven Delay⁽²⁾

Note 2

Note 3

This parameter is ensured by characterization.

POR/BOR voltage trip point is not slope-dependent. Hysteresis implemented with time delay.

DS20006089B-page 6

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min. Typ. Max. Units

Conditions

Supply Current

I_DD

—

230

310

460

620

330

410

560

720

160

280

µA Single 100 kHz⁽²⁾Serial interface active,

VRxB:VRxA = 10⁽⁴⁾

_OUTis unloaded,

,

400 kHz

V

1.7 MHz⁽²⁾

3.4 MHz⁽²⁾

100 kHz⁽²⁾

400 kHz

V_REF= V_DD= 5.5V,

Volatile DAC register = Mid-Scale

Dual

1.7 MHz⁽²⁾

3.4 MHz⁽²⁾

Single Serial interface inactive, VRxB:VRxA = 10,

V_OUTis unloaded, V_REF= V_DD= 5.5V,

Volatile DAC register = Mid-Scale

Dual

LAT/HVC Pin

I_{DD(MTP_WR)}

—

6.40

mA

µA

—

Serial interface inactive (MTP write active),

VRxB:VRxA = 10(valid for all modes),

Write Current⁽²⁾

V_DD= 5.5V, LAT/HVC = V_IHH

,

write all ‘1’s to nonvolatile DAC0,

V_OUTpins are unloaded

PDxB:PDxA = 01⁽⁵⁾, VRxB:VRxA = 10,

V_OUTnot connected

Power-Down

Current

I_DDP

—

0.65 3.80

Note 2 This parameter is ensured by characterization.

Note 4 Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = 10.

Note 5 The PDxB:PDxA = 01, 10and 11configurations should have the same current.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 7

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Resistor Ladder

R_L

63.9

71

78.1

k

VRxB:VRxA = 10,

V_REF= V_DD

Resistance⁽⁶⁾

Resolution (# of resistors

and # of taps),

(see C.1 “Resolution”)

N

256

1024

4096

Taps

%

8-bit No missing codes

10-bit No missing codes

12-bit No missing codes

1.8V  V_DD 5.5V⁽²⁾

Nominal V_OUTMatch⁽¹⁰⁾

|V_OUT– V_OUTMEAN|/

V_OUTMEAN

—

0.016 0.300

V_OUTTempco⁽²⁾

(see C.19 “V_OUT

V_OUT/T

3

—

ppm/°C Code = Mid-Scale,

VRxB:VRxA = 00, 10and 11

Temperature Coefficient”)

V

_REFPin Input Voltage

V_REF

V_SS

—

V_DD

V

1.8V  V_DD 5.5V

Range⁽¹⁾

Note 1

Note 2

Note 6

This parameter is ensured by design.

This parameter is ensured by characterization.

Resistance is defined as the resistance between the V_REFpin (mode VRxB:VRxA = 10) to the V_SSpin.

For dual channel devices (MCP47CXBX2), this is the effective resistance of each resistor ladder. The

resistance measurement is one of the two resistor ladders measured in parallel.

Note 10

Variation of one output voltage to mean output voltage for dual devices only.

DS20006089B-page 8

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Zero-Scale Error

(Code = 000h)

E_ZS

—

0.375

LSb

8-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

(see C.5 “Zero-Scale

Error (E_ZS)”)

—

1.5

6

LSb

10-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

12-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

VRxB:VRxA = 10, G = 1,

V_REF= 0.5 X V_DD, no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRxB:VRxA = 01, G = 0, G = 1,

V_DD= 1.8V-5.5V, no load

Performance Curves”⁽²⁾

Offset Error

(see C.7 “Offset Error

(E_OS)”)

E_OS

-6

±0.4

+6

mV VRxB:VRxA = 10, Gx = 0, no load,

8-bit: Code = 4; 10-bit: Code = 16;

12-bit: Code = 64

Offset Voltage Temperature V_OSTC

Coefficient^(2,9)

—

±5

—

2.5

9

µV/°C

Full-Scale Error

(see C.4 “Full-Scale

Error (E_FS)”)

E_FS

LSb

8-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

10-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

35

12-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

VRxB:VRxA = 10, G = 1,

V_REF= 0.5 X V_DD, no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRxB:VRxA = 01, G = 0, G = 1,

V_DD= 1.8V-5.5V, no load

Performance Curves”⁽²⁾

Gain Error

E_G

-1

—

±0.1

-6

+1

—

% of

FSR

VRxB:VRxA = 10, G = 0,

Code = 252, V_REF= V_DD, no load

8-bit

10-bit

12-bit

(see C.9 “Gain Error

(E_G)”)⁽⁷⁾

% of

FSR

VRxB:VRxA = 10, G = 0,

Code = 1008, V_REF= V_DD, no load

% of

FSR

VRxB:VRxA = 10, G = 0,

Code = 4032, V_REF= V_DD, no load

Gain Error Drift^(2,9)

(see C.10 “Gain Error

Drift (EG_D)”)

G/°C

ppm/°C

Note 2

Note 7

Note 9

This parameter is ensured by characterization.

This gain error does not include the offset error.

Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to

4032.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 9

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Total Unadjusted Error^(2,9)

(see C.6 “Total

E_T

-2.5

—

0.75

LSb

8-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

Unadjusted Error (E_T)”)

-9

—

3

LSb 10-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

-35

12

LSb 12-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRxB:VRxA = 10, G = 1,

V_REF= 0.5 X V_DD, no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRxB:VRxA = 01, G = 0, G = 1,

V_DD= 1.8V-5.5V, no load

Performance Curves”⁽²⁾

Integral Nonlinearity

(see C.11 “Integral

Nonlinearity (INL)”)⁽⁹⁾

INL

-0.1

-0.25

-1

—

+0.1

+0.25

+1

8-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

LSb 10-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

LSb 12-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRxB:VRxA = 10, G = 1,

V_REF= 0.5 X V_DD, no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRxB:VRxA = 01, G = 0, G = 1,

V_DD= 1.8V-5.5V, no load

Performance Curves”⁽²⁾

Differential Nonlinearity

(see C.12 “Differential

Nonlinearity (DNL)”)⁽⁹⁾

DNL

-0.1

-0.25

-1.0

—

+0.1

+0.25

+1.0

8-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

LSb 10-bit VRxB:VRxA = 10, G = 0,

_REF= V_DD, no load

V

LSb 12-bit VRxB:VRxA = 10, G = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRxB:VRxA = 10, G = 1,

V_REF= 0.5 X V_DD, no load

Performance Curves”⁽²⁾

See Section 2.0 “Typical

VRxB:VRxA = 01, G = 0, G = 1,

V_DD= 1.8V-5.5V, no load

Performance Curves”⁽²⁾

Note 2

Note 9

This parameter is ensured by characterization.

Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to

4032.

DS20006089B-page 10

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

-3 dB Bandwidth

(see C.16 “-3 dB

Bandwidth”)

BW

—

60

35

—

kHz

V

_REF= 3.00V ± 2V, VRxB:VRxA = 10, Gx = 0

_REF= 3.50V ± 1.5V, VRxB:VRxA = 10,

Gx = 1

Output Amplifier (Op Amp)

Phase Margin⁽¹⁾

PM

—

6

58

0.15

130

320

10

—

14

—

°C

R_L= ∞

Slew Rate

SR

—

V/µs R_L= 2 k

Load Regulation

µV/mA 1 mA I  mA

µV/mA -6 mA I-1 mA

V_DD= 5.5V,

DAC code = Mid-Scale

Short-Circuit Current

I_{SC_OA}

mA

µs

Short to V_SS

Short to V_DD

R_L= 2 k

DAC code = Full Scale

DAC code = Zero Scale

6

10

Settling Time⁽⁸⁾

t_SETTLING

—

16

Internal Band Gap

Band Gap Voltage

Short-Circuit Current

V_BG

1.180 1.214

1.260

14

V

1.8V  V_DD 5.5V

Short to V_SS

I_{SC_BG}

6

10

16

mA

14

Short to V_DD

Band Gap Voltage

Temperature

Coefficient

V_BGTC

—

ppm/°C 1.8V  V_DD 5.5V

Band Gap mode,

V_REFPin Load

Regulation

I_BG

—

30

—

µV/mA 1 mA I6 mA V_DD= 5.5V

µV/mA -6 mA I-1 mA

390

Note 1

Note 8

This parameter is ensured by design.

Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-

bit device.)

 2018-2019 Microchip Technology Inc.

DS20006089B-page 11

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

External Reference (V_REF

)

Input Range⁽¹⁾

V_REF

C_REF

R_L

V_SS

—

V_DD

—

V

VRxB:VRxA = 10

(Unbuffered mode)

Input Capacitance

Input Impedance

29

pF

k

µA

dB

VRxB:VRxA = 10

(Unbuffered mode)

See

2.7V  V_DD 5.5V,

VRxB:VRxA = 10, V_REF V_DD

Resistor Ladder Resistance⁽⁶⁾

(1)

Current through V_REF

I_VREF

THD

—

172.15

Mathematically from R_VREF(min)

spec (at 5.5V)

Total Harmonic

Distortion⁽¹⁾

—

-76

—

V_REF= 2.048V ± 0.1V,

VRxB:VRxA = 10, Gx = 0,

Frequency = 1 kHz

Dynamic Performance

Major Code Transition Glitch

(see C.14 “Major Code

Transition Glitch”)

—

10

<2

—

nV-s 1 LSb change around major carry

(7FFh to 800h)

Digital Feedthrough (see C.15

“Digital Feedthrough”)

nV-s

Note 1

Note 6

This parameter is ensured by design.

Resistance is defined as the resistance between the V_REFpin (mode VRxB:VRxA = 10) to the V_SSpin.

For dual channel devices (MCP47CXBX2), this is the effective resistance of each resistor ladder. The

resistance measurement is one of the two resistor ladders measured in parallel.

DS20006089B-page 12

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Digital Inputs/Outputs (LAT0/HVC, LAT1, A0, A1)

Schmitt Trigger High Input

Threshold

V_IH

0.45 V_DD

—

V

1.8V  V_DD 5.5V (allows 2.7V digital

V_DDwith 5.5V analog V_DDor 1.8V

digital V_DDwith 3.0V analog V_DD

)

Schmitt Trigger Low Input

Threshold

V_IL

—

0.2 V_DD

—

V

Hysteresis of Schmitt

Trigger Inputs

V_HYS

0.1 V_DD

Input Leakage Current

Pin Capacitance

I_IL

-1

—

1

µA V_IN= V_DDand V_IN= V_SS

pF

C_IN, C_OUT

—

10

—

Digital Interface (SDA, SCL)

Output Low Voltage

V_OL

—

0.4

0.2 V_DD

—

V

V_DD 2.0V, I_OL= 3 mA

V_DD< 2.0V, I_OL= 1 mA

1.8V  V_DD 5.5V

Input High Voltage

(SDA and SCL pins)

V_IH

V_IL

0.7 V_DD

Input Low Voltage

(SDA and SCL pins)

—

-1

—

10

0.3 V_DD

V

1.8V  V_DD 5.5V

Input Leakage

I_L

1

µA SCL = SDA = V_SSor

SCL = SDA = V_DD

Pin Capacitance

RAM Value

C_PIN

—

pF

Value Range

N

0h

—

FFh

3FFh

FFFh

Hex

8-bit

10-bit

12-bit

8-bit

DAC Register POR/BOR

Value

See Table 4-2

10-bit

12-bit

PDCON Initial

Factory Setting

—

See Table 4-2

0.0010

Hex

Power Requirements

Power Supply Sensitivity

(C.17 “Power Supply

Sensitivity (PSS)”)

PSS

—

0.0035

%/%

8-bit Code = Mid-Scale

10-bit

12-bit

 2018-2019 Microchip Technology Inc.

DS20006089B-page 13

MCP47CXBXX

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +1.000V to V_DD, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Multi-Time Programming Memory (MTP)

MTP Programming

Voltage⁽¹⁾

V_{PG_MTP}

V_IHH

2.0

—

5.5

V

HVC = V_IHH, -20°C  T_A +125°C

LAT/HVC Pin Voltage

for MTP Programming

(high-voltage

7.25

7.5

7.75V

The LAT/HVC pin will be at one of the

(1,11),

three input levels (V_IL, V_IHor V_IHH

)

the LAT/HVC pin must supply the

commands)

required MTP programming current

(up to 6.4 mA)

Writes Cycles

Data Retention

MTP Range

—

DR_MTP

N

—

10

—

32⁽¹²⁾

—

Cycles Note 1

Years At +85°C⁽¹⁾

0h

FFh

Hex

8-bit

10-bit

12-bit

0h

3FFh

FFFh

7FFFh

0h

0000h

Hex All general purpose memory

—

Initial Factory Setting

N

See Table 4-2

—

MTP Programming

Write Cycle Time⁽¹⁾

t_WC(MTP)

—

250

µs

V_DD= +2.0V to 5.5V,

-20°C  T_A +125°C

Note 1 This parameter is ensured by design.

Note 11 High-voltage on the LAT/HVC pin must be limited to the command + programming time. After the

programming cycle, the LAT/HVC pin voltage must be returned to 5.5V or lower.

Note 12 After 32 MTP write cycles, writes are inhibited and the 32nd write value is retained (not corrupted).

DS20006089B-page 14

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

DC Notes:

1. This parameter is ensured by design.

2. This parameter is ensured by characterization.

3. POR/BOR voltage trip point is not slope-dependent. Hysteresis implemented with time delay.

4. Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = 10.

5. The PDxB:PDxA = 01, 10and 11configurations should have the same current.

6. Resistance is defined as the resistance between the V_REFpin (mode VRxB:VRxA = 10) to the V_SSpin. For

dual channel devices (MCP47CXBX2), this is the effective resistance of each resistor ladder. The resistance

measurement is one of the two resistor ladders measured in parallel.

7. This gain error does not include the offset error.

8. Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit

device.)

9. Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.

10. Variation of one output voltage to mean output voltage for dual devices only.

11. High-voltage on the LAT/HVC pin must be limited to the command + programming time. After the programming

cycle, the LAT/HVC pin voltage must be returned to 5.5V or lower.

12. After 32 MTP write cycles, writes are inhibited and the 32nd write value is retained (not corrupted).

 2018-2019 Microchip Technology Inc.

DS20006089B-page 15

MCP47CXBXX

1.1

Timing Waveforms and Requirements

1.1.1

WIPER SETTLING TIME

± 0.5 LSb

New Value

Old Value

V_OUT

FIGURE 1-1:

V_OUTSettling Time Waveforms.

TABLE 1-1:

WIPER SETTLING TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym. Min. Typ. Max. Units

t_S16 µs

Conditions

V

_OUTSettling Time

—

12-bit Code = 400h  C00h; C00h  400h⁽²⁾

(see C.13 “Settling Time”)

Note 2

Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR.

LATCH PIN (LAT) TIMING

1.1.2

LATx

t

LAT

SCL

Wx

FIGURE 1-2:

LAT Pin Waveforms.

TABLE 1-2:

LAT PIN TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_SS= 0V, RL = 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

LATx pin pulse width

t_LAT

20

—

ns

DS20006089B-page 16

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2

1.2

I C Mode Timing Waveforms and Requirements

V_POR

V_BOR

V_DD

t_{POR2SIA = POR2OD}

t

t_BORD

V_OUTat High-Z

V_OUT

SPI Interface is Operational

Power-on and Brown-out Reset Waveforms.

FIGURE 1-3:

Stop

Start

ACK

SDA

SCL

t_PDD

t_PDE

V_OUT

FIGURE 1-4:

I²C Power-Down Command Timing.

RESET TIMING

TABLE 1-3:

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended)

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_SS= 0V, RL = 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min. Typ. Max. Units

Conditions

Power-on Reset Delay⁽¹⁾

t_POR2SIA

—

30

130

145

—

µs

Single Monitor ACK bit response to ensure

the device responds to command

Dual

Brown-out Reset Delay

t_BORD

T_PDE

µs

V_DDtransitions from V_DD(MIN) > V_POR,

V_OUTdriven to V_OUTdisabled

Power-Down Output

Enable Time Delay

—

1.5

—

PDxB:PDxA = 11, 10, or 01 00started from

the rising edge of the SCL at the end of the 8th

clock cycle, Volatile DAC register = FFFh,

V_OUT= 10 mV, V_OUTnot connected

Power-Down Output

Disable Time Delay

T_PDD

—

0.025

—

µs

PDxB:PDxA = 00 11, 10or 01started from

the rising edge of the SCL at the end of the

8th clock cycle, V_OUT= V_OUT– 10 mV,

V_OUTnot connected

Note 1 Not tested. This parameter is ensured by characterization.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 17

MCP47CXBXX

V

94

IHH

V

IH

HVC

SCL

SDA

IH

V_IH

93

91

90

92

111

V_IL

Stop

Condition

Start

Condition

Note 1: The HVC pin must be at V_IHHuntil the MTP write cycle is complete.

FIGURE 1-5:

I²C Bus Start/Stop Bits and HVC Timing Waveforms.

DS20006089B-page 18

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

TABLE 1-4:

I²C BUS START/STOP BITS AND LAT REQUIREMENTS

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40C  T_A +125C (Extended).

The operating voltage range is described in DC Characteristics.

I²C AC Characteristics

Param.

Sym.

No.

Characteristic

SCL Pin Frequency Standard mode

Min.

Max. Units

Conditions

—

90

91

92

93

94

F_SCL

0

100

400

1.7

3.4

—

kHz C_b= 400 pF, 1.8V-5.5V⁽¹⁾

kHz C_b= 400 pF, 2.7V-5.5V

MHz C_b= 400 pF, 4.5V-5.5V⁽¹⁾

MHz C_b= 100 pF, 4.5V-5.5V⁽¹⁾

Fast mode

0

High Speed 1.7

High Speed 3.4

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

0

T_SU:STAStart Condition

Setup Time

4700

600

160

4000

600

160

4000

600

160

4000

600

160

0

ns

µs

Note 1

—

(only relevant for

Repeated Start condition)

—

T_HD:STAStart Condition

Hold Time

—

(after this period, the first

clock pulse is generated)

—

T_SU:STOStop Condition

—

Setup Time

—

T_HD:STOStop Condition

Hold Time

—

T_HVCSUHVC High to Start Condition

(setup time)

—

Not tested, specification

ensured by Master

Note 1 Not tested. This parameter is ensured by characterization.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 19

MCP47CXBXX

103

102

100

101

109

SCL

90

91

106

92

107

SDA In

110

109

SDA Out

FIGURE 1-6:

I²C Bus Data Timing Waveforms.

I²C BUS REQUIREMENTS (SLAVE MODE)

TABLE 1-5:

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40C  T_A +125C (Extended).

The operating voltage range is described in DC Characteristics.

I²C AC Characteristics

Param.

Sym.

No.

Characteristic

Min.

Max. Units

Conditions

1.8V-5.5V⁽¹⁾

100

T_HIGH

Clock HighTime 100 kHz mode

400 kHz mode

4000

600

120

60

—

ns

2.7V-5.5V

1.7 MHz mode

—

4.5V-5.5V⁽¹⁾

1.8V-5.5V⁽¹⁾

2.7V-5.5V

4.5V-5.5V⁽¹⁾

3.4 MHz mode

—

101

T_LOW

Clock Low Time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

4700

1300

320

160

—

102A⁽¹⁰⁾

T_RSCLSCL Rise Time

1000

300

80

C_bis specified to be from

10 to 400 pF (100 pF

maximum for 3.4 MHz mode)

(4)

400 kHz mode 20 + 0.1C_b

1.7 MHz mode

20

160

After a Repeated Start

condition or an

Acknowledge bit

3.4 MHz mode

10

40

80

ns

After a Repeated Start

condition or an

Acknowledge bit

102B⁽¹⁰⁾

T_RSDA

SDA Rise Time 100 kHz mode

400 kHz mode

—

1000

300

160

80

ns

Cb is specified to be from

10 to 400 pF (100 pF

maximum for 3.4 MHz mode)

20 + 0.1C_b

1.7 MHz mode

20

3.4 MHz mode

10

103A⁽¹⁰⁾

T_FSCL

SCL Fall Time

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

—

20 + 0.1C_b

20

300

80

C_bis specified to be from

10 to 400 pF (100 pF

maximum for 3.4 MHz

mode)⁽⁴⁾

10

40

Note 1

Note 4

Not tested. This parameter is ensured by characterization.

Use Cb in pF for the calculations.

Note 10 Not tested. This parameter is ensured by design.

DS20006089B-page 20

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

TABLE 1-5:

I²C BUS REQUIREMENTS (SLAVE MODE) (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40C  T_A +125C (Extended).

I²C AC Characteristics

The operating voltage range is described in DC Characteristics.

Param.

Sym.

No.

Characteristic

100 kHz mode

Min.

Max. Units

Conditions

103B⁽¹⁰⁾T_FSDASDA Fall Time

—

300

ns C_bis specified to be from

10 to 400 pF (100 pF

400 kHz mode 20 + 0.1C_b300

ns

maximum for 3.4 MHz

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

100 kHz mode

400 kHz mode

1.7 MHz mode

3.4 MHz mode

20

10

0

160

80

—

ns

mode)⁽⁴⁾

ns

106

107

109

110

111

T_HD:DATData Input Hold

Time

ns 1.8V-5.5V^(1,5)

ns 2.7V-5.5V⁽⁵⁾

ns 4.5V-5.5V^(1,5)

ns Notes 1, 6

0

—

0

—

0

—

T_SU:DATData Input Setup

Time

250

100

10

—

ns Note 6

—

ns Notes 1, 6

—

ns Notes 1, 6

T_AA

Output Valid from

Clock

3450

900

310

150

—

ns Notes 1, 5, 7, 9

ns Notes 5, 7, 9

ns C_b= 400 pF^(1,9)

ns C_b= 100 pF^(1,9)

ns Time the bus must be free

—

T_BUFBus Free Time

4700

1300

N.A.

—

before a new transmission

—

ns

can start⁽¹⁾

ns

—

ns

T_SP

Input Filter Spike

Suppression (SDA

and SCL)

50

10

ns NXP Spec states N.A.⁽¹⁾

ns NXP Spec states N.A.

ns NXP Spec states N.A.⁽¹⁾

—

Note 1 Not tested. This parameter is ensured by characterization.

Note 4 Use Cb in pF for the calculations.

Note 5 A Master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does

not unintentionally create a Start or Stop condition.

Note 6 A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement, t_SU:DAT 250 ns, must then be met. This will automatically be the case if the device does not

stretch the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it

must output the next data bit to the SDA line, T_Rmax.+ t_SU:DAT= 1000 + 250 = 1250 ns (according to the

Standard mode I²C bus specification) before the SCL line is released.

Note 7 As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

Note 8 Ensured by the T_AA3.4 MHz specification test.

Note 9 The specification is not part of the I²C specification. T_AA= T_HD:DAT+ T_FSDA(or T_RSDA).

Note 10 Not tested. This parameter is ensured by design.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 21

MCP47CXBXX

Timing Notes:

1. Not tested. This parameter is ensured by characterization.

2. Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR.

3. The transition of the LAT signal, between 10 ns before the rising edge (Spec 94) and 250 ns after the rising edge

(Spec 95) of the SCL signal, is indeterminate whether the change in V_OUTis delayed or not.

4. Use C_bin pF for the calculations.

5. A Master transmitter must provide a delay to ensure that the difference between SDA and SCL fall times does

not unintentionally create a Start or Stop condition.

6. A Fast mode (400 kHz) I²C bus device can be used in a Standard mode (100 kHz) I²C bus system, but the

requirement, t_SU:DAT 250 ns, must then be met. This will automatically be the case if the device does not stretch

the Low period of the SCL signal. If such a device does stretch the Low period of the SCL signal, it must output

the next data bit to the SDA line, T_Rmax.+ t_SU:DAT= 1000 + 250 = 1250 ns (according to the Standard mode I²C

bus specification) before the SCL line is released.

7. As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region

(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.

8. Ensured by the T_AA3.4 MHz specification test.

9. The specification is not part of the I²C specification. T_AA= T_HD:DAT+ T_FSDA(or T_RSDA).

10. Not tested. This parameter is ensured by design.

DS20006089B-page 22

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym.

Min.

Typical Max. Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+125

+150

°C

Thermal Package Resistances

Thermal Resistance, 10L-MSOP

Thermal Resistance, 10L-DFN (3x3)

Thermal Resistance, 16L-QFN (3x3)

_JA

—

206

91

—

°C/W

58

 2018-2019 Microchip Technology Inc.

DS20006089B-page 23

MCP47CXBXX

NOTES:

DS20006089B-page 24

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range), and therefore, outside the warranted range.

2.1

Electrical Data

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-1:

Average Device Supply

FIGURE 2-4:

Average Device Supply

Current vs. F_SCLFrequency, Voltage and

Temperature – Active Interface,

VRxB:VRxA = 00, (V_DDMode).

Current – Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRxB:VRxA = 00

(V_DDMode).

FIGURE 2-5:

Average Device Supply

FIGURE 2-2:

Average Device Supply

Current – Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRxB:VRxA = 01

(Band Gap Mode).

Current vs. F_SCLFrequency, Voltage and

Temperature – Active Interface,

VRxB:VRxA = 01 (Band Gap Mode).

FIGURE 2-6:

Average Device Supply

FIGURE 2-3:

Average Device Supply

Current – Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRxB:VRxA = 11

(V_REFBuffered Mode).

Current vs. F_SCLFrequency, Voltage and

Temperature – Active Interface,

VRxB:VRxA = 11 (V_REFBuffered Mode).

 2018-2019 Microchip Technology Inc.

DS20006089B-page 25

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-7:

Average Device Supply

FIGURE 2-9:

Average Device Supply

Current vs. F_SCLFrequency, Voltage and

Temperature – Active Interface,

VRxB:VRxA = 10 (V_REFUnbuffered Mode).

Current – Inactive Interface (SCL = V_IHor V_IL) vs.

Voltage and Temperature, VRxB:VRxA = 10

(V_REFUnbuffered Mode).

FIGURE 2-8:

Active Current (I_DDA) (at 5.5V and

_SCL= 3.4 MHz) vs. Temperature and DAC

Average Device Supply

F

Reference Voltage Mode.

DS20006089B-page 26

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2.2

Linearity Data

2.2.1

TOTAL UNADJUSTED ERROR (TUE) – MCP47CXB2X (12-BIT), V_REF= V_DD

(VRXB:VRXA = 10), GAIN = 1x, CODE 64-4032

Note:

Unless otherwise indicated: T_A= +25°C, V_DD= 5.5V.

FIGURE 2-10:

Total Unadjusted Error

FIGURE 2-13:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 5.5V.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 5.5V.

FIGURE 2-11:

Total Unadjusted Error

FIGURE 2-14:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 2.7V.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 2.7V.

FIGURE 2-12:

Total Unadjusted Error

FIGURE 2-15:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 1.8V.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 1.8V.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 27

MCP47CXBXX

2.2.2

INTEGRAL NONLINEARITY (INL) – MCP47CXB2X (12-BIT), V_REF= V_DD(VRXB:VRXA = 10),

GAIN = 1x, CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-16:

Temperature (Single Channel – MCP47CXB21),

_DD= 5.5V.

INL Error vs. DAC Code and

FIGURE 2-19:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V.

INL Error vs. DAC Code and

V

FIGURE 2-17:

INL Error vs. DAC Code and

FIGURE 2-20:

INL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

V_DD= 2.7V.

Temperature (Code 100-4000) (Dual Channel –

MCP47CXB22), V_DD= 2.7V.

FIGURE 2-18:

INL Error vs. DAC Code and

FIGURE 2-21:

INL Error vs. DAC Code

Temperature (Single Channel – MCP47CXB21),

V_DD= 1.8V.

and Temperature (Dual Channel – MCP47CXB22),

V_DD= 1.8V.

DS20006089B-page 28

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2.2.3

Note:

DIFFERENTIAL NONLINEARITY (DNL) – MCP47CXB2X (12-BIT), V_REF= V_DD

(VRXB:VRXA = 10), GAIN = 1x, CODE 64-4032

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-22:

DNL Error vs. DAC Code

FIGURE 2-25:

DNL Error vs. DAC Code

and Temperature (Single Channel –

MCP47CXB21), V_DD= 5.5V.

and Temperature (Dual Channel –

MCP47CXB22), V_DD= 5.5V.

FIGURE 2-23:

DNL Error vs. DAC Code

FIGURE 2-26:

DNL Error vs. DAC Code

and Temperature (Single Channel –

MCP47CXB21), V_DD= 2.7V.

and Temperature (Dual Channel –

MCP47CXB22), V_DD= 2.7V.

FIGURE 2-24:

DNL Error vs. DAC Code

FIGURE 2-27:

DNL Error vs. DAC Code

and Temperature (Single Channel –

MCP47CXB21), V_DD= 1.8V.

and Temperature (Dual Channel –

MCP47CXB22), V_DD= 1.8V.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 29

MCP47CXBXX

2.2.4

TOTAL UNADJUSTED ERROR (TUE) – MCP47CXB2X (12-BIT), EXTERNAL V_REF= 0.5 V_DD

(VRXB:VRXA = 10), UNBUFFERED, CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-28:

Total Unadjusted Error

FIGURE 2-30:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21),

(V_OUT) vs. DAC Code, and Temperature (Dual

Channel – MCP47CXB22),

V_REF= 0.5 x V_DD= 2.75V, Gain = 2x.

FIGURE 2-29:

Total Unadjusted Error

FIGURE 2-31:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21),

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22),

V_REF= 0.5 x V_DD= 1.35V, Gain = 2x.

DS20006089B-page 30

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2.2.5

Note:

INTEGRAL NONLINEARITY (INL) – MCP47CXB2X (12-BIT), EXTERNAL V_REF= 0.5 V_DD

(VRXB:VRXA = 10), UNBUFFERED, CODE 64-4032

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-32:

Temperature (Single Channel – MCP47CXB21),

_REF= 0.5 x V_DD= 2.75V, Gain = 2x.

INL Error vs. DAC Code and

FIGURE 2-34:

Temperature (Dual Channel – MCP47CXB22),

V_REF= 0.5 x V_DD= 2.75V, Gain = 2x.

INL Error vs. DAC Code and

V

FIGURE 2-33:

Temperature (Single Channel – MCP47CXB21),

V_REF= 0.5 x V_DD= 1.35V, Gain = 2x.

INL Error vs. DAC Code and

FIGURE 2-35:

Temperature (Dual Channel – MCP47CXB22),

_REF= 0.5 x V_DD= 1.35V, Gain = 2x.

INL Error vs. DAC Code and

V

 2018-2019 Microchip Technology Inc.

DS20006089B-page 31

MCP47CXBXX

2.2.6

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP47CXB2X (12-BIT),

EXTERNAL V_REF= 0.5 V_DD(VRXB:VRXA = 10), UNBUFFERED, CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-36:

Temperature (Single Channel – MCP47CXB21),

_DD= 5.5V, V_REF= 0.5 x V_DD= 2.75V.

DNL Error vs. DAC Code and

FIGURE 2-38:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V, V_REF= 0.5 x V_DD= 2.75V.

DNL Error vs. DAC Code and

V

FIGURE 2-37:

DNL Error vs. DAC Code and

FIGURE 2-39:

DNL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

V_DD= 5.5V, V_REF= 0.5 x V_DD= 1.35V.

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V, V_REF= 0.5 x V_DD= 1.35V.

DS20006089B-page 32

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2.2.7

TOTAL UNADJUSTED ERROR (TUE) – MCP47CXB2X (12-BIT), V_REF= INTERNAL

BAND GAP (VRXB:VRXA = 01), CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-40:

Total Unadjusted Error

FIGURE 2-43:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 5.5V,

Gain = 1x.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 5.5V,

Gain = 1x.

FIGURE 2-41:

Total Unadjusted Error

FIGURE 2-44:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 5.5V,

Gain = 2x.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 5.5V,

Gain = 2x.

FIGURE 2-42:

Total Unadjusted Error

FIGURE 2-45:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 2.7V,

Gain = 1x.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 2.7V,

Gain = 1x.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 33

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-46:

Total Unadjusted Error

FIGURE 2-49:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 2.7V,

Gain = 2x.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 2.7V,

Gain = 2x.

FIGURE 2-47:

Total Unadjusted Error

FIGURE 2-50:

Total Unadjusted Error

(V_OUT) vs. DAC Code and Temperature (Single

Channel – MCP47CXB21), V_DD= 1.8V,

Gain = 1x.

(V_OUT) vs. DAC Code and Temperature (Dual

Channel – MCP47CXB22), V_DD= 1.8V,

Gain = 1x.

FIGURE 2-48:

Total Unadjusted Error

FIGURE 2-51:

Total Unadjusted Error

(V_OUT) vs. DAC Code, 25°C, Gain = 1x.

(V_OUT) vs. DAC Code, 25°C, Gain = 2x.

DS20006089B-page 34

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-52:

Total Unadjusted Error

(V_OUT) vs. DAC Code, +25°C, Gain = 1x and 2x.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 35

MCP47CXBXX

2.2.8

INTEGRAL NONLINEARITY ERROR (INL) – MCP47CXB2X (12-BIT), V_REF= INTERNAL

BAND GAP (VRXB:VRXA = 01), CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-53:

Temperature (Single Channel – MCP47CXB21),

_DD= 5.5V, Gain = 1x.

INL Error vs. DAC Code and

FIGURE 2-56:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V, Gain = 1x.

INL Error vs. DAC Code and

V

FIGURE 2-54:

INL Error vs. DAC Code and

FIGURE 2-57:

INL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

V_DD= 5.5V, Gain = 2x.

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V, Gain = 2x.

FIGURE 2-55:

INL Error vs. DAC Code and

FIGURE 2-58:

INL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

V_DD= 2.7V, Gain = 1x.

Temperature (Dual Channel – MCP47CXB22),

V_DD= 2.7V, Gain = 1x.

DS20006089B-page 36

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-59:

Temperature (Single Channel – MCP47CXB21),

_DD= 2.7V, Gain = 2x.

INL Error vs. DAC Code and

FIGURE 2-62:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 2.7V, Gain = 2x.

INL Error vs. DAC Code and

V

FIGURE 2-60:

Temperature (Single Channel – MCP47CXB21),

_DD= 1.8V, Gain = 1x.

INL Error vs. DAC Code and

FIGURE 2-63:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 1.8V, Gain = 1x.

INL Error vs. DAC Code and

V

FIGURE 2-61:

INL Error vs. DAC Code,

FIGURE 2-64:

INL Error vs. DAC Code,

+25°C, Gain = 1x.

+25°C, Gain = 2x.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 37

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-65:

INL Error vs. DAC Code,

+25°C, Gain = 1x and 2x.

DS20006089B-page 38

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2.2.9

Note:

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP47CXB2X (12-BIT), V_REF= INTERNAL

BAND GAP (VRXB:VRXA = 01), CODE 64-4032

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-66:

Temperature (Single Channel – MCP47CXB21),

_DD= 5.5V, Gain = 1x.

DNL Error vs. DAC Code and

FIGURE 2-69:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V, Gain = 1x.

DNL Error vs. DAC Code and

V

FIGURE 2-67:

DNL Error vs. DAC Code and

FIGURE 2-70:

DNL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

V_DD= 5.5V, Gain = 2x.

Temperature (Dual Channel – MCP47CXB22),

V_DD= 5.5V, Gain = 2x.

FIGURE 2-68:

DNL Error vs. DAC Code and

FIGURE 2-71:

DNL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

V_DD= 2.7V, Gain = 1x.

Temperature (Dual Channel – MCP47CXB22),

V_DD= 2.7V, Gain = 1x.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 39

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-72:

DNL Error vs. DAC Code and

FIGURE 2-75:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 2.7V, Gain = 2x.

DNL Error vs. DAC Code and

Temperature (Single Channel – MCP47CXB21),

_DD= 2.7V, Gain = 2x.

V

FIGURE 2-73:

Temperature (Single Channel – MCP47CXB21),

_DD= 1.8V, Gain = 1x.

DNL Error vs. DAC Code and

FIGURE 2-76:

Temperature (Dual Channel – MCP47CXB22),

V_DD= 1.8V, Gain = 1x.

DNL Error vs. DAC Code and

V

FIGURE 2-74:

DNL Error vs. DAC Code,

FIGURE 2-77:

DNL Error vs. DAC Code,

+25°C, Gain = 1x.

+25°C, Gain = 2x.

DS20006089B-page 40

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-78:

DNL Error vs. DAC Code,

+25°C, Gain = 1x and 2x.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 41

MCP47CXBXX

NOTES:

DS20006089B-page 42

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

3.0

PIN DESCRIPTIONS

Overviews of the pin functions are provided in

Section 3.1 “Positive Power Supply Input (V_DD)”

through Section 3.9 “No Connect (NC)”.

The descriptions of the pins for the single DAC output

device are listed in Table 3-1 and descriptions for the

dual DAC output device are listed in Table 3-2.

TABLE 3-1:

MSOP DFN

MCP47CXBX1 (SINGLE DAC) PIN FUNCTION TABLE

Buffer

Type

Symbol

I/O

Description

QFN

16L

10L

1

2

3

4

5

1

2

3

4

5

16

1

V_DD

A0

—

I

P

Supply Voltage Pin

I²C Slave Address Bit 0 Pin

ST

2

V_REF

V_OUT

NC

A

—

Analog Voltage Reference Input/Output Pin

Analog Buffered Analog Voltage Output Pin

3

4,5,6,7,

8,14,15

—

Not Internally Connected

6

9

LAT/HVC

I

ST

DAC Wiper Register Latch/High-Voltage Command Pin.

The Latch pin allows the value in the Volatile DAC registers

(Wiper and Configuration bits) to be transferred to the DAC

output (V_OUT).

High-voltage commands allow the user MTP Configuration

bits to be written.

7

8

7

8

10

11

12

13

17

V_SS

A1

—

I

P

Ground Reference Pin for all circuitries on the device

I²C Slave Address Bit 1 Pin

I²C Serial Clock Pin

ST

P

9

SCL

SDA

EP

I

10

—

10

—

I/O

—

I²C Serial Data Pin

Exposed Thermal Pad Pin, must be connected to V_SS

Note 1: A = Analog, I = Input, ST = Schmitt Trigger, O = Output, I/O = Input/Output, P = Power

 2018-2019 Microchip Technology Inc.

DS20006089B-page 43

MCP47CXBXX

TABLE 3-2:

MSOP DFN

MCP47CXBX2 (DUAL DAC) PIN FUNCTION TABLE

Buffer

Type

Symbol

I/O

Description

QFN

16L

10L

1

2

1

2

16

1

V_DD

A0

—

I

P

Supply Voltage Pin

I²C Slave Address Bit 0 Pin

ST

3

—

2

V_REF

V_REF0

V_REF1

V_OUT0

V_OUT1

NC

A

—

Analog Voltage Reference Input/Output Pin

—

4

—

4

Analog Voltage Reference Input/Output Pin for DAC0

Analog Voltage Reference Input/Output Pin for DAC1

Analog Buffered Analog Voltage Output 0 Pin

Analog Buffered Analog Voltage Output 1 Pin

4

3

5

—

6,7,14,

15

—

Not Internally Connected

6

—

LAT/HVC

LAT0/HVC

LAT1

I

ST

DAC Wiper Register Latch/High-Voltage Command Pin.

The Latch pin allows the value in the Volatile DAC registers

(Wiper and Configuration bits) to be transferred to the DAC

output (V_OUT).

High-voltage commands allow the user MTP Configuration

bits to be written.

—

9

ST

DAC0 Wiper Register Latch/High-Voltage Command Pin.

The Latch pin allows the value in the Volatile DAC0 registers

(Wiper and Configuration bits) to be transferred to the DAC0

output (V_OUT0).

High-voltage commands allow the user MTP Configuration

bits to be written.

8

DAC1 Wiper Register Latch Pin.

The Latch pin allows the value in the Volatile DAC1 registers

(Wiper and Configuration bits) to be transferred to the DAC1

output (V_OUT1).

7

8

7

8

10

11

12

13

V_SS

A1

—

I

P

Ground Reference Pin for all circuitries on the device

I²C Slave Address Bit 1 Pin

I²C Serial Clock Pin

ST

9

SCL

SDA

I

10

I/O

I²C Serial Data Pin

Note 1: A = Analog, I = Input, ST = Schmitt Trigger, O = Output, I/O = Input/Output, P = Power

DS20006089B-page 44

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

3.1

Positive Power Supply Input (V

)

3.4

Analog Output Voltage Pins

DD

V_DDis the positive supply voltage input pin. The input

supply voltage is relative to V_SS

(V

V

)

OUT0, OUT1

.

V_OUT0and V_OUT1are the DAC analog voltage output

pins. Each DAC output has an output amplifier. The DAC

output range is dependent on the selection of the voltage

reference source (and potential output gain selection).

These are:

The power supply at the V_DDpin should be as clean as

possible for good DAC performance. It is recom-

mended to use an appropriate bypass capacitor of

about 0.1 µF (ceramic) to ground as close as possible

to the pin. An additional 10 µF capacitor (tantalum) in

parallel is also recommended to further attenuate noise

present in application boards.

• Device V_DD– The Full-Scale Range (FSR) of the

DAC output is from V_SSto approximately V_DD

.

• V_REFpin – The Full-Scale Range of the DAC

output is from V_SSto G x V_RL, where G is the gain

selection option (1x or 2x).

3.2

Ground (V

)

SS

• Internal Band Gap – The Full-Scale Range of the

DAC output is from V_SSto G X V_BG, where G is

the gain selection option (1x or 2x).

The V_SSpin is the device ground reference.

The user must connect the V_SSpin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application PCB (Printed

Circuit Board), it is highly recommended that the V_SS

pin be tied to the analog ground path or isolated within

an analog ground plane of the circuit board.

In Normal mode, the DC impedance of the output pin is

about 1. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

1 k, 100 k or open. The power-down selection bits

settings are shown in Register 4-3 (Table 5-5).

3.3

Voltage Reference Pin (V

)

REF

3.5

Latch/High-Voltage Command Pin

(LAT/HVC)

The V_REFpin is either an input or an output. When the

DAC’s voltage reference is configured as the V_REFpin,

the pin is an input. When the DAC’s voltage reference is

configured as the internal band gap, the pin is an output.

The DAC output value update event can be controlled

and synchronized using the LAT pin, for one or both

channels, on single or different devices.

When the DAC’s voltage reference is configured as the

V_REFpin, there are two options for this voltage input:

V_REFpin voltage is buffered or unbuffered. The

buffered option is offered in cases where the external

reference voltage does not have sufficient current

capability to not drop its voltage when connected to the

internal resistor ladder circuit.

The LAT pin controls the effect of the Volatile Wiper

registers, VRxB:VRxA and PDxB:PDxA, and the Gx bits

on the DAC output. If the LAT pin is held at V_IH, the

values sent to the Volatile Wiper registers and Configu-

ration bits have no effect on the DAC outputs. After the

Volatile Wiper registers and Configuration bits have

been loaded with the desired data, once the voltage on

the pin transitions to V_IL, the values in the Volatile Wiper

registers and Configuration bits are transferred to the

DAC outputs. Pulsing LAT low during writes to the

registers could lead to unpredictable DAC output voltage

values until the next pulse is issued and should be

avoided. The pin is level-sensitive, so writing to the

Volatile Wiper registers and Configuration bits while it is

being held at V_IL, will trigger an immediate change in the

outputs.

When the DAC’s voltage reference is configured as the

device V_DD, the V_REFpin is disconnected from the

internal circuit.

When the DAC’s voltage reference is configured as the

internal band gap, the V_REFpin’s drive capability is

minimal, so the output signal should be buffered.

See Section 5.2 “Voltage Reference Selection” and

Register 4-2 for more details on the Configuration bits.

For dual output devices in MSOP and DFN packages,

the LAT pin controls both channels at the same time.

The HVC pin allows the device’s MTP memory to be

programmed for the MCP47CMBXX devices. The

programming voltage supply should provide 7.5V and

at least 6.4 mA.

Note:

The HVC pin should have voltages

greater than 5.5V present only during the

MTP programming operation. Using

voltages greater than 5.5V for an

extended time on the pin may cause

device reliability issues.

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DS20006089B-page 45

MCP47CXBXX

2

3.6

I C – Serial Clock Pin (SCL)

3.8

I C Slave Address Pins (A0,A1)

The SCL pin is the serial clock pin of the I²C interface.

The MCP47CXBXX I²C interface only acts as a Slave

and the SCL pin accepts only external serial clocks.

The input data from the Master device are shifted into

the SDA pin on the rising edges of the SCL clock and

output from the device occurs at the falling edges of the

SCL clock. The SCL pin is an open-drain N-channel

driver. Therefore, it needs an external pull-up resistor

from the V_DDline to the SCL pin. Refer to Section 6.0

“I²C Serial Interface Module” for more details on the

I²C serial interface communication.

The state of these pins will determine the device’s I²C

Slave Address bit 0 value (overriding the ADD0 bit and

the ADD1 bit in Register 4-5).

3.9

No Connect (NC)

The NC pin is not internally connected to the device.

2

3.7

I C – Serial Data Pin (SDA)

The SDA pin is the serial data pin of the I²C interface.

The SDA pin is used to write or read the DAC registers

and Configuration bits. The SDA pin is an open-drain

N-channel driver. Therefore, it needs an external

pull-up resistor from the V_DDline to the SDA pin. Except

for Start and Stop conditions, the data on the SDA pin

must be stable during the high period of the clock. The

high or low state of the SDA pin can only change when

the clock signal on the SCL pin is low. See Section 6.0

“I²C Serial Interface Module”.

DS20006089B-page 46

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MCP47CXBXX

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

4.0

GENERAL DESCRIPTION

The MCP47CXBX1 (MCP47CXB01, MCP47CXB11

and MCP47CXB21) devices are single-channel voltage

output devices.

The internal Power-on Reset (POR)/Brown-out Reset

(BOR) circuit monitors the power supply voltage (V_DD

)

during operation. This circuit ensures correct device

start-up at system power-up and power-down events.

MCP47CXBX2 (MCP47CXB02, MCP47CXB12 and

MCP47CXB22) are dual channel voltage output devices.

The device’s RAM Retention Voltage (V_RAM) is lower

than the POR/BOR Voltage Trip Point (V_POR/V_BOR).

The maximum V_POR/V_BORvoltage is less than 1.8V.

These devices are offered with 8-bit (MCP47CXB0X),

10-bit (MCP47CXB1X) and 12-bit (MCP47CXB2X)

resolutions.

The POR and BOR trip points are at the same voltage,

and the condition is determined by whether the V_DD

voltage is rising or falling (see Figure 4-1). What occurs

is different depending on whether the Reset is a POR

or BOR Reset.

The family offers two memory options: the

MCP47CVBXX devices have volatile memory, while

the MCP47CMBXX have 32-times programmable

nonvolatile memory (MTP).

All devices include an I²C serial interface and a write

latch (LAT) pin to control the update of the analog out-

put voltage value from the value written in the Volatile

DAC Output register.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

V_DD(MIN)or higher).

When V_POR/V_BOR< V_DD< 2.7V, the electrical perfor-

mance may not meet the data sheet specifications. In

this region, the device is capable of reading and writing

to its volatile memory if the proper serial command is

executed.

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal V_DD, an external V_REF

pin voltage (buffered or unbuffered) or an internal

band gap voltage source.

4.1.1

The Power-on Reset is the case where the device’s

_DDhas power applied to it from the V_SSvoltage level.

POWER-ON RESET

The DAC output is buffered with a low-power and

precision output amplifier. This output amplifier pro-

vides a rail-to-rail output with low offset voltage and

low noise. The gain (1x or 2x) of the output buffer is

software configurable.

V

As the device powers up, the V_OUTpin floats to an

unknown value. When the device’s V_DDis above the

transistor threshold voltage of the device, the output

starts to be pulled low.

The devices operate from a single supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation, and from 1.8V to 5.5V for digital operation.

The device operates between 1.8V and 2.7V, but

some device parameters are not specified.

After the V_DDis above the POR/BOR trip point

(V_BOR/V_POR), the resistor network’s wiper is loaded

with the POR value. The POR value is either mid-scale

(MCP47CVBXX) or the user’s MTP programmed value

(MCP47CMBXX).

The MCP47CMBXX devices also have user-

programmable nonvolatile configuration memory

(MTP). This allows the device’s desired POR values to

be saved or the I²C address to be changed. The

device also has general purpose MTP memory

locations for storing system-specific information

(calibration data, serial numbers, system ID informa-

tion). A high-voltage requirement for programming on

the HVC pin ensures that these device settings are not

accidentally modified during normal system operation.

Therefore, it is recommended that the MTP memory

should only be programmed at the user’s factory.

Note:

In order to have the MCP47CMBXX

devices load the values from nonvolatile

memory locations at POR, they have to be

programmed at least once by the user;

otherwise, the loaded values will be the

default ones. After MTP programming, a

POR event is required to load the written

values from the nonvolatile memory.

The main functional blocks are:

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• Resistor Ladder

• Output Buffer/V_OUTOperation

• I²C Serial Interface Module

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DS20006089B-page 47

MCP47CXBXX

Volatile memory determines the Analog Output (V_OUT

pin voltage. After the device is powered up, the user

can update the device memory.

)

The Analog Output (V_OUT) state is determined by the

state of the Volatile Configuration bits and the DAC

register. This is called a Power-on Reset (event).

When the rising V_DDvoltage crosses the V_PORtrip

point, the following occur:

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

• The default DAC POR value is latched into the

Volatile DAC register.

• The default DAC POR Configuration bit values

are latched into the Volatile Configuration bits.

• POR status bit is set (‘1’).

• The Reset Delay Timer (t_PORD) starts; when the

Reset Delay Timer (t_PORD) times out, the I²C

serial interface is operational. During this delay

time, the I²C interface will not accept commands.

• The Device Memory Address Pointer is forced to 00h.

POR starts Reset Delay Timer.

Case 1: V Ramp

DD

When timer times out, the I²C interface

Default device configuration

latched into Volatile Configuration

bits and DAC register.

can operate (if V_DD

 V_DD(MIN)).

BOR Reset,

Volatile DAC Register = 000h

Volatile VRxB:VRxA = 00

POR status bit is set (‘

1’).

Volatile Memory

Retains Data Value

Volatile Gx =

0

POR Reset

Force Active

T_POR2OD

Volatile PDxB:PDxA = 11

V_DD(MIN)

V_POR

Volatile Memory

V_BOR

becomes Corrupted

V_RAM

Device in Unknown

State

Device Normal Operation

in POR

State

Below Min. Device in Device in

Operating Power- Unknown

Voltage Down State State

Volatile Memory

Retains Data Value

Device in

Known State

POR Event

Case 2: V Step

DD

V_DD(MIN)

V_POR

Volatile Memory

becomes Corrupted

V_BOR

T_PORD2OD

V_RAM

Device in Unknown

State

Normal Operation

Below Min. Device in Device in

Operating Power-

Voltage

Unknown

Down State State

FIGURE 4-1:

Power-on Reset Operation.

DS20006089B-page 48

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MCP47CXBXX

Each memory location is up to 16 bits wide. The

memory-mapped register space is shown in Table 4-1.

4.1.2

BROWN-OUT RESET

A Brown-out Reset occurs when a device had power

applied to it and that power (voltage) drops below the

specified range.

The I²C interface depends on how this memory is read

and written. Refer to Section 6.0 “I²C Serial Interface

Module” and Section 7.0 “Device Commands” for

more details on reading and writing the device’s

memory.

When the falling V_DDvoltage crosses the V_PORtrip

point (BOR event), the following occurs:

• Serial interface is disabled.

• MTP writes are disabled.

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

• Device is forced into a power-down state

(PDxB:PDxA = 11). Analog circuitry is turned off.

The MCP47CXBXX devices have volatile memory to

directly control the operation of the DACs. There are

up to five volatile memory locations:

• Volatile DAC register is forced to 000h.

Volatile Configuration bits, VRxB:VRxA and Gx, are

forced to ‘0’.

• DAC0 and DAC1 Output Value registers

• VREF Select register

If the V_DDvoltage decreases below the V_RAMvoltage,

all volatile memory may become corrupted.

• Power-Down Configuration register

• Gain and Status register

As the voltage recovers above the V_POR/V_BORvoltage,

see Section 4.1.1 “Power-on Reset” for further details.

The volatile memory starts functioning when the

device V_DDis at (or above) the RAM retention voltage

(V_RAM). The volatile memory will be loaded with the

default device values when the V_DDrises across the

Serial commands not completed due to a brown-out

condition may cause the memory location to become

corrupted.

V_POR/V_BORvoltage trip point.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

After the device is powered-up, the user can update the

device memory. Table 4-2 shows the volatile memory

locations and their interaction due to a POR event.

4.2

Device Memory

User memory includes the following types:

• Volatile Register Memory (RAM)

• Nonvolatile Register Memory (MTP)

MTP memory is present just for the MCP47CMBXX

devices and has three groupings:

• NV DAC Output Values (loaded on POR event)

• Device Configuration Memory

• General Purpose NV Memory

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DS20006089B-page 49

MCP47CXBXX

TABLE 4-1:

MCP47CXBXX MEMORY MAP (16-BIT)

Function

00h Volatile DAC Wiper Register 0

01h Volatile DAC Wiper Register 1

02h Reserved

Y

10h Nonvolatile DAC Wiper Register 0

11h Nonvolatile DAC Wiper Register 1

12h Reserved

Y

—

— —

03h Reserved

13h Reserved

04h Reserved

14h Reserved

05h Reserved

15h Reserved

06h Reserved

16h Reserved

07h Reserved

17h Reserved

08h Volatile VREF Register

09h Volatile Power-Down Register

0Ah Volatile Gain and Status Register

0Bh Reserved

Y

18h Nonvolatile VREF Register

19h Nonvolatile Power-Down Register

1Ah NV Gain and I²C 7-Bit Slave Address

1Bh NV WiperLock™ Technology Register

1Ch General Purpose MTP

1Dh General Purpose MTP

1Eh General Purpose MTP

1Fh General Purpose MTP

Y

— —

(1)

0Ch General Purpose MTP

0Dh General Purpose MTP

0Eh General Purpose MTP

0Fh General Purpose MTP

(1)

Legend:

Volatile Memory Addresses

MTP Memory Addresses

Memory Locations Not Implemented on this Device Family

Note 1: On nonvolatile memory devices only (MCP47CMBXX).

DS20006089B-page 50

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MCP47CXBXX

4.2.2

NONVOLATILE REGISTER

MEMORY (MTP)

4.2.3

POR/BOR OPERATION WITH

WIPERLOCK TECHNOLOGY

ENABLED

This memory option is available only for the

MCP47CMBXX devices.

Regardless of the WiperLock technology state, a POR

event will load the Volatile DACx Wiper register value

with the Nonvolatile DACx Wiper register value. Refer

to Section 4.1 “Power-on Reset/Brown-out Reset

(POR/BOR)” for further information.

MTP memory starts functioning below the device’s

V_POR/V_BORtrip point, and once the V_PORevent

occurs, the Volatile Memory registers are loaded with

the corresponding MTP register memory values.

Memory addresses, 0Ch through 1Fh, are nonvolatile

memory locations. These registers contain the DAC

POR/BOR wiper values, the DAC POR/BOR Configura-

tion bits, the I²C Slave address and eight general

purpose memory addresses for storing user-defined

data as calibration constants or identification numbers.

The Nonvolatile DAC Wiper registers and Configuration

bits contain the user’s DAC Output and configuration

values for the POR event.

4.2.4

UNIMPLEMENTED LOCATIONS

Unimplemented Register Bits

4.2.4.1

When issuing read commands to a valid memory loca-

tion with unimplemented bits, the unimplemented bits

will be read as ‘0’.

4.2.4.2

Unimplemented (RESERVED)

Locations

The Nonvolatile DAC Wiper registers contain the user’s

DAC output and configuration values for the POR

event. These nonvolatile values will overwrite the

factory default values. If these MTP addresses are

unprogrammed, the factory default values define the

output state.

There are a number of unimplemented memory

locations that are reserved for future use. Normal

(voltage) commands (read or write) to any unimple-

mented memory address will result in a command

error condition (I²C NACK).

High-voltage commands to any unimplemented

Configuration bit(s) will also result in a command error

condition.

The Nonvolatile DAC registers enable the stand-alone

operation of the device (without microcontroller control)

after being programmed to the desired values.

To program nonvolatile memory locations, a high-

voltage source on the LAT/HVC pin is required. Each

register/MTP location can be programmed 32 times.

After 32 writes, a new write operation will not be

possible and the last successful value written will

remain associated with the memory location.

The device starts writing the MTP memory cells at the

completion of the serial interface command at the rising

edge of the last data bit. The high voltage should

remain present on the LAT/HVC pin until the write cycle

is complete; otherwise, the write is unsuccessful and

the location is compromised (cannot be used again and

the number of available writes decreases by one).

To recover from an aborted MTP write operation, the

following procedure must be used:

• Write again any valid value to the same address

• Force a POR condition

• Write again the desired value to the MTP location

It is recommended to keep high voltage on only during

the MTP write command and programming cycle;

otherwise, the reliability of the device could be affected.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 51

MCP47CXBXX

TABLE 4-2:

FACTORY DEFAULT POR/BOR VALUES (MTP MEMORY UNPROGRAMMED)

POR/BOR Value

Function

00h Volatile DAC0 Register

01h Volatile DAC1 Register

7Fh

1FFh 7FFh

10h Nonvolatile DAC0 Wiper

7Fh

1FFh

7FFh

(1)

Register

7Fh

11h Nonvolatile DAC1 Wiper

7Fh

7FFh

(1)

Register

(3)

02h Reserved

—

12h Reserved

—

(3)

03h Reserved

13h Reserved

(3)

04h Reserved

14h Reserved

—

(3)

05h Reserved

15h Reserved

—

(3)

06h Reserved

16h Reserved

—

(3)

07h Reserved

17h Reserved

—

(1)

08h Volatile VREF Register

0000h 0000h 0000h

18h Nonvolatile VREF Register

0000h 0000h

0000h

09h Volatile Power-Down

Register

19h Nonvolatile Power-Down

(1)

Register

2

0Ah Volatile Gain and Status

0080h 0080h 0080h

0000h 0000h 0000h

1Ah NV Gain and I C 7-Bit Slave 0060h 0060h

0060h

0000h

(4)

(1,2)

Register

Address

(3)

0Bh Reserved

1Bh NV WiperLock™

Technology Register

0000h 0000h

(1)

0Ch General Purpose MTP

0Dh General Purpose MTP

0Eh General Purpose MTP

0Fh General Purpose MTP

0000h 0000h 0000h

1Ch General Purpose MTP

1Dh General Purpose MTP

1Eh General Purpose MTP

1Fh General Purpose MTP

0000h 0000h

0000h

(1)

Legend:

Volatile Memory Address Range

Nonvolatile Memory Address Range

Not Implemented

Note 1: On nonvolatile devices only (MCP47CMBXX).

2

2: Default I C 7-bit Slave address is ‘110 0000’ (‘110 00xx’ when A1:A0 bits are determined from the A1 and A0 pins).

2

3: Reading a reserved memory location will result in the I C command to Not ACK the command byte. The device data

2

bits will output all ‘1’s. A Start condition will reset the I C interface.

4: The ‘1’ bit is the POR status bit, which is set after the POR event and cleared after address 0Ah is read.

DS20006089B-page 52

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MCP47CXBXX

4.2.5

DEVICE REGISTERS

Register 4-1 shows the format of the DAC Output Value

registers for the volatile memory locations. These

registers will be either 8 bits, 10 bits or 12 bits wide. The

values are right justified.

REGISTER 4-1:

DAC0 (00h/10h) AND DAC1 (01h/11h) OUTPUT VALUE REGISTERS

(VOLATILE/NONVOLATILE)

U-0 R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

U-0

—

U-0

—

U-0

—

12-bit

10-bit

8-bit

—

D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

—

D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

D07 D06 D05 D04 D03 D02 D01 D00

bit 0

—

bit 15

Legend:

R = Readable bit

-n = Value at POR

= 12-bit device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= 10-bit device

= 8-bit device

12-bit

10-bit

8-bit

bit 15-12 bit 15-10 bit 15-8 Unimplemented: Read as ‘0’

bit 11-0

—

D11:D00: DAC Output Value bits – 12-bit devices

FFFh = Full-scale output value

7FFh = Mid-scale output value

000h = Zero scale output value

—

bit 9-0

—

D09:D00: DAC Output Value bits – 10-bit devices

3FFh = Full-scale output value

1FFh = Mid-scale output value

000h = Zero scale output value

—

bit 7-0

D07:D00: DAC Output Value bits – 8-bit devices

FFh = Full-scale output value

7Fh = Mid-scale output value

00h = Zero scale output value

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DS20006089B-page 53

MCP47CXBXX

Register 4-2 shows the format of the Voltage Refer-

ence Control register. Each DAC has two bits to control

the source of the voltage reference of the DAC. This

register is for the volatile memory locations. The width

of this register is two times the number of DACs for the

device.

REGISTER 4-2:

VOLTAGE REFERENCE (VREF) CONTROL REGISTERS (08h/18h)

(VOLATILE/NONVOLATILE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0 R/W-n R/W-n R/W-n R/W-n

(1)

Single

Dual

—

VR0B VR0A

—

VR1B VR1A VR0B VR0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Single channel device

= Dual channel device

Single

Dual

bit 15-2 bit 15-4 Unimplemented: Read as ‘0’

bit 1-0

bit 3-0

VRxB:VRxA: DAC Voltage Reference Control bits

11= V_REFpin (buffered); V_REFbuffer enabled

10= V_REFpin (unbuffered); V_REFbuffer disabled

01= Internal band gap (1.214V typical); V_REFbuffer enabled, V_REFvoltage driven when

powered down⁽²⁾

00= V_DD(unbuffered); V_REFbuffer disabled, use this state with power-down bits for lowest current

Note 1: Unimplemented bit, read as ‘0’.

2: When the internal band gap is selected, the band gap voltage source will continue to output the voltage on

the V_REFpin in any of the Power-Down modes. To reduce the power consumption to its lowest level

(band gap disabled), after selecting the desired Power-Down mode, the voltage reference should be

changed to V_DDor the V_REFpin unbuffered (‘00’ or ‘10’), which turns off the Internal band gap circuitry.

After wake-up, the user needs to reselect the internal band gap (‘01’) for the voltage reference source.

DS20006089B-page 54

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MCP47CXBXX

Register 4-3 shows the format of the Power-Down

Control register. Each DAC has two bits to control the

power-down state of the DAC. This register is for the

volatile memory locations and the nonvolatile memory

locations. The width of this register is two times the

number of DACs for the device.

REGISTER 4-3:

POWER-DOWN CONTROL REGISTERS (09h/19h)

(VOLATILE/NONVOLATILE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

U-0 R/W-n R/W-n R/W-n R/W-n

(1)

Single

Dual

—

PD0B PD0A

—

PD1B PD1A PD0B PD0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Single channel device

= Dual channel device

Single

bit 15-2 bit 15-4 Unimplemented: Read as ‘0’

bit 1-0 bit 3-0

PDxB:PDxA: DAC Power-Down Control bits⁽²⁾

11= Powered down – V_OUTis open circuit

Dual

10= Powered down – V_OUTis loaded with a 100 k resistor to ground

01= Powered down – V_OUTis loaded with a 1 k resistor to ground

00= Normal operation (not powered down)

Note 1: Unimplemented bit, read as ‘0’.

2: See Table 5-5 for more details.

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DS20006089B-page 55

MCP47CXBXX

Register 4-4 shows the format of the Gain Control and

System Status register. Each DAC has one bit to

control the gain of the DAC and two Status bits.

REGISTER 4-4:

GAIN CONTROL AND SYSTEM STATUS REGISTER (0Ah

)

(VOLATILE)

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0 R/W-n R/W-n R/C-1

R

U-0 U-0

U-0

—

U-0

—

U-0

—

U-0

—

(1)

Single

Dual

—

G0

POR MTPMA

—

G1

—

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

C = Clearable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

= Single channel device

= Dual channel device

Single

Dual

bit 15-9 bit 15-10 Unimplemented: Read as ‘0’

—

bit 9

bit 8

bit 7

G1: DAC1 Output Driver Gain Control bit

(2)

1= 2x gain; not applicable when V_DDis used as V_RL

0= 1x gain

bit 8

bit 7

G0: DAC0 Output Driver Gain Control bit

(2)

1= 2x gain; not applicable when V_DDis used as V_RL

0= 1x gain

POR: Power-on Reset (Brown-out Reset) Status bit

This bit indicates if a POR or BOR event has occurred since the last read command of this

register. Reading this register clears the state of the POR Status bit.

1= A POR (BOR) event occurred since the last read of this register; reading this register clears

this bit

0= A POR (BOR) event has not occurred since the last read of this register

bit 6

MTPMA: MTP Memory Access Status bit⁽³⁾

This bit indicates if the MTP memory access is occurring.

1= An MTP memory access is currently occurring (during the POR MTP read cycle or an MTP

write cycle is occurring); only serial commands addressing the volatile memory are allowed

0= An MTP memory access is NOT currently occurring

bit 5-0

Unimplemented: Read as ‘0’

Note 1: Unimplemented bit, read as ‘0’.

2: The DAC’s Gain bit is ignored and the gain is forced to 1x (Gx = 0) when the DAC voltage reference is

selected as V_DD(VRxB:VRxA = 00).

3: For devices configured as volatile memory, this bit is read as ‘0’.

DS20006089B-page 56

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MCP47CXBXX

Register 4-5 shows the format of the Nonvolatile Gain

Control and Slave Address register. Each DAC has

one bit to control the gain of the DAC. I²C devices also

have seven bits that are the I²C Slave address.

REGISTER 4-5:

GAIN CONTROL AND SLAVE ADDRESS REGISTER (1Ah)

(NONVOLATILE)

U-0 U-0 U-0 U-0 U-0 U-0 R/W-n R/W-n U-0 R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

Single

Dual

—

G1

G0

—

ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

C = Clearable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

= Single-channel device

= Dual-channel device

Single

Dual

bit 15-10

bit 9-8

bit 15-10

bit 9-8

Unimplemented: Read as ‘0’

Gx: DAC Output Driver Gain Control bits⁽¹⁾

1= 2x gain

0= 1x gain

bit 7

Unimplemented: Read as ‘0’

bit 6-0

ADD6:ADD0: I²C 7-Bit Slave Address bits⁽²⁾

Note 1: When the DAC voltage reference is selected as V_DD(VRxB:VRxA = 00), the DAC’s Gain bit is ignored and

the gain is forced to 1x (Gx = 0).

2: For I²C devices that have the A1 and A0 pins, the 7-bit Slave address is ADD6:ADD2 + A1:A0. For devices

without the A1 and A0 pins, the 7-bit Slave address is ADD6:ADD0.

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DS20006089B-page 57

MCP47CXBXX

Register 4-6 shows the format of the DAC WiperLock

Technology Status register. The width of this register is

two times the number of DACs for the device.

WiperLock technology bits only control access to

volatile memory. Nonvolatile memory write access is

controlled by the requirement of high voltage on the

HVC pin, which is recommended to not be available

during normal device operation.

REGISTER 4-6:

WiperLock™ TECHNOLOGY CONTROL REGISTER (1Bh) (NONVOLATILE)

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

U-0

—

U-0 U-0 R/W-n R/W-n R/W-n R/W-n

(1)

Single

Dual

—

WL0B WL0A

—

WL1B WL1A WL0B WL0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

W = Writable bit

‘1’ = Bit is set

C = Clearable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

= Single channel device

= Dual channel device

Single

bit 15-2 bit 15-4 Unimplemented: Read as ‘0’

bit 1-0 bit 3-1

WLxB:WLxA: WiperLock™ Technology Status bits⁽²⁾

Dual

11= Volatile DAC Wiper register and Volatile DAC Configuration bits are locked

10= Volatile DAC Wiper register is locked and Volatile DAC Configuration bits are unlocked

01= Volatile DAC Wiper register is unlocked and Volatile DAC Configuration bits are locked

00= Volatile DAC Wiper register and Volatile DAC Configuration bits are unlocked

Note 1: Unimplemented bit, read as ‘0’.

2: The Volatile PDxB:PDxA bits are NOT locked due to the requirement of being able to exit Power-Down mode.

DS20006089B-page 58

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MCP47CXBXX

The functional blocks of the DAC include:

5.0

DAC CIRCUITRY

• Resistor Ladder

The Digital-to-Analog Converter circuitry converts a

digital value into its analog representation. This

description describes the functional operation of the

device.

• Voltage Reference Selection

• Output Buffer/V_OUTOperation

• Latch Pin (LAT)

• Power-Down Operation

The DAC circuit uses a resistor ladder implementation.

Devices have up to two DACs. Figure 5-1 shows the

functional block diagram for the MCP47CXBXX DAC

circuitry.

Power-Down

Operation

V_DD

PD1:PD0 and

VREF1:VREF0

Internal Band Gap

V_DD

Voltage

Reference

V_REF

VREF1:VREF0

and PD1:PD0

Selection

Band Gap

(1.214V typical)

V_DD

VREF1:VREF0

Power-Down

Operation

V

A (RL)

RL

DAC

Output

Selection

R_{S(2 )}

n

V_DD

PD1:PD0

R_S(2

n

– 1)

– 2)

V_W

R_S(2

n

V_OUT

R_S(2

n

PD1:PD0

– 3)

Gain

(1x or 2x)

R_RL

(~71 k)

Output Buffer/V_OUT

Operation

Power-Down

Operation

R_S(2)

DAC Register Value

V_W= ---------------------------------------------------------------------  V_RL

# Resistor in Resistor Ladder

R_S(1)

Where:

B

# Resistors in Resistor Ladder = 256 (MCP47CXB0X)

1024 (MCP47CXB1X)

Resistor

Ladder

4096 (MCP47CXB2X)

FIGURE 5-1:

MCP47CXBXX DAC Module Block Diagram.

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DS20006089B-page 59

MCP47CXBXX

5.1

Resistor Ladder

DAC

The resistor ladder is a digital potentiometer with the

A Terminal connected to the selected reference voltage

and the B Terminal internally grounded (see Figure 5-2).

The Volatile DAC register controls the wiper position.

The Wiper Voltage (V_W) is proportional to the DAC

register value divided by the number of Resistor

Elements (R_S) in the ladder (256, 1024 or 4096) related

to the V_RLvoltage.

Register

V_RL

R_{S(2 )}

n

(1)

R_W

2ⁿ– 1

2ⁿ– 2

R_S(2

n

– 1)

– 2)

– 3)

(1)

R_W

The output of the resistor network will drive the input of

an output buffer.

n

(1)

R_W

n

2 – 3

The resistor network is made up of three parts:

• Resistor Ladder (string of R_Selements)

• Wiper Switches

V_W

• DAC Register Decode

(1)

R_RL

R_W

2

1

The resistor ladder has a typical impedance (R_RL) of

approximately 71 k. This Resistor Ladder Resistance

(R_RL) may vary from device to device, up to ±10%.

Since this is a voltage divider configuration, the actual

R_RLresistance does not affect the output, given a fixed

R_S(2)

(1)

R_W

R_S(1)

(1)

voltage at V_RL

.

0

Equation 5-1 shows the calculation for the step

resistance.

Analog MUX

Note:

The maximum wiper position is 2ⁿ– 1,

while the number of resistors in the

resistor ladder is 2ⁿ. This means that

when the DAC register is at full scale,

there is one Resistor Element (R_S)

between the wiper and the V_RLvoltage.

Note 1:

The analog Switch Resistance (R_W)

does not affect performance due to

the voltage divider configuration.

FIGURE 5-2:

Resistor Ladder Model

Block Diagram.

If the unbuffered V_REFpin is used as the V_RLvoltage

source, the external voltage source should have a low

output impedance.

EQUATION 5-1:

R_SCALCULATION

When the DAC is powered down, the resistor ladder is

disconnected from the selected reference voltage.

R

RL

R

= --------------

8-Bit Device

S

256

R

RL

R

= -----------------

10-Bit Device

12-Bit Device

S

1024

R

RL

R

= -----------------

S

4096

DS20006089B-page 60

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MCP47CXBXX

5.2

Voltage Reference Selection

V_DD

The resistor ladder has up to four sources for the refer-

ence voltage. The selection of the voltage reference

source is specified with the Volatile VREF1:VREF0

Configuration bits (see Register 4-2). The selected

voltage source is connected to the V_RLnode (see

Figure 5-3 and Figure 5-4).

PD1:PD0 and

VREF1:VREF0

PD1:PD0 and

VREF1:VREF0

The four voltage source options for the Resistor Ladder

are:

Band Gap⁽¹⁾

(1.214V typical)

1. V_DDpin voltage.

V_REF

V_RL

2. Internal Band Gap Voltage Reference (V_BG).

3. V_REFpin voltage – unbuffered.

4. V_REFpin voltage – internally buffered.

On a POR/BOR event, the default configuration state or

the value written in the Nonvolatile register is latched into

the Volatile VREF1:VREF0 Configuration bits.

V_DD

If the V_REFpin is used with an external voltage source,

then the user must select between Buffered or

Unbuffered mode.

PD1:PD0 and

VREF1:VREF0

Note 1: The Band Gap Voltage (V_BG) is 1.214V

typical. The band gap output goes

through the buffer with a 2x gain to

create the V_RLvoltage. See Table 5-1

for additional information on the

band gap circuit.

VREF1:VREF0

V

REF

V

DD

Band Gap

V

RL

FIGURE 5-4:

Reference Voltage Selection

Implementation Block Diagram.

Buffer

FIGURE 5-3:

Voltage Selection Block Diagram.

Resistor Ladder Reference

5.2.1 USING V_DDAS V_REF

When the user selects the V_DDas reference, the V_REF

pin voltage is not connected to the resistor ladder. The

V_DDvoltage is internally connected to the resistor

ladder.

5.2.2

USING AN EXTERNAL V_REF

SOURCE IN UNBUFFERED MODE

In this case, the V_REFpin voltage may vary from V_SSto

V_DD. The voltage source should have a low output

impedance. If the voltage source has a high output

impedance, then the voltage on the V_REFpin could be

lower than expected. The resistor ladder has a typical

impedance of 71 k and a typical capacitance of 29 pF.

If a single V_REFpin is supplying multiple DACs, the

V_REFpin source must have adequate current capability

to support the number of DACs. It must be assumed

that the Resistor Ladder Resistance (R_RL) of each DAC

is at the minimum specified resistance and these

resistances are in parallel.

If the V_REFpin is tied to the V_DDvoltage, selecting

the V_DDReference mode (VREF1:VREF0 = 00) is

recommended.

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MCP47CXBXX

5.2.3

USING AN EXTERNAL V_REF

SOURCE IN BUFFERED MODE

5.3

Output Buffer/V

Operation

OUT

The output driver buffers the Wiper Voltage (V_W) of the

resistor ladder.

The V_REFpin voltage may be from 0V to V_DD. The input

buffer (amplifier) provides low offset voltage, low noise,

and a very high input impedance, with only minor

limitations on the input range and frequency response.

The DAC output is buffered with a low-power, precision

output amplifier with selectable gain. This amplifier pro-

vides a rail-to-rail output with low offset voltage and low

noise. The amplifier’s output can drive the resistive and

high-capacitive loads without oscillation. The amplifier

provides a maximum load current, which is enough for

most programmable voltage reference applications.

Refer to Section 1.0 “Electrical Characteristics” for

the specifications of the output amplifier.

Any variation or noises on the reference source can

directly affect the DAC output. The reference voltage

needs to be as clean as possible for accurate DAC

performance.

5.2.4

USING THE INTERNAL BAND GAP

AS VOLTAGE REFERENCE

Note:

The load resistance must be kept higher

than 2 k to maintain stability of the

analog output and have it meet electrical

specifications.

The internal band gap is designed to drive the resistor

ladder buffer.

If the internal band gap is selected, then the band gap

voltage source will drive the external V_REFpins. The

V_REF0pin can source up to 1 mA of current without

affecting the DAC output specifications. The V_REF1pin

must be left unloaded in this mode. The voltage refer-

ence source can be independently selected on devices

with two DAC channels, but restrictions apply:

Figure 5-5 shows a block diagram of the output driver

circuit.

V_DD

PD1:PD0

• The V_DDmode can be used without issues on any

channel.

• When the internal band gap is selected as the voltage

source, all the V_REFpins are connected to its output.

The use of the Unbuffered mode is only possible on

V_REF0, because it’s the only one that can be loaded.

• When using the Internal Band Gap mode on

Channel 0, Channel 1 must be put in Buffered

External V_REFmode or V_DDReference mode and

the V_REF1pin must be left unloaded.

V_W

V_OUT

PD1:PD0

Gain

(1x or 2x)

The resistance of the Resistor Ladder (R_RL) is targeted

to be 71 k (10%), which means a minimum

resistance of 63.9 k.

FIGURE 5-5:

Output Driver Block Diagram.

Power-down logic also controls the output buffer

operation (see Section 5.5 “Power-Down Operation”

for additional information on power-down). In any of the

three Power-Down modes, the output amplifier is

powered down and its output becomes a high-impedance

to the V_OUTpin.

The band gap selection can be used across the V_DD

voltages while maximizing the V_OUTvoltage ranges.

For V_DDvoltages below the Gain  V_BGvoltage, the

output for the upper codes will be clipped to the V_DD

voltage. Table 5-1 shows the maximum DAC register

code given device V_DDand Gain bit setting.

5.3.1

PROGRAMMABLE GAIN

TABLE 5-1:

V_OUTUSING BAND GAP

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (see Register 4-4) and the V_RL

reference selection (see Register 4-2).

(1)

Max DAC Code

Comment

12-Bit 10-Bit 8-Bit

The Gain options are:

(3)

1

FFFh 3FFh FFh

V

= 1.214V

OUT(max)

a) Gain of 1, with either the V_DDor V_REFpin used

as the reference voltage.

5.5

2

= 2.428V

= 1.214V

= 2.428V

= 1.214V

1

b) Gain of 2, only when the V_REFpin or the internal

band gap is used as the reference voltage. The

V_REFpin voltage should be limited to V_DD/2.

When the Reference Voltage Selection (V_RL) is

the device’s V_DDvoltage, the Gx bit is ignored

and a gain of 1 is used.

2.7

2

1

1.8

(2)

2

BBCh 2EFh BBh 1.8V

Note 1: Without the V

pin voltage being clipped.

OUT

2: Recommended to use the Gain = 1setting.

3: When V = 1.214V typical.

BG

DS20006089B-page 62

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MCP47CXBXX

Table 5-2 shows the gain bit operation.

TABLE 5-2: OUTPUT DRIVER GAIN

When Gain = 2 (V_RL= V_REF), if V_REF> V_DD/2, the V_OUT

voltage is limited to V_DD. So if V_REF= V_DD, the V_OUT

voltage does not change for Volatile DAC register

values mid-scale and greater, since the output amplifier

is at full-scale output.

Gain Bit

Gain

Comment

0

1

2

The following events update the DAC register value,

and therefore, the analog Voltage Output (V_OUT):

Limits V

relative to device V voltage.

pin voltages

REF

DD

• Power-on Reset

The volatile G bit value can be modified by:

• POR Event

• Brown-out Reset

• I²C write command (to Volatile registers) on the

rising edge of the last write command bit

• I²C General Call Reset command; the output is

updated with default POR data or MTP values

• I²C general call wake-up command; the output is

updated with default POR data or MTP values

• BOR Event

• I²C Write Commands

• I²C General Call Reset Command

5.3.2

OUTPUT VOLTAGE

Next, the V_OUTvoltage starts driving to the new value

after the event has occurred.

The Volatile DAC register values, along with the

device’s Configuration bits, control the analog V_OUT

voltage. The Volatile DAC register’s value is unsigned

binary. The formula for the output voltage is provided in

Equation 5-2. Examples of Volatile DAC register values

and the corresponding theoretical V_OUTvoltage for the

MCP47CXBXX devices are shown in Table 5-6.

5.3.3

STEP VOLTAGE (V_S)

The step voltage depends on the device resolution and

the calculated output voltage range. One LSb is

defined as the ideal voltage difference between two

successive codes. The step voltage can easily be cal-

culated by using Equation 5-3 (the DAC register value

is equal to ‘1’). Theoretical step voltages are shown in

Table 5-3 for several V_REFvoltages.

EQUATION 5-2:

CALCULATING OUTPUT

VOLTAGE (V_OUT

V_RL DAC Register Value

)

V_OUT= ---------------------------------------------------------------------  Gain

# Resistor in Resistor Ladder

EQUATION 5-3:

V_SCALCULATION

Where:

V_RL

# Resistors in R-Ladder = 4096 (MCP47CXB2X)

1024 (MCP47CXB1X)

V_S= ---------------------------------------------------------------------  Gain

# Resistor in Resistor Ladder

Where:

256 (MCP47CXB0X)

# Resistors in R-Ladder = 4096 (12-bit)

1024 (10-bit)

256 (8-bit)

TABLE 5-3:

THEORETICAL STEP VOLTAGE (V_S)⁽¹⁾

V_REF

1.8

Step

Voltage

5.0

2.7

1.5

1.0

1.22 mV

4.88 mV

19.5 mV

659 uV

2.64 mV

10.5 mV

439 uV

1.76 mV

7.03 mV

366 uV

1.46 mV

5.86 mV

244 uV

977 uV

3.91 mV

12-bit

10-bit

8-bit

V_S

Note 1: When Gain = 1x, V_FS= V_RLand V_ZS= 0V.

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DS20006089B-page 63

MCP47CXBXX

Driving large capacitive loads can cause stability

problems for voltage feedback output amplifiers. As the

load capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the V_OUTpin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

V_OUTpin.

5.3.4

OUTPUT SLEW RATE

Figure 5-6 shows an example of the slew rate of the V_OUT

pin. The slew rate can be affected by the characteristics

of the circuit connected to the V_OUTpin.

V_OUT(B)

V_OUT(A)

DACx = A

DACx = B

So, when driving large capacitive loads with the output

buffer, a small Series Resistor (R_ISO) at the output (see

Figure 5-7) improves the output buffer’s stability

(feedback loop’s phase margin) by making the output

load resistive at higher frequencies. The bandwidth will

be generally lower than the bandwidth with no

capacitive load.

Time

V

_OUTB– V_OUTA

Slew Rate = --------------------------------------------------

T

FIGURE 5-6:

V_OUTPin Slew Rate.

5.3.4.1

Small Capacitive Load

With a small capacitive load, the output buffer’s current

is not affected by the Capacitive Load (C_L). But still, the

V_OUTpin’s voltage is not a step transition from one out-

put value (DAC register value) to the next output value.

The change of the V_OUTvoltage is limited by the output

buffer’s characteristics, so the V_OUTpin voltage will

have a slope from the old voltage to the new voltage.

This slope is fixed for the output buffer, and is referred

to as the Buffer Slew Rate (SR_BUF).

V_OUT

V_W

R_ISO

R_L

V_CL

C_L

Gain

FIGURE 5-7:

Circuit to Stabilize Output

Buffer for Large Capacitive Loads (C_L).

5.3.4.2

Large Capacitive Load

The R_ISOresistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this R_ISOresistor

value should be verified on the bench. Modify the

R_ISO’s resistance value until the output characteristics

meet your requirements.

With a larger capacitive load, the slew rate is

determined by two factors:

• The output buffer’s Short-Circuit Current (I_SC

)

• The V_OUTpin’s external load

I_OUTcannot exceed the output buffer’s Short-Circuit

Current (I_SC), which fixes the output Buffer Slew Rate

A method to evaluate the system’s performance is to

inject a step voltage on the V_REFpin and observe the

(SR_BUF). The voltage on the Capacitive Load (C_L), V_CL

,

changes at a rate proportional to I_OUT, which fixes a

Capacitive Load Slew Rate (SR_CL).

V_OUTpin’s characteristics.

Note: Additional insight into circuit design for

The V_CLvoltage slew rate is limited to the slower of the

output buffer’s internally Set Slew Rate (SRBUF) and

the Capacitive Load Slew Rate (SR_CL).

driving capacitive loads can be found in

AN884, “Driving Capacitive Loads With

Op Amps” (DS00884).

5.3.5

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The V_OUTpin can drive up to 100 pF of capacitive load

in parallel with a 5 k resistive load (to meet electrical

specifications). V_OUTdrops slowly as the load resis-

tance decreases after about 3.5 k. It is recommended

to use a load with R_Lgreater than 2 k.

Refer to Section 2.0 “Typical Performance Curves” for

a detailed V_OUTvs. Resistive Load characterization

graph.

DS20006089B-page 64

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MCP47CXBXX

5.4

Latch Pin (LAT)

Serial Shift Reg.

The Latch pin controls when the Volatile DAC register

value is transferred to the DAC wiper. This is useful for

applications that need to synchronize the wiper(s)

updates to an external event, such as zero-crossing or

updates to the other wipers on the device. The LAT pin

is asynchronous to the serial interface operation.

Register Address

Write Command

16 Clocks

Vol. DAC Register x

Transfer

Data

LAT

SYNC

(internal signal)

When the LAT pin is high, transfers from the Volatile

DAC register to the DAC wiper are inhibited. The Volatile

DAC register value(s) can continue to be updated.

DAC Wiper x

When the LAT pin is low, the Volatile DAC register

value is transferred to the DAC wiper.

Transfer

Data

LAT SYNC

Comment

Note:

This allows both the Volatile DAC0 and

DAC1 registers to be updated while the

LAT pin is high, and to have outputs

synchronously updated as the LAT pin is

driven low.

1

0

1

0

1

0

1

0

No Transfer

Vol. DAC Register x  DAC Wiper x

No Transfer

Figure 5-8 shows the interaction of the LAT pin and the

loading of the DAC Wiper x (from the Volatile DAC

Register x). The transfers are level-driven. If the LAT

pin is held low, the corresponding DAC wiper is

updated as soon as the Volatile DAC register value is

updated.

FIGURE 5-8:

LAT and DAC Interaction.

The LAT pin allows the DAC wiper to be updated to an

external event and to have multiple DAC

channels/devices update at a common event.

Since the DAC Wiper x is updated from the Volatile

DAC Register x, all DACs that are associated with a

given LAT pin can be updated synchronously.

If the application does not require synchronization, then

this signal should be tied low.

Figure 5-9 shows two cases of using the LAT pin to

control when the Wiper register is updated relative to

the value of a sine wave signal.

Case 1: Zero-Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Case 2: Fixed-Point Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Indicates where LAT pin pulses are active (Volatile DAC0 register updated)

FIGURE 5-9:

Example Use of LAT Pin Operation.

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DS20006089B-page 65

MCP47CXBXX

The power-down bits are modified by using a write

command to the Volatile Power-Down register, or a POR

event, which transfers the Nonvolatile Power-Down

register to the Volatile Power-Down register.

Section 7.0 “Device Commands” describes the I²C

commands for writing the power-down bits. The

commands that can update the volatile PD1:PD0 bits are:

5.5

Power-Down Operation

To allow the application to conserve power when DAC

operation is not required, three Power-Down modes

are available. On devices with multiple DACs, each

DAC’s Power-Down mode is individually controllable.

All Power-Down modes do the following:

• Turn off most of the DAC module’s internal circuits

• Op amp output becomes high-impedance to the

• Write

• General Call Reset

• General Call Wake-up

V_OUTpin

• Retain the value of the Volatile DAC register and

Configuration bits

Note 1: The I²C serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

I²C Master device.

Depending on the selected Power-Down mode, the

following will occur:

• V_OUTpin is switched to one of the two resistive

pull-downs:

2: A General Call Reset will do the POR

event sequence, except that the MTP

shadow memory values will be transfered

to the Volatile Memory registers.

- 100 k (typical)

- 1 k (typical)

• Op amp is powered down and the V_OUTpin

becomes high-impedance

The Power-Down Configuration bits (PD1:PD0) control

the power-down operation (Table 5-4).

5.5.1

EXITING POWER-DOWN

The following events change the PD1:PD0 bits to ‘00’,

and therefore, exit the Power-Down mode. These are:

• Any I²C Write Command, where the PD1:PD0 bits

TABLE 5-4:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

are ‘00’

PD1

PD0

Function

• I²C General Call Wake-up Command

• I²C General Call Reset Command

0

1

0

1

0

1

Normal operation

1 k resistor to ground

100 k resistor to ground

Open circuit

When the device exits Power-Down mode, the

following occurs:

• Disabled internal circuits are turned on

There is a delay (T_PDD) between the PD1:PD0 bits

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the

op amp no longer driving the V_OUToutput, and the

pull-down resistors’ sinking current.

• Resistor ladder is connected to the selected

Reference Voltage (V_RL

)

• Selected pull-down resistor is disconnected

• The V_OUToutput is driven to the voltage

represented by the Volatile DAC register’s value

and Configuration bits

In any of the Power-Down modes, where the V_OUTpin

is not externally connected (sinking or sourcing cur-

rent), as the number of DACs increases, the device’s

power-down current will also increase.

The DAC Wiper register and DAC wiper value may be

different due to the DAC Wiper register being modified

while the LAT pin was driven to (and remaining at) V_IH.

Table 5-5 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in normal operating mode or one of

the Power-Down modes.

The V_OUToutput signal requires time as these circuits

are powered up and the output voltage is driven to the

specified value, as determined by the Volatile DAC

register and Configuration bits.

TABLE 5-5:

DAC CURRENT SOURCES

PDxB:xA = 00

VREFxB:xA =

,

PDxB:xA  00

VREFxB:xA =

,

Device V_DDCurrent

Source

Note:

Since the op amp and resistor ladder were

powered off (0V), the op amp’s Input

Voltage (V_W) can be considered as 0V.

There is a delay (T_PDE) between the

PD1:PD0 bits updating to ‘00’ and the

op amp driving the V_OUToutput. The

op amp’s settling time (from 0V) needs to

be taken into account to ensure the V_OUT

voltage reflects the selected value.

00 01 10 11 00 01 10 11

Output Op Amp

Resistor Ladder

V_REFSelection Buffer

Band Gap

Y

N

Y

N⁽¹⁾

N

Y

N

N⁽¹⁾

N

N⁽²⁾Y⁽²⁾N⁽²⁾N⁽²⁾

Note 1: The current is sourced from the V_REFpin, not the

device V_DD

.

2: If DAC0 and DAC1 are in one of the Power-Down

modes, MTP write operations are not recommended.

DS20006089B-page 66

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

TABLE 5-6:

Device

DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (V_OUT) (V_DD= 5.0V)

(3)

LSb

Equation

5.0V/4096 1,220.7

2.5V/4096 610.4

V_OUT

Equation

Volatile DAC

Register Value

Gain

(1)

V_RL

Selection ⁽²⁾

µV

V

1111 1111 1111 5.0V

1x

2x⁽²⁾

V_RL (4095/4096)  1

V_RL (4095/4096)  2)

V_RL (2047/4096)  1)

V_RL (2047/4096)  2)

V_RL (1023/4096)  1)

V_RL (1023/4096)  2)

V_RL (0/4096) * 1)

V_RL (0/4096) * 2)

V_RL (1023/1024)  1

V_RL (1023/1024)  2

V_RL (511/1024)  1

V_RL (511/1024)  2

V_RL (255/1024)  1

V_RL (255/1024)  2

V_RL (0/1024)  1

4.998779

2.499390

4.998779

2.498779

1.249390

2.498779

1.248779

0.624390

1.248779

0

2.5V

0111 1111 1111 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0011 1111 1111 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0000 0000 0000 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0

11 1111 1111

01 1111 1111

00 1111 1111

00 0000 0000

1111 1111

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

4.995117

2.497559

4.995117

2.495117

1.247559

2.495117

1.245117

0.622559

1.245117

0

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

V_RL (0/1024)  1

0

V_RL (0/1024)  1

0

5.0V

2.5V

5.0V/256 19,531.3

1x

V_RL (255/256)  1

V_RL (255/256)  2

V_RL (127/256)  1

V_RL (127/256)  2

V_RL (63/256)  1

4.980469

2.490234

4.980469

2.480469

1.240234

2.480469

1.230469

0.615234

1.230469

0

2.5V/256

9,765.6

1x

2x⁽²⁾

0111 1111

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

2x⁽²⁾

0011 1111

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

V_RL (63/256)  1

2x⁽²⁾

V_RL (63/256)  2

0000 0000

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

V_RL (0/256)  1

1x

V_RL (0/256)  1

0

2x⁽²⁾

V_RL (0/256)  2

0

Note 1:

V_RLis the resistor ladder’s reference voltage. It is independent of the VREF1:VREF0 selection.

2: Gain selection of 2x (Gx = 1) requires the voltage reference source to come from the V_REFpin

(VREF1:VREF0 = 10or 11) and requires V_REFpin voltage (or V_RL) ≤ V_DD/2 or from the internal band gap

(VREF1:VREF0 = 01).

3: These theoretical calculations do not take into account the offset, gain and nonlinearity errors.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 67

MCP47CXBXX

NOTES:

DS20006089B-page 68

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

2

6.2

Communication Data Rates

6.0

I C SERIAL INTERFACE

The I²C interface specifies different communication bit

rates. These are referred to as Standard, Fast or High-

Speed modes. The MCP47CXBXX supports these

three modes. The clock rates (bit rate) of these modes

are:

MODULE

The MCP47CXBXX’s I²C serial interface module

supports the I²C serial protocol specification. This I²C

interface is a two-wire interface (clock and data).

Figure 6-1 shows a typical I²C interface connection.

• Standard mode: Up to 100 kHz (kbit/s)

• Fast mode: Up to 400 kHz (kbit/s)

The I²C specification only defines the field types,

lengths, timings, etc., of a frame. The frame content

defines the behavior of the device. The frame content

(commands) for the MCP47CXBXX is defined in

Section 7.0 “Device Commands”.

• High-Speed mode (HS mode): Up to 3.4 MHz

(Mbit/s)

A description on how to enter High-Speed mode is

described in Section 6.8 “Slope Control”.

An overview of the I²C protocol is available in

Appendix B: “I²C Serial Interface”.

6.3

POR/BOR

Typical I²C Interface Connections

On a POR/BOR event, the I²C serial interface module

state machine is reset, which includes forcing the

device’s Memory Address Pointer to 00h.

MCP47CVBXX

(Slave)

Host

Controller

(Master)

6.4

Device Memory Address

SCL

SDA

The memory address is the 5-bit value that specifies

the location in the device’s memory that the specified

command will operate on.

SDA

On a POR/BOR event, the device’s Memory Address

Pointer is forced to 00h.

Other Devices

Typical I²C Interface.

FIGURE 6-1:

The MCP47CXBXX retains the last received “Device

Memory Address”. That is, the MCP47CXBXX does not

“corrupt” the “device memory address” after Repeated

Start or Stop conditions.

6.1

Overview

This section discusses some of the specific character-

istics of the MCP47CXBXX devices’ I²C serial interface

module. This is to assist in the development of your

application.

6.5

General Call Commands

The general call commands utilize the I²C specification

reserved general call command address and command

The following sections discuss some of these

device-specific characteristics.

codes. The MCP47CXBXX also implements

nonstandard general call command.

a

• Interface Pins (SCL and SDA)

• Communication Data Rates

• POR/BOR

The general call commands are:

• General Call Reset

• Device Memory Address

• General Call Commands

• Device I²C Slave Addressing

• Slope Control

• General Call Wake-up (MCP47CXBXX defined)

The general call wake-up command will cause all the

MCP47CXBXX devices to exit their power-down state.

6.6

Multi-Master Systems

6.1.1

INTERFACE PINS (SCL AND SDA)

The MCP47CXBXX is not a Master device (generates

the interface clock), but it can be used in Multi-Master

applications.

The MCP47CXBXX I²C module SCL pin does not

generate the serial clock since the device operates in

Slave mode. Also, the MCP47CXBXX will not stretch

the clock signal (SCL) since memory read access

occurs fast enough.

The MCP47CXBXX I²C module implements slope

control on the SDA pin output driver.

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DS20006089B-page 69

MCP47CXBXX

Table 6-1 shows the four standard orderable I²C Slave

addresses and their respective device order codes.

2

6.7

Device I C Slave Addressing

The address byte is the first byte received following the

Start (or Repeated Start) condition from the Master device

(see Figure 6-2). For nonvolatile devices, the seven bits of

the I²C Slave address are user-programmable. The

default address is ‘110 0000’. If the address pins are

present on the specific package, the lower two bits of

the address are determined by the state of the A1 and

A0 pins.

TABLE 6-1:

I²C ADDRESS/ORDER CODE

Default

Memory

Tape

and

Reel

Device Order

2

7-Bit I C

(1)

Code

VOL NV

Address

MCP47CXBXX-E/XX

Y

N

Y

‘1100000’

MCP47CXBXXT-E/XX

2

Note:

Address bits, A6:A0, are MTP and can

be programmed during the user’s

manufacturing flow.

Note 1: Nonvolatile devices’ I C Slave address can

be reprogrammed by the end user.

6.7.1

CUSTOM I²C SLAVE ADDRESS

OPTIONS

For volatile devices (MCP47CVBXX), the I²C Slave

address bits, A6:A0, are fixed (‘110 0000’). The user

still has Slave address programmability with the A1:A0

address pins (if available on the package).

Custom I²C Slave address options can be requested.

Users can request the custom I²C Slave address via

the Nonstandard Customer Authorization Request

(NSCAR) process.

Acknowledge Bit

Note:

Non-Recurring Engineering (NRE) charges

and minimum ordering requirements for

custom orders. Please contact Microchip

sales for additional information.

Start Bit

Read/Write Bit

Slave Address

Address Byte

R/W ACK

A custom device will be assigned custom

device marking.

Slave Address (7 bits)

Default

Factory

Address

(Note 1)

6.8

Slope Control

1

0

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

Clock modes of the interface.

A6 A5 A4 A3 A2 A1 A0

6.9

Pulse Gobbler

Note 1: Address bits (A6:A0) can be

programmed by the user

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes <10 ns during HS mode.

(MCP47CMBXX devices). Bits A1 and

A0 are determined by either the MTP

bits or the A0 and A1 pin values if

present on the package.

FIGURE 6-2:

Slave Address Bits in the

I²C Control Byte.

DS20006089B-page 70

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MCP47CXBXX

After switching to High-Speed mode, the next trans-

ferred byte is the I²C control byte, which specifies the

device to communicate with and any number of data

bytes plus Acknowledgments. The Master device can

then either issue a Repeated Start bit to address a

different device (at High-Speed mode) or a Stop bit to

return to the bus Fast/Standard Speed mode. After the

Stop bit, any other Master device (in a Multi-Master

system) can arbitrate for the I²C bus.

6.10 Entering High-Speed (HS) Mode

The I²C specification requires that a High-Speed mode

device be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by the Master sending

a special address byte following the Start bit. This byte

is referred to as the High-Speed Master Mode Code

(HSMMC).

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

The MCP47CXBXX device does not Acknowledge the

HS select byte. However, upon receiving this

command, the device switches to HS mode.

The Master code is sent as follows:

1. Start condition (S).

See Figure 6-3 for an illustration of the HS mode

command sequence.

2. High-Speed Master Mode Code (‘0000 1xxx’);

the ‘xxx’ bits are unique to the High-Speed (HS)

Master mode.

For more information on the HS mode, or other I²C

modes, refer to the “NXP I²C Specification”.

3. No Acknowledge (A).

F/S Mode

HS Mode

P

F/S Mode

S

‘

0000 1xxx’b

’

A Sr Slave Address R/W

Control Byte

A

Data

A/A

HS Mode Continues

Sr Slave Address R/W

A

HS Select Byte

Command/Data Byte(s)

S = Start bit

Sr = Repeated Start bit

Control Byte

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

P = Stop bit (Stop condition terminates HS mode)

FIGURE 6-3: HS Mode Sequence.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 71

MCP47CXBXX

NOTES:

DS20006089B-page 72

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

See Section 7.5 “Write Command” for a full description

of the write commands.

7.0

DEVICE COMMANDS

The I²C protocol does not specify how commands are

formatted, so this section specifies the MCP47CXBXX

device’s I²C command formats and operation.

Note:

The 8-bit data devices use the same

format as 10-bit and 12-bit devices. This

allows code migration compatibility at the

cost of nine extra clock cycles per data

byte transferred.

The commands can be grouped into the following

categories:

• Write Commands (C1:C0 = 00)

• Read Commands (C1:C0 = 11)

• General Call Commands

7.2

Read Commands

Read commands are used to transfer data from the

desired memory location to the Host controller. The

read command format writes two bytes (Control byte

(R/W bit) = 0) and the read command byte (desired

memory address and the read command). Then, a

Restart condition is followed by a second control byte,

but this control byte indicates an I²C read operation

(R/W bit = 1). The Master will then supply 16 clocks so

the specified address data are transfered. See

Section 7.6 “Read Command” for full a description of

the read commands.

The supported commands are shown in Table 7-1.

These commands allow both single data or continuous

data operation. Continuous data operation means that

the I²C Master does not generate a Stop bit but repeats

the required data/clocks. This allows faster updates

since the overhead of the I²C control byte is removed.

Table 7-1 also shows the required number of bit clocks

for each command’s different mode of operation.

7.1

Write Commands

Write commands are used to transfer data to the

desired memory location (from the Host controller). The

modes are Single or Continuous. The Continuous

mode format allows the fastest data update rate for the

device’s memory locations.

TABLE 7-1:

DEVICE COMMANDS – NUMBER OF CLOCKS

Command

Code

C1 C0

Data Update Rate

(8-bit/10-bit/12-bit)

(Data Words/Second)

# of Bit

Clocks

Comments

(1)

Operation

Mode

(3)

100 kHz 400 kHz 3.4 MHz

(4)

Write Command

0

Single

38

27n + 11

48

2,632

3,559

2,083

4,762

3,448

5,000

10,526

14,235

8,333

89,474

Continuous

Random

120,996 For ten data words

70,833

Read Command

1

Continuous

Last Address

Single

18n + 11

29

19,048

13,793

20,000

161,905 For ten data words

117,241

1

General Call Reset

Command

—

20

170,000 Note 2

General Call Wake-up

Command

—

Single

20

5,000

20,000

170,000 Note 2

Note 1: “n” indicates the number of times the command operation is to be repeated.

2

2: Determined by general call command byte after the I C general call address.

3: There is a minimal overhead to enter into 3.4 MHz mode.

4: This command can be at either normal or high voltage. A high-voltage command requires the HVC pin to be at

, for the entire command, until the completion of the MTP cycle.

V

IHH

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DS20006089B-page 73

MCP47CXBXX

A write command to a volatile memory location

changes that location after a properly formatted write

command and the rising edge of the D00 bit (last data

bit) clock has been detected.

7.3

General Call Commands

The general call commands utilize the I²C specification

reserved general call command address and command

codes. The General Call Reset command format is

specified by the “NXP I²C Specification”. The general

call wake-up command is a Microchip-defined format.

I²C devices Acknowledge the general call address

command (0x00 in the first byte). The meaning of the

general call address is always specified in the second

byte. The I²C specification does not allow ‘00000000’

(00h) in the second byte. Also, the ‘00000100’ and

‘00000110’ functionality is defined by the “NXP I²C

Specification”. Lastly, a data byte with a ‘1’ in the LSb

indicates a “Hardware General Call”.

A write command to a nonvolatile memory location will

only start a write cycle after a properly formatted write

command has been received and the Stop condition

has occurred.

Note 1: Writes to volatile memory locations will

be dependent on the state of their

respective WiperLock Technology bits.

2: During device communication, if the

device address/command combination is

invalid or an unimplemented device

address is specified, then the MCP47CX-

BXX will NACK that byte. To reset the I²C

state machine, the I²C communication

must detect a Start bit.

Please refer to the “NXP I²C Specification” for more

details on the general call specifications.

The MCP47CXBXX devices support the following I²C

general calls:

3: Writes to volatile memory locations will

be dependent on the state of their

respective WiperLock Technology bits.

• General Call Reset

• General Call Wake-up

See Section 7.7.1 “General Call Reset” for a full

description of the General Call Reset command and

the general call wake-up command.

7.5.1

SINGLE WRITE TO VOLATILE

MEMORY

For volatile memory locations, data are written to the

MCP47CXBXX after every data word transfer (16 bits)

during the rising edge of the last data bit. If a Stop or

Restart condition is generated during a data transfer

(before the last data bit is received), the data will not be

written to the MCP47CXBXX. After the A bit, the Master

can initiate the next sequence with a Stop or Restart

condition. (See Figure 7-1 for the write sequence.)

7.4

Aborting a Transmission

A Restart or Stop condition in an expected data bit

position will abort the current command sequence, and

if the command is a write, that data word will not be writ-

ten to the MCP47CXBXX. Also, the I²C state machine

will be reset.

7.5

Write Command

Note:

Writes to a Volatile DAC register will not

transfer to the output register until the LAT

(HVC) pin is transitioned to the V_IL

voltage.

The write command can be issued to both the volatile

and nonvolatile memory locations. Write commands

can also be structured as either single or continuous.

The continuous format allows the fastest data update

rate for the device’s memory locations.

7.5.2

SINGLE WRITE TO NONVOLATILE

MEMORY (HVC PIN = V_ILOR V_IH)

The format of the command is shown in Figure 7-1. The

MCP47CXBXX generates the A/A bits. The format of

the command is shown in Figure 7-1 (single) and

Figure 7-3 (continuous); for example, ACK/NACK

behavior (see Figure 7-2).

In normal user mode, the MTP memory address

cannot be written. Writing to the MTP address space,

while the HVC pin is not at V_IHH, will not have any

effect; the command is Acknowledged but the memory

is not modified.

DS20006089B-page 74

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

During an MTP write cycle, access to the volatile mem-

ory is allowed when using the appropriate command

sequence. Commands that address nonvolatile memory

are ignored until the MTP Write Cycle (t_wc) completes.

This allows the Host controller to operate on the Volatile

DAC registers.

7.5.3

SINGLE WRITE TO NONVOLATILE

MEMORY (HVC PIN = V_IHH

)

Note:

Writes to MTP memory require the HVC

pin at 7.5V. This is not the normal operat-

ing conditions of the device; it is designed

for factory programming of configuration

parameters.

Once a write command to a nonvolatile memory

location has been received, no other commands should

be received before the Stop condition occurs.

The sequence to write to a single nonvolatile memory

location is the same as a single write to volatile memory,

with the exception that the MTP Write Cycle (t_wc) is

started after a properly formatted command, including

the Stop bit, is received. After the Stop condition occurs,

the serial interface may immediately be re-enabled by

initiating a Start condition.

Note:

If a Stop condition does not occur, then the

NV Write does not occur and all following

command(s) will have an error condition

(A). A Start bit is required to reset the com-

mand state machine.

Writes to a NV memory location while an MTP write

cycle is occurring will force an error condition (A). A

Start bit is required to reset the command state

machine.

The HVC pin must be at V_IHHuntil the completion of the

MTP Write Cycle (t_wc).

Figure 7-1 shows the waveform for a single write.

Control Byte

Write Command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

0

x

A

6

5

4

3

2

1

0

4

3

2

1

0

Data to Write MSB

Data to Write LSB

D

A

P

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Start Bit

I²C ACK bit⁽¹⁾

A

Reserved, should be Set to ‘0’

Register Data (to be written)⁽²⁾

I²C Stop Bit⁽³⁾

S

x

SA

n

AD

n

D

nn

I²C Slave Address

I²C Write Bit

Memory Address

0

P

Write Command

Note 1: The Acknowledge bit is generated by the MCP47CXBXX.

2: At the rising edge of the SCL signal for the last bit (D00) of the write command, the device updates the

value of the specified device register. For DAC Output registers, the output voltage depends on the

state of the LAT pin.

3: This command sequence does not need to terminate (using the Stop bit) and the write command can

be repeated (see continuous write format, Section 7.5.4 “Continuous Writes to Volatile Memory”).

FIGURE 7-1:

Write Random Address Command.

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MCP47CXBXX

7.5.4

CONTINUOUS WRITES TO

VOLATILE MEMORY

7.5.5

CONTINUOUS WRITES TO

NONVOLATILE MEMORY

A Continuous Write mode of operation is possible when

writing to the device’s Volatile Memory registers (see

Table 7-2). This Continuous Write mode allows writes

without a Stop or Restart condition, or repeated trans-

missions of the I²C control byte. Figure 7-3 shows the

sequence for three continuous writes. The writes do not

need to be to the same volatile memory address. The

sequence ends with the Master sending a Stop or

Restart condition.

If a continuous write is attempted on nonvolatile

memory, the missing Stop condition will cause the

command to be an error condition (A) on all following

bytes. A Start bit is required to reset the command state

machine.

Note:

All bytes are ignored and not transferred

to memory.

TABLE 7-2:

VOLATILE MEMORY

ADDRESSES

Address

Single Channel

Dual Channel

00h

01h

08h

09h

0Ah

Yes

No

Yes

Write 1 Word Command

S

Slave Address

Command

Data Byte

P

Master

0

x

Example 1 (No Command Error)

Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P

MCP47CXBXX

I²C Bus

0

S 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 x 0 d d d d d d d d 0 d d d d d d d d 0 P

Example 2 (Command Error)

Master

S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1 d d d d d d d d 1 d d d d d d d d 1 P

MCP47CXBXX

0

1

I²C Bus

S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 0 d d d d d d d d 1 d d d d d d d d 1 P

Note: Once a command error has occurred (Example 2), the MCP47CVBXX will NACK until a Start condition occurs.

FIGURE 7-2:

I²C ACK/NACK Behavior (Write Command Example).

DS20006089B-page 76

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MCP47CXBXX

Control Byte

Write Command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

0

x

A

6

5

4

3

2

1

0

4

3

2

1

0

Data to Write MSB

Data to Write LSB

D

A

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Write Command

AD AD AD AD AD

0

x

A

4

3

2

1

0

Data to Write MSB

Data to Write LSB

D

A

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Write Command

AD AD AD AD AD

0

x

A

4

3

2

1

0

Data to Write MSB

Data to Write LSB

D

A

P

15 14 13 12 11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Start Bit

I²C ACK Bit ⁽¹⁾

A

Reserved, should be Set to ‘0’

Register Data (to be written)⁽²⁾

I²C Stop Bit⁽³⁾

S

x

SA

n

AD

n

D

nn

I²C Slave Address

I²C Write Bit

Memory Address

0

P

Write Command

Note 1: The Acknowledge bit is generated by the MCP47CXBXX.

2: At the falling edge of the SCL pin for the write command ACK bit, the MCP47CXBXX device updates

the value of the specified device register.

3: This command sequence does not need to terminate (using the Stop bit) and the write command can

be repeated (see continuous write format, Section 7.5.4 “Continuous Writes to Volatile Memory”).

4: Only functions when writing to Volatile registers (AD4:AD0 = 00h through 0Ah).

FIGURE 7-3:

Continuous Write Commands (Volatile Memory Only).

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DS20006089B-page 77

MCP47CXBXX

7.6.1

SINGLE READ

7.6

Read Command

The read command format writes two bytes, the control

byte and the read command byte (desired memory

address and the read command), and then has a

Restart condition. Then, a second control byte is

transmitted, but this control byte indicates an I²C read

operation (R/W bit = 1).

Read commands are used to transfer data from the

specified memory location to the Host controller.

The read command can be issued to both the volatile

and nonvolatile memory locations. During an MTP

memory write cycle, the read command can only read

the volatile memory locations. By reading the Status

Register (0Ah), the Host controller can determine

when the Write Cycle (t_wc) has been completed (via

the state of the MTPMA bit).

7.6.1.1

Single Memory Address

Figure 7-4 shows the sequence for reading a specified

memory address.

The read command formats include:

7.6.1.2

Last Memory Address Accessed

• Single Read

- Single Memory Address

- Last Memory Address Accessed

• Continuous Reads

This is useful for checking the status of the MTPMA bit

or when writes to other I²C devices on the bus must

occur between these memory reads. The Master must

send a Stop or Restart condition after the data word is

sent from the Slave. Figure 7-5 shows the waveforms

for a single read of the last memory location accessed.

The MCP47CXBXX retains the last received device

memory address. This means the MCP47CXBXX does

not corrupt the device memory address after Repeated

Start or Stop conditions.

7.6.2

CONTINUOUS READS

Continuous reads allow the device’s memory to be

read quickly and are valid for all memory locations.

Note 1: During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, the MCP47CXBXX will NACK

that byte. To reset the I²C state machine,

the I²C communication must detect a

Start bit.

Figure 7-7 shows the sequence for three continuous

reads.

For continuous reads, instead of transmitting a Stop or

Restart condition after the data transfer, the Master

continually reads the data byte. The sequence ends

with the Master Not Acknowledging and then sending a

Stop or Restart.

2: If the LAT pin is high (V_IH), reads of the

Volatile DAC register return the current

output value, not the internal register

value.

7.6.3

IGNORING AN I²C TRANSMISSION

AND “FALLING OFF” THE BUS

3: The read commands operate the same

regardless of the state of the High-Voltage

Command (HVC) signal.

The MCP47CXBXX expects to receive complete, valid

I²C commands and will assume any command not

defined as a valid command is due to a bus corruption,

thus entering a passive high condition on the SDA

signal. All signals will be ignored until the next valid

Start condition and control byte are received.

DS20006089B-page 78

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MCP47CXBXX

Control Byte

Read Command

SA SA SA SA SA SA SA

AD AD AD AD AD

S

0

A

1

x

1

A

6

5

4

3

2

1

0

4

3

2

1

0

Control Byte

SA SA SA SA SA SA SA

Sr

6

5

4

3

2

1

0

Data Read MSB

Data Read LSB

D

A

P

0

11 10 09 08

07 06 05 04 03 02 01 00

Legend:

AD

n

I²C Start Bit

Memory Address⁽⁵⁾

I²C Read Bit

I²C Stop Bit⁽³⁾

S

1

P

SA

n

D

nn

I²C Slave Address

Read Command

Data (read from memory)

1

x

1

I²C Write Bit

Reserved, Set to ‘0’

I C ACK Bit

2

(2)

0

A

I²C ACK Bit⁽¹⁾

I²C Start Bit, Repeated

I²C NACK Bit⁽⁴⁾

A

Sr

Note 1: The Master device is responsible for the A/A signal. If an A signal occurs, the MCP47CXBXX will

abort this transfer and release the bus.

2: This Acknowledge bit is generated by the Master device.

3: This command sequence does not need to terminate (using the Stop bit) and the read command can

be repeated (see Section 7.6.2 “Continuous Reads”).

4: The Master device will Not Acknowledge and the MCP47CXBXX will release the bus so the Master

device can generate a Stop or Repeated Start condition.

5: The MCP47CXBXX retains the last received “device memory address”.

6: The non-data bits of the Read Data Word will be output as ‘0’s:

for 12-bit devices, bits D15:D12 are ‘0’s

for 10-bit devices, bits D15:D10 are ‘0’s

for 8-bit devices, bits D15:D08 are ‘0’s

FIGURE 7-4:

Read Command – Single Memory Address.

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DS20006089B-page 79

MCP47CXBXX

Control Byte

SA SA SA SA SA SA SA

S

1

A

6

5

4

3

2

1

0

Data Read MSB

Data Read LSB

D

A

P

0

11 10 09 08

07 06 05 04 03 02 01 00

Legend:

I²C Start Bit

I²C Read Bit

I²C NACK Bit⁽⁴⁾

I²C Stop Bit⁽³⁾

S

1

A

SA

n

D

nn

I²C Slave Address

I²C ACK Bit⁽¹⁾

Data (read from memory)

P

2

(2)

A

I C ACK Bit

Note 1: The Master device is responsible for the A/A signal. If an A signal occurs, the MCP47CXBXX will

abort this transfer and release the bus.

2: This Acknowledge bit is generated by the Master device.

3: This command sequence does not need to terminate (using the Stop bit) and the read command can

be repeated (see Section 7.6.2 “Continuous Reads”).

4: The Master device will Not Acknowledge and the MCP47CXBXX will release the bus so the Master

device can generate a Stop or Repeated Start condition.

5: The MCP47CXBXX retains the last received “Device Memory Address”.

6: The non-data bits of the Read Data Word will be output as ‘0’s:

for 12-bit devices, bits D15:D12 are ‘0’s

for 10-bit devices, bits D15:D10 are ‘0’s

for 8-bit devices, bits D15:D08 are ‘0’s

7: If the last device address written (via the read or write command) is invalid for a read, then the read

last memory address command will NACK due to the invalid device memory address.

FIGURE 7-5:

Read Command – Last Memory Address Accessed.

DS20006089B-page 80

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MCP47CXBXX

Read 1 Word Command

S

Slave Address

Command

Master

0

1

Slave Address

Data Byte

P

Master (Continued)

1 P

1 1

1

Example 1 (No Command Error)

Master S 1 1 0 0 0 0 0 0 1 0 0 0 0 1 1 1 x 1

MCP47CXBXX

0

I²C Bus S 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 x 0

Master (Continued)

S 0 0 0 0 1 0 0 1 1

1

1 P

MCP47CXBXX (Continued)

I²C Bus (Continued)

0 d d d d d d d d 0 d d d d d d d d 0

S 0 0 0 0 0 0 0 1 0 d d d d d d d d 0 d d d d d d d d 0 P

Example 2 (Command Error)

Master S 1 1 0 0 0 0 0 0 1 0 1 1 1 1 0 0 x 1

MCP47CXBXX

I²C Bus S 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 x 1

0

1

Master (Continued)

S 1 1 0 0 0 0 0 1 1

1

1 P

MCP47CXBXX (Continued)

I²C Bus (Continued)

0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1

S 1 1 0 0 0 0 0 1 0 ? ? ? ? ? ? ? ? 0 ? ? ? ? ? ? ? ? 1 P

Note 1: Once a command error has occurred (Example 2), the MCP47CXBXX will NACK until a Start condition

occurs.

2: For command error case (Example 2), the data read is from the register of the last valid address loaded

into the device.

FIGURE 7-6:

I²C ACK/NACK Behavior (Read Command Example).

 2018-2019 Microchip Technology Inc.

DS20006089B-page 81

MCP47CXBXX

Control Byte

Read Command

SA SA SA SA SA SA SA

S

AD AD AD AD AD

0

A

Sr

D

1

x

1

A

6

5

4

3

2

1

0

4

3

2

1

0

Control Byte

SA SA SA SA SA SA SA

A

D

6

5

4

3

2

1

0

Data Read MSB

Data Read LSB

D

A

0

11 10 09 08

07 06 05 04 03 02 01 00

Data Read MSB

Data Read LSB

D

A

0

11 10 09 08

07 06 05 04 03 02 01 00

Data Read MSB

Data Read LSB

D

P

0

11 10 09 08

07 06 05 04 03 02 01 00

Legend:

AD

n

I²C Start Bit

Memory Address⁽⁵⁾

I²C Read Bit

P

I²C Stop Bit⁽³⁾

S

1

SA

n

D

nn

I²C Slave Address

I²C Write Bit

Read Command

Data (read from memory)

1

2

(2)

0

x

A

Reserved, Set to ‘0’

I C ACK Bit

I²C ACK Bit⁽¹⁾

I²C Start Bit, Repeated

I²C NACK Bit⁽⁴⁾

A

Sr

Note 1: The Master device is responsible for the A/A signal. If an A signal occurs, the MCP47CXBXX will

abort this transfer and release the bus.

2: This Acknowledge bit is generated by the Master device.

3: This command sequence does not need to terminate (using the Stop bit) and the read command can

be repeated (see Section 7.6.2 “Continuous Reads”).

4: The Master device will Not Acknowledge and the MCP47CXBXX will release the bus so the Master

device can generate a Stop or Repeated Start condition.

5: The MCP47CXBXX retains the last received “Device Memory Address”.

6: The non-data bits of the Read Data Word will be output as ‘0’s:

for 12-bit devices, bits D15:D12 are ‘0’s

for 10-bit devices, bits D15:D10 are ‘0’s

for 8-bit devices, bits D15:D08 are ‘0’s

FIGURE 7-7:

Continuous Read Command of Specified Address.

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MCP47CXBXX

The General Call Reset command format is specified

by the I²C Specification. The general call wake-up

command is a Microchip-defined format. The general

call wake-up command will have all devices wake-up

(that is, exit the Power-Down mode).

The other two I²C specification command codes (04h

and 00h) are not supported, and therefore, those

commands are Not Acknowledged.

If these 7-bit commands conflict with other I²C devices

on the bus, the user will need two I²C buses to ensure

that the devices are on the correct bus for their desired

application functionality.

7.7

General Call Commands

The MCP47CXBXX Acknowledges the general call

address command (00h in the first byte). General call

commands can be used to communicate to all devices

on the I²C bus (at the same time) that understand the

general call command. The meaning of the general call

address is always specified in the second byte (see

Figure 7-8).

If the second byte has a ‘1’ in the LSb, the specification

intends this to indicate a “Hardware General Call”. The

MCP47CXBXX will ignore this byte and all following

bytes (and A), until a Stop bit (P) is encountered.

The MCP47CXBXX devices support the following I²C

general call commands:

Note:

Refer to the “NXP Specification”,

#UM10204, Rev. 03 19, June 2007 docu-

ment for more details on the general call

specifications. The I²C specification does

not allow ‘00000000’ (00h) in the second

byte.

• General Call Reset (06h)

• General Call Wake-up (0Ah)

General Call Address

7-Bit Command

S

A

0

x

0

A

P

0

Legend:

I²C Start Bit

I²C ACK Bit⁽¹⁾

GC Command

I²C Stop Bit^(2,3)

S

A

x

P

Note 1: The Acknowledge bit is generated by the MCP47CXBXX.

2: This command sequence does not need to terminate (using the Stop bit) and the general call com-

mand can be repeated or another general call command can be sent. Only the first command will

be accepted by the MCP47CXBXX.

FIGURE 7-8:

General Call Formats.

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DS20006089B-page 83

MCP47CXBXX

7.7.1

GENERAL CALL RESET

7.7.2

GENERAL CALL WAKE-UP

The I²C General Call Reset command forces a reset

event. This is similar to the Power-On Reset, except

that the reset delay timer is not started. This command

allows multiple devices to be reset synchronously.

The I²C General Call Wake-Up command forces the

device to exit from its Power-Down state (forces the

PDxB:PDxA bits to ‘00’). This command allows multiple

MCP47CXBXX devices to wake up synchronously.

The device performs General Call Reset if the second

byte is ‘00000110’ (06h). At the acknowledgment of

this byte, the device will perform the following tasks:

The device performs General Call Wake-Up if the

second byte (after the General Call Address) is

‘00001010’ (0Ah). At the acknowledgment of this byte,

the device will perform the following task:

• Internal reset similar to a POR. The contents of

the MTP are loaded into the DAC registers

• The device’s volatile power-down bits

(PDxB:PDxA) are forced to ‘00’.

• Analog output (V_OUT) is available after the POR

sequence has been completed.

7-Bit Command

General Call Address

S

A

0

1

0

A

P

0

Legend:

I²C Start Bit

I²C ACK Bit⁽¹⁾

Reset Command

I²C Stop Bit^(2,3)

S

A

0

1

P

Note 1: The Acknowledge bit is generated by the MCP47CXBXX.

2: At the falling edge of the SCL pin for the General Call Reset command ACK bit, the

MCP47CXBXX device is reset.

3: This command sequence does not need to terminate (using the Stop bit) and the General Call Reset

command can be repeated or the general call wake-up command can be sent. Only the first

command will be accepted by the MCP47CXBXX.

FIGURE 7-9:

General Call Reset Command.

7-Bit Command

General Call Address

S

A

0

1

0

1

0

A

P

0

Legend:

I²C Start Bit

I²C ACK Bit⁽¹⁾

Reset Command

I²C Stop Bit⁽³⁾

S

A

1

0

1

P

Note 1: The Acknowledge bit is generated by the MCP47CXBXX.

2: At the rising edge of the last data bit for the general call wake-up command, the volatile

Power-Down bits (PDxB:PDxA) are forced to ‘00’.

3: This command sequence does not need to terminate (using the Stop bit) and the general call

wake-up command can be repeated or the General Call Reset command can be sent.

FIGURE 7-10:

General Call Wake-up Command.

DS20006089B-page 84

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MCP47CXBXX

8.1.1

DEVICE CONNECTION TEST

8.0

TYPICAL APPLICATIONS

The user can test the presence of the device on the I²C

bus line using a simple I²C command. This test can be

achieved by checking an Acknowledge response from

the device after sending a read or write command.

Figure 8-1 shows an example with a read command.

The steps are:

The MCP47CXBXX devices are general purpose,

single/dual channel voltage output DACs for various

applications where a precision operation with low

power is needed.

Applications generally suited for the devices are:

• Set Point or Offset Trimming

• Sensor Calibration

1. Set the R/W bit “High” in the device’s address byte.

2. Check the ACK bit of the address byte.

If the device Acknowledges (ACK = 0) the

command, then the device is connected;

otherwise, it is not connected.

• Portable Instrumentation (Battery-Powered)

• Motor Control

2

3. Send Stop bit.

8.1

Connecting to the I C Bus Using

Pull-up Resistors

Address Byte

The SCL and SDA pins of the MCP47CXBXX devices

are open-drain configurations. These pins require a

pull-up resistor, as shown in Figure 8-2.

SCL

SDA

1

2

3

4

5

6

7

8

9

The pull-up resistor values (R₁and R₂) for SCL and

SDA pins depend on the operating speed (standard,

fast and high speed) and loading capacitance of the I²C

bus line. A higher value of the pull-up resistor consumes

less power, but increases the signal transition time

(higher RC time constant) on the bus line; therefore, it

can limit the bus operating speed. The lower resistor

value, on the other hand, consumes higher power, but

allows higher operating speed. If the bus line has higher

capacitance due to long metal traces or multiple device

connections to the bus line, a smaller pull-up resistor is

needed to compensate for the long RC time constant.

The pull-up resistor is typically chosen between 1 k

and 10 kranges for Standard and Fast modes, and

less than 1 kfor High-Speed mode.

A6 A5 A4 A3 A2 A1 A0

Address Bits

1

Start

Bit

Stop

Bit

R/W

Device

Response

FIGURE 8-1:

I²C Bus Connection Test.

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DS20006089B-page 85

MCP47CXBXX

8.2

Power Supply Considerations

V_DD

R₂

The power source should be as clean as possible. The

power supply to the device is also used for the DAC

voltage reference internally if the internal V_DDis

selected as the resistor ladder’s reference voltage

(VRxB:VRxA = 00).

R₁

V_DD

SDA

SCL

1

2

3

4

8

7

6

5

To MCU

C₁

C₂

V_REF

V_OUT0

V_OUT1

C₄

Optional

Any noise induced on the V_DDline can affect the DAC

performance. Typical applications will require a bypass

capacitor in order to filter out high-frequency noise on

the V_DDline. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC out-

put. The bypass capacitor helps to minimize the effect of

these noise sources on signal integrity. Figure 8-2

shows an example of using two bypass capacitors (a

10 µF tantalum capacitor and a 0.1 µF ceramic capaci-

tor) in parallel on the V_DDline. These capacitors should

be placed as close to the V_DDpin as possible (within

4 mm). If the application circuit has separate digital and

analog power supplies, the V_DDand V_SSpins of the

device should reside on the analog plane.

LAT/HVC

V_SS

Analog

Output

MCP47CVBX2

C₃

(a) Circuit when V_DDis selected as reference.

Note: V_DDis connected to the reference circuit internally.

V_DD

C₁

C₂

R₂

R₁

V_DD

SDA

SCL

1

2

3

4

8

7

V_REF

To MCU

V_REF

V_OUT0

V_OUT1

C₅

Optional

Analog

Output

C₃

Optional

C₆

6

5

LAT/HVC

V_SS

MCP47CVBX2

C₄

(b) Circuit when external reference is used.

2

R and R are I C pull-up resistors:

1

2

R and R :

1

2

5 k-10 k for f

100 kHz to 400 kHz

3.4 MHz

=

SCL

~700 for f

SCL

C : 0.1 µF capacitor

Ceramic

1

C : 10 µF capacitor

Tantalum

2

C : ~ 0.1 µF

Optional to reduce noise in

3

V

OUT

C : 0.1 µF capacitor

Ceramic

Tantalum

Ceramic

=

4

C : 10 µF capacitor

5

C : 0.1 µF capacitor

6

FIGURE 8-2:

Example Circuit.

DS20006089B-page 86

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MCP47CXBXX

Using an external Voltage Reference (V_REF) is an

option if the external reference is available with the

desired output voltage range. However, when using a

low-voltage reference voltage, occasionally the noise

floor causes an SNR error that is intolerable. Using a

voltage divider method is another option, and provides

some advantages when external voltage reference

needs to be very low, or when the desired output

voltage is not available. In this case, a larger value

reference voltage is used, while two resistors scale the

output range down to the precise desired level.

8.3

Application Examples

The MCP47CXBXX devices are rail-to-rail output

DACs designed to operate with a V_DDrange of 2.7V to

5.5V. The internal output amplifier is robust enough to

drive common, small signal loads directly, thus

eliminating the cost and size of the external buffers for

most applications. The user can use the gain of 1 or 2

of the output op amp by setting the Configuration

register bits. The internal V_DDor an external reference

can be used. There are various user options and easy-

to-use features that make the devices suitable for

various modern DAC applications.

Figure 8-3 illustrates this concept. A bypass capacitor

on the output of the voltage divider plays a critical

function in attenuating the output noise of the DAC and

the induced noise from the environment.

Application examples include:

• Decreasing Output Step-Size

• Building a “Window” DAC

• Bipolar Operation

V_DD

• Selectable Gain and Offset Bipolar Voltage Output

• Designing a Double Precision DAC

• Building Programmable Current Source

• Serial Interface Communication Times

• Software I²C Interface Reset Sequence

• Power Supply Considerations

• Layout Considerations

Optional

R_SENSE

V_REFV_DD

V_CC

+

V_OUT

R₁

V_TRIP

Comp.

V_CC

MCP47CVBXX

V_O

R₂

C₁

-

8.3.1

DC SET POINT OR CALIBRATION

I²C

2-Wire

A common application for the devices is a digitally

controlled set point and/or calibration of variable

parameters, such as sensor offset or slope. For

example, the MCP47CVB2X provides 4096 output

steps. If the voltage reference is 4.096V (where Gx = 0),

the LSb size is 1 mV. If a smaller output step-size is

desired, a lower external voltage reference is needed.

FIGURE 8-3:

or Threshold Calibration.

Example Circuit of Set Point

EQUATION 8-1: _OUTAND V_TRIP

V

CALCULATIONS

8.3.1.1

Decreasing Output Step-Size

DAC Register Value

V

_OUT= V_REF• G •

2^N

If the application is calibrating the bias voltage of a

diode or transistor, a bias voltage range of 0.8V may be

desired, with about 200 µV resolution per step. Two

common methods to achieve small step-size are to use

a lower V_REFpin voltage or a voltage divider on the

DAC’s output.

R









2

V

= V

--------------------



trip

OUT

R + R



2

1

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DS20006089B-page 87

MCP47CXBXX

8.3.1.2

Building a “Window” DAC

8.4

Bipolar Operation

When calibrating a set point or threshold of a sensor,

typically only a small portion of the DAC output range is

utilized. If the LSb size is adequate enough to meet the

application’s accuracy needs, the unused range is

sacrificed without consequences. If greater accuracy is

needed, then the output range will need to be reduced

to increase the resolution around the desired threshold.

Bipolar operation is achievable by utilizing an external

operational amplifier. This configuration is desirable

due to the wide variety and availability of op amps. This

allows a general purpose DAC, with its cost and

availability advantages, to meet almost any desired

output voltage range, power and noise performance.

Figure 8-5 illustrates a simple bipolar voltage source

configuration. R₁and R₂allow the gain to be selected,

while R₃and R₄shift the DAC's output to a selected

offset. Note that R4 can be tied to V_DDinstead of V_SSif

a higher offset is desired.

If the threshold is not near V_REF, 2 • V_REFor V_SS, then

creating a “window” around the threshold has several

advantages. One simple method to create this “window”

is to use a voltage divider network with a pull-up and

pull-down resistor. Figure 8-4 and Figure 8-6 illustrate

this concept.

Optional

V_REFV_DD

V_CC+

R₃

V_OUT

V_OA+

C₁

Optional

V_O

V_CC

+

MCP47CVBXX

R_SENSE

V_REFV_DD

V_CC

+

R₄

R₃

I²C

2-Wire

V_CC

-

V_O

R₁

V_TRIP

C₁

Comp.

V_CC

MCP47CVBXX

V_OUT

R₂

V_CC

-

V_IN

I²C

2-Wire

R₁

-

FIGURE 8-5:

Voltage Source Example Circuit.

Digitally Controlled Bipolar

FIGURE 8-4:

Single-Supply “Window” DAC.

_OUTAND V_TRIP

EQUATION 8-2:

V

EQUATION 8-3: _OUT, V_OA+ AND V_O

V

CALCULATIONS

DAC Register Value

2^N

V_OUT= V_REF• G •

DAC Register Value

V_OUT= V_REF• G •

2^N

V

R

+ V

R

OUT 23

23 1

V

= --------------------------------------------------

V_OUT• R₄

R₃+ R₄

TRIP

R + R

1

23

V_OA+

=

R₂R₃

R₂₃= ------------------

R₂+ R₃

R₂

R₁

R₂

R₁

Thevenin

Equivalent

V_O= V_OA+• (1 +

) – V_DD• (

)

V_CC+R₂ + V_CC-R₃

V₂₃= ------------------------------------------------------

R₂+ R₃

R₁

V_OUT

V_TRIP

R₂₃

V₂₃

DS20006089B-page 88

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

8.5

Selectable Gain and Offset Bipolar

Voltage Output

Optional

V_CC

+

In some applications, precision digital control of the

output range is desirable. Figure 8-6 illustrates how to

use the DAC devices to achieve this in a bipolar or

single-supply application.

Optional

V_REFV_DD

R₅

V_CC

+

This circuit is typically used for linearizing a sensor

whose slope and offset varies.

R₃

V_OA+

C₁

V_OUT

MCP47CVBXX

V_O

The equation to design a bipolar “window” DAC would

be utilized if R₃, R₄and R₅are populated.

R₄

V_CC

I²C

2-Wire

V_CC

-

8.5.1

BIPOLAR DAC EXAMPLE

R₂

An output step-size of 1 mV, with an output range of

±2.05V, is desired for a particular application.

V_IN

R₁

Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V

Step 2: Calculate the resolution needed:

4.1V/1 mV = 4100

C₁= 0.1 µF

Bipolar Voltage Source with

FIGURE 8-6:

Since 2¹²= 4096, 12-bit resolution is desired

Selectable Gain and Offset.

Step 3: The amplifier gain (R₂/R₁), multiplied by

full-scale V_OUT(4.096V), must be equal to

the desired minimum output to achieve bipo-

lar operation. Since any gain can be realized

by choosing resistor values (R₁+ R₂), the

EQUATION 8-6:

V_OUT, V_OA+ AND V_O

CALCULATIONS

DAC Register Value

V_OUT= V_REF• G •

2^N

_OUT• R₄+ V_CC-• R₅

R₃+ R₄

V_REFvalue must be selected first. If a V_REF

of 4.096V is used, solve for the amplifier’s

gain by setting the DAC to 0, knowing that

the output needs to be -2.05V.

V

V_OA+

=

R₂

R₁

The equation can be simplified to:

V_O= V_OA+• (1 +

) – V_IN• (

)

R₁

EQUATION 8-4:

Offset Adjust Gain Adjust

–R₂

R₂

----- = --

R₁2

–2.05

4.096V

1

-------- = ----------------

R₁

EQUATION 8-7:

BIPOLAR “WINDOW” DAC

If R₁= 20 k and R₂= 10 k, the gain will be 0.5.

USING R₄AND R₅

V_CC+R₄+ V_CC-R₅

Thevenin

Equivalent

Step 4: Next, solve for R₃and R₄by setting the

DAC to 4096, knowing that the output

needs to be +2.05V.

V₄₅= --------------------------------------------

R₄+ R₅

V_OUTR₄₅+ V₄₅R₃

V_IN+= --------------------------------------------

R₃+ R₄₅

EQUATION 8-5:

R₄

2.05V + 0.5  4.096V

2

3

R₄R₅

----------------------- = ------------------------------------------------------- = --

R₄₅= ------------------

R₄+ R₅

R₃+ R₄

1.5  4.096V

If R₄= 20 k, then R₃= 10 k.

R₂











V_O= V

1 + ----- – V -----

^A

^IN+



R₁

Offset Adjust Gain Adjust

 2018-2019 Microchip Technology Inc.

DS20006089B-page 89

MCP47CXBXX

8.6

Designing a Double Precision

DAC

8.7

Building Programmable Current

Source

Figure 8-7 shows an example design of a single-supply

voltage output capable of up to 24-bit resolution. This

requires two 12-bit DACs. This design is simply a

voltage divider with a buffered output.

Figure 8-8 shows an example of building

a

programmable current source using a voltage follower.

The current sensor resistor is used to convert the DAC

voltage output into a digitally-selectable current source.

As an example, if a similar application to the one

developed in Section 8.5.1 “Bipolar DAC Example”

required a resolution of 1 µV instead of 1 mV, and a

range of 0V to 4.1V, then 12-bit resolution would not be

adequate.

The smaller R_SENSEis, the less power is dissipated

across it. However, this also reduces the resolution that

the current can be controlled at.

V_DD

(or V_REF

Step1: Calculate the resolution needed:

Optional

)

4.1V/1 µV = 4.1 x 10⁶

V_REFV_DD

Since 2²²= 4.2 x 10⁶, a 22-bit resolution is

desired. Since DNL = ±1.0 LSb, this design

can be attempted with the 12-bit DAC.

Load

V_CC

+

V_OUT

I_L

MCP47CVBXX

Step2: Since DAC1’s V_OUT1has a resolution of

1 mV, its output only needs to be “pulled”

1/1000 to meet the 1 µV target. Dividing

V_OUT0by 1000 would allow the application

to compensate for DAC1’s DNL error.

I_b

V_CC

-

I²C

2-Wire

I_L

R_SENSE

Step3: If R₂is 100, then R₁needs to be 100 k.

I_b= ----



Step4: The resulting transfer function is shown in

V_OUT

I_L= --------------  ------------

R_sense + 1



Equation 8-8.

Where: Common Emitter Current Gain

Optional

V_REFV_DD

FIGURE 8-8:

Digitally-Controlled Current

Source.

V_OUT0

MCP47CVBX2

8.8

Serial Interface Communication

Times

(DAC0)

R₁

I²C

2-Wire

V_CC

+

Table 7-1 shows the time/frequency of the supported

operations of the I²C serial interface for the different

serial interface operational frequencies. This, along

with the V_OUToutput performance (such as slew rate),

would be used to determine your application’s Volatile

DAC register update rate.

V_OUT

Optional

V_REFV_DD

0.1 µF

V_CC

-

R₂

V_OUT1

MCP47CVBX2

(DAC1)

I²C

2-Wire

FIGURE 8-7:

Simple Double Precision

DAC Using MCP47CVBX2.

EQUATION 8-8: _OUTCALCULATION

V_OUT0R + V

V

R

*

1

*

2

OUT1

V_OUT

=

R₁+ R₂

Where:

V_OUT0= (V_REF Gx  DAC0 Register Value)/4096

_OUT1= (V_REF Gx  DAC1 Register Value)/4096

Gx = Selected Op Amp Gain

V

DS20006089B-page 90

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

The Stop bit terminates the current I²C bus activity. The

MCP47CXBXX waits to detect the next Start condition.

This sequence does not affect any other I²C devices

which may be on the bus, as they should disregard this

as an invalid command.

2

8.9

Software I C Interface Reset

Sequence

Note:

This technique is documented in AN1028,

“Recommended Usage of Microchip I²C

Serial EEPROM Devices” (DS01028).

8.10 Design Considerations

At times, it may become necessary to perform a

Software Reset sequence to ensure the MCP47CXBXX

device is in a correct and known I²C interface state. This

technique only resets the I²C state machine.

In the design of a system with the MCP47CXBXX

devices, the following considerations should be taken

into account:

This is useful if the MCP47CXBXX device powers up in

an incorrect state (due to excessive bus noise, etc.), or

if the Master device is reset during communication.

Figure 8-9 shows the communication sequence to

software reset the device.

• Power Supply Considerations

• Layout Considerations

8.10.1

POWER SUPPLY

CONSIDERATIONS

The typical application requires a bypass capacitor in

order to filter high-frequency noise, which can be

induced onto the power supply’s traces. The bypass

capacitor helps to minimize the effect of these noise

sources on signal integrity. Figure 8-10 illustrates an

appropriate bypass strategy.

S

‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’ ‘1’

Nine Bits of ‘1’

S

P

Start Bit

Stop Bit

Start

Bit

FIGURE 8-9:

Format.

Software Reset Sequence

In this example, the recommended bypass capacitor

value is 0.1 µF. This capacitor should be placed as close

(within 4 mm) to the device power pin (V_DD) as possible.

The first Start bit will cause the device to reset from a

state in which it is expecting to receive data from the

Master device. In this mode, the device is monitoring

the data bus in Receive mode and can detect if the

Start bit forces an internal Reset.

The power source supplying these devices should be

as clean as possible. If the application circuit has

separate digital and analog power supplies, V_DDand

V_SSshould reside on the analog plane.

The nine bits of ‘1’ are used to force a reset of those

devices that could not be reset by the previous Start bit.

This occurs only if the MCP47CXBXX is driving an A bit

on the I²C bus or is in Output mode (from a read

command) and is driving a data bit of ‘0’ onto the I²C

bus. In both of these cases, the previous Start bit could

not be generated due to the MCP47CXBXX holding the

bus low. By sending out nine ‘1’ bits, it is ensured that the

device will see an A bit (the Master device does not drive

the I²C bus low to Acknowledge the data sent by the

MCP47CXBXX), which also forces the MCP47CXBXX to

reset.

V_DD

0.1 µF

V_DD

0.1 µF

The second Start bit is sent to address the rare

possibility of an erroneous write. This could occur if the

Master device was reset while sending a write com-

mand to the MCP47CXBXX, and then as the Master

device returns to normal operation and issues a Start

condition, while the MCP47CXBXX is issuing an

Acknowledge. In this case, if the second Start bit is not

sent (and the Stop bit was sent), the MCP47CXBXX

could initiate a write cycle.

SCL

SDA

V_REF

V_OUT

Note:

The potential for this erroneous write

ONLY occurs if the Master device is reset

while sending a write command to the

MCP47CVBXX.

V_SS

Typical Microcontroller

V_SS

FIGURE 8-10:

Connections.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 91

MCP47CXBXX

8.10.2

LAYOUT CONSIDERATIONS

8.10.2.2

PCB Area Requirements

Several layout considerations may be applicable to

your application. These may include:

In some applications, PCB area is a criteria for device

selection. Table 8-1 shows the typical package

dimensions and area for the different package options.

• Noise

)

PACKAGE FOOTPRINT⁽¹

• PCB Area Requirements

TABLE 8-1:

Package

Package Footprint

8.10.2.1

Noise

Inductively coupled AC transients and digital switching

noise can degrade the input and output signal integrity,

potentially masking the MCP47CXBXX device’s perfor-

mance. Careful board layout minimizes these effects

and increases the Signal-to-Noise Ratio (SNR). Multi-

layer boards utilizing a low-inductance ground plane,

isolated inputs, isolated outputs and proper decoupling

are critical to achieving the performance that the silicon is

capable of providing. Particularly harsh environments

may require shielding of critical signals.

Dimensions

(mm)

Type

Code

Area (mm²)

Length Width

10 MSOP

10 DFN

16 QFN

UN

MF

MG

3.00

4.90

3.00

14.70

9.00

Note 1: Does not include recommended land

pattern dimensions. Dimensions are

typical values.

Separate digital and analog ground planes are

recommended. In this case, the V_SSpin and the ground

pins of the V_DDcapacitors should be terminated to the

analog ground plane.

Note:

Breadboards and wire-wrapped boards

are not recommended.

DS20006089B-page 92

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

9.2

Technical Documentation

9.0

DEVELOPMENT SUPPORT

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs and Design Guides. Table 9-2 lists

some of these documents.

Development support can be classified into two groups:

• Development Tools

• Technical Documentation

9.1

Development Tools

Several development tools are available to assist in your

design and evaluation of the MCP47CXBXX devices.

The currently available tools are shown in Table 9-1.

Figure 9-1 shows how the ADM00309 bond-out PCB

can be populated to easily evaluate the MCP47CXBXX

devices. Device evaluation can use the PICkit™ Serial

Analyzer to control the DAC Output registers and state

of the Configuration, Control and Status registers.

The ADM00309 boards may be purchased directly

from the Microchip web site at www.microchip.com.

TABLE 9-1:

DEVELOPMENT TOOLS⁽¹⁾

Board Name

Part #

Comment

MSOP-8 and MSOP-10 Evaluation Board

ADM00309

The MSOP-8 and MSOP-10 Evaluation Board is a

bond-out board that allows the system designer to

quickly evaluate the operation of Microchip

Technology’s devices in any of the following packages:

• MSOP (8/10-pin)

• DIP (10 pin)

Note 1: Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.

TABLE 9-2:

TECHNICAL DOCUMENTATION

Application

Note Number

Title

Literature #

AN1326

Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications

Signal Chain Design Guide

DS01326

DS21825

DS01005

—

Analog Solutions for Automotive Applications Design Guide

 2018-2019 Microchip Technology Inc.

DS20006089B-page 93

MCP47CXBXX

MCP47CVBXX in MSOP-10 Package

Installed in U1 Footprint

Connected to

Digital Ground

(DGND) Plane

Connected to

Digital Power (V_L) Plane

4.7k 

0 

V

SDA

SCL

A1

1.0µF

DD

A0

V

REF

V

SS

OUT0

0 

NC/V

LAT/HVC

OUT1

Two Wire Jumpers to Connect the

PICkit™ Serial Interface (I²C) to Device Pins

1 x 6 Male Header with 90° Right Angle

FIGURE 9-1:

MCP47CXBXX Evaluation Board Circuit Using ADM00309.

DS20006089B-page 94

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

10-Lead MSOP

Example

XXXXXX

47CV01

YWWNNN

935256

10-Lead DFN (3x3 mm)

Example

Part Number

Code

MCP47CVB01-E/MF

MCP47CVB11-E/MF

MCP47CVB21-E/MF

MCP47CVB02-E/MF

MCP47CVB12-E/MF

MCP47CVB22-E/MF

MCP47CMB01-E/MF

MCP47CMB11-E/MF

MCP47CMB21-E/MF

MCP47CMB02-E/MF

MCP47CMB12-E/MF

MCP47CMB22-E/MF

BAJU

BAJX

BAJZ

BAJV

BAJY

BAKA

BAJV

BAJQ

BAJS

BAJP

BAJR

BAJT

XXXX

YYWW

NNN

PIN 1

BAJU

1935

256

PIN 1

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

e

3

*

)

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 95

MCP47CXBXX

16-Lead QFN (3x3 mm)

Example

Part Number

Code

PIN 1

XXX

AAD

MCP47CVB02-E/MG

MCP47CVB12-E/MG

MCP47CVB22-E/MG

MCP47CMB02-E/MG

MCP47CMB12-E/MG

MCP47CMB22-E/MG

AAD

AAE

AAF

AAA

AAB

AAC

XYYW

WNNN

1935

256

Note:

For MCP47CVB02, MCP47CVB12, MCP47CVB22, MCP47CMB02, MCP47CMB12 and MCP47CMB22)

devices.

DS20006089B-page 96

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

UN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2018-2019 Microchip Technology Inc.

DS20006089B-page 97

MCP47CXBXX

UN

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006089B-page 98

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

10-Lead Plastic Micro Small Outline Package (UN) [MSOP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2018-2019 Microchip Technology Inc.

DS20006089B-page 99

MCP47CXBXX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006089B-page 100

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2018-2019 Microchip Technology Inc.

DS20006089B-page 101

MCP47CXBXX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006089B-page 102

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2018-2019 Microchip Technology Inc.

DS20006089B-page 103

MCP47CXBXX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

DS20006089B-page 104

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2018-2019 Microchip Technology Inc.

DS20006089B-page 105

MCP47CXBXX

NOTES:

DS20006089B-page 106

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

APPENDIX A: REVISION HISTORY

Revision B (June 2019)

• Corrected the Internal Band Gap voltage

throughout the document.

• Updated the Block Diagrams.

• Updated DC Characteristics table.

• Added Section 1.1.2, Latch Pin (LAT) Timing.

• Updated Figure 1-3, Figure 1-4 and Figure 4-1.

• Updated Table 1-3, Table 1-5, Table 3-2 and

Table 4-1.

• Updated Section 3.5 “Latch/High-Voltage

Command Pin (LAT/HVC)”.

• Updated Section 4.2.2 “Nonvolatile Register

Memory (MTP)”.

• Updated Section 5.2.3 “Using an External V_REF

Source in Buffered Mode”.

• Updated Section 5.3.2 “Output Voltage”.

• Various typographical edits.

Revision A (September 2018)

• Original release of this document.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 107

MCP47CXBXX

NOTES:

DS20006089B-page 108

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

The I²C protocol supports two addressing modes:

• 7-Bit Slave Addressing

2

APPENDIX B: I C SERIAL

INTERFACE

• 10-Bit Slave Addressing (allows more devices on

the I²C bus)

This I²C is a two-wire interface that allows multiple

devices to be connected to the two-wire bus. Figure B-1

shows a typical I²C interface connection.

Only 7-Bit Slave Addressing will be discussed in this

section.

The I²C serial protocol allows multiple Master devices

on the I²C bus. This is referred to as “Multi-Master”. For

this, all Master devices must support Multi-Master

operation. In this configuration, all Master devices mon-

itor their communication. If they detect that they wish to

transmit a bit that is a logic high, but is detected as a

logic low (some other Master device driving), they “get

off” the bus. That is, they stop their communication and

continue to listen to determine if the communication is

directed towards them.

The I²C serial protocol only defines the field types, field

lengths, timings, etc., of a frame. The frame content

defines the behavior of the device. For details on the

frame content (commands/data), refer to Section 7.0,

Device Commands.

Typical I²C Interface Connections

Slave

Master

SCL

SDA

SCL

SDA

Other Devices

Typical I²C Interface.

FIGURE B-1:

B.1

Overview

A device that sends data onto the bus is defined as a

transmitter and a device receiving data is defined as a

receiver. The bus has to be controlled by a Master

device which generates the Serial Clock (SCL), con-

trols the bus access and generates the Start and Stop

conditions. Devices that do not generate a serial clock

work as Slave devices. Both Master and Slave can

operate as transmitter or receiver, but the Master

device determines which mode is activated. Communi-

cation is initiated by the Master (microcontroller), which

sends the Start bit followed by the Slave address byte.

The first byte transmitted is always the Slave address

byte, which contains the device code, the address bits

and the R/W bit.

The I²C serial protocol defines some commands, called

“General Call Addressing”, which allow the Master

device to communicate to all Slave devices on the I²C

bus.

Note:

Refer to the “NXP Specification

#UM10204”, Rev. 06, April 2014

4

document for more details on the

I²C specifications.

The I²C interface specifies different communication bit

rates. These are referred to as Standard, Fast or High-

Speed modes and the MCP47CXBXX supports these

three modes. The clock rates (bit rate) of these modes

are:

• Standard mode: Up to 100 kHz (kbit/s)

• Fast mode: Up to 400 kHz (kbit/s)

• High-Speed mode (HS mode): Up to 3.4 MHz

(Mbit/s)

 2018-2019 Microchip Technology Inc.

DS20006089B-page 109

MCP47CXBXX

B.3.1.2

Data Bit

B.2

Signal Descriptions

The I²C interface uses two pins (signals). These are:

The SDA signal may change state while the SCL signal

is low. While the SCL signal is high, the SDA signal

MUST be stable (see Figure B-3).

• SDA (Serial Data)

• SCL (Serial Clock)

B.2.1

SERIAL DATA (SDA)

1^stBit

2^ndBit

SDA

The Serial Data (SDA) signal is the data signal of the

device. The value on this pin is latched on the rising

edge of the SCL signal when the signal is an input.

SCL

Data Bit

With the exception of the Start (Restart) and Stop con-

ditions, the high or low state of the SDA pin can only

change when the clock signal on the SCL pin is low.

During the high period of the clock, the SDA pin’s value

(high or low) must be stable. Changes in the SDA pin’s

value while the SCL pin is high will be interpreted as a

Start or a Stop condition.

FIGURE B-3:

Data Bit.

B.3.1.3

Acknowledge (A) Bit

The A bit (see Figure B-4) is typically a response from

the receiving device to the transmitting device.

Depending on the context of the transfer sequence, the

A bit may indicate different things. Typically, the Slave

device will supply an A response after the Start bit and

eight “data” bits have been received. An A bit has the

SDA signal low, while the A bit has the SDA signal high.

B.2.2

SERIAL CLOCK (SCL)

The Serial Clock (SCL) signal is the clock signal of the

device. The rising edge of the SCL signal latches the

value on the SDA pin.

Depending on the Clock Rate mode, the interface will

display different characteristics.

SDA

SCL

D0

A

9

2

8

B.3

I C Operation

B.3.1

I²C BIT STATES AND SEQUENCE

FIGURE B-4:

Acknowledge Waveform.

Figure B-8 shows the I²C transfer sequence, while

Figure B-7 shows the bit definitions. The serial clock is

generated by the Master. The following definitions are

used for the bit states:

Table B-1 shows some of the conditions where the

Slave device issues the A or Not A (A).

If an error condition occurs (such as an A instead of A),

then a Start bit must be issued to reset the command

state machine.

• Start Bit (S)

• Data Bit

• Acknowledge (A) Bit (driven low)/

No Acknowledge (A) bit (not driven low)

• Repeated Start Bit (Sr)

• Stop Bit (P)

TABLE B-1:

MCP47CXBXX A/A

RESPONSES

Acknowledge

Bit Response

Event

Comment

B.3.1.1

Start Bit

General Call

A

The Start bit (see Figure B-2) indicates the beginning of

a data transfer sequence. The Start bit is defined as the

SDA signal falling when the SCL signal is “high”.

Slave Address

Valid

Slave Address

Not Valid

A

1^stBit

2^ndBit

Bus Collision

N/A

I²C module resets or is

a “Don’t Care” if the

collision occurs on the

Master’s “Start bit”

SDA

SCL

S

FIGURE B-2:

Start Bit.

DS20006089B-page 110

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

B.3.1.4

Repeated Start Bit

B.3.1.5

Stop Bit

The Repeated Start bit (see Figure B-5) indicates the

current Master device wishes to continue communicat-

ing with the current Slave device without releasing the

I²C bus. The Repeated Start condition is the same as

the Start condition, except that the Repeated Start bit

follows a Start bit (with the Data bits + A bit) and not a

Stop bit.

The Stop bit (see Figure B-6) Indicates the end of the

I²C data transfer sequence. The Stop bit is defined as

the SDA signal rising when the SCL signal is “high”.

A Stop bit should reset the I²C interface of the Slave

device.

The Start bit is the beginning of a data transfer

sequence and is defined as the SDA signal falling when

the SCL signal is “high”.

SDA

SCL

A/A

P

Note 1: A bus collision during the Repeated Start

condition occurs if:

FIGURE B-6:

Stop Condition Receive or

• SDA is sampled low when SCL goes

from low-to-high.

Transmit Mode.

B.3.2

CLOCK STRETCHING

• SCL goes low before SDA is

asserted low. This may indicate that

another Master is attempting to

transmit a data ‘1’.

“Clock Stretching” is something the receiving device

can do, to allow additional time to “respond” to the

“data” that has been received.

B.3.3

ABORTING A TRANSMISSION

If any part of the I²C transmission does not meet the

command format, it is aborted. This can be intentionally

accomplished with a Start or Stop condition. This is done

so that noisy transmissions (usually an extra Start or Stop

condition) are aborted before they corrupt the device.

1st Bit

SDA

SCL

Sr = Repeated Start

FIGURE B-5:

Repeated Start Condition

Waveform.

SDA

SCL

S

1^stBit 2^ndBit 3^rdBit 4^thBit 5^thBit 6^thBit 7^thBit 8^thBit

A/A

P

FIGURE B-7:

SDA

Typical 8-Bit I²C Waveform Format.

SCL

Start

Condition

Data Allowed

to Change

Data or

A Valid

Stop

Condition

FIGURE B-8:

I²C Data States and Bit Sequence.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 111

MCP47CXBXX

a special address byte following the Start bit. This byte

is referred to as the High-Speed Master Mode Code

(HSMMC).

B.3.4

SLOPE CONTROL

As the device transitions from High-Speed (HS) mode to

Fats (FS) mode, the slope control parameter will change

from the HS specification to the FS specification.

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

For FS and HS modes, the device has a spike

suppression and a Schmitt Trigger at SDA and SCL

inputs.

The Master code is sent as follows:

1. Start condition (S).

B.3.5

DEVICE ADDRESSING

2. High-Speed Master Mode Code (‘0000 1xxx’);

the ‘xxx’ bits are unique to the HS mode Master.

The I²C Slave address control byte is the first byte

received following the Start condition from the Master

device. This byte has seven bits to specify the Slave

address and the read/write control bit.

Figure B-9 shows the I²C Slave address byte format,

which contains the seven address bits and

Read/Write (R/W) bit.

3. No Acknowledge (A).

After switching to HS mode, the next transferred byte is

the I²C control byte, which specifies the device to com-

municate with, and any number of data bytes plus

Acknowledgments. The Master device can then either

issue a Repeated Start bit to address a different device

(at high speed) or a Stop bit to return to fast/standard

bus speed. After the Stop bit, any other Master device

(in a Multi-Master system) can arbitrate for the I²C bus.

a

Acknowledge Bit

Start Bit

Read/Write Bit

See Figure B-10 for an illustration of an HS mode

command sequence.

A6 A5 A4 A3 A2 A1 A0 R/W ACK

For more information on the HS mode, or other I²C

7-Bit Slave Address

Address Byte

modes, refer to the “NXP I²C Specification”.

I²C Slave Address Control

B.3.6.1

Slope Control

FIGURE B-9:

Byte.

The slope control on the SDA output is different

between the Fast/Standard Speed and the High-Speed

Clock modes of the interface.

B.3.6

HS MODE

The I²C specification requires that a High-Speed mode

device must be ‘activated’ to operate in High-Speed

(3.4 Mbit/s) mode. This is done by the Master sending

B.3.6.2

Pulse Gobbler

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes <10 ns during HS mode.

F/S Mode

HS Mode

P

F/S Mode

S

0000 1xxx’b

A Sr Slave Address R/W A

Data

A/A

HS Mode Continues

Sr Slave Address R/W

Control Byte

A

HS Select Byte

Control Byte

Command/Data Byte(s)

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

P = Stop bit (Stop condition terminates HS mode)

FIGURE B-10:

HS Mode Sequence.

DS20006089B-page 112

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

For details on the operation of the MCP47CXBXX

device’s general call commands, see Section 7.3

“General Call Commands”.

B.3.7

GENERAL CALL

The general call is a method the Master device can use

to communicate with all other Slave devices. In a Multi-

Master application, the other Master devices are

operating in Slave mode. The general call address has

two documented formats. These are shown in

Figure B-11.

Note:

Only one general call command per issue

of the general call control byte. Any

additional general call commands are

ignored and Not Acknowledged.

The I²C specification documents three 7-bit command

bytes.

The I²C specification does not allow ‘00000000’ (00h)

in the second byte. Also, the ‘00000100’ and

‘00000110’ functionalities are defined by the specifica-

tion. Lastly, a data byte with a ‘1’ in the LSb indicates a

“Hardware General Call”.

Second Byte

S

0

A

x

0

A

P

General Call Address

7-Bit Command

Reserved 7-Bit Commands (by I²C Specification – “NXP Specification # UM10204”, Rev. 06, 4 April 2014)

‘0000 011’b’ – Reset and Write Programmable Part of Slave Address by Hardware

‘0000 010’b’ – Write Programmable Part of Slave Address by Hardware

The Following is a “Hardware General Call” Format

Second Byte

n Occurrences of (Data + A)

S

0

A

x

1

A

x

A P

General Call Address

Master Address

This Indicates a “Hardware General Call”

FIGURE B-11:

General Call Formats.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 113

MCP47CXBXX

NOTES:

DS20006089B-page 114

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

C.3

Monotonic Operation

APPENDIX C: TERMINOLOGY

The monotonic operation means that the device’s

Output Voltage (V_OUT) increases with every one code

step (LSb) increment (from V_SSto the DAC’s reference

voltage (V_DDor V_REF)).

C.1

Resolution

The resolution is the number of DAC output states that

divide the Full-Scale Range (FSR). For the 12-bit DAC,

the resolution is 2¹², meaning the DAC code ranges

from 0 to 4095.

V_S64

40h

3Fh

Note:

When there are 2^Nresistors in the resistor

ladder and 2^Ntap points, the full-scale

DAC register code is the resistor element

(1 LSb) from the source reference voltage

(V_DDor V_REF).

V_S63

3Eh

V_S3

03h

02h

V_S1

C.2

Least Significant Bit (LSb)

This is the voltage difference between two successive

codes. For a given output voltage range, it is divided by

the resolution of the device (Equation C-1). The range

may be V_DD(or V_REF) to V_SS(ideal); the DAC register

codes across the linear range of the output driver

(Measured 1) or full scale to zero scale (Measured 2).

V_S0

01h

00h

V_W(@ Tap)

n = ?

V_W

=

V_Sn+ V_{ZS(@ Tap 0)}

n = 0

EQUATION C-1:

LSb VOLTAGE

CALCULATION

Voltage (V_W~= V_OUT

)

FIGURE C-1:

V_W(V_OUT).

Ideal

V_DD

V_{LSbIDEAL}= ---------- or ------------

2^N2^N

V_REF

Measured 1

V_OUT(@4032)– V_OUT(@64)

V_{LSbMeasured}= --------------------------------------------------------------

4032 – 64

Measured 2

V_OUT(@FS)– V_OUT(@ZS)

V_LSb= ----------------------------------------------------------

2

^N– 1

2^N= 4096 (MCP47CVB2X)

= 1024 (MCP47CVB1X)

= 256 (MCP47CVB0X)

 2018-2019 Microchip Technology Inc.

DS20006089B-page 115

MCP47CXBXX

C.4

Full-Scale Error (E )

C.6

Total Unadjusted Error (E )

T

FS

The Full-Scale Error, E_FS(see Figure C-3), is the error

on the V_OUTpin relative to the expected V_OUTvoltage

(theoretical) for the maximum device DAC register

code (code FFFh for 12-bit, code 3FFh for 10-bit and

code FFh for 8-bit); see Equation C-2. The error is

dependent on the resistive load on the V_OUTpin (and

where that load is tied to, such as V_SSor V_DD). For

loads (to V_SS) greater than specified, the full-scale

error will be greater.

The Total Unadjusted Error (E_T) is the difference

between the ideal and measured V_OUTvoltage. Typi-

cally, calibration of the output voltage is implemented

to improve the system’s performance.

The error in bits is determined by the theortical voltage

step-size to give an error in LSb.

Equation C-4 shows the total unadjusted error

calculation.

The error in bits is determined by the theoretical voltage

step-size to give an error in LSb.

EQUATION C-4:

TOTAL UNADJUSTED

ERROR CALCULATION

V_{OUT_Actual(@code)}– V_{OUT_Ideal(@code)}

E_T= -------------------------------------------------------------------------------------------------

V_{LSbIdeal}



EQUATION C-2:

FULL-SCALE ERROR

V_OUT(@FS)– V_IDEAL(@FS)

E_FS= ---------------------------------------------------------------

V_{LSbIDEAL}

Where:

E_Tis expressed in LSb.

E

is expressed in LSb.

FS

V_{OUT_Actual(@code)}= The measured DAC output

V

is the V

voltage when the DAC

OUT

OUT(@FS)

voltage at the specified

code

register code is at full scale.

is the ideal output voltage when the

V

IDEAL(@FS)

DAC register code is at full scale.

is the theoretical voltage step-size.

V_{OUT_Ideal(@code)}= The calculated DAC output

voltage at the specified

V

LSb(IDEAL)

code (code * V_LSb(Ideal)

)

V_LSb(Ideal)= V_REF/# Steps

C.5

Zero-Scale Error (E )

ZS

12-bit = V_REF/4096

10-bit = V_REF/1024

8-bit = V_REF/256

The Zero-Scale Error, E_ZS(see Figure C-2), is the differ-

ence between the ideal and measured V_OUTvoltage with

the DAC register code equal to 000h (Equation C-3). The

error is dependent on the resistive load on the V_OUTpin

(and where that load is tied to, such as V_SSor V_DD). For

loads (to V_DD) greater than specified, the zero-scale

error is greater.

The error in bits is determined by the theoretical voltage

step-size to give an error in LSb.

EQUATION C-3:

ZERO-SCALE ERROR

V_OUT(@ZS)

E_ZS= ---------------------------

V_LSb(IDEAL)

Where:

E

is expressed in LSb.

FS

V

is the V

voltage when the DAC

OUT

OUT(@ZS)

register code is at zero scale.

is the theoretical voltage step-size.

V

LSb(IDEAL)

DS20006089B-page 116

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

C.7

Offset Error (E

)

OS

Gain Error (E )

G

The Offset Error (E_OS) is the delta voltage of the V_OUT

voltage from the ideal output voltage at the specified

code. This code is specified where the output amplifier

is in the linear operating range; for the MCP47CXBXX,

we specify code 100 (decimal). Offset error does not

include gain error, which is illustrated in Figure C-2.

(@ code = 4032)

V_REF

Actual

Transfer

Function

Full-Scale

Error (E

)

FS

This error is expressed in mV. Offset error can be

negative or positive. The error can be calibrated by

software in application circuits.

Ideal Transfer

Function Shifted by

Offset Error

(crosses at start of

defined linear range)

Ideal Transfer

Function

0

64

4032 4095

DAC Input Code

FIGURE C-3:

Error Example.

Gain Error and Full-Scale

Actual

Transfer

Function

EQUATION C-5:

GAIN ERROR EXAMPLE

V_OUT(@4032)– V_OS– V_{OUT_Ideal(@4032)}



E_G= ---------------------------------------------------------------------------------------------------- * 1 0 0

V_{Full-Scale Range}

Zero-Scale

Ideal Transfer

Function

Error (E

)

ZS

0

64

4032

DAC Input Code

Where:

Offset

Error (E

E_Gis expressed in % of Full-Scale Range (FSR).

)

OS

V_OUT(@4032)= The measured DAC output

voltage at the specified code

FIGURE C-2:

Offset Error (Zero Gain

V_{OUT_Ideal(@4032)}= The calculated DAC output

voltage at the specified code

Error).

(4032 * V_LSb(Ideal)

)

C.8

Offset Error Drift (E

)

OSD

V_OS= Measured offset voltage

The Offset Error Drift (E_OSD) is the variation in offset

error due to a change in ambient temperature. The off-

set error drift is typically expressed in ppm/°C or µV/°C.

V_{Full-Scale Range}= Expected full-scale output

value (such as the V_REF

voltage)

C.9

Gain Error (E )

G

C.10 Gain Error Drift (E

)

GD

Gain Error (E_G) is a calculation based on the ideal

slope using the voltage boundaries for the linear range

of the output driver (e.g., code 100 and code 4000); see

Figure C-3). The gain error calculation nullifies the

device’s offset error.

The Gain Error Drift (E_GD) is the variation in gain error

due to a change in ambient temperature. The gain error

drift is typically expressed in ppm/°C (of Full-Scale

Range).

The gain error indicates how well the slope of the actual

transfer function matches the slope of the ideal transfer

function. The gain error is usually expressed as a percent

of Full-Scale Range (% of FSR) or in LSb. FSR is the

ideal full-scale voltage of the DAC (see Equation C-5).

 2018-2019 Microchip Technology Inc.

DS20006089B-page 117

MCP47CXBXX

C.11 Integral Nonlinearity (INL)

C.12 Differential Nonlinearity (DNL)

The Integral Nonlinearity (INL) error is the maximum

deviation of an actual transfer function, from an ideal

transfer function (straight line), passing through the

defined end-points of the DAC transfer function (after

Offset and Gain Errors have been removed).

The Differential Nonlinearity (DNL) error (see

Figure C-5) is the measure of step-size between codes

in an actual transfer function. The ideal step-size

between codes is 1 LSb. A DNL error of zero would

imply that every code is exactly 1 LSb wide. If the DNL

error is less than 1 LSb, the DAC ensures monotonic

output and no missing codes. Equation C-7 shows how

to calculate the DNL error between any two adjacent

codes in LSb.

For the MCP47CXBXX, INL is calculated using the

defined end points, DAC code 64 and code 4032. INL

can be expressed as a percentage of Full-Scale Range

(FSR) or in LSb. INL is also called relative accuracy.

Equation C-6 shows how to calculate the INL error in

LSb and Figure C-4 shows an example of INL accuracy.

EQUATION C-7:

DNL ERROR

V_{OUT(code = n+1)}– V_{OUT(code = n)}



Positive INL means a V_OUTvoltage higher than the

ideal one. Negative INL means a V_OUTvoltage lower

than the ideal one.

E_DNL= ----------------------------------------------------------------------------------- – 1

V_{LSbMeasured}

Where:

EQUATION C-6:

INL ERROR

DNL is expressed in LSb.

V_OUT– V_{Calc_Ideal}



V_{OUT(Code = n)}= The measured DAC output

voltage with a given DAC

register code

E_INL= --------------------------------------------------

V_{LSbMeasured}

Where:

V_{LSb(Measured)}= For Measured:

(V_OUT(4032)– V_OUT(64))/3968

INL is expressed in LSb

V_{Calc_Ideal}= Code * V_{LSb(Measured)}+ V_OS

V_{OUT(Code = n)}= The measured DAC output

voltage with a given DAC

register code

7

V_{LSb(Measured)}= For Measured:

(V_OUT(4032)– V_OUT(64))/3968

DNL = 0.5 LSb

6

5

V_OS= Measured offset voltage

DNL = 2 LSb

Analog

Output

4

(LSb)

3

7

INL = < -1 LSb

2

1

6

INL = -1 LSb

5

0

4

Analog

000 001 010 011 100 101 110 111

Output

(LSb)

INL = 0.5 LSb

3

DAC Input Code

Ideal Transfer Function

Actual Transfer Function

2

1

0

FIGURE C-5:

DNL Accuracy.

000 001 010 011 100 101 110 111

DAC Input Code

Ideal Transfer Function

Actual Transfer Function

FIGURE C-4:

INL Accuracy.

DS20006089B-page 118

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

C.13 Settling Time

C.17 Power Supply Sensitivity (PSS)

The settling time is the time delay required for the V_OUT

voltage to settle into its new output value. This time is

measured from the start of code transition to when the

PSS indicates how the output of the DAC is affected by

changes in the supply voltage. PSS is the ratio of the

change in V_OUTto a change in V_DDfor mid-scale output

of the DAC. The V_OUTis measured while the V_DDis

varied from 5.5V to 2.7V as a step (V_REFvoltage held

constant), and expressed in %/%, which is the %

change of the DAC output voltage with respect to the %

change of the V_DDvoltage.

V_OUTvoltage is within the specified accuracy.

For the MCP47CXBXX, the settling time is a measure

of the time delay until the V_OUTvoltage reaches within

0.5 LSb of its final value, when the Volatile DAC register

changes from 1/4 to 3/4 of the Full-Scale Range (12-bit

device: 400h to C00h).

EQUATION C-8:

PSS CALCULATION

C.14 Major Code Transition Glitch

V_OUT(@5.5V)– V_OUT(@2.7V)  V_OUT(@5.5V)

PSS = ---------------------------------------------------------------------------------------------------------

5.5V – 2.7V  5.5V

Major code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes the state. It is normally spec-

ified as the area of the glitch in nV-Sec and is measured

when the digital code is changed by 1 LSb at the major

carry transition (Example: 011...111 to 100...

000, or 100...000to 011...111).

Where:

PSS is expressed in %/%.

V_OUT(@5.5V)= The measured DAC output

voltage with V_DD= 5.5V

V_OUT(@2.7V)= The measured DAC output

voltage with V_DD= 2.7V

C.15 Digital Feedthrough

The digital feedthrough is the glitch that appears at the

analog output caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec and is measured with a full-scale change

(Example: all ‘0’s to all ‘1’s and vice versa) on the digital

input pins. The digital feedthrough is measured when

the DAC is not being written to the output register.

C.18 Power Supply Rejection Ratio

(PSRR)

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in V_OUTto a change in V_DDfor full-scale

output of the DAC. The V_OUTis measured while the

V_DDis varied ±10% (V_REFvoltage held constant) and

expressed in dB or µV/V.

C.16 -3 dB Bandwidth

This is the frequency of the signal at the V_REFpin that

causes the voltage at the V_OUTpin to fall to -3 dB from

a static value on the V_REFpin. The output decreases

due to the RC characteristics of the resistor ladder and

the characteristics of the output buffer.

C.19

V

Temperature Coefficient

OUT

The V_OUTtemperature coefficient quantifies the error in

the resistor ladder’s resistance ratio (DAC register

code value) and output buffer due to temperature drift.

C.20 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies the

error in the end-to-end output voltage (nominal output

voltage, V_OUT) due to temperature drift. For a DAC, this

error is typically not an issue due to the ratiometric

aspect of the output.

C.21 Noise Spectral Density

The noise spectral density is a measurement of the

device’s internally generated random noise and is

characterized as a spectral density (voltage per √Hz).

It is measured by loading the DAC to the mid-scale

value and measuring the noise at the V_OUTpin. It is

measured in nV/√Hz.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 119

MCP47CXBXX

NOTES:

DS20006089B-page 120

 2018-2019 Microchip Technology Inc.

MCP47CXBXX

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

(1)

-

PART NO.

Device

X

/XX

a) MCP47CVB01-E/MF: 1 LSb INL Voltage Output

Digital-to-Analog Converter,

Tape and Temperature Package

Reel Range

8-Bit Resolution, Extended

Temperature, 10LD DFN, with

Volatile Memory.

b) MCP47CVB01T-E/MF: 1 LSb INL Voltage Output

Digital-to-Analog Converter,

Device:

MCP47CXBXX: 1 LSb INL Voltage Output Digital-to-Analog

Converters with I²C Interface,

8-Bit Resolution, Tape and Reel,

Extended Temperature,

10LD DFN, with Volatile Memory.

8/10/12-Bit Resolution, Single/Dual Outputs

and Volatile/MTP Memory

a) MCP47CVB12-E/MG: 1 LSb INL Voltage Output

Digital-to-Analog Converter,

Tape and Reel:

T

E

= Tape and Reel

10-Bit Resolution, Extended

Temperature, 16LD QFN, with

Volatile Memory.

Temperature

Range:

= -40°C to +125°C (Extended)

b) MCP47CVB12T-E/MG: 1 LSb INL Voltage Output

Digital-to-Analog Converter,

10-Bit Resolution, Tape and Reel,

Extended Temperature,

16LD QFN, with Volatile Memory.

Package:

MF = Plastic Dual Flat, No Lead Package (DFN),

3x3x0.9 mm, 10-Lead

MG = Plastic Quad Flat, No Lead Package (QFN),

3x3x0.9 mm, 16-Lead

a) MCP47CMB21-E/UN: 1 LSb INL Voltage Output

Digital-to-Analog Converter,

UN = Plastic Micro Small Outline Package (MSOP),

10-Lead

12-Bit Resolution, Extended

Temperature, 10LD MSOP, with

Nonvolatile Memory.

b) MCP47CMB21T-E/UN: 1 LSb INL Voltage Output

Digital-to-Analog Converter,

12-Bit Resolution, Tape and Reel,

Extended Temperature,

10LD MSOP, with Nonvolatile

Memory.

Note 1: Tape and Reel identifier only appears in the

catalog part number description. This identifier is

used for ordering purposes and is not printed on

the device package. Check with your Microchip

Sales Office for package availability with the Tape

and Reel option.

 2018-2019 Microchip Technology Inc.

DS20006089B-page 121

MCP47CXBXX

NOTES:

DS20006089B-page 122

 2018-2019 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA

are registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company,

EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,

IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision

Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,

SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, Vite, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

Reserved.

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

ISBN: 978-1-5224-4636-1

 2018-2019 Microchip Technology Inc.

DS20006089B-page 123

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DS20006089B-page 124

 2018-2019 Microchip Technology Inc.

05/14/19


型号：	MCP47CVB22-EMF
厂家：	MICROCHIP
描述：	8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with I2C Interface
文件：	总124页 (文件大小：9049K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP47CVB22-EMF [MICROCHIP]

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