MCP48CXBX2 [MICROCHIP]
8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with SPI Interface;
| 型号： | MCP48CXBX2 |
| 厂家： | 
MICROCHIP |
| 描述： | 8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL Single/Dual Voltage Outputs with SPI Interface |
| 文件： | 总106页 (文件大小：8854K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP48CXBXX
8/10/12-Bit Digital-to-Analog Converters, 1 LSb INL
Single/Dual Voltage Outputs with SPI Interface
Features
Package Types
• Memory Options:
MCP48CXBX1 (Single)
- Volatile Memory: MCP48CVBXX
- Nonvolatile Memory: MCP48CMBXX
• Operating Voltage Range:
MSOP-10, DFN-10 (3 x 3)
V
DD
1
2
3
10
SDI
CS
REF
OUT
- 2.7V to 5.5V – Full specifications
- 1.8V to 2.7V – Reduced device specifications
• Output Voltage Resolutions:
9 SCK
V
SDO
8
V
4
7 V
SS
-
8-Bit: MCP48CXB0X (256 steps)
NC 5
6 LAT/HVC
- 10-Bit: MCP48CXB1X (1024 steps)
- 12-Bit: MCP48CXB2X (4096 steps)
• Nonvolatile Memory (MTP) Size: 32 Locations
• 1 LSb Integral Nonlinearity (INL) Specification
• DAC Voltage Reference Source Options:
- Device VDD
QFN-16 (3 x 3)
CS
1
2
3
4
12
SCK
V
V
11 SDO
REF
- External VREF pin (buffered or unbuffered)
- Internal band gap (1.214V typical)
• Output Gain Options:
(1)
17 EP
10 V
OUT
SS
NC
9
LAT/HVC
- 1x (Unity)
- 2x (available when not using internal VDD as
voltage source)
MCP48CXBX2 (Dual)
MSOP-10, DFN-10 (3 x 3)
• Power-on/Brown-out Reset (POR/BOR)
Protection
• Power-Down Modes:
V
DD
1
2
3
10
SDI
- Disconnects output buffer (High-Impedance)
CS
9 SCK
- Selection of VOUT pull-down resistors
(100 k or 1 k)
• SPI Interface:
V
SDO
8
REF
V
OUT0
OUT1
4
5
7 V
SS
(2)
V
6 LAT/HVC
- Supports ‘00’ and ‘11’ modes
- 50 MHz write speed
- 25 MHz read speed
• Package Types:
QFN-16 (3 x 3)
- Dual: 16-lead 3 x 3 QFN, 10-lead MSOP,
10-lead 3 x 3 DFN
CS
1
2
3
4
12
SCK
- Single: 16-lead 3 x 3 QFN, 10-lead MSOP,
10-lead 3 x 3 DFN
V
V
11 SDO
REF0
(1)
17 EP
10 V
OUT0
SS
• Extended Temperature Range: -40°C to +125°C
V
9
LAT0/HVC
REF1
Note 1: Exposed pad (substrate paddle).
2: This pin’s signal can be connected to DAC0
and/or DAC1.
2019 Microchip Technology Inc.
DS20006160A-page 1
MCP48CXBXX
When the VREF pin is used with an external voltage
reference, the user can select between a gain of 1 or 2
and can have the reference buffer enabled or disabled.
When the gain is 2, the VREF pin voltage should be
limited to a maximum of VDD/2.
General Description
The MCP48CXBXX are single and dual-channel 8-bit,
10-bit, and 12-bit buffered voltage output
Digital-to-Analog Converters (DAC), with volatile or
MTP memory and an SPI serial interface.
These devices have a four-wire SPI-compatible serial
interface with speeds up to 50 MHz for write and
25 MHz for read operations.
The MTP memory can be written by the user up to 32
times, for each specific register. It requires
a
high-voltage level on the HVC pin, typically 7.5V, in
order to successfully program the desired memory
location. The nonvolatile memory includes power-up
output values, device configuration registers and
general purpose memory.
Applications
• Set Point or Offset Trimming
• Sensor Calibration
The VREF pin, the device VDD or the internal band gap
voltage can be selected as the DAC’s reference
voltage. When VDD is selected, VDD is internally
connected to the DAC reference circuit.
• Low-Power Portable Instrumentation
• PC Peripherals
• Data Acquisition Systems
MCP48CVBX1 Block Diagram (Single-Channel Output)
VDD
VSS
Memory
Power-up/Brown-out Control
VOLATILE (4 x 16)
DAC0
VREF
POWER-DOWN
GAIN
STATUS
SCK
SDI
SPI Serial Interface Module
and Control Logic
(WiperLock™ Technology)
SDO
CS
NONVOLATILE (13 x 16)
DAC0
VREF
VIHH
LAT/HVC
POWER-DOWN
GAIN
LAT0
WIPERLOCK™
VDD
PD1:PD0 and
VREF1:VREF0
VBG
Band gap
1.214V
GAIN
VREF1:VREF0
OPAMP
VOUT0
VREF0
VDD
PD1:PD0
VREF1:VREF0
Note 1: Available only on specific packages.
DS20006160A-page 2
2019 Microchip Technology Inc.
MCP48CXBXX
MCP48CVBX2 Block Diagram (Dual-Channel Output)
VDD
VSS
Memory
Power-up/Brown-out Control
VOLATILE (5 x 16)
DAC0 and DAC1
VREF
POWER-DOWN
GAIN
SCK
SDI
SPI Serial Interface Module
and Control Logic
(WiperLock™ Technology)
SDO
CS
STATUS
NONVOLATILE (14 x 16)
DAC0 and DAC1
VREF
VIHH
LAT0/HVC
POWER-DOWN
GAIN
LAT0
WIPERLOCK™
VDD
PD1:PD0 and
VREF1:VREF0
VBG
Band gap
1.214V
GAIN
VREF1:VREF0
OPAMP
VOUT0
(3)
VREF0
VDD
PD1:PD0
VREF1:VREF0
LAT1(2)
LAT0(2)
VDD
PD1:PD0 and
VREF1:VREF0
GAIN
VBG
VREF1:VREF0
OPAMP
VOUT1
(3)
VREF1
VDD
PD1:PD0
VREF1:VREF0
Note 1: Available only on specific packages.
2: On dual output devices, except those in a QFN16 package, the LAT0 pin is internally connected to LAT1
input of DAC1.
3: On dual output devices, except those in a QFN16 package, the VREF0 pin is internally connected to
VREF1 input of DAC1.
2019 Microchip Technology Inc.
DS20006160A-page 3
MCP48CXBXX
Family Device Features
DAC Output
POR/BOR
Setting(1)
Device
Package Type
MCP48CVB01
MCP48CVB11
MCP48CVB21
MSOP, QFN, DFN
MSOP, QFN, DFN
MSOP, QFN, DFN
QFN
1
1
1
2
2
2
2
2
2
1
1
1
2
2
2
2
2
2
8
7Fh
1FFh
7FFh
7Fh
1
1
1
2
1
2
1
2
1
1
1
1
2
1
2
1
2
1
1
1
1
2
1
2
1
2
1
1
1
1
2
1
2
1
2
1
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
RAM
MTP
MTP
MTP
MTP
MTP
MTP
MTP
MTP
MTP
—
—
—
—
—
—
—
—
—
8
10
12
8
MCP48CVB02
MCP48CVB12
MCP48CVB22
MSOP, DFN
QFN
8
7Fh
10
10
12
12
8
1FFh
1FFh
7FFh
7FFh
7Fh
MSOP, DFN
QFN
MSOP, DFN
MSOP, QFN, DFN
MSOP, QFN, DFN
MSOP, QFN, DFN
QFN
MCP48CMB01
MCP48CMB11
MCP48CMB21
10
12
8
1FFh
7FFh
7Fh
8
8
8
MCP48CMB02
MCP48CMB12
MCP48CMB22
MSOP, DFN
QFN
8
7Fh
8
10
10
12
12
1FFh
1FFh
7FFh
7FFh
8
MSOP, DFN
QFN
8
8
MSOP, DFN
8
Note 1: The factory default value.
2: Each nonvolatile memory location can be written 32 times. For subsequent writes to the MTP, the device
will ignore the commands and the memory will not be modified.
3: If the product is a dual device and the package has only one LAT pin, it is associated with both DAC0 and
DAC1.
DS20006160A-page 4
2019 Microchip Technology Inc.
MCP48CXBXX
1.0
ELECTRICAL CHARACTERISTICS
(†)
Absolute Maximum Ratings
Voltage on VDD with respect to VSS ......................................................................................................... -0.6V to +6.5V
Voltage on all pins with respect to VSS ............................................................................................... -0.6V to VDD+0.3V
Input Clamp Current, IIK (VI < 0, VI > VDD, VI > VPP on HV pins) ........................................................................±20 mA
Output Clamp Current, IOK (VO < 0 or VO > VDD) .................................................................................................±20 mA
Maximum Current out of VSS pin
(Single)..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum Current into VDD pin
(Single)..........................................................................................................50 mA
(Dual)...........................................................................................................100 mA
Maximum Current sourced by the VOUT pin............................................................................................................20 mA
Maximum Current sunk by the VOUT pin.................................................................................................................20 mA
Maximum Current source/sunk by the VREF(0) pin (in Band Gap mode) ................................................................20 mA
Maximum Current sunk by the VREFx pin (when VREF is in Unbuffered mode) .....................................................175 µA
Maximum Current sourced by the VREFx pin............................................................................................................20 µA
Maximum Current sunk by the VREF pin ................................................................................................................125 µA
Maximum Output Current sunk by SDO Output pin................................................................................................25 mA
Maximum Output Current sourced by SDO Output pin...........................................................................................25 mA
Total Power Dissipation(1) ....................................................................................................................................400 mW
ESD Protection on all pins±6 kV (HBM)
±400V (MM)
±2 kV (CDM)
Latch-Up (per JEDEC JESD78A) at +125°C .....................................................................................................±100 mA
Storage Temperature ..............................................................................................................................-65°C to +150°C
Ambient Temperature with power applied ..............................................................................................-55°C to +125°C
Soldering Temperature of leads (10 seconds) ...................................................................................................... +300°C
Maximum Junction Temperature (TJ).................................................................................................................... +150°C
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at those or any other conditions above those indicated in the
operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods
may affect device reliability.
Note 1: Power dissipation is calculated as follows:
PDIS = VDD x {IDD - IOH} + {(VDD – VOH) x IOH} + (VOL x IOL
)
2019 Microchip Technology Inc.
DS20006160A-page 5
MCP48CXBXX
DC CHARACTERISTICS
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Supply Voltage
Sym.
Min.
Typ.
Max.
Units
Conditions
VDD
2.7
1.8
—
—
5.5
2.7
V
V
DAC operation (reduced analog
specifications) and Serial Interface
VPOR
VDD Voltage
(rising) to ensure device
Power-on Reset
—
—
—
1.75
1.61
V
V
RAM retention voltage (VRAM) < VPOR
VDD voltages greater than the VPOR limit
ensure that the device is out of reset.
VDD Voltage
VBOR
VRAM
RAM retention voltage (VRAM) < VBOR
(falling) to ensure device
Brown-out Reset
VDD Rise Rate to ensure
Power-on Reset
VDDRR
(Note 3)
V/ms
Power-on Reset to
Output-Driven Delay
(Note 2)
TPOR2OD
—
—
—
—
130
145
µs VDD rising, VDD > VPOR
Single Output
µs VDD rising, VDD > VPOR
Dual Output
Note 2
Note 3
This parameter is ensured by characterization.
POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
DS20006160A-page 6
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min. Typ. Max.
Units
Conditions
Serial Interface Active
Supply Current
IDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
250
700
µA
Single 1 MHz
10 MHz(2)
VRxB:VRxA = ‘10’(4)
VOUT is unloaded,
VREF = VDD = 5.5V
Volatile DAC
,
2300
350
50 MHz(2)
µA
Dual
1 MHz
register = Midscale
800
10 MHz(2)
50 MHz(2)
2400
160
µA
µA
Single Serial Interface Inactive
VRxB:VRxA = ‘10’, VREF = VDD = 5.5V
SCK = SDI = VSS
OUT is unloaded,
280
Dual
,
V
Volatile DAC register = Midscale
LAT/HVC Pin
IDD(MTP_WR)
—
—
—
6.40
3.80
mA
µA
—
Serial Interface Inactive
(MTP Write Active),
VRxB:VRxA = ‘10’ (valid for all modes)
VDD = 5.5V, LAT/HVC = VIHH
Write all ‘1’s to nonvolatile DAC0,
VOUT pins are unloaded.
Write Current(2)
,
Power-Down
Current
IDDP
0.56
—
PDxB:PDxA = ‘01’(5)
VRxB:VRxA = ‘10’,
VOUT not connected
,
Note 2
Note 4
Note 5
This parameter is ensured by characterization.
Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
2019 Microchip Technology Inc.
DS20006160A-page 7
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Resistor Ladder
Resistance(6)
RL
63.9
71
78.1
k
VRxB:VRxA = ‘10’,
VREF = VDD
Resolution
(# of Resistors and
# of Taps)
N
256
1024
4096
Taps
Taps
Taps
8-bit No Missing Codes
10-bit No Missing Codes
12-bit No Missing Codes
(see B.1 “Resolution”)
Nominal VOUT Match(10)
|VOUT - VOUTMEAN
|
—
—
0.016
3
0.3
—
%
1.8V VDD 5.5V(2)
/VOUTMEAN
VOUT Tempco(2)
(see B.19 “VOUT
Temperature
VOUT/T
ppm/°C Code = Mid-scale
(7Fh, 1FFh or 7FFh),
VRxB:VRxA =
Coefficient”)
‘00’, ‘10’, and ‘11’
VREF Pin
VREF
VSS
—
VDD
V
1.8V VDD 5.5V(1)
Input Voltage Range
Note 1
Note 2
Note 6
This parameter is ensured by design.
This parameter is ensured by characterization.
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP48CXBX2), this is the effective resistance of each resistor ladder. The
resistance measurement is one of the two resistor ladders measured in parallel.
Note 10
Variation of one output voltage to mean output voltage for dual devices only.
DS20006160A-page 8
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Zero-Scale Error
(Code = 000h)
(see B.5
“Zero-Scale
Error (EZS)”)
EZS
—
—
0.375
LSb 8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
—
—
—
—
1.5
6
LSb 10-bit VRxB:VRxA = ‘10’, G = ‘0’,
REF = VDD, No Load.
V
LSb 12-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
LSb
LSb
mV
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
Performance Curves”(2)
See Section 2.0 “Typical
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
Performance Curves”(2)
Offset Error
(see B.7 “Offset
Error (EOS)”)
EOS
VOSTC
EFS
-6
±0.7
+6
VRxB:VRxA = ‘10’, Gx = ‘0’, No Load
8-bit: Code = 4; 10-bit: Code = 16;
12-bit: Code = 64
Offset Voltage
Temperature
Coefficient(2, 9)
—
±5
—
µV/°C
Full-Scale Error
(see B.4
—
—
—
—
—
—
2.5
9
LSb 8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
“Full-Scale
Error (EFS)”)
LSb 10-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
35
LSb 12-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
LSb
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
Performance Curves”(2)
See Section 2.0 “Typical
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
Performance Curves”(2)
Gain Error
EG
-1
-1
-1
—
±0.1
±0.1
±0.1
-6
+1
+1
+1
—
% of
FSR 8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
Code = 252,
VREF = VDD, No Load
(see B.9 “Gain
Error (EG)”)(7)
% of
VRxB:VRxA = ‘10’, G = ‘0’,
FSR 10-bit Code = 1008,
VREF = VDD, No Load
VRxB:VRxA = ‘10’, G = ‘0’,
FSR 12-bit Code = 4032,
VREF = VDD, No Load
% of
Gain-Error Drift(2) G/°C
(see B.10 “Gain
Error Drift
ppm/°C
(EGD)”)(9)
Note 2 This parameter is ensured by characterization.
Note 7 This gain error does not include the offset error.
Note 9 Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
2019 Microchip Technology Inc.
DS20006160A-page 9
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
TotalUnadjustedError
(see B.6 “Total
Unadjusted Error
(ET)”)(2, 9)
ET
-2.5
—
0.75
LSb 8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
-9
—
—
3
LSb 10-bit VRxB:VRxA = ‘10’, G = ‘0’,
REF = VDD, No Load.
V
-35
12
LSb 12-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
Performance Curves”
VREF = 0.5 X VDD, No Load.
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
Performance Curves”
VDD = 1.8-5.5V, No Load.
Integral
INL
-0.10
-0.25
-1
—
—
—
+0.10
+0.25
+1
LSb 8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
Nonlinearity
(see B.11 “Integral
Nonlinearity
(INL)”)(9)
LSb 10-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
LSb 12-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
VREF = 0.5 X VDD, No Load.
Performance Curves”(2)
See Section 2.0 “Typical
LSb
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
Performance Curves”(2)
Differential
Nonlinearity
(see B.12
“Differential
Nonlinearity
(DNL)”)(9)
DNL
-0.1
-0.25
-1.0
—
—
—
+0.1
+0.25
+1.0
LSb 8-bit
VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
LSb 10-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
LSb 12-bit VRxB:VRxA = ‘10’, G = ‘0’,
VREF = VDD, No Load.
See Section 2.0 “Typical
LSb
LSb
VRxB:VRxA = ‘10’, G = ‘1’,
REF = 0.5 X VDD, No Load.
Performance Curves”(2)
V
See Section 2.0 “Typical
VRxB:VRxA = ‘01’, G = ‘0’, G = ‘1’,
VDD = 1.8-5.5V, No Load.
Performance Curves”(2)
Note 2 This parameter is ensured by characterization.
Note 9 Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
DS20006160A-page 10
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
-3 dB Bandwidth
(see B.16 “-3 dB
Bandwidth”)
BW
—
60
—
kHz
VREF = 3.0V+/-2V,
VRxB:VRxA = ‘10’, Gx = ‘0’
—
35
—
kHz
VREF = 3.5V+/-1.5V,
VRxB:VRxA = ‘10’, Gx = ‘1’
Output Amplifier (Op Amp)
Phase Margin(1)
PM
—
—
—
—
58
—
—
—
—
°C
R =
L
Slew Rate
SR
—
0.15
130
320
V/µs RL = 2 k
Load Regulation
µV/mA 1 mA < I < 6 mA
µV/mA -6 mA < I < -1 mA
VDD = 5.5V,
DAC code =
Midscale
Short-Circuit Current
ISC_OA
6
6
10
10
16
14
14
—
mA
mA
µs
Short to
VSS
DAC code = Full Scale
DAC code = Zero Scale
Short to
VDD
Settling Time(8)
tSETTLING
—
RL = 2 k
Internal Band Gap
Band Gap Voltage
Short Circuit Current
VBG
1.180 1.214
1.260
14
V
1.8 < VDD < 5.5V
Short to VSS
ISC_BG
6
6
10
10
16
mA
mA
14
Short to VDD
Band Gap Voltage
Temperature
Coefficient
VBGTC
—
—
ppm/°C 1.8V VDD 5.5V
Band Gap mode VREF
pin load regulation
IBG
—
—
30
—
—
μV/mA 1 mA < I < 6 mA
μV/mA -6 mA < I < -1 mA
VDD = 5.5V,
DAC code = Mid-
scale
390
Note 1
Note 8
This parameter is ensured by design.
Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a
12-bit device.)
2019 Microchip Technology Inc.
DS20006160A-page 11
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
External Reference (VREF
)
Input Range(1)
VREF
CREF
RL
VSS
—
—
VDD – 0.04
—
V
VRxB:VRxA = ‘10’
(Unbuffered mode)
Input Capacitance
Input Impedance
29
pF
k
VRxB:VRxA = ‘10’
(Unbuffered mode)
See Resistor Ladder Resistance(6)
2.7V <= VDD <= 5.5V
VRxB:VRxA = ‘10’
VREF = VDD
Current through
VREF
IVREF
THD
—
—
—
172.15
—
μA
Mathematically from RVREF(min)
spec (at 5.5V)
(1)
Total Harmonic
Distortion(1)
-76
dB
VREF = 2.048V ± 0.1V,
VRxB:VRxA = ‘10’, Gx = ‘0’,
Frequency = 1 kHz
Dynamic Performance
Major Code
—
—
—
—
10
<2
—
—
nV-s 1 LSb change around major carry
(7FFh to 800h)
Transition Glitch (see
B.14 “Major-Code
Transition Glitch”)
Digital Feedthrough
(see B.15 “Digital
Feed-Through”)
nV-s
Note 1
Note 6
This parameter is ensured by design.
Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP48CXBX2), this is the effective resistance of each resistor ladder. The
resistance measurement is one of the two resistor ladders measured in parallel.
DS20006160A-page 12
2019 Microchip Technology Inc.
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Digital Inputs/Outputs (CS, SDI, SDO, SCK, LATx)
Schmitt Trigger High-Input
Threshold
VIH
0.45 VDD
—
—
V
1.8V VDD 5.5V (Allows 2.7V
Digital VDD with 5.5V Analog VDD
or 1.8V Digital VDD with 3.0V
Analog VDD
)
Schmitt Trigger Low-Input
Threshold
VIL
—
—
—
0.2 VDD
—
V
V
Hysteresis of Schmitt Trig-
ger Inputs
VHYS
0.1 VDD
Output Low Voltage (SDO)
Output High Voltage (SDO)
Input Leakage Current
Pin Capacitance
VOL
VOH
VSS
0.7 VDD
-1
—
—
—
10
0.3 VDD
V
V
IOL = 200 µA
IOH = -200 µA
VDD
1
IIL
µA VIN = VDD and VIN = VSS
pF
CIN, COUT
—
—
RAM Value
Value Range
N
N
0h
0h
0h
—
—
—
FFh
3FFh
FFFh
hex
8-bit
hex 10-bit
hex 12-bit
DAC Register POR/BOR
Value
See Table 4-2
See Table 4-2
See Table 4-2
See Table 4-2
hex
8-bit
hex 10-bit
hex 12-bit
hex
PDCON Initial
Factory Setting
—
Power Requirements
Power Supply Sensitivity
(B.17 “Power-Supply
Sensitivity (PSS)”)
PSS
—
0.001
0.0035
%/% 8-bit Code = Midscale
10-bit
12-bit
2019 Microchip Technology Inc.
DS20006160A-page 13
MCP48CXBXX
DC CHARACTERISTICS (CONTINUED)
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VREF = +1.000V to VDD, VSS = 0V,
RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
Multi-Time Programming Memory (MTP)
MTP Programming
Voltage (Note 1)
VPG_MTP
VIHH
2.0
—
5.5
V
V
HVC = VIHH, -20°C TA +125°C
LAT/HVC pin Voltage for
MTP Programming
(High-Voltage
7.25
7.5
7.75V
The LAT/HVC pin will be at one of
the three input levels (VIL, VIH or
(1,11)
VIHH
)
Commands)(1)
The LAT/HVC pin must supply the
required MTP programming
current (up to 6.4 mA).
Writes Cycles
Data Retention
MTP Range
—
DRMTP
N
—
10
—
—
—
—
—
32(12)
—
Cycles Note 1
Years at +85°C(1)
0h
FFh
hex
hex
hex
hex
—
8-bit
0h
3FFh
FFFh
7FFFh
10-bit
0h
12-bit
0000h
All General Purpose Memory
Initial Factory Setting
N
See Table 4-2
MTP
tWC(MTP)
—
—
250
us
VDD = +2.0V to 5.5V,
-20°C TA +125°C
(Note 1)
Programming Write Cycle
Time
Note 1
This parameter is ensured by design.
Note 11
High voltage on the LAT/HVC pin must be limited to the command + programming time. After the
programming cycle, the LAT/HVC pin voltage must be returned to 5.5V or lower.
Note 12
After 32 MTP write cycles, writes are inhibited and the 32nd write value is retained (not corrupted).
DS20006160A-page 14
2019 Microchip Technology Inc.
MCP48CXBXX
DC Notes:
1. This parameter is ensured by design.
2. This parameter is ensured by characterization.
3. POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.
4. Supply current is independent of current through the resistor ladder in mode VRxB:VRxA = ‘10’.
5. The PDxB:PDxA = ‘01’, ‘10’, and ‘11’ configurations should have the same current.
6. Resistance is defined as the resistance between the VREF pin (mode VRxB:VRxA = ‘10’) to VSS pin. For
dual-channel devices (MCP48CXBX2), this is the effective resistance of each resistor ladder. The resistance
measurement is one of the two resistor ladders measured in parallel.
7. This gain error does not include the offset error.
8. Within 1/2 LSb of the final value, when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a 12-bit
device.)
9. Code range dependent on resolution: 8-bit, codes 4 to 252; 10-bit, codes 16 to 1008; 12-bit, codes 64 to 4032.
10. Variation of one output voltage to mean output voltage for dual devices only.
11. High voltage on the LAT/HVC pin must be limited to the command + programming time. After the programming
cycle, the LAT/HVC pin voltage must be returned to 5.5V or lower.
12. After 32 MTP write cycles, writes are inhibited and the 32nd write value is retained (not corrupted).
2019 Microchip Technology Inc.
DS20006160A-page 15
MCP48CXBXX
1.1
Timing Waveforms and Requirements
1.1.1
WIPER SETTLING TIME
± 0.5 LSb
New Value
Old Value
VOUT
FIGURE 1-1:
VOUT Settling Time Waveforms.
TABLE 1-1:
WIPER SETTLING TIMING
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym. Min. Typ. Max. Units
tS 16 µs
Conditions
V
OUT Settling Time
—
—
12-bit Code = 400h C00h; C00h 400h (Note 1)
(see B.13 “Settling
Time”)
Note 1: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR.
1.1.2 LATCH PIN (LAT) TIMING
LATx
SCK
Wx
t
LAT
FIGURE 1-2:
LAT Pin Waveforms.
TABLE 1-2:
LAT PIN TIMING
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym.
Min.
Typ.
Max.
Units
Conditions
LATx Pin Pulse Width
tLAT
20
—
—
ns
DS20006160A-page 16
2019 Microchip Technology Inc.
MCP48CXBXX
1.1.3
RESET AND POWER-DOWN TIMING
VPOR
VBOR
VDD
t
POR2SIA = tPOR2OD
tBORD
VOUT at High Z
VOUT
SPI Interface is operational
Power-on and Brown-out Reset Waveforms.
FIGURE 1-3:
24th bit
(Write
1st bit
(Next
24th bit
(Write
command) command)
command)
SCK
tPDE
tPDD
VOUT
FIGURE 1-4:
SPI Power-Down Waveforms.
TABLE 1-3:
RESET AND POWER-DOWN TIMING
Standard Operating Conditions (unless otherwise specified):
Operating Temperature: -40°C TA +125°C (Extended)
Timing Characteristics
All parameters apply across the specified operating ranges unless noted.
VDD = +2.7V to 5.5V, VSS = 0V, RL = 2 k from VOUT to GND, CL = 100 pF.
Typical specifications represent values for VDD = 5.5V, TA = +25°C.
Parameters
Sym. Min. Typ. Max. Units
Conditions
Power-on Reset Delay tPOR2SIA
(Note 1)
—
—
—
—
—
30
130
145
—
µs
Single VDD transitions from VDD(MIN) > VPOR
VOUT disabled to VOUT driven
Dual
Brown-out Reset Delay tBORD
µs
VDD transitions from VDD(normal operation) <
VBOR
VOUT driven to VOUT disabled
Power-Down Output
Enable Time Delay
TPDE
—
—
1.5
—
—
µs
µs
PDxB:PDxA = ‘11’, ‘10’, or ‘01’ “00” started from
the rising edge of the 24th SCK clock cycle;
Volatile DAC Register = FFFh, VOUT = 10 mV;
VOUT not connected.
Power-Down Output
Disable Time Delay
TPDD
0.025
PDxB:PDxA = “00” ‘11’, ‘10’, or ‘01’ started from
the rising edge of the 24th SCK clock cycle;
VOUT = VOUT - 10 mV;
VOUT not connected.
Note 1: This parameter is ensured by characterization.
2019 Microchip Technology Inc.
DS20006160A-page 17
MCP48CXBXX
1.2
SPI Mode Timing Waveforms and Requirements
V
IHH
89
V
V
V
IH
IH
Note: HVC pin must be at V
until MTP Write cycle completes
IHH
HVC
V
IH
IH
CS
V
IL
84
70
72
SCK
83
71
80
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
77
75, 76
MSb IN
74
LSb IN
73
FIGURE 1-5:
SPI Timing Waveform (Mode = ‘11’).
SPI REQUIREMENTS (MODE = ‘11’)
TABLE 1-4:
#
Characteristic(2)
Sym.
Min. Max. Units
Conditions
—
SCK Input Frequency
FSCK
—
25
MHz VDD = 2.7V to 5.5V - Read
command, CL = 20 pF
—
50
MHz VDD = 2.7V to 5.5V - Write
commands, CL = 20 pF
—
15
10
20
10
20
5
10
—
—
—
—
—
—
—
20
MHz VDD = 1.8V to 2.7V
ns
70 CS Active (VIL) to SCK Input
71 SCK Input High Time
TcsA2scH
TscH
ns
VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
72 SCK Input Low Time
TscL
ns
ns
ns
VDD = 1.8V to 2.7V
73 SDI Input Valid to SCK Edge (Setup Time)
74 SCK Edge to SDI Input Invalid (Hold Time)
77 CS Inactive (VIH) to SDO Output
High-Impedance
TDIV2scH
TscH2DIL
TcsH2DOZ
10
—
ns Note 1
80 SCK Edge to SDO Data Output Valid
83 SCK Edge to CS Inactive (VIH) (Hold Time)
84 CS Input High Time
TscL2DOV
TscH2csI
—
—
15
20
30
0
20
35
—
—
—
—
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
ns
ns
ns
VDD = 1.8V to 2.7V
TcsA2csI
—
89 Delay from HVC VIHH to First Command
Byte(1)
Note 1: This specification is ensured by design.
2: This parameter is ensured by characterization.
DS20006160A-page 18
2019 Microchip Technology Inc.
MCP48CXBXX
V
89
IHH
V
V
IH
IH
Note: HVC pin must be at V
until MTP Write cycle completes
IHH
HVC
CS
V
V
IH
IH
82
V
IL
84
70
SCK
83
80
71
72
MSb
BIT6 - - - - - -1
BIT6 - - - -1
LSb
SDO
SDI
75, 76
77
73
MSb IN
74
LSb IN
FIGURE 1-6:
SPI Timing Waveform (Mode = 00).
TABLE 1-5:
#
SPI REQUIREMENTS (MODE = 00)
Characteristic(2)
Sym.
Min. Max. Units
Conditions
—
SCK Input Frequency
FSCK
—
25
MHz VDD = 2.7V to 5.5V -
Read command,
CL = 20 pF
—
50
MHz VDD = 2.7V to 5.5V -
Write commands,
CL = 20 pF
—
15
10
20
10
20
5
10
—
—
—
—
—
—
—
20
MHz VDD = 1.8V to 2.7V
ns
70 CS Active (VIL or VIHH) to SCK Input
71 SCK Input High Time
TcsA2scH
TscH
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
72 SCK Input Low Time
TscL
ns
VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
73 SDI Input Valid to SCK Edge (Setup Time)
74 SCK Edge to SDI Input Invalid (Hold Time)
77 CS Inactive (VIH) to SDO Output
High-Impedance
TDIV2scH
TscH2DIL
TcsH2DOZ
ns
10
—
ns
ns Note 1
80 SCK Edge to SDO Data Output Valid
82 CS Active (VIL) to SDO Data Output Valid
83 SCK Edge to CS Inactive (VIH) (Hold Time)
84 CS Input High Time
TscL2DOV
TcsL2DOV
TscH2csI
—
—
—
—
15
20
30
0
20
35
20
35
—
—
—
—
ns VDD = 2.7V to 5.5V
ns VDD = 1.8V to 2.7V
ns 2.7V to 5.5V
ns 1.8V to 2.7V
ns VDD = 2.7V to 5.5V
ns
ns
ns
V
DD = 1.8V to 2.7V
TcsA2csI
—
89 Delay from HVC VIHH to First Command
Byte(1)
Note 1: This specification is ensured by design.
2: This parameter is ensured by characterization.
2019 Microchip Technology Inc.
DS20006160A-page 19
MCP48CXBXX
TEMPERATURE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters
Temperature Ranges
Sym.
Min.
Typ.
Max. Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
TA
TA
TA
-40
-40
-65
—
—
—
+125
+125
+150
°C
°C
°C
Note 1
Thermal Package Resistances
Thermal Resistance, 10L-MSOP
Thermal Resistance, 10L-DFN (3 x 3)
Thermal Resistance, 16L-QFN
JA
JA
JA
—
—
—
206
91
—
—
—
°C/W
°C/W
°C/W
58
Note 1: The MCP48CXBXX devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the Maximum Junction Temperature of
+150°C.
DS20006160A-page 20
2019 Microchip Technology Inc.
MCP48CXBXX
2.0
TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
2.1
Electrical Data
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-1:
Average Device Supply
FIGURE 2-4:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature - Active Interface,
VRxB:VRxA = ‘00’, (VDD Mode).
Current - Inactive Interface (SCK = VIH or VIL) vs.
Voltage and Temperature, VRxB:VRxA = ‘00’
(VDD Mode).
FIGURE 2-5:
Average Device Supply
FIGURE 2-2:
Average Device Supply
Current - Inactive Interface (SCK = VIH or VIL) vs.
Voltage and Temperature, VRxB:VRxA = ‘01’
(Band Gap Mode).
Current vs. FSCK Frequency, Voltage and
Temperature - Active Interface,
VRxB:VRxA = ‘01’ (Band Gap Mode).
FIGURE 2-3:
Average Device Supply
FIGURE 2-6:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature - Active Interface,
VRxB:VRxA = ‘11’ (VREF Buffered Mode).
Current - Inactive Interface (SCK = VIH or VIL)
vs. Voltage and Temperature, VRxB:VRxA = ‘11’
(VREF Buffered Mode).
2019 Microchip Technology Inc.
DS20006160A-page 21
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-7:
Average Device Supply
FIGURE 2-9:
Average Device Supply
Current vs. FSCK Frequency, Voltage and
Temperature - Active Interface,
VRxB:VRxA = ‘10’ (VREF Unbuffered Mode).
Current - Inactive Interface (SCK = VIH or VIL) vs.
Voltage and Temperature, VRxB:VRxA = ‘10’
(VREF Unbuffered Mode).
FIGURE 2-8:
Active Current (IDDA) (at 5.5V and
SCK = 50 MHz) vs. Temperature and DAC
Average Device Supply
F
Reference Voltage Mode.
DS20006160A-page 22
2019 Microchip Technology Inc.
MCP48CXBXX
2.2
Linearity Data
2.2.1
TOTAL UNADJUSTED ERROR (TUE) - MCP48CXB2X (12-BIT), VREF = VDD
(VRXB:VRXA = ‘00’), GAIN = 1X, CODE 64-4032
Note:
Unless otherwise indicated: TA = +25°C, VDD = 5.5V
FIGURE 2-10:
Total Unadjusted Error
FIGURE 2-13:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 5.5V.
(Dual-Channel - MCP48CXB22), VDD = 5.5V.
FIGURE 2-11:
Total Unadjusted Error
FIGURE 2-14:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 2.7V.
(Dual-Channel - MCP48CXB22), VDD = 2.7V.
FIGURE 2-12:
Total Unadjusted Error
FIGURE 2-15:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 1.8V.
(Dual-Channel - MCP48CXB22), VDD = 1.8V.
2019 Microchip Technology Inc.
DS20006160A-page 23
MCP48CXBXX
2.2.2
INTEGRAL NONLINEARITY (INL) - MCP48CXB2X (12-BIT), VREF = VDD (VRXB:VRXA = ‘00’),
GAIN = 1X, CODE 64-4032
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-16:
Temperature (Single-Channel - MCP48CXB21),
DD = 5.5V.
INL Error vs. DAC Code and
FIGURE 2-19:
Temperature (Dual-Channel - MCP48CXB22),
VDD = 5.5V.
INL Error vs. DAC Code and
V
FIGURE 2-17:
INL Error vs. DAC Code and
FIGURE 2-20:
INL Error vs. DAC Code and
Temperature (Single-Channel - MCP48CXB21),
VDD = 2.7V.
Temperature (Dual-Channel - MCP48CXB22),
VDD = 2.7V.
FIGURE 2-18:
INL Error vs. DAC Code and
FIGURE 2-21:
INL Error vs. DAC Code
Temperature (Single-Channel - MCP48CXB21),
VDD = 1.8V.
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 1.8V.
DS20006160A-page 24
2019 Microchip Technology Inc.
MCP48CXBXX
2.2.3
Note:
DIFFERENTIAL NONLINEARITY (DNL) - MCP48CXB2X (12-BIT), VREF = VDD
(VRXB:VRXA = ‘00’), GAIN = 1X, CODE 64 - 4032
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-22:
DNL Error vs. DAC Code
FIGURE 2-25:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
MCP48CXB21), VDD = 5.5V.
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 5.5V.
FIGURE 2-23:
DNL Error vs. DAC Code
FIGURE 2-26:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
MCP48CXB21), VDD = 2.7V.
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 2.7V.
FIGURE 2-24:
DNL Error vs. DAC Code
FIGURE 2-27:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
MCP48CXB21), VDD = 1.8V.
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 1.8V.
2019 Microchip Technology Inc.
DS20006160A-page 25
MCP48CXBXX
2.2.4
TOTAL UNADJUSTED ERROR (TUE) - MCP48CXB2X (12-BIT), EXTERNAL VREF = 0.5 VDD
(VRXB:VRXA = ‘10’), UNBUFFERED, CODE 64 - 4032
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-28:
Total Unadjusted Error
FIGURE 2-30:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21),
(VOUT) vs. DAC Code, and Temperature
(Dual-Channel - MCP48CXB22),
VREF = 0.5 x VDD = 2.75V, Gain = 2X.
VREF = 0.5 x VDD = 2.75V, Gain = 2X.
FIGURE 2-29:
Total Unadjusted Error
FIGURE 2-31:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21),
(VOUT) vs. DAC Code and Temperature
(Dual-Channel - MCP48CXB22),
VREF = 0.5 x VDD = 1.35V, Gain = 2X.
VREF = 0.5 x VDD = 1.35V, Gain = 2X.
DS20006160A-page 26
2019 Microchip Technology Inc.
MCP48CXBXX
2.2.5
Note:
INTEGRAL NONLINEARITY (INL) - MCP48CXB2X (12-BIT), EXTERNAL VREF = 0.5 VDD
(VRXB:VRXA = ‘10’), UNBUFFERED, CODE 64 - 4032
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-32:
Temperature (Single-Channel - MCP48CXB21),
REF = 0.5 x VDD = 2.75V, Gain = 2X.
INL Error vs. DAC Code and
FIGURE 2-34:
Temperature (Dual-Channel - MCP48CXB22),
VREF = 0.5 x VDD = 2.75V, Gain = 2X.
INL Error vs. DAC Code and
V
FIGURE 2-33:
Temperature (Single-Channel - MCP48CXB21),
VREF = 0.5 x VDD = 1.35V, Gain = 2X.
INL Error vs. DAC Code and
FIGURE 2-35:
Temperature (Dual-Channel - MCP48CXB22),
REF = 0.5 x VDD = 1.35V, Gain = 2X.
INL Error vs. DAC Code and
V
2019 Microchip Technology Inc.
DS20006160A-page 27
MCP48CXBXX
2.2.6
DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP48CXB2X (12-BIT), EXTERNAL
REF = 0.5 VDD (VRXB:VRXA = ‘10’), UNBUFFERED, CODE 64 - 4032
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
V
Note:
FIGURE 2-36:
DNL Error vs. DAC Code
FIGURE 2-38:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
MCP48CXB21), VDD = 5.5V,
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 5.5V,
VREF = 0.5 x VDD = 2.75V.
VREF = 0.5 x VDD = 2.75V.
FIGURE 2-37:
DNL Error vs. DAC Code
FIGURE 2-39:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
MCP48CXB21), VDD = 5.5V,
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 5.5V,
VREF = 0.5 x VDD = 1.35V.
VREF = 0.5 x VDD = 1.35V.
DS20006160A-page 28
2019 Microchip Technology Inc.
MCP48CXBXX
TOTAL UNADJUSTED ERROR (TUE) - MCP48CXB2X (12-BIT), VREF = INTERNAL BAND
2.2.7
GAP (VRXB:VRXA = ‘01’), CODE 64 - 4032
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-40:
Total Unadjusted Error
FIGURE 2-43:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 5.5V,
Gain = 1X.
(VOUT) vs. DAC Code and Temperature
(Dual-Channel - MCP48CXB22), VDD = 5.5V,
Gain = 1X.
FIGURE 2-41:
Total Unadjusted Error
FIGURE 2-44:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 5.5V,
Gain = 2X.
(VOUT) vs. DAC Code and Temperature
(Dual-Channel - MCP48CXB22), VDD = 5.5V,
Gain = 2X.
FIGURE 2-42:
Total Unadjusted Error
FIGURE 2-45:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 2.7V,
Gain = 1X.
(VOUT) vs. DAC Code and Temperature
(Dual-Channel - MCP48CXB22), VDD = 2.7V,
Gain = 1X.
2019 Microchip Technology Inc.
DS20006160A-page 29
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-46:
Total Unadjusted Error
FIGURE 2-49:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 2.7V,
Gain = 2X.
(VOUT) vs. DAC Code and Temperature
(Dual-Channel - MCP48CXB22), VDD = 2.7V,
Gain = 2X.
FIGURE 2-47:
Total Unadjusted Error
FIGURE 2-50:
Total Unadjusted Error
(VOUT) vs. DAC Code and Temperature
(Single-Channel - MCP48CXB21), VDD = 1.8V,
Gain = 1X.
(VOUT) vs. DAC Code and Temperature
(Dual-Channel - MCP48CXB22), VDD = 1.8V,
Gain = 1X.
FIGURE 2-48:
Total Unadjusted Error
FIGURE 2-51:
Total Unadjusted Error
(VOUT) vs. DAC Code, +25°C, Gain = 1X.
(VOUT) vs. DAC Code, +25°C, Gain = 2X.
DS20006160A-page 30
2019 Microchip Technology Inc.
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-52:
Total Unadjusted Error
(VOUT) vs. DAC Code, +25°C, Gain = 1X and 2X.
2019 Microchip Technology Inc.
DS20006160A-page 31
MCP48CXBXX
2.2.8
INTEGRAL NONLINEARITY ERROR (INL) - MCP48CXB2X (12-BIT), VREF = INTERNAL
BAND GAP (VRXB:VRXA = ‘01’), CODE 64-4032
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-53:
Temperature (Single-Channel - MCP48CXB21),
DD = 5.5V, Gain = 1X.
INL Error vs. DAC Code and
FIGURE 2-56:
Temperature (Dual-Channel - MCP48CXB22),
VDD = 5.5V, Gain = 1X.
INL Error vs. DAC Code and
V
FIGURE 2-54:
INL Error vs. DAC Code and
FIGURE 2-57:
INL Error vs. DAC Code and
Temperature (Single-Channel - MCP48CXB21),
VDD = 5.5V, Gain = 2X.
Temperature (Dual-Channel - MCP48CXB22),
VDD = 5.5V, Gain = 2X.
FIGURE 2-55:
INL Error vs. DAC Code and
FIGURE 2-58:
INL Error vs. DAC Code
Temperature (Single-Channel - MCP48CXB21),
VDD = 2.7V, Gain = 1X.
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 2.7V, Gain = 1X.
DS20006160A-page 32
2019 Microchip Technology Inc.
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-59:
Temperature (Single-Channel - MCP48CXB21),
DD = 2.7V, Gain = 2X.
INL Error vs. DAC Code and
FIGURE 2-62:
Temperature (Dual-Channel - MCP48CXB22),
VDD = 2.7V, Gain = 2X.
INL Error vs. DAC Code and
V
FIGURE 2-60:
Temperature (Single-Channel - MCP48CXB21),
DD = 1.8V, Gain = 1X.
INL Error vs. DAC Code and
FIGURE 2-63:
Temperature (Dual-Channel - MCP48CXB22),
VDD = 1.8V, Gain = 1X.
INL Error vs. DAC Code and
V
FIGURE 2-61:
INL Error vs. DAC Code,
FIGURE 2-64:
INL Error vs. DAC Code,
+25°C, Gain = 1X.
+25°C, Gain = 2X.
2019 Microchip Technology Inc.
DS20006160A-page 33
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-65:
INL Error vs. DAC Code,
+25°C, Gain = 1X and 2X.
DS20006160A-page 34
2019 Microchip Technology Inc.
MCP48CXBXX
2.2.9
Note:
DIFFERENTIAL NONLINEARITY ERROR (DNL) - MCP48CXB2X (12-BIT), VREF = INTERNAL
BAND GAP (VRXB:VRXA = ‘01’), CODE 64-4032
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-66:
DNL Error vs. DAC Code
FIGURE 2-69:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
and Temperature (Dual-Channel -
MCP48CXB21), VDD = 5.5V, Gain = 1X.
MCP48CXB22), VDD = 5.5V, Gain = 1X.
FIGURE 2-67:
DNL Error vs. DAC Code
FIGURE 2-70:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
and Temperature (Dual-Channel -
MCP48CXB21), VDD = 5.5V, Gain = 2X.
MCP48CXB22), VDD = 5.5V, Gain = 2X.
FIGURE 2-68:
DNL Error vs. DAC Code
FIGURE 2-71:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
MCP48CXB21), VDD = 2.7V, Gain = 1X.
and Temperature (Dual-Channel -
MCP48CXB22), VDD = 2.7V, Gain = 1X.
2019 Microchip Technology Inc.
DS20006160A-page 35
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-72:
DNL Error vs. DAC Code
FIGURE 2-75:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
and Temperature (Dual-Channel -
MCP48CXB21), VDD = 2.7V, Gain = 2X.
MCP48CXB22), VDD = 2.7V, Gain = 2X.
FIGURE 2-73:
DNL Error vs. DAC Code
FIGURE 2-76:
DNL Error vs. DAC Code
and Temperature (Single-Channel -
and Temperature (Dual-Channel -
MCP48CXB21), VDD = 1.8V, Gain = 1X.
MCP48CXB22), VDD = 1.8V, Gain = 1X.
FIGURE 2-74:
DNL Error vs. DAC Code,
FIGURE 2-77:
DNL Error vs. DAC Code,
+25°C, Gain = 1X.
+25°C, Gain = 2X.
DS20006160A-page 36
2019 Microchip Technology Inc.
MCP48CXBXX
Note:
Unless otherwise indicated, TA = +25°C, VDD = 5.5V.
FIGURE 2-78:
DNL Error vs. DAC Code,
+25°C, Gain = 1X and 2X.
2019 Microchip Technology Inc.
DS20006160A-page 37
MCP48CXBXX
NOTES:
DS20006160A-page 38
2019 Microchip Technology Inc.
MCP48CXBXX
3.0
PIN DESCRIPTIONS
Overviews of the pin functions are provided from
Section 3.1 to Section 3.10.
The descriptions of the pins for the single-DAC output
device are listed in Table 3-1, and descriptions for the
dual-DAC output device are listed in Table 3-2.
TABLE 3-1:
Pin
MSOP DFN
MCP48CXBX1 (SINGLE-DAC) PIN FUNCTION TABLE
Buffer
Type
Symbol
I/O
Description
QFN
16L
10L
10L
1
1
16
VDD
—
P
Supply Voltage
SPI Chip Select
2
3
2
3
1
2
CS
I
ST
VREF
A
Analog Voltage Reference Input/Output
Analog Buffered Analog Voltage Output
4
5
4
5
3
VOUT
NC
A
4,5,6,7,
8,14,15
—
—
Not Internally Connected
6
6
9
LAT/HVC
I
ST
DAC Wiper Register Latch/High-Voltage Command Pin
The Latch Pin allows the value in the volatile DAC registers
(wiper and configuration bits) to be transferred to the DAC
output (VOUT).
High-Voltage commands allow the User MTP configuration
bits to be written.
7
7
10
VSS
—
P
Ground Reference for all circuitries on the device
8
9
8
9
11
12
13
17
SDO
SCK
SDI
EP
O
I
ST
ST
ST
P
SPI Serial Data Output
SPI Serial Clock
10
—
10
—
I
SPI Serial Data Input
—
Exposed Thermal Pad, must be connected to VSS
Note 1: A = Analog, I = Input, ST = Schmitt Trigger, O = Output, I/O = Input/Output, P = Power
2019 Microchip Technology Inc.
DS20006160A-page 39
MCP48CXBXX
TABLE 3-2:
Pin
MSOP DFN
MCP48CXBX2 (DUAL-DAC) PIN FUNCTION TABLE
Buffer
Type
Symbol
I/O
Description
QFN
16L
10L
10L
1
1
16
VDD
—
P
Supply Voltage
SPI Chip Select
2
3
2
3
1
CS
I
ST
—
VREF
A
Analog Voltage Reference Input/Output
—
—
4
—
—
4
2
4
3
5
VREF0
VREF1
VOUT0
VOUT1
NC
A
A
Analog Voltage Reference Input/Output for DAC0
Analog Voltage Reference Input/Output for DAC1
Analog Buffered Analog Voltage Output 0
Analog Buffered Analog Voltage Output 1
A
5
5
A
—
—
6,7,14,
15
—
—
Not Internally Connected
6
6
—
LAT/HVC
I
I
ST
DAC Wiper Register Latch/High-Voltage Command Pin.
The Latch Pin allows the value in the volatile DAC registers
(wiper and configuration bits) to be transferred to the DAC
output (VOUT).
High-Voltage commands allow the User MTP configuration
bits to be written.
—
—
9
LAT0/HVC
ST
DAC0 Wiper Register Latch/High-Voltage Command Pin.
The Latch Pin allows the value in the volatile DAC0 registers
(wiper and configuration bits) to be transferred to the DAC0
output (VOUT0).
High-Voltage commands allow the User MTP configuration
bits to be written.
—
7
—
7
8
LAT1
VSS
I
ST
P
DAC1 Wiper Register Latch.
The Latch Pin allows the value in the volatile DAC1 registers
(wiper and configuration bits) to be transferred to the DAC1
output (VOUT1).
10
—
Ground Reference for all circuitries on the device
8
9
8
9
11
12
13
17
SDO
SCK
SDI
EP
O
I
ST
ST
ST
P
SPI Serial Data Output
SPI Serial Clock
10
—
10
—
I
SPI Serial Data Input
—
Exposed Thermal Pad, must be connected to VSS
Note 1: A = Analog, I = Input, ST = Schmitt Trigger, O = Output, I/O = Input/Output, P = Power
DS20006160A-page 40
2019 Microchip Technology Inc.
MCP48CXBXX
3.1
Positive Power Supply Input (V
)
3.5
Analog Output Voltage Pins
DD
VDD is the positive supply voltage input pin. The input
supply voltage is relative to VSS
(V
V
)
OUT0, OUT1
.
VOUT0 and VOUT1 are the DAC analog voltage output
pins. Each DAC output has an output amplifier. The DAC
output range depends on the selection of the voltage
reference source (and potential Output Gain selection).
These are:
The power supply at the VDD pin should be as clean as
possible for good DAC performance. It is
recommended to use an appropriate bypass capacitor
of about 0.1 µF (ceramic) to ground as close as
possible to the pin. An additional 10 µF capacitor
(tantalum) in parallel is also recommended to further
attenuate noise present in application boards.
• Device VDD - The full-scale range of the DAC
output is from VSS to approximately VDD
.
• VREF pin - The full-scale range of the DAC output
is from VSS to G x VRL, where G is the gain
selection option (1X or 2X).
3.2
Ground (V
)
SS
• Internal Band Gap - The full-scale range of the
DAC output is from VSS to G X VBG, where G is
the gain selection option (1X or 2X).
The VSS pin is the device ground reference.
The user must connect the VSS pin to a ground plane
through a low-impedance connection. If an analog
ground path is available in the application PCB (Printed
Circuit Board), it is highly recommended that the VSS
pin be tied to the analog ground path or isolated within
an analog ground plane of the circuit board.
In Normal mode, the DC impedance of the output pin is
about 1. In Power-Down mode, the output pin is
internally connected to a known pull-down resistor of
1 k, 100 k, or open. The Power-Down selection bits
settings are shown in Register 4-3 (Table 5-5).
3.3
Voltage Reference Pin (V
)
REF
3.6
Latch/High-Voltage Command Pin
(LAT/HVC)
The VREF pin is either an input or an output. When the
DAC’s voltage reference is configured as the VREF pin,
the pin is an input. When the DAC’s voltage reference is
configured as the internal band gap, the pin is an output.
The DAC output value update event can be controlled
and synchronized using the LAT pin, for one or both
channels, on a single or different devices.
When the DAC’s voltage reference is configured as the
VREF pin, there are two options for this voltage input:
VREF pin voltage is buffered or unbuffered. The
buffered option is offered in cases where the external
reference voltage does not have sufficient current
capability to not drop its voltage when connected to the
internal resistor ladder circuit.
The LAT pin controls the effect of the volatile wiper
registers, VRxB:VRxA, PDxB:PDxA and Gx bits on the
DAC output.
If the LAT pin is held at VIH, the values sent to the
volatile wiper registers and configuration bits have no
effect on the DAC outputs.
When the DAC’s voltage reference is configured as the
device VDD, the VREF pin is disconnected from the
internal circuit.
Once voltage on the pin transitions to VIL, the values in
the volatile wiper registers and configuration bits are
transferred to the DAC outputs.
When the DAC’s voltage reference is configured as the
internal band gap, the VREF pin’s drive capability is
minimal, so the output signal should be buffered.
The pin is level-sensitive, so writing to the volatile wiper
registers and configuration bits, while it is being held at
VIL, will trigger an immediate change in the outputs.
See Section 5.2 “Voltage Reference Selection” and
Register 4-2 for more details on the configuration bits.
For dual output devices in MSOP and DFN packages,
the LAT pin controls both channels at the same time.
The HVC pin allows the device’s MTP memory to be
programmed for the MCP48CMBXX devices. The
programming voltage supply should provide 7.5V and
at least 6.4 mA.
3.4
No Connect (NC)
The NC pin is not internally connected to the device.
Note:
The HVC pin should have voltages
greater than 5.5V present only during the
MTP programming operation. Using
voltages greater than 5.5V for an
extended time on the pin may cause
device reliability issues.
2019 Microchip Technology Inc.
DS20006160A-page 41
MCP48CXBXX
3.7
SPI - Chip Select Pin (CS)
3.9
SPI - Serial Data In Pin (SDI)
The CS pin enables/disables the serial interface (SDI,
SDO, and SCK). The serial interface must be enabled
for the device to receive any serial commands.
The SDI pin is the serial data input pin of the SPI
interface. The SDI pin is used to write the DAC wiper
registers and configuration bits.
Refer to Section 6.4 “Interface Pins (CS, SCK, SDI,
SDO, and LAT/HVC)” for more details regarding the
SPI serial interface communication.
3.10 SPI - Serial Data Out Pin (SDO)
The SDO pin is the serial data output pin of the SPI
interface. The SDO pin is used to read the DAC wiper
registers and configuration bits.
3.8
SPI - Serial Clock Pin (SCK)
The SCK pin is the serial clock pin of the SPI interface.
The MCP48CXBXX SPI Interface only accepts external
serial clocks.
DS20006160A-page 42
2019 Microchip Technology Inc.
MCP48CXBXX
4.1
Power-on Reset/Brown-out Reset
(POR/BOR)
4.0
GENERAL DESCRIPTION
The MCP48CXBX1 devices are single-channel voltage
output devices.
The internal Power-on Reset (POR)/Brown-out Reset
(BOR) circuit monitors the power supply voltage (VDD
during operation. This circuit ensures correct device
start-up at system power-up and power-down events.
)
The MCP48CXBX2 devices are dual-channel voltage
output devices.
These devices are offered with 8-bit (MCP48CXB0X),
10-bit (MCP48CXB1X) and 12-bit (MCP48CXB2X)
resolutions.
The device’s RAM retention voltage (VRAM) is lower
than the POR/BOR voltage trip point (VPOR/VBOR).
The maximum VPOR/VBOR voltage is less than 1.8V.
The family offers two memory options: the
MCP48CVBXX devices have a volatile memory, while
the MCP48CMBXX have a 32-times programmable
nonvolatile memory (MTP).
The POR and BOR trip points are at the same voltage,
and the condition is determined by whether the VDD
voltage is rising or falling (see Figure 4-1). What occurs
is different depending on whether the reset is a POR or
BOR reset.
All devices include an SPI serial interface and a write
latch (LAT) pin to control the update of the analog
output voltage value from the value written in the
volatile DAC output register.
POR occurs as the voltage rises (typically from 0V),
while BOR occurs as the voltage falls (typically from
VDD(MIN) or higher).
The devices use a resistor ladder architecture. The
resistor
When
VPOR/VBOR < VDD < 2.7V,
the
electrical
ladder
DAC
is
driven
from
a
performance may not meet the data sheet
specifications. In this region, the device is capable of
reading and writing to its volatile memory if the proper
serial command is executed.
software-selectable voltage reference source. The
source can be either the device’s internal VDD, an
external VREF pin voltage (buffered or unbuffered) or
an internal band gap voltage source.
The DAC output is buffered with a low power and
precision output amplifier. This output amplifier
provides a rail-to-rail output with low offset voltage and
low noise. The gain (1X or 2X) of the output buffer is
software configurable.
4.1.1
The Power-on Reset is the case where the device’s
DD has power applied to it from the VSS voltage level.
As the device powers-up, the VOUT pin floats to an
unknown value. When the device’s VDD is above the
transistor threshold voltage of the device, the output
starts to be pulled low.
POWER-ON RESET
V
The devices operate from a single supply voltage. This
voltage is specified from 2.7V to 5.5V for full specified
operation, and from 1.8V to 5.5V for digital operation.
The device operates between 1.8V and 2.7V, but
some device parameters are not specified.
After the VDD is above the POR/BOR trip point
(VBOR/VPOR), the resistor network’s wiper is loaded
with the POR value. The POR value is either mid-scale
(MCP48CVBXX) or the user’s MTP programmed value
(MCP48CMBXX).
The
MCP48CMBXX
devices
also
have
user-programmable nonvolatile configuration memory
(MTP). This allows the device’s desired POR values to
be saved. The device also has general purpose MTP
memory locations for storing system specific
information (calibration data, serial numbers, system
Note:
In order to have the MCP48CMBXX
devices load the values from nonvolatile
memory locations at POR, they have to be
programmed at least once by the user;
otherwise, the loaded values will be the
default ones. After MTP programming, a
POR event is required to load the written
values from the nonvolatile memory.
ID information).
A high-voltage requirement for
programming the nonvolatile locations on the HVC pin
ensures that these device settings are not accidentally
modified during normal system operation. Therefore, it
is recommended that the MTP memory should be only
programmed at the user’s factory.
Volatile memory determines the analog output (VOUT
pin voltage. After the device is powered-up, the user
can update the device memory.
)
The main functional blocks are:
• Power-on Reset/Brown-out Reset (POR/BOR)
• Device Memory
• Resistor Ladder
• Output Buffer/VOUT Operation
• SPI Serial Interface Module
2019 Microchip Technology Inc.
DS20006160A-page 43
MCP48CXBXX
When the rising VDD voltage crosses the VPOR trip
point, the following occurs:
The analog output (VOUT) state is determined by the
state of the volatile configuration bits and the DAC
register. This is called a Power-on Reset (event).
• The default DAC POR value is latched into the
volatile DAC register.
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
• The default DAC POR Configuration bit values
are latched into the volatile configuration bits.
• POR Status bit is set (‘1’).
• The Reset Delay Timer (tPORD) starts; when the
reset delay timer (tPORD) times out, the SPI serial
interface is operational. During this delay time, the
SPI interface will not accept commands.
• The Device Memory Address pointer is forced to
00h.
POR starts Reset Delay Timer.
Default Device configuration
latched into volatile configuration
bits and DAC register.
Case 1: V Ramp
DD
When timer times out, the SPI interface
can operate (if VDD VDD(MIN)
)
BOR reset,
POR status bit is set (‘1’)
Volatile memory
volatile DAC register = 000h
volatile VRxB:VRxA = 00
volatile Gx = 0
retains data value
POR reset
TPORD2OD
volatile PDxB:PDxA = 11
forced active
VDD(MIN)
VPOR
Volatile memory
becomes corrupted
VBOR
VRAM
Device in
Below min. Power-D
Device in unknown
state
Device in
unknown
own state
state
Normal Operation
Device
in POR
state
operating
voltage
Volatile memory
retains data value
Device in
known state
POR Event
Case 2: V Step
DD
VDD(MIN)
Volatile memory
becomes corrupted
TPORD2OD
VBOR
VPOR
VRAM
Device in
Power-D
own state
Normal Operation
Device in
unknown
state
Device in unknown
state
Below min.
operating
voltage
FIGURE 4-1:
Power-on Reset Operation.
DS20006160A-page 44
2019 Microchip Technology Inc.
MCP48CXBXX
The volatile memory starts functioning when the
device VDD is at (or above) the RAM retention voltage
(VRAM). The volatile memory will be loaded with the
default device values when the VDD rises across the
VPOR/VBOR voltage trip point.
4.1.2
BROWN-OUT RESET
A Brown-out Reset occurs when a device had power
applied to it and that power (voltage) drops below the
specified range.
When the falling VDD voltage crosses the VPOR trip
point (BOR event), the following occurs:
After the device is powered-up, the user can update
the device memory. Table 4-2 shows the volatile
memory locations and their interaction due to a POR
event.
• Serial Interface is disabled.
• MTP Writes are disabled.
• Device is forced into a Power-Down state
(PDxB:PDxA = ‘11’). Analog circuitry is turned off.
4.2.2
NONVOLATILE REGISTER
MEMORY (MTP)
• Volatile DAC register is forced to 000h.
This memory option is available only for the
MCP48CMBXX devices.
Volatile configuration bits VRxB:VRxA and GX are
forced to ‘0’.
MTP memory starts functioning below the device’s
VPOR/VBOR trip point and, once the VPOR event
occurs, the volatile memory registers are loaded with
the corresponding MTP register memory values.
If the VDD voltage decreases below the VRAM voltage,
all volatile memory may become corrupted.
As the voltage recovers above the VPOR/VBOR voltage,
see Section 4.1.1 “Power-on Reset” for further
details.
Memory addresses 0Ch through 1Fh are nonvolatile
memory locations. These locations contain the DAC
POR/BOR Wiper values, the DAC POR/BOR
configuration bits and 8 general purpose memory
locations for storing user-defined data as calibration
constants or identification numbers.
Serial commands not completed due to a brown-out
condition may cause the memory location to become
corrupted.
Figure 4-1 illustrates the conditions for power-up and
power-down events under typical conditions.
The nonvolatile wiper registers and configuration bits
determine the DAC Output and Configuration values at
the POR event.
4.2
Device Memory
These nonvolatile values will overwrite the factory
default values. If these MTP addresses are
unprogrammed, the factory default values define the
output state.
User memory includes the following types:
• Volatile Register Memory (RAM)
• Nonvolatile Register Memory (MTP)
MTP memory is present just for the MCP48CMBXX
devices and has three groupings:
The nonvolatile DAC registers enable the standalone
operation of the device (without microcontroller
control), after being programmed to the desired
values.
• NV DAC Output Values (loaded on POR event)
• Device Configuration Memory
• General Purpose NV Memory
To program nonvolatile memory locations,
a
high-voltage source on the LAT/HVC pin is required.
Each register/MTP location can be programmed 32
times. After 32 writes, a new write operation will not be
possible and the last successful value written will
remain associated with the memory location.
Each memory location is up to 16 bits wide. The
memory mapped register space is shown in Table 4-1.
The SPI interface depends on how this memory is read
and written. Refer to Section 6.0 “SPI Serial Interface
Module” and Section 7.0 “Device Commands” for
more details on reading and writing the device’s
memory.
The device starts writing the MTP memory cells at the
completion of the serial interface command. The high
voltage should remain present on the LAT/HVC pin
until the write cycle is complete; otherwise, the write is
unsuccessful and the location is compromised (cannot
be used again and the number of available writes
decreases by one).
4.2.1
VOLATILE REGISTER MEMORY
(RAM)
The MCP48CXBXX devices have volatile memory to
directly control the operation of the DACs. There are
up to five volatile memory locations:
To recover from an aborted MTP write operation, the
following procedure must be used:
• DAC0 and DAC1 Output Value registers
• VREF Select register
• Write any valid value to the same address again
• Force a POR condition
• Power-Down Configuration register
• Gain and Status register
• Write the desired value to the MTP location again
2019 Microchip Technology Inc.
DS20006160A-page 45
MCP48CXBXX
It is recommended to keep high voltage on only during
the MTP Write command and programming cycle;
otherwise, the reliability of the device could be
affected.
CMDERR). High-Voltage commands
unimplemented configuration bit(s) will also result in a
Command Error condition.
to any
4.2.5
POR/BOR OPERATION WITH
WIPERLOCK TECHNOLOGY
ENABLED
4.2.3
UNIMPLEMENTED LOCATIONS
Unimplemented Register Bits
4.2.3.1
Regardless of the WiperLock Technology state, a POR
event will load the Volatile DACx Wiper register value
with the Nonvolatile DACx Wiper register value. Refer
to Section 4.1 “Power-on Reset/Brown-out Reset
(POR/BOR)” for further information.
When issuing Read commands to a valid memory
location with unimplemented bits, the unimplemented
bits will be read as ‘0’.
4.2.4
UNIMPLEMENTED (RESERVED)
LOCATIONS
There are a number of unimplemented memory
locations that are reserved for future use. Normal
(Voltage) commands (Read or Write) to any
unimplemented memory address will result in a
Command Error condition (SPI Command Error -
TABLE 4-1:
Function
MCP48CXBXX MEMORY MAP (16-BIT)
Function
00h Volatile DAC Wiper Register 0
01h Volatile DAC Wiper Register 1
02h Reserved
Y
Y
Y
10h Nonvolatile DAC Wiper Register 0
11h Nonvolatile DAC Wiper Register 1
12h Reserved
Y
Y
Y
—
—
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
— —
03h Reserved
13h Reserved
04h Reserved
14h Reserved
05h Reserved
15h Reserved
06h Reserved
16h Reserved
07h Reserved
17h Reserved
08h Volatile VREF Register
09h Volatile Power-Down Register
Y
Y
Y
Y
18h Nonvolatile VREF Register
Y
Y
Y
Y
19h Nonvolatile Power-Down
Register
0Ah Volatile Gain and Status
Register
Y
Y
1Ah NV Gain
Y
Y
0Bh Reserved
— —
(1)
1Bh NV WiperLock™ Technology Register
1Ch General Purpose MTP
Y
Y
0Ch General Purpose MTP
0Dh General Purpose MTP
0Eh General Purpose MTP
0Fh General Purpose MTP
(1)
(1)
1Dh General Purpose MTP
(1)
(1)
(1)
(1)
1Eh General Purpose MTP
(1)
1Fh General Purpose MTP
Legend:
Volatile Memory addresses
MTP Memory addresses
Memory locations not implemented on this device family
Note 1: On nonvolatile memory devices only (MCP48CMBXX)
DS20006160A-page 46
2019 Microchip Technology Inc.
MCP48CXBXX
TABLE 4-2:
FACTORY DEFAULT POR/BOR VALUES (MTP MEMORY UNPROGRAMMED)
POR/BOR Value
POR/BOR Value
Function
Function
00h Volatile DAC0 Register
01h Volatile DAC1 Register
7Fh
1FFh 7FFh
1FFh 7FFh
10h Nonvolatile DAC0 Wiper
7Fh
1FFh
1FFh
7FFh
(1)
Register
7Fh
11h Nonvolatile DAC1 Wiper
7Fh
7FFh
(1)
Register
02h Reserved
12h Reserved
13h Reserved
14h Reserved
15h Reserved
16h Reserved
17h Reserved
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
03h Reserved
04h Reserved
—
05h Reserved
—
06h Reserved
—
07h Reserved
—
08h Volatile VREF Register
0000h 0000h 0000h
18h
0000h 0000h
0000h
Nonvolatile VREF
register
(1)
09h Volatile Power-Down
Register
0000h 0000h 0000h
0080h 0080h 0080h
0000h 0000h 0000h
19h Nonvolatile Power-Down
0000h 0000h
0000h 0000h
0000h 0000h
0000h
0000h
0000h
(1)
Register
(1)
0Ah Volatile Gain and Status
1Ah NV Gain
(2)
Register
0Bh Reserved
1Bh NV WiperLock™
(1)
Technology Register
(1)
(1)
0Ch General Purpose MTP
0Dh General Purpose MTP
0Eh General Purpose MTP
—
—
—
1Ch General Purpose MTP
0000h 0000h
0000h 0000h
0000h 0000h
0000h 0000h
0000h
0000h
0000h
0000h
(1)
(1)
(1)
0000h 0000h 0000h
0000h 0000h 0000h
0000h 0000h 0000h
1Dh General Purpose MTP
(1)
1Eh
1Fh
General Purpose MTP
General Purpose MTP
(1)
(1)
0Fh
General Purpose MTP
Legend:
Volatile Memory address range
Nonvolatile Memory address range
Not implemented
Note 1: On nonvolatile devices only (MCP48CMBXX).
2: The “1” bit is the POR status bit, which is set after the POR event and cleared after address 0Ah is read.
2019 Microchip Technology Inc.
DS20006160A-page 47
MCP48CXBXX
4.2.6
DEVICE REGISTERS
Register 4-1 shows the format of the DAC Output Value
registers for the volatile memory locations. These reg-
isters will be either 8 bits, 10 bits, or 12 bits wide. The
values are right justified.
REGISTER 4-1:
DAC0 (00H/10H) AND DAC1 (01H/11H) OUTPUT VALUE REGISTERS
(VOLATILE/NONVOLATILE)
R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n
D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
U
-0
U
-0
U
-0
U-0
12-bit
10-bit
8-bit
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
D09 D08 D07 D06 D05 D04 D03 D02 D01 D00
—
—
D07 D06 D05 D04 D03 D02 D01 D00
bit 0
bit 15
Legend:
R = Readable bit
-n = Value at POR
= 12-bit device
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
= 10-bit device
= 8-bit device
12-bit
10-bit
8-bit
bit 15-12 bit 15-10 bit 15-8 Unimplemented: Read as ‘0’
bit 11-0
—
—
D11-D00: DAC Output value - 12-bit devices
FFFh = Full-Scale output value
7FFh = Mid-Scale output value
000h = Zero-Scale output value
—
bit 9-0
—
—
D09-D00: DAC Output value - 10-bit devices
3FFh = Full-Scale output value
1FFh = Mid-Scale output value
000h = Zero-Scale output value
—
bit 7-0
D07-D00: DAC Output value - 8-bit devices
FFh = Full-Scale output value
7Fh = Mid-Scale output value
00h = Zero-Scale output value
Note 1: Unimplemented bit, read as ‘0’.
DS20006160A-page 48
2019 Microchip Technology Inc.
MCP48CXBXX
Register 4-2 shows the format of the Voltage
Reference Control register. Each DAC has two bits to
control the source of the voltage reference of the DAC.
This register is for the volatile memory locations. The
width of this register is 2 times the number of DACs for
the device.
REGISTER 4-2:
VOLTAGE REFERENCE (VREF) CONTROL REGISTERS (08h/18h)
(VOLATILE/NONVOLATILE)
R/W-n R/W-n R/W-n R/W-n
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
(1)
(1)
Single
Dual
—
—
VR0B VR0A
—
—
—
—
—
—
—
—
—
—
—
—
VR1B VR1A VR0B VR0A
bit 0
bit 15
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
= Single-channel device
= Dual-channel device
Single
bit 15-2 bit 15-4 Unimplemented: Read as ‘0’
bit 1-0 bit 3-0 VRxB-VRxA: DAC Voltage Reference Control bits
Dual
11= VREF pin (Buffered); VREF buffer enabled
10= VREF pin (Unbuffered); VREF buffer disabled
01= Internal Band Gap(2) (1.214V typical); VREF buffer enabled. VREF voltage driven when
powered-down.
00= VDD (Unbuffered); VREF buffer disabled. Use this state with power-down bits for lowest
current.
Note 1: Unimplemented bit, read as ‘0’.
2: When the Internal Band Gap is selected, the band gap voltage source will continue to output the voltage
on the VREF pin in any of the Power-Down modes. To reduce the power consumption to its lowest level
(Band Gap disabled), after selecting the desired Power-Down mode, the voltage reference should be
changed to VDD or VREF pin unbuffered (“00” or ‘10’), which turns off the Internal Band Gap circuitry. After
wake-up, the user needs to reselect the Internal Band Gap (“01”) for the voltage reference source.
2019 Microchip Technology Inc.
DS20006160A-page 49
MCP48CXBXX
Register 4-3 shows the format of the Power-Down
Control register. Each DAC has two bits to control the
Power-Down state of the DAC. This register is for the
volatile memory locations and the nonvolatile memory
locations. The width of this register is 2 times the
number of DACs for the device.
REGISTER 4-3:
POWER-DOWN CONTROL REGISTERS (09h/19h)
(VOLATILE/NONVOLATILE)
R/W-n R/W-n R/W-n R/W-n
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
(1)
(1)
Single
Dual
—
—
PD0B PD0A
—
—
—
—
—
—
—
—
—
—
—
—
PD1B PD1A PD0B PD0A
bit 0
bit 15
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
x = Bit is unknown
= Single-channel device
= Dual-channel device
Single
bit 15-2 bit 15-4 Unimplemented: Read as ‘0’
bit 1-0 bit 3-0
PDxB-PDxA: DAC Power-Down Control bits(2)
11=Powered-Down - VOUT is open circuit
Dual
10=Powered-Down - VOUT is loaded with a 100 k resistor to ground
01=Powered-Down - VOUT is loaded with a 1 k resistor to ground
00=Normal Operation (Not powered-down)
Note 1: Unimplemented bit, read as ‘0’.
2: See Table 5-5 for more details.
DS20006160A-page 50
2019 Microchip Technology Inc.
MCP48CXBXX
Register 4-4 shows the format of the Gain Control and
System Status register. Each DAC has one bit to
control the gain of the DAC and two Status bits.
REGISTER 4-4:
GAIN CONTROL AND SYSTEM STATUS REGISTER (0Ah)
(VOLATILE)
R/W-n R/W-n R/C-1
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
R
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
(1)
Single
Dual
—
G0 POR MTPMA
G0 POR MTPMA
—
—
—
—
—
—
G1
—
—
—
—
—
—
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
C = Clearable bit
‘0’ = Bit is cleared
= Dual-channel device
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
= Single-channel device
Single
Dual
bit 15-9 bit 15-10 Unimplemented: Read as ‘0’
—
bit 9
bit 8
bit 7
G1: DAC1 Output Driver Gain control bits
(2)
1
0
= 2x Gain. Not applicable when VDD is used as VRL
= 1x Gain
bit 8
bit 7
G0: DAC0 Output Driver Gain control bits
(2)
1
0
= 2x Gain. Not applicable when VDD is used as VRL
= 1x Gain
POR: Power-on Reset (Brown-out Reset) Status bit
This bit indicates if a POR or BOR event has occurred since the last Read command of
this register. Reading this register clears the state of the POR Status bit.
1
= A POR (BOR) event occurred since the last read of this register. Reading this register clears
this bit.
0 = A POR (BOR) event has not occurred since the last read of this register.
bit 6
bit 6
MTPMA: MTP Memory Access Status bit(3)
This bit indicates if the MTP Memory Access is occurring.
1
0
= An MTP Memory Access is currently occurring (during the POR MTP read cycle or an MTP
write cycle is occurring). Only serial commands addressing the volatile memory are allowed.
= An MTP memory Access is NOT currently occurring
bit 5-0
bit 5-0
Unimplemented: Read as ‘0’
Note 1: Unimplemented bit, read as ‘0’.
2: The DAC’s Gain bit is ignored, and the gain is forced to 1X (GX = “0”) when the DAC Voltage Reference is
selected as VDD (VRxB:VRxA = “00”).
3: For devices configured as volatile memory, this bit is read as ‘0’.
2019 Microchip Technology Inc.
DS20006160A-page 51
MCP48CXBXX
Register 4-5 shows the format of the Nonvolatile Gain
Control register. Each DAC has one bit to control the
gain of the DAC.
REGISTER 4-5:
GAIN CONTROL REGISTER (1Ah)
(NONVOLATILE)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0 R/W-n R/W-n U-0 U-0
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
Single
Dual
—
—
G1
G1
G0
G0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
bit 15
bit 0
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
C = Clearable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
= Single-channel device
= Dual-channel device
Single
Dual
bit 15-10
bit 9-8
bit 15-10
bit 9-8
Unimplemented: Read as ‘0’
GX(1): DAC Output Driver Gain control bits
1= 2X Gain
0= 1X Gain
bit 7-0
bit 7-0
Unimplemented: Read as ‘0’
Note 1: When the DAC Voltage Reference is selected as VDD (VRxB:VRxA = “00”), the DAC’s Gain bit is ignored
and the gain is forced to 1X (GX = “0”).
DS20006160A-page 52
2019 Microchip Technology Inc.
MCP48CXBXX
Register 4-6 shows the format of the DAC WiperLock
Technology Status Register. The width of this register is
2 times the number of DACs for the device.
WiperLock Technology bits only control access to
volatile memory. Nonvolatile memory write access is
controlled by the requirement of high voltage on the
HVC pin, which is recommended to not be available
during normal device operation.
REGISTER 4-6:
WIPERLOCK TECHNOLOGY CONTROL REGISTER (1BH)
(NONVOLATILE)
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0
—
U-0 R/W-n R/W-n R/W-n R/W-n
(1)
(1)
Single
Dual
—
—
—
—
WL0B WL0A
—
—
—
—
—
—
—
—
—
—
—
WL1B WL1A WL0B WL0A
bit 0
bit 15
Legend:
R = Readable bit
-n = Value at POR
W = Writable bit
‘1’ = Bit is set
C = Clearable bit
‘0’ = Bit is cleared
U = Unimplemented bit, read as ‘0’
x = Bit is unknown
= Single-channel device
= Dual-channel device
Single
bit 15-2 bit 15-4 Unimplemented: Read as ‘0’
bit 1-0 bit 3-0
WLXB-WLXA: WiperLock™ Technology Status bits(2)
Dual
11= Vol. DAC Wiper Register and Vol. DAC configuration bits are locked
10= Vol. DAC Wiper Register is locked, and Vol. DAC configuration bits are unlocked
01= Vol. DAC Wiper Register is unlocked, and Vol. DAC configuration bits are locked
00= Vol. DAC Wiper Register and Vol. DAC configuration bits are unlocked
Note 1: Unimplemented bit, read as ‘0’.
2: The volatile PDxB:PDxA bits are NOT locked due to the requirement of being able to exit Power-Down
mode.
2019 Microchip Technology Inc.
DS20006160A-page 53
MCP48CXBXX
NOTES:
DS20006160A-page 54
2019 Microchip Technology Inc.
MCP48CXBXX
The functional blocks of the DAC include:
5.0
DAC CIRCUITRY
• Resistor Ladder
The Digital to Analog Converter circuitry converts a digital
value into its analog representation. The description
describes the functional operation of the device.
• Voltage Reference Selection
• Output Buffer/VOUT Operation
• Latch Pin (LAT)
The DAC Circuit uses a resistor ladder implementation.
Devices have up to two DACs. Figure 5-1 shows the
functional block diagram for the MCP48CXBXX DAC
circuitry.
• Power-Down Operation
Power-Down
Operation
VDD
PD1:PD0 and
VREF1:VREF0
Internal Band Gap
VDD
Voltage
Reference
Selection
VREF
VREF1:VREF0 and
PD1:PD0
Band Gap
(1.214V typical)
VDD
VREF1:VREF0
Power-Down
Operation
V
A (RL)
RL
DAC
Output
Selection
VDD
RS(2 )
n
PD1:PD0
RS(2
n
- 1)
VW
RS(2n - 2)
VOUT
RS(2n - 3)
PD1:PD0
Gain
RRL
(~71 k)
(1x or 2x)
Output Buffer/VOUT
Operation
Power-Down
Operation
RS(2)
RS(1)
DAC Register Value
VW = --------------------------------------------------------------------- VRL
# Resistor in Resistor Ladder
Where:
# Resistors in Resistor Ladder = 256
B
Resistor
Ladder
(MCP48CXB0X)
1024 (MCP48CXB1X)
4096 (MCP48CXB2X)
FIGURE 5-1:
MCP48CXBXX DAC Module Block Diagram.
2019 Microchip Technology Inc.
DS20006160A-page 55
MCP48CXBXX
5.1
Resistor Ladder
DAC
Register
The resistor ladder is a digital potentiometer with the
A Terminal connected to the selected reference voltage
and the B Terminal internally grounded (see
Figure 5-2). The volatile DAC register controls the
wiper position. The wiper voltage (VW) is proportional to
the DAC register value divided by the number of resis-
tor elements (RS) in the ladder (256, 1024 or 4096)
related to the VRL voltage.
V
RL
RS(2 )
n
(1)
2n - 1
2n - 2
RW
RW
RS(2
n
( )
1
- 1)
The output of the resistor network will drive the input of
an output buffer.
RS(2n - 2)
( )
1
RW
2n - 3
The Resistor Network is made up of three parts:
• Resistor Ladder (string of RS elements)
• Wiper switches
VW
RS(2n - 3)
( )
1
• DAC register decode
RW
RW
RRL
2
The resistor ladder has a typical impedance (RRL) of
approximately 71 k. This resistor ladder resistance
(RRL) may vary from device to device up to ±10%.
Since this is a voltage divider configuration, the actual
RRL resistance does not affect the output, given a fixed
RS(2)
( )
1
1
0
RS(1)
( )
1
RW
voltage at VRL
.
Equation 5-1 shows the calculation for the step
resistance.
Analog Mux
Note:
The maximum wiper position is 2n – 1,
while the number of resistors in the
resistor ladder is 2n. This means that
when the DAC register is at full scale,
there is one resistor element (RS)
between the wiper and the VRL voltage.
Note 1:
The analog switch resistance (RW)
does not affect performance due to the
voltage divider configuration.
FIGURE 5-2:
Block Diagram.
Resistor Ladder Model
If the unbuffered VREF pin is used as the VRL voltage
source, the external voltage source should have a low
output impedance.
When the DAC is powered down, the resistor ladder is
disconnected from the selected reference voltage.
EQUATION 5-1:
RS CALCULATION
R
RL
R
= --------------
8-bit Device
S
256
R
RL
R
= -----------------
10-bit Device
12-bit Device
S
1024
R
RL
R
= -----------------
S
4096
DS20006160A-page 56
2019 Microchip Technology Inc.
MCP48CXBXX
If the VREF pin is tied to the VDD voltage, selecting
the VDD Reference mode (VREF1:VREF0 = ‘00’) is
recommended.
5.2
Voltage Reference Selection
The resistor ladder has up to four sources for the
reference voltage. The selection of the voltage
reference source is specified with the volatile
VREF1:VREF0 configuration bits (see Register 4-2).
The selected voltage source is connected to the VRL
node (see Figure 5-3 and Figure 5-4).
5.2.3
USING AN EXTERNAL VREF
SOURCE IN BUFFERED MODE
The VREF pin voltage may be from 0V to VDD. The input
buffer (amplifier) provides low offset voltage, low noise,
and a very high input impedance, with only minor
limitations on the input range and frequency response.
VREF1:VREF0
VREF
VDD
Any variation or noises on the reference source can
directly affect the DAC output. The reference voltage
needs to be as clean as possible for accurate DAC
performance.
Band Gap
VRL
VDD
VDD
Buffer
PD1:PD0 and
VREF1:VREF0
FIGURE 5-3:
Voltage Selection Block Diagram.
Resistor Ladder Reference
PD1:PD0 and
VREF1:VREF0
The four voltage source options for the Resistor Ladder
are:
(1)
1. VDD pin voltage
Band Gap
(1.214V typical)
2. Internal band gap voltage reference (VBG
3. VREF pin voltage - unbuffered
)
VREF
VRL
4.
VREF pin voltage - internally buffered
On a POR/BOR event, the default configuration state or
the value written in the nonvolatile register is latched into
the volatile VREF1:VREF0 configuration bits.
VDD
If the VREF pin is used with an external voltage source,
then the user must select between Buffered or
Unbuffered mode.
PD1:PD0 and
VREF1:VREF0
5.2.1
USING VDD AS VREF
When the user selects the VDD as reference, the VREF
pin voltage is not connected to the Resistor Ladder.
The VDD voltage is internally connected to the Resistor
Ladder.
Note 1: The Band Gap voltage (VBG) is 1.214V
typical. The band gap output goes
through the buffer with a 2X gain to
create the VRL voltage. See Table 5-1
for additional information on the band
gap circuit.
5.2.2
USING AN EXTERNAL VREF
SOURCE IN UNBUFFERED MODE
In this case, the VREF pin voltage may vary from VSS to
VDD. The voltage source should have a low-output
impedance. If the voltage source has a high-output
impedance, then the voltage on the VREF pin could be
lower than expected. The resistor ladder has a typical
impedance of 71 k and a typical capacitance of 29 pF.
FIGURE 5-4:
Implementation Block Diagram.
Reference Voltage Selection
If a single VREF pin is supplying multiple DACs, the
VREF pin source must have adequate current capability
to support the number of DACs. It must be assumed
that the resistor ladder resistance (RRL) of each DAC is
at the minimum specified resistance and these resis-
tances are in parallel.
2019 Microchip Technology Inc.
DS20006160A-page 57
MCP48CXBXX
5.2.4
USING THE INTERNAL BAND GAP
AS VOLTAGE REFERENCE
5.3
Output Buffer/V
Operation
OUT
The Output Driver buffers the wiper voltage (VW) of the
Resistor Ladder.
The Internal Band Gap is designed to drive the Resistor
Ladder Buffer.
The DAC output is buffered with a low-power, precision
output amplifier with selectable gain. This amplifier
provides a rail-to-rail output with low offset voltage and low
noise. The amplifier’s output can drive the resistive and
high-capacitive loads without oscillation. The amplifier
provides a maximum load current which is enough for
most programmable voltage reference applications. Refer
to Section 1.0 “Electrical Characteristics” for the
specifications of the output amplifier.
If the Internal Band Gap is selected, then the band gap
voltage source will drive the external VREF pins. The
VREF1 pin must be left unloaded in this mode. The
voltage reference source can be independently
selected on devices with two DAC channels, but
restrictions apply:
• The VDD mode can be used without issues on any
channel.
• When the Internal Band Gap is selected as the
voltage source, all the VREF pins are connected to
its output. The use of the Unbuffered mode is only
possible on VREF0, because it’s the only one that
can be loaded.
Note:
The load resistance must be kept higher
than 2 k to maintain stability of the
analog output and have it meet electrical
specifications.
• When using the Internal Band Gap mode on
channel 0, channel 1 must be put in Buffered
External VREF mode or VDD Reference mode and
the VREF1 pin must be left unloaded.
Figure 5-5 shows a block diagram of the output driver
circuit.
VDD
The resistance of the resistor ladder (RRL) is targeted
to be 71 k (10%), which means a minimum
resistance of 63.9 k.
PD1:PD0
The band gap selection can be used across the VDD
voltages while maximizing the VOUT voltage ranges.
For VDD voltages below the Gain VBG voltage, the
output for the upper codes will be clipped to the VDD
voltage. Table 5-4 shows the maximum DAC register
code given device VDD and Gain bit setting.
VW
VOUT
PD1:PD0
Gain
(1x or 2x)
TABLE 5-1:
VOUT USING BAND GAP
(1)
Max DAC Code
FIGURE 5-5:
Output Driver Block Diagram.
Comment
12-bit 10-bit 8-bit
Power-Down logic also controls the output buffer
operation (see Section 5.5 “Power-Down Operation”
for additional information on Power-Down). In any of
the three Power-Down modes, the output amplifier is
powered down and its output becomes a high
impedance to the VOUT pin.
(3)
(3)
(3)
1
FFFh 3FFh FFh
FFFh 3FFh FFh
FFFh 3FFh FFh
FFFh 3FFh FFh
FFFh 3FFh FFh
V
V
V
V
V
= 1.214V
OUT(max)
OUT(max)
OUT(max)
OUT(max)
OUT(max)
5.5
2
= 2.428V
= 1.214V
= 2.428V
= 1.214V
1
2.7
2
1
5.3.1
PROGRAMMABLE GAIN
1.8
(2)
2
BBCh 2EFh BBh 1.8V
The amplifier’s gain is controlled by the Gain (G)
Configuration bit (see Register 4-4) and the VRL
reference selection (see Register 4-2).
Note 1: Without the V
pin voltage being clipped.
OUT
2: Recommended to use the Gain = 1 setting.
3: When V = 1.214V typical.
BG
The Gain options are:
a) Gain of 1, with either the VDD or VREF pin used
as reference voltage.
b) Gain of 2, only when the VREF pin or the Internal
Band Gap is used as reference voltage. The
VREF pin voltage should be limited to VDD/2.
When the reference voltage selection (VRL) is
the device’s VDD voltage, the G bit is ignored
and a gain of 1 is used.
Table 5-2 shows the gain bit operation.
DS20006160A-page 58
2019 Microchip Technology Inc.
MCP48CXBXX
TABLE 5-2:
OUTPUT DRIVER GAIN
VOUT(B)
Gain Bit
Gain
Comment
0
1
1
2
Limits V
pin voltages
REF
relative to device V voltage
DD
VOUT(A)
DACx = A
DACx = B
The volatile G bit value can be modified by:
• POR event
• BOR event
Time
• SPI Write commands
V
OUTB – VOUTA
Slew Rate = --------------------------------------------------
T
5.3.2
OUTPUT VOLTAGE
The volatile DAC register values, along with the
device’s configuration bits, control the analog VOUT
voltage. The volatile DAC register’s value is unsigned
binary. The formula for the output voltage is provided in
Equation 5-2. Examples of volatile DAC register values
and the corresponding theoretical VOUT voltage for the
MCP48CXBXX devices are shown in Table 5-6.
FIGURE 5-6:
VOUT Pin Slew Rate.
5.3.3.1
Small Capacitive Load
With a small capacitive load, the output buffer’s current
is not affected by the capacitive load (CL). But still, the
VOUT pin’s voltage is not a step transition from one out-
put value (DAC register value) to the next output value.
The change of the VOUT voltage is limited by the output
buffer’s characteristics, so the VOUT pin voltage will
have a slope from the old voltage to the new voltage.
This slope is fixed for the output buffer, and is referred
to as the buffer slew rate (SRBUF).
EQUATION 5-2:
CALCULATING OUTPUT
VOLTAGE (VOUT
VRL DAC Register Value
)
VOUT = --------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
Where:
5.3.3.2
Large Capacitive Load
# Resistors in R-Ladder = 4096 (MCP48CXB2X)
1024 (MCP48CXB1X)
With a larger capacitive load, the slew rate is
determined by two factors:
256 (MCP48CXB0X)
• The output buffer’s short-circuit current (ISC
)
• The VOUT pin’s external load
When Gain = 2 (VRL = VREF), if VREF > VDD/2, the VOUT
voltage is limited to VDD. So if VREF = VDD, the VOUT
voltage does not change for volatile DAC register values
mid-scale and greater, since the output amplifier is at
full-scale output.
IOUT cannot exceed the output buffer’s short-circuit
current (ISC), which fixes the output buffer slew rate
(SRBUF). The voltage on the capacitive load (CL), VCL
changes at a rate proportional to IOUT, which fixes a
capacitive load slew rate (SRCL).
The following events update the DAC register value
and therefore the analog voltage output (VOUT):
So the VCL voltage slew rate is limited to the slower of
the output buffer’s internally set slew rate (SRBUF) and
the capacitive load slew rate (SRCL).
• Power-on Reset
• Brown-out Reset
• SPI Write command (to volatile registers)
5.3.4
DRIVING RESISTIVE AND
CAPACITIVE LOADS
Next, the VOUT voltage starts driving to the new value
after the event has occurred.
The VOUT pin can drive up to 100 pF of capacitive load
in parallel with a 5 k resistive load (to meet electrical
specifications). VOUT drops slowly as the load resis-
tance decreases after about 3.5 k. It is recommended
to use a load with RL greater than 2 k.
5.3.3
OUTPUT SLEW RATE
Figure 5-6 shows an example of the slew rate of the
VOUT pin. The slew rate can be affected by the
characteristics of the circuit connected to the VOUT pin.
Refer to the Characterization Data documents for a
detailed VOUT vs. Resistive Load characterization
graph.
2019 Microchip Technology Inc.
DS20006160A-page 59
MCP48CXBXX
Driving large capacitive loads can cause stability
problems for voltage feedback output amplifiers. As the
load capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response with overshoot and ringing in the step
response. That is, since the VOUT pin’s voltage does
not quickly follow the buffer’s input voltage (due to the
large capacitive load), the output buffer will overshoot
the desired target voltage. Once the driver detects this
overshoot, it compensates by forcing it to a voltage
below the target. This causes voltage ringing on the
VOUT pin.
A method to evaluate the system’s performance is to
inject a step voltage on the VREF pin and observe the
VOUT pin’s characteristics.
Note: Additional insight into circuit design for
driving capacitive loads can be found in
AN884 – “Driving Capacitive Loads With
Op Amps” (DS00000884).
5.3.5
STEP VOLTAGE (VS)
The Step Voltage depends on the device resolution and
the calculated output voltage range. 1 LSb is defined
as the ideal voltage difference between two successive
codes. The step voltage can easily be calculated by
using Equation 5-3 (the DAC register value is equal to
1). Theoretical Step Voltages are shown in Table 5-3 for
several VREF voltages.
So, when driving large capacitive loads with the output
buffer, a small series resistor (RISO) at the output (see
Figure 5-7) improves the output buffer’s stability
(feedback loop’s phase margin) by making the output
load resistive at higher frequencies. The bandwidth will
be generally lower than the bandwidth with no
capacitive load.
EQUATION 5-3:
VS CALCULATION
VRL
VS = --------------------------------------------------------------------- Gain
# Resistor in Resistor Ladder
VOUT
VW
RISO
RL
Where:
# Resistors in R-Ladder = 4096
VCL
(12-bit)
(10-bit)
(8-bit)
CL
1024
256
Gain
FIGURE 5-7:
Circuit to Stabilize Output
Buffer for Large Capacitive Loads (CL).
The RISO resistor value for your circuit needs to be
selected. The resulting frequency response peaking
and step response overshoot for this RISO resistor
value should be verified on the bench. Modify the
RISO’s resistance value until the output characteristics
meet your requirements.
TABLE 5-3:
THEORETICAL STEP VOLTAGE (VS)(1)
VREF
Step
Voltage
#bits
5.0
2.7
1.8
1.5
1.0
1.22 mV
4.88 mV
19.5 mV
659 uV
2.64 mV
10.5 mV
439 uV
1.76 mV
7.03 mV
366 uV
1.46 mV
5.86 mV
244 uV
977 uV
3.91 mV
12-bit
VS
10-bit
8-bit
Note 1: When Gain = 1X, VFS = VRL, and VZS = 0V.
DS20006160A-page 60
2019 Microchip Technology Inc.
MCP48CXBXX
5.4
Latch Pin (LAT)
Serial Shift reg.
The Latch pin controls when the volatile DAC register
value is transferred to the DAC wiper. This is useful for
applications that need to synchronize the wiper(s)
updates to an external event, such as zero crossing or
updates to the other wipers on the device. The LAT pin
is asynchronous to the serial interface operation.
Register Address
Write command
24 Clocks
Vol. DAC register x
LAT
SYNC
(internal signal)
Transfer
Data
When the LAT pin is high, transfers from the volatile DAC
register to the DAC wiper are inhibited. The volatile DAC
register value(s) can continue to be updated.
DAC wiper x
When the LAT pin is low, the volatile DAC register value
is transferred to the DAC wiper.
Transfer
Data
LAT SYNC
Comment
1
1
0
0
1
0
1
0
0
0
1
0
No Transfer
No Transfer
Note:
This allows both the volatile DAC0 and
DAC1 registers to be updated while the
LAT pin is high, and to have outputs
synchronously updated as the LAT pin is
driven low.
Vol. DAC register x DAC wiper x
No Transfer
FIGURE 5-8:
LAT and DAC Interaction.
Figure 5-8 shows the interaction of the LAT pin and the
loading of the DAC wiper x (from the volatile DAC
register x). The transfers are level driven. If the LAT pin
is held low, the corresponding DAC wiper is updated as
soon as the volatile DAC register value is updated.
Since the DAC wiper x is updated from the volatile DAC
register x, all DACs that are associated with a given
LAT pin can be updated synchronously.
If the application does not require synchronization, then
this signal should be tied low.
The LAT pin allows the DAC wiper to be updated to an
external event and to have multiple DAC chan-
nels/devices update at a common event.
Figure 5-9 shows two cases of using the LAT pin to
control when the wiper register is updated relative to
the value of a sine wave signal.
Case 1: Zero Crossing of Sine Wave to update the volatile DAC0 register (using LAT pin)
Case 2: Fixed point Crossing of Sine Wave to update the volatile DAC0 register (using LAT pin)
Indicates where LAT pin pulses are active (volatile DAC0 register updated)
FIGURE 5-9:
Example Use of LAT Pin Operation.
• Retain the value of the volatile DAC register and
configuration bits
5.5 Power-Down Operation
To allow the application to conserve power when DAC
operation is not required, three Power-Down modes
are available. On devices with multiple DACs, each
DAC’s Power-Down mode is individually controllable.
Depending on the selected Power-Down mode, the
following will occur:
• VOUT pin is switched to one of the two resistive
pull-downs:
All Power-Down modes do the following:
- 100 k (typical)
- 1 k (typical)
• Turn off most of the DAC module’s internal circuits
• Op amp is powered down and the VOUT pin
becomes high-impedance
2019 Microchip Technology Inc.
DS20006160A-page 61
MCP48CXBXX
The Power-Down configuration bits (PD1:PD0) control
the power-down operation (Table 5-4).
Note 1: The SPI serial interface circuit is not
affected by the Power-Down mode. This
circuit remains active in order to receive
any command that might come from the
SPI Master device.
TABLE 5-4:
POWER-DOWN BITS AND
OUTPUT RESISTIVE LOAD
PD1
PD0
Function
5.5.1
EXITING POWER-DOWN
0
0
1
1
0
1
0
1
Normal operation
The following event changes the PD1:PD0 bits to ‘00’
and therefore exits the Power-Down mode. This is any
SPI Write command where the PD1:PD0 bits are ‘00’.
1 k resistor to ground
100 k resistor to ground
Open circuit
When the device exits Power-Down mode, the
following occurs:
There is a delay (TPDD) between the PD1:PD0 bits
changing from ‘00’ to either ‘01’, ‘10’ or ‘11’ and the op
amp no longer driving the VOUT output, and the
pull-down resistors sinking current.
• Disabled internal circuits are turned on
• Resistor ladder is connected to the selected
reference voltage (VRL
)
• Selected pull-down resistor is disconnected
In any of the Power-Down modes where the VOUT pin
is not externally connected (sinking or sourcing cur-
rent), as the number of DACs increases, the device’s
power-down current will also increase.
• The VOUT output is driven to the voltage
represented by the volatile DAC register’s value
and configuration bits
DAC Wiper register and DAC Wiper value may be
different due to the DAC Wiper register being modified
while the LAT pin was driven to (and remaining at) VIH.
Table 5-6 shows the current sources for the DAC based
on the selected source of the DAC’s reference voltage
and if the device is in normal operating mode or one of
the Power-Down modes.
The VOUT output signal requires time as these circuits
are powered-up and the output voltage is driven to the
specified value as determined by the volatile DAC
register and configuration bits.
TABLE 5-5:
DAC CURRENT SOURCES
Device
VDD
PDxB:xA = ‘00’,
VREFxB:xA =
PDxB:xA ‘00’,
VREFxB:xA =
Current
Source
Note:
Since the op amp and Resistor Ladder
were powered off (0V), the op amp’s input
voltage (VW) can be considered 0V. There
is a delay (TPDE) between the PD1:PD0
bits updating to ‘00’ and the op amp
driving the VOUT output. The op amp’s
settling time (from 0V) needs to be taken
into account to ensure the VOUT voltage
reflects the selected value.
00 01 10 11 00 01 10 11
Output
Op Amp
Y
Y
N
Y
Y
Y
Y
N(1)
N
Y
Y
Y
N
N
N
N
N
N
N
N(1)
N
N
N
N
Resistor
Ladder
VREF
Selection
Buffer
Band Gap
N
Y
N
N
N(2) Y(2) N(2) N(2)
Note 1: The current is sourced from the VREF pin,
not the device VDD
.
2: If DAC0 and DAC1 are in one of the
Power-Down modes, MTP write
operations are not recommended.
The power-down bits are modified by using a write
command to the volatile Power-Down register or a
POR event, which transfers the nonvolatile
Power-Down Register to the volatile Power-Down
Register.
Section 7.0 “Device Commands” describes the SPI
command for writing the power-down bits.
DS20006160A-page 62
2019 Microchip Technology Inc.
MCP48CXBXX
TABLE 5-6:
Device
DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (VOUT) (VDD = 5.0V)
(3)
LSb
Gain
VOUT
Volatile DAC
Register Value
(1)
VRL
Selection
(2)
Equation
5.0V/4096 1,220.7
2.5V/4096 610.4
µV
Equation
V
1111 1111 1111 5.0V
1x
1x
VRL (4095/4096) 1
VRL (4095/4096) 1
VRL (4095/4096) 2)
VRL (2047/4096) 1)
VRL (2047/4096) 1)
VRL (2047/4096) 2)
VRL (1023/4096) 1)
VRL (1023/4096) 1)
VRL (1023/4096) 2)
VRL (0/4096) * 1)
VRL (0/4096) * 1)
VRL (0/4096) * 2)
VRL (1023/1024) 1
VRL (1023/1024) 1
VRL (1023/1024) 2
VRL (511/1024) 1
VRL (511/1024) 1
VRL (511/1024) 2
VRL (255/1024) 1
VRL (255/1024) 1
VRL (255/1024) 2
VRL (0/1024) 1
4.998779
2.499390
4.998779
2.498779
1.249390
2.498779
1.248779
0.624390
1.248779
0
2.5V
2x(2)
0111 1111 1111 5.0V
5.0V/4096 1,220.7
2.5V/4096 610.4
1x
2.5V
1x
2x(2)
0011 1111 1111 5.0V
5.0V/4096 1,220.7
2.5V/4096 610.4
1x
2.5V
1x
2x(2)
0000 0000 0000 5.0V
5.0V/4096 1,220.7
2.5V/4096 610.4
1x
2.5V
1x
2x(2)
0
0
11 1111 1111
01 1111 1111
00 1111 1111
00 0000 0000
1111 1111
5.0V
2.5V
5.0V/1024 4,882.8
2.5V/1024 2,441.4
1x
4.995117
2.497559
4.995117
2.495117
1.247559
2.495117
1.245117
0.622559
1.245117
0
1x
2x(2)
5.0V
2.5V
5.0V/1024 4,882.8
2.5V/1024 2,441.4
1x
1x
2x(2)
5.0V
2.5V
5.0V/1024 4,882.8
2.5V/1024 2,441.4
1x
1x
2x(2)
5.0V
2.5V
5.0V/1024 4,882.8
2.5V/1024 2,441.4
1x
1x
2x(2)
VRL (0/1024) 1
0
VRL (0/1024) 1
0
5.0V
2.5V
5.0V/256 19,531.3
1x
VRL (255/256) 1
VRL (255/256) 1
VRL (255/256) 2
VRL (127/256) 1
VRL (127/256) 1
VRL (127/256) 2
VRL (63/256) 1
4.980469
2.490234
4.980469
2.480469
1.240234
2.480469
1.230469
0.615234
1.230469
0
2.5V/256
9,765.6
1x
2x(2)
0111 1111
5.0V
2.5V
5.0V/256 19,531.3
2.5V/256 9,765.6
1x
1x
2x(2)
0011 1111
5.0V
2.5V
5.0V/256 19,531.3
2.5V/256 9,765.6
1x
1x
2x(2)
VRL (63/256) 1
VRL (63/256) 2
0000 0000
5.0V
2.5V
5.0V/256 19,531.3
2.5V/256 9,765.6
1x
VRL (0/256) 1
1x
VRL (0/256) 1
0
2x(2)
VRL (0/256) 2
0
Note 1: VRL is the resistor ladder’s reference voltage. It is independent of the VREF1:VREF0 selection.
2: Gain selection of 2X (GX = ‘1‘) requires the voltage reference source to come from the VREF pin
(VREF1:VREF0 = ‘10’ or ‘11’) and requires VREF pin voltage (or VRL) ≤ VDD/2 or from the internal band
gap (VREF1:VREF0 = ‘01’).
3: These theoretical calculations do not take into account the Offset, Gain and Nonlinearity errors.
2019 Microchip Technology Inc.
DS20006160A-page 63
MCP48CXBXX
NOTES:
DS20006160A-page 64
2019 Microchip Technology Inc.
MCP48CXBXX
pin is high-voltage tolerant. To enter a high voltage
command, the HVC pin must be greater than the VIHH
voltage.
6.0
SPI SERIAL INTERFACE
MODULE
The MCP48CXBXX’s SPI Serial Interface Module is a
4-wire interface. The devices operate only as slaves
(do not generate the master clock). Figure 6-1 shows a
typical SPI interface connection.
Typical SPI Interfaces are shown in Figure 6-1. In the
SPI interface, the Master’s Output pin is connected to
the Slave’s Input pin, and the Master’s Input pin is
connected to the Slave’s Output pin.
The MCP48CXBXX SPI module supports two (of the
four) standard SPI modes. These are Mode 0,0and
1,1. The SPI mode is determined by the state of the
SCK pin (VIH or VIL) when the CS pin transitions from
inactive (VIH) to active (VIL).
Typical SPI Interface Connections
Host
MCP48CXBXX
Other Devices
Controller
SDO
SDI
SDI
6.2
Communication Data Rates
SDO
SCK
The MCP48CXBXX supports clock rates (bit rates) of
up to 25 MHz for read, and 50 MHz for Write
commands.
SCK
GPIO
GPIO
CS
For most applications, the write time will be considered
more important, since that is how the device operation
is controlled.
LAT/HVC
(Master)
(Slave)
FIGURE 6-1:
Typical SPI Interface.
6.3
POR/BOR
The frame content (commands) for the MCP48CXBXX
On a POR/BOR event, the SPI Serial Interface Module
state machine is reset, which includes forcing the
device’s Memory Address pointer to 00h.
are defined in Section 7.0 “Device Commands”.
6.1
Overview
This section discusses some of the specific
characteristics of the MCP48CXBXX’s SPI Serial
Interface Module. This is to assist in the development of
your application.
6.4
Interface Pins (CS, SCK, SDI, SDO,
and LAT/HVC)
The operation of the four interface pins and the
High-Voltage command (HVC) pin is discussed in this
section. The serial interface works on 24-bit
boundaries. The CS pin frames the SPI commands.
The following sections discuss some of these
device-specific characteristics:
• Communication Data Rates
• POR/BOR
6.4.1
SERIAL DATA IN (SDI)
The Serial Data In (SDI) signal is the data signal in the
device. The value on this pin is latched on the rising
edge of the SCK signal.
• Interface Pins (CS, SCK, SDI, SDO, and
LAT/HVC)
• Device Memory Address
• SPI Modes
6.4.2
SERIAL DATA OUT (SDO)
The MCP48CXBXX devices support the SPI serial
protocol. This SPI operates in Slave mode (does not
generate the serial clock).
The Serial Data Out (SDO) signal is the data signal out
of the device. The value on this pin is driven on the
falling edge of the SCK signal.
The SPI interface uses four pins. These are:
Once the CS pin is forced to the active level (VIL), the
SDO pin is driven. The state of the SDO pin is deter-
mined by the serial bit’s position in the command, the
selected command, and if there is a state of command
error (CMDERR).
• CS - Chip Select
• SCK - Serial Clock
• SDI - Serial Data In
• SDO - Serial Data Out
A fifth pin is used if a write is being done in the MTP
memory. This pin is HVC - High Voltage Command
(customer manufacturing only, multiplexed with LAT0
functionality).
6.4.3
SERIAL CLOCK (SCK)
(SPI FREQUENCY OF OPERATION)
The SPI interface is specified to operate up to 50 MHz
for Write commands and 25 MHz for read commands.
The actual clock rate depends on the configuration of
the system and the serial command used. Table 6-1
shows the SCK frequency for different configurations.
The HVC pin is used to program the MTP memory.
This is intended to be used only during the customer’s
factory production flow. On volatile devices, the HVC
2019 Microchip Technology Inc.
DS20006160A-page 65
MCP48CXBXX
TABLE 6-1:
SCK FREQUENCY
6.5
Device Memory Address
Command
The memory address is the 5-bit value that specifies
the location in the device’s memory that the specified
command will operate on.
Memory Type Access
Read
Write
50 MHz (1)
On a POR/BOR event, the device’s Memory Address
pointer is forced to 00h.
Nonvolatile
Memory
SDI, SDO 25 MHz
Volatile
Memory
SDI, SDO 25 MHz
50 MHz (1)
6.6
SPI Modes
The SPI module supports two (of the four) standard
SPI modes. These are Mode 0,0 and 1,1. The
MCP48CXBXX’s SPI mode is automatically
determined based on the Master’s configured mode.
Note 1: After issuing a Write command to the NV
locations, the internal write cycle must be
completed before the next SPI command
addressing the NV locations is received
(twc).
6.4.4
The CS signal is used to select the device and frame a
command sequence. To start command, or
THE CS SIGNAL
a
sequence of commands, the CS signal must transition
from the inactive state (VIH) to an active state (VIL).
After the CS signal has gone active, the SDO pin is
driven and the clock bit counter is reset.
Note: There is a required delay after the CS pin
goes active to the 1st edge of the SCK pin.
If an error condition occurs for an SPI command, then
the Command byte’s Command Error (CMDERR) bit
(on the SDO pin) will be driven low (VIL). To exit the
error condition, the user must take the CS pin to the
VIH level.
When the CS pin returns to the inactive state (VIH), the
SPI module resets (including the address pointer).
While the CS pin is in the inactive state (VIH), the serial
interface is ignored. This allows the Host Controller to
interface to other SPI devices using the same SDI,
SDO, and SCK signals.
6.4.5
THE HVC SIGNAL
The high voltage requirement of the HVC pin for
programming MTP registers ensure that a device in
normal operation does not corrupt the values.
DS20006160A-page 66
2019 Microchip Technology Inc.
MCP48CXBXX
6.6.1
OPERATION IN SPI MODE 0,0
6.6.2
OPERATION IN SPI MODE 1,1
In SPI Mode 0,0:
In SPI Mode 1,1:
• SCK idle state = Low (VIL)
• SCK idle state = High (VIH)
• Data is clocked in on the SDI pin on the rising
edge of SCK
• Data is clocked in on the SDI pin on the rising
edge of SCK
• Data is clocked out on the SDO pin on the falling
edge of SCK
• Data is clocked out on the SDO pin on the falling
edge of SCK
7.5V
VIH
VIH
Note: HVC must be at VIHH before start of a Write command and only lowered to VIH or VIL after MTP write cycle
completes (MTPMA bit). Also shadow PD0B:PD0A = ‘00” (so that Band Gap circuitry is operational)
HVC
CS
V
IH
VIL
SCK
Write to
SSPBUF
CMDERR bit
bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14
SDO
bit1
bit0
••• ••• ••• •••
••• ••• ••• •••
AD4 AD3 AD2 AD1 AD0
bit23 bit22 bit21 bit20 bit19
D16 D15 D14
bit16 bit15 bit14
D1
bit1
D0
SDI
bit0
C1 C0
Input
Sample
FIGURE 6-2:
24-Bit Commands (Write, Read) - SPI Waveform (Mode 0,0).
7.5V
VIH
VIH
Note: HVC must be at VIHH before start of a Write command and only lowered to VIH or VIL after MTP write cycle
completes (MTPMA bit). Also shadow PD0B:PD0A = ‘00” (so that Band Gap circuitry is operational)
HVC
CS
VIH
VIL
SCK
Write to
SSPBUF
CMDERR bit
SDO
SDI
bit23 bit22 bit21 bit20 bit19 bit18 bit17 bit16 bit15 bit14
bit1
bit0
••• ••• ••• •••
••• ••• ••• •••
AD4 AD3 AD2 AD1 AD0
bit23 bit22 bit21 bit20
D16 D15 D14
bit16 bit15 bit14
D1
D0
bit1
bit0
bit19
C1 C0
Input
Sample
FIGURE 6-3:
24-Bit Commands (Write, Read) - SPI Waveform (Mode 1,1).
2019 Microchip Technology Inc.
DS20006160A-page 67
MCP48CXBXX
NOTES:
DS20006160A-page 68
2019 Microchip Technology Inc.
MCP48CXBXX
TABLE 7-1:
COMMAND BITS OVERVIEW
7.0
DEVICE COMMANDS
Bit States
C1:C0
# of
The MCP48CXBXX’s SPI command format supports
32 memory address locations and two commands.
The command may have two modes. These are:
Command
Normal or HV
Bits
24-Bits Normal only(1)
Read Data
Write Data
Reserved
Reserved
11
00
01
10
• Normal Serial Commands
• MTP Programming (HV) Serial Commands
24-Bits
—
Both
—
Normal serial commands are those where the HVC pin
is driven to either VIH or VIL. With High-Voltage Serial
commands, the HVC pin is driven to 7.5V. These
commands are shown in Table 7-1.
—
—
Note 1: Reading from the NV memory locations
will return the shadow RAM value of the
NV memory, not the NV memory contents.
Once a write cycle starts, no other com-
mands accessing NV memory locations
are allowed.
Table 7-2 shows an overview of all the SPI commands
and their interaction with other device features.
The 24-bit commands (Read Command and Write
Command) contain a Command Byte and a Data
Word. The Command Byte contains one reserved bit,
see Figure 7-1.
Command Byte
Data Word (2 bytes)
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
X
X
X
X
4
3
2
1
0
1
11 10 09 08 07 06 05 04 03 02 01 00
AD
n
C
n
D
nn
Legend:
Memory Address
Command Bits
Data Bits
X Reserved
FIGURE 7-1:
24-bit SPI Command Format.
TABLE 7-2:
SPI COMMANDS - NUMBER OF CLOCKS
Command
Data Update Rate
(8-bit/10-bit/12-bit)
(Data Words/Second)
Code
# of Bit
Clocks
Comments
(2)
(1)
Operation
Mode
HV
C1 C0
1 MHz
10 MHz
50 MHz
(4,7)
Write Command(3,6)
Read Command(5)
0 0
0 0
1 1
1 1
Y
N
N
N
Single
24
41,666 416,666 2,083,333
Continuous
Random
24 * n
24
41,666 416,666 2,083,333 For 10 data words
41,666 416,666 2,083,333
Continuous
24 * n
41,666 416,666 2,083,333 For 10 data words
Note 1: Nonvolatile registers can only use the Single mode.
2: “n” indicates the number of times the command operation is to be repeated.
3: The registers are updated after the 24th clock bit or after the CS rising, depending on mode.
4: If the state of the HVC pin is VIHH, then the command is ignored, but a Command Error condition (CMDERR)
will NOT be generated.
5: This command is useful to determine when an MTP programming cycle has completed.
6: This command can be either normal voltage or high voltage.
7: The MTP write cycle starts after the CS rising edge. A High-Voltage command requires the HVC pin to be at
VIHH for the entire command, until the completion of the MTP write cycle.
2019 Microchip Technology Inc.
DS20006160A-page 69
MCP48CXBXX
SPI is more susceptible to noise than other bus
protocols. The most likely case is that this noise
corrupts the value of the data being clocked into the
MCP48CXBXX or the SCK pin is injected with extra
clock pulses. This may cause data to be corrupted in
the device, or a command error to occur, since the
address and command bits were not a valid combina-
tion. The extra SCK pulse will also cause the SPI data
(SDI) and clock (SCK) to be out of sync. Forcing the
CS pin to the Inactive state (VIH) resets the serial inter-
face. The SPI interface will ignore activity on the SDI
and SCK pins until the CS pin transition to the active
state is detected (VIH to VIL).
7.1
Command Byte
The Command Byte has three fields, the Address (5
bits), the Command (2 bits), and 1 Reserved bit, see
Figure 7-1.
The device memory is accessed when the master
sends a proper Command Byte to select the desired
operation. The memory location getting accessed is
contained in the Command Byte’s AD4:AD0 bits. The
action desired is contained in the Command Byte’s
C1:C0 bits, see Figure 7-5. C1:C0 determines if the
desired memory location will be read or written.
As the Command Byte is loaded into the device (on
the SDI pin), the device’s SDO pin drives. The SDO
pin will output high bits for the first seven bits of that
command. On the 8th bit, the SDO pin will output the
CMDERR bit state.
Note 1: When the MCP48CXBXX does not
receive data, it is recommended that the
CS pin be forced to the inactive level (VIL).
7.4
Continuous Commands
7.2
Data Bytes
The device supports the ability to execute commands
continuously. While the CS pin is in Active state (VIL),
any sequence of valid commands may be received.
The Read and Write commands use Data Bytes, see
Figure 7-1. The D16 bit is currently unused, and
corresponds to the position on the SDO data of the
CMDERR bit.
The following example is a valid sequence of events:
1. CS pin driven active (VIL)
2. Read command
7.3
Error Condition
3. Write command (Volatile memory)
4. Write command (Nonvolatile memory)
5. CS pin driven inactive (VIH)
The CMDERR bit indicates if the five address bits
received (AD4:AD0) and the two command bits
received (C1:C0) are
a valid combination. The
CMDERR bit is high if the combination is valid and low
if the combination is invalid.
Note 1: While the CS pin is active, only one type of
command should be issued. When
changing commands, it is recommended
to take the CS pin inactive then force it
back to the active state.
The command error bit will also be low if a write to a
nonvolatile address has been specified and another
SPI command occurs before the CS pin is driven
inactive (VIH).
2: Long command strings should be broken
down into shorter command strings. This
reduces the probability of noise on the
SCK pin corrupting the desired SPI
command string.
SPI commands that do not have a multiple of 24
clocks are ignored.
Once an error condition has occurred, any following
commands are ignored. All following SDO bits will be
low until the CMDERR condition is cleared by forcing
the CS pin to the Inactive state (VIH) or doing a POR.
7.5
Write Command
The Write command is a 24-bit command. The Write
command can be issued to both the volatile and non-
volatile memory locations. The format of the command
is shown in Figure 7-2.
7.3.1
ABORTING A TRANSMISSION
All SPI transmissions must have the correct number of
SCK pulses to be executed. The command is not
executed until the complete number of clocks have
been received. Some commands also require the CS
pin to be forced inactive (VIH). If the CS pin is forced to
the Inactive state (VIH), the serial interface is reset.
Partial commands are not executed.
A Write command to a volatile memory location
changes that location after a properly formatted Write
command (24-clock) has been received.
A Write command to a nonvolatile memory location will
only start a write cycle after a properly formatted Write
command (24-clock) has been received and the CS
pin transitions to the Inactive state (VIH).
Note: Writes to volatile memory locations depend
on the state of the WiperLock™ Technology
bits.
DS20006160A-page 70
2019 Microchip Technology Inc.
MCP48CXBXX
A write cycle will not start if the write command isn’t
exactly 24 clock’s pulses. This protects against system
issues from corrupting the nonvolatile memory
locations.
7.5.1
SINGLE WRITE TO VOLATILE
MEMORY
The write operation requires that the CS pin be in the
Active state (VIL). Typically, the CS pin is in the Inac-
tive state (VIH) and is driven to the Active state (VIL).
The 24-bit Write command (Command Byte and Data
Bytes) is then clocked in on the SCK and SDI pins.
Once all 24 bits have been received, the specified
volatile address is updated. A write will not occur if the
Write command isn’t exactly 24 clocks pulses. This
protects against system issues from corrupting the
nonvolatile memory locations.
After the CS pin is driven inactive (VIH), the serial
interface may immediately be re-enabled by driving
the CS pin to the Active state (VIL).
During an MTP write cycle, only serial commands to
volatile memory are accepted. All other serial
commands are ignored until the MTP write cycle (twc
)
is completed. The MTPMA bit in the Status register
indicates the status of an MTP Write Cycle.
Figure 7-2 shows the waveform for a single write.
Once a Write command to a nonvolatile memory
location has been received, NO other SPI commands
should be received before the CS pin transitions to the
Inactive state (VIH) or a Command Error (CMDERR)
on the current SPI command occurs.
7.5.2
SINGLE WRITE TO NONVOLATILE
MEMORY
The sequence to write to a single nonvolatile memory
location is the same as a single write to volatile
memory with the exception that before the command,
the HVC pin must be driven to VIHH. After the
command, the CS pin is driven inactive (VIH), which
then starts the MTP write cycle (twc). The HVC pin
must remain at the VIHH level until the completion of
the MTP write cycle.
The write to a Nonvolatile Memory command has the
same format as the write to a Volatile Memory
command (see Figure 7-2).
12-bit data
10-bit data
8-bit data
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
X
X
X
X
4
3
2
1
0
1
0
1
1
11 10 09 08 07 06 05 04 03 02 01 00
SDI
(1)
*
*
*
*
*
0
1
1
*
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(2)
Invalid(3)
SDO
Note 1: For Write commands addressing the DAC Wiper Registers, the Data bits depend on the
resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00.
Data are right justified for easy Host Controller operation (no data manipulation before
transmitting the desired value). The unimplemented bits are ignored.
2: After a valid memory address and a Write command byte are received (CMDERR = ‘1’), all
the following SDO bits will be output as ‘1’.
3: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’
until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).
FIGURE 7-2:
Write Single Memory Location Command - SDI and SDO States.
2019 Microchip Technology Inc.
DS20006160A-page 71
MCP48CXBXX
7.5.3
CONTINUOUS WRITES TO
VOLATILE MEMORY
7.5.4
CONTINUOUS WRITES TO
NONVOLATILE MEMORY
Continuous writes are possible only when writing to
the volatile memory registers.
Continuous writes to nonvolatile memory are not
allowed, and attempts to do so will result in a
command error (CMDERR) condition.
Figure 7-3 shows the sequence for three continuous
writes. The writes do not need to be to the same
volatile memory address.
12-bit data
10-bit data
8-bit data
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
X
X
X
X
4
3
2
1
0
1
0
1
1
11 10 09 08 07 06 05 04 03 02 01 00
SDI
(1)
*
*
*
*
*
0
1
1
*
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(2)
Invalid(3)
SDO
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
*
X
X
X
X
4
3
2
1
0
1
0
1
0
11 10 09 08 07 06 05 04 03 02 01 00
SDI
(1)
*
*
*
*
*
0
1
0
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
1
0
1
0
1
0
1
0
1
(4)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(2)
Invalid(3)
SDO
(3)
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
*
X
X
X
X
4
3
2
1
0
1
0
1
0
11 10 09 08 07 06 05 04 03 02 01 00
SDI
(1)
*
*
*
*
*
0
1
0
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
1
0
1
0
1
0
1
0
1
(4)
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(2)
Invalid(3)
SDO
(3)
Note 1: For Write commands addressing the DAC Wiper Registers, the Data bits depend on the
resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00.
Data are right justified for easy Host Controller operation (no data manipulation before
transmitting the desired value). The unimplemented bits are ignored.
2: After a valid memory address and a Write command byte are received (CMDERR = ‘1’), all
the following SDO bits will be output as ‘1’.
3: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’
until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).
4: This CMDERR bit will be forced to ‘0’, regardless if this Address + Command combination
is valid. This command will not be completed and requires the CS pin to return to VIH to clear
the CMDERR condition.
FIGURE 7-3:
Continuous Write Sequence (Volatile Memory Only).
DS20006160A-page 72
2019 Microchip Technology Inc.
MCP48CXBXX
7.6.1
SINGLE READ
7.6
Read Command
The read operation requires that the CS pin be in the
Active state (VIL). Typically, the CS pin will be in the
Inactive state (VIH) and is driven to the Active state
(VIL). The 24-bit Read command (Command Byte and
Data Word) is then clocked in on the SCK and SDI pins.
The SDO pin starts driving high (VIH) when the CS goes
active and starts driving data on the 8th bit (CMDERR
bit); the addressed data comes out on the 9th through
24th clocks.
The Read command is a 24-bit command. The Read
command can be issued to both the volatile and
nonvolatile memory locations. The format of the
command is shown in Figure 7-4.
The first 7 bits of the Read command determine the
address and the command. The 8th clock will output
the CMDERR bit on the SDO pin. For the remaining 16
clocks, the device will transmit the data bits of the
specified address (AD4:AD0).
Figure 7-4 shows the SDI and SDO information for a
Read command.
During an MTP write cycle, the Read command can
only be issued to the volatile memory locations. By
reading the Status register, the Host Controller can
determine when the write cycle has been completed
(via the state of the MTPMA bit).
12-bit data
10-bit data
8-bit data
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
X
X
X
X
4
3
2
1
0
1
1
1
1
11 10 09 08 07 06 05 04 03 02 01 00
SDI
*
*
*
*
*
1
1
1
*
*
*
*
*
*
*
d
0
*
*
d
0
*
*
d
0
*
*
d
0
*
*
d
0
*
*
d
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
d
0
d
0
d
0
d
0
d
0
d
0
Valid(1)
Invalid(2)
SDO
Note 1: The Data bits depend on the resolution of the device: 12-bit = D11:D00,
10-bit = D09:D00, and 8-bit = D07:D00.
The unimplemented bits are output as ‘0’ and data are right justified for easy Host Controller
operation (no data manipulation after reading the register value).
2: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’
until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).
FIGURE 7-4:
Read Single Memory Location Command - SDI and SDO States.
2019 Microchip Technology Inc.
DS20006160A-page 73
MCP48CXBXX
7.6.2
CONTINUOUS READS
Continuous reads allows the devices memory to be
read quickly. Continuous reads are possible to all
memory locations. Read commands may only access
volatile memory locations during an MTP Write Cycle.
Figure 7-5 shows the sequence for three continuous
reads. The reads do not need to be to the same
memory address.
12-bit data
10-bit data
8-bit data
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
X
X
X
X
4
3
2
1
0
1
0
1
1
11 10 09 08 07 06 05 04 03 02 01 00
SDI
*
*
*
*
*
0
1
1
*
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(1)
Invalid(2)
SDO
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
*
X
X
X
X
4
3
2
1
0
1
0
1
0
11 10 09 08 07 06 05 04 03 02 01 00
SDI
*
*
*
*
*
0
1
0
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
0
1
0
1
0
1
0
1
0
1
(3)
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(1)
Invalid(2)
SDO
AD AD AD AD AD C
C
0
D
D
D
D
D
D
D
D
D
D
D
D
X
*
X
X
X
X
4
3
2
1
0
1
0
1
0
11 10 09 08 07 06 05 04 03 02 01 00
SDI
*
*
*
*
*
0
1
0
*
*
*
*
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
*
*
1
0
1
0
1
0
1
0
1
0
1
0
1
(3)
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Valid(1)
Invalid(2)
SDO
Note 1: The Data bits depend on the resolution of the device: 12-bit = D11:D00,
10-bit = D09:D00, and 8-bit = D07:D00.
The unimplemented bits are output as ‘0’ and data are right justified for easy Host Controller
operation (no data manipulation after reading the register value).
2: If an Error Condition occurs (CMDERR = ‘0’), all the following SDO bits will be output as ‘0’
until the CMDERR condition is cleared (the CS pin is forced to the Inactive state).
3: This CMDERR bit will be forced to ‘0’, regardless if this Address + Command combination
is valid. This command will not be completed and requires the CS pin to return to VIH to clear
the CMDERR condition.
FIGURE 7-5:
Continuous Read Sequence.
DS20006160A-page 74
2019 Microchip Technology Inc.
MCP48CXBXX
8.0
TYPICAL APPLICATIONS
The MCP48CXBXX devices are general purpose,
single/dual-channel voltage output DACs for various
applications where a precision operation with low power is
needed.
VDD
SDI
V
1
2
3
10
9
DD
C1
C2 CS
SCK
SDO
To MCU
VREF
8
Applications generally suited for the devices are:
VOUT0
4
5
7
VSS
Analog
Output
• Set Point or Offset Trimming
• Sensor Calibration
VOUT1
6 LAT/HVC
MCP48CXBX2
C3
C4
• Portable Instrumentation (Battery-Powered)
• Motor Control
Optional
(a) Circuit when VDD is selected as reference.
8.1
Design Considerations
(Note: V is connected to the reference circuit internally.)
DD
V
DD
In the design of a system with the MCP48CXBXX
devices, the following considerations should be taken
into account:
C1
C2
SDI
1
2
3
10
9
VDD
CS
• Power Supply Considerations
• Layout Considerations
SCK
SDO
VREF
To MCU
8
VREF
8.1.1
POWER SUPPLY
CONSIDERATIONS
C5
Optional
VOUT0
C6
4
5
7
6
VSS
VOUT1
LAT/HVC
The power source supplying these devices must be as
clean as possible. If the application circuit has separate
digital and analog power supplies, VDD and VSS may
reside on the analog plane.
Analog
Output
MCP48CXBX2
C3
C4
Optional
The power supply to the device is also used for the
DAC voltage reference internally if the internal VDD is
selected as the resistor ladder’s reference voltage.
(b) Circuit when external reference is used.
C : 0.1 µF capacitor
Ceramic
=
=
=
1
The typical application requires a bypass capacitor in
order to filter high-frequency noise, which can be
induced onto the power supply's traces. The bypass
capacitor helps to minimize the effect of these noise
sources on signal integrity.
C : 10 µF capacitor
Tantalum
2
C : ~ 0.1 µF
Optional to reduce noise
3
in V
pin.
OUT
C : 0.1 µF capacitor
Ceramic
=
=
=
4
Any noise induced on the VDD line can affect the DAC
performance. Typical applications require a bypass
capacitor in order to filter out high-frequency noise on
the VDD line. The noise can be induced onto the power
supply’s traces or as a result of changes on the DAC out-
put. The bypass capacitor helps to minimize the effect of
these noise sources on signal integrity. Figure 8-1
shows an example of using two bypass capacitors (a
10 µF tantalum capacitor and a 0.1 µF ceramic capaci-
tor) in parallel on the VDD line. These capacitors should
be placed as close to the VDD pin as possible (within
4 mm). If the application circuit has separate digital and
analog power supplies, the VDD and VSS pins of the
device should reside on the analog plane.
C : 10 µF capacitor
Tantalum
Ceramic
5
C : 0.1 µF capacitor
6
FIGURE 8-1:
Example Circuit.
2019 Microchip Technology Inc.
DS20006160A-page 75
MCP48CXBXX
8.1.2
LAYOUT CONSIDERATIONS
8.1.2.2
PCB Area Requirements
Several layout considerations may be applicable to
your application. These may include:
In some applications, PCB area is a criteria for device
selection. Table 8-1 shows the typical package
dimensions and area for the different package options.
• Noise
)
PACKAGE FOOTPRINT(1
• PCB Area Requirements
TABLE 8-1:
Package
Package Footprint
8.1.2.1
Noise
Inductively-coupled AC transients and digital switching
noise can degrade the input and output signal integrity,
potentially masking the MCP48CXBXX’s performance.
Careful board layout minimizes these effects and
increases the Signal-to-Noise Ratio (SNR). Multilayer
Dimensions
(mm)
Type
Code
Area (mm2)
Length Width
10 MSOP
10 DFN
16 QFN
UN
MF
MG
3.00
3.00
3.00
4.90
3.00
3.00
14.70
9.00
9.00
boards utilizing
a low-inductance ground plane,
isolated inputs, isolated outputs and proper decoupling
are critical to achieving the performance that the silicon
is capable of providing. Particularly harsh
environments may require shielding of critical signals.
Note 1: Does not include recommended land
pattern dimensions. Dimensions are
typical values.
Separate digital and analog ground planes are
recommended. In this case, the VSS pin and the ground
pins of the VDD capacitors must be terminated to the
analog ground plane.
Note:
Breadboards and wire-wrapped boards
are not recommended.
DS20006160A-page 76
2019 Microchip Technology Inc.
MCP48CXBXX
8.2.1.1
Decreasing Output Step Size
8.2
Application Examples
If the application calibrates the bias voltage of a diode
or transistor, a bias voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common methods to achieve small step size are to use
a lower VREF pin voltage or a voltage divider on the
DAC’s output.
The MCP48CXBXX devices are rail-to-rail output
DACs designed to operate with a VDD range of 2.7V to
5.5V. The internal output amplifier is robust enough to
drive common, small-signal loads directly, thus
eliminating the cost and size of the external buffers for
most applications. The user can select the gain of 1 or
2 of the output op amp by setting the Configuration
register bits. The internal VDD or an external reference
can be used. Various user options and easy-to-use
features that make the devices suitable for various
modern DAC applications.
Using an external voltage reference (VREF) is an option
if the external reference is available with the desired
output voltage range. However, when using
a
low-voltage reference voltage, occasionally the noise
floor causes an SNR error that is intolerable. Using a
voltage divider method is another option, and provides
some advantages when the external voltage reference
needs to be very low, or when the desired output
voltage is not available. In this case, a larger value
reference voltage is used, while two resistors scale the
output range down to the precise desired level.
Application examples include:
• Decreasing Output Step Size
• Building a “Window” DAC
• Bipolar Operation
• Selectable Gain and Offset Bipolar Voltage Output
• Designing a Double-Precision DAC
• Building Programmable Current Source
• Serial Interface Communication Times
• Development Support
Figure 8-2 illustrates this concept. A bypass capacitor
on the output of the voltage divider plays a critical
function in attenuating the output noise of the DAC and
the induced noise from the environment.
• Power Supply Considerations
• Layout Considerations
VDD
8.2.1
DC SET POINT OR CALIBRATION
Optional
A
common application for the devices is
a
RSENSE
VREF VDD
digitally-controlled set point and/or calibration of
variable parameters, such as sensor offset or slope.
For example, the MCP48CVB2X provides 4096 output
steps. If voltage reference is 4.096V (where GX = ‘0’),
the LSb size is 1 mV. If a smaller output step size is
desired, a lower external voltage reference is needed.
VCC
+
VOUT
R1
VTRIP
Comp.
VCC
MCP48CVBXX
VO
C1
–
R2
SPI
2-wire
FIGURE 8-2:
Example Circuit Of Set Point
or Threshold Calibration.
EQUATION 8-1: OUT AND VTRIP
V
CALCULATIONS
DAC Register Value
VOUT = VREF • G •
2N
R
2
V
= V
--------------------
trip
OUT
R + R
1
2
2019 Microchip Technology Inc.
DS20006160A-page 77
MCP48CXBXX
8.2.1.2
Building a “Window” DAC
8.3
Bipolar Operation
When calibrating a set point or threshold of a sensor,
typically only a small portion of the DAC output range is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
Bipolar operation is achievable by utilizing an external
operational amplifier. This configuration is desirable
due to the wide variety and availability of op amps. This
allows a general purpose DAC, with its cost and
availability advantages, to meet almost any desired
output voltage range, power and noise performance.
Figure 8-4 illustrates a simple bipolar voltage source
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC's output to a selected
offset. Note that R4 can be tied to VDD instead of VSS if
a higher offset is desired.
If the threshold is not near VREF, 2 • VREF, or VSS, then
creating a “window” around the threshold has several
advantages. One simple method to create this “window”
is to use a voltage divider network with a pull-up and
pull-down resistor. Figure 8-3 and Figure 8-5 illustrate
this concept.
Optional
VREF
VDD
VCC
+
R3
VOUT
VOA+
C1
Optional
VCC
+
RSENSE
VO
MCP48CVBXX
VREF
VDD
VCC
VTRIP Comp.
C1
+
R4
R3
R2
VO
SPI
2-wire
VCC
–
R1
VOUT
MCP48CVBXX
R2
VCC–
VIN
SPI
2-wire
R1
VCC
–
FIGURE 8-4:
Voltage Source Example Circuit.
Digitally-Controlled Bipolar
FIGURE 8-3:
DAC.
Single-Supply “Window”
EQUATION 8-3: OUT, VOA+, AND VO
V
EQUATION 8-2:
VOUT AND VTRIP
CALCULATIONS
CALCULATIONS
DAC Register Value
2N
DAC Register Value
VOUT = VREF • G •
VOUT = VREF • G •
2N
V
R
+ V
R
VOUT • R4
R3 + R4
OUT 23
23 1
V
= --------------------------------------------------
VOA+
=
TRIP
R + R
1
23
R2R3
R23 = ------------------
R2 + R3
R2
R1
R2
R1
VO = VOA+ • (1 +
) - VDD • (
)
Thevenin
Equivalent
VCC+R2 + VCC-R3
V23 = ------------------------------------------------------
R2 + R3
R1
VOUT
VTRIP
R23
V23
DS20006160A-page 78
2019 Microchip Technology Inc.
MCP48CXBXX
8.4
Selectable Gain and Offset Bipolar
Voltage Output
Optional
VCC
+
In some applications, precision digital control of the
output range is desirable. Figure 8-5 illustrates how to
use the DAC devices to achieve this in a bipolar or
single-supply application.
Optional
VREF VDD
R5
VCC
+
R3
VOA+
C1
This circuit is typically used for linearizing a sensor
whose slope and offset varies.
VOUT
MCP48CVBXX
VO
R4
VCC
VIN
The equation to design a bipolar “window” DAC would
be utilized if R3, R4 and R5 are populated.
SPI
2-wire
VCC
–
–
8.4.1
BIPOLAR DAC EXAMPLE
R2
An output step size of 1 mV, with an output range of
±2.05V, is desired for a particular application.
R1
Step 1: Calculate the range: +2.05V – (-2.05V) = 4.1V
Step 2: Calculate the resolution needed:
4.1V/1 mV = 4100
C1 = 0.1 µF
FIGURE 8-5:
Bipolar Voltage Source with
Selectable Gain and Offset.
Since 212 = 4096, 12-bit resolution is desired.
Step 3: The amplifier gain (R2/R1), multiplied by
full-scale VOUT (4.096V), must be equal to
the desired minimum output to achieve bipo-
lar operation. Since any gain can be realized
by choosing resistor values (R1 + R2), the
EQUATION 8-6: OUT, VOA+, AND VO
V
CALCULATIONS
DAC Register Value
VOUT = VREF • G •
VREF value must be selected first. If a VREF
2N
VOUT • R4 + VCC- • R5
R3 + R4
of 4.096V is used, solve for the amplifier’s
gain by setting the DAC to 0, knowing that
the output needs to be -2.05V.
VOA+
=
R2
R2
R1
The equation can be simplified to:
VO = VOA+ • (1 +
) - VIN • (
)
R1
EQUATION 8-4:
Offset Adjust
Gain Adjust
–R2
R2
----- = --
R1 2
–2.05
4.096V
1
-------- = ----------------
R1
EQUATION 8-7:
BIPOLAR “WINDOW” DAC
USING R4 AND R5
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
VCC+R4 + VCC-R5
Thevenin
Equivalent
Step 4: Next, solve for R3 and R4 by setting the
DAC to 4096, knowing that the output
needs to be +2.05V.
V45 = --------------------------------------------
R4 + R5
VOUTR45 + V45R3
VIN+ = --------------------------------------------
R3 + R45
EQUATION 8-5:
R4
2.05V + 0.5 4.096V
2
3
R4R5
----------------------- = ------------------------------------------------------- = --
R45 = ------------------
R4 + R5
R3 + R4
1.5 4.096V
If R4 = 20 k, then R3 = 10 k
R2
R2
A
R1
VO = V
1 + ----- – V -----
IN+
R1
Offset Adjust Gain Adjust
2019 Microchip Technology Inc.
DS20006160A-page 79
MCP48CXBXX
8.5
Designing a Double-Precision
DAC
8.6
Building Programmable Current
Source
Figure 8-6 shows an example design of a single-supply
voltage output capable of up to 24-bit resolution. This
requires two 12-bit DACs. This design is simply a
voltage divider with a buffered output.
Figure 8-7 shows an example of building
a
programmable current source using a voltage follower.
The current sensor resistor is used to convert the DAC
voltage output into a digitally-selectable current source.
As an example, if a similar application to the one
developed in Section 8.4.1 “Bipolar DAC Example”
required a resolution of 1 µV instead of 1 mV, and a
range of 0V to 4.1V, then a 12-bit resolution would not
be adequate.
The smaller RSENSE is, the less power is dissipated
across it. However, this also reduces the resolution that
the current can be controlled at.
VDD
Step1: Calculate the resolution needed:
(or VREF
)
Optional
4.1V/1 µV = 4.1 x 106
VREF
VDD
Since 222 = 4.2 x 106, a 22-bit resolution is
desired. Since DNL = ±1.0 LSb, this design
can be attempted with the 12-bit DAC.
Load
VCC+
VOUT
IL
MCP48CVBXX
Step2: Since DAC1’s VOUT1 has a resolution of
1 mV, its output only needs to be “pulled”
1/1000 to meet the 1 µV target. Dividing
VOUT0 by 1000 would allow the application
to compensate for DAC1’s DNL error.
Ib
VCC–
SPI
2-wire
IL
RSENSE
Step3: If R2 is 100, then R1 needs to be 100 k.
Ib = ----
Step4: The resulting transfer function is shown in
VOUT
Equation 8-8.
IL = -------------- ------------
Rsense + 1
Optional
where Common-Emitter Current Gain
VDD
VREF
FIGURE 8-7:
Digitally-Controlled Current
Source.
VOUT0
R1
MCP48CVBX2
(DAC0)
8.7
Serial Interface Communication
Times
SPI
VCC+
2-wire
Table 7-2 shows the time/frequency of the supported
operations of the SPI Serial Interface for the different
serial interface operational frequencies. This, along
with the VOUT output performance (such as slew rate),
would be used to determine your application’s volatile
DAC register update rate.
VOUT
Optional
VREF VDD
0.1 µF
R2
VCC
–
MCP48CVBX2
(DAC1)
VOUT1
SPI
2-wire
FIGURE 8-6:
Simple Double Precision
DAC Using MCP48CVBX2.
EQUATION 8-8:
VOUT
V
OUT CALCULATION
VOUT0 R + V
R
*
1
*
2
OUT1
=
R1 + R2
Where:
VOUT0 = (VREF G DAC0 register value)/4096
VOUT1 = (VREF G DAC1 register value)/4096
GX = Selected Op Amp Gain
DS20006160A-page 80
2019 Microchip Technology Inc.
MCP48CXBXX
The ADM00309 boards may be purchased directly
from the Microchip web site at www.microchip.com.
9.0
DEVELOPMENT SUPPORT
Development support can be classified into two groups:
• Development Tools
9.2
Technical Documentation
• Technical Documentation
Several additional technical documents for design and
development are available. These technical
documents include Application Notes, Technical Briefs,
and Design Guides. Table 9-2 lists some of these
documents.
9.1
Development Tools
Several development tools are available to assist in the
design and evaluation of the MCP48CXBXX devices.
The currently available tools are shown in Table 9-1.
Figure 9-1 shows how the ADM00309 bond-out PCB
can be populated to easily evaluate the MCP48CXBXX
devices. Device evaluation can use the PICkit™ Serial
Analyzer to control the DAC output registers and state
of the Configuration, Control and Status register.
TABLE 9-1:
DEVELOPMENT TOOLS (Note 1)
Board Name
MSOP-8 and MSOP-10 Evaluation Board
Part #
Comment
ADM00309
The MSOP-10 and MSOP-8 Evaluation Board is a
bond-out board that allows the system designer to
quickly evaluate the operation of Microchip
Technology’s devices in any of the following packages:
• MSOP (8/10-pin)
• DIP (10-pin)
Note 1: Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.
TABLE 9-2:
TECHNICAL DOCUMENTATION
Application
Note Number
Title
Literature #
AN1326
Using the MCP4728 12-Bit DAC for LDMOS Amplifier Bias Control Applications
Signal Chain Design Guide
DS01326
DS21825
DS01005
—
—
Analog Solutions for Automotive Applications Design Guide
2019 Microchip Technology Inc.
DS20006160A-page 81
MCP48CXBXX
MCP48CXBXX in MSOP-10 package
installed in U1 footprint
Connected to
Digital Ground
(DGND) Plane
Connected to
Digital Power (VL) Plane
0
V
SDI
1.0µF
DD
SCK
SDO
CS
V
REF
V
V
SS
OUT0
OUT1
0
NC/V
LAT/HVC
Two wire jumpers to connect the
PICkit™ Serial Interface (SPI) to device pins
1 x 6 male header, with 90° right angle
FIGURE 9-1:
MCP48CXBXX Evaluation Board Circuit Using ADM00309.
DS20006160A-page 82
2019 Microchip Technology Inc.
MCP48CXBXX
10.0 PACKAGING INFORMATION
10.1 Package Marking Information
10-Lead MSOP
Example
48CV01
908256
10-Lead 3 x 3 mm DFN
Example
Part Number
Code
BAKH
1908
256
MCP48CVB01-E/MF
MCP48CVB11-E/MF
MCP48CVB21-E/MF
MCP48CVB02-E/MF
MCP48CVB12-E/MF
MCP48CVB22-E/MF
MCP48CMB01-E/MF
MCP48CMB11-E/MF
MCP48CMB21-E/MF
MCP48CMB02-E/MF
MCP48CMB12-E/MF
MCP48CMB22-E/MF
BAKH
BAKL
BAKN
BAKJ
BAKM
BAKP
BAKB
BAKD
BAKF
BAKC
BAKE
BAKG
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
e
3
e
3
*
)
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2019 Microchip Technology Inc.
DS20006160A-page 83
MCP48CXBXX
Example
16-Lead 3 x 3 mm QFN
Part Number
Code
ANN
1908
256
MCP48CVB01-E/MG
MCP48CVB11-E/MG
MCP48CVB21-E/MG
MCP48CVB02-E/MG
MCP48CVB12-E/MG
MCP48CVB22-E/MG
MCP48CMB01-E/MG
MCP48CMB11-E/MG
MCP48CMB21-E/MG
MCP48CMB02-E/MG
MCP48CMB12-E/MG
MCP48CMB22-E/MG
ANN
APP
ARR
AAK
AAL
AAM
AKK
ALL
AMM
AAG
AAH
AAJ
DS20006160A-page 84
2019 Microchip Technology Inc.
MCP48CXBXX
UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006160A-page 85
MCP48CXBXX
UN
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006160A-page 86
2019 Microchip Technology Inc.
MCP48CXBXX
10-Lead Plastic Micro Small Outline Package (UN) [MSOP]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006160A-page 87
MCP48CXBXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006160A-page 88
2019 Microchip Technology Inc.
MCP48CXBXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006160A-page 89
MCP48CXBXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006160A-page 90
2019 Microchip Technology Inc.
MCP48CXBXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006160A-page 91
MCP48CXBXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20006160A-page 92
2019 Microchip Technology Inc.
MCP48CXBXX
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2019 Microchip Technology Inc.
DS20006160A-page 93
MCP48CXBXX
NOTES:
DS20006160A-page 94
2019 Microchip Technology Inc.
MCP48CXBXX
APPENDIX A: REVISION HISTORY
Revision A (February 2019)
• Original release of this document.
2019 Microchip Technology Inc.
DS20006160A-page 95
MCP48CXBXX
NOTES:
DS20006160A-page 96
2019 Microchip Technology Inc.
MCP48CXBXX
B.3
Monotonic Operation
APPENDIX B: TERMINOLOGY
The monotonic operation means that the device’s
output voltage (VOUT) increases with every 1 code step
(LSb) increment (from VSS to the DAC’s reference
voltage (VDD or VREF)).
B.1
Resolution
The resolution is the number of DAC output states that
divide the full-scale range. For the 12-bit DAC, the
resolution is 212, meaning the DAC code ranges from
0 to 4095.
VS64
40h
3Fh
VS63
Note:
When there are 2N resistors in the resistor
ladder and 2N tap points, the full-scale
DAC register code is the resistor element
(1 LSb) from the source reference voltage
(VDD or VREF).
3Eh
VS3
03h
02h
VS1
B.2
Least Significant Bit (LSb)
VS0
01h
This is the voltage difference between two successive
codes. For a given output voltage range, it is divided by
the resolution of the device (Equation B-1). The range
may be VDD (or VREF) to VSS (ideal), the DAC register
codes across the linear range of the output driver
(Measured 1), or full-scale to zero-scale (Measured 2).
00h
VW (@ tap)
n = ?
VW
=
VSn + VZS(@ Tap 0)
n = 0
Voltage (VW ~= VOUT
)
EQUATION B-1:
LSb VOLTAGE
CALCULATION
FIGURE B-1:
B.4
VW (VOUT).
Ideal:
Full-Scale Error (E )
VDD
VLSbIDEAL = ---------- or ------------
2N 2N
VREF
FS
The Full-Scale Error (see Figure B-3) is the error on
the VOUT pin relative to the expected VOUT voltage
(theoretical) for the maximum device DAC register
code (code FFFh for 12-bit, code 3FFh for 10-bit, and
code FFh for 8-bit) (see Equation B-2). The error is
dependent on the resistive load on the VOUT pin (and
where that load is tied to, such as VSS or VDD). For
loads (to VSS) greater than specified, the full-scale
error will be greater.
Measured 1 (12-bit device):
VOUT(@4032) – VOUT(@64)
VLSbMeasured = --------------------------------------------------------------
4032 – 64
Measured 2:
VOUT(@FS) – VOUT(@ZS)
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
VLSb = ----------------------------------------------------------
2N – 1
2N = 4096 (MCP48CXB2X)
= 1024 (MCP48CXB1X)
= 256 (MCP48CXB0X)
EQUATION B-2:
FULL-SCALE ERROR
VOUT(@FS) – VIDEAL(@FS)
EFS = ---------------------------------------------------------------
VLSbIDEAL
Where:
E
is expressed in LSb
FS
V
is the V
voltage when the DAC
OUT
OUT(@FS)
register code is at full-scale.
V
V
is the ideal output voltage when the
DAC register code is at full-scale.
IDEAL(@FS)
is the theoretical voltage step size.
LSb(IDEAL)
2019 Microchip Technology Inc.
DS20006160A-page 97
MCP48CXBXX
B.5
Zero-Scale Error (E )
B.7
Offset Error (E
)
OS
ZS
The Zero-Scale Error (see Figure B-2) is the difference
between the ideal and measured VOUT voltage with the
DAC register code equal to 000h (Equation B-3). The
error is dependent on the resistive load on the VOUT pin
(and where that load is tied to, such as VSS or VDD). For
loads (to VDD) greater than specified, the Zero-Scale
Error is greater.
The Offset Error is the delta voltage of the VOUT
voltage from the ideal output voltage at the specified
code. This code is specified where the output amplifier
is in the linear operating range; for the MCP48CXBXX
we specify code 64 (decimal). Offset Error does not
include gain error, which is illustrated in Figure B-2.
This error is expressed in mV. Offset Error can be
negative or positive. The error can be calibrated by
software in application circuits.
The error in bits is determined by the theoretical voltage
step size to give an error in LSb.
EQUATION B-3:
ZERO SCALE ERROR
VOUT(@ZS)
EZS = ---------------------------
VLSb(IDEAL)
Actual
Transfer
Function
Where:
E
is expressed in LSb.
FS
V
is the V
voltage when the DAC
OUT
OUT(@ZS)
register code is at Zero-Scale.
V
is the theoretical voltage step size.
LSb(IDEAL)
Zero-Scale
Ideal Transfer
Function
Error (E
)
ZS
B.6
Total Unadjusted Error (E )
T
0
64
4032
DAC Input Code
Offset
Error (E
The Total Unadjusted Error (ET) is the difference
between the ideal and measured VOUT voltage.
Typically, calibration of the output voltage is
implemented to improve the system’s performance.
)
OS
FIGURE B-2:
GAIN ERROR).
OFFSET ERROR (ZERO
The error in bits is determined by the theortical voltage
step size to give an error in LSb.
B.8
Offset Error Drift (E
)
OSD
Equation B-4 shows the Total Unadjusted Error
calculation
The Offset Error Drift is the variation in Offset Error due
to a change in ambient temperature. The Offset Error
Drift is typically expressed in ppm/°C or µV/°C.
EQUATION B-4:
TOTAL UNADJUSTED
ERROR CALCULATION
B.9
Gain Error (E )
G
VOUT_Actual(@code) – VOUT_Ideal(@code)
ET = -------------------------------------------------------------------------------------------------
VLSbIdeal
Gain Error is a calculation based on the ideal slope
using the voltage boundaries for the linear range of the
output driver (e.g., code 64 and code 4032) (see
Figure B-3). The Gain Error calculation nullifies the
device’s Offset Error.
Where:
ET is expressed in LSb.
VOUT_Actual(@code) = The measured DAC
output voltage at the
The Gain Error indicates how well the slope of the
actual transfer function matches the slope of the ideal
transfer function. The Gain Error is usually expressed
as a percentage of full-scale range (% of FSR) or in
LSb. FSR is the ideal full-scale voltage of the DAC (see
Equation B-5).
specified code
VOUT_Ideal(@code) = The calculated DAC
output voltage at the
specified code
( code * VLSb(Ideal)
)
VLSb(Ideal) = VREF/# Steps
12-bit = VREF/4096
10-bit = VREF/1024
8-bit = VREF/256
DS20006160A-page 98
2019 Microchip Technology Inc.
MCP48CXBXX
B.11 Integral Nonlinearity (INL)
Gain Error (E )
G
(@ code = 4032)
The Integral Nonlinearity (INL) Error is the maximum
deviation of an actual transfer function from an ideal
transfer function (straight line) passing through the
defined end-points of the DAC transfer function (after
Offset and Gain Errors have been removed).
V
REF
Actual
Transfer
Function
Full-Scale
Error (E
)
FS
For the MCP48CXBXX, INL is calculated using the
defined end-points, DAC code 64 and code 4032. INL
can be expressed as a percentage of FSR or in LSb.
INL is also called relative accuracy. Equation B-6 shows
how to calculate the INL error in LSb and Figure B-4
shows an example of INL accuracy.
Ideal Transfer
Function shifted by
Offset Error
(crosses at start of
defined linear range)
Ideal Transfer
Function
0
64
4032 4095
DAC Input Code
Positive INL means a VOUT voltage higher than the
ideal one. Negative INL means a VOUT voltage lower
than the ideal one.
FIGURE B-3:
GAIN ERROR AND FULL-
SCALE ERROR EXAMPLE.
EQUATION B-6:
INL ERROR
EQUATION B-5:
GAIN ERROR EXAMPLE
VOUT – VCalc_Ideal
VOUT(@4032) – VOS – VOUT_Ideal(@4032)
EINL = --------------------------------------------------
EG = ---------------------------------------------------------------------------------------------------- * 1 0 0
VFull-Scale Range
VLSbMeasured
Where:
Where:
INL is expressed in LSb.
VCalc_Ideal = Code * VLSb(Measured) + VOS
EG is expressed in % of Full-Scale Range (FSR).
VOUT(Code = n) = The measured DAC output
voltage with a given DAC
VOUT(@4032)
=
The measured DAC
output voltage at the
specified code.
register code
VLSb(Measured) = For Measured:
(VOUT(4032) - VOUT(64))/3968
VOUT_Ideal(@4032)
=
The calculated DAC
output voltage at the
specified code.
VOS = Measured offset voltage
(4032 * VLSb(Ideal)
)
VOS
=
=
Measured offset voltage.
VFull-Scale Range
Expected Full-Scale
output value (such as the
VREF voltage).
7
INL = < -1 LSb
INL = - 1 LSb
6
5
B.10 Gain Error Drift (E
)
GD
Analog 4
Output
The Gain Error Drift is the variation in Gain Error due to
a change in ambient temperature. The Gain Error Drift
is typically expressed in ppm/°C (of FSR).
INL = 0.5 LSb
3
2
1
0
(LSb)
000 001 010 011 100 101 110 111
DAC Input Code
Ideal Transfer Function
Actual Transfer Function
FIGURE B-4:
INL ACCURACY.
2019 Microchip Technology Inc.
DS20006160A-page 99
MCP48CXBXX
B.12 Differential Nonlinearity (DNL)
B.14 Major-Code Transition Glitch
The Differential Nonlinearity (DNL) Error (see
Figure B-5) is the measure of step size between codes
in actual transfer function. The ideal step size between
codes is 1 LSb. A DNL Error of zero would imply that
every code is exactly 1 LSb wide. If the DNL Error is
less than 1 LSb, the DAC guarantees monotonic output
and no missing codes. Equation B-7 shows how to cal-
culate the DNL Error between any two adjacent codes
in LSb.
Major-Code transition glitch is the impulse energy
injected into the DAC analog output when the code in
the DAC register changes the state. It is normally
specified as the area of the glitch in nV-Sec and is
measured when the digital code is changed by 1 LSb at
the major carry transition (Example: 011...111 to
100... 000, or 100... 000to 011 ... 111).
B.15 Digital Feed-Through
The digital feed-through is the glitch that appears at the
analog output caused by coupling from the digital input
pins of the device. The area of the glitch is expressed
in nV-Sec and is measured with a full-scale change
(Example: all 0s to all 1s and vice versa) on the digital
input pins. The digital feed-through is measured when
the DAC is not being written to the output register.
EQUATION B-7:
DNL ERROR
VOUT(code = n+1) – VOUT(code = n)
EDNL = ----------------------------------------------------------------------------------- – 1
VLSbMeasured
Where:
DNL is expressed in LSb.
VOUT(Code = n)
=
The measured DAC output
voltage with a given DAC
register code
B.16 -3 dB Bandwidth
This is the frequency of the signal at the VREF pin that
causes the voltage at the VOUT pin to fall to -3 dB from
a static value on the VREF pin. The output decreases
due to the RC characteristics of the resistor ladder and
the characteristics of the output buffer.
VLSb(Measured)
=
For Measured:
(VOUT(4032) - VOUT(64))/3968
B.17 Power-Supply Sensitivity (PSS)
7
6
DNL = 0.5 LSb
PSS indicates how the output of the DAC is affected by
changes in the supply voltage. PSS is the ratio of the
change in VOUT to a change in VDD for mid-scale output
of the DAC. The VOUT is measured while the VDD is
varied from 5.5V to 2.7V as a step (VREF voltage held
constant) and expressed in %/%, which is the %
change of the DAC output voltage with respect to the %
change of the VDD voltage.
5
DNL = 2 LSb
4
3
Analog
Output
(LSb)
2
1
0
EQUATION B-8:
PSS CALCULATION
VOUT(@5.5V) – VOUT(@2.7V) VOUT(@5.5V)
PSS = ---------------------------------------------------------------------------------------------------------
5.5V – 2.7V 5.5V
000 001 010 011 100 101 110 111
DAC Input Code
Where:
PSS is expressed in %/%.
Ideal Transfer Function
Actual Transfer Function
VOUT(@5.5V)
=
The measured DAC output
voltage with VDD = 5.5V
FIGURE B-5:
DNL ACCURACY.
VOUT(@2.7V)
=
The measured DAC output
voltage with VDD = 2.7V
B.13 Settling Time
The Settling time is the time delay required for the VOUT
voltage to settle into its new output value. This time is
measured from the start of code transition to when the
VOUT voltage is within the specified accuracy.
For the MCP48CXBXX, the settling time is a measure
of the time delay until the VOUT voltage reaches within
0.5 LSb of its final value, when the volatile DAC register
changes from 1/4 to 3/4 of the FSR (12-bit device: 400h
to C00h).
DS20006160A-page 100
2019 Microchip Technology Inc.
MCP48CXBXX
B.18 Power-Supply Rejection Ratio
(PSRR)
B.20 Absolute Temperature Coefficient
The absolute temperature coefficient quantifies the
error in the end-to-end output voltage (Nominal output
voltage VOUT) due to temperature drift. For a DAC, this
error is typically not an issue due to the ratiometric
aspect of the output.
PSRR indicates how the output of the DAC is affected
by changes in the supply voltage. PSRR is the ratio of
the change in VOUT to a change in VDD for full-scale
output of the DAC. The VOUT is measured while the
VDD is varied +/-10% (VREF voltage held constant) and
expressed in dB or µV/V.
B.21 Noise Spectral Density
The noise spectral density is a measurement of the
device’s internally generated random noise, and is
characterized as a spectral density (voltage per √Hz).
It is measured by loading the DAC to the mid-scale
value and measuring the noise at the VOUT pin. It is
measured in nV/√Hz.
B.19
V
Temperature Coefficient
OUT
The VOUT temperature coefficient quantifies the error in
the resistor ladder’s resistance ratio (DAC register
code value) and Output Buffer due to temperature drift.
2019 Microchip Technology Inc.
DS20006160A-page 101
MCP48CXBXX
NOTES:
DS20006160A-page 102
2019 Microchip Technology Inc.
MCP48CXBXX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
(1)
PART NO.
Device
X
X
/XX
a) MCP48CVB01-E/MF:
1 LSb INL Voltage Output
Digital-to-Analog Converter,
8-bit Resolution, Extended
Temperature, 10LD DFN, with
volatile memory.
Tape and
Reel
Temperature
Range
Package
Device:
MCP48CXBXX: 1 LSb INL Voltage Output Digital-to-Analog
Converters, with SPI Interface,
b) MCP48CVB01T-E/MF:
1 LSb INL Voltage Output
Digital-to-Analog Converter,
8-bit Resolution, Tape and
Reel, Extended Temperature,
10LD DFN, with volatile
memory
8/10/12-bit Resolution, Single/Dual Outputs
and Volatile/MTP Memory
Tape and Reel:
T
E
=
=
Tape and Reel
a) MCP48CVB12-E/MG:
1 LSb INL Voltage Output
Digital-to-Analog Converter,
10-bit Resolution, Extended
Temperature, 16LD QFN, with
volatile memory.
Temperature
Range:
-40°C to +125°C (Extended)
Package:
MF
MG
UN
=
=
=
Plastic Dual Flat, No Lead Package (DFN),
3 x 3 x 0.9 mm, 10-Lead
Plastic Quad Flat, No Lead Package (QFN),
3 x 3 x 0.9 mm, 16-Lead
Plastic Micro Small Outline Package (MSOP),
10-Lead
b) MCP48CVB12T-E/MG: 1 LSb INL Voltage Output
Digital-to-Analog Converter,
10-bit Resolution, Tape and
Reel, Extended Temperature,
16LD QFN, with volatile
memory.
a) MCP48CMB21-E/UN:
1 LSb INL Voltage Output
Digital-to-Analog Converter,
12-bit Resolution, Extended
Temperature, 10LD MSOP,
with nonvolatile memory.
b) MCP48CMB21T-E/UN: 1 LSb INL Voltage Output
Digital-to-Analog Converter,
12-bit Resolution, Tape and
Reel, Extended Temperature,
10LD MSOP, with nonvolatile
memory.
Note 1:
Tape and Reel identifier only appears in the
catalog part number description. This
identifier is used for ordering purposes and
is not printed on the device package. Check
with your Microchip Sales Office for package
availability with the Tape and Reel option.
2019 Microchip Technology Inc.
DS20006160A-page 103
MCP48CXBXX
NOTES:
DS20006160A-page 104
2019 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, chipKIT, chipKIT logo,
CryptoMemory, CryptoRF, dsPIC, FlashFlex, flexPWR, Heldo,
JukeBlox, KeeLoq, Kleer, LANCheck, LINK MD, maXStylus,
maXTouch, MediaLB, megaAVR, MOST, MOST logo, MPLAB,
OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, Prochip
Designer, QTouch, SAM-BA, SpyNIC, SST, SST Logo,
SuperFlash, tinyAVR, UNI/O, and XMEGA are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity,
JitterBlocker, KleerNet, KleerNet logo, memBrain, Mindi, MiWi,
motorBench, MPASM, MPF, MPLAB Certified logo, MPLIB,
MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation,
PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon,
QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial Quad I/O,
SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
© 2019, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-4219-6
== ISO/TS 16949 ==
2019 Microchip Technology Inc.
DS20006160A-page 105
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DS20006160A-page 106
2019 Microchip Technology Inc.
08/15/18
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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