MCP48FEB04_技术文档

MCP48FXBX4/8

8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL

Digital-to-Analog Converters with SPI Interface

Features

Package Types

• Operating Voltage Range:

- 2.7V to 5.5V – Full specifications

- 1.8V to 2.7V – Reduced device specifications

• Output Voltage Resolutions:

SDO

V

CS 1

15

14

13

12

MCP48FXBX4

20-Lead VQFN

5x5 mm Quad

-

8-bit: MCP48FXB0X (256 steps)

V_REF0

2

3

4

5

REF1

- 10-bit: MCP48FXB1X (1024 steps)

- 12-bit: MCP48FXB2X (4096 steps)

• Rail-to-Rail Output

V_OUT0

V_OUT2

NC

(1)

V

OUT1

OUT3

21 EP

11 NC

• Fast Settling Time of 7.8 µs (Typical)

• DAC Voltage Reference Source Options:

- Device V_DD

LAT1 1

V_{DD 2}

20 LAT0/HVC

19 SDI

- External V_REFpin (buffered or unbuffered)

- Internal band gap (1.22V typical)

• Output Gain Options:

CS 3

18 SCK

17 SDO

16 V_REF1

15 V_OUT1

14 V_OUT3

13 NC

MCP48FXBX4

20-Lead TSSOP

Quad

V_REF0

4

V_{OUT0 5}

V_{OUT2 6}

- 1x (unity)

- 2x (available when not using internal V_DDas

voltage source)

NC

7

8

• Nonvolatile Memory (EEPROM) Option:

V_{SS 9}

12 NC

- User-programmable Power-on Reset

(POR)/Brown-out Reset (BOR) output setting

and device Configuration bits recall

NC 10

11 NC

- Auto-recall of saved DAC register setting

- Auto-recall of saved device configuration

(voltage reference, gain, power-down)

CS 1

15 SDO

• Power-on/Brown-out Reset Protection

• Power-Down Modes:

MCP48FXBX8

20-Lead VQFN

5x5 mm Octal

V_REF0

2

3

4

5

14 V_REF1

13 V_OUT1

12 V_OUT3

11 V_OUT5

V_OUT0

V_OUT2

(1)

21 EP

- Disconnects output buffer (high-impedance)

- Selection of V_OUTpull-down resistors

(125 k or 1 k)

V_OUT4

• Low-Power Consumption:

- Normal operation: <2.6 mA (quad), 3.2 mA (octal)

- Power-down operation: 680 nA typical

LAT1 1

20 LAT0/HVC

19 SDI

- EEPROM write cycle: 2.2 mA (quad),

2.7 mA (octal) maximum

V_DD

2

CS 3

18 SCK

MCP48FXBX8

20-Lead TSSOP

Octal

V_REF0

• SPI Interface:

4

17 SDO

V_OUT0

5

V_{OUT2 6}

16 V_REF1

15 V_OUT1

14 V_OUT3

- Supports Mode 0,0 and Mode 1,1

- Up to 20 MHz writes and 10 MHz reads

V_OUT4

7

- Input buffers support interfacing to

low-voltage digital devices

V_{OUT6 8}

V_{SS 9}

13

V

OUT5

12 V_OUT7

11 NC

• Package Types: 20-Lead TSSOP,

20-Lead 5 mm x 5 mm VQFN

NC 10

Note 1: Includes Exposed Thermal Pad (EP); see

• Extended Temperature Range: -40°C to +125°C

Table 3-1 and Table 3-2.

 2020 Microchip Technology Inc.

DS20006362A-page 1

MCP48FXBX4/8

In the Internal Band Gap Voltage Reference mode, the

gain can be selected between 2 and 4.

General Description

The MCP48FXBX4/8 devices are a family of buffered

voltage output Digital-to-Analog Converters (DAC),

with the following options:

This family of devices features WiperLock™

functionality, which prevents inadvertent changes of

the output value. It uses a high voltage on a specific

pin, together with dedicated commands, to lock the

values that are stored in memory.

• Quad or octal output channel configurations

• 8/10/12-bit resolution

• Volatile or nonvolatile user memory

These devices have an SPI compatible serial interface.

WRITEcommands are supported up to 20 MHz, while

READcommands are supported up to 10 MHz.

The quad and octal options differ only by the number of

output channels. The volatile and nonvolatile versions

have an identical analog circuit structure.

Applications

There are three voltage reference sources: the external

V_REFpin, the device’s V_DDor an internal band gap

voltage source.

• Set Point or Offset Trimming

• Sensor Calibration

When the V_DDmode is selected, it is internally con-

nected to the DAC’s reference circuit. When the external

V_REFpin is used, the user has the option to select

between a gain of 1 and 2 if the Buffered mode is used,

or the internal buffer can be bypassed entirely in the

External V_REFUnbuffered mode.

• Low-Power Portable Instrumentation

• PC Peripherals

• Data Acquisition Systems

• Motor Control

MCP48FXBX4/8 DAC Output Channel Block Diagram

V

DD

VRnB:VRnA/PDnB:PDnA

PDnB:PDnA

V

+

–

REF

PDnB:PDnA

VRnB:VRnA

Band Gap

V_DD

V

GAIN

OUT

PDnB:PDnA

VRnB:VRnA

LAT

1 kΩ

125 kΩ

DS20006362A-page 2

 2020 Microchip Technology Inc.

MCP48FXBX4/8

MCP48FXBX4 Block Diagram (Quad-Channel Output)

V_DD

Power-up/Brown-out Control

V_SS

SCK

SDI

SDO

CS

MEMORY

SPI Serial Interface Module

and Control Logic

VOLATILE

(WiperLock™ Technology)

NONVOLATILE

DAC CHANNELS

0, 2

V_REF0

V_REF

V_OUT0

V_OUT2

LAT

LAT0/HVC

V_REF1

DAC CHANNELS

1, 3

V_OUT1

V_OUT3

V_REF

LAT

LAT1

MCP48FXBX8 Block Diagram (Octal-Channel Output)

V_DD

Power-up/Brown-out Control

V_SS

SCK

SDI

SDO

CS

MEMORY

SPI Serial Interface Module

and Control Logic

VOLATILE

(WiperLock™ Technology)

NONVOLATILE

DAC CHANNELS

0, 2, 4, 6

V_OUT0

V_OUT2

V_OUT4

V_OUT6

V_REF0

V_REF

LAT

LAT0/HVC

DAC CHANNELS

1, 3, 5, 7

V_OUT1

V_OUT3

V_OUT5

V_OUT7

V_REF1

V_REF

LAT

LAT1

 2020 Microchip Technology Inc.

DS20006362A-page 3

MCP48FXBX4/8

Device Features

DAC

Output

Internal

Band

Gap

Device

Package Type

Memory

POR/BOR

Setting⁽¹⁾

MCP48FVB04

MCP48FVB14

MCP48FVB24

MCP48FVB08

MCP48FVB18

MCP48FVB28

MCP48FEB04

MCP48FEB14

MCP48FEB24

MCP48FEB08

MCP48FEB18

MCP48FEB28

VQFN-20 5 x 5, TSSOP-20

4

8

4

8

7Fh

1FFh

7FFh

7Fh

2

Yes

RAM

10

12

8

RAM

10

12

8

1FFh

7FFh

7Fh

RAM

EEPROM

10

12

8

1FFh

7FFh

7Fh

10

12

1FFh

7FFh

Note 1: The factory default value. The DAC output POR/BOR value can be modified via the nonvolatile DAC

Output register (available only on nonvolatile devices – MCP48FEBXX).

DS20006362A-page 4

 2020 Microchip Technology Inc.

MCP48FXBX4/8

1.0

ELECTRICAL CHARACTERISTICS

(†)

Absolute Maximum Ratings

Voltage on V_DDwith Respect to V_SS........................................................................................................ -0.6V to +6.5V

Voltage on All Pins with Respect to V_SS............................................................................................ -0.6V to V_DD+0.3V

Input Clamp Current, I_IK(V_I< 0, V_I> V_DD, V_I> V_PPon HV Pins) ........................................................................±20 mA

Output Clamp Current, I_OK(V_O< 0 or V_O> V_DD) .................................................................................................±20 mA

Maximum Current out of the V_SSPin (Quad) .........................................................................................................150 mA

(Octal)..........................................................................................................150 mA

Maximum Current into the V_DDPin (Quad) .........................................................................................................150 mA

(Octal)..........................................................................................................150 mA

Maximum Current Sourced by the V_OUTPin...........................................................................................................20 mA

Maximum Current Sunk by the V_OUTPin................................................................................................................20 mA

Maximum Current Sunk by the V_REFPin ...............................................................................................................125 µA

Maximum Input Current Source/Sunk by the SDI, SCK and CS Pins ......................................................................2 mA

Maximum Output Current Sunk by the SDO Output Pin ........................................................................................25 mA

Total Power Dissipation⁽¹⁾....................................................................................................................................400 mW

Package Power Dissipation (T_A= +50°C, T_J= +150°C)

20-Lead TSSOP......................................................................................................................................1300 mW

20-Lead VQFN (5 x 5 mm, ML)...............................................................................................................2800 mW

ESD Protection on all Pins±6 kV (HBM)

±400V (MM)

±2 kV (CDM)

Latch-up (per JEDEC^®JESD78A) at +125°C ....................................................................................................±100 mA

Storage Temperature ..............................................................................................................................-65°C to +150°C

Ambient Temperature with Power Applied .............................................................................................-55°C to +125°C

Soldering Temperature of Leads (10 seconds) ..................................................................................................... +300°C

Maximum Junction Temperature (T_J).................................................................................................................... +150°C

† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only and functional operation of the device at those or any other conditions above those indicated

in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

Note 1: Power dissipation is calculated as follows:

P_DIS= V_DD× {I_DD–  I_OH} +  {(V_DD– V_OH) × I_OH} + (V_OL× I_OL

)

 2020 Microchip Technology Inc.

DS20006362A-page 5

MCP48FXBX4/8

DC CHARACTERISTICS

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Supply Voltage

Sym.

Min.

Typ.

Max.

Units

Conditions

V_DD

2.7

1.8

—

5.5

2.7

V

Serial interface operational,

DAC operation with reduced analog

specifications

V_DDVoltage

V_POR/BOR

—

1.7

V

RAM retention voltage: (V_RAM) < V_POR,

(Rising) to Ensure Device

Power-on Reset

V_DDvoltages greater than the V_POR/BOR

limit ensure that the device is out of

Reset

V_DDRise Rate to Ensure

Power-on Reset

V_DDRR

V_HV

V_IHHEN

V_IHHEX

Note 3

—

V/ms

High-Voltage Commands

Voltage Range (HVC Pin)

V_SS

9.0

—

12.5

—

V

The HVC pin will be at one of the three

(1)

input levels (V_IL, V_IHor V_IHH

)

High-Voltage

Input Entry Voltage

—

Threshold for entry into WiperLock™

technology

High-Voltage

—

V_DD+ 0.8V

Note 1

Input Exit Voltage

Note 1: This parameter is ensured by design.

3: POR/BOR voltage trip point is not slope dependent. Hysteresis implemented with time delay.

DS20006362A-page 6

 2020 Microchip Technology Inc.

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters Sym.

Min.

Typ.

Max.

Units

Conditions

Supply Current I_DD

—

1.0

1.7

2.6

1.6

2.3

3.2

mA

Quad 1 MHz⁽¹⁾Serial interface active (not

10 MHz⁽¹⁾

High-Voltage Command),

VRnB:VRnA = All Modes⁽⁴⁾

,

20 MHz

V_OUTis unloaded, V_DD= 5.5V,

Volatile DAC Register = Midscale

Octal

1 MHz⁽¹⁾

10 MHz⁽¹⁾

20 MHz

—

0.85

1.6

mA

Quad Serial interface inactive⁽¹⁾(not

High-Voltage Command),

Octal

VRnB:VRnA = All Modes, SCK = SDI = V_SS,

V_OUTis unloaded,

Volatile DAC Register = Midscale

—

2.2

2.7

mA

Quad EE write current, V_REF= V_DD= 5.5V

(after write, serial interface is inactive),

Octal

write 0x7FF to nonvolatile DAC0 (address

10h), V_OUTpins are unloaded

—

560

700

µA

Quad HVC = 12.5V (High-Voltage Command),

serial interface inactive, V_REF= V_DD= 5.5V,

1100

1300

Octal

LAT/HVC = V_IHH, DAC Registers = Midscale,

V_OUTpins are unloaded

Power-Down

Current

I_DDP

—

0.68

3.8

µA

PDnB:PDnA = 01⁽⁵⁾, V_OUTnot connected

Note 1: This parameter is ensured by characterization.

4: Supply current is independent of current through the resistor ladder in mode VRnB:VRnA = 10.

5: The PDnB:PDnA = 00, 10and 11configurations should have the same current.

 2020 Microchip Technology Inc.

DS20006362A-page 7

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Resistor Ladder

Resistance

R_L

100

140

180

k

VRnB:VRnA = 10,

V_REF= V_DD

(6)

Resolution; # of

Resistors and # of Taps

(see B.1 “Resolution”)

N

256

1024

4096

0.5

Taps

%

8-bit No missing codes

10-bit No missing codes

12-bit No missing codes

2.7V  V_DD 5.5V⁽²⁾

1.8V⁽²⁾

Nominal V_OUTMatch⁽¹¹⁾

|V_OUT– V_OUTMEAN

/V_OUTMEAN

|

—

1.0

1.2

—

%

V_OUTTemperature

Coefficient (see B.19

“V_OUTTemperature

Coefficient”)

V_OUT/T

15

ppm/°C Code = Midscale

(7Fh, 1FFh or 7FFh)

V

_REFPin Input Voltage

Range

Note 1: This parameter is ensured by design.

2: This parameter is ensured by characterization.

V_REF

V_SS

—

V_DD

V

1.8V  V_DD 5.5V⁽¹⁾

6: Resistance is defined as the resistance between the V_REFpin (mode VRnB:VRnA = 10) to V_SSpin. For

octal-channel devices (MCP48FXBX8), this is the effective resistance of each resistor ladder. The

resistance measurement is one of the two resistor ladders measured in parallel.

11: Variation of one output voltage to mean output voltage.

DS20006362A-page 8

 2020 Microchip Technology Inc.

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Zero-Scale Error;

Code = 000h

E_ZS

—

0.75

LSb

8-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD,no load

(see B.5 “Zero-Scale

Error (EZS)”)

—

3

LSb 10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

12

LSb 12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx= 1,

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

Full-Scale Error (see

B.4 “Full-Scale Error

(EFS)”)

E_FS

—

4.5

18

70

8-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD,no load

LSb 10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

LSb 12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_REF= V_DD,

V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

Offset Error

E_OS

-15

±1.5

+15

mV VRnB:VRnA = 00, Gx = 0, no load

(see B.7 “Offset

Error (EOS)”)

Offset Voltage

Temperature

Coefficient

V_OSTC

—

±10

—

µV/°C

Note 1: This parameter is ensured by characterization.

 2020 Microchip Technology Inc.

DS20006362A-page 9

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Gain Error

Sym.

Min.

Typ.

Max.

Units

Conditions

E_G

-1.0

±0.1

+1.0

% of

FSR

Code = 250, no load,

VRnB:VRnA = 00, Gx = 0

8-bit

10-bit

12-bit

(see B.9 “Gain Error

(EG)”)⁽⁸⁾

-1.0

—

±0.1

-3

+1.0

—

% of

FSR

Code = 1000, no load,

VRnB:VRnA = 00, Gx = 0

% of

FSR

Code = 4000, no load,

VRnB:VRnA = 00, Gx = 0

Gain Error Drift (see

B.10 “Gain Error Drift

(EGD)”)

G/°C

ppm/°C

Total Unadjusted Error

(see B.6 “Total

Unadjusted Error

(ET)”)⁽²⁾

E_T

-2.5

-10.0

-40.0

—

+0.5

+2.0

+8.0

LSb

8-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

10-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

V_REF= V_DD/2, V_{REF =}V_DD,

V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

Note 1: This parameter is ensured by characterization.

DS20006362A-page 10

 2020 Microchip Technology Inc.

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Integral Nonlinearity

(see B.11 “Integral

Nonlinearity

INL

-0.5

±0.1

+0.5

LSb

8-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

-1.5

-6

±0.4

±1.5

+1.5

+6

LSb

10-bit VRnB:VRnA = 10, Gx = 0,

(INL)”)^(7,10)

V_REF= V_DD, no load

12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

Performance Curves”⁽¹⁾

V_REF= V_DD/2, V_REF= V_DD

,

V_DD= 2.7-5.5V, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx = 1,

Performance Curves”⁽¹⁾

V_REF= V_DD/2, V_REF= V_DD

,

V_DD= 2.7-5.5V, no load

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

Note 1: This parameter is ensured by characterization.

7: INL and DNL are measured at V_OUTwith V_RL= V_DD(VRnB:VRnA = 00)_.

10: Code range is dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit,

100 to 4000.

 2020 Microchip Technology Inc.

DS20006362A-page 11

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max. Units

LSb 8-bit

Conditions

DifferentialNonlinearity DNL

(see B.12

-0.25

±0.0125 +0.25

VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

“Differential

-0.5

-1.0

±0.05

±0.2

+0.5

+1.0

LSb 10-bit VRnB:VRnA = 10, Gx = 0,

Nonlinearity

V_REF= V_DD, no load

(DNL)”)^(7,10)

LSb 12-bit VRnB:VRnA = 10, Gx = 0,

V_REF= V_DD, no load

See Section 2.0 “Typical

LSb

VRnB:VRnA = 11, Gx = 0, Gx = 1,

V_REF= 0.5 × V_DD= 2.7, no load

Performance Curves”⁽¹⁾

See Section 2.0 “Typical

VRnB:VRnA = 10, Gx = 0, Gx = 1,

Performance Curves”⁽¹⁾

V_REF= V_DD/2, V_REF= V_DD

V_DD= 2.7-5.5V, no load

,

See Section 2.0 “Typical

LSb

VRnB:VRnA = 10, Gx = 0, Gx = 1,

Performance Curves”⁽¹⁾

V_REF= V_DD/2, V_REF= V_DD

V_DD= 2.7-5.5V, no load

,

See Section 2.0 “Typical

VRnB:VRnA = 00, Gx = 0,

V_REF= V_DD= 2.7-5.5V, no load

Performance Curves”⁽¹⁾

Note 1: This parameter is ensured by characterization.

7: INL and DNL are measured at V_OUTwith V_RL= V_DD(VRnB:VRnA = 00)_.

10: Code range is dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit,

100 to 4000.

DS20006362A-page 12

 2020 Microchip Technology Inc.

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

-3 dB Bandwidth

(see B.16 “-3 dB

Bandwidth”)

BW

—

86.5

—

kHz

V

_REF= 2.048V ±0.1V,

VRnB:VRnA = 10, Gx = 0

—

67.7

—

kHz

V_REF= 2.048V ±0.1V,

VRnB:VRnA = 10, Gx = 1

Output Amplifier

Minimum Output

Voltage

V_OUT(MIN)

V_OUT(MAX)

—

0.01

—

V

1.8V  V_DD 5.5V,

output amplifier’s minimum drive

Maximum Output

Voltage

V_DD– 0.016

1.8V  V_DD 5.5V,

output amplifier’s maximum drive

Phase Margin

Slew Rate⁽⁹⁾

PM

SR

I_SC

—

3

58

0.44

9

—

22

°C

V/µs

mA

C_L= 400 pF, R_L= 

R_L= 5 k

Short-Circuit Current

Short to V_SSDAC Code = Full Scale

Short to V_DDDAC Code = 000h

3

9

Internal Band Gap

Band Gap Voltage

V_BG

1.18

—

1.22

15

1.26

—

V

Band Gap Voltage

Temperature

Coefficient

V_BGTC

ppm/°C

Operating Range

V_DD

2.0

2.2

—

5.5

V

V_REFpin voltage stable

V_OUToutput linear

External Reference (V_REF

)

Input Range⁽¹⁾

V_REF

V_SS

—

V_DD– 0.04

V_DD

V

VRnB:VRnA = 11(Buffered mode)

VRnB:VRnA = 10(Unbuffered

mode)

Input Capacitance

C_REF

THD

—

1

—

pF

dB

VRnB:VRnA = 10(Unbuffered

mode)

Total Harmonic

Distortion⁽¹⁾

-64

V_REF= 2.048V ±0.1V,

VRnB:VRnA = 10, Gx = 0,

Frequency = 1 kHz

Dynamic Performance

Major Code

—

45

—

nV-s

1 LSb change around major carry

(7FFh to 800h)

Transition Glitch (see

B.14 “Major Code

Transition Glitch”)

Digital Feedthrough

(see B.15 “Digital

Feedthrough”)

<10

Note 1: This parameter is ensured by design.

9: Within 1/2 LSb of final value when code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a 12-bit

device.)

 2020 Microchip Technology Inc.

DS20006362A-page 13

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

Digital Inputs/Outputs (CS, SCK, SDI, SDO, LAT0/HVC, LAT1)

Schmitt Trigger

High Input Threshold

V_IH

0.45 V_DD

0.5 V_DD

—

V

2.7V  V_DD 5.5V

1.8V  V_DD 2.7V

Schmitt Trigger

Low Input Threshold

V_IL

V_HYS

V_OL

0.2 V_DD

Hysteresis of Schmitt

Trigger Inputs

—

0.1 V_DD

—

V

Output Low Voltage

V_SS

—

10

0.3 V_DD

V_DD

V

I_OL= 5 mA, V_DD= 5.5V

I_OL= 1 mA, V_DD= 1.8V

I_OH= -2.5 mA, V_DD= 5.5V

I_OH= -1 mA, V_DD= 1.8V

Output High Voltage

V_OH

0.7 V_DD

-1

V_DD

Input Leakage Current

Pin Capacitance

I_IL

1

µA V_IN= V_DDand V_IN= V_SS

pF f_C= 20 MHz

C_IN, C_OUT

—

DS20006362A-page 14

 2020 Microchip Technology Inc.

MCP48FXBX4/8

DC CHARACTERISTICS (CONTINUED)

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_REF= +2.048V to V_DD, V_SS= 0V, Gx = 0, R_L= 5 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

RAM Value

Sym.

Min.

Typ.

Max.

Units

Conditions

Value Range

N

0h

—

FFh

3FFh

FFFh

Hex

8-bit

—

10-bit

12-bit

8-bit

—

DAC Register POR/BOR

Value

N

See Table 4-2

10-bit

12-bit

PDCON Initial

Factory Setting

EEPROM

Endurance

EN_EE

DR_EE

N

—

0h

1M

—

Cycles Notes 1, 2

Years At +25°C^(1,2)

Data Retention

EEPROM Range

200

—

FFh

3FFh

FFFh

Hex

8-bit

DACn register(s)

—

10-bit DACn register(s)

12-bit DACn register(s)

—

See Table 4-2

11

Initial Factory Setting

N

EEPROM Programming

Write Cycle Time

t_WC

—

16

ms

V_DD= +1.8V to 5.5V

Power Requirements

Power Supply Sensitivity

(B.17 “Power Supply

Sensitivity (PSS)”)

PSS

—

0.002

0.005

%/% 8-bit

Code = 7Fh

%/% 10-bit Code = 1FFh

%/% 12-bit Code = 7FFh

Note 1: This parameter is ensured by design.

2: This parameter is ensured by characterization.

 2020 Microchip Technology Inc.

DS20006362A-page 15

MCP48FXBX4/8

DC Notes:

1. This parameter is ensured by design.

2. This parameter is ensured by characterization.

3. POR/BOR voltage trip point is not slope-dependent. Hysteresis is implemented with time delay.

4. Supply current is independent of current through the resistor ladder in mode VRnB:VRnA = 10.

5. The PDnB:PDnA bits = 01, 10and 11configurations should have the same current.

6. Resistance is defined as the resistance between the V_REFpin (mode VRnB:VRnA = 10) to V_SSpin. For

octal-channel devices (MCP48FXBX8), this is the effective resistance of each resistor ladder. The resistance

measurement is one of the two resistor ladders measured in parallel.

7. INL and DNL are measured at V_OUTwith V_RL= V_DD(VRnB:VRnA = 00).

8. This gain error does not include an offset error.

9. Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in a

12-bit device.)

10. Code range is dependent on resolution: 8-bit, codes 6 to 250; 10-bit, codes 25 to 1000; 12-bit, codes 100 to 4000.

11. Variation of one output voltage to mean output voltage.

DS20006362A-page 16

 2020 Microchip Technology Inc.

MCP48FXBX4/8

1.1

Timing Waveforms and Requirements

1.1.1

WIPER SETTLING TIME

±0.5 LSb

New Value

Old Value

V_OUT

FIGURE 1-1:

V_OUTSettling Time Waveforms.

TABLE 1-1:

WIPER SETTLING TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

Timing Characteristics

Parameters

All parameters apply across the specified operating ranges unless noted.

V_DD= +1.8V to 5.5V, V_SS= 0V, R_L= 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Sym. Min. Typ. Max. Units

t_S7.8 µs

Conditions

V_OUTSettling Time; ±0.5 LSb

—

12-bit Code = 400h  C00h; C00h  400h⁽¹⁾

Error Band, C_L= 100 pF

(see B.13 “Settling Time”)

Note 1: Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR.

1.1.2 LATCH PIN (LAT) TIMING

LATx

t

LAT

SCK

Wx

FIGURE 1-2:

LAT Pin Waveforms.

TABLE 1-2:

LAT PIN TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended).

Timing Characteristics

All parameters apply across the specified operating ranges unless noted.

V_DD= +2.7V to 5.5V, V_SS= 0V, RL = 2 k from V_OUTto GND, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym.

Min.

Typ.

Max.

Units

Conditions

LATx Pin Pulse Width

t_LAT

20

—

ns

 2020 Microchip Technology Inc.

DS20006362A-page 17

MCP48FXBX4/8

1.1.3

RESET AND POWER-DOWN TIMING

V_POR

V_BOR

t_BORD

V_DD

t_PORD

V_OUTat High-Z

V_OUT

SPI Interface is Operational

Power-on and Brown-out Reset Waveforms.

FIGURE 1-3:

24th Bit

(WRITE

command) command)

1st Bit

(next

24th Bit

(WRITE

command)

SCK

t_PDD

t_PDE

V_OUT

FIGURE 1-4:

SPI Power-Down Command Waveforms.

TABLE 1-3:

RESET AND POWER-DOWN TIMING

Standard Operating Conditions (unless otherwise specified):

Operating Temperature: -40°C  T_A +125°C (Extended.

Timing Characteristics

Unless otherwise noted, all parameters apply across these specified operating ranges:

V_DD= +2.7V to 5.5V, V_SS= 0V, R_L= 5 k from V_OUTto V_SS, C_L= 100 pF.

Typical specifications represent values for V_DD= 5.5V, T_A= +25°C.

Parameters

Sym. Min. Typ. Max. Units

Conditions

µs V_DDrising, V_DD> V_POR

µs V_DDtransitions from V_DD(MIN) > V_POR

Power-on Reset Delay t_PORD

Brown-out Reset Delay t_BORD

—

60

45

—

,

V_OUTdriven to V_OUTdisabled

Power-Down DAC

Output Disable Time

Delay

T_PDE

—

10.5

1

—

µs PDnB:PDnA = 00 11, 10or 01started from the falling

edge of the SCK at the end of the 24th clock cycle,

V_OUT= V_OUT– 10 mV, V_OUTnot connected

Power-Down DAC

Output Enable Time

Delay

T_PDD

µs PDnB:PDnA = 11, 10or 01 00started from the falling

edge of the SCK at the end of the 24th clock cycle,

Volatile DAC Register = FFh, V_OUT= 10 mV,

V_OUTnot connected

DS20006362A-page 18

 2020 Microchip Technology Inc.

MCP48FXBX4/8

1.2

SPI Mode Timing Waveforms and Requirements

V

IHH

HVC

V

IH

97

98

V

IH

CS

V

IL

96

84

‘1’

‘0’

‘1’

‘0’

LAT

94

70

72

96

SCK

SDO

83

71

80

MSb

Bit 6 - - - - - -1

Bit 6 - - - -1

LSb

73

74

77

SDI

MSb In

LSb In

FIGURE 1-5:

SPI Timing Waveforms – Mode 1,1.

V

IHH

97

V

98

IH

HVC

CS

V

IH

V

IH

82

71

V

IH

V

IL

84

‘1’

‘0’

‘1’

‘0’

96

LAT

94

83

96

70

72

SCK

73

80

77

SDO

SDI

MSb

Bit 6 - -1

LSb

74

MSb In

Bit 6 - - - -1

LSb In

FIGURE 1-6:

SPI Timing (Mode 0,0) Waveforms.

 2020 Microchip Technology Inc.

DS20006362A-page 19

MCP48FXBX4/8

TABLE 1-4:

#

SPI REQUIREMENTS (MODE 1,1)

Characteristic

Symbol Min. Max. Units

Conditions

SCK Input Frequency

F_SCK

—

10 MHz V_DD= 2.7V to 5.5V

(READcommand)

—

20 MHz

V_DD= 2.7V to 5.5V

(all other commands)

70

71

CS Active (V_IL) to Command’s 1st SCK  Input T_CSA2SCH

60

20

—

50

ns

SCK Input High Time

T_SCH

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

400

20

72

SCK Input Low Time

T_SCL

400

10

73

74

77

Setup Time of SDI Input to SCK  Edge

Hold Time of SDI Input from SCK  Edge

T_DIV2SCH

T_SCH2DIL

T_CSH2DOZ

20

ns

CS Inactive (V_IH) to SDO Output

High-Impedance

—

ns Note 1

80

83

SDO Data Output Valid after SCK  Edge

CS Inactive (V_IH) after SCK  Edge

CS High Time (V_IH)

T_SCL2DOV

—

45

170

—

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns V_DD= 2.7V to 5.5V

µs V_DD= 1.8V to 2.7V

ns

T_SCH2CSL100

1

84

94

T_CSH

50

20

—

LAT  to SCK ↑ (write data 24th bit) Setup

T_LATSU

ns Write data transferred⁽³⁾

Time

96

97

LAT High or Low Time

T_LAT

20

0

—

ns

HVC  to SCK  (1st data bit)

T_HVCSU

ns High-Voltage Commands⁽¹⁾

(HVC setup time)

98

SCK ↑ (last bit of command, 8th or 24th bit) to T_HVCHD

HVC  (HVC hold time)

25

—

ns High-Voltage Commands⁽¹⁾

Note 1: This parameter is ensured by design.

3: Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in

12-bit device.) The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK

signal (Spec 94) or the current register data value may not be transferred to the output latch (V_OUT) before

the register is overwritten with the new value.

DS20006362A-page 20

 2020 Microchip Technology Inc.

MCP48FXBX4/8

TABLE 1-5:

#

SPI REQUIREMENTS (MODE 0,0)

Characteristic

Sym.

Min. Max. Units

Conditions

SCK Input Frequency

F_SCK

—

10

MHz V_DD= 2.7V to 5.5V

(READcommand)

—

20

MHz V_DD= 2.7V to 5.5V

(all other commands)

70

71

CS Active (V_IL) to SCK  Input

T_CSA2SCH

T_SCH

60

20

—

50

ns

SCK Input High Time

ns V_DD= 2.7V to 5.5V

400

20

ns

V_DD= 1.8V to 2.7V

72

SCK Input Low Time

T_SCL

ns V_DD= 2.7V to 5.5V

400

10

ns V_DD= 1.8V to 2.7V

73

74

77

Setup Time of SDI Input to SCK  Edge

Hold Time of SDI Input from SCK  Edge

T_DIV2SCH

T_SCH2DIL

T_CSH2DOZ

ns

20

ns

CS Inactive (V_IH) to SDO Output

High-Impedance

—

ns Note 1

80

SDO Data Output Valid after SCK  Edge

T_SCL2DOV

—

45

170

70

ns V_DD= 2.7V to 5.5V

ns V_DD= 1.8V to 2.7V

ns

82

83

SDO Data Output Valid after CS Active (V_IL)

T_SSL2DOV

T_SCH2CSL

—

CS Inactive (V_IH) after SCK  Edge

100

1

—

ns V_DD= 2.7V to 5.5V

µs V_DD= 1.8V to 2.7V

ns

84

94

CS High Time (V_IH)

T_CSH

50

10

—

LAT  to SCK ↑ (write data 24th bit) Setup

T_LATSU

ns Write data transferred⁽³⁾

Time

96

97

LAT High or Low Time

T_LAT

50

0

—

ns

HVC  to SCK  (1st data bit)

T_HVCSU

ns High-Voltage Commands⁽¹⁾

(HVC setup time)

98

SCK  (last bit of command, 8th or 24th bit) to

HVC  (HVC hold time)

T_HVCHD

25

—

ns High-Voltage Commands⁽¹⁾

Note 1: This parameter is ensured by design.

3: Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in

12-bit device.) The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK

signal (Spec 94) or the current register data value may not be transferred to the output latch (V_OUT) before

the register is overwritten with the new value.

 2020 Microchip Technology Inc.

DS20006362A-page 21

MCP48FXBX4/8

Timing Table Notes:

1. This parameter is ensured by design.

2. This parameter is ensured by characterization.

3. Within 1/2 LSb of the final value when the code changes from 1/4 to 3/4 of FSR. (Example: 400h to C00h in 12-bit

device).The transition of the LAT signal must occur 10 ns before the rising edge of the 24th SCK signal (Spec 94)

or the current register data value may not be transferred to the output latch (V_OUT) before the register is

overwritten with the new value.

DS20006362A-page 22

 2020 Microchip Technology Inc.

MCP48FXBX4/8

TEMPERATURE SPECIFICATIONS

Electrical Specifications: Unless otherwise indicated, V_DD= +2.7V to +5.5V, V_SS= GND.

Parameters

Temperature Ranges

Sym.

Min.

Typ.

Max. Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+125

+150

°C

Note 1

Thermal Package Resistances

Thermal Resistance, 20-Lead TSSOP

_JA

—

90

—

°C/W

Thermal Resistance, 20-Lead VQFN

(5x5 mm, P8X)

36.1

Note 1: Operation in this range must not cause T_Jto exceed the Maximum Junction Temperature of +150°C.

 2020 Microchip Technology Inc.

DS20006362A-page 23

MCP48FXBX4/8

NOTES:

DS20006362A-page 24

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.0

TYPICAL PERFORMANCE CURVES

Note: The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

2.1

Electrical Data

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-1:

Current vs. F_SCKFrequency, Voltage and

Temperature – Active Interface,

VRnB:VRnA = 00, (V_DDMode).

Average Device Supply

FIGURE 2-4:

Average Device Supply

Current – Inactive Interface (SCK = V_IHor V_IL)

vs. Voltage and Temperature, VRnB:VRnA = 00

(V_DDMode).

FIGURE 2-2:

Current vs. F_SCKFrequency, Voltage and

Temperature – Active Interface,

VRnB:VRnA = 01 (Band Gap Mode).

Average Device Supply

FIGURE 2-5:

Average Device Supply

Current – Inactive Interface (SCK = V_IHor V_IL)

vs. Voltage and Temperature, VRnB:VRnA = 01

(Band Gap Mode).

FIGURE 2-3:

Current vs. F_SCKFrequency, Voltage and

Temperature – Active Interface,

VRnB:VRnA = 11 (V_REFBuffered Mode).

Average Device Supply

FIGURE 2-6:

Average Device Supply

Current – Inactive Interface (SCK = V_IHor V_IL)

vs. Voltage and Temperature, VRnB:VRnA = 11

(V_REFBuffered Mode).

 2020 Microchip Technology Inc.

DS20006362A-page 25

MCP48FXBX4/8

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-7:

Current vs. F_SCKFrequency, Voltage and

Temperature – Active Interface,

VRnB:VRnA = 10 (V_REFUnbuffered Mode).

Average Device Supply

FIGURE 2-9:

Average Device Supply

Current – Inactive Interface (SCK = V_IHor V_IL)

vs. Voltage and Temperature, VRnB:VRnA = 10

(V_REFUnbuffered Mode).

FIGURE 2-8:

Active Current (I_DDA) (at 5.5V and

_SCK= 20 MHz) vs. Temperature and DAC

Average Device Supply

FIGURE 2-10:

Power-Down Currents.

F

Reference Voltage Mode.

DS20006362A-page 26

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2

Linearity Data

2.2.1

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), V_REF= V_DD

(VRnB:VRnA = 00), GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated: T_A= +25°C, V_DD= 5.5V

FIGURE 2-11:

Total Unadjusted Error

FIGURE 2-14:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-12:

Total Unadjusted Error

FIGURE 2-15:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-13:

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

Total Unadjusted Error

FIGURE 2-16:

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

Total Unadjusted Error

 2020 Microchip Technology Inc.

DS20006362A-page 27

MCP48FXBX4/8

2.2.2

INTEGRAL NONLINEARITY (INL) – MCP48FXB28 (12-BIT), V_REF= V_DD(VRnB:VRnA = 00),

GAIN = 1x, CODE 64-4032

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-17:

INL Error vs. DAC Code,

FIGURE 2-20:

INL Error vs. DAC Code,

T = 40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-18:

INL Error vs. DAC Code,

FIGURE 2-21:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-19:

INL Error vs. DAC Code,

FIGURE 2-22:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 28

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.3

Note:

DIFFERENTIAL NONLINEARITY (DNL) – MCP48FXB28 (12-BIT), V_REF= V_DD

(VRnB:VRnA = 00), GAIN = 1x, CODE 64-4032

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-23:

DNL Error vs. DAC Code,

FIGURE 2-26:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-24:

DNL Error vs. DAC Code,

FIGURE 2-27:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-25:

DNL Error vs. DAC Code,

FIGURE 2-28:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 29

MCP48FXBX4/8

2.2.4

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), BAND GAP MODE

(VRnB:VRnA = 01), GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-29:

Total Unadjusted Error

FIGURE 2-32:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-30:

Total Unadjusted Error

FIGURE 2-33:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-31:

Total Unadjusted Error

FIGURE 2-34:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

DS20006362A-page 30

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.5

Note:

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), BAND GAP MODE

(VRnB:VRnA = 01), GAIN = 4x, CODE 100-4000

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-35:

Total Unadjusted Error

FIGURE 2-37:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

FIGURE 2-36:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 5.5V.

 2020 Microchip Technology Inc.

DS20006362A-page 31

MCP48FXBX4/8

2.2.6

INTEGRAL NONLINEARITY (INL) – MCP48FXB28 (12-BIT), BAND GAP MODE

(VRnB:VRnA = 01), GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-38:

INL Error vs. DAC Code,

FIGURE 2-41:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-39:

INL Error vs. DAC Code,

FIGURE 2-42:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-40:

INL Error vs. DAC Code,

FIGURE 2-43:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 32

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.7

Note:

INTEGRAL NONLINEARITY (INL) – MCP48FXB28 (12-BIT), BAND GAP MODE

(VRnB:VRnA = 01), GAIN = 4x, CODE 100-4000

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-46:

T = +125°C, V_DD= 5.5V.

INL Error vs. DAC Code,

FIGURE 2-44:

T = -40°C, V_DD= 5.5V.

INL Error vs. DAC Code,

FIGURE 2-45:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

 2020 Microchip Technology Inc.

DS20006362A-page 33

MCP48FXBX4/8

2.2.8

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), BAND GAP MODE

(VRnB:VRnA = 01), GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-47:

DNL Error vs. DAC Code,

FIGURE 2-50:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-48:

DNL Error vs. DAC Code,

FIGURE 2-51:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-49:

DNL Error vs. DAC Code,

FIGURE 2-52:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 34

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.9

Note:

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), BAND GAP MODE

(VRnB:VRnA = 01), GAIN = 4x, CODE 100-4000

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-55:

T = +125°C, V_DD= 5.5V.

DNL Error vs. DAC Code,

FIGURE 2-53:

T = -40°C, V_DD= 5.5V.

DNL Error vs. DAC Code,

FIGURE 2-54:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

 2020 Microchip Technology Inc.

DS20006362A-page 35

MCP48FXBX4/8

2.2.10

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

UNBUFFERED MODE (VRnB:VRnA = 10), V_REF= V_DD, GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-56:

Total Unadjusted Error

FIGURE 2-59:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-57:

Total Unadjusted Error

FIGURE 2-60:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-58:

Total Unadjusted Error

FIGURE 2-61:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

DS20006362A-page 36

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.11

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

UNBUFFERED MODE (VRnB:VRnA = 10), V_REF= V_DD/2, GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-62:

Total Unadjusted Error

FIGURE 2-65:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-63:

Total Unadjusted Error

FIGURE 2-66:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-64:

Total Unadjusted Error

FIGURE 2-67:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 37

MCP48FXBX4/8

2.2.12

INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, UNBUFFERED (VRnB:VRnA = 10), V_REF= V_DD, GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-68:

INL Error vs. DAC Code,

FIGURE 2-71:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-69:

INL Error vs. DAC Code,

FIGURE 2-72:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-70:

INL Error vs. DAC Code,

FIGURE 2-73:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 38

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.13

INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, UNBUFFERED (VRnB:VRnA = 10), V_REF= V_DD/2, GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-74:

INL Error vs. DAC Code,

FIGURE 2-77:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-75:

INL Error vs. DAC Code,

FIGURE 2-78:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-76:

INL Error vs. DAC Code,

FIGURE 2-79:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 39

MCP48FXBX4/8

2.2.14

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, UNBUFFERED (VRnB:VRnA = 10), V_REF= V_DD, GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-80:

DNL Error vs. DAC Code,

FIGURE 2-83:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-81:

DNL Error vs. DAC Code,

FIGURE 2-84:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-82:

DNL Error vs. DAC Code,

FIGURE 2-85:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 40

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.15

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, UNBUFFERED (VRnB:VRnA = 10), V_REF= V_DD/2, GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-86:

DNL Error vs. DAC Code,

FIGURE 2-89:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-87:

DNL Error vs. DAC Code,

FIGURE 2-90:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-88:

DNL Error vs. DAC Code,

FIGURE 2-91:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 41

MCP48FXBX4/8

2.2.16

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

BUFFERED MODE (VRnB:VRnA = 10), V_REF= V_DD, GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-92:

Total Unadjusted Error

FIGURE 2-95:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-93:

Total Unadjusted Error

FIGURE 2-96:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-94:

Total Unadjusted Error

FIGURE 2-97:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

DS20006362A-page 42

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.17

TOTAL UNADJUSTED ERROR (TUE) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

BUFFERED MODE (VRnB:VRnA = 10), V_REF= V_DD/2, GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-98:

Total Unadjusted Error

FIGURE 2-101:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = -40°C, V_DD= 2.7V.

FIGURE 2-99:

Total Unadjusted Error

FIGURE 2-102:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +25°C,V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +25°C, V_DD= 2.7V.

FIGURE 2-100:

Total Unadjusted Error

FIGURE 2-103:

Total Unadjusted Error

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 5.5V.

(V_OUT) vs. DAC Code, T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 43

MCP48FXBX4/8

2.2.18

INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, BUFFERED (VRnB:VRnA = 11), V_REF= V_DD, GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-104:

INL Error vs. DAC Code,

FIGURE 2-107:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-105:

INL Error vs. DAC Code,

FIGURE 2-108:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-106:

INL Error vs. DAC Code,

FIGURE 2-109:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 44

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.19

INTEGRAL NONLINEARITY ERROR (INL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, BUFFERED (VRnB:VRnA = 11), V_REF= V_DD/2, GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

FIGURE 2-110:

INL Error vs. DAC Code,

FIGURE 2-113:

INL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-111:

INL Error vs. DAC Code,

FIGURE 2-114:

INL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-112:

INL Error vs. DAC Code,

FIGURE 2-115:

INL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 45

MCP48FXBX4/8

2.2.20

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, BUFFERED (VRnB:VRnA = 11), V_REF= V_DD, GAIN = 1x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-116:

DNL Error vs. DAC Code,

FIGURE 2-119:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-117:

DNL Error vs. DAC Code,

FIGURE 2-120:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-118:

DNL Error vs. DAC Code,

FIGURE 2-121:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

DS20006362A-page 46

 2020 Microchip Technology Inc.

MCP48FXBX4/8

2.2.21

DIFFERENTIAL NONLINEARITY ERROR (DNL) – MCP48FXB28 (12-BIT), EXTERNAL V_REF

MODE, BUFFERED (VRnB:VRnA = 11), V_REF= V_DD/2, GAIN = 2x, CODE 100-4000

Note:

Unless otherwise indicated, T_A= +25°C, V_DD= 5.5V.

.

FIGURE 2-122:

DNL Error vs. DAC Code,

FIGURE 2-125:

DNL Error vs. DAC Code,

T = -40°C, V_DD= 5.5V.

T = -40°C, V_DD= 2.7V.

FIGURE 2-123:

DNL Error vs. DAC Code,

FIGURE 2-126:

DNL Error vs. DAC Code,

T = +25°C, V_DD= 5.5V.

T = +25°C, V_DD= 2.7V.

FIGURE 2-124:

DNL Error vs. DAC Code,

FIGURE 2-127:

DNL Error vs. DAC Code,

T = +125°C, V_DD= 5.5V.

T = +125°C, V_DD= 2.7V.

 2020 Microchip Technology Inc.

DS20006362A-page 47

MCP48FXBX4/8

NOTES:

DS20006362A-page 48

 2020 Microchip Technology Inc.

MCP48FXBX4/8

3.0

PIN DESCRIPTIONS

Overviews of the pin functions are provided in

Section 3.1 “Positive Power Supply Input Pin

(V_DD)” through Section 3.10 “No Connect Pin (NC)”.

The descriptions of the pins for the quad DAC output

devices are listed in Table 3-1 and descriptions for the

octal DAC output devices are listed in Table 3-2.

TABLE 3-1:

MCP48FXBX4 (QUAD DAC) PIN FUNCTION TABLE

Description

20-Lead 20-Lead

Buffer

Type

Symbol

LAT1

I/O

TSSOP

VQFN

1

19

I

ST

DAC Register Latch Pin. The Latch 1 pin allows the value in the

volatile DAC1/DAC3 registers (wiper and Configuration bits) to

be transferred to the DAC1/DAC3 outputs (V_OUT1, V_OUT3).

2

3

4

5

6

20

1

V_DD

CS

—

I

P

Supply Voltage Pin

SPI Chip Select Pin

ST

2

V_REF0

V_OUT0

V_OUT2

NC

A

—

Analog Voltage Reference Input 0 Pin

3

Analog Buffered Analog Voltage Output – Channel 0 Pin

Analog Buffered Analog Voltage Output – Channel 2 Pin

4

7, 8, 10, 5, 6, 8, 9,

—

Not internally connected

11, 12, 13

10,11

9

7

V_SS

V_OUT3

V_OUT1

V_REF1

SDO

—

A

I

P

Ground Reference Pin for all circuitries on the device

Buffered Analog Voltage Output – Channel 3 Pin

Buffered Analog Voltage Output – Channel 1 Pin

14

15

16

17

18

19

20

12

13

14

15

16

17

18

—

Analog Voltage Reference Input 1 Pin

—

ST

SPI Serial Data Output Pin

SPI Serial Clock Pin

SCK

I

SDI

I

SPI Serial Data Input Pin

LAT0/HVC

I

DAC Register Latch/High-Voltage Command Pin. The Latch 0

pin allows the value in the volatile DAC0/DAC2 registers (wiper

and Configuration bits) to be transferred to the DAC0/DAC2

outputs (V_OUT0, V_OUT2). The High-Voltage Command (HVC)

allows user Configuration bits to be written.

—

21

EP

—

Exposed Thermal Pad Pin⁽¹⁾

Note 1: A = Analog, ST = Schmitt Trigger, HV = High Voltage, I = Input, O = Output, I/O = Input/Output,

P = Power.

 2020 Microchip Technology Inc.

DS20006362A-page 49

MCP48FXBX4/8

TABLE 3-2:

MCP48FXBX8 (OCTAL DAC) PIN FUNCTION TABLE

Description

20-Lead 20-Lead

TSSOP VQFN

Buffer

Type

Symbol

LAT1

I/O

1

19

I

ST

DAC Register Latch Pin. The Latch 1 pin allows the value in the

volatile DAC1/DAC3/DAC5/DAC7 registers (wiper and Configura-

tion bits) to be transferred to the DAC1/DAC3/DAC5/DAC7 outputs

(V_OUT1, V_OUT3, V_OUT5, V_OUT7).

2

3

20

1

V_DD

CS

—

I

P

Supply Voltage Pin

SPI Chip Select Pin

ST

4

2

V_REF0

V_OUT0

V_OUT2

V_OUT4

V_OUT6

V_SS

A

—

A

I

Analog Voltage Reference Input 0 Pin

5

3

Analog Buffered Analog Voltage Output – Channel 0 Pin

Analog Buffered Analog Voltage Output – Channel 2 Pin

Analog Buffered Analog Voltage Output – Channel 4 Pin

Analog Buffered Analog Voltage Output – Channel 6 Pin

6

4

7

5

8

6

9

7

P

Ground Reference Pin for all circuitries on the device

Not internally connected

10, 11

12

13

14

15

16

17

18

19

20

8, 9

10

11

12

13

14

15

16

17

18

NC

—

V_OUT7

V_OUT5

V_OUT3

V_OUT1

V_REF1

SDO

Analog Buffered Analog Voltage Output – Channel 7 Pin

Analog Buffered Analog Voltage Output – Channel 5 Pin

Analog Buffered Analog Voltage Output – Channel 3 Pin

Analog Buffered Analog Voltage Output – Channel 1 Pin

Analog Voltage Reference Input 1 Pin

—

ST

SPI Serial Data Output Pin

SPI Serial Clock Pin

SCK

I

SDI

I

SPI Serial Data Input Pin

LAT0/HVC

I

DAC Register Latch/High-Voltage Command Pin. The Latch 0 pin

allows the value in the volatile DAC0/DAC2/DAC4/DAC6 registers

(wiper and Configuration bits) to be transferred to the

DAC0/DAC2/DAC4/DAC6 outputs (V_OUT0, V_OUT2, V_OUT4, V_OUT6).

The High-Voltage Command (HVC) allows user Configuration bits

to be written.

—

21

EP

—

Exposed Thermal Pad Pin⁽¹⁾

Note 1: A = Analog, ST = Schmitt Trigger, HV = High Voltage, I = Input, O = Output, I/O = Input/Output, P = Power.

DS20006362A-page 50

 2020 Microchip Technology Inc.

MCP48FXBX4/8

3.1

Positive Power Supply Input Pin

(V

3.4

Analog Output Voltage Pins

)

(V

)

DD

V_DDis the positive supply voltage input pin. The input

supply voltage is relative to V_SS

OUTn

V_OUTis the DAC analog voltage output pin. The DAC

output has an output amplifier. The DAC output range

depends on the selection of the voltage reference

source (and potential output gain selection). These are:

.

The power supply at the V_DDpin should be as clean as

possible for a good DAC performance. It is recom-

mended to use an appropriate bypass capacitor of

about 0.1 µF (ceramic) to ground. An additional 10 µF

capacitor (tantalum) in parallel is also recommended to

further attenuate noise present in application boards.

• Device V_DD– The full-scale range of the DAC

output is from V_SSto approximately V_DD

.

• V_REFPin – The full-scale range of the DAC output

is from V_SSto G × V_RL, where G is the gain

selection option (1x or 2x).

3.2

Ground Pin (V

)

SS

• Internal Band Gap – The full-scale range of the

DAC output is from V_SSto G × (2 × V_BG), where G

is the gain selection option (1x or 2x).

The V_SSpin is the device ground reference.

The user must connect the V_SSpin to a ground plane

through a low-impedance connection. If an analog

ground path is available in the application PCB (Printed

Circuit Board), it is highly recommended that the V_SS

pin be tied to the analog ground path or isolated within

an analog ground plane of the circuit board.

In Normal mode, the DC impedance of the output pin is

about 1. In Power-Down mode, the output pin is

internally connected to a known pull-down resistor of

1 k, 125 k or open. The power-down selection bits

setting are shown in Register 4-3 and Table 5-4.

3.5

Latch Pin (LAT)/High-Voltage

Command Pin (HVC)

3.3

Voltage Reference Pins (V

)

REF

The V_REFpin is either an input or an output. When the

DAC’s voltage reference is configured as the V_REFpin,

the pin is an input. When the DAC’s voltage reference is

configured as the internal band gap, the pin is an output.

The DAC output value update event can be controlled

and synchronized using the LAT pins, for one or both

channels, on a single or different devices.

The LAT pins control the effect of the Volatile Wiper

registers, and the VRnB:VRnA, PDnB:PDnA and Gx

bits on the DAC output.

When the DAC’s voltage reference is configured as the

V_REFpin, there are two options for this voltage input:

• V_REFpin voltage buffered

• V_REFpin voltage unbuffered

If the LAT pins are held at V_IH, the values sent to the

Volatile Wiper registers and Configuration bits have no

effect on the DAC outputs.

The buffered option is offered in cases where the exter-

nal reference voltage does not have sufficient current

capability to not drop its voltage when connected to the

internal resistor ladder circuit.

Once voltage on the pin transitions to V_IL, the values in

the Volatile Wiper registers and Configuration bits are

transferred to the DAC outputs.

When the DAC’s voltage reference is configured as the

device V_DD, the V_REFpin is disconnected from the

internal circuit.

The pin is level-sensitive, so writing to the Volatile

Wiper registers and Configuration bits, while it is being

held at V_IL, will trigger an immediate change in the

outputs.

When the DAC’s voltage reference is configured as the

internal band gap, the V_REFpin’s drive capability is min-

imal, so the output signal should be buffered.

The HVC pin allows the device’s nonvolatile user

Configuration bits to be programmed when the voltage

on the pin is greater than the V_IHHentry voltage.

There are two V_REFpins, each corresponding to a

group of output channels. V_REF0is connected to even

channels: 0-6, while V_REF1is connected to odd

channels: 1-7. See Section 5.2 “Voltage Reference

Selection” and Register 4-2 for more details on the

configuration bits.

3.6

SPI – Chip Select Pin (CS)

The CS pin enables/disables the serial interface. The

serial interface must be enabled for the SPI commands

to be received by the device. See Section 6.2 “SPI

Serial Interface” for more details on the SPI serial

interface communication.

 2020 Microchip Technology Inc.

DS20006362A-page 51

MCP48FXBX4/8

3.7

SPI – Serial Data Input Pin (SDI)

3.10 No Connect Pin (NC)

The SDI pin is the serial data input pin of the SPI

interface. The SDI pin is used to read the DAC registers

and Configuration bits.

The NC pins are not connected to the device.

3.11 Exposed Pad Pin

See Section 6.2 “SPI Serial Interface” for more

details on the SPI serial interface communication.

This pad is conductively connected to the device’s

substrate. It should be tied to the same potential as the

V_SSpin (or left unconnected). This pad could be used

to assist in heat dissipation for the device when con-

nected to a PCB heat sink. The pad is only present on

the VQFN package.

3.8

SPI– SerialDataOutputPin(SDO)

The SDO pin is the serial data output pin of the SPI

interface. The SDO pin is used to write the DAC

registers and Configuration bits.

See Section 6.2 “SPI Serial Interface” for more

details on the SPI serial interface communication.

3.9

SPI – Serial Clock Pin (SCK)

The SCK pin is the serial clock pin of the SPI interface.

The MCP48FXBX4/8 SPI interface only accepts

external serial clocks.

See Section 6.2, SPI Serial Interface for more details

on the SPI serial interface communication.

DS20006362A-page 52

 2020 Microchip Technology Inc.

MCP48FXBX4/8

4.1

Power-on Reset/Brown-out Reset

(POR/BOR)

4.0

GENERAL DESCRIPTION

The MCP48FXBX4 (MCP48FXB04, MCP48FXB14

and MCP48FXB24) devices are quad-channel voltage

output devices. The MCP48FXBX8 (MCP48FXB08,

MCP48FXB18 and MCP48FXB28) devices are

octal-channel voltage output devices.

The internal POR/BOR circuit monitors the power

supply voltage (V_DD) during operation. This circuit

ensures correct device start-up at system power-up

and power-down events. The device’s RAM Retention

Voltage (V_RAM) is lower than the POR/BOR Voltage

(V_POR/V_BOR) trip point. The maximum V_POR/V_BOR

voltage is less than 1.8V.

These devices are offered with 8-bit (MCP48FXB0X),

10-bit (MCP48FXB1X) and 12-bit (MCP48FXB2X) res-

olutions and include nonvolatile memory (EEPROM),

an SPI serial interface and two write Latch pins (LAT0,

LAT1) to control the update of the written DAC value to

the DAC output pin.

POR occurs as the voltage rises (typically from 0V),

while BOR occurs as the voltage falls (typically from

V_DD(MIN)or higher).

The devices use a resistor ladder architecture. The

resistor ladder DAC is driven from a software-

selectable voltage reference source. The source can

be either the device’s internal V_DD, an external V_REF

pin voltage (buffered or unbuffered) or an internal band

gap voltage source.

The POR and BOR trip points are at the same voltage

and the condition is determined by whether the V_DD

voltage is rising or falling (see Figure 4-1). What occurs

is different depending on whether the reset is a POR or

BOR.

When V_POR/V_BOR< V_DD< 2.7V, the electrical perfor-

mance may not meet the data sheet specifications. In

this region, the device is capable of reading and writing

to its EEPROM and reading and writing to its volatile

memory if the proper serial command is executed.

The DAC output is buffered with a low-power and

precision output amplifier (op amp). This output

amplifier provides a rail-to-rail output with low offset

voltage and low noise. The gain (1x or 2x) of the

output buffer is software configurable.

4.1.1

POWER-ON RESET

This device family also has a user-programmable

nonvolatile memory (EEPROM) option, which allows

the user to save the desired POR/BOR value of the

DAC register and device Configuration bits.

The Power-on Reset is the case where the V_DDhas

power applied to it, ramping up from the V_SSvoltage

level. As the device powers up, the V_OUTpin floats to

an unknown value. When V_DDis above the transistor

threshold voltage of the device, the output starts to be

pulled low. After the V_DDis above the POR/BOR trip

point (V_BOR/V_POR), the resistor network’s wiper is

loaded with the POR value (midscale). The volatile

memory determines the analog output (V_OUT) pin volt-

age. After the device is powered up, the user can

update the device’s memory.

High-voltage lock bits can be used to ensure that the

device’s output settings are not accidentally modified.

The device operates from a single-supply voltage. This

voltage is specified from 2.7V to 5.5V for full specified

operation and from 1.8V to 5.5V for digital operation.

The device can operate between 1.8V and 2.7V, but its

analog performance is significantly reduced; therefore,

most device parameters are not specified for this

range.

When the rising V_DDvoltage crosses the V_PORtrip

point, the following occurs:

The main functional blocks are:

• The nonvolatile DAC register value is latched into

the volatile DAC register.

• Power-on Reset/Brown-out Reset (POR/BOR)

• Device Memory

• The nonvolatile Configuration bit values are

latched into the volatile Configuration bits.

• Resistor Ladder

• Output Buffer/V_OUTOperation

• Internal Band Gap

• The POR status bit is set (‘1’).

• The POR Reset Delay Timer (t_PORD) starts; when

the POR Reset Delay Timer (t_PORD) times out, the

serial interface is operational. During this delay

time, the serial interface will not accept commands.

• SPI Serial Interface Module

• The Device Memory Address Pointer is forced to

00h.

The Analog Output (V_OUT) state is determined by the

state of the volatile Configuration bits and the DAC

register. This is called a Power-on Reset (event).

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

 2020 Microchip Technology Inc.

DS20006362A-page 53

MCP48FXBX4/8

If the V_DDvoltage decreases below the V_RAMvoltage,

all volatile memory may become corrupted.

4.1.2

BROWN-OUT RESET

The Brown-out Reset occurs when a device has power

applied to it and that power (voltage) drops below the

specified range.

As the voltage recovers above the V_POR/V_BORvoltage,

see Section 4.1.1 “Power-on Reset”.

Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and

nonvolatile) to become corrupted.

When the falling V_DDvoltage crosses the V_PORtrip

point (BOR event), the following occurs:

• The serial interface is disabled.

• EEPROM writes are disabled.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

• The device is forced into a Power-Down state

(PDnB:PDnA = 11). Analog circuitry is turned off.

• The volatile DAC register is forced to 000h.

• Volatile Configuration bits, VRnB:VRnA and Gx,

are forced to ‘0’.

POR Starts Reset Delay Timer;

After it Times Out, the Serial Interface

Default Device Configuration

Latched into Volatile Configuration

Bits and DAC Register; POR

can Operate (if V_DD

 V_DD(MIN))

BOR,

Status Bit is Set (‘1’)

Volatile DAC Register = 000h,

Volatile Memory Retains

Data Values

Volatile VRnB:VRnA = 00

Volatile Gx =

Volatile PDnB:PDnA = 11

,

POR Forced

Active

0,

T

PORD

V

DD(MIN)

Volatile Memory

becomes Corrupted

V

BOR

POR

RAM

V

Device in

Unknown

State

Device in Unknown

State

Device Normal Operation

in POR

State

Device in

Power-

Down

Below Min.

Operating

Voltage

State

FIGURE 4-1:

POR/BOR Operation.

DS20006362A-page 54

 2020 Microchip Technology Inc.

MCP48FXBX4/8

4.2.3

DEVICE CONFIGURATION

MEMORY

4.2

Device Memory

User memory includes the following types:

There are up to sixteen nonvolatile user bits that are not

directly mapped into the address space. These non-

volatile device Configuration bits control the WiperLock

technology for DAC registers and configuration (two bits

per DAC).

• Volatile Register Memory (RAM)

• Nonvolatile Register Memory

• Device Configuration Memory

Each memory address is 16 bits wide. There are up to

17 nonvolatile user control bits that do not reside in

memory-mapped register space (see Section 4.2.3

“Device Configuration Memory”).

The Status register shows the states of the device

WiperLock technology Configuration bits. The Status

register is described in Register 4-6.

The operation of WiperLock technology is discussed in

Section 4.2.6 “WiperLock Technology”.

4.2.1

VOLATILE REGISTER MEMORY

(RAM)

There are up to twelve volatile memory locations:

4.2.4

READ commands of

unimplemented bits as ‘0’.

UNIMPLEMENTED REGISTER BITS

• DAC0 through DAC7 Output Value registers

• V_REFSelect register

a

valid location will read

• Power-Down Configuration register

• Gain and Status register

4.2.5

UNIMPLEMENTED (RESERVED)

LOCATIONS

• WiperLock Technology Status register

Normal (voltage) commands (READ or WRITE) to any

unimplemented memory address (reserved) will result

in a Command Error (CMDERR) condition. READ

commands of a reserved location will read bits as ‘1’.

The volatile memory starts functioning when the

device V_DDis at (or above) the RAM Retention Voltage

(V_RAM). The volatile memory will be loaded with the

default device values when the V_DDrises across the

V_POR/V_BORvoltage trip point.

High-Voltage Commands (enable or disable) to any

unimplemented Configuration bits will result in a

Command Error (CMDERR) condition.

4.2.2

NONVOLATILE REGISTER

MEMORY

4.2.5.1

Default Factory POR Memory State

of Nonvolatile Memory (EEPROM)

This device family uses the nonvolatile memory for the

DAC output value and Configuration registers:

Table 4-2 shows the default factory POR initialization

of the device memory map for the 8, 10 and 12-bit

devices. In the case of volatile memory devices

(MCP48FVBXX), the factory default values cannot be

modified.

• Nonvolatile DAC0 through DAC7 Output Value

registers

• Nonvolatile V_REFSelect register

• Nonvolatile Power-Down Configuration register

• Nonvolatile Gain register

Note:

The volatile memory locations will be

determined by the nonvolatile memory

states (registers and device Configuration

bits).

The nonvolatile memory starts functioning below the

device’s V_POR/V_BORtrip point, and is loaded into the

corresponding volatile registers whenever the device

rises above the POR/BOR voltage trip point.

The device starts writing the nonvolatile (EEPROM)

memory location at the completion of the serial

interface command, after the Acknowledge pulse of the

WRITE single command. Continuous WRITE

commands addressing the nonvolatile memory are not

permitted.

Note:

When the nonvolatile memory is written,

the corresponding volatile memory is not

modified.

Nonvolatile DAC registers enable the stand-alone

operation of the device (without microcontroller control)

after being programmed to the desired value.

 2020 Microchip Technology Inc.

DS20006362A-page 55

MCP48FXBX4/8

TABLE 4-1:

MCP48FXBX4/8 MEMORY MAP

Function

00h Volatile DAC0 Register

01h Volatile DAC1 Register

02h Volatile DAC2 Register

03h Volatile DAC3 Register

04h Volatile DAC4 Register

05h Volatile DAC5 Register

06h Volatile DAC6 Register

07h Volatile DAC7 Register

CL0

CL1

CL2

CL3

CL4

CL5

CL6

CL7

—

Y

10h Nonvolatile DAC0 Register

11h Nonvolatile DAC1 Register

12h Nonvolatile DAC2 Register

13h Nonvolatile DAC3 Register

14h Nonvolatile DAC4 Register

15h Nonvolatile DAC5 Register

16h Nonvolatile DAC6 Register

17h Nonvolatile DAC7 Register

DL0

DL1

DL2

DL3

DL4

DL5

DL6

DL7

—

Y

—

Y

—

Y

08h

V

Register

18h Nonvolatile V

Register

REF

09h Power-Down Register

—

Y

19h Nonvolatile Power-Down

Register

—

Y

0Ah Gain and Status Register

—

Y

1Ah Nonvolatile Gain Register

1Bh Reserved

—

Y

0Bh WiperLock™ Technology

Status Register

—

Volatile Memory Address Range

Nonvolatile Memory Address Range

Note 1:

Device Configuration memory bits require a high-voltage enable or disable command

(LATn = V or CS = V ) to modify the bit value.

IHH

TABLE 4-2:

FACTORY DEFAULT POR/BOR VALUES

POR/BOR Value

Function

00h Volatile DAC0 Register

01h Volatile DAC1 Register

02h Volatile DAC2 Register

03h Volatile DAC3 Register

04h Volatile DAC4 Register

05h Volatile DAC5 Register

06h Volatile DAC6 Register

07h Volatile DAC7 Register

7Fh

FFh

1FFh 7FFh

3FFh FFFh

10h Nonvolatile DAC0 Register

11h Nonvolatile DAC1 Register

12h Nonvolatile DAC2 Register

13h Nonvolatile DAC3 Register

14h Nonvolatile DAC4 Register

15h Nonvolatile DAC5 Register

16h Nonvolatile DAC6 Register

17h Nonvolatile DAC7 Register

7Fh

1FFh 7FFh

3FFh FFFh

7Fh

FFh

08h V

Register

0000h 0000h 0000h

18h Nonvolatile V

Register

REF

0000h 0000h 0000h

REF

09h Power-Down Register

19h Nonvolatile Power-Down

Register

0Ah Gain and Status Register

0080h 0080h 0080h

0000h 0000h 0000h

1Ah Nonvolatile Gain Register

0000h 0000h 0000h

(1)

0Bh WiperLock™ Technology

Status Register

1Bh Reserved

—

Volatile Memory address range

Note 1: Reading a reserved memory location results in the SPI command error condition. The SDO pin will output all

‘0’s. Forcing the CS pin to the V state will reset the SPI interface.

Nonvolatile Memory address range

IH

DS20006362A-page 56

 2020 Microchip Technology Inc.

MCP48FXBX4/8

To modify the Configuration bits, the HVC pin must be

forced to the V_IHHstate and then an enable or disable

command must be received for the desired pair of

DAC register addresses.

4.2.6

WIPERLOCK TECHNOLOGY

The MCP48FXBX4/8 WiperLock technology allows

application-specific device settings (DAC register and

configuration) to be secured without requiring the use

of an additional write-protect pin. There are two Con-

figuration bits (DLn:CLn) for each DAC channel (DAC0

through DAC7).

Example: To modify the CL0 bit, the enable or disable

command specifies address 00h; while to modify the

DL0 bit, the enable or disable command specifies

address 10h.

Dependent on the state of the DLn:CLn Configuration

bits, WiperLock technology prevents the serial com-

mands from the following actions on the DACn

registers and bits:

Note:

During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, the MCP48FXBX4/8 will com-

mand error that command byte. To reset

the serial interface state machine, the CS

pin must be driven to the Inactive state

(V_IH) before returning to the Active state

(V_ILor V_IHH).

• Writing to the specified volatile DACn register

memory location

• Writing to the specified nonvolatile DACn register

memory location

• Writing to the specified volatile DACn

Configuration bits

• Writing to the specified nonvolatile DACn

Configuration bits

4.2.6.1

POR/BOR Operation with

Each pair of these Configuration bits controls one of

the four modes.

WiperLock Technology Enabled

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the volatile

DACn register values with the nonvolatile or default

factory values (in case of volatile memory only devices).

TABLE 4-3:

DLn:CLn⁽¹⁾

WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS – FUNCTIONAL DESCRIPTION

Register/Bits

DACn Wiper

DACn Configuration⁽¹⁾

Comments

Volatile Nonvolatile Volatile Nonvolatile

11

10

Locked

All DACn registers are locked.

Unlocked

All DACn registers are locked, except for volatile

DACn Configuration registers. This allows

operation of Power-Down modes.

01

00

Unlocked

Locked

Unlocked

Locked

Volatile DACn registers are unlocked, nonvolatile

DACn registers are locked.

Unlocked

Unlocked All DACn registers are unlocked.

Note 1: The state of these Configuration bits (DLn:CLn) is reflected in the WLnB:WLnA bits, as shown in

Register 4-6. DAC Configuration bits include Voltage Reference Control bits (VRnB:VRnA), Power-Down

Control bits (PDnB:PDnA) and Output Gain bits (Gx).

 2020 Microchip Technology Inc.

DS20006362A-page 57

MCP48FXBX4/8

4.2.7

DEVICE REGISTERS

Register 4-1 shows the format of the DAC Output

Value registers for both volatile and nonvolatile mem-

ory locations. These registers will be either 8 bits,

10 bits or 12 bits wide. The values are right justified.

REGISTER 4-1:

DAC0 TO DAC7: DAC OUTPUT VALUE REGISTERS

(ADDRESSES 00h THROUGH 07h/10h THROUGH 17h; VOLATILE/NONVOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

U-0

—

U-0

—

U-0

—

U-0

—

12-bit

10-bit

8-bit

D11 D10 D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

(1)

—

D09 D08 D07 D06 D05 D04 D03 D02 D01 D00

(1)

—

D07 D06 D05 D04 D03 D02 D01 D00

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= 12-bit device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= 10-bit device

= 8-bit device

12-Bit

10-Bit

8-Bit

bit 15-12 bit 15-10 bit 15-8 Unimplemented: Read as ‘0’

bit 11-0

—

bit 9-0

—

D11-D00: DAC Output Value – 12-bit devices

FFFh = Full-scale output value

7FFh = Midscale output value

000h = Zero scale output value

—

D09-D00: DAC Output Value – 10-bit devices

3FFh = Full-scale output value

1FFh = Midscale output value

000h = Zero scale output value

—

bit 7-0

D07-D00: DAC Output Value – 8-bit devices

FFh = Full-scale output value

7Fh = Midscale output value

000h = Zero scale output value

Note 1: Unimplemented bit, read as ‘0’.

DS20006362A-page 58

 2020 Microchip Technology Inc.

MCP48FXBX4/8

Register 4-2 shows the format of the Voltage

Reference Control register. Each DAC has two bits to

control the source of the DAC’s voltage reference. This

register is for both volatile and nonvolatile memory

locations.

REGISTER 4-2:

VREF: VOLTAGE REFERENCE CONTROL REGISTER

(ADDRESSES 08h AND 18h; VOLATILE/NONVOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

Octal VR7B VR7A VR6B VR6A VR5B VR5A VR4B VR4A VR3B VR3A VR2B VR2A VR1B VR1A VR0B VR0A

(1)

Quad

—

VR3B VR3A VR2B VR2A VR1B VR1A VR0B VR0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-8 Unimplemented: Read as ‘0’

—

bit 15-0 bit 7-0

VRnB:VRnA: DAC Voltage Reference Control

11= V_REFpin (buffered); V_REFbuffer enabled

10= V_REFpin (unbuffered); V_REFbuffer disabled

01= Internal band gap (1.22V typical); V_REFbuffer enabled, V_REFvoltage driven when powered

down

00= V_DD(unbuffered); V_REFbuffer disabled

Use this state with Power-Down bits for lowest current.

Note 1: Unimplemented bit, read as ‘0’.

 2020 Microchip Technology Inc.

DS20006362A-page 59

MCP48FXBX4/8

Register 4-3 shows the format of the Power-Down

Control register. Each DAC has two bits to control the

Power-Down state of the DAC. This register is for both

volatile and nonvolatile memory locations.

REGISTER 4-3:

POWER-DOWN CONTROL REGISTER (ADDRESSES 09h, 19h;

VOLATILE/NONVOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n

Octal PD7B PD7A PD6B PD6A PD5B PD5A PD4B PD4A PD3B PD3A PD2B PD2A PD1B PD1A PD0B PD0A

(1)

Quad

—

PD0B PD0A PD0B PD0A PD0B PD0A PD0B PD0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-8 Unimplemented: Read as ‘1’

—

bit 15-0 bit 7-0

PDnB:PDnA: DAC Power-Down Control⁽²⁾

11= Powered down – V_OUTis open circuit

10= Powered down – V_OUTis loaded with a 125 k resistor to ground

01= Powered down – V_OUTis loaded with a 1 k resistor to ground

00= Normal operation (not powered down)

Note 1: Unimplemented bit, read as ‘0’.

2: See Table 5-4 for more details.

DS20006362A-page 60

 2020 Microchip Technology Inc.

MCP48FXBX4/8

Register 4-4 shows the format of the volatile Gain

Control and System Status register. Each DAC has one

bit to control the gain of the DAC and three status bits.

REGISTER 4-4:

GAIN CONTROL AND SYSTEM STATUS REGISTER (ADDRESS 0Ah; VOLATILE)

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/C-1

R-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

Octal

Quad

G7

G6

G5

G4

G3

G2

G1

G0 POR EEWA

(1)

—

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

C = Clearable bit

‘0’ = Bit is cleared

U = Unimplemented bit, read as ‘0’

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-12 Unimplemented: Read as ‘0’

—

bit 15-8 bit 11-8

Gn: DAC Channel n Output Driver Gain Control

1= 2x gain

0= 1x gain

bit 7

POR: Power-on Reset (Brown-out Reset) Status bit

This bit indicates if a POR or BOR event has occurred since the last READcommand of this

register. Reading this register clears the state of the POR status bit.

1= A POR (BOR) event has occurred since the last read of this register; reading this register

clears this bit

0= A POR (BOR) event has not occurred since the last read of this register

bit 6

EEWA: EEPROM Write Active Status

This bit indicates if the EEPROM write cycle is occurring.

1= An EEPROM write cycle is currently occurring; only serial commands to the volatile mem-

ory are allowed

0= An EEPROM write cycle is NOT currently occurring

bit 5-0

Unimplemented: Read as ‘0’

Note 1: Unimplemented bit, read as ‘0’.

 2020 Microchip Technology Inc.

DS20006362A-page 61

MCP48FXBX4/8

Register 4-5 shows the format of the nonvolatile Gain

Control register. Each DAC has one bit to control the

gain of the DAC.

REGISTER 4-5:

GAIN CONTROL REGISTER (ADDRESS 1Ah; NONVOLATILE

)

U-0

—

R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n R/W-n U-0

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

U-0

—

Octal

Quad

—

G7

G6

G5

(1)

G4

G3

G2

G1

G0

(1)

—

bit 15

bit 0

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-12 Unimplemented: Read as ‘0’

—

bit 15-8 bit 11-8

Gn: DACn Output Driver Gain Control bits

1= 2x gain

0= 1x gain

bit 7-0

Unimplemented bits.

Note 1: Unimplemented bit, read as ‘0’.

DS20006362A-page 62

 2020 Microchip Technology Inc.

MCP48FXBX4/8

Register 4-6 shows the format of the DAC WiperLock

Technology Status register.

REGISTER 4-6:

DAC WiperLock™ TECHNOLOGY STATUS REGISTER (ADDRESS 0Bh; VOLATILE)

(1)

R-0

WL7B WL7A WL6B WL6A WL5B WL5A WL4B WL4A WL3B WL3A WL2B WL2A WL1B WL1A WL0B WL0A

Octal

Quad

(2)

—

WL3B WL3A WL2B WL2A WL1B WL1A WL0B WL0A

bit 0

bit 15

Legend:

R = Readable bit

-n = Value at POR

= Quad-channel device

W = Writable bit

‘1’ = Bit is set

U = Unimplemented bit, read as ‘0’

‘0’ = Bit is cleared

x = Bit is unknown

= Octal-channel device

Octal

Quad

bit 15-8 Unimplemented: Read as ‘0’

bit 15-0 bit 7-0 WLnB:WLnA: WiperLock™ Technology Status

—

These bits reflect the state of the DLn:CLn nonvolatile Configuration bits.

11= DAC Wiper and DAC Configuration (volatile and nonvolatile registers) are locked

(DLn = CLn = Enabled)

10= DAC Wiper (volatile and nonvolatile) and DAC Configuration (nonvolatile registers) are

locked (DLn = Enabled; CLn = Disabled)

01= DAC Wiper (nonvolatile) and DAC Configuration (nonvolatile registers) are locked

(DLn = Disabled; CLn = Enabled)

00= DAC Wiper and DAC Configuration are unlocked (DLn = CLn = Disabled)

Note 1: POR value depends on the programmed values of the DLn:CLn Configuration bits. The devices are

shipped with a default DLn:CLn Configuration bit state of ‘0’.

2: Unimplemented bit, read as ‘0’.

 2020 Microchip Technology Inc.

DS20006362A-page 63

MCP48FXBX4/8

NOTES:

DS20006362A-page 64

 2020 Microchip Technology Inc.

MCP48FXBX4/8

The functional blocks of the DAC include:

5.0

DAC CIRCUITRY

• Resistor Ladder

The Digital-to-Analog Converter circuitry converts a

digital value into its analog representation. The

description shows the functional operation of the device.

• Voltage Reference Selection

• Output Buffer/V_OUTOperation

• Internal Band Gap

The DAC circuit uses a resistor ladder implementation.

Devices have up to eight DACs.

• Latch Pins (LATn)

• Power-Down Operation

Figure 5-1 shows the functional block diagram for the

MCP48FXBX4/8 DAC circuitry.

Power-Down

Operation

V_DD

PDnB:PDnAand

VRnB:VRnA

Internal Band Gap

V_DD

Voltage

Reference

Selection

V_REF

VRnB:VRnA and

PDnB:PDnA

Band Gap

(1.22V typical)

V_DD

PDnB:PDnA

VRnB:VRnA

Power-Down

Operation

V

A (RL)

RL

DAC

Output

Selection

V_DD

R_{S(2 )}

n

PDnB:PDnA

R_S(2

n

– 1)

V_W

R_S(2n _{– 2)}

V_OUT

R_S(2n _{– 3)}

PDnB:PDnA

Gain

(1x or 2x)

R_RL

(~120 k)

Output Buffer/V_OUT

Operation

Power-Down

Operation

R_S(2)

R_S(1)

DAC Register Value

V_W= ---------------------------------------------------------------------  V_RL

# Resistor in Resistor Ladder

B

Where:

# Resistors in Resistor Ladder =

Resistor Ladder

256 (MCP48FXB0X)

1024 (MCP48FXB1X)

4096 (MCP48FXB2X)

FIGURE 5-1:

MCP48FXBX4/8 DAC Module Block Diagram.

 2020 Microchip Technology Inc.

DS20006362A-page 65

MCP48FXBX4/8

Equation 5-1 shows the calculation for the step

resistance:

5.1

Resistor Ladder

The resistor ladder is a digital potentiometer with the B

Terminal internally grounded and the A Terminal

connected to the selected reference voltage (see

Figure 5-2). The volatile DAC register controls the

wiper position. The Wiper Voltage (V_W) is proportional

to the DAC register value divided by the number of

Resistor Elements (R_S) in the ladder (256, 1024 or

4096) related to the V_RLvoltage.

EQUATION 5-1:

R_SCALCULATION

R_RL

R_S= -------------

8-Bit Device

256

R_RL

R_S= ----------------

10-Bit Device

12-Bit Device

1024

The output of the resistor network will drive the input of

an output buffer.

R_RL

R_S= ----------------

4096

V

RL

DAC

The maximum wiper position is 2ⁿ– 1,

while the number of resistors in the

resistor ladder is 2ⁿ. This means that

when the DAC register is at full scale,

there is one Resistor Element (R_S)

between the wiper and the V_RLvoltage.

Register

Note:

PDnB:PDnA

R_{S(2 )}

n

(1)

2ⁿ– 1

2ⁿ– 2

R_W

R_S(2

n

( )

1

– 1)

R_W

If the unbuffered V_REFpin is used as the V_RLvoltage

source, this voltage source should have a low output

impedance.

R_S(2n _{– 2)}

( )

1

R_W

2ⁿ– 3

When the DAC is powered down, the resistor ladder is

disconnected from the selected reference voltage.

V_W

R_S(2n _{– 3)}

5.2

Voltage Reference Selection

( )

1

R_W

R_RL

2

The resistor ladder has up to four sources for the

reference voltage. Two user control bits (VRnB:VRnA)

are used to control the selection with the selection con-

nected to the V_RLnode (see Figure 5-3 and Figure 5-4).

R_S(2)

( )

1

R_W

1

0

R_S(1)

( )

1

R_W

VRnB:VRnA

V_REF

V_DD

Analog Mux

Band Gap

V_RL

Note 1:

The analog Switch Resistance (R ) does not

W

affect performance due to the voltage divider

configuration.

Buffer

FIGURE 5-2:

Resistor Ladder Model.

FIGURE 5-3:

Resistor Ladder Reference

The resistor network is made of these three parts:

Voltage Selection Block Diagram.

• Resistor ladder (string of R_Selements)

• Wiper switches

• DAC register decode

The four voltage source options for the resistor ladder

are:

1. V_DDpin voltage.

The Resistor Ladder (R_RL) has a typical impedance of

approximately 120 k. This resistance may vary from

device to device by up to ±20%. Since this is a voltage

divider configuration, the actual R_RLresistance does

2. Internal Voltage Reference (V_BG).

3.

V_REFpin voltage unbuffered.

4. V_REFpin voltage internally buffered.

not affect the output given a fixed voltage at V_RL

.

DS20006362A-page 66

 2020 Microchip Technology Inc.

MCP48FXBX4/8

The selection of the voltage is specified with the volatile

VRnB:VRnA Configuration bits (see Register 4-2).

There are nonvolatile and volatile VRnB:VRnA Config-

uration bits. On a POR/BOR event, the state of the

nonvolatile VRnB:VRnA Configuration bits is latched

into the volatile VRnB:VRnA Configuration bits.

5.2.2

UNBUFFERED MODE

The V_REFpin voltage may be from V_SSto V_DD

.

Note 1: The voltage source should have a low

output impedance. If the voltage source

has a high output impedance, then the

voltage on the V_REFpin is lower than

expected. The resistor ladder has a

typical impedance of 140 k and a typical

capacitance of 29 pF.

When the user selects the V_DDas reference, the V_REF

pin voltage is not connected to the resistor ladder.

V_DD

2: If the V_REFpin is tied to the V_DDvoltage,

the V_DDmode (VRnB:VRnA

recommended.

= 00) is

PDnB:PDnA and

VRnB:VRnA

5.2.3

BAND GAP MODE

PDnB:PDnA and

VRnB:VRnA

If the internal band gap is selected, then the external

V_REFpin should not be driven and should only use

high-impedance loads.

(1)

Band Gap

(1.227V typical)

The band gap output is buffered, but the internal

switches limit the current that the output should source

to the V_REFpin. The resistor ladder buffer is used to

drive the band gap voltage for the cases of multiple

DAC outputs. This ensures that the resistor ladders are

always properly sourced when the band gap is

selected.

V_RL

+

–

V_REF

V_DD

5.3

Internal Band Gap

The internal band gap is designed to drive the resistor

ladder buffer.

PDnB:PDnA and

VRnB:VRnA

The resistance of a Resistor Ladder (R_RL) is targeted to

be 140 k (40 k), which means a minimum

resistance of 100 k.

Note 1: The Band Gap Voltage (V_BG) is 1.22V

typical. The band gap output goes

through the buffer with a 2x gain to

create the V_RLvoltage. See Table 5-1

for additional information on the

band gap circuit.

The band gap selection can be used across the V_DD

voltages while maximizing the V_OUTvoltage ranges.

For V_DDvoltages below the 2 × Gain × V_BGvoltage, the

output for the upper codes will be clipped to the V_DD

voltage. Table 5-1 shows the maximum DAC register

code given device V_DDand Gain bit setting.

FIGURE 5-4:

Reference Voltage Selection

Implementation Block Diagram.

If the V_REFpin is selected, then a selection has to be

made between the Buffered and Unbuffered mode.

TABLE 5-1:

V_OUTUSING BAND GAP

Max DAC Code⁽¹⁾

5.2.1

BUFFERED MODE

Comment

12-Bit 10-Bit 8-Bit

The V_REFpin voltage may be from 0.01V to V_DD– 0.04V.

The input buffer (amplifier) provides low offset voltage,

low noise and a very high input impedance, with only

minor limitations on the input range and frequency

response.

1

2

1

2

FFFh 3FFh FFh V_OUT(max)= 2.44V⁽²⁾

FFFh 3FFh FFh V_OUT(max)= 4.88V⁽²⁾

FFFh 3FFh FFh V_OUT(max)= 2.44V⁽²⁾

8CDh 233h 8Ch ~ 0 to 56% range

5.5

2.7

Note 1: Any variation or noises on the reference

source can directly affect the DAC output.

The reference voltage needs to be as

clean as possible for accurate DAC

performance.

Note 1: Without the V_OUTpin voltage being

clipped.

2: When V_BG= 1.22V typical.

3: Band gap performance achieves full

performance starting from a V_DDof 2.0V.

2: If the V_REFpin is tied to the V_DDvoltage,

the V_DDmode (VRnB:VRnA

recommended.

= 00) is

 2020 Microchip Technology Inc.

DS20006362A-page 67

MCP48FXBX4/8

5.4.2

OUTPUT VOLTAGE

5.4

Output Buffer/V

Operation

OUT

The volatile DAC register values, along with the

device’s Configuration bits, control the analog V_OUT

voltage. The volatile DAC register’s value is unsigned

binary. The formula for the output voltage is given in

Equation 5-2. Table 5-5 shows examples of volatile

DAC register values and the corresponding theoretical

The output driver buffers the Wiper Voltage (V_W) of the

resistor ladder.

The DAC output is buffered with a low-power and pre-

cision output amplifier (op amp). This amplifier provides

a rail-to-rail output with low offset voltage and low

noise. The amplifier’s output can drive the resistive and

high capacitive loads without oscillation. The amplifier

provides a maximum load current, which is enough for

most programmable voltage reference applications.

See Section 1.0 “Electrical Characteristics” for the

specifications of the output amplifier.

V

_OUTvoltage for the MCP48FXBX4/8 devices.

EQUATION 5-2: CALCULATING OUTPUT

VOLTAGE (V_OUT

V_RL DAC Register Value

)

V_OUT= ---------------------------------------------------------------------  Gain

# Resistor in Resistor Ladder

Note:

The load resistance must be kept higher

than 5 k for the stable and expected

analog output (to meet electrical

specifications).

Where:

# Resistors in R-Ladder = 4096 (MCP48FXB2X)

1024 (MCP48FXB1X)

256 (MCP48FXB0X)

Figure 5-5 shows the block diagram of the output driver

circuit.

The user can select the output gain of the output

amplifier. The gain options are:

Note:

When Gain = 2 (V_RL= V_REF) and if

V_REF> V_DD/2, the V_OUTvoltage will be

limited to V_DD. So if V_REF= V_DD, then the

V_OUTvoltage will not change for volatile

DAC register values midscale and

greater, since the op amp is at full-scale

output.

a) Gain of 1, when either the V_DD, External V_REFor

Band Gap mode are used. In case of the Band

Gap mode, the effective gain is 2; see

Section 5.3 “Internal Band Gap”.

b) Gain of 2, when the External V_REFor Internal

Band Gap modes are used. In case of the Band

Gap mode, the effective gain is 4; see

Section 5.3 “Internal Band Gap”.

The following events update the DAC register value,

and therefore, the analog Voltage Output (V_OUT):

• POR

• BOR

• WRITEcommand

V_DD

The V_OUTvoltage starts driving to the new value after

the event has occurred.

PDnB:PDnA

5.4.3

STEP VOLTAGE (V_S)

V_W

+

–

The step voltage depends on the device resolution and

the calculated output voltage range. One LSb is

defined as the ideal voltage difference between two

successive codes. The step voltage can be easily cal-

culated by using Equation 5-3 (DAC register value is

equal to 1). Theoretical step voltages are shown in

Table 5-2 for several V_REFvoltages.

V_OUT

PDnB:PDnA

Gain

(1x or 2x)

EQUATION 5-3:

V_SCALCULATION

FIGURE 5-5:

5.4.1

Output Driver Block Diagram.

V_RL

V_S= ---------------------------------------------------------------------  Gain

# Resistor in Resistor Ladder

PROGRAMMABLE GAIN

Where:

The amplifier’s gain is controlled by the Gain (G)

Configuration bit (see Register 4-5) and the V_RL

reference selection.

# Resistors in R-Ladder = 4096 (12-bit)

1024 (10-bit)

The volatile Gain bit value can be modified by:

• POR events

256 (8-bit)

• BOR events

• SPI WRITEcommands

DS20006362A-page 68

 2020 Microchip Technology Inc.

MCP48FXBX4/8

TABLE 5-2:

THEORETICAL STEP

VOLTAGE (V_S)⁽¹⁾

5.4.5

DRIVING RESISTIVE AND

CAPACITIVE LOADS

The V_OUTpin can drive up to 100 pF of capacitive load

in parallel with a 5 k resistive load (to meet electrical

specifications).

V

REF

5.0

2.7

1.8

1.5

1.0

1.22 mV 659 µV 439 µV 366 µV 244 µV 12-bit

4.88 mV 2.64 mV 1.76 mV 1.46 mV 977 µV 10-bit

19.5 mV 10.5 mV 7.03 mV 5.86 mV 3.91 mV 8-bit

V_OUTdrops slowly as the load resistance decreases

after about 3.5 k. It is recommended to use a load with

R_Lgreater than 5 k.

V

S

Driving large capacitive loads can cause stability

problems for voltage feedback op amps. As the load

capacitance increases, the feedback loop’s phase mar-

gin decreases and the closed-loop bandwidth is

reduced. This produces gain peaking in the frequency

response with overshoot and ringing in the step

response. That is, since the V_OUTpin’s voltage does

not quickly follow the buffer’s input voltage (due to the

large capacitive load), the output buffer will overshoot

the desired target voltage. Once the driver detects this

overshoot, it compensates by forcing it to a voltage

below the target. This causes voltage ringing on the

V_OUTpin.

Note 1: When Gain = 1x, V = V and V = 0V.

FS

RL

ZS

5.4.4

Figure 5-6 shows an example of the slew rate for the

_OUTpin. The slew rate can be affected by the charac-

OUTPUT SLEW RATE

V

teristics of the circuit connected to the V_OUTpin.

V_OUT(B)

V_OUT(A)

When driving large capacitive loads with the output

buffer, a small Series Resistor (R_ISO) at the output (see

Figure 5-7) improves the output buffer’s stability (feed-

back loop’s phase margin) by making the output load

resistive at higher frequencies. The bandwidth will be

generally lower than the bandwidth with no capacitive

load.

DACn = A

DACn = B

Time

V

_OUTB– V_OUTA

Slew Rate = --------------------------------------------------

T

FIGURE 5-6:

V_OUTPin Slew Rate.

V_OUT

V_W

R_ISO

R_L

5.4.4.1 Small Capacitive Load

+

–

V_CL

With a small Capacitive Load (C_L), the output buffer’s

current is not affected, but the V_OUTpin’s voltage is not

a step transition from one output value (DAC register

value) to the next output value. The change of the V_OUT

voltage is limited by the output buffer’s characteristics,

so the V_OUTpin voltage will have a slope from the old

voltage to the new one. This slope is fixed for the output

buffer and is referred to as the Buffer Slew Rate

(SR_BUF).

C_L

Gain

FIGURE 5-7:

Circuit to Stabilize the

Output Buffer for Large Capacitive Loads (C_L).

The R_ISOresistor value for your circuit needs to be

selected. The resulting frequency response peaking

and step response overshoot for this R_ISOresistor

value should be verified on the bench. Modify the

R_ISO’s resistance value until the output characteristics

meet your requirements.

5.4.4.2

Large Capacitive Load

With a larger capacitive load, the slew rate is determined

by two factors:

• The output buffer’s Short-Circuit Current (I_SC

)

• The V_OUTpin’s external load

A method to evaluate the system’s performance is to

inject a step voltage on the V_REFpin and observe the

I_OUTcannot exceed the output buffer’s Short-Circuit

Current (I_SC), which fixes the output Buffer Slew Rate

V_OUTpin’s characteristics.

(SR_BUF). The voltage on the Capacitive Load, V_CL

changes at a rate proportional to I_OUT, which fixes a

Capacitive Load Slew Rate (SR_CL).

,

Note: Additional insight into circuit design for

driving capacitive loads can be found in

AN884, “Driving Capacitive Loads with

Op Amps” (DS00884).

The V_CLvoltage slew rate is limited to the slower of the

output buffer’s internally set Slew Rate (SRBUF) and

the Capacitive Load Slew Rate (SR_CL).

 2020 Microchip Technology Inc.

DS20006362A-page 69

MCP48FXBX4/8

The Power-Down bits are modified by using a WRITE

command to the volatile Power-Down register or a POR

event which transfers the nonvolatile Power-Down

register to the volatile Power-Down register.

5.5

Power-Down Operation

To allow the application to conserve power when the

DAC operation is not required, three Power-Down

modes are available. The Power-Down configuration

bits (PDnB:PDnA) control the power-down operation

(Figure 5-8 and Table 5-3). On devices with multiple

DACs, each DACs Power-Down mode is individually

controllable. All Power-Down modes do the following:

TABLE 5-3:

POWER-DOWN BITS AND

OUTPUT RESISTIVE LOAD

PDnB PDnA

Function

0

1

0

1

0

1

Normal operation

• Turn off most DAC module’s internal circuits

(output op amp, resistor ladder, etc.)

1 k resistor to ground

125 k resistor to ground

Open circuit

• Op amp output becomes high-impedance to the

V_OUTpin

• Disconnect the resistor ladder from the Reference

Table 5-4 shows the current sources for the DAC based

on the selected source of the DAC’s reference voltage

and if the device is in a normal operating mode or in

one of the Power-Down modes.

Voltage (V_RL

)

• Retain the value of the volatile DAC register and

Configuration bits and the nonvolatile (EEPROM)

DAC register and Configuration bits

TABLE 5-4:

DAC CURRENT SOURCES

Depending on the selected Power-Down mode, the

following will occur:

PDnB:A = 00,

PDnB:A  00,

Device V_DD

Current

Source

• V_OUTpin is switched to one of the two resistive

pull-downs (see Table 5-4):

VRnB:A =

00 01 10 11 00 01 10 11

- 125 k (typical)

- 1 k (typical)

• Op amp is powered down and the V_OUTpin

becomes high-impedance

Output Op Amp

Y

N⁽¹⁾

Y

N

N⁽¹⁾

N

Resistor

Ladder

RL Op Amp

Band Gap

N

Y

N

Y

N

Y

N

There is a delay (T_PDE) between the PDnB:PDnA bits,

changing from ‘00’ to either ‘01’, ‘10’ or ‘11’, with the op

amp no longer driving the V_OUToutput and the pull-down

resistors sinking current.

Note 1: Current is sourced from the V_REFpin, not

the device V_DD

.

Section 7.0 “SPI Device Commands” describes the

SPI commands for writing the power-down bits. The com-

mand that can update the volatile PDnB:PDnA bits is a

WRITEcommand (normal and high voltage).

V_DD

PDnB:PDnA

V_W

Note:

The SPI serial interface circuit is not

affected by the Power-Down mode. This

circuit remains active in order to receive

any command that might come from the

master device.

V_OUT

PDnB:PDnA

Gain

(1x or 2x)

FIGURE 5-8:

V_OUTPower-Down Block

Diagram.

In any of the Power-Down modes where the V_OUTpin

is not externally connected (sinking or sourcing cur-

rent), the power-down current will typically be 680 nA

for a quad DAC device. As the number of DACs

increases, the device’s power-down current will also

increase.

DS20006362A-page 70

 2020 Microchip Technology Inc.

MCP48FXBX4/8

5.5.1

EXITING POWER-DOWN

5.6

DAC Registers, Configuration Bits

and Status Bits

When the device exits Power-Down mode, the

following occurs:

The MCP48FXBX4/8 device family has both volatile

and nonvolatile (EEPROM) memory options. Table 4-2

shows the volatile and nonvolatile memory, and their

interaction due to a POR event.

• Disabled circuits (op amp, resistor ladder, etc.)

are turned on

• The resistor ladder is connected to the selected

Reference Voltage (V_RL

)

There are five Configuration bits, DAC registers, and two

volatile status bits in both the volatile and nonvolatile

memory. The DAC registers (volatile and nonvolatile) will

be either twelve bits (MCP48FXB2X), ten bits

(MCP48FEB1X) or eight bits (MCP48FXB0X) wide.

• The selected pull-down resistor is disconnected

• The V_OUToutput will be driven to the voltage

represented by the volatile DAC register’s value

and Configuration bits

When the device is first powered up, it automatically

uploads the EEPROM memory values or factory

default values (in case of MCP48FVBXX devices) to

the volatile memory. The volatile memory determines

the analog Output Voltage (V_OUT) pin. After the device

is powered up, the user can update the memory.

The V_OUToutput signal requires time as these circuits

are powered up and the output voltage is driven to the

specified value as determined by the volatile DAC

register and Configuration bits.

Note:

Since the op amp and resistor ladder are

powered off (0V), the op amp’s Input

Voltage (V_W) can be considered 0V. There

This memory is read and written through the SPI inter-

face. See Section 6.0 “SPI Serial Interface Module”

and Section 7.0 “SPI Device Commands” for more

details on reading and writing the device’s memory.

is

a

delay (T_PDD

)

between the

PDnB:PDnA bits updating to ‘00’ and the

op amp driving the V_OUToutput. The

op amp’s settling time (from 0V) needs to

be taken into account to ensure the V_OUT

voltage reflects the selected value.

When the nonvolatile memory is written, the device

starts writing the EEPROM cell at the Acknowledge

pulse of the WRITEsingle memory location command.

Register 4-4 shows the operation of the device status

bits and Table 4-2 shows the factory default value of a

POR/BOR event for the device Configuration bits.

Any WRITEcommand where the PDnB:PDnA bits are

‘00’ will cause the device to exit the Power-Down mode.

There are two status bits. These are only in volatile

memory and indicate the status of the device. The POR

bit indicates if the device V_DDis above or below the

POR trip point. During normal operation, this bit should

be ‘1’. The EEWA bit indicates if an EEPROM write

cycle is in progress. While the EEWA bit is ‘1’ (during

the EEPROM writing), all commands are ignored,

except for the READcommand.

 2020 Microchip Technology Inc.

DS20006362A-page 71

MCP48FXBX4/8

5.7

Latch Pins (LATn)

Serial Shift Reg.

The Latch pins control when the volatile DAC register

value is transferred to the DAC wiper. This is useful for

applications that need to synchronize the wiper(s)

updates to an external event, such as zero-crossing or

updates to the other wipers on the device. The LAT pin

functionality is asynchronous to the serial interface

operation.

Register Address

WRITECommand

16 Clocks

Vol. DAC Register n

Transfer

Data

LAT

SYNC

(internal signal)

When the LAT pin is high, transfers from the volatile DAC

register to the DAC wiper are inhibited. The volatile DAC

register value(s) can continue to update.

DAC Wiper n

Transfer

Data

When the LAT pin is low, the volatile DAC register value

is transferred to the DAC wiper.

LAT SYNC

Comment

1

0

1

0

1

0

1

0

No Transfer

Note:

This allows the volatile DAC0 through

DAC7 registers to be updated while the

LATn pins are high, and to have outputs

synchronously updated as the LATn pins

are driven low.

Vol. DAC Register n  DAC Wiper n

No Transfer

FIGURE 5-9:

LAT and DAC Interaction.

Figure 5-9 shows the interaction of the LAT pin and the

loading of the DAC Wiper n (from the volatile DAC

register n). The transfers are level-driven. If the LAT pin

is held low, the corresponding DAC wiper is updated as

soon as the volatile DAC register value is updated.

Since the DAC wiper n is updated from the volatile DAC

register n, all DACs that are associated with a given

LAT pin can be updated synchronously.

If the application does not require synchronization, then

this signal should be tied low.

The LAT pin allows the DAC wiper to be updated to

an external event and have multiple DAC

channels/devices updating at a common event.

Figure 5-10 shows two examples of using the LAT pin

to control when the Wiper register is updated relative to

the value of a sine wave signal.

Case 1: Zero-Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Case 2: Fixed-Point Crossing of Sine Wave to Update the Volatile DAC0 Register (using LAT pin)

Indicates Where LAT Pin Pulses are Active (volatile DAC0 register updated)

FIGURE 5-10:

LAT Pin Operation Example.

DS20006362A-page 72

 2020 Microchip Technology Inc.

MCP48FXBX4/8

TABLE 5-5:

Device

DAC INPUT CODE VS. CALCULATED ANALOG OUTPUT (V_OUT) (V_DD= 5.0V)

(3)

LSb

Equation

5.0V/4096 1,220.7

2.5V/4096 610.4

V_OUT

Equation

Volatile DAC

Register Value

Gain

(1)

V_RL

Selection⁽²⁾

µV

V

1111 1111 1111 5.0V

1x

2x⁽²⁾

V_RL (4095/4096)  1

V_RL (4095/4096)  2)

V_RL (2047/4096)  1)

V_RL (2047/4096)  2)

V_RL (1023/4096)  1)

V_RL (1023/4096)  2)

V_RL (0/4096) * 1)

V_RL (0/4096) * 2)

V_RL (1023/1024)  1

V_RL (1023/1024)  2

V_RL (511/1024)  1

V_RL (511/1024)  2

V_RL (255/1024)  1

V_RL (255/1024)  2

V_RL (0/1024)  1

4.998779

2.499390

4.998779

2.498779

1.249390

2.498779

1.248779

0.624390

1.248779

0

2.5V

0111 1111 1111 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0011 1111 1111 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0000 0000 0000 5.0V

5.0V/4096 1,220.7

2.5V/4096 610.4

1x

2.5V

1x

2x⁽²⁾

0

11 1111 1111

01 1111 1111

00 1111 1111

00 0000 0000

1111 1111

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

4.995117

2.497559

4.995117

2.495117

1.247559

2.495117

1.245117

0.622559

1.245117

0

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

2x⁽²⁾

5.0V

2.5V

5.0V/1024 4,882.8

2.5V/1024 2,441.4

1x

V_RL (0/1024)  1

0

2x⁽²⁾

V_RL (0/1024)  1

0

5.0V

2.5V

5.0V/256 19,531.3

1x

V_RL (255/256)  1

V_RL (255/256)  2

V_RL (127/256)  1

V_RL (127/256)  2

V_RL (63/256)  1

4.980469

2.490234

4.980469

2.480469

1.240234

2.480469

1.230469

0.615234

1.230469

0

2.5V/256

9,765.6

1x

2x⁽²⁾

0111 1111

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

2x⁽²⁾

0011 1111

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

2x⁽²⁾

V_RL (63/256)  1

V_RL (63/256)  2

0000 0000

5.0V

2.5V

5.0V/256 19,531.3

2.5V/256 9,765.6

1x

V_RL (0/256)  1

1x

V_RL (0/256)  1

0

2x⁽²⁾

V_RL (0/256)  2

0

Note 1:

V_RLis the resistor ladder’s reference voltage. It is independent of the VRnB:VRnA selection.

2: Gain selection of 2x (Gx = 1) requires the voltage reference source to come from the V_REFpin

(VRnB:VRnA = 10or 11) and requires a V_REFpin voltage (or V_RL) ≤ V_DD/2, or from the internal band gap

(VRnB:VRnA = 01).

3: These theoretical calculations do not take into account the offset, gain and nonlinearity errors.

 2020 Microchip Technology Inc.

DS20006362A-page 73

MCP48FXBX4/8

NOTES:

DS20006362A-page 74

 2020 Microchip Technology Inc.

MCP48FXBX4/8

The MCP48FXBX4/8 SPI’s module supports two (of

the four) standard SPI modes. These are Mode 0,0

and 1,1. The SPI mode is determined by the state of

the SCK pin (V_IHor V_IL) when the CS pin transitions

from inactive (V_IH) to active (V_IL).

6.0

SPI SERIAL INTERFACE

MODULE

The MCP48FXBX4/8 devices’ SPI serial interface

module supports the SPI serial protocol specification.

An additional HVC pin is available for High-Voltage

Command support. High-Voltage Commands allow the

device to enable and disable nonvolatile Configuration

bits. Without a high voltage present, those bits are

inhibited from being modified.

The command format and waveforms for the

MCP48FXBX4/8 are defined in Section 7.0 “SPI

Device Commands”.

6.1

Overview

The HVC pin is high-voltage tolerant. To enter a High-

Voltage Command, the HVC pin must be greater than

the V_IHHvoltage.

This section discusses some of the specific

characteristics of the MCP48FXBX4/8’s serial interface

module.

6.2.1

SPI MODES

The following sections discuss some of these

device-specific characteristics:

The SPI module supports two (of the four) standard

SPI modes. These are Mode 0,0 and 1,1. The mode is

determined by the state of the SDI pin on the rising

edge of the first clock bit (of the 8-bit byte).

• SPI Serial Interface

• Interface Pins (CS, SCK, SDI, SDO and

LAT/HVC)

• Communication Data Rates

• POR/BOR

6.2.1.1

Mode 0,0

In Mode 0,0:

• SCK Idle state = low (V_IL)

6.2

SPI Serial Interface

• Data are clocked in on the SDI pin on the rising

edge of SCK

The MCP48FXBX4/8 devices support the SPI serial

protocol. This SPI operates in Slave mode (does not

generate the serial clock).

• Data are clocked out on the SDO pin on the falling

edge of SCK

The SPI interface uses up to four pins. These are:

6.2.1.2

Mode 1,1

• CS – Chip Select

• SCK – Serial Clock

• SDI – Serial Data In (MOSI)

• SDO – Serial Data Out (MISO)

In Mode 1,1:

• SCK Idle state = high (V_IH)

• Data are clocked in on the SDI pin on the rising

edge of SCK

Typical SPI interfaces are shown in Figure 6-1. In the

SPI interface, the master’s output pin is connected to

the slave’s input pin, and the master’s input pin is

connected to the slave’s output pin.

• Data are clocked out on the SDO pin on the falling

edge of SCK

6.3

Interface Pins (CS, SCK, SDI, SDO

and LAT/HVC)

Typical SPI Interface Connections

Host

Controller

MCP48FXBXX

The operation of the five interface pins and the High-

Voltage Command (HVC) pin is discussed in this

section. The pins are:

Other Devices

SDO

SDI

• SDI (Serial Data In)

• SDO (Serial Data Out)

• SCK (Serial Clock)

SDO

SCK

• CS (Chip Select)

• LAT/HVC (High-Voltage Command)

GPIO

CS

LAT/HVC

The serial interface works on either 8-bit or 24-bit

boundaries depending on the selected command. The

Chip Select (CS) pin frames the SPI commands.

(Master)

(Slave)

FIGURE 6-1:

Typical SPI Interface Block

Diagram.

 2020 Microchip Technology Inc.

DS20006362A-page 75

MCP48FXBX4/8

6.3.1

SERIAL DATA IN (SDI)

6.3.4

CS SIGNAL

The Serial Data In (SDI) signal is the data signal into

the device. The value on this pin is latched on the

rising edge of the SCK signal.

The Chip Select (CS) signal is used to select the

device and frame a command sequence. To start a

command, or sequence of commands, the CS signal

must transition from the Inactive state (V_IH) to an

Active state (V_ILor V_IHH).

6.3.2

SERIAL DATA OUT (SDO)

The Serial Data Out (SDO) signal is the data signal out

of the device. The value on this pin is driven on the

falling edge of the SCK signal.

After the CS signal has gone active, the SDO pin is

driven and the clock bit counter is reset.

Note: There is a required delay after the CS pin

Once the CS pin is forced to the active level (V_ILor

V_IHH), the SDO pin will be driven. The state of the

SDO pin is determined by the serial bit’s position in the

command, the command selected and if there is a

Command Error (CMDERR) state.

goes active to the first edge of the SCK pin.

If an error condition occurs for an SPI command, then

the command byte’s Command Error (CMDERR) bit

(on the SDO pin) will be driven low (V_IL). To exit the

error condition, the user must take the CS pin to the

6.3.3

SERIAL CLOCK (SCK)

V_IHlevel.

(SPI FREQUENCY OF OPERATION)

When the CS pin returns to the Inactive state (V_IH), the

SPI module resets (including the Address Pointer).

While the CS pin is in the Inactive state (V_IH), the serial

interface is ignored. This allows the host controller to

interface to other SPI devices using the same SDI,

SDO and SCK signals.

The SPI interface is specified to operate up to 20 MHz.

The actual clock rate depends on the configuration of

the system and the serial command used. Table 6-1

shows the SCK frequency for different configurations.

TABLE 6-1:

SCK FREQUENCY

Command

Write,

6.3.5

HVC SIGNAL

The high-voltage capability of the HVC pin allows High-

Voltage Commands. High-Voltage Commands allow the

device’s WiperLock technology and write-protect

features to be enabled and disabled.

Memory Type Access

Read

Enable,

Disable

Nonvolatile

Memory

SDI, SDO 10 MHz

20 MHz^(1,2)

6.4

Communication Data Rates

Volatile

Memory

20 MHz⁽²⁾

The MCP48FXBX4/8 devices support clock rates (bit

rate) of up to 20 MHz for WRITE commands and

10 MHz for READcommands.

Note 1: After a WRITEcommand, the internal

write cycle must be completed before the

next SPI command is received.

For most applications, the write time will be considered

more important, since that is how the device operation

is controlled.

2: This is a design goal. The SDO pin

performance is believed to be the limiting

factor.

6.5

POR/BOR

On a POR/BOR event, the SPI serial interface module

state machine is reset, which means that the device’s

Memory Address Pointer is forced to 00h.

DS20006362A-page 76

 2020 Microchip Technology Inc.

MCP48FXBX4/8

7.0

SPI DEVICE COMMANDS

Command Byte

The MCP48FXBX4/8 devices’ SPI command format

supports 32 memory address locations and four

commands:

AD AD AD AD AD C

C

0

X

4

3

2

1

0

1

Legend:

• WRITEcommand (C1:C0 = 00)

• READcommand (C1:C0 = 11)

• Enable Configuration bit (high voltage,

HVC = V_IHH):

AD

C

n

Memory Address

Data Bits

Command Bits

Reserved

n

D

nn

- Enable Configuration bit (C1:C0 = 10)

- Disable Configuration bit (C1:C0 = 01)

X

The supported commands are shown in Table 7-1.

These commands allow for both single data or continu-

ous data operation. Table 7-2 also shows the required

number of bit clocks for each command’s different mode

of operation.

FIGURE 7-1:

8-Bit SPI Command Format.

7.1

Command Byte

The command byte has three fields: the address, the

command and one reserved bit (see Figure 7-1).

Commands may have two modes. These are:

The device memory is accessed when the master

sends a proper command byte to select the desired

operation. The memory location getting accessed is

contained in the command byte’s AD4:AD0 bits. The

action desired is contained in the command byte’s

C1:C0 bits; see Table 7-2. C1:C0 determines if the

desired memory location will be read, written, enabled

or disabled.

• Normal Serial Commands

• High-Voltage Serial Commands

Normal serial commands are those where the HVC pin

is driven to either V_IHor V_IL. With high-voltage serial

commands, the HVC pin is driven to V_IHH

.

TABLE 7-1:

COMMAND BITS OVERVIEW

C1:C0 Bit

States

Command # of Bits Normal or HV

As the command byte is being loaded into the device (on

the SDI pin), the device’s SDO pin is driving. The SDO pin

will output high bits for the first seven bits of that com-

mand. On the 8th bit, the SDO pin will output the

CMDERR bit state (see Section 7.6 “Error Condition”).

11

00

01

10

Read Data

24 Bits Normal

8 Bits HV Only

Write Data

Enable⁽¹⁾

Disable⁽¹⁾

7.2

Data Bytes

Note 1: High-voltage enable and disable com-

mands on selected nonvolatile memory

locations.

Data bytes are only present in the READ and WRITE

commands. These commands concatenate the two

data bytes, after the command byte, for a 24-bit long

command (see Figure 7-2).

The 8-bit commands (see Figure 7-1) are used to mod-

ify the device Configuration bits (Section 7.9 “Enable

Configuration Bit (High Voltage)” and Section 7.10

“Disable Configuration Bit (High Voltage)”) while

the 24-bit commands (see Figure 7-2) are used to read

and write to the device registers (Section 7.8 “READ

Command (Normal and High Voltage)” and

Section 7.7 “WRITE Command (Normal and High

Voltage)”). These commands contain a command byte

and two data bytes.

Command Byte

Data Word (2 bytes)

AD AD AD AD AD C

C

0

D

X

4

3

2

1

0

1

11 10 09 08 07 06 05 04 03 02 01 00

AD

n

C

n

D

nn

Legend:

Memory Address

Command Bits

Data Bits

X

Reserved

FIGURE 7-2:

24-Bit SPI Command Format.

 2020 Microchip Technology Inc.

DS20006362A-page 77

MCP48FXBX4/8

TABLE 7-2:

SPI COMMANDS – OVERVIEW AND COMMAND RATE

Estimated Peak

Command Rate

Command

Code

# of Bit

(Commands/ms)⁽⁵⁾

Comments

Clocks⁽²⁾

Operation

HV

Mode⁽¹⁾

1 MHz 10 MHz 20 MHz

C1 C0

WRITECommand

READCommand⁽⁴⁾

0 0

1 1

1 0

0 1

No⁽³⁾Single

No⁽³⁾Continuous

No⁽³⁾Single

24

24 * n

24

41

416

833

Read frequency can

be up to 10 MHz

No⁽³⁾Continuous

24 * n

8

Enable Configuration

Bit (High Voltage)

Yes Single

Yes Continuous

Yes Single

8 * n

8

125

1250

2500

Disable Configuration

Bit (High Voltage)

Yes Continuous

8 * n

Note 1: Nonvolatile registers can only use the Single mode.

2: “n” indicates the number of times the command operation is to be repeated.

3: If the state of the HVC pin is V_IHH, then the command is ignored, but a Command Error condition

(CMDERR) will NOT be generated.

4: This command is used to determine when an EEPROM programming cycle is complete.

5: The actual voltage output update rate depends on several factors, such as output settling time, code,

reference voltage or load impedance.

7.3

Continuous Commands

7.4

Commands to Modify the Device

Configuration Bits

The devices support the ability to execute commands

continuously. While the CS pin is in the Active state

(V_IL), any sequence of valid commands may be

received.

The MCP48FXBX4/8 devices support two commands,

which are used to program the device’s Configuration

bits. These commands require a High Voltage (V_IHH) on

the HVC pin. The commands are:

The following example is a valid sequence of events:

• Enable Configuration Bit (High Voltage)

• Disable Configuration Bit (High Voltage)

1. CS pin is driven active (V_IL).

2. READcommand.

3. WRITEcommand (volatile memory).

4. WRITEcommand (nonvolatile memory).

5. CS pin is driven inactive (V_IH).

The Configuration bits are used to inhibit the DAC

values from inadvertent modification. High voltage is

required to change the state of these bits if/when the

DAC values need to be modified.

Note 1: It is recommended that while the CS pin is

active, only one type of command should

be issued. When changing commands, it

is advisable to take the CS pin inactive,

then force it back to the Active state.

7.5

High-Voltage Command (HVC)

Signal

The High-Voltage Command (HVC) signal is used to

indicate that the command or sequence of commands

are in the High-Voltage mode. Signals higher than V_IHH

(~9.0V) on the LAT/HVC pin puts the device into High-

Voltage mode. High-voltage commands allow the

device’s WiperLock technology and write-protect

features to be enabled and disabled.

2: Long command strings should be broken

down into shorter command strings. This

reduces the probability of noise on the

SCK pin, corrupting the desired SPI

command string.

Note 1: There is a required delay after the HVC

pin is driven to the V_IHHlevel on the first

edge of the SCK pin.

DS20006362A-page 78

 2020 Microchip Technology Inc.

MCP48FXBX4/8

7.6

Error Condition

7.7

WRITE Command

(Normal and High Voltage)

The Command Error (CMDERR) bit indicates if the five

Address bits received (AD4:AD0) and the two Com-

mand bits received (C1:C0) are a valid combination (see

Figures 7-1 and 7-2). The CMDERR bit is high if the

combination is valid and low if the combination is invalid.

WRITE commands are used to transfer data to the

desired memory location (from the host controller). The

WRITEcommand can be issued to both the volatile and

nonvolatile memory locations.

The Command Error bit will also be low if a write to a

nonvolatile address has been specified and another

SPI command occurs before the CS pin is driven

inactive (V_IH).

WRITEcommands can be structured as either single or

continuous.

The format of the command is shown in Figure 7-3

(single) and Figure 7-6 (continuous).

SPI commands that do not have a multiple of eight

clocks are ignored.

A WRITE command to a volatile memory location

changes that location after a properly formatted WRITE

command has been received.

Once an error condition has occurred, any following

commands are ignored. All following SDO bits will be

low until the CMDERR condition is cleared by forcing

the CS pin to the Inactive state (V_IH).

A WRITE command to a nonvolatile memory location

starts an EEPROM write cycle only after a properly for-

matted WRITE command has been received and the

CS pin transitions to the Inactive state (V_IH).

7.6.1

ABORTING A TRANSMISSION

Note 1: Writes to certain memory locations

depend on the state of the WiperLock™

technology status bits.

All SPI transmissions must have the correct number of

SCK pulses to be executed. The command is not

executed until the complete number of clocks is

received. Some commands also require the CS pin to

be forced inactive (V_IH). If the CS pin is forced to the

Inactive state (V_IH), the serial interface is reset. Partial

commands are not executed.

2: During device communication, if an

unimplemented address is specified, then

the MCP48FXBX4/8 will generate

a

Command Error state. To reset the SPI

state machine, the CS pin must transition

to the Inactive state (V_IH).

SPI is more susceptible to noise than other bus

protocols. The most likely case is that noise corrupts

the value of the data being clocked into the

MCP48FXBX4/8 or the SCK pin is injected with extra

clock pulses. This may cause data to be corrupted in

the device, or a Command Error to occur, since the

address and command bits were not a valid combina-

tion. The extra SCK pulse will also cause the SPI data

(SDI) and clock (SCK) to be out of sync. Forcing the

CS pin to the Inactive state (V_IH) resets the serial inter-

7.7.1

SINGLE WRITE TO VOLATILE

MEMORY

The write operation requires that the CS pin be in the

Active state (V_IL). Typically, the CS pin will be in the

Inactive state (V_IH) and it is driven to the Active state

(V_IL). The 24-bit WRITEcommand (command byte and

data bytes) is then clocked in on the SCK and SDI pins.

Once all 24 bits have been received, the specified

volatile address is updated. A write will not occur if the

WRITE command is not exactly 24 clock pulses. This

protects against system issues corrupting the

nonvolatile memory locations.

face. The SPI interface will ignore activity on the SDI

and SCK pins until the CS pin transition to the Active

state is detected (V_IHto V_ILor V_IHto V_IHH).

Note 1: When the MCP48FXBX4/8 devices do not

receive data, it is recommended that the

CS pin be forced to the Inactive Level (V_IL).

Figures 7-4 and 7-5 show the waveforms for a single

write (depending on the SPI mode).

2: It is also recommended that long continu-

ous command strings be broken down

into single commands or shorter continu-

ous command strings. This reduces the

probability of noise on the SCK pin

corrupting the desired SPI commands.

 2020 Microchip Technology Inc.

DS20006362A-page 79

MCP48FXBX4/8

7.7.2

SINGLE WRITE TO NONVOLATILE

MEMORY

7.7.3

CONTINUOUS WRITES TO

VOLATILE MEMORY

The sequence to write to a single nonvolatile memory

location is the same as a single write to volatile memory,

with the exception that after the CS pin is driven inactive

(V_IH), the EEPROM Write Cycle (t_WC) is started. A write

cycle will not start if the WRITEcommand is not exactly

24 clock pulses. This protects against system issues

corrupting the nonvolatile memory locations.

AContinuous Write mode of operation is possible when

writing to the device’s volatile memory registers (see

Table 7-3). Figure 7-6 shows the sequence for three

continuous writes. The writes do not need to be to the

same volatile memory address.

TABLE 7-3:

VOLATILE MEMORY

ADDRESSES

Once a WRITE command to a nonvolatile memory

location has been received, no other SPI commands

should be received before the CS pin transitions to the

Inactive state (V_IH) or the current SPI command will

have a Command Error (CMDERR) occur.

Address

Quad-Channel

Octal-Channel

00h-03h

04h-07h

08h

Yes

No

Yes

After the CS pin is driven inactive (V_IH), the serial

interface may immediately be re-enabled by driving

the CS pin to the Active state (V_IL).

09h

0Ah

During an EEPROM write cycle, access to the volatile

memory is allowed when using the appropriate com-

mand sequence. Commands that address nonvolatile

memory are ignored until the EEPROM Write Cycle

(t_WC) completes. This allows the host controller to

operate on the volatile DAC registers.

7.7.4

CONTINUOUS WRITES TO

NONVOLATILE MEMORY

Continuous writes to nonvolatile memory are not

allowed and attempts to do so will result in a

Command Error (CMDERR) condition.

Note:

The EEWA status bit indicates if an

EEPROM write cycle is active (see

Register 4-4).

7.7.5

HIGH-VOLTAGE COMMAND (HVC)

SIGNAL

The High-Voltage Command (HVC) signal is used to

indicate that the command or sequence of commands

are in the high-voltage operational state. HVC

commands allow the device’s WiperLock technology

and write-protect features to be enabled and disabled.

Note:

Writes to a volatile DAC register will not

transfer to the output register until the LAT

(HVC) pin is transitioned from the V_IHHEN

voltage to a V_ILvoltage.

12-bit data

10-bit data

8-bit data

AD AD AD AD AD C

C

0

D

X

4

3

2

1

0

1

11 10 09 08 07 06 05 04 03 02 01 00

SDI

*

0

X

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽²⁾

Invalid⁽³⁾

SDO

Note 1: For WRITEcommands addressing the DAC Wiper registers, the data bits depend on the resolution of the

device: 12-bit = D11:D00, 10-bit = D09:D00 and 8-bit = D07:D00. Data are right justified for easy host

controller operation (no data manipulation before transmitting the desired value). The unimplemented bits

are ignored.

2: After a valid memory address and WRITEcommand byte are received (CMDERR = 1), all the following

SDO bits will be output as ‘1’.

3: If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the

CMDERR condition is cleared (the CS pin is forced to the Inactive state).

FIGURE 7-3:

Write Single Memory Location Command – SDI and SDO States.⁽¹⁾

DS20006362A-page 80

 2020 Microchip Technology Inc.

MCP48FXBX4/8

V_IHH

HVC⁽¹⁾

CS

Note: HVC must be at V_IHHbefore the start of a WRITEcommand and only lowered to V_IHor V_ILafter the last bit of the 24-bit command.

V_IH

V_IL

SCK

SDI

00

01

02

03

04

05

06

07

08

09

20

21

22

23

AD4

AD3 AD2 AD1 AD0

C1

C0

X

D15

D14

D03

D02

D01

D00

SDO

Input

CMDERR

Sample

Note 1: If the state of the HVC pin is V_IHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.

FIGURE 7-4:

24-Bit WRITE Command (C1:C0 = 00) – SPI Waveform (Mode 1,1).

V_IHH

HVC⁽¹⁾

Note: HVC must be at V_IHHbefore the start of a WRITEcommand and only lowered to V_IHor V_ILafter the last bit of the 24-bit command.

V_IH

V_IL

CS

SCK

00

01

02

03

04

05

06

07

08

09

19

20

21

22

23

AD4 AD3 AD2 AD1 AD0

C1

C0

X

D15

D14

D03

D02

D01

D00

SDI

SDO

Input

CMDERR

Sample

Note 1: If the state of the HVC pin is V_IHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.

FIGURE 7-5:

24-Bit WRITE Command (C1:C0 = 00) – SPI Waveform (Mode 0,0).

 2020 Microchip Technology Inc.

DS20006362A-page 81

MCP48FXBX4/8

12-bit data

10-bit data

8-bit data

AD AD AD AD AD C

C

0

D

X

4

3

2

1

0

1

11 10 09 08 07 06 05 04 03 02 01 00

SDI

(1)

*

0

X

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽²⁾

Invalid⁽³⁾

SDO

AD AD AD AD AD C

C

0

D

X

*

X

4

3

2

1

0

1

0

1

0

11 10 09 08 07 06 05 04 03 02 01 00

SDI

(1)

*

0

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

1

(3)

1

0

1

0

1

0

1

0

1

(4)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽²⁾

Invalid⁽³⁾

SDO

AD AD AD AD AD C

C

0

D

X

*

X

4

3

2

1

0

1

0

1

0

11 10 09 08 07 06 05 04 03 02 01 00

SDI

(1)

*

0

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

1

(3)

1

0

1

0

1

0

1

0

1

(4)

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽²⁾

Invalid⁽³⁾

SDO

Note 1: For WRITEcommands addressing the DAC Wiper registers, the data bits depend on the resolution of the

device: 12-bit = D11:D00, 10-bit = D09:D00, and 8-bit = D07:D00. Data are right justified for easy host

controller operation (no data manipulation before transmitting the desired value). The unimplemented

bits are ignored.

2: After a valid memory address and WRITEcommand byte are received (CMDERR = 1), all the following

SDO bits will be output as ‘1’.

3: If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the

CMDERR condition is cleared (the CS pin is forced to the Inactive state).

4: This CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This

command will not be completed and requires the CS pin to return to V_IHto clear the CMDERR

condition.

FIGURE 7-6:

Continuous WRITE Commands (Volatile Memory Only).

DS20006362A-page 82

 2020 Microchip Technology Inc.

MCP48FXBX4/8

The READcommand formats include:

7.8

READ Command

(Normal and High Voltage)

• Single Read

• Continuous Reads

The READcommand is a 24-bit command and is used

to transfer data from the specified memory location to

the host controller. The READcommand can be issued

to both the volatile and nonvolatile memory locations.

The format of the command, as well as an example of

SDI and SDO data, are shown in Figure 7-7.

7.8.1

LAT PIN INTERACTION

During a READcommand of the DACn registers, if the

LAT pin transitions from V_IHto V_IL, then the read data

may be corrupted. This is due to the fact that the data

being read are the output value and not the DAC

register value. The LAT pin transition causes an update

of the output value. Based on the DAC output value,

the DACn register value and the Command bit where

the LAT pin transitions, the value being read could be

corrupted.

The first seven bits of the READ command determine

the address and the command. The 8th clock will out-

put the CMDERR bit on the SDO pin. By means of the

remaining 16 clocks, the device will transmit the data

bits of the specified address (AD4:AD0).

During an EEPROM write cycle (write to nonvolatile

memory location or enable/disable Configuration bit

command), the READ command can only read the

volatile memory locations. By reading the Status

register (0Ah), the host controller can determine when

the write cycle has been completed (via the state of the

EEWA bit).

If LAT pin transitions occur during a read of the DACn

register, it is recommended that sequential reads be

performed until the two most recent read values match.

Then the most recent read data are good.

7.8.2

SINGLE READ

The READ command operation requires that the

CS pin be in the Active state (V_IL). Typically, the CS

pin will be in the Inactive state (V_IH) and is driven to

the Active state (V_IL). The 24-bit READ command

(command byte and data byte) is then clocked in on

the SCK and SDI pins. The SDO pin starts driving data

on the 8th bit (CMDERR bit) and the addressed data

come out on the 9th through 24th clocks.

Note 1: During device communication, if an unim-

plemented address is specified, then the

MCP48FXBX4/8 will command error that

byte. To reset the SPI state machine, the

CS pin must be driven to the V_IHstate.

2: If the LAT pin is high (V_IH), reads of the

volatile DAC register read the output

value, not the internal register.

3: The READ commands operate the same

regardless of the state of the High-Voltage

Command (HVC) signal.

12-bit data

10-bit data

8-bit data

AD AD AD AD AD C

C

0

D

X

4

3

2

1

0

1

11 10 09 08 07 06 05 04 03 02 01 00

SDI

*

1

X

*

d

0

*

d

0

*

d

0

*

d

0

*

d

0

*

d

0

X

1

0

d

0

d

0

d

0

d

0

d

0

d

0

Valid⁽¹⁾

Invalid⁽²⁾

SDO

Note 1: The Data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and

8-bit = D07:D00. The unimplemented bits are output as ‘0’ and data are right justified for easy host

controller operation (no data manipulation after reading the register value).

2: If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the

CMDERR condition is cleared (the CS pin is forced to the Inactive state).

FIGURE 7-7:

READ Command – SDI and SDO States.

 2020 Microchip Technology Inc.

DS20006362A-page 83

MCP48FXBX4/8

Figure 7-8 shows the sequence for three continuous

reads. The reads do not need to be to the same

memory address.

7.8.3

CONTINUOUS READS

Continuous reads format allows the device’s memory

to be read quickly. Continuous reads are possible to all

memory locations. If a nonvolatile memory write cycle

is occurring, then READ commands may only access

the volatile memory locations.

This is useful in reading the System Status register

(0Ah) to determine if an EEPROM write cycle is

complete (EEWA bit).

12-bit data

10-bit data

8-bit data

AD AD AD AD AD C

C

0

D

X

4

3

2

1

0

1

11 10 09 08 07 06 05 04 03 02 01 00

SDI

*

0

X

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽¹⁾

Invalid⁽²⁾

SDO

AD AD AD AD AD C

C

0

D

X

*

X

4

3

2

1

0

1

0

1

0

11 10 09 08 07 06 05 04 03 02 01 00

SDI

*

0

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

(3)

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽¹⁾

Invalid⁽²⁾

SDO

AD AD AD AD AD C

C

0

D

X

*

X

4

3

2

1

0

1

0

1

0

11 10 09 08 07 06 05 04 03 02 01 00

SDI

*

0

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

*

1

0

1

0

1

0

1

0

1

0

1

0

1

(3)

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽¹⁾

Invalid⁽²⁾

SDO

Note 1: The data bits depend on the resolution of the device: 12-bit = D11:D00, 10-bit = D09:D00, and

8-bit = D07:D00. The unimplemented bits are output as ‘0’ and data are right justified for easy host

controller operation (no data manipulation after reading the register value).

2: If an error condition occurs (CMDERR = 0), all the following SDO bits will be output as ‘0’ until the

CMDERR condition is cleared (the CS pin is forced to the Inactive state).

3: The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This

command will not be completed and requires the CS pin to return to V_IHto clear the CMDERR

condition.

FIGURE 7-8:

READ Command – Continuous Read Sequence.

DS20006362A-page 84

 2020 Microchip Technology Inc.

MCP48FXBX4/8

V_IHH

HVC⁽¹⁾

CS

Note: HVC must be at V_IHHbefore the start of a WRITEcommand and only lowered to V_IHor V_ILafter the last bit of the 24-bit command.

V_IH

V_IL

SCK

SDI

00

01

02

03

04

05

06

07

08

09

20

21

22

23

D03

D02

D01

D00

AD4 AD3 AD2 AD1 AD0

C1

C0

X

D15

D14

SDO

Input

CMDERR

Sample

Note 1: If the state of the HVC pin is V_IHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.

FIGURE 7-9:

24-Bit READ Command (C1:C0 = 11) – SPI Waveforms (Mode 1,1).

V_IHH

HVC⁽¹⁾

Note: HVC must be at V_IHHbefore start of a WRITEcommand and only lowered to V_IHor V_ILafter the last bit of the 24-bit command.

V_IH

V_IL

CS

SCK

SDI

00

01

02

03

04

05

06

07

08

09

19

20

21

22

23

X

AD4

AD3

AD2

AD1

AD0

C1

C0

D15

D14

D03

D02

D01

D00

SDO

Input

CMDERR

Sample

Note 1: If the state of the HVC pin is V_IHH, then the command is ignored, but a Command Error condition (CMDERR) will NOT be generated.

FIGURE 7-10:

24-Bit READ Command (C1:C0 = 11) – SPI Waveforms (Mode 0,0).

 2020 Microchip Technology Inc.

DS20006362A-page 85

MCP48FXBX4/8

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial com-

7.9

Enable Configuration Bit

(High Voltage)

mands are ignored until the EEPROM Write Cycle (t_WC

)

Figure 7-11 shows the formats for a single enable

Configuration bit command. The command will only

start the EEPROM Write Cycle (t_WC) after a properly

formatted command has been received.

completes. This allows the host controller to operate on

the volatile DAC, the volatile V_REF, Power-Down, Gain

and Status, and WiperLock Technology Status registers.

The EEWA bit in the Status register indicates the status

of the EEPROM write cycle.

AD AD AD AD AD C

C

0

AD AD AD AD AD C

C

0

AD AD AD AD AD C

C

0

X

4

3

2

1

0

1

4

3

2

1

0

1

0

4

3

2

1

0

1

0

SDI

*

1

0

X

*

0

1

0

*

1

0

*

0

1

0

*

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽¹⁾

Invalid⁽²⁾

SDO

Note 1: If an error condition occurs (CMDERR = 0), all the following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the Inactive state).

2: The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This

command will not be completed and requires the CS pin to return to V_IHto clear the CMDERR

condition.

FIGURE 7-11:

Enable Command Sequence.

V_IHH

V_IH

HVC

CS

V_IL

SCK

SDI

00

01

02

03

04

05

06

07

AD4 AD3 AD2 AD1

AD0

C1

C0

X

SDO

Input

CMDERR

Sample

FIGURE 7-12:

8-Bit Enable Command (C1:C0 = 10) – SPI Waveforms (Mode 1,1).

DS20006362A-page 86

 2020 Microchip Technology Inc.

MCP48FXBX4/8

V_IHH

V_IH

HVC

CS

V_IL

SCK

SDI

00

01

02

03

04

05

06

07

AD4 AD3 AD2

AD1

AD0

C1

C0

X

SDO

CMDERR

Input

Sample

FIGURE 7-13:

8-Bit Enable Command (C1:C0 = 10) – SPI Waveforms (Mode 0,0).

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial

commands are ignored until the EEPROM Write Cycle

(t_WC) completes. This allows the host controller to oper-

ate on the volatile DAC, the volatile V_REF, Power-Down,

Gain and Status, and WiperLock Technology Status

registers. The EEWA bit in the Status register indicates

the status of an EEPROM write cycle.

7.10 Disable Configuration Bit

(High Voltage)

Figure 7-14 shows the formats for a single disable

Configuration bit command. The command will only

start an EEPROM Write Cycle (t_WC) after a properly

formatted command has been received.

AD AD AD AD AD C

C

0

AD AD AD AD AD C

C

0

AD AD AD AD AD C

C

0

X

4

3

2

1

0

1

4

3

2

1

0

1

0

1

0

4

3

2

1

0

1

0

1

0

SDI

*

0

1

X

*

1

0

*

1

0

*

1

0

*

1

0

X

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Valid⁽¹⁾

Invalid⁽²⁾

SDO

Note 1: If an error condition occurs (CMDERR = 0), all the following SDO bits will be low until the CMDERR

condition is cleared (the CS pin is forced to the Inactive state).

2: The CMDERR bit will be forced to ‘0’, regardless if this Address+Command combination is valid. This

command will not be completed and requires the CS pin to return to V_IHto clear the CMDERR

condition.

FIGURE 7-14:

Disable Command Sequence.

 2020 Microchip Technology Inc.

DS20006362A-page 87

MCP48FXBX4/8

V_IHH

V_IH

HVC

CS

V_IL

SCK

SDI

00

01

02

03

04

05

06

07

AD4 AD3 AD2 AD1

AD0

C1

C0

X

SDO

CMDERR

Input

Sample

FIGURE 7-15:

8-Bit Disable Command (C1:C0 = 01) – SPI Waveforms (Mode 1,1).

V_IHH

V_IH

HVC

CS

V_IL

SCK

SDI

00

01

02

03

04

05

06

07

AD4 AD3 AD2 AD1

AD0

C1

C0

X

SDO

CMDERR

Input

Sample

FIGURE 7-16:

8-Bit Disable Command (C1:C0 = 01) – SPI Waveforms (Mode 0,0).

DS20006362A-page 88

 2020 Microchip Technology Inc.

MCP48FXBX4/8

8.0

APPLICATIONS INFORMATION

V

DD

The MCP48FXBX4/8 devices are general purpose,

quad/octal-channel voltage output DACs for various

V_DD

applications, where

low-power and nonvolatile EEPROM memory is

needed.

a

precision operation with

SDI

SDO

SCK

CS

C₁

C₂

V_REF

V_OUT0

To MCU

Since the devices include a nonvolatile EEPROM

memory, the user can utilize these devices for

applications that require the output to return to the

previous setup value on subsequent power-ups.

Analog

Output

LAT/HVC

V_SS

V_OUTN

8.1

Power Supply Considerations

C₃

Optional

C_N

The power source should be as clean as possible. The

power supply to the device is also used for the DAC

voltage reference internally if the internal V_DDis

selected as the resistor ladder’s reference voltage

(VRnB:VRnA = 00).

(a) Circuit when V is selected as reference.

DD

Note:

V

is connected to the reference circuit internally.

DD

Any noise induced on the V_DDline can affect the DAC

performance. Typical applications will require a bypass

capacitor in order to filter out high-frequency noise on

the V_DDline. The noise can be induced onto the power

supply’s traces or as a result of changes on the DAC out-

put. The bypass capacitor helps to minimize the effect of

these noise sources on signal integrity. Figure 8-1

shows an example of using two bypass capacitors (a

10 µF tantalum capacitor and a 0.1 µF ceramic capaci-

tor) in parallel on the V_DDline. These capacitors should

be placed as close to the V_DDpin as possible (within

4 mm). If the application circuit has separate digital and

analog power supplies, the V_DDand V_SSpins of the

device should reside on the analog plane.

V

DD

C₁

C₂

Analog

V_REF

SDI

V_DD

SDO

V_REF

To MCU

SCK

CS

V_OUT0

LAT/HVC

V_SS

Analog

Output

V_OUTN

When setting the part voltage reference to Band Gap

mode, the use of the V_REFpin decoupling capacitors is

not recommended.

C₃

C_N

Optional

(b) Circuit when external reference is used.

C : 0.1 µF capacitor

Ceramic

Tantalum

=

1

C : 10 µF capacitor

2

C : ~0.1 µF

Optional to reduce noise

in V pin

3

OUT

C : 0.1 µF capacitor

Ceramic

=

4

C : 10 µF capacitor

Tantalum

Ceramic

5

C : 0.1 µF capacitor

6

FIGURE 8-1:

Example Circuit.

 2020 Microchip Technology Inc.

DS20006362A-page 89

MCP48FXBX4/8

8.2.0.2

PCB Area Requirements

8.2

Layout Considerations

In some applications, PCB area is a criteria for device

selection. Table 8-1 shows the typical package

dimensions and area for the different package options.

Several layout considerations may be applicable to

your application. These may include:

• Noise

)

TABLE 8-1:

Package

PACKAGE FOOTPRINT⁽¹

• PCB Area Requirements

Package Footprint

8.2.0.1

Noise

Dimensions

(mm)

Particularly harsh environments may require shielding

of critical signals. Inductively coupled AC transients

and digital switching noise can degrade the input and

output signal integrity, potentially masking the

MCP48FXBX4/8 devices’ performance. Careful board

layout minimizes these effects and increases the

Signal-to-Noise Ratio (SNR).

Type

Code

Area (mm²)

Length Width

20 TSSOP

20 VQFN

ST

3.00

5

4.90

5

14.70

25

MQ

Note 1: Does not include recommended land

pattern dimensions. Dimensions are

typical values.

Multilayer boards utilizing a low-inductance ground

plane, isolated inputs, isolated outputs and proper

decoupling are critical to achieving the performance

that the silicon is capable of providing.

Separate digital and analog ground planes are

recommended. In this case, the V_SSpin and the ground

pins of the V_DDcapacitors should be terminated to the

analog ground plane.

Note:

Breadboards and wire-wrapped boards

are not recommended.

DS20006362A-page 90

 2020 Microchip Technology Inc.

MCP48FXBX4/8

Figure 9-1 shows how the TSSOP20EV bond-out PCB

can be populated to easily evaluate the

MCP48FXBX4/8 devices. The PICkit™ Serial Analyzer

can be used to control the DAC Output registers and

state of the Configuration, Control and Status register.

9.0

DEVELOPMENT SUPPORT

Development support can be classified into two groups.

These are:

• Development Tools

• Technical Documentation

The TSSOP20EV boards may be purchased directly

from the Microchip website at www.microchip.com.

9.1

Development Tools

9.2

Technical Documentation

Several development tools are available to assist in

your design and evaluation of the MCP48FXBX4/8

devices. The currently available tools are shown in

Table 9-1.

Several additional technical documents are available to

assist you in your design and development. These

technical documents include Application Notes,

Technical Briefs and Design Guides. Table 9-2 lists

some of these documents.

TABLE 9-1:

DEVELOPMENT TOOLS⁽¹⁾

Board Name

Part #

Comment

20-Pin TSSOP and SSOP Evaluation Board TSSOP20EV Most Flexible Option – Recommended Bond-out PCB

Note 1: Supports the PICkit™ Serial Analyzer. See the User’s Guide for additional information and requirements.

TABLE 9-2:

TECHNICAL DOCUMENTATION

Application

Note Number

Title

Literature #

AN1326

Using the MCP4828 12-Bit DAC for LDMOS Amplifier Bias Control Applications

Signal Chain Design Guide

DS01326

DS21825

DS01005

—

Analog Solutions for Automotive Applications Design Guide

 2020 Microchip Technology Inc.

DS20006362A-page 91

MCP48FXBX4/8

MCP48FXBX8-20E/ST

Installed in U3 Footprint

Connected to

Digital Ground

(DGND) Plane

Connected to

Digital Power (V_L) Plane

LAT1

LAT0/HVC

1.0 µF

4.7k 

0 

V

SDI

DD

10k



SCK

CS

REF0

OUT0

V

SDO

V

REF1

OUT7

V

OUT2

V

OUT4

OUT6

OUT5

OUT3

V

SS

OUT1

0 

Two-Wire Jumpers to Connect the

PICkit™ Serial Analyzer (SPI) to Device Pins

1x6 Male Header with 90° Right Angle

FIGURE 9-1:

MCP48FXBX4/8 Evaluation Board Circuit Using TSSOP20EV.

DS20006362A-page 92

 2020 Microchip Technology Inc.

MCP48FXBX4/8

10.0 PACKAGING INFORMATION

10.1 Package Marking Information

20-Lead 5 x 5 mm VQFN

Example

MCP48FE

B04

-E/MQ

2010256

20-Lead TSSOP

Example

XXXXXXXX

XXXXXNNN

YYWW

MCP48FVB

0420E256

2010

Legend: XX...X Customer-specific information

Y

Year code (last digit of calendar year)

YY

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Pb-free JEDEC designator for Matte Tin (Sn)

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

e

3

e

3

*

)

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

 2020 Microchip Technology Inc.

DS20006362A-page 93

MCP48FXBX4/8

20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

D

A

B

E

N

NOTE 1

1

2

(DATUM B)

(DATUM A)

2X

0.20 C

2X

TOP VIEW

0.20 C

0.10 C

A1

C

A

SEATING

PLANE

20X

(A3)

0.08 C

C A B

SIDE VIEW

0.10

D2

0.10

C A B

E2

2

1

NOTE 1

K

N

L

20X b

0.10

0.05

C A B

C

e

BOTTOM VIEW

Microchip Technology Drawing C04-139C (MQ) Sheet 1 of 2

DS20006362A-page 94

 2020 Microchip Technology Inc.

MCP48FXBX4/8

20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

Units

Dimension Limits

MILLIMETERS

NOM

MIN

MAX

Number of Terminals

Pitch

Overall Height

N

20

0.65 BSC

0.90

0.02

0.20 REF

5.00 BSC

3.25

5.00 BSC

3.25

0.30

0.40

e

A

A1

(A3)

D

D2

E

E2

b

0.80

0.00

1.00

0.05

Standoff

Contact Thickness

Overall Length

Exposed Pad Length

Overall Width

Exposed Pad Width

Contact Width

3.15

3.35

3.15

0.25

0.35

0.20

3.35

0.35

0.45

-

Contact Length

Contact-to-Exposed Pad

L

K

-

Notes:

1. Pin 1 visual index feature may vary, but must be located within the hatched area.

2. Package is saw singulated

3. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

REF: Reference Dimension, usually without tolerance, for information purposes only.

Microchip Technology Drawing C04-139C (MQ) Sheet 2 of 2

 2020 Microchip Technology Inc.

DS20006362A-page 95

MCP48FXBX4/8

20-Lead Plastic Quad Flat, No Lead Package (MQ) – 5x5x1.0 mm Body [VQFN]

With 0.40 mm Contact Length

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

C1

X2

EV

20

1

ØV

2

G

Y2

C2

EV

Y1

E

X1

SILK SCREEN

RECOMMENDED LAND PATTERN

Units

Dimension Limits

E

MILLIMETERS

NOM

0.65 BSC

MIN

MAX

Contact Pitch

Optional Center Pad Width

Optional Center Pad Length

Contact Pad Spacing

W2

T2

C1

C2

X1

Y1

G

3.35

4.50

Contact Pad Spacing

Contact Pad Width (X20)

Contact Pad Length (X20)

Distance Between Pads

Thermal Via Diameter

Thermal Via Pitch

0.40

0.55

0.20

V

EV

0.30

1.00

Notes:

1. Dimensioning and tolerancing per ASME Y14.5M

BSC: Basic Dimension. Theoretically exact value shown without tolerances.

2. For best soldering results, thermal vias, if used, should be filled or tented to avoid solder loss during

reflow process

Microchip Technology Drawing C04-2139B (MQ)

DS20006362A-page 96

 2020 Microchip Technology Inc.

MCP48FXBX4/8

 2020 Microchip Technology Inc.

DS20006362A-page 97

MCP48FXBX4/8

DS20006362A-page 98

 2020 Microchip Technology Inc.

MCP48FXBX4/8

Note: For the most current package drawings, please see the Microchip Packaging Specification located at

http://www.microchip.com/packaging

 2020 Microchip Technology Inc.

DS20006362A-page 99

MCP48FXBX4/8

NOTES:

DS20006362A-page 100

 2020 Microchip Technology Inc.

MCP48FXBX4/8

APPENDIX A: REVISION HISTORY

Revision A (May 2020)

• Original release of this document.

 2020 Microchip Technology Inc.

DS20006362A-page 101

MCP48FXBX4/8

NOTES:

DS20006362A-page 102

 2020 Microchip Technology Inc.

MCP48FXBX4/8

B.3

Monotonic Operation

APPENDIX B: TERMINOLOGY

Monotonic operation means that the device’s output

voltage (V_OUT) increases with every 1 code step (LSb)

increment (from V_SSto the DAC’s reference voltage

(V_DDor V_REF)).

B.1

Resolution

The resolution is the number of DAC output states that

divide the full-scale range. For the 12-bit DAC, the

resolution is 2¹², meaning the DAC code ranges from

0 to 4095.

V_S64

40h

3Fh

Note:

When there are 2^Nresistors in the resistor

ladder and 2^Ntap points, the full-scale

DAC register code is the resistor element

(1 LSb) from the source reference voltage

(V_DDor V_REF).

V_S63

3Eh

V_S3

03h

02h

B.2

Least Significant Bit (LSb)

V_S1

This is the voltage difference between two successive

codes. For a given output voltage range, it is divided by

the resolution of the device (Equation B-1). The range

may be V_DD(or V_REF) to V_SS(ideal); the DAC register

codes across the linear range of the output driver

(Measured 1), or full scale to zero scale (Measured 2).

V_S0

01h

00h

V_W(@ tap)

n = ?

V_W

=

V_Sn+ V_{ZS(@ Tap 0)}

n = 0

EQUATION B-1:

Ideal

LSb VOLTAGE

CALCULATION

Voltage (V_W V_OUT

)

FIGURE B-1:

V_W(V_OUT).

V

DD

REF

---------------

N

or

V

= ------------

LSb(IDEAL)

N

2

Measured 1

V

– V

OUT(@4000)

OUT(@100)

V

= -----------------------------------------------------------------------------

LSb(Measured)

4000 – 100

Measured 2

V

– V

OUT(@FS)

OUT(@ZS)

V

= ---------------------------------------------------------------------

LSb

N

2

– 1

2^N= 4096 (MCP48FXB2X)

= 1024 (MCP48FXB1X)

= 256 (MCP48FXB0X)

 2020 Microchip Technology Inc.

DS20006362A-page 103

MCP48FXBX4/8

B.4

Full-Scale Error (E )

B.6

Total Unadjusted Error (E )

T

FS

The Full-Scale Error (see Figure B-3) is the error on

the V_OUTpin relative to the expected V_OUTvoltage

(theoretical) for the maximum device DAC register

code (code FFFh for 12-bit, code 3FFh for 10-bit and

code FFh for 8-bit); see Equation B-2. The error

depends on the resistive load on the V_OUTpin (and

where that load is tied to, such as V_SSor V_DD). For

loads (to V_SS) greater than specified, the Full-Scale

Error will be greater.

The Total Unadjusted Error (E_T) is the difference

between the ideal and the measured V_OUTvoltage.

Typically, calibration of the output voltage is

implemented to improve system performance.

The error in bits is determined by the theoretical

voltage step-size to give an error in LSb.

Equation B-4 shows the Total Unadjusted Error

calculation.

The error in bits is determined by the theoretical volt-

age step-size to give an error in LSb.

EQUATION B-4:

TOTAL UNADJUSTED

ERROR CALCULATION

EQUATION B-2:

FULL-SCALE ERROR

V

– V



OUT_Actual(@Code)

OUT_Ideal(@Code)

E

= ------------------------------------------------------------------------------------------------------------------------

V

– V

T

V

OUT(@FS)

IDEAL(@FS)

LSb(Ideal)

E

= --------------------------------------------------------------------------

FS

V

LSb(IDEAL)

Where:

E_Tis expressed in LSb.

E_FSis expressed in LSb.

V_{OUT_Actual(@Code)}= The measured DAC output

voltage at the specified code.

V_OUT(@FS)= The V_OUTvoltage when the DAC

register code is at full scale.

V_{OUT_Ideal(@Code)}= The calculated DAC output

voltage at the specified code.

V_IDEAL(@FS)= The ideal output voltage when the

DAC register code is at full scale.

(code × V_LSb(Ideal)).

V_LSb(IDEAL)= The theoretical voltage step size.

V_LSb(Ideal)= V_REF/# Steps

12-bit = V_REF/4096

10-bit = V_REF/1024

8-bit = V_REF/256

B.5

Zero-Scale Error (E )

ZS

The Zero-Scale Error (see Figure B-2) is the difference

between the ideal and the measured V_OUTvoltage with

the DAC register code equal to 000h (Equation B-3).

The error depends on the resistive load on the V_OUTpin

(and where that load is tied to, such as V_SSor V_DD). For

loads (to V_DD) greater than specified, the Zero-Scale

Error will be greater.

The error in bits is determined by the theoretical

voltage step-size to give an error in LSb.

EQUATION B-3:

ZERO-SCALE ERROR

V

OUT(@ZS)

E

= ---------------------------------

ZS

V

LSb(IDEAL)

Where:

_ZSis expressed in LSb.

E

V_OUT(@ZS)= The V_OUTvoltage when the DAC

register code is at zero scale.

V_LSb(IDEAL)= The theoretical voltage step-size.

DS20006362A-page 104

 2020 Microchip Technology Inc.

MCP48FXBX4/8

Gain Error indicates how well the slope of the actual

transfer function matches the slope of the ideal transfer

function. Gain Error is usually expressed as a percent

of full-scale range (% of FSR) or in LSb. FSR is the

ideal full-scale voltage of the DAC (see Equation B-5).

B.7

Offset Error (E

)

OS

The Offset Error is the delta voltage of the V_OUTvoltage

from the ideal output voltage at the specified code. This

code is specified where the output amplifier is in the

linear operating range; for the MCP48FXBX4/8, we

specify code 100 (decimal). Offset error does not

include Gain Error, see Figure B-2.

Gain Error (E )

G

(@ Code = 4000)

This error is expressed in mV. Offset Error can be

negative or positive. The Offset Error can be calibrated

by software in application circuits.

V

REF

Actual

Transfer

Function

Full-Scale

Error (E

)

FS

Ideal Transfer

Function Shifted by

Offset Error

(crosses at start of

defined linear range)

Actual

Transfer

Function

Ideal Transfer

Function

0

100

4000 4095

DAC Input Code

FIGURE B-3:

Error Example.

Gain Error and Full-Scale

Zero-Scale

Ideal Transfer

Function

Error (E

)

ZS

0

100

DAC Input Code

4000

EQUATION B-5:

EXAMPLE GAIN ERROR

Offset

Error (E

)

V

– V



OS

OUT(@4000)

OS

OUT_Ideal(@4000)

E

= ----------------------------------------------------------------------------------------------------------------------  1 0 0

G

V

Full-Scale Range

FIGURE B-2:

Offset Error and Zero-Scale

Error.

Where:

E_Gis expressed in % of FSR.

B.8

Offset Error Drift (E

)

OSD

V_OUT(@4000)= The measured DAC output

voltage at the specified code.

The Offset Error Drift is the variation in Offset Error due

to a change in ambient temperature. The Offset Error

Drift is typically expressed in ppm/°C or µV/°C.

V_{OUT_Ideal(@4000)}= The calculated DAC output

voltage at the specified code

(4000 * V_LSb(Ideal)).

B.9

Gain Error (E )

G

V_OS= Measured offset voltage.

Gain Error is a calculation based on the ideal slope

using the voltage boundaries for the linear range of the

output driver (ex.: code 100 and code 4000); see

Figure B-3. The Gain Error calculation nullifies the

device’s Offset Error.

V_{Full-Scale Range}= Expected full-scale output

value (such as the V_REF

voltage).

B.10 Gain Error Drift (E

)

GD

The Gain Error Drift is the variation in Gain Error due to

a change in ambient temperature. Gain Error Drift is

typically expressed in ppm/°C (of FSR).

 2020 Microchip Technology Inc.

DS20006362A-page 105

MCP48FXBX4/8

B.11 Integral Nonlinearity (INL)

B.12 Differential Nonlinearity (DNL)

The Integral Nonlinearity (INL) error is the maximum

deviation of an actual transfer function from an ideal

transfer function (straight line) passing through the

defined end points of the DAC transfer function (after

offset and gain errors have been removed).

The Differential Nonlinearity (DNL) error (see

Figure B-5) is the measure of step-size between codes

in an actual transfer function. The ideal step-size

between codes is 1 LSb. A DNL error of zero would

imply that every code is exactly 1 LSb wide. If the DNL

error is less than 1 LSb, the DAC ensures monotonic

output and no missing codes. Equation B-7 shows how

to calculate the DNL error between any two adjacent

codes in LSb.

In the MCP48FXBX4/8, INL is calculated using the

defined end points, DAC code 100 and code 4000. INL

can be expressed as a percentage of FSR or in LSb.

INL is also called ‘Relative Accuracy’. Equation B-6

shows how to calculate the INL error in LSb and

Figure B-4 shows an example of INL accuracy.

EQUATION B-7:

DNL ERROR

V

– V



Positive INL means higher V_OUTvoltage than the ideal

one. Negative INL means lower V_OUTvoltage than the

ideal one.

OUT(code = n+1)

OUT(code = n)

E

= ---------------------------------------------------------------------------------------------------- – 1

DNL

V

LSb(Measured)

Where:

EQUATION B-6:

INL ERROR

– V

DNL is expressed in LSb.

V



OUT

Calc_Ideal

E

= ---------------------------------------------------------

V_{OUT(code = n)}= The measured DAC output voltage

with a given DAC register code.

INL

V

LSb(Measured)

V_{LSb(Measured)}= For Measured:

(V_OUT(4000)– V_OUT(100))/3900.

Where:

INL is expressed in LSb.

V_{Calc_Ideal}= Code × V_{LSb(Measured)}+ V_OS

V_{OUT(Code = n)}= The measured DAC output

voltage with a given DAC

register code.

7

DNL = 0.5 LSb

V_{LSb(Measured)}= For Measured:

(V_OUT(4000)– V_OUT(100))/3900.

6

5

V_OS= Measured offset voltage.

DNL = 2 LSb

Analog

Output

4

(LSb)

3

7

2

1

INL = < -1 LSb

6

INL = -1 LSb

5

0

Analog

4

000 001 010 011 100 101 110 111

Output

DAC Input Code

INL = 0.5 LSb

(LSb)

3

2

Ideal Transfer Function

Actual Transfer Function

1

0

FIGURE B-5:

DNL Accuracy.

000 001 010 011 100 101 110 111

DAC Input Code

Ideal Transfer Function

Actual Transfer Function

FIGURE B-4:

INL Accuracy.

DS20006362A-page 106

 2020 Microchip Technology Inc.

MCP48FXBX4/8

B.13 Settling Time

B.17 Power Supply Sensitivity (PSS)

The settling time is the time delay required for the V_OUT

voltage to settle into its new output value. This time is

measured from the start of code transition to when the

PSS indicates how the output of the DAC is affected by

changes in the supply voltage. PSS is the ratio of the

change in V_OUTto a change in V_DDfor midscale output

of the DAC. The V_OUTis measured while the V_DDis

varied from 5.5V to 2.7V as a step (V_REFvoltage held

constant) and is expressed in %/%, which is the %

change of the DAC output voltage with respect to the %

change of the V_DDvoltage.

V_OUTvoltage is within the specified accuracy.

For the MCP48FXBX4/8, the settling time is a

measurement of the time delay until the V_OUTvoltage

reaches within 0.5 LSb of its final value, when the vol-

atile DAC register changes from 1/4 to 3/4 of the FSR

(12-bit device: 400h to C00h).

EQUATION B-8:

PSS CALCULATION

B.14 Major Code Transition Glitch

V

– V

  V

OUT(@5.5V)

OUT(@2.7V)

OUT(@5.5V)

PSS = ----------------------------------------------------------------------------------------------------------------------------

Major code transition glitch is the impulse energy

injected into the DAC analog output when the code in

the DAC register changes the state. It is normally

specified as the area of the glitch in nV-Sec and is

measured when the digital code is changed by 1 LSb at

the major carry transition.

5.5V – 2.7V  5.5V

Where:

PSS is expressed in %/%.

V_OUT(@5.5V)= The measured DAC output

voltage with V_DD= 5.5V.

Example: 011...111to 100...000

or 100...000to 011...111

V_OUT(@2.7V)= The measured DAC output

voltage with V_DD= 2.7V.

B.15 Digital Feedthrough

B.18 Power Supply Rejection Ratio

(PSRR)

The digital feed-through is the glitch that appears at the

analog output, caused by coupling from the digital input

pins of the device. The area of the glitch is expressed

in nV-Sec and is measured with a full-scale change on

the digital input pins; example: all ‘0’s to all ‘1’s and vice

versa. The digital feedthrough is measured when the

DAC is not written to the output register.

PSRR indicates how the output of the DAC is affected

by changes in the supply voltage. PSRR is the ratio of

the change in V_OUTto a change in V_DDfor full-scale

output of the DAC. The V_OUTis measured while the

V_DDis varied ±10% (V_REFvoltage held constant) and

expressed in dB or µV/V.

B.16 -3 dB Bandwidth

B.19

V

Temperature Coefficient

OUT

This is the frequency of the signal at the V_REFpin that

causes the voltage at the V_OUTpin to fall a -3 dB value

from a static value on the V_REFpin. The output

decreases due to the RC characteristics of the resistor

ladder and the characteristics of the output buffer.

The V_OUTtemperature coefficient quantifies the error in

the resistor ladder’s resistance ratio (DAC register

code value) and output buffer due to temperature drift.

B.20 Absolute Temperature Coefficient

The absolute temperature coefficient quantifies the

error in the end-to-end output voltage (nominal Output

Voltage, V_OUT) due to temperature drift. For a DAC,

this error is typically not an issue due to the ratiometric

aspect of the output.

B.21 Noise Spectral Density

Noise spectral density is a measurement of the

device’s internally generated random noise and is

characterized as a spectral density (voltage per √Hz).

It is measured by loading the DAC to the midscale

value and measuring the noise at the V_OUTpin. It is

measured in nV/√Hz.

 2020 Microchip Technology Inc.

DS20006362A-page 107

MCP48FXBX4/8

NOTES:

DS20006362A-page 108

 2020 Microchip Technology Inc.

MCP48FXBX4/8

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

XX

X

/XX

a) MCP48FEB04-E/MQ:

b) MCP48FEB08T-E/MQ:

c) MCP48FEB18-20E/ST:

Quad-Channel, 8-Bit Nonvolatile

DAC, Extended Temperature,

20-Lead VQFN.

Tape and

Reel

Count

Temperature Package

Range

Octal-Channel, 8-Bit Nonvolatile

DAC, Tape and Reel, Extended

Temperature, 20-Lead VQFN.

Octal-Channel, 10-Bit Nonvolatile

DAC, Extended Temperature,

20-Lead TSSOP.

Device:

MCP48FXB0X: Quad/Octal-Channel, 8-Bit DAC

with SPI Interface

MCP48FXB1X: Quad/Octal-Channel, 10-Bit DAC

with SPI Interface

d) MCP48FEB18T-20E/ST: Octal-Channel, 10-Bit Nonvolatile

DAC, Tape and Reel, Extended

MCP48FXB2X: Quad/Octal-Channel, 12-Bit DAC

with SPI Interface

Temperature, 20-Lead TSSOP.

e) MCP48FVB28-E/MQ:

f) MCP48FVB28T-E/MQ:

Octal-Channel, 12-Bit Volatile

DAC, Extended Temperature,

20-Lead VQFN.

Octal-Channel, 12-Bit Volatile

DAC, Tape and Reel, Extended

Temperature, 20-Lead VQFN.

Tape and Reel:

Pin Count:

T

= Tape and Reel

Blank = Tube

20-Lead

Temperature

Range:

E

= -40°C to +125°C (Extended)

Note 1:

Tape and Reel identifier only appears in the

catalog part number description. This identifier is

used for ordering purposes and is not printed on

the device package. Check with your Microchip

Sales Office for package availability with the

Tape and Reel option.

Package:

MQ = Plastic Quad Flat, No Lead Package (VQFN),

5 x 5 mm, 20-Lead

ST

= Plastic Thin Shrink Small Outline

Package (TSSOP), 20-Lead

 2020 Microchip Technology Inc.

DS20006362A-page 109

MCP48FXBX4/8

NOTES:

DS20006362A-page 110

 2020 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights unless otherwise stated.

Trademarks

The Microchip name and logo, the Microchip logo, Adaptec,

AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,

chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,

flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,

LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,

Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,

PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,

Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,

SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,

TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA

are registered trademarks of Microchip Technology Incorporated in

the U.S.A. and other countries.

APT, ClockWorks, The Embedded Control Solutions Company,

EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,

IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision

Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,

SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,

TimePictra, TimeProvider, Vite, WinPath, and ZL are registered

trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,

CryptoAuthentication, CryptoAutomotive, CryptoCompanion,

CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average

Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial

Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,

KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,

MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,

Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,

PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple

Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,

SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,

USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and

ZENA are trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.

The Adaptec logo, Frequency on Demand, Silicon Storage

Technology, and Symmcom are registered trademarks of Microchip

Technology Inc. in other countries.

GestIC is a registered trademark of Microchip Technology Germany

II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in

other countries.

All other trademarks mentioned herein are property of their

respective companies.

ISBN: 978-1-5224-6143-2

For information regarding Microchip’s Quality Management Systems,

please visit www.microchip.com/quality.

 2020 Microchip Technology Inc.

DS20006362A-page 111

Worldwide Sales and Service

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://www.microchip.com/

support

Australia - Sydney

Tel: 61-2-9868-6733

India - Bangalore

Tel: 91-80-3090-4444

Austria - Wels

Tel: 43-7242-2244-39

Fax: 43-7242-2244-393

China - Beijing

Tel: 86-10-8569-7000

India - New Delhi

Tel: 91-11-4160-8631

Denmark - Copenhagen

Tel: 45-4485-5910

Fax: 45-4485-2829

China - Chengdu

Tel: 86-28-8665-5511

India - Pune

Tel: 91-20-4121-0141

Finland - Espoo

Tel: 358-9-4520-820

China - Chongqing

Tel: 86-23-8980-9588

Japan - Osaka

Tel: 81-6-6152-7160

Web Address:

www.microchip.com

France - Paris

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

China - Dongguan

Tel: 86-769-8702-9880

Japan - Tokyo

Tel: 81-3-6880- 3770

Atlanta

Duluth, GA

Tel: 678-957-9614

Fax: 678-957-1455

China - Guangzhou

Tel: 86-20-8755-8029

Korea - Daegu

Tel: 82-53-744-4301

Germany - Garching

Tel: 49-8931-9700

China - Hangzhou

Tel: 86-571-8792-8115

Korea - Seoul

Tel: 82-2-554-7200

Germany - Haan

Tel: 49-2129-3766400

Austin, TX

Tel: 512-257-3370

China - Hong Kong SAR

Tel: 852-2943-5100

Malaysia - Kuala Lumpur

Tel: 60-3-7651-7906

Germany - Heilbronn

Tel: 49-7131-72400

Boston

Westborough, MA

Tel: 774-760-0087

Fax: 774-760-0088

China - Nanjing

Tel: 86-25-8473-2460

Malaysia - Penang

Tel: 60-4-227-8870

Germany - Karlsruhe

Tel: 49-721-625370

China - Qingdao

Philippines - Manila

Germany - Munich

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Tel: 86-532-8502-7355

Tel: 63-2-634-9065

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

China - Shanghai

Tel: 86-21-3326-8000

Singapore

Tel: 65-6334-8870

Germany - Rosenheim

Tel: 49-8031-354-560

China - Shenyang

Tel: 86-24-2334-2829

Taiwan - Hsin Chu

Tel: 886-3-577-8366

Dallas

Addison, TX

Tel: 972-818-7423

Fax: 972-818-2924

Israel - Ra’anana

Tel: 972-9-744-7705

China - Shenzhen

Tel: 86-755-8864-2200

Taiwan - Kaohsiung

Tel: 886-7-213-7830

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Suzhou

Tel: 86-186-6233-1526

Taiwan - Taipei

Tel: 886-2-2508-8600

Detroit

Novi, MI

Tel: 248-848-4000

China - Wuhan

Tel: 86-27-5980-5300

Thailand - Bangkok

Tel: 66-2-694-1351

Italy - Padova

Tel: 39-049-7625286

Houston, TX

Tel: 281-894-5983

China - Xian

Tel: 86-29-8833-7252

Vietnam - Ho Chi Minh

Tel: 84-28-5448-2100

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

Indianapolis

Noblesville, IN

Tel: 317-773-8323

Fax: 317-773-5453

Tel: 317-536-2380

China - Xiamen

Tel: 86-592-2388138

Norway - Trondheim

Tel: 47-7288-4388

China - Zhuhai

Tel: 86-756-3210040

Poland - Warsaw

Tel: 48-22-3325737

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

Tel: 951-273-7800

Romania - Bucharest

Tel: 40-21-407-87-50

Spain - Madrid

Tel: 34-91-708-08-90

Fax: 34-91-708-08-91

Raleigh, NC

Tel: 919-844-7510

Sweden - Gothenberg

Tel: 46-31-704-60-40

New York, NY

Tel: 631-435-6000

Sweden - Stockholm

Tel: 46-8-5090-4654

San Jose, CA

Tel: 408-735-9110

Tel: 408-436-4270

UK - Wokingham

Tel: 44-118-921-5800

Fax: 44-118-921-5820

Canada - Toronto

Tel: 905-695-1980

Fax: 905-695-2078

DS20006362A-page 112

 2020 Microchip Technology Inc.

02/28/20


型号：	MCP48FEB04
厂家：	MICROCHIP
描述：	8/10/12-Bit Quad/Octal Voltage Output, 6 LSb INL Digital-to-Analog Converters with SPI Interface
文件：	总112页 (文件大小：9618K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP48FEB04 [MICROCHIP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E