MCP6001RT-I/MS_技术文档

MCP6001/2/4

1 MHz, Low-Power Op Amp

Features

Description

• Available in SC-70-5 and SOT-23-5 packages

• Gain Bandwidth Product: 1 MHz (typ.)

• Rail-to-Rail Input/Output

The Microchip Technology Inc. MCP6001/2/4 family of

operational amplifiers (op amps) is specifically

designed for general-purpose applications. This family

has a 1 MHz Gain Bandwidth Product (GBWP) and

90° phase margin (typ.). It also maintains 45° phase

margin (typ.) with a 500 pF capacitive load. This family

operates from a single supply voltage as low as 1.8V,

while drawing 100 µA (typ.) quiescent current.

Additionally, the MCP6001/2/4 supports rail-to-rail

input and output swing, with a common mode input

voltage range of V_DD+ 300 mV to V_SS– 300 mV. This

family of op amps is designed with Microchip’s

advanced CMOS process.

• Supply Voltage: 1.8V to 5.5V

• Supply Current: I_Q= 100 µA (typ.)

• Phase Margin: 90° (typ.)

• Temperature Range:

- Industrial: -40°C to +85°C

- Extended: -40°C to +125°C

• Available in Single, Dual and Quad Packages

Applications

The MCP6001/2/4 family is available in the industrial

and extended temperature ranges, with a power supply

range of 1.8V to 5.5V.

• Automotive

• Portable Equipment

• Photodiode Amplifier

• Analog Filters

Package Types

• Notebooks and PDAs

• Battery-Powered Systems

MCP6001

MCP6002

SC-70-5, SOT-23-5

PDIP, SOIC, MSOP

V_DD

V_OUT

V_OUTA

8

7

6

5

V_DD

1

2

3

5

1

2

3

4

Available Tools

V_SS

V_IN

V_INA

–

+

-

V_OUTB

+

-

SPICE Macro Models (at www.microchip.com)

FilterLab^®Software (at www.microchip.com)

+

V_IN–

V_INA

4

+ -

V_INB

–

+

V_SS

Typical Application

MCP6001R

V_DD

SOT-23-5

MCP6004

PDIP, SOIC, TSSOP

V_SS

V_OUT

V_DD

V_IN

1

5

4

+

2

3

V_OUTA

V

V_OUT

14

13

12

11

MCP6001

1

2

3

4

OUTD

-

V_IN

+

V_IN–

V_INA

V_DD

–

+ -

- +

IND

+

IND

V_SS

V_INB

+

V

+

–

MCP6001U

10

9

5

6

7

INC

R₁

-

+

V_INB

–

V_INC

R₂

SOT-23-5

R₁

-----

V_OUTB

V_OUTC

8

V_IN

+

V_DD

5

1

Gain = 1 +

+

R₂

V_SS

V_REF

2

3

-

V_IN

–

V_OUT

4

Non-Inverting Amplifier

DS21733F-page 1

MCP6001/2/4

† Notice: Stresses above those listed under “Maximum

Ratings” may cause permanent damage to the device.

This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification

is not implied. Exposure to maximum rating conditions

for extended periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V

– V ........................................................................7.0V

SS

DD

All Inputs and Outputs ................... V – 0.3V to V + 0.3V

SS

DD

Difference Input Voltage ...................................... |V – V

|

DD

SS

Output Short-Circuit Current .................................continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±30 mA

Storage Temperature.....................................-65°C to +150°C

Maximum Junction Temperature (T )..........................+150°C

J

ESD Protection On All Pins (HBM;MM) ............... ≥ 4 kV; 200V

DC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND, V_CM= V_DD/2,

R_L= 10 kΩ to V_DD/2 and V_OUT≈ V_DD/2.

Parameters

Input Offset

Input Offset Voltage

Sym

Min

Typ

Max

Units

Conditions

V_OS

-4.5

—

+4.5

—

mV V_CM= V_SS(Note 1)

Input Offset Drift with Temperature ΔV_OS/ΔT_A

±2.0

µV/°C T_A= -40°C to +125°C,

V_CM= V_SS

Power Supply Rejection Ratio

Input Bias Current and Impedance

Input Bias Current:

PSRR

—

86

—

dB

V_CM= V_SS

I_B

—

±1.0

19

—

pA

Industrial Temperature

T_A= +85°C

Extended Temperature

I_B

1100

pA

T_A= +125°C

Input Offset Current

I_OS

Z_CM

Z_DIFF

±1.0

pA

Common Mode Input Impedance

Differential Input Impedance

Common Mode

10¹³||6

10¹³||3

Ω||pF

Common Mode Input Range

Common Mode Rejection Ratio

V_CMR

V_SS− 0.3

—

V_DD+ 0.3

—

V

CMRR

60

76

dB

V_CM= -0.3V to 5.3V,

V_DD= 5V

Open-Loop Gain

DC Open-Loop Gain (Large Signal)

A_OL

88

112

—

dB

V_OUT= 0.3V to V_DD– 0.3V,

V_CM= V_SS

Output

Maximum Output Voltage Swing

Output Short-Circuit Current

V_OL, V_OHV_SS+ 25

—

±6

V_DD– 25

mV V_DD= 5.5V

mA V_DD= 1.8V

I_SC

—

±23

mA

V_DD= 5.5V

Power Supply

Supply Voltage

V_DD

I_Q

1.8

50

—

5.5

V

Quiescent Current per Amplifier

100

170

µA

I_O= 0, V_DD= 5.5V, V_CM= 5V

Note 1: MCP6001/2/4 parts with date codes prior to December 2004 (week code 49) were tested to ±7 mV minimum/

maximum limits.

DS21733F-page 2

MCP6001/2/4

AC ELECTRICAL SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8 to 5.5V, V_SS= GND, V_CM= V_DD/2,

V_OUT≈ V_DD/2, R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

Parameters

Sym

Min

Typ

Max

Units

Conditions

AC Response

Gain Bandwidth Product

Phase Margin

GBWP

PM

—

1.0

90

—

MHz

°

G = +1

Slew Rate

SR

0.6

V/µs

Noise

Input Noise Voltage

Input Noise Voltage Density

Input Noise Current Density

E_ni

e_ni

i_ni

—

6.1

28

—

µVp-p f = 0.1 Hz to 10 Hz

nV/√Hz f = 1 kHz

fA/√Hz f = 1 kHz

0.6

TEMPERATURE SPECIFICATIONS

Electrical Characteristics: Unless otherwise indicated, V_DD= +1.8V to +5.5V and V_SS= GND.

Parameters

Temperature Ranges

Sym

Min

Typ

Max

Units

Conditions

Industrial Temperature Range

Extended Temperature Range

Operating Temperature Range

Storage Temperature Range

T_A

-40

-65

—

+85

°C

+125

+150

Note

Thermal Package Resistances

Thermal Resistance, 5L-SC70

Thermal Resistance, 5L-SOT-23

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC (150 mil)

Thermal Resistance, 8L-MSOP

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

—

θ_JA

331

256

85

°C/W

163

206

70

120

100

Note:

The industrial temperature devices operate over this extended temperature range, but with reduced

performance. In any case, the internal Junction Temperature (T_J) must not exceed the Absolute Maximum

specification of +150°C.

DS21733F-page 3

MCP6001/2/4

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

100

95

90

85

80

75

70

20%

18%

16%

14%

12%

10%

8%

64,695 Samples

_CM= V_SS

V

PSRR (V_CM= V_SS

)

6%

4%

CMRR (V_CM= -0.3V to +5.3V)

2%

0%

-50

-25

0

25

50

75

100

125

Input Offset Voltage (mV)

Ambient Temperature (°C)

FIGURE 2-1:

Input Offset Voltage.

FIGURE 2-4:

CMRR, PSRR vs. Ambient

Temperature.

100

90

80

70

60

50

40

30

20

120

100

80

60

40

20

0

V_CM= V_SS

-30

-60

Phase

PSRR–

PSRR+

-90

-120

Gain

CMRR

-150

-180

-210

V_CM= V_SS

-20

10

100

1.E+02

1k

10k

1.E+04

100k

1.E+05

1.E+01

1.E+03

0.1

1

10 100 1k 10k 100k 1M 10M

1.E- 1.E 1.E 1.E 1.E 1.E 1.E 1.E 1.E

01 +00 +01 F+r0e2qu+e0n3cy+(0H4z)+05 +06 +07

Frequency (Hz)

FIGURE 2-2:

PSRR, CMRR vs.

FIGURE 2-5:

Open-Loop Gain, Phase vs.

Frequency.

14%

55%

50%

45%

40% V_CM= V_DD

35%

30%

25%

20%

15%

10%

5%

1230 Samples

V_DD= 5.5V

V_CM= V_DD

605 Samples

_DD= 5.5V

12%

10%

8%

V

T_A= +85°C

T_A= +125°C

6%

4%

2%

0%

Input Bias Current (pA)

FIGURE 2-3:

Input Bias Current at +85°C.

FIGURE 2-6:

Input Bias Current at +125°C.

DS21733F-page 4

MCP6001/2/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

1,000

18%

1225 Samples

T_A= -40°C to +125°C

16%

14%

V_CM= V_SS

12%

10%

100

8%

6%

4%

2%

0%

10

0.1

1

10

100

1.E-01 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0

1k

10k 100k

Input Offset Voltage Drift (µV/°C)

0

F1reque2ncy (Hz3)

4

5

FIGURE 2-7:

Input Noise Voltage Density

FIGURE 2-10:

Input Offset Voltage Drift.

vs. Frequency.

200

150

100

50

0

V_DD= 1.8V

-100

-200

-300

-400

-500

-600

-700

V_DD= 5.5V

0

V_DD= 1.8V

T_A= -40°C

-50

-100

-150

-200

T

_A= +25°C

_A= +85°C

T_A= +125°C

V_CM= V_SS

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Output Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-11:

Input Offset Voltage vs.

FIGURE 2-8:

Input Offset Voltage vs.

Output Voltage.

Common Mode Input Voltage at V_DD= 1.8V.

30

0

V_DD= 5.5V

-100

-200

-300

25

20

15

10

5

T_A= -40°C

T_A= +25°C

T_A= +85°C

T_A= +125°C

-400

-500

-600

-700

T_A= -40°C

T

_A= +25°C

_A= +85°C

T_A= +125°C

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

Common Mode Input Voltage (V)

FIGURE 2-12:

Output Short-Circuit Current

FIGURE 2-9:

Input Offset Voltage vs.

vs. Power Supply Voltage.

Common Mode Input Voltage at V_DD= 5.5V.

DS21733F-page 5

MCP6001/2/4

Note: Unless otherwise indicated, T_A= +25°C, V_DD= +1.8V to +5.5V, V_SS= GND, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 10 kΩ to V_DD/2 and C_L= 60 pF.

0.08

1.0

0.9

G = +1 V/V

Falling Edge, V_DD= 5.5V

0.06

Falling Edge, V_DD= 1.8V

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0.0

0.04

0.02

0.00

Rising Edge, V_DD= 5.5V

Rising Edge, V_DD= 1.8V

-0.02

-0.04

-0.06

-0.08

-50

-25

0

25

50

75

100

125

0.E+00

1.E-06

2.E-06

3.E-06

4.E-06

5.E-06

6.E-06

7.E-06

8.E-06

9.E-06

1.E-05

Ambient Temperature (°C)

Time (1 µs/div)

FIGURE 2-13:

Slew Rate vs. Ambient

FIGURE 2-16:

Small-Signal, Non-Inverting

Temperature.

Pulse Response.

1,000

100

10

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

G = +1 V/V

V

_DD= 5.0V

V_DD– V_OH

V_OL– V_SS

1

10µ

100µ

1.E-04

1m

1.E-03

10m

1.E-02

0.0 0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

8.E-05

9.E-05

1.E-04

1.E-05

Time (10 µs/div)

Output Current Magnitude (A)

FIGURE 2-14:

Output Voltage Headroom

FIGURE 2-17:

Large-Signal, Non-Inverting

vs. Output Current Magnitude.

Pulse Response.

180

10

V_CM= V_DD- 0.5V

160

140

120

100

80

V_DD= 5.5V

V_DD= 1.8V

1

T_A= +125°C

60

T_A= +85°C

_A= +25°C

40

T

T_A= -40°C

20

0

0.1

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

1k

10k

1.E+04

100k

1.E+05

1M

1.E+06

1.E+03

Frequency (Hz)

FIGURE 2-15:

Output Voltage Swing vs.

FIGURE 2-18:

Quiescent Current vs.

Frequency.

Power Supply Voltage.

DS21733F-page 6

MCP6001/2/4

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE

MCP6001 MCP6001R MCP6001U MCP6002 MCP6004

Symbol

Description

1

4

1

4

3

1

2

3

8

5

6

1

2

3

4

5

6

V_OUT, V_OUTAAnalog Output (op amp A)

V_IN–, V_INA

–

+

Inverting Input (op amp A)

Non-inverting Input (op amp A)

Positive Power Supply

3

1

V_IN+, V_INA

V_DD

5

2

5

—

V_INB

+

–

Non-inverting Input (op amp B)

Inverting Input (op amp B)

V_INB

—

2

—

5

—

2

7

V_OUTB

V_OUTC

Analog Output (op amp B)

Analog Output (op amp C)

Inverting Input (op amp C)

Non-inverting Input (op amp C)

Negative Power Supply

—

4

8

9

V_INC

–

+

10

11

12

13

14

V_INC

V_SS

—

V_IND

+

Non-inverting Input (op amp D)

Inverting Input (op amp D)

Analog Output (op amp D)

V_IND

–

V_OUTD

3.1

Analog Outputs

3.3

Power Supply (V and V

)

DD

SS

The output pins are low-impedance voltage sources.

The positive power supply (V_DD) is 1.8V to 5.5V higher

than the negative power supply (V_SS). For normal

operation, the other pins are at voltages between V_SS

3.2

Analog Inputs

and V_DD

.

The non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

Typically, these parts are used in a single (positive)

supply configuration. In this case, V_SSis connected to

ground and V_DDis connected to the supply. V_DDwill

need a local bypass capacitor (typically 0.01 µF to

0.1 µF) within 2 mm of the V_DDpin. These parts can

share a bulk capacitor with analog parts (typically

2.2 µF to 10 µF) within 100 mm of the V_DDpin.

DS21733F-page 7

MCP6001/2/4

4.0

APPLICATION INFORMATION

–

The MCP6001/2/4 family of op amps is manufactured

using Microchip’s state-of-the-art CMOS process and

is specifically designed for low-cost, low-power and

general-purpose applications. The low supply voltage,

low quiescent current and wide bandwidth makes the

MCP6001/2/4 ideal for battery-powered applications.

This device has high phase margin, which makes it

stable for larger capacitive load applications.

V_OUT

R_IN

MCP600X

+

V_IN

(Maximum expected V_IN) – V_DD

------------------------------------------------------------------------------

2 mA

R_IN

≥

V_SS– (Minimum expected V_IN

)

4.1

Rail-to-Rail Input

---------------------------------------------------------------------------

R_IN

≥

2 mA

The MCP6001/2/4 op amps are designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 4-1 shows the input voltage exceeding

the supply voltage without any phase reversal.

FIGURE 4-2:

Resistor (R_IN).

Input Current Limiting

4.2

Rail-to-Rail Output

6

The output voltage range of the MCP6001/2/4 op amps

is V_DD– 25 mV (min.) and V_SS+ 25 mV (max.) when

R_L= 10 kΩ is connected to V_DD/2 and V_DD= 5.5V.

Refer to Figure 2-14 for more information.

V_IN

V_DD= 5.0V

G = +2 V/V

5

4

V_OUT

3

4.3

Capacitive Loads

2

Driving large capacitive loads can cause stability prob-

lems for voltage feedback op amps. As the load capac-

itance increases, the feedback loop’s phase margin

decreases and the closed-loop bandwidth is reduced.

This produces gain peaking in the frequency response,

with overshoot and ringing in the step response. While

a unity-gain buffer (G = +1) is the most sensitive to

capacitive loads, all gains show the same general

behavior.

1

0

0.E+00

1.E-05

2.E-05

3.E-05

4.E-05

5.E-05

6.E-05

7.E-05

8.E-05

9.E-05

1.E-04

-1

Time (10 µs/div)

FIGURE 4-1:

Phase Reversal.

The MCP6001/2/4 Show No

The input stage of the MCP6001/2/4 op amps use two

differential input stages in parallel. One operates at a

low common mode input voltage (V_CM), while the other

operates at a high V_CM. With this topology, the device

operates with a V_CMup to 300 mV above V_DDand

300 mV below V_SS. The input offset voltage is

measured at V_CM= V_SS– 300 mV and V_DD+ 300 mV

to ensure proper operation.

When driving large capacitive loads with these op

amps (e.g., > 100 pF when G = +1), a small series

resistor at the output (R_ISOin Figure 4-3) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The band-

width will be generally lower than the bandwidth with no

capacitance load.

Input voltages that exceed the input voltage range

(V_SS– 0.3V to V_DD+ 0.3V at 25°C) can cause

excessive current to flow into or out of the input pins,

while current beyond ±2 mA can cause reliability

problems. Applications that exceed this rating must be

externally limited with a resistor, as shown in Figure 4-2.

–

R_ISO

V_OUT

MCP600X

+

V_IN

C_L

FIGURE 4-3:

Output resistor, R_ISO

stabilizes large capacitive loads.

DS21733F-page 8

MCP6001/2/4

Figure 4-4 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit's noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

4.5

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 10¹²Ω. A 5V difference would

cause 5 pA of current to flow; which is greater than the

MCP6001/2/4 family’s bias current at 25°C (1 pA, typ.).

1000

V_DD= 5.0V

R_L= 100 k:

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in

Figure 4-5.

100

G_N= 1

G_Nt 2

V_IN-

V_IN+

V_SS

10

10p

100p

1.E-10

1n

1.E-09

10n

1.E-08

1.E-11

Normalized Load Capacitance; C_L/G_N(F)

FIGURE 4-4:

Recommended R_ISOvalues

for Capacitive Loads.

After selecting R_ISOfor your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO’s value until the

response is reasonable. Bench evaluation and simula-

tions with the MCP6001/2/4 SPICE macro model are

very helpful.

Guard Ring

Example Guard Ring Layout

FIGURE 4-5:

for Inverting Gain.

1. Non-inverting Gain and Unity-Gain Buffer:

4.4

Supply Bypass

a. Connect the non-inverting pin (V_IN+) to the

input with a wire that does not touch the

PCB surface.

With this family of operational amplifiers, the power

supply pin (V_DDfor single-supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with other analog parts.

b. Connect the guard ring to the inverting input

pin (V_IN–). This biases the guard ring to the

common mode input voltage.

2. Inverting Gain and Transimpedance Gain

Amplifiers (convert current to voltage, such as

photo detectors):

a. Connect the guard ring to the non-inverting

input pin (V_IN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., V_DD/2 or ground).

b. Connect the inverting pin (V_IN–) to the input

with a wire that does not touch the PCB

surface.

DS21733F-page 9

MCP6001/2/4

4.6

Application Circuits

100 pF

4.6.1

UNITY-GAIN BUFFER

The rail-to-rail input and output capability of the

MCP6001/2/4 op amp is ideal for unity-gain buffer

applications. The low quiescent current and wide

bandwidth makes the device suitable for a buffer

configuration in an instrumentation amplifier circuit, as

shown in Figure 4-6.

14.3 kΩ 53.6 kΩ

V

IN

+

MCP6002

–

V

33 pF

OUT

FIGURE 4-7:

Low- Pass Filter.

Active Second-Order

–

R₁

R₂

1/2

MCP6002

V_IN1

+

4.6.3

PEAK DETECTOR

–

The MCP6001/2/4 op amp has a high input impedance,

rail-to-rail input/output and low input bias current, which

makes this device suitable for peak detector applica-

tions. Figure 4-8 shows a peak detector circuit with

clear and sample switches. The peak-detection cycle

uses a clock (CLK), as shown in Figure 4-8.

V_OUT

MCP6001

+

–

R₂

1/2

MCP6002

V_IN2

+

R = 20 kΩ

1

R₁

At the rising edge of CLK, Sample Switch closes to

begin sampling. The peak voltage stored on C₁is sam-

pled to C₂for a sample time defined by t_SAMP. At the

end of the sample time (falling edge of Sample Signal),

Clear Signal goes high and closes the Clear Switch.

When the Clear Switch closes, C₁discharges through

R₁for a time defined by t_CLEAR. At the end of the clear

time (falling edge of Clear Signal), op amp A begins to

store the peak value of V_INon C₁for a time defined by

R = 10 kΩ

2

V_REF

R₁

-----

V_OUT= (V_IN2– V_IN1) •

+ V_REF

R₂

FIGURE 4-6:

with Unity-Gain Buffer Inputs.

Instrumentation Amplifier

t_DETECT

.

4.6.2

ACTIVE LOW-PASS FILTER

In order to define t_SAMPand t_CLEAR, it is necessary to

determine the capacitor charging and discharging

period. The capacitor charging time is limited by the

^{amplifier source current, while the discharging time (}τ)

is defined using R₁(τ = R₁C₁). t_DETECTis the time that

the input signal is sampled on C₁and is dependent on

the input voltage change frequency.

The MCP6001/2/4 op amp’s low input bias current

makes it possible for the designer to use larger resis-

tors and smaller capacitors for active low-pass filter

applications. However, as the resistance increases, the

noise generated also increases. Parasitic capacitances

and the large value resistors could also modify the fre-

quency response. These trade-offs need to be

considered when selecting circuit elements.

The op amp output current limit, and the size of the

storage capacitors (both C₁and C₂), could create slew-

ing limitations as the input voltage (V_IN) increases.

Current through a capacitor is dependent on the size of

the capacitor and the rate of voltage change. From this

relationship, the rate of voltage change or the slew rate

can be determined. For example, with an op amp short-

circuit current of I_SC= 25 mA and a load capacitor of

C₁= 0.1 µF, then:

Usually, the op amp bandwidth is 100X the filter cutoff

frequency (or higher) for good performance. It is possi-

ble to have the op amp bandwidth 10X higher than the

cutoff frequency, thus having a design that is more

sensitive to component tolerances.

Figure 4-7 shows a second-order Butterworth filter with

100 kHz cutoff frequency and a gain of +1 V/V; the op

amp bandwidth is only 10X higher than the cutoff

frequency. The component values were selected using

Microchip’s FilterLab^®software.

EQUATION 4-1:

dV_C1

------------

I_SC= C₁

dt

dV_C1

------------

I_SC

-------

C₁

=

dt

25mA

--------------

0.1μF

dV_C1

------------

= 250mV ⁄ μs

dt

DS21733F-page 10

MCP6001/2/4

This voltage rate of change is less than the MCP6001/2/4

slew rate of 0.6 V/µs. When the input voltage swings

below the voltage across C₁, D₁becomes reverse-

biased. This opens the feedback loop and rails the

amplifier. When the input voltage increases, the amplifier

recovers at its slew rate. Based on the rate of voltage

change shown in the above equation, it takes an

extended period of time to charge a 0.1 µF capacitor. The

capacitors need to be selected so that the circuit is not

limited by the amplifier slew rate. Therefore, the capaci-

tors should be less than 40 µF and a stabilizing resistor

(R_ISO) needs to be properly selected. (Refer to

Section 4.3 “Capacitive Loads”).

V_IN

D₁

+

R_ISO

V_C1

1/2

R_ISO

+

V_C2

MCP6002

1/2

V_OUT

+

MCP6002

–

C₁

R₁

Op Amp A

MCP6001

–

C₂

Op Amp B

Op Amp C

Sample

Switch

Clear

Switch

t

SAMP

Sample Signal

t

CLEAR

Clear Signal

CLK

t

DETECT

FIGURE 4-8:

Peak Detector with Clear and Sample CMOS Analog Switches.

DS21733F-page 11

MCP6001/2/4

5.0

DESIGN TOOLS

Microchip provides the basic design tools needed for

the MCP6001/2/4 family of op amps.

5.1

SPICE Macro Model

The latest SPICE macro model for the MCP6001/2/4

op amps is available on our web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation at room temperature. See the

model file for information on its capabilities.

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

®

5.2

FilterLab Software

Microchip’s FilterLab^®software is an innovative

software tool that simplifies analog active filter (using

op amps) design. Available at no cost from our web site

at www.microchip.com, the FilterLab design tool

provides full schematic diagrams of the filter circuit with

component values. It also outputs the filter circuit in

SPICE format, which can be used with the macro

model to simulate actual filter performance.

DS21733F-page 12

MCP6001/2/4

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

5-Lead SC-70 (MCP6001)

Example: (I-Temp)

I-Temp

Code

E-Temp

Code

XXN (Front)

YWW (Back)

AA7 (Front)

432 (Back)

Device

MCP6001

AAN

CDN

Note: Applies to 5-Lead SC-70.

OR

I-Temp

Code

E-Temp

Code

Device

AA74

XXNN

MCP6001

AANN

CDNN

Note: Applies to 5-Lead SC-70.

Example: (E-Temp)

5-Lead SOT-23 (MCP6001/1R/1U)

5

4

5

4

I-Temp

Code

E-Temp

Code

Device

MCP6001

AANN

ADNN

AFNN

CDNN

CENN

CFNN

CD25

XXNN

MCP6001R

MCP6001U

1

2

3

1

2

3

Note: Applies to 5-Lead SOT-23.

8-Lead PDIP (300 mil)

Example:

XXXXXXXX

XXXXXNNN

MCP6002

I/P256

0432

YYWW

Legend: XX...X Customer specific information*

YY

WW

NNN

Year code (last 2 digits of calendar year)

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line thus limiting the number of available characters

for customer specific information.

*

Standard marking consists of Microchip part number, year code, week code, traceability code (facility

code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please

check with your Microchip Sales Office.

DS21733F-page 13

MCP6001/2/4

Package Marking Information (Continued)

8-Lead SOIC (150 mil)

Example:

XXXXXXXX

MCP6002

XXXXYYWW

I/SN0432

NNN

256

Example:

8-Lead MSOP

XXXXXX

YWWNNN

6002I

432256

14-Lead PDIP (300 mil) (MCP6004)

Example:

XXXXXXXXXXXXXX

MCP6004-I/P

0432256

YYWWNNN

14-Lead SOIC (150 mil) (MCP6004)

Example:

XXXXXXXXXX

MCP6004ISL

0432256

YYWWNNN

Example:

14-Lead TSSOP (MCP6004)

XXXXXX

YYWW

6004ST

0432

NNN

256

DS21733F-page 14

MCP6001/2/4

5-Lead Plastic Package (SC-70)

E

E1

D

p

B

n

1

Q1

A2

A

c

A1

L

Units

INCHES

NOM

5

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

5

MAX

n

p

Number of Pins

Pitch

.026 (BSC)

0.65 (BSC)

Overall Height

A

.031

.000

.071

.045

.071

.004

.006

.043

0.80

1.10

Molded Package Thickness

Standoff

A2

A1

E

.039

.004

.094

.053

.087

.012

.016

.007

.012

0.80

0.00

1.80

1.15

1.80

0.10

0.15

1.00

0.10

2.40

1.35

2.20

0.30

0.40

0.18

0.30

Overall Width

Molded Package Width

Overall Length

E1

D

Foot Length

L

Q1

c

Top of Molded Pkg to Lead Shoulder

Lead Thickness

Lead Width

B

*Controlling Parameter

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed .005" (0.127mm) per side.

JEITA (EIAJ) Standard: SC-70

Drawing No. C04-061

DS21733F-page 15

MCP6001/2/4

5-Lead Plastic Small Outline Transistor (OT) (SOT23)

E

E1

p

B

p1

D

n

1

α

c

A

A2

φ

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

5

MAX

n

p

Number of Pins

5

Pitch

.038

.075

.046

.043

.003

.110

.064

.116

.018

5

0.95

1.90

p1

Outside lead pitch (basic)

Overall Height

A

A2

A1

E

.035

.000

.102

.059

.110

.014

0

.057

0.90

1.18

1.10

0.08

2.80

1.63

2.95

0.45

5

1.45

Molded Package Thickness

.051

.006

.118

.069

.122

.022

10

1.30

0.15

3.00

1.75

3.10

0.55

10

Standoff

§

0.00

2.60

1.50

2.80

0.35

0

Overall Width

Molded Package Width

Overall Length

E1

D

Foot Length

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.004

.014

0

.006

.017

5

.008

.020

10

0.09

0.35

0

0.15

0.43

5

0.20

0.50

10

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-178

Drawing No. C04-091

DS21733F-page 16

MCP6001/2/4

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.100

.155

.130

2.54

3.94

3.30

Top to Seating Plane

A

.140

.170

3.56

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

2.92

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

3.68

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

DS21733F-page 17

MCP6001/2/4

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.050

.061

.056

.007

.237

.154

.193

.015

.025

4

1.27

Overall Height

A

.053

.069

1.35

1.32

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

0.10

5.79

3.71

4.80

0.25

0.48

0

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS21733F-page 18

MCP6001/2/4

8-Lead Plastic Micro Small Outline Package (MS) (MSOP)

E

E1

p

D

2

B

n

1

α

A2

A

c

φ

A1

(F)

L

β

Units

Dimension Limits

INCHES

NOM

8

MILLIMETERS*

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.026 BSC

0.65 BSC

Overall Height

A

A2

A1

E

-

.043

-

1.10

Molded Package Thickness

Standoff

.030

.000

.033

.037

.006

0.75

0.00

0.85

0.95

0.15

-

Overall Width

.193 TYP.

4.90 BSC

Molded Package Width

Overall Length

Foot Length

E1

D

.118 BSC

3.00 BSC

.118 BSC

3.00 BSC

L

.016

.024

.031

0.40

0.60

0.80

Footprint (Reference)

Foot Angle

F

.037 REF

0.95 REF

φ

c

0°

.003

.009

5°

-

.006

.012

-

8°

.009

.016

15°

0°

0.08

0.22

5°

-

8°

0.23

0.40

15°

Lead Thickness

Lead Width

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

*Controlling Parameter

Notes:

5°

-

15°

5°

15°

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not

exceed .010" (0.254mm) per side.

JEDEC Equivalent: MO-187

Drawing No. C04-111

DS21733F-page 19

MCP6001/2/4

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

B1

β

eB

p

B

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

14

.100

.155

.130

2.54

Top to Seating Plane

A

.140

.170

3.56

2.92

0.38

7.62

6.10

18.80

3.18

0.20

1.14

0.36

7.87

5

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.740

.125

.008

.045

.014

.310

5

.145

3.68

.313

.250

.750

.130

.012

.058

.018

.370

10

.325

.260

.760

.135

.015

.070

.022

.430

15

7.94

6.35

19.05

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

19.30

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-005

DS21733F-page 20

MCP6001/2/4

14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

α

h

45°

c

A2

A

φ

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

14

.050

.061

.056

.007

.236

.154

.342

.015

.033

4

1.27

1.55

1.42

0.18

5.99

3.90

8.69

0.38

0.84

4

Overall Height

A

.053

.069

1.35

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.150

.337

.010

.016

0

.061

.010

.244

.157

.347

.020

.050

8

1.32

0.10

5.79

3.81

8.56

0.25

0.41

0

1.55

0.25

6.20

3.99

8.81

0.51

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.014

0

.009

.017

12

.010

.020

15

0.20

0.36

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-065

DS21733F-page 21

MCP6001/2/4

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

φ

A1

A2

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

14

.026

0.65

Overall Height

A

.043

1.10

0.95

0.15

6.50

4.50

5.10

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.033

.002

.246

.169

.193

.020

0

.035

.004

.251

.173

.197

.024

4

.037

.006

.256

.177

.201

.028

8

0.85

0.05

0.90

0.10

6.38

4.40

5.00

0.60

4

§

Overall Width

6.25

4.30

4.90

0.50

0

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B1

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-087

DS21733F-page 22

MCP6001/2/4

APPENDIX A: REVISION HISTORY

Revision F (March 2005)

Updated 6.0 “Packaging Information” to include old

and new packaging examples.

Revision E (December 2004)

The following is the list of modifications:

1. V_OSspecification reduced to ±4.5 mV from

±7.0 mV for parts starting with date code

YYWW = 0449

2. Corrected package markings in Section 6.0

“Packaging Information”

3. Added Appendix A: Revision History.

Revision D (May 2003)

Revision C (December 2002)

Revision B (October 2002)

Revision A (June 2002)

Original data sheet release.

DS21733E-page 23

MCP6001/2/4

NOTES:

DS21733E-page 24

MCP6001/2/4

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a)

b)

c)

d)

MCP6001T-I/LT:

Tape and Reel,

Temperature

Range

Package

Industrial Temperature,

5LD SC-70 package

Tape and Reel,

Industrial Temperature,

5LD SOT-23 package.

MCP6001T-I/OT:

Device:

MCP6001T:

Single Op Amp (Tape and Reel)

(SC-70, SOT-23)

Single Op Amp (Tape and Reel) (SOT-23)

MCP6001RT-I/OT: Tape and Reel,

Industrial Temperature,

5LD SOT-23 package.

MCP6001UT-E/OT: Tape and Reel,

MCP6001RT:

MCP6001UT: Single Op Amp (Tape and Reel) (SOT-23)

MCP6002:

MCP6002T:

Dual Op Amp

Dual Op Amp (Tape and Reel)

(SOIC, MSOP)

Quad Op Amp

Quad Op Amp (Tape and Reel)

(SOIC, MSOP)

Extended Temperature,

5LD SOT-23 package.

MCP6004:

MCP6004T:

a)

b)

c)

d)

e)

MCP6002-I/MS:

MCP6002-I/P:

Industrial Temperature,

8LD MSOP package.

Industrial Temperature,

8LD PDIP package.

Extended Temperature,

8LD PDIP package.

Industrial Temperature,

8LD SOIC package.

Tape and Reel,

Temperature Range:

Package:

I

E

=

-40°C to +85°C

-40°C to +125°C

MCP6002-E/P:

MCP6002-I/SN:

MCP6002T-I/MS:

LT

OT

=

Plastic Package (SC-70), 5-lead (MCP6001 only)

Plastic Small Outline Transistor (SOT-23), 5-lead

(MCP6001, MCP6001R, MCP6001U)

Plastic MSOP, 8-lead

Plastic DIP (300 mil Body), 8-lead, 14-lead

Plastic SOIC, (150 mil Body), 8-lead

Plastic SOIC (150 mil Body), 14-lead

Plastic TSSOP (4.4mm Body), 14-lead

MS

P

SN

SL

ST

=

Industrial Temperature,

8LD MSOP package.

a)

b)

c)

d)

e)

MCP6004-I/P:

MCP6004-I/SL:

MCP6004-E/SL:

MCP6004-I/ST:

MCP6004T-I/SL:

Industrial Temperature,

14LD PDIP package.

IndustrialTemperature,,

14LD SOIC package.

Extended Temperature,,

14LD SOIC package.

Industrial Temperature,

14LD TSSOP package.

Tape and Reel,

Industrial Temperature,

14LD SOIC package.

Tape and Reel,

f)

MCP6004T-I/ST:

Industrial Temperature,

14LD TSSOP package.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and

recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

Customer Notification System

Register on our web site (www.microchip.com) to receive the most current information on our products.

DS21733E-page 25

MCP6001/2/4

NOTES:

DS21733E-page 26

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,

PICSTART, PRO MATE, PowerSmart, rfPIC, and

SmartShunt are registered trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,

SmartSensor and The Embedded Control Solutions Company

are registered trademarks of Microchip Technology

Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, Migratable Memory, MPASM,

MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,

PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,

PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,

SmartTel and Total Endurance are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS21733E-page 27

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

India - Bangalore

Tel: 91-80-2229-0061

Fax: 91-80-2229-0062

Austria - Weis

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Denmark - Ballerup

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

France - Massy

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Japan - Kanagawa

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Germany - Ismaning

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Korea - Seoul

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Boston

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Westford, MA

Tel: 978-692-3848

Fax: 978-692-3821

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

England - Berkshire

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Dallas

Addison, TX

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Tel: 972-818-7423

Fax: 972-818-2924

Taiwan - Hsinchu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shunde

Detroit

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Qingdao

Tel: 86-532-502-7355

Fax: 86-532-502-7205

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

10/20/04

DS21733E-page 28


型号：	MCP6001RT-I/MS
厂家：	MICROCHIP
描述：	1 MHz, Low-Power Op Amp 1兆赫，低功耗运算放大器运算放大器
文件：	总28页 (文件大小：455K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP6001RT-I/MS [MICROCHIP]

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