MCP608I/P_技术文档

MCP606/7/8/9

2.5V to 5.5V Micropower CMOS Op Amps

Description

Features

The MCP606/7/8/9 family of operational amplifiers (op

amps) from Microchip Technology Inc. are unity-gain

stable with low offset voltage (250 µV, max.).

Performance characteristics include rail-to-rail output

swing capability and low input bias current (80 pA at

+85°C, max.). These features make this family of op

amps well suited for single-supply, precision, high-

impedance, battery-powered applications.

• Low Input Offset Voltage: 250 µV (max.)

• Rail-to-Rail Output

• Low Input Bias Current: 80 pA (max. at 85°C)

• Low Quiescent Current: 25 µA (max.)

• Power Supply Voltage: 2.5V to 5.5V

• Unity-Gain Stable

• Chip Select (CS) Capability: MCP608

• Industrial Temperature Range: -40°C to +85°C

• No Phase Reversal

The single MCP606 is available in standard 8-lead

PDIP, SOIC and TSSOP packages, as well as in a

SOT-23-5 package. The single MCP608 with Chip

Select (CS) is offered in standard 8-lead PDIP, SOIC

and TSSOP packages. The dual MCP607 is offered in

standard 8-lead PDIP, SOIC and TSSOP packages.

Finally, the quad MCP609 is offered in standard

14-lead PDIP, SOIC and TSSOP packages. All devices

are fully specified from -40°C to +85°C, with power

supplies from 2.5V to 5.5V.

• Available in Single, Dual and Quad Packages

Typical Applications

• Battery Power Instruments

• High-Impedance Applications

- Photodiode Amplifier

- pH Probe Buffer Amplifier

- Infrared Detectors

Package Types

- Precision Integrators

MCP606

PDIP, SOIC,TSSOP

MCP606

SOT-23-5

- Charge Amplifier for Piezoelectric

Transducers

NC 1

8

7

6

V_OUT

V_SS

V_IN+

1

5

NC

V_DD

• Strain Gauges

2

3

4

2

3

V_IN–

V_IN+

V_SS

V_DD

V_OUT

• Medical Instruments

• Test Equipment

4 V_IN–

5 NC

Available Tools

MCP607

PDIP, SOIC,TSSOP

MCP608

PDIP, SOIC,TSSOP

• SPICE Macro Models (at www.microchip.com)

• FilterLab^®Software (at www.microchip.com)

V_OUTA

V_INA

V_SS

1

2

3

4

8

7

6

NC 1

8

7

6

V_DD

CS

2

3

4

–

+

V_OUTBV_IN–

V_INB

V_DD

V_OUT

Typical Application

–

+

V_IN+

V_SS

5 V_INB

5 NC

I_L

MCP609

PDIP, SOIC,TSSOP

R_F

50 kΩ

R_G

5 kΩ

To Load

(V_LP

)

V_OUTA

1

2

3

4

5

6

7

14

13

12

V_OUTD

2.5V

to

5.5V

V_INA

–

+

V_IND

–

+

V_OUT

11 V_SS

V_DD

V_INB

MCP606

R_SEN

10Ω

To Load

10

9

+

–

V_INC

+

–

(V_LM

)

8 V_OUTC

V_OUTB

Low-Side Battery Current Sensor

DS11177D-page 1

MCP606/7/8/9

† Notice: Stresses above those listed under “Absolute

Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of

the device at those or any other conditions above those

indicated in the operational listings of this specification is not

implied. Exposure to maximum rating conditions for extended

periods may affect device reliability.

1.0

ELECTRICAL

CHARACTERISTICS

Absolute Maximum Ratings †

V

– V

.......................................................................7.0V

SS

DD

All Inputs and Outputs ................... V – 0.3V to V + 0.3V

SS

DD

Difference Input Voltage ...................................... |V – V

|

DD

SS

Output Short Circuit Current ..................................continuous

Current at Input Pins ....................................................±2 mA

Current at Output and Supply Pins ............................±30 mA

Storage temperature ....................................-65°C to +150°C

Maximum Junction Temperature (T ) .........................+150°C

J

ESD protection on all pins (HBM;MM) ...................2 kV; 200V

DC CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V = +2.5V to +5.5V, V = GND, T = +25°C, V

= V /2,

DD

SS

A

CM

V

≈ V /2 and R = 100 kΩ to V /2.

OUT

DD

L

DD

Parameters

Sym

Min

Typ

Max

Units

Conditions

Input Offset

Input Offset Voltage

V_OS

-250

—

±1.8

93

+250

—

µV

Input Offset Drift with Temperature

Power Supply Rejection Ratio

ΔV_OS/ΔT

µV/°C T = -40°C to +85°C

A

PSRR

80

—

dB

Input Bias Current and Impedance

Input Bias Current

I

—

1

—

1

—

80

—

pA

B

At Temperature

pA T = +85°C

B

A

Input Offset Bias Current

Common Mode Input Impedance

Differential Input Impedance

Common Mode

I

pA

OS

13

Z

10 ||6

Ω||pF

CM

13

Z

10 ||6

Ω||pF

DIFF

Common Mode Input Range

Common Mode Rejection Ratio

V

– 0.3

V

– 1.1

DD

V

CMRR ≥ 75 dB

CMR

SS

CMRR

75

91

—

dB

V

= 5V,

= -0.3V to 3.9V

DD

CM

Open-Loop Gain

DC Open-Loop Gain

(Large-signal)

A

105

100

121

118

—

dB R = 25 kΩ to V /2,

OL

L

DD

V

= 50 mV to V – 50 mV

OUT

DD

DC Open-Loop Gain

(Large-signal)

A

dB R = 5 kΩ to V /2,

OL

L

DD

V

= 0.1V to V – 0.1V

OUT

DD

Output

Maximum Output Voltage Swing

V

, V

V

+ 15

—

V

– 20

mV R = 25 kΩ to V /2,

L DD

OL

OH

SS

DD

0.5V output overdrive

V

+ 45

+ 50

– 60

– 50

mV R = 5 kΩ to V /2,

OL

OH

L

DD

0.5V output overdrive

Linear Output Voltage Range

Output Short Circuit Current

V

mV R = 25 kΩ to V /2,

OUT

L

DD

A

≥ 105 dB

OL

V

+ 100

V

– 100

mV R = 5 kΩ to V /2,

SS

DD

L

DD

A

V

≥ 100 dB

OL

I

—

7

—

mA

= 2.5V

SC

DD

I

17

—

= 5.5V

SC

Power Supply

Supply Voltage

V

2.5

—

5.5

25

V

DD

Quiescent Current per Amplifier

I

18.7

µA

I = 0

O

Q

DS11177D-page 2

MCP606/7/8/9

AC CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V = +2.5V to +5.5V, V = GND, T = 25°C, V

= V /2,

DD

SS

A

CM

V

≈ V /2, R = 100 kΩ to V /2 and C = 60 pF.

OUT

DD

L

DD

L

Parameters

Sym

Min

Typ

Max

Units

Conditions

AC Response

Gain Bandwidth Product

Phase Margin

GBWP

PM

—

155

62

—

kHz

°

G = +1

G = 1

Slew Rate

SR

0.08

V/µs

Noise

Input Noise Voltage

Input Noise Voltage Density

Input Noise Current Density

E

e

—

2.8

38

3

—

µV

f = 0.1 Hz to 10 Hz

ni

P-P

nV/√Hz f = 1 kHz

fA/√Hz f = 1 kHz

ni

i

ni

MCP608 CHIP SELECT (CS) CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V = +2.5V to +5.5V, V = GND, T = 25°C, V

= V /2,

DD

SS

A

CM

V

≈ V /2, R = 100 kΩ to V /2 and C = 60 pF.

DD L DD L

OUT

Parameters

Sym

Min

Typ

Max

Units

Conditions

CS Low Specifications

CS Logic Threshold, Low

CS Input Current, Low

V

—

0.2 V

—

V

IL

SS

DD

I

-0.1

0.01

µA

CS = 0.2V

DD

CSL

CS High Specifications

CS Logic Threshold, High

CS Input Current, High

CS Input High, GND Current

V

0.8 V

—

0.01

-0.05

10

V

DD

V

IH

DD

I

0.1

—

µA

nA

CS = V

CSH

DD

I

-2

SS

O(LEAK)

Amplifier Output Leakage, CS High

CS Dynamic Specifications

I

—

CS Low to Amplifier Output Turn-on Time

t

—

9

100

—

µs

V

CS = 0.2V to V

= 0.9(V /2),

OUT DD

ON

DD

G = +1 V/V, R = 1 kΩ to V

L

SS

CS High to Amplifier Output Hi-Z

CS Hysteresis

t

0.1

0.6

CS = 0.8V to V

= 0.1(V /2),

OUT DD

OFF

DD

G = +1 V/V, R = 1 kΩ to V

L

SS

V

—

V

= 5.0V

HYST

DD

V_IH

V_IL

CS

V_OUT

I_SS

t_OFF

t_ON

Hi-Z

-18.7 µA (typ.)

-50 nA (typ.)

I_CS

FIGURE 1-1:

Timing Diagram for the CS

Pin on the MCP608.

DS11177D-page 3

MCP606/7/8/9

TEMPERATURE CHARACTERISTICS

Electrical Characteristics: Unless otherwise indicated, V = +2.5V to +5.5V and V = GND.

DD

SS

Parameters

Temperature Ranges

Sym

Min

Typ

Max

Units

Conditions

Specified Temperature Range

Operating Temperature Range

Storage Temperature Range

Thermal Package Resistances

Thermal Resistance, 5L-SOT23

Thermal Resistance, 8L-PDIP

Thermal Resistance, 8L-SOIC

Thermal Resistance, 8L-TSSOP

Thermal Resistance, 14L-PDIP

Thermal Resistance, 14L-SOIC

Thermal Resistance, 14L-TSSOP

T

-40

-65

—

+85

+125

+150

°C

A

T

Note 1

A

T

A

θ

—

256

85

—

°C/W

JA

163

124

70

120

100

Note 1: The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the

Junction Temperature (T ) must not exceed the Absolute Maximum specification of +150°C.

J

DS11177D-page 4

MCP606/7/8/9

2.0

TYPICAL PERFORMANCE CURVES

Note:

The graphs and tables provided following this note are a statistical summary based on a limited number of

samples and are provided for informational purposes only. The performance characteristics listed herein

are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified

operating range (e.g., outside specified power supply range) and therefore outside the warranted range.

Note: Unless otherwise indicated, V_DD= +2.5V to +5.5V, V_SS= GND, T_A= 25°C, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 100 kΩ to V_DD/2 and C_L= 60 pF.

25%

20%

15%

10%

5%

16%

14%

12%

10%

8%

1200 Samples

V_DD= 5.5V

1200 Samples

_DD= 5.5V

V

6%

4%

2%

0%

Input Offset Voltage (µV)

Input Offset Voltage Drift Magnitude (µV/°C)

FIGURE 2-1:

Input Offset Voltage at

FIGURE 2-4:

Input Offset Voltage Drift

V_DD= 5.5V.

Magnitude at V_DD= 5.5V.

16%

25%

20%

15%

10%

5%

1200 Samples

_DD= 2.5V

1200 Samples

V_DD= 2.5V

14%

12%

10%

8%

V

6%

4%

2%

0%

Input Offset Voltage (µV)

Input Offset Voltage Drift Magnitude (µV/°C)

FIGURE 2-2:

Input Offset Voltage at

FIGURE 2-5:

Input Offset Voltage Drift

V_DD= 2.5V.

Magnitude at V_DD= 2.5V.

24

22

20

18

16

14

12

22

20

18

16

14

12

10

8

6

4

2

0

V_DD= 5.5V

V_DD= 2.5V

T_A= +85°C

T_A= +25°C

T_A= -40°C

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Power Supply Voltage (V)

-50

-25

0

25

50

75

100

Ambient Temperature (°C)

FIGURE 2-3:

Quiescent Current vs.

FIGURE 2-6:

Quiescent Current vs.

Power Supply Voltage.

Ambient Temperature.

DS11177D-page 5

MCP606/7/8/9

Note: Unless otherwise indicated, V_DD= +2.5V to +5.5V, V_SS= GND, T_A= 25°C, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 100 kΩ to V_DD/2 and C_L= 60 pF.

120

100

80

60

40

20

0

500

400

300

200

100

0

V_DD= 5.5V

V_DD=2.5V

V_DD= 5.5V

T_A= +85°C

T_A= +25°C

T_A= -40°C

Representative Part

-20

-50

-25

0

25

50

75

100

Ambient Temperature (°C)

Common Mode Input Voltage (V)

FIGURE 2-7:

Input Offset Voltage vs.

FIGURE 2-10:

Input Offset Voltage vs.

Ambient Temperature.

Common Mode Input Voltage.

120

100

80

60

40

20

0

90

160

80

70

60

50

40

30

20

10

0

R_L= 25 kΩ

140

120

100

80

GBWP

45

0

Phase Margin

Gain

-45

-90

-135

-180

-225

Phase

60

40

20

V_DD= 5.0V

0

-20

0.01 0.1

-50 -25

0

25

50

75 100

1

10 100 1k 10k 100k 1M

Frequency (Hz)

Ambient Temperature (°C)

FIGURE 2-8:

Open-Loop Gain and Phase

FIGURE 2-11:

Gain Bandwidth Product,

vs. Frequency.

Phase Margin vs. Ambient Temperature.

1000

140

130

120

110

100

90

100

Referred to Input

80

10

0.1

100 1k

10k

1.E+04

100k

1.E+05

1

10 100 1k

F1reque2ncy (Hz3)

10k 100k

1.E- 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0 1.E+0

1.E+02 1.E+03

Frequency (Hz)

01

0

4

5

FIGURE 2-9:

Channel-to-Channel

FIGURE 2-12:

Input Noise Voltage Density

Separation (MCP607 and MCP609 only).

vs. Frequency.

DS11177D-page 6

MCP606/7/8/9

Note: Unless otherwise indicated, V_DD= +2.5V to +5.5V, V_SS= GND, T_A= 25°C, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 100 kΩ to V_DD/2 and C_L= 60 pF.

100

10

1

60

50

40

30

20

10

0

V_DD= 5.5V

_CM= V_DD

T_A= +85°C

_DD= 5.5V

V

I_B

I_OS

| I_OS

|

0.1

-10

25 30 35 40 45 50 55 60 65 70 75 80 85

Ambient Temperature (°C)

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

Common Mode Input Voltage (V)

FIGURE 2-13:

Input Bias Current, Input

FIGURE 2-16:

Input Bias Current, Input

Offset Current vs. Ambient Temperature.

Offset Current vs. Common Mode Input Voltage.

135

130

125

150

R_L= 25 kΩ

140

130

120

110

100

120

115

110

105

100

V_DD= 5.5V

V_DD= 2.5V

90

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

100

1k

1.E+03

10k

100k

1.E+05

1.E+02

1.E+04

Power Supply Voltage (V)

Load Resistance (Ω)

FIGURE 2-14:

DC Open-Loop Gain vs.

FIGURE 2-17:

DC Open-Loop Gain vs.

Load Resistance.

Power Supply Voltage.

120

100

80

60

40

20

0

100

95

90

85

80

75

PSRR-

PSRR+

PSRR

CMRR

-50

-25

0

25

50

75

100

0.1

1

10

100

1k

10k

1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04

Frequency (Hz)

Ambient Temperature (°C)

FIGURE 2-15:

Frequency.

CMRR, PSRR vs.

FIGURE 2-18:

Temperature.

CMRR, PSRR vs. Ambient

DS11177D-page 7

MCP606/7/8/9

Note: Unless otherwise indicated, V_DD= +2.5V to +5.5V, V_SS= GND, T_A= 25°C, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 100 kΩ to V_DD/2 and C_L= 60 pF.

40

35

30

25

20

15

10

5

1000

100

10

V_DD– V_OH, V_DD= 5.5V

_OL– V_SS, V_DD= 5.5V

V_DD- V_OH, V_DD= 2.5V

V_OL- V_SS, V_DD= 2.5V

V

R_L= 5 kΩ

V_DD- V_OH, V_DD= 5.5V

V_OL- V_SS, V_DD= 5.5V

V_DD– V_OH, V_DD= 2.5V

V_OL– V_SS, V_DD= 2.5V

1

0

0.1

1

10

100

-50

-25

0

25

50

75

100

Output Current (mA)

Ambient Temperature (°C)

FIGURE 2-19:

Output Voltage Headroom

FIGURE 2-22:

Output Voltage Headroom

vs. Output Current Magnitude.

vs. Ambient Temperature at R_L= 5 kΩ.

10

6

G = +2 V/V

V

_DD= 5.0V

5

4

V_DD= 5.5V

V_DD= 2.5V

3

1

2

V_IN

1

V_OUT

0

0.1

-1

100

1k

1.E+03

10k

1.E+04

100k

1.E+05

1.E+02

Frequency (Hz)

Time (100 µs/div)

FIGURE 2-20:

Maximum Output Voltage

FIGURE 2-23:

The MCP606/7/8/9 Show

Swing vs. Frequency.

No Phase Reversal.

0.12

25

20

15

10

+I_SC, V_DD= 5.5V

| -I_SC|, V_DD= 5.5V

0.10

0.08

0.06

0.04

0.02

0.00

Low to High

High to Low

5

0

+I_SC, V_DD= 2.5V

| -I_SC|, V_DD= 2.5V

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Ambient Temperature (°C)

FIGURE 2-21:

Slew Rate vs. Ambient

FIGURE 2-24:

Output Short Circuit Current

Temperature.

Magnitude vs. Ambient Temperature.

DS11177D-page 8

MCP606/7/8/9

Note: Unless otherwise indicated, V_DD= +2.5V to +5.5V, V_SS= GND, T_A= 25°C, V_CM= V_DD/2, V_OUT≈ V_DD/2,

R_L= 100 kΩ to V_DD/2 and C_L= 60 pF.

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

V_DD= 5.0V

Time (50 µs/div)

FIGURE 2-25:

Large-signal, Non-inverting

FIGURE 2-28:

Large-signal, Inverting

Pulse Response.

V_DD= 5.0V

R_L= 25 kΩ

Time (50 µs/div)

FIGURE 2-26:

Small-signal, Non-inverting

FIGURE 2-29:

Small-signal, Inverting Pulse

Pulse Response.

Response.

3.5

3.0

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

15

V_DD= 5.0V

G = +1 V/V

10

Amplifier Output Active

R_L= 1 kΩ to V_SS

5

2.5

2.0

1.5

1.0

0.5

0.0

-0.5

CS

0

CS Input

High to Low

CS Input

Low to High

-5

Output Enabled

-10

-15

-20

V_OUT

Hysteresis

1.0

-25

Output

Hi-Z

Output

Hi-Z

Amplifier Output Hi-Z

0.5

0.0

-30

-35

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

CS Input Voltage (V)

Time (5 µs/div)

FIGURE 2-27:

Chip Select (CS) Hysteresis

FIGURE 2-30:

Amplifier Output Response

(MCP608 only).

Times vs. Chip Select (CS) Pulse

(MCP608 only).

DS11177D-page 9

MCP606/7/8/9

3.0

PIN DESCRIPTIONS

Descriptions of the pins are listed in Table 3-1.

TABLE 3-1:

PIN FUNCTION TABLE.

MCP606

(PDIP, SOIC,

TSSOP)

MCP607 MCP608 MCP609

Symbol

Description

(SOT-23-5)

6

2

1

2

6

2

1

2

V_OUT, V_OUTAOutput (op amp A)

4

V_IN–, V_INA

V_IN+, V_INA

V_DD

–

Inverting Input (op amp A)

Non-inverting Input (op amp A)

Positive Power Supply

Non-inverting Input (op amp B)

Inverting Input (op amp B)

Output (op amp B)

3

+

7

5

4

7

4

—

4

—

2

5

—

4

5

V_INB

+

6

–

7

V_OUTB

V_OUTC

—

8

Output (op amp B)

9

V_INC

–

+

Inverting Input (op amp C)

Non-inverting Input (op amp C)

Negative Power Supply

Non-inverting Input (op amp D)

Inverting Input (op amp D)

Output (op amp D)

10

11

12

13

14

—

V_INC

V_SS

—

1, 5, 8

—

8

V_IND+

V_IND–

V_OUTD

CS

Chip Select

1, 5

NC

No Internal Connection

3.1

Analog Outputs

3.4

Digital Input

The output pins are low-impedance voltage sources.

The Chip Select (CS) pin is a Schmitt-triggered, CMOS

logic input. It is used to place the MCP608 op amp in a

Low-power mode, with the output(s) in a Hi-Z state.

3.2

Analog Inputs

The non-inverting and inverting inputs are high-

impedance CMOS inputs with low bias currents.

3.3

Power Supply (V and V

)

DD

SS

The positive power supply pin (V_DD) is 2.5V to 5.5V

higher than the negative power supply pin (V_SS). For

normal operation, the output pins are at voltages

between V_SSand V_DD; while the input pins are at

voltages between V_SS– 0.3V and V_DD+ 0.3V.

Typically, these parts are used in a single-supply

(positive) configuration. In this case, V_SSis connected

to ground and V_DDis connected to the supply. V_DDwill

need a local bypass capacitor (typically 0.01 µF to

0.1 µF) within 2 mm of the V_DDpin. These parts can

share a bulk capacitor with nearby analog parts

(typically 1 µF or larger) within 100 mm of the V_DDpin.

DS11177D-page 10

MCP606/7/8/9

linear region. To verify linear operation in this range, the

large-signal DC Open-Loop Gain (A_OL) is measured at

points inside the supply rails. The measurement must

meet the specified A_OLconditions in the specification

table.

4.0

APPLICATIONS INFORMATION

The MCP606/7/8/9 family of op amps is manufactured

using Microchip’s state-of-the-art CMOS process

These op amps are unity-gain stable and suitable for a

wide range of general purpose applications.

4.3

Capacitive Loads

4.1

Inputs

Driving large capacitive loads can cause stability

problems for voltage-feedback op amps. As the load

capacitance increases, the feedback loop’s phase

margin decreases and the closed-loop bandwidth is

reduced. This produces gain-peaking in the frequency

response, with overshoot and ringing in the step

response. A unity-gain buffer (G = +1) is the most

sensitive to capacitive loads, though all gains show the

same general behavior.

The MCP606/7/8/9 op amps are designed to prevent

phase reversal when the input pins exceed the supply

voltages. Figure 2-23 shows the input voltage

exceeding the supply voltage without any phase rever-

sal.

The inputs of the MCP606/7/8/9 op amps connect to a

differential PMOS input stage. The Common Mode

Input Voltage Range (V_CMR) includes ground in single-

supply systems (V_SS), but does not include V_DD. This

means that the amplifier input behaves linearly as long

as the Common Mode Input Voltage (V_CM) is kept within

the specified V_CMRlimits (V_SS– 0.3V to V_DD– 1.1V at

+25°C).

When driving large capacitive loads with these op

amps (e.g., > 60 pF when G = +1), a small series

resistor at the output (R_ISOin Figure 4-2) improves the

feedback loop’s phase margin (stability) by making the

output load resistive at higher frequencies. The

bandwidth will be generally lower than the bandwidth

with no capacitive load.

Input voltages that exceed the Absolute Maximum

Voltage Range (V_SS– 0.3V to V_DD+ 0.3V) can cause

excessive current to flow into or out of the input pins.

Current beyond ±2 mA can cause reliability problems.

Applications that exceed this rating must be externally

limited with a resistor, as shown in Figure 4-1.

R_ISO

V_OUT

MCP60X

V_IN

C_L

V_OUT

MCP60X

R_IN

FIGURE 4-2:

Output Resistor, R_ISO

V_IN

stabilizes large capacitive loads.

Figure 4-3 gives recommended R_ISOvalues for

different capacitive loads and gains. The x-axis is the

normalized load capacitance (C_L/G_N), where G_Nis the

circuit’s noise gain. For non-inverting gains, G_Nand the

Signal Gain are equal. For inverting gains, G_Nis

1+|Signal Gain| (e.g., -1 V/V gives G_N= +2 V/V).

(Maximum expected V_IN) – V_DD

------------------------------------------------------------------------------

2 mA

R_IN

≥

V_SS– (Minimum expected V_IN

)

---------------------------------------------------------------------------

2 mA

R_IN

≥

FIGURE 4-1:

Resistor (R_IN).

Input Current-Limiting

10000

10k

4.2

Rail-to-Rail Output

There are two specifications that describe the output-

swing capability of the MCP606/7/8/9 family of op amps.

The first specification (Maximum Output Voltage Swing)

defines the absolute maximum swing that can be

achieved under the specified load conditions. For

instance, the output voltage swings to within 15 mV of

the negative rail with a 25 kΩ load to V_DD/2. Figure 2-23

shows how the output voltage is limited when the input

goes beyond the linear region of operation.

1000

1k

G_N= +1

G

_N= +2

G_Nt +4

100

10

100

1000

10000

10p

100p

1n

10n

Normalized Load Capacitance; C_L/G_N(F)

FIGURE 4-3:

for Capacitive Loads.

Recommended R_ISOValues

The second specification that describes the output-

swing capability of these amplifiers (Linear Output

Voltage Range) defines the maximum output swing that

can be achieved while the amplifier still operates in its

DS11177D-page 11

MCP606/7/8/9

After selecting R_ISOfor your circuit, double-check the

resulting frequency response peaking and step

response overshoot. Modify R_ISO’s value until the

response is reasonable. Bench evaluation and simula-

tions with the MCP606/7/8/9 SPICE macro model are

helpful.

1. Non-inverting Gain and Unity-gain Buffer:

a) Connect the non-inverting pin (V_IN+) to the

input with a wire that does not touch the

PCB surface.

b) Connect the guard ring to the inverting input

pin (V_IN–). This biases the guard ring to the

common mode input voltage.

4.4

MCP608 Chip Select (CS)

2. Inverting Gain and Transimpedance Gain

(convert current to voltage, such as photo

detectors) amplifiers:

The MCP608 is a single op amp with Chip Select (CS).

When CS is pulled high, the supply current drops to

50 nA (typ.) and flows through the CS pin to V_SS. When

this happens, the amplifier output is put into a high-

impedance state. By pulling CS low, the amplifier is

enabled. If the CS pin is left floating, the amplifier may

not operate properly. Figure 1-1 shows the output

voltage and supply current response to a CS pulse.

a) Connect the guard ring to the non-inverting

input pin (V_IN+). This biases the guard ring

to the same reference voltage as the op

amp (e.g., V_DD/2 or ground).

b) Connect the inverting pin (V_IN–) to the input

with a wire that does not touch the PCB

surface.

4.5

Supply Bypass

4.7

Application Circuits

With this family of operational amplifiers, the power

supply pin (V_DDfor single-supply) should have a local

bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm

for good high-frequency performance. It also needs a

bulk capacitor (i.e., 1 µF or larger) within 100 mm to

provide large, slow currents. This bulk capacitor can be

shared with other nearby analog parts.

4.7.1

LOW-SIDE BATTERY CURRENT

SENSOR

The MCP606/7/8/9 op amps can be used to sense the

load current on the low-side of a battery using the

circuit in Figure 4-5. In this circuit, the current from the

power supply (minus the current required to power the

MCP606) flows through a sense resistor (R_SEN), which

converts it to voltage. This is gained by the the amplifier

and resistors, R_Gand R_F.Since the non-inverting input

of the amplifier is at the load’s negative supply (V_LM),

the gain from R_SENto V_OUTis R_F/R_G.

4.6

PCB Surface Leakage

In applications where low input bias current is critical,

Printed Circuit Board (PCB) surface-leakage effects

need to be considered. Surface leakage is caused by

humidity, dust or other contamination on the board.

Under low humidity conditions, a typical resistance

between nearby traces is 10¹²Ω. A 5V difference would

cause 5 pA of current to flow, which is greater than the

MCP606/7/8/9 family’s bias current at 25°C (1 pA, typ.).

V_OUT= V_LM+ I R

(R ⁄ R_G)

F

L

SEN

I_L

The easiest way to reduce surface leakage is to use a

guard ring around sensitive pins (or traces). The guard

ring is biased at the same voltage as the sensitive pin.

An example of this type of layout is shown in Figure 4-4.

R_F

50 kΩ

R_G

5 kΩ

To Load

(V_LP

)

2.5V

to

5.5V

V_OUT

MCP606

R_SEN

To Load

V_IN-

V_IN+

V_SS

10Ω

(V_LM

)

FIGURE 4-5:

Low Side Battery Current

Sensor.

Since the input bias current and input offset voltage of

the MCP606 are low, and the input is capable of swing-

ing below ground, there is very little error generated by

the amplifier. The quiescent current is very low, which

helps conserve battery power. The rail-to-rail output

makes it possible to read very low currents.

Guard Ring

FIGURE 4-4:

Example Guard Ring Layout

for Inverting Gain.

DS11177D-page 12

MCP606/7/8/9

operate at a much higher speed. This reverse bias also

increases the dark current and current noise, however.

Resistor R₂converts the current into voltage. Capacitor

C₂limits the bandwidth and helps stabilize the circuit

when D₁’s junction capacitance is large.

4.7.2

PHOTODIODE AMPLIFIERS

Sensors that produce an output current and have high

output impedance can be connected to a transimped-

ance amplifier. The transimpedance amplifier converts

the current into voltage. Photodiodes are one sensor

that produce an output current.

V_B< 0

The key op amp characteristics that are needed for

these circuits are: low input offset voltage, low input

bias current, high input impedance and an input

common mode range that includes ground. The low

input offset voltage and low input bias current support

a very low voltage drop across the photodiode; this

gives the best photodiode linearity. Since the

photodiode is biased at ground, the op amp’s input

needs to function well both above and below ground.

V_OUT= I

R

D1

2

C₂

R₂

V_OUT

I_D1

V_DD

Light

4.7.2.1

Photo-Voltaic Mode

D₁

MCP606

Figure 4-6 shows a transimpedance amplifier with a

photodiode (D₁) biased in the Photo-voltaic mode (0V

across D₁), which is used for precision photodiode

sensing.

VB

As light impinges on D₁, charge is generated, causing

a current to flow in the reverse bias direction of D₁. The

op amp’s negative feedback forces the voltage across

the D₁to be nearly 0V. Resistor R₂converts the current

into voltage. Capacitor C₂limits the bandwidth and

helps stabilize the circuit when D₁’s junction

capacitance is large.

FIGURE 4-7:

conductive mode) and Transimpedance

Amplifier.

Photodiode (in Photo-

4.7.3

TWO OP AMP INSTRUMENTATION

AMPLIFIER

The two op amp instrumentation amplifier shown in

Figure 4-8 serves the function of taking the difference

of two input voltages, level-shifting it and gaining it to

the output. This configuration is best suited for higher

V_OUT= I

R

D1

2

C₂

R₂

gains (i.e., gain > 3 V/V). The reference voltage (V_REF

)

is typically at mid-supply (V_DD/2) in a single-supply

environment.

V_OUT

I_D1

R

2R

⎛

⎞

1

V_DD

Light

V

= (V – V ) 1 + ------ + --------- + V

⎜

⎟

OUT

1

2

REF

R

⎝

⎠

2

G

D₁

MCP606

R_G

R₁

R₂

R₁

V_REF

V_OUT

FIGURE 4-6:

Photodiode (in Photo-voltaic

mode) and Transimpedance Amplifier.

V₂

V₁

½

MCP607

4.7.2.2 Photo-Conductive Mode

Figure 4-6 shows a transimpedance amplifier with a

photodiode (D₁) biased in the Photo-conductive mode

(D₁is reverse biased), which is used for high-speed

applications.

FIGURE 4-8:

Amplifier.

Two op amp Instrumentation

The key specifications that make the MCP606/7/8/9

family appropriate for this application circuit are low

input bias current, low offset voltage and high common-

mode rejection.

As light impinges on D₁, charge is generated, causing

a current to flow in the reverse bias direction of D₁.

Placing a negative bias on D₁significantly reduces its

junction capacitance, which allows the circuit to

DS11177D-page 13

MCP606/7/8/9

4.7.4

THREE OP AMP

INSTRUMENTATION AMPLIFIER

4.7.5

PRECISION GAIN WITH GOOD

LOAD ISOLATION

A classic, three op amp instrumentation amplifier is

illustrated in Figure 4-9. The two input op amps provide

differential signal gain and a common mode gain of +1.

The output op amp is a difference amplifier, which

converts its input signal from differential to a single

ended output; it rejects common mode signals at its

input. The gain of this circuit is simply adjusted with one

resistor (R_G). The reference voltage (V_REF) is typically

referenced to mid-supply (V_DD/2) in single-supply

applications.

In Figure 4-10, the MCP606 op amps, R₁and R₂

provide a high gain to the input signal (V_IN). The

MCP606’s low offset voltage makes this an accurate

circuit.

The MCP601 is configured as a unity-gain buffer. It

isolates the MCP606’s output from the load, increasing

the high-gain stage’s precision. Since the MCP601 has

a higher output current, with the two amplifiers being

housed in separate packages, there is minimal change

in the MCP606’s offset voltage due to loading effect.

R

⎞

4

2R

⎛

⎞ ⎛

⎟ ⎜

⎠ ⎝

2

V

= V (1 + R ⁄ R )

IN 2 1

-----

+ V

⎟

V

= (V – V ) 1 + ---------

⎜

OUT

1

2

REF

R

⎝

⎠

3

G

MCP606

V_IN

½

MCP601

MCP607

V₂

V_OUT

R₃

R₄

R₁

R₂

V_OUT

R₂

R_G

R₂

FIGURE 4-10:

Load Isolation.

Precision Gain with Good

MCP606

V_REF

R₃

R₄

V₁

½

MCP607

FIGURE 4-9:

Three op amp

Instrumentation Amplifier.

DS11177D-page 14

MCP606/7/8/9

5.0 DESIGN TOOLS

Microchip provides the basic design tools needed for

the MCP606/7/8/9 family of op amps.

5.1

SPICE Macro Model

The latest SPICE macro model for the MCP606/7/8/9

op amps is available on our web site at

www.microchip.com. This model is intended to be an

initial design tool that works well in the op amp’s linear

region of operation at room temperature. See the

model file for information on its capabilities.

Bench testing is a very important part of any design and

cannot be replaced with simulations. Also, simulation

results using this macro model need to be validated by

comparing them to the data sheet specifications and

characteristic curves.

®

5.2

FilterLab Software

The FilterLab software is an innovative tool that

simplifies analog active-filter (using op amps) design. It

is available free of charge from our web site at

www.microchip.com. The FilterLab software tool

provides full schematic diagrams of the filter circuit with

component values. It also outputs the filter circuit in

SPICE format, which can be used with the macro

model to simulate actual filter performance.

DS11177D-page 15

MCP606/7/8/9

6.0

6.1

PACKAGING INFORMATION

Package Marking Information

5-Lead SOT-23-5

Example:

XXNN

SB25

8-Lead PDIP (300 mil)

Example:

XXXXXXXX

XXXXXNNN

MCP606

I/P^^256

e3

YYWW

0545

8-Lead SOIC (150 mil)

Example:

MCP606

XXXXXXXX

XXXXYYWW

e

3

SN^^0545

NNN

256

8-Lead TSSOP

Example:

XXXX

YYWW

606

I545

NNN

256

Legend: XX...X Customer-specific information

Y

YY

Year code (last digit of calendar year)

Year code (last 2 digits of calendar year)

WW

NNN

Week code (week of January 1 is week ‘01’)

Alphanumeric traceability code

e

3

Pb-free JEDEC designator for Matte Tin (Sn)

*

This package is Pb-free. The Pb-free JEDEC designator (

can be found on the outer packaging for this package.

)

e3

Note: In the event the full Microchip part number cannot be marked on one line, it will

be carried over to the next line, thus limiting the number of available

characters for customer-specific information.

DS11177D-page 16

MCP606/7/8/9

Package Marking Information (Continued)

14-Lead PDIP (300 mil) (MCP609)

Example:

XXXXXXXXXXXXXX

XXXXXXXXXXXNNN

MCP609

e

3

I/P^^256

YYWW

0545

14-Lead SOIC (150 mil) (MCP609)

Example:

XXXXXXXXXX

YYWWNNN

MCP609

e

3

I/SL^^

0545256

Example:

14-Lead TSSOP (MCP609)

XXXXXXXX

YYWW

609IST

0545

NNN

256

DS11177D-page 17

MCP606/7/8/9

5-Lead Plastic Small Outline Transistor (OT) (SOT23)

E

E1

p

B

p1

D

n

1

α

c

A

A2

φ

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

5

MAX

n

p

Number of Pins

5

Pitch

.038

.075

.046

.043

.003

.110

.064

.116

.018

5

0.95

1.90

p1

Outside lead pitch (basic)

Overall Height

A

A2

A1

E

.035

.000

.102

.059

.110

.014

0

.057

0.90

1.18

1.10

0.08

2.80

1.63

2.95

0.45

5

1.45

Molded Package Thickness

.051

.006

.118

.069

.122

.022

10

1.30

0.15

3.00

1.75

3.10

0.55

10

Standoff

§

0.00

2.60

1.50

2.80

0.35

0

Overall Width

Molded Package Width

Overall Length

E1

D

Foot Length

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.004

.014

0

.006

.017

5

.008

.020

10

0.09

0.35

0

0.15

0.43

5

0.20

0.50

10

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MO-178

Drawing No. C04-091

DS11177D-page 18

MCP606/7/8/9

8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

β

B1

B

p

eB

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.100

.155

.130

2.54

3.94

3.30

Top to Seating Plane

A

.140

.170

3.56

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.360

.125

.008

.045

.014

.310

5

.145

2.92

0.38

7.62

6.10

9.14

3.18

0.20

1.14

0.36

7.87

5

3.68

.313

.250

.373

.130

.012

.058

.018

.370

10

.325

.260

.385

.135

.015

.070

.022

.430

15

7.94

6.35

9.46

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

9.78

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-018

DS11177D-page 19

MCP606/7/8/9

8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

h

α

45°

c

A2

A

φ

β

L

A1

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

8

MAX

n

p

Number of Pins

Pitch

8

.050

.061

.056

.007

.237

.154

.193

.015

.025

4

1.27

Overall Height

A

.053

.069

1.35

1.32

1.55

1.42

0.18

6.02

3.91

4.90

0.38

0.62

4

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.146

.189

.010

.019

0

.061

.010

.244

.157

.197

.020

.030

8

1.55

0.25

6.20

3.99

5.00

0.51

0.76

8

§

0.10

5.79

3.71

4.80

0.25

0.48

0

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.013

0

.009

.017

12

.010

.020

15

0.20

0.33

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-057

DS11177D-page 20

MCP606/7/8/9

8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

A1

A2

φ

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

8

.026

0.65

Overall Height

A

.043

1.10

Molded Package Thickness

Standoff

A2

A1

E

.033

.035

.004

.251

.173

.118

.024

4

.037

.006

.256

.177

.122

.028

8

0.85

0.90

0.10

6.38

4.40

3.00

0.60

4

0.95

0.15

6.50

4.50

3.10

0.70

8

§

.002

.246

.169

.114

.020

0

0.05

6.25

4.30

2.90

0.50

0

Overall Width

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-086

DS11177D-page 21

MCP606/7/8/9

14-Lead Plastic Dual In-line (P) – 300 mil (PDIP)

E1

D

2

n

1

α

E

A2

A

L

c

A1

B1

β

eB

p

B

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

14

.100

.155

.130

2.54

Top to Seating Plane

A

.140

.170

3.56

2.92

0.38

7.62

6.10

18.80

3.18

0.20

1.14

0.36

7.87

5

3.94

3.30

4.32

Molded Package Thickness

Base to Seating Plane

Shoulder to Shoulder Width

Molded Package Width

Overall Length

A2

A1

E

.115

.015

.300

.240

.740

.125

.008

.045

.014

.310

5

.145

3.68

.313

.250

.750

.130

.012

.058

.018

.370

10

.325

.260

.760

.135

.015

.070

.022

.430

15

7.94

6.35

19.05

3.30

0.29

1.46

0.46

9.40

10

8.26

6.60

19.30

3.43

0.38

1.78

0.56

10.92

15

E1

D

Tip to Seating Plane

Lead Thickness

L

c

Upper Lead Width

B1

B

Lower Lead Width

Overall Row Spacing

Mold Draft Angle Top

Mold Draft Angle Bottom

§

eB

α

β

5

10

15

5

10

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-001

Drawing No. C04-005

DS11177D-page 22

MCP606/7/8/9

14-Lead Plastic Small Outline (SL) – Narrow, 150 mil (SOIC)

E

E1

p

D

2

B

n

1

α

h

45°

c

A2

A

φ

A1

L

β

Units

INCHES*

NOM

MILLIMETERS

Dimension Limits

MIN

MAX

MIN

NOM

MAX

n

p

Number of Pins

Pitch

14

.050

.061

.056

.007

.236

.154

.342

.015

.033

4

1.27

1.55

1.42

0.18

5.99

3.90

8.69

0.38

0.84

4

Overall Height

A

.053

.069

1.35

1.75

Molded Package Thickness

Standoff

A2

A1

E

.052

.004

.228

.150

.337

.010

.016

0

.061

.010

.244

.157

.347

.020

.050

8

1.32

0.10

5.79

3.81

8.56

0.25

0.41

0

1.55

0.25

6.20

3.99

8.81

0.51

1.27

8

§

Overall Width

Molded Package Width

Overall Length

E1

D

Chamfer Distance

Foot Length

h

L

φ

Foot Angle

c

Lead Thickness

Lead Width

.008

.014

0

.009

.017

12

.010

.020

15

0.20

0.36

0

0.23

0.42

12

0.25

0.51

15

B

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

12

15

0

12

15

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.010” (0.254mm) per side.

JEDEC Equivalent: MS-012

Drawing No. C04-065

DS11177D-page 23

MCP606/7/8/9

14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP)

E

E1

p

D

2

1

n

B

α

A

c

φ

A1

A2

β

L

Units

INCHES

NOM

MILLIMETERS*

Dimension Limits

MIN

MAX

MIN

NOM

14

MAX

n

p

Number of Pins

Pitch

14

.026

0.65

Overall Height

A

.043

1.10

0.95

0.15

6.50

4.50

5.10

0.70

8

Molded Package Thickness

Standoff

A2

A1

E

.033

.002

.246

.169

.193

.020

0

.035

.004

.251

.173

.197

.024

4

.037

.006

.256

.177

.201

.028

8

0.85

0.05

0.90

0.10

6.38

4.40

5.00

0.60

4

§

Overall Width

6.25

4.30

4.90

0.50

0

Molded Package Width

Molded Package Length

Foot Length

E1

D

L

φ

Foot Angle

c

Lead Thickness

.004

.007

0

.006

.010

5

.008

.012

10

0.09

0.19

0

0.15

0.25

5

0.20

0.30

10

Lead Width

B1

α

β

Mold Draft Angle Top

Mold Draft Angle Bottom

0

5

10

0

5

10

* Controlling Parameter

§ Significant Characteristic

Notes:

Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed

.005” (0.127mm) per side.

JEDEC Equivalent: MO-153

Drawing No. C04-087

DS11177D-page 24

MCP606/7/8/9

APPENDIX A: REVISION HISTORY

Revision D (February 2005)

The following is the list of modifications:

1. Added Section 3.0 “Pin Descriptions”.

2. Updated Section 4.0 “Applications Information”.

3. Added Section 4.3 “Capacitive Loads”

4. Updated Section 5.0 “Design Tools” to

include FilterLab^®and to point to the latest

SPICE macro model.

5. Corrected and updated Section 6.0 “Packaging

Information”.

6. Added Section Appendix A: “Revision History”.

Revision C (January 2001)

Revision B (May 2000)

Revision A (January 2000)

• Original Release of this Document.

DS11177D-page 25

MCP606/7/8/9

NOTES:

DS11177D-page 26

MCP606/7/8/9

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Examples:

PART NO.

Device

X

/XX

a)

b)

c)

MCP606-I/P:

Industrial Temperature,

8LD PDIP package.

Temperature Package

Range

MCP606-I/SN: Industrial Temperature,

8LD SOIC package.

MCP606T-I/SN: Tape and Reel,

Industrial Temperature,

8LD SOIC package.

Device

MCP606

MCP606T = Single Op Amp

Tape and Reel (SOIC, TSSOP)

Dual Op Amp

MCP607T = Dual Op Amp

Tape and Reel (SOIC, TSSOP)

Single Op Amp with CS

= Single Op Amp

d)

e)

f)

MCP606-I/ST:

Industrial Temperature,

8LD TSSOP package.

MCP607

=

MCP606-I/OT: Industrial Temperature,

5LD SOT-23 package.

MCP606T-I/OT: Tape and Reel,

Industrial Temperature,

MCP608

=

MCP608T = Single Op Amp with CS

Tape and Reel (SOIC, TSSOP)

MCP609

MCP609T = Quad Op Amp

Tape and Reel (SOIC, TSSOP)

5LD SOT-23 package.

= Quad Op Amp

a)

b)

MCP607-I/P:

Industrial Temperature,

8LD PDIP package.

MCP607T-I/P: Industrial Temperature,

8LD PDIP package.

Temperature Range

Package

I

=

-40°C to +85°C

a)

b)

MCP608-I/SN: Industrial Temperature,

8LD SOIC package.

MCP608T-I/SN: Tape and Reel,

Industrial Temperature,

8LD SOIC package.

OT

P

SN

SL

ST

=

Plastic SOT-23, 5-lead

Plastic DIP (300 mil Body), 8-lead & 14-lead

Plastic SOIC (150 mil Body), 8-lead

Plastic SOIC (150 mil Body), 14-lead

Plastic TSSOP, 8-lead & 14-lead

a)

b)

MCP609-I/P:

Industrial Temperature,

14LD PDIP package.

MCP609T-I/P: Industrial Temperature,

14LD PDIP package.

DS11177D-page 27

MCP606/7/8/9

NOTES:

DS11177D-page 28

Note the following details of the code protection feature on Microchip devices:

•

Microchip products meet the specification contained in their particular Microchip Data Sheet.

•

Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

•

There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

•

Microchip is willing to work with the customer who is concerned about the integrity of their code.

Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR WAR-

RANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,

WRITTEN OR ORAL, STATUTORY OR OTHERWISE,

RELATED TO THE INFORMATION, INCLUDING BUT NOT

LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE,

MERCHANTABILITY OR FITNESS FOR PURPOSE.

Microchip disclaims all liability arising from this information and

its use. Use of Microchip’s products as critical components in

life support systems is not authorized except with express

written approval by Microchip. No licenses are conveyed,

implicitly or otherwise, under any Microchip intellectual property

rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron,

dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART,

PRO MATE, PowerSmart, rfPIC, and SmartShunt are

registered trademarks of Microchip Technology Incorporated

in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB,

PICMASTER, SEEVAL, SmartSensor and The Embedded

Control Solutions Company are registered trademarks of

Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM,

dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,

FanSense, FlexROM, fuzzyLAB, In-Circuit Serial

Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK,

MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail,

PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB,

rfPICDEM, Select Mode, Smart Serial, SmartTel, Total

Endurance and WiperLock are trademarks of Microchip

Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for

its worldwide headquarters, design and wafer fabrication facilities in

Chandler and Tempe, Arizona and Mountain View, California in

October 2003. The Company’s quality system processes and

procedures are for its PICmicro^®8-bit MCUs, KEELOQ^®code hopping

devices, Serial EEPROMs, microperipherals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS11177D-page 29

WORLDWIDE SALES AND SERVICE

AMERICAS

ASIA/PACIFIC

EUROPE

Corporate Office

Australia - Sydney

Tel: 61-2-9868-6733

Fax: 61-2-9868-6755

India - Bangalore

Tel: 91-80-2229-0061

Fax: 91-80-2229-0062

Austria - Weis

Tel: 43-7242-2244-399

Fax: 43-7242-2244-393

2355 West Chandler Blvd.

Chandler, AZ 85224-6199

Tel: 480-792-7200

Fax: 480-792-7277

Technical Support:

http://support.microchip.com

Web Address:

www.microchip.com

China - Beijing

Tel: 86-10-8528-2100

Fax: 86-10-8528-2104

Denmark - Ballerup

Tel: 45-4450-2828

Fax: 45-4485-2829

India - New Delhi

Tel: 91-11-5160-8631

Fax: 91-11-5160-8632

China - Chengdu

Tel: 86-28-8676-6200

Fax: 86-28-8676-6599

France - Massy

Tel: 33-1-69-53-63-20

Fax: 33-1-69-30-90-79

Japan - Kanagawa

Tel: 81-45-471- 6166

Fax: 81-45-471-6122

Atlanta

China - Fuzhou

Tel: 86-591-8750-3506

Fax: 86-591-8750-3521

Germany - Ismaning

Tel: 49-89-627-144-0

Fax: 49-89-627-144-44

Korea - Seoul

Alpharetta, GA

Tel: 770-640-0034

Fax: 770-640-0307

Tel: 82-2-554-7200

Fax: 82-2-558-5932 or

82-2-558-5934

Italy - Milan

Tel: 39-0331-742611

Fax: 39-0331-466781

China - Hong Kong SAR

Tel: 852-2401-1200

Fax: 852-2401-3431

Boston

Singapore

Tel: 65-6334-8870

Fax: 65-6334-8850

Westford, MA

Tel: 978-692-3848

Fax: 978-692-3821

Netherlands - Drunen

Tel: 31-416-690399

Fax: 31-416-690340

China - Shanghai

Tel: 86-21-5407-5533

Fax: 86-21-5407-5066

China - Shenyang

Tel: 86-24-2334-2829

Fax: 86-24-2334-2393

Taiwan - Kaohsiung

Tel: 886-7-536-4818

Fax: 886-7-536-4803

Chicago

Itasca, IL

Tel: 630-285-0071

Fax: 630-285-0075

England - Berkshire

Tel: 44-118-921-5869

Fax: 44-118-921-5820

Taiwan - Taipei

Tel: 886-2-2500-6610

Fax: 886-2-2508-0102

Dallas

Addison, TX

China - Shenzhen

Tel: 86-755-8203-2660

Fax: 86-755-8203-1760

Tel: 972-818-7423

Fax: 972-818-2924

Taiwan - Hsinchu

Tel: 886-3-572-9526

Fax: 886-3-572-6459

China - Shunde

Detroit

Tel: 86-757-2839-5507

Fax: 86-757-2839-5571

Farmington Hills, MI

Tel: 248-538-2250

Fax: 248-538-2260

China - Qingdao

Tel: 86-532-502-7355

Fax: 86-532-502-7205

Kokomo

Kokomo, IN

Tel: 765-864-8360

Fax: 765-864-8387

Los Angeles

Mission Viejo, CA

Tel: 949-462-9523

Fax: 949-462-9608

San Jose

Mountain View, CA

Tel: 650-215-1444

Fax: 650-961-0286

Toronto

Mississauga, Ontario,

Canada

Tel: 905-673-0699

Fax: 905-673-6509

10/20/04

DS11177D-page 30


型号：	MCP608I/P
厂家：	MICROCHIP
描述：	2.5V TO 5.5V MICROPOWER CMOS OP AMPS 2.5V至5.5V微功耗CMOS运算放大器运算放大器
文件：	总30页 (文件大小：494K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCP608I/P [MICROCHIP]

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