MCP608T-I/SN [MICROCHIP]
2.5V to 6.0V Micropower CMOS Op Amp; 2.5V至6.0V微功耗CMOS运算放大器
| 型号： | MCP608T-I/SN |
| 厂家： | 
MICROCHIP |
| 描述： | 2.5V to 6.0V Micropower CMOS Op Amp |
| 文件： | 总42页 (文件大小：720K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP606/7/8/9
2.5V to 6.0V Micropower CMOS Op Amp
Description
Features
The MCP606/7/8/9 family of operational amplifiers (op
amps) from Microchip Technology Inc. are unity-gain
stable with low offset voltage (250 µV, maximum).
Performance characteristics include rail-to-rail output
swing capability and low input bias current (80 pA at
+85°C, maximum). These features make this family of
op amps well suited for single-supply, precision,
high-impedance, battery-powered applications.
• Low Input Offset Voltage: 250 µV (maximum)
• Rail-to-Rail Output
• Low Input Bias Current: 80 pA (maximum at
+85°C)
• Low Quiescent Current: 25 µA (maximum)
• Power Supply Voltage: 2.5V to 6.0V
• Unity-Gain Stable
• Chip Select (CS) Capability: MCP608
• Industrial Temperature Range: -40°C to +85°C
• No Phase Reversal
The single is available in standard 8-lead PDIP, SOIC
and TSSOP packages, as well as in a SOT-23-5
package. The single MCP608 with Chip Select (CS) is
offered in the standard 8-lead PDIP, SOIC and TSSOP
packages. The dual MCP607 is offered in the standard
8-lead PDIP, SOIC and TSSOP packages. Finally, the
quad MCP609 is offered in the standard 14-lead PDIP,
SOIC and TSSOP packages. All devices are fully
specified from -40°C to +85°C, with power supplies
from 2.5V to 6.0V.
• Available in Single, Dual and Quad Packages
Typical Applications
• Battery Power Instruments
• High-Impedance Applications
• Strain Gauges
• Medical Instruments
• Test Equipment
Package Types
MCP606
MCP606
PDIP, SOIC,TSSOP
SOT-23-5
Design Aids
NC 1
8
7
6
VOUT
VSS
VIN+
1
5
4
NC
VDD
• SPICE Macro Models
• FilterLab® Software
2
3
4
2
3
VIN–
VIN+
VSS
VDD
VOUT
VIN–
• Mindi™ Circuit Designer & Simulator
• Analog Demonstration and Evaluation Boards
• Application Notes
5 NC
MCP607
PDIP, SOIC,TSSOP
MCP608
PDIP, SOIC,TSSOP
Typical Application
VOUTA
1
2
3
4
8
7
6
NC 1
8
7
6
VDD
CS
2
3
4
VINA
VINA
–
+
VOUTB VIN–
VDD
VOUT
VOUT = VLM + I R
(R ⁄ RG)
F
L
SEN
IL
VINB
–
+
VIN+
VSS
5 VINB
5 NC
VSS
RF
RG
To Load
(VLP
)
50 kΩ
5 kΩ
MCP609
PDIP, SOIC,TSSOP
2.5V
to
6.0V
VOUT
VOUTA
1
2
3
4
5
6
7
14
13
VOUTD
VINA
VINA
–
+
VIND
–
+
MCP606
RSEN
10Ω
12 VIND
11 VSS
10
9
To Load
(VLM
)
VDD
VINB
VINB
+
–
VINC
VINC
+
–
Low-Side Battery Current Sensor
8 VOUTC
VOUTB
© 2009 Microchip Technology Inc.
DS11177F-page 1
MCP606/7/8/9
NOTES:
DS11177F-page 2
© 2009 Microchip Technology Inc.
MCP606/7/8/9
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD – VSS ........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+, VIN–) ††........ VSS – 1.0V to VDD + 1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V
†† See Section 4.1.2 “Input Voltage and Current Limits”.
Difference Input Voltage ...................................... |VDD – VSS
|
Output Short Circuit Current ................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature .................................–65° C to +150° C
Maximum Junction Temperature (TJ).........................+150° C
ESD Protection On All Pins (HBM; MM) .............. ≥ 3 kV; 200V
DC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Input Offset
Sym
Min
Typ
Max
Units
Conditions
Input Offset Voltage
VOS
-250
—
—
±1.8
93
+250
—
µV
Input Offset Drift with Temperature
Power Supply Rejection Ratio
Input Bias Current and Impedance
Input Bias Current
ΔVOS/ΔTA
PSRR
µV/°C TA = -40°C to +85°C
dB
80
—
IB
IB
—
—
—
—
—
1
—
—
80
—
—
—
pA
At Temperature
pA TA = +85°C
Input Offset Bias Current
Common Mode Input Impedance
Differential Input Impedance
Common Mode
IOS
1
pA
ZCM
ZDIFF
1013||6
1013||6
Ω||pF
Ω||pF
Common Mode Input Range
Common Mode Rejection Ratio
Open-Loop Gain
VCMR
VSS – 0.3
75
VDD – 1.1
—
V
CMRR ≥ 75 dB
CMRR
91
dB VDD = 5V, VCM = -0.3V to 3.9V
DC Open-Loop Gain
(Large-signal)
AOL
AOL
105
100
121
118
—
—
dB RL = 25 kΩ to VL,
V
OUT = 50 mV to VDD – 50 mV
DC Open-Loop Gain
(Large-signal)
dB RL = 5 kΩ to VL,
V
OUT = 0.1V to VDD – 0.1V
Output
Maximum Output Voltage Swing
VOL, VOH
VSS + 15
VSS + 45
VSS + 50
VSS + 100
—
—
—
—
VDD – 20
VDD – 60
VDD – 50
VDD – 100
mV RL = 25 kΩ to VL,
0.5V input overdrive
V
OL, VOH
VOUT
mV RL = 5 kΩ to VL,
0.5V input overdrive
Linear Output Voltage Range
Output Short Circuit Current
mV RL = 25 kΩ to VL,
AOL ≥ 105 dB
VOUT
mV RL = 5 kΩ to VL,
AOL ≥ 100 dB
ISC
ISC
—
—
7
—
—
mA VDD = 2.5V
mA VDD = 5.5V
17
Power Supply
Supply Voltage
VDD
IQ
2.5
—
—
6.0
25
V
Quiescent Current per Amplifier
18.7
µA IO = 0
Note 1: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.5V and 5.5V.
© 2009 Microchip Technology Inc.
DS11177F-page 3
MCP606/7/8/9
AC CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
155
62
—
—
—
kHz
°
G = +1 V/V
Slew Rate
SR
0.08
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
2.8
38
3
—
—
—
µVP-P
f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
fA/√Hz f = 1 kHz
MCP608 CHIP SELECT CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2,
VOUT ≈ VDD/2, VL = VDD/2, RL = 100 kΩ to VL and CL = 60 pF, and CS is tied low (refer to Figure 1-2 and Figure 1-3).
Parameters
Sym
Min
Typ
Max
Units
Conditions
CS Low Specifications
CS Logic Threshold, Low
VIL
VSS
-0.1
—
0.2 VDD
—
V
CS Input Current, Low
ICSL
0.01
µA
CS = 0.2VDD
CS High Specifications
CS Logic Threshold, High
VIH
ICSH
0.8 VDD
—
0.01
-0.05
10
VDD
0.1
—
V
CS Input Current, High
—
-2
—
µA
µA
nA
CS = VDD
CS = VDD
CS = VDD
CS Input High, GND Current
Amplifier Output Leakage, CS High
CS Dynamic Specifications
CS Low to Amplifier Output Turn-on Time
ISS
IO(LEAK)
—
tON
tOFF
—
—
—
9
100
—
µs
µs
V
CS = 0.2VDD to VOUT = 0.9 VDD/2,
G = +1 V/V, RL = 1 kΩ to VSS
CS High to Amplifier Output Hi-Z
CS Hysteresis
0.1
0.6
CS = 0.8VDD to VOUT = 0.1 VDD/2,
G = +1 V/V, RL = 1 kΩ to VSS
VHYST
—
VDD = 5.0V
VIH
VIL
CS
VOUT
ISS
tOFF
tON
Hi-Z
Hi-Z
-18.7 µA
(typical)
-50 nA
(typical)
-50 nA
(typical)
ICS
-50 nA
-50 nA
(typical)
(typical)
FIGURE 1-1:
Timing Diagram for the CS
Pin on the MCP608.
DS11177F-page 4
© 2009 Microchip Technology Inc.
MCP606/7/8/9
TEMPERATURE CHARACTERISTICS
Electrical Characteristics: Unless otherwise indicated, VDD = +2.5V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Specified Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SOT23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-TSSOP
Thermal Resistance, 14L-PDIP
Thermal Resistance, 14L-SOIC
Thermal Resistance, 14L-TSSOP
TA
TA
TA
-40
-40
-65
—
—
—
+85
+125
+150
°C
°C
°C
Note 1
θJA
θJA
θJA
θJA
θJA
θJA
θJA
—
—
—
—
—
—
—
220.7
89.3
149.5
139
—
—
—
—
—
—
—
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
70
95.3
100
Note 1: The MCP606/7/8/9 operate over this extended temperature range, but with reduced performance. In any case, the
Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
1.1
Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-3. The bypass
capacitors are laid out according to the rules discussed
in Section 4.5 “Supply Bypass”.
VDD
1 µF
0.1 µF
VIN
VOUT
RL
RN
RG
MCP60X
CL
RF
VDD/2
VL
FIGURE 1-2:
AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
VDD
1 µF
0.1 µF
VDD/2
VOUT
RL
RN
RG
MCP60X
CL
RF
VIN
VL
FIGURE 1-3:
AC and DC Test Circuit for
Most Inverting Gain Conditions.
© 2009 Microchip Technology Inc.
DS11177F-page 5
MCP606/7/8/9
NOTES:
DS11177F-page 6
© 2009 Microchip Technology Inc.
MCP606/7/8/9
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
16%
16%
206 Samples
1200 Samples
DD = 5.5V
14%
12%
10%
8%
14%
12%
10%
8%
V
DD = 5.5V
V
6%
6%
4%
4%
2%
2%
0%
0%
-8
-6
-4
-2
0
2
4
6
8
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-1:
Input Offset Voltage at
FIGURE 2-4:
Input Offset Voltage Drift
V
= 5.5V.
Magnitude at V = 5.5V.
DD
DD
18%
16%
206 Samples
16%
1200 Samples
DD = 2.5V
14%
12%
10%
8%
V
DD = 2.5V
V
14%
12%
10%
8%
6%
4%
6%
2%
4%
0%
2%
0%
-8
-6
-4
-2
0
2
4
6
8
Input Offset Voltage (µV)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-2:
Input Offset Voltage at
FIGURE 2-5:
Input Offset Voltage Drift
V
= 2.5V.
Magnitude at V = 2.5V.
DD
DD
24
22
22
20
18
16
14
12
10
8
6
4
2
0
VDD = 5.5V
20
18
16
14
12
TA = +85°C
TA = +25°C
TA = -40°C
VDD = 2.5V
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
FIGURE 2-3:
Quiescent Current vs.
FIGURE 2-6:
Quiescent Current vs.
Power Supply Voltage.
Ambient Temperature.
© 2009 Microchip Technology Inc.
DS11177F-page 7
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
120
100
80
60
40
20
0
500
400
300
200
100
0
VDD = 5.5V
VDD =2.5V
DD = 5.5V
V
TA = +85°C
TA = +25°C
T
A = -40°C
Representative Part
-20
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
Common Mode Input Voltage (V)
FIGURE 2-7:
Input Offset Voltage vs.
FIGURE 2-10:
Input Offset Voltage vs.
Ambient Temperature.
Common Mode Input Voltage.
120
100
80
90
45
0
160
80
70
60
50
40
30
20
10
0
RL = 25 kΩ
140
120
100
80
GBWP
Phase Margin
Gain
60
-45
-90
Phase
40
60
20
-135
-180
-225
40
20
0
VDD = 5.0V
0
-20
0.01 0.1
-50
-25
0
25
50
75
100
1
10 100 1k 10k 100k 1M
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-8:
Open-Loop Gain and Phase
FIGURE 2-11:
Gain Bandwidth Product,
vs. Frequency.
Phase Margin vs. Ambient Temperature.
1000
140
130
120
110
100
90
100
10
Referred to Input
80
0.1
1
10
100
1k
10k
100k
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05
Frequency (Hz)
100 1k
10k
1.E+04
100k
1.E+05
1.E+02 1.E+03
Frequency (Hz)
FIGURE 2-9:
Separation (MCP607 and MCP609 only).
Channel-to-Channel
FIGURE 2-12:
vs. Frequency.
Input Noise Voltage Density
DS11177F-page 8
© 2009 Microchip Technology Inc.
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
100
10
1
60
50
40
30
20
10
0
VDD = 5.5V
CM = VDD
TA = 85°C
DD = 5.5V
V
V
IB
IB
IOS
| IOS
|
0.1
-10
25 30 35 40 45 50 55 60 65 70 75 80 85
Ambient Temperature (°C)
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
FIGURE 2-13:
Input Bias Current, Input
FIGURE 2-16:
Input Bias Current, Input
Offset Current vs. Ambient Temperature.
Offset Current vs. Common Mode Input Voltage.
135
130
125
150
RL = 25 kΩ
140
130
120
110
100
120
115
110
105
100
VDD = 5.5V
VDD = 2.5V
10k
90
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
100
1k
1.E+03
100k
1.E+05
1.E+02
1.E+04
Power Supply Voltage (V)
Load Resistance (Ω)
FIGURE 2-14:
DC Open-Loop Gain vs.
FIGURE 2-17:
DC Open-Loop Gain vs.
Load Resistance.
Power Supply Voltage.
120
100
80
60
40
20
0
100
95
90
85
80
75
PSRR-
PSRR+
PSRR
CMRR
CMRR
0.1
1
10
100
1k
10k
-50
-25
0
25
50
75
100
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04
Frequency (Hz)
Ambient Temperature (°C)
FIGURE 2-15:
Frequency.
CMRR, PSRR vs.
FIGURE 2-18:
Temperature.
CMRR, PSRR vs. Ambient
© 2009 Microchip Technology Inc.
DS11177F-page 9
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
1000
100
10
40
35
30
25
20
15
10
5
RL = 5 kΩ
VDD = 2.5V
VDD - VOH
VDD = 5.5V
VDD - VOH
VDD = 5.5V
VDD = 2.5V
VOL - VSS
VOL - VSS
0
1
-50
-25
0
25
50
75
100
0.1
1
10
100
Ambient Temperature (°C)
Output Current (mA)
FIGURE 2-19:
Output Voltage Headroom
FIGURE 2-22:
Output Voltage Headroom
vs. Output Current Magnitude.
vs. Ambient Temperature at R = 5 kΩ.
L
10
6
G = +2 V/V
VDD = 5.0V
5
4
VDD = 5.5V
VDD = 2.5V
3
1
2
VIN
1
VOUT
0
0.1
100
1k
1.E+03
10k
1.E+04
100k
1.E+05
-1
1.E+02
Frequency (Hz)
Time (100 µs/div)
FIGURE 2-20:
Maximum Output Voltage
FIGURE 2-23:
The MCP606/7/8/9 Show
Swing vs. Frequency.
No Phase Reversal.
0.12
0.10
25
20
15
10
+ISC , VDD = 5.5V
| -ISC |, VDD = 5.5V
Low to High
0.08
0.06
0.04
0.02
0.00
High to Low
5
0
+ISC , VDD = 2.5V
| -ISC |, VDD = 2.5V
-50
-25
0
25
50
75
100
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
Ambient Temperature (°C)
FIGURE 2-21:
Slew Rate vs. Ambient
FIGURE 2-24:
Output Short Circuit Current
Temperature.
Magnitude vs. Ambient Temperature.
DS11177F-page 10
© 2009 Microchip Technology Inc.
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD = 5.0V
VDD = 5.0V
Time (50 µs/div)
Time (50 µs/div)
FIGURE 2-25:
Large-signal, Non-inverting
FIGURE 2-28:
Large-signal, Inverting
Pulse Response.
Pulse Response.
VDD = 5.0V
RL = 25 kΩ
Time (50 µs/div)
Time (50 µs/div)
FIGURE 2-26:
Small-signal, Non-inverting
FIGURE 2-29:
Small-signal, Inverting Pulse
Pulse Response.
Response.
3.5
3.0
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
G = +1 V/V
RL = 1 kΩ to VSS
VDD = 5.0V
Amplifier Output Active
5
2.5
2.0
1.5
1.0
0.5
0.0
-0.5
CS
0
CS Input
High to Low
CS Input
Output Enabled
Low to High
Hysteresis
VOUT
1.0
Amplifier Output Hi-Z
Output
Hi-Z
Output
Hi-Z
0.5
0.0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
CS Input Voltage (V)
Time (5 µs/div)
FIGURE 2-27:
Chip Select (CS) Hysteresis
FIGURE 2-30:
Amplifier Output Response
(MCP608 only).
Times vs. Chip Select (CS) Pulse (MCP608
only).
© 2009 Microchip Technology Inc.
DS11177F-page 11
MCP606/7/8/9
Note: Unless otherwise indicated, VDD = +2.5V to +5.5V, VSS = GND, TA = +25°C, VCM = VDD/2, VOUT ≈ VDD/2,
VL = VDD/2, RL = 100 kΩ to VL, CL = 60 pF, and CS is tied low.
1.E-02
10m
1.E-03
1m
1.E- 4
100µ
1.E1-05µ
1.E-016µ
100n
1.E- 7
10n
1.E- 8
1n
1.E-09
100p
1.E-10
10p
1.E-11
+125°C
+85°C
+25°C
-40°C
1p
1.E-12
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
FIGURE 2-31:
Measured Input Current vs.
Input Voltage (below V ).
SS
DS11177F-page 12
© 2009 Microchip Technology Inc.
MCP606/7/8/9
3.0
PIN DESCRIPTIONS
Descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
MCP606
MCP607 MCP608 MCP609
Symbol
Description
PDIP, SOIC,
TSSOP
SOT-23-5
6
2
1
1
2
6
2
1
2
VOUT, VOUTA Output (op amp A)
4
VIN–, VINA
VIN+, VINA
VDD
–
+
Inverting Input (op amp A)
Non-inverting Input (op amp A)
Positive Power Supply
Non-inverting Input (op amp B)
Inverting Input (op amp B)
Output (op amp B)
3
3
3
3
3
7
5
8
7
4
—
—
—
—
—
—
4
—
—
—
—
—
—
2
5
—
—
—
—
—
—
4
5
VINB
VINB
+
6
6
–
7
7
VOUTB
VOUTC
—
—
—
4
8
Output (op amp B)
9
VINC
VINC
–
Inverting Input (op amp C)
Non-inverting Input (op amp C)
Negative Power Supply
Non-inverting Input (op amp D)
Inverting Input (op amp D)
Output (op amp D)
10
11
12
13
14
—
—
+
VSS
—
—
—
—
1, 5, 8
—
—
—
—
—
—
—
—
—
—
—
—
—
8
VIND
+
VIND
–
VOUTD
CS
Chip Select
1, 5
NC
No Internal Connection
3.1
Analog Outputs
3.4
Power Supply Pins
The output pins are low-impedance voltage sources.
The positive power supply pin (VDD) is 2.5V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the output pins are at voltages
between VSS and VDD; while the input pins are at
voltages between VSS – 0.3V and VDD + 0.3V.
3.2
Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
Typically, these parts are used in a single-supply
(positive) configuration. In this case, VSS is connected
to ground and VDD is connected to the supply. VDD will
need bypass capacitors .
3.3
Chip Select Digital Input
The Chip Select (CS) pin is a Schmitt-triggered, CMOS
logic input. It is used to place the MCP608 op amp in a
Low-power mode, with the output(s) in a Hi-Z state.
© 2009 Microchip Technology Inc.
DS11177F-page 13
MCP606/7/8/9
NOTES:
DS11177F-page 14
© 2009 Microchip Technology Inc.
MCP606/7/8/9
4.0
APPLICATIONS INFORMATION
VDD
The MCP606/7/8/9 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process
These op amps are unity-gain stable and suitable for a
wide range of general purpose applications.
D1 D2
V1
V2
R1
R2
MCP60X
4.1
Rail-to-Rail Inputs
4.1.1
PHASE REVERSAL
The MCP606/7/8/9 op amp is designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 2-23 shows the input voltage
exceeding the supply voltage without any phase
reversal.
R3
VSS – (minimum expected V1)
R1 >
R2 >
2 mA
VSS – (minimum expected V2)
2 mA
4.1.2
INPUT VOLTAGE AND CURRENT
LIMITS
FIGURE 4-2:
Protecting the Analog
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit the useable voltage
range.
Bond
VDD
Pad
4.1.3
NORMAL OPERATION
Bond
Pad
Bond
Pad
Input
Stage
The input stage of the MCP606/7/8/9 op amps use a
PMOS input stage. It operates at low common mode
VIN+
VIN–
input voltage (V ), including ground. WIth this
CM
topology, the device operates with V up to V –1.1V
CM
DD
and 0.3V below V
.
Bond
Pad
SS
VSS
Figure 4-3 shows a unity gain buffer. Since VOUT is the
same voltage as the inverting input, VOUT must be kept
below VDD–1.2V for correct operation.
FIGURE 4-1:
Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must limit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
VIN
+
VOUT
MCP60X
–
FIGURE 4-3:
Unity Gain Buffer has a
Range.
Limited V
OUT
© 2009 Microchip Technology Inc.
DS11177F-page 15
MCP606/7/8/9
4.2
Rail-to-Rail Output
10000
10k
There are two specifications that describe the
output-swing capability of the MCP606/7/8/9 family of
op amps. The first specification (Maximum Output
Voltage Swing) defines the absolute maximum swing
that can be achieved under the specified load
conditions. For instance, the output voltage swings to
within 15 mV of the negative rail with a 25 kΩ load to
VDD/2. Figure 2-23 shows how the output voltage is
limited when the input goes beyond the linear region of
operation.
1000
1k
GN = +1
N = +2
GN ≥ +4
G
100
100
10
100
1000
10000
10p
100p
1n
10n
Normalized Load Capacitance; CL/GN (F)
The second specification that describes the output-
swing capability of these amplifiers (Linear Output
Voltage Range) defines the maximum output swing that
can be achieved while the amplifier still operates in its
linear region. To verify linear operation in this range, the
large-signal DC Open-Loop Gain (AOL) is measured at
points inside the supply rails. The measurement must
meet the specified AOL conditions in the specification
table.
FIGURE 4-5:
Recommended R
Values
ISO
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO’s value until the
response is reasonable. Bench evaluation and simula-
tions with the MCP606/7/8/9 SPICE macro model are
helpful.
4.3
Capacitive Loads
4.4
MCP608 Chip Select
Driving large capacitive loads can cause stability
problems for voltage-feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain-peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
The MCP608 is a single op amp with Chip Select (CS).
When CS is pulled high, the supply current drops to
50 nA (typical) and flows through the CS pin to VSS
When this happens, the amplifier output is put into a
high-impedance state. By pulling CS low, the amplifier
is enabled. The CS pin has an internal 5 MΩ (typical)
pull-down resistor connected to VSS, so it will go low if
the CS pins is left floating. Figure 1-1 shows the output
voltage and supply current response to a CS pulse.
.
When driving large capacitive loads with these op
amps (e.g., > 60 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-4) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will be generally lower than the bandwidth
with no capacitive load.
4.5
Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) should have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good high-frequency performance. It also needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with other nearby analog parts.
RISO
MCP60X
VOUT
VIN
CL
FIGURE 4-4:
Output Resistor, R
ISO
stabilizes large capacitive loads.
Figure 4-5 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
DS11177F-page 16
© 2009 Microchip Technology Inc.
MCP606/7/8/9
1. Non-inverting Gain and Unity-gain Buffer:
4.6
Unused Op Amps
a) Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
An unused op amp in a quad package (MCP609)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
b) Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
2. Inverting Gain and Transimpedance Gain
(convert current to voltage, such as photo
detectors) amplifiers:
a) Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
¼ MCP609 (B)
¼ MCP609 (A)
VDD
VDD
b) Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
VDD
R1
R2
VREF
4.8
Application Circuits
4.8.1
LOW-SIDE BATTERY CURRENT
SENSOR
R2
------------------
⋅
The MCP606/7/8/9 op amps can be used to sense the
load current on the low-side of a battery using the
circuit in Figure 4-8. In this circuit, the current from the
power supply (minus the current required to power the
MCP606) flows through a sense resistor (RSEN), which
converts it to voltage. This is gained by the the amplifier
and resistors, RG and RF.Since the non-inverting input
of the amplifier is at the load’s negative supply (VLM),
the gain from RSEN to VOUT is RF/RG.
VREF = VDD
R1 + R2
FIGURE 4-6:
Unused Op Amps.
4.7
PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP606/7/8/9 family’s bias current at +25°C (1 pA,
typical).
VOUT = VLM + I R
(R ⁄ RG)
F
L
SEN
IL
RF
50 kΩ
RG
5 kΩ
To Load
(VLP
)
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in Figure 4-7.
2.5V
to
6.0V
VOUT
MCP606
RSEN
To Load
10Ω
(VLM
)
VIN-
VIN+
VSS
FIGURE 4-8:
Low Side Battery Current
Sensor.
Since the input bias current and input offset voltage of
the MCP606 are low, and the input is capable of
swinging below ground, there is very little error
generated by the amplifier. The quiescent current is
very low, which helps conserve battery power. The
rail-to-rail output makes it possible to read very low
currents.
Guard Ring
Example Guard Ring Layout
FIGURE 4-7:
for Inverting Gain.
© 2009 Microchip Technology Inc.
DS11177F-page 17
MCP606/7/8/9
operate at a much higher speed. This reverse bias also
increases the dark current and current noise, however.
Resistor R2 converts the current into voltage. Capacitor
C2 limits the bandwidth and helps stabilize the circuit
when D1’s junction capacitance is large.
4.8.2
PHOTODIODE AMPLIFIERS
Sensors that produce an output current and have high
output impedance can be connected to
transimpedance amplifier. The transimpedance
amplifier converts the current into voltage. Photodiodes
are one sensor that produce an output current.
a
VB < 0
The key op amp characteristics that are needed for
these circuits are: low input offset voltage, low input
bias current, high input impedance and an input
common mode range that includes ground. The low
input offset voltage and low input bias current support
a very low voltage drop across the photodiode; this
gives the best photodiode linearity. Since the
photodiode is biased at ground, the op amp’s input
needs to function well both above and below ground.
VOUT = I
R
D1
2
C2
R2
VOUT
ID1
VDD
Light
4.8.2.1
Photo-Voltaic Mode
D1
MCP606
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D1) biased in the Photo-voltaic mode (0V
across D1), which is used for precision photodiode
sensing.
VB
FIGURE 4-10:
As light impinges on D1, charge is generated, causing
a current to flow in the reverse bias direction of D1. The
op amp’s negative feedback forces the voltage across
the D1 to be nearly 0V. Resistor R2 converts the current
into voltage. Capacitor C2 limits the bandwidth and
helps stabilize the circuit when D1’s junction
capacitance is large.
Photodiode (in Photo-
conductive mode) and Transimpedance
Amplifier.
4.8.3
TWO OP AMP INSTRUMENTATION
AMPLIFIER
The two op amp instrumentation amplifier shown in
Figure 4-11 serves the function of taking the difference
of two input voltages, level-shifting it and gaining it to
the output. This configuration is best suited for higher
VOUT = I
R
D1
2
C2
R2
gains (i.e., gain > 3 V/V). The reference voltage (VREF
)
is typically at mid-supply (VDD/2) in a single-supply
environment.
VOUT
ID1
R
2R
⎛
⎞
1
1
VDD
Light
V
= (V – V ) 1 + ------ + --------- + V
⎜
⎝
⎟
⎠
OUT
1
2
REF
R
R
2
G
D1
MCP606
RG
R1
R2
R2
R1
VREF
VOUT
FIGURE 4-9:
Photodiode (in Photo-voltaic
mode) and Transimpedance Amplifier.
V2
V1
½
½
MCP607
MCP607
4.8.2.2 Photo-Conductive Mode
Figure 4-9 shows a transimpedance amplifier with a
photodiode (D1) biased in the Photo-conductive mode
(D1 is reverse biased), which is used for high-speed
applications.
FIGURE 4-11:
Instrumentation Amplifier.
Two Op Amp
The key specifications that make the MCP606/7/8/9
family appropriate for this application circuit are low
input bias current, low offset voltage and high
common-mode rejection.
As light impinges on D1, charge is generated, causing
a current to flow in the reverse bias direction of D1.
Placing a negative bias on D1 significantly reduces its
junction capacitance, which allows the circuit to
DS11177F-page 18
© 2009 Microchip Technology Inc.
MCP606/7/8/9
4.8.4
THREE OP AMP
INSTRUMENTATION AMPLIFIER
4.8.5
PRECISION GAIN WITH GOOD
LOAD ISOLATION
A classic, three op amp instrumentation amplifier is
illustrated in Figure 4-12. The two input op amps
provide differential signal gain and a common mode
gain of +1. The output op amp is a difference amplifier,
which converts its input signal from differential to a sin-
gle ended output; it rejects common mode signals at its
input. The gain of this circuit is simply adjusted with one
resistor (RG). The reference voltage (VREF) is typically
referenced to mid-supply (VDD/2) in single-supply
applications.
In Figure 4-13, the MCP606 op amps, R1 and R2
provide a high gain to the input signal (VIN). The
MCP606’s low offset voltage makes this an accurate
circuit.
The MCP601 is configured as a unity-gain buffer. It
isolates the MCP606’s output from the load, increasing
the high-gain stage’s precision. Since the MCP601 has
a higher output current, with the two amplifiers being
housed in separate packages, there is minimal change
in the MCP606’s offset voltage due to loading effect.
R
2R
⎛
⎞ ⎛
⎟ ⎜
⎠ ⎝
⎞
⎟
⎠
4
2
V
= V (1 + R ⁄ R )
IN 2 1
-----
V
= (V – V ) 1 + ---------
+ V
⎜
OUT
OUT
1
2
REF
R
3
R
⎝
G
MCP606
½
VIN
MCP601
MCP607
V2
VOUT
R3
R4
R1
R2
VOUT
R2
RG
R2
FIGURE 4-13:
Load Isolation.
Precision Gain with Good
MCP606
VREF
R3
R4
V1
½
MCP607
FIGURE 4-12:
Three Op Amp
Instrumentation Amplifier.
© 2009 Microchip Technology Inc.
DS11177F-page 19
MCP606/7/8/9
NOTES:
DS11177F-page 20
© 2009 Microchip Technology Inc.
MCP606/7/8/9
5.5
Analog Demonstration and
Evaluation Boards
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP606/7/8/9 family of op amps.
Microchip offers
a
broad spectrum of Analog
Demonstration and Evaluation Boards that are
designed to help you achieve faster time to market. For
5.1
SPICE Macro Model
a
complete listing of these boards and their
The latest SPICE macro model for the MCP606/7/8/9
op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
corresponding user’s guides and technical information,
visit the Microchip web site at www.microchip.com/
analogtools.
Two of our boards that are especially useful are:
• 8-Pin SOIC/MSOP/TSSOP/DIP Evaluation Board,
P/N SOIC8EV
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
• 14-Pin SOIC/TSSOP/DIP Evaluation Board, P/N
SOIC14EV
5.6
Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended as supplemental
reference resources.
5.2
FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filterlab, the
FilterLab design tool provides full schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can be
used with the macro model to simulate actual filter
performance.
• ADN003: “Select the Right Operational Amplifier
for your Filtering Circuits”, DS21821
• AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
• AN723: “Operational Amplifier AC Specifications
and Applications”, DS00723
• AN884: “Driving Capacitive Loads With Op
Amps”, DS00884
5.3
Mindi™ Circuit Designer &
Simulator
• AN990: “Analog Sensor Conditioning Circuits –
An Overview”, DS00990
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams,
simulate circuits. Circuits developed using the Mindi
Circuit Designer & Simulator can be downloaded to a
personal computer or workstation.
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
5.4
Microchip Advanced Part Selector
(MAPS)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip website at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparasion
reports. Helpful links are also provided for Datasheets,
Purchase, and Sampling of Microchip parts.
© 2009 Microchip Technology Inc.
DS11177F-page 21
MCP606/7/8/9
NOTES:
DS11177F-page 22
© 2009 Microchip Technology Inc.
MCP606/7/8/9
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
Example:
5-Lead SOT-23 (MCP606)
XXNN
SB25
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
XXXXXNNN
MCP606
I/P256
0722
MCP606
I/P 256
0936
e
3
OR
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
MCP606
MCP606I
e
3
XXXXYYWW
I/SN0722
SN 0936
OR
NNN
256
256
Example:
8-Lead TSSOP
606
I936
256
XXXX
YYWW
NNN
Legend: XX...X Customer-specific information
Y
YY
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
WW
NNN
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
e
3
Pb-free JEDEC designator for Matte Tin (Sn)
*
This package is Pb-free. The Pb-free JEDEC designator (
can be found on the outer packaging for this package.
)
e3
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS11177F-page 23
MCP606/7/8/9
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP609)
Example:
MCP609-I/P
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
0722256
MCP609
e
3
I/P
OR
0936256
14-Lead SOIC (150 mil) (MCP609)
Example:
MCP609ISL
XXXXXXXXXX
XXXXXXXXXX
YYWWNNN
0722256
MCP609
OR
I/SL^
e
3
0936256
Example:
14-Lead TSSOP (MCP609)
XXXXXXXX
YYWW
609IST
0936
NNN
256
DS11177F-page 24
© 2009 Microchip Technology Inc.
MCP606/7/8/9
ꢀꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢒꢓꢄꢑꢉꢋꢉꢊꢔꢓꢆꢕꢏꢒꢖꢆꢗꢍꢏꢒꢁꢘꢙꢚ
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b
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)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
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© 2009 Microchip Technology Inc.
DS11177F-page 25
MCP606/7/8/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢐꢄꢈꢆ!ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆꢙ##ꢆꢎꢋꢈꢆ$ꢔꢅ%ꢆꢗꢇ !ꢇꢚ
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ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
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ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ꢈ)ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐꢀ;)
DS11177F-page 26
© 2009 Microchip Technology Inc.
MCP606/7/8/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ&'ꢆꢙ()#ꢆꢎꢎꢆ$ꢔꢅ%ꢆꢗꢍꢏ!*ꢚ
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ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
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ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐ(ꢒ)
© 2009 Microchip Technology Inc.
DS11177F-page 27
MCP606/7/8/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢛꢖꢆMꢆꢛꢄꢓꢓꢔ&'ꢆꢙ()#ꢆꢎꢎꢆ$ꢔꢅ%ꢆꢗꢍꢏ!*ꢚ
ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
DS11177F-page 28
© 2009 Microchip Technology Inc.
MCP606/7/8/9
ꢝꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢒ+ꢋꢑꢆꢍ+ꢓꢋꢑ,ꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢒꢖꢆMꢆ-(-ꢆꢎꢎꢆ$ꢔꢅ%ꢆꢗꢒꢍꢍꢏꢇꢚ
ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
N
E
E1
NOTE 1
1
2
b
e
c
φ
A
A2
A1
L
L1
3ꢆꢃ#
ꢏꢙ44ꢙꢏ"ꢗ"ꢚꢕ
ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
ꢏꢙ5
56ꢏ
ꢏꢔ7
5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ
1ꢃ#ꢊꢌ
5
ꢅ
;
ꢐꢁ=(ꢈ)ꢕ*
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ꢕ#ꢉꢆ!ꢇ%%ꢈ
ꢔ
M
ꢐꢁ;ꢐ
ꢐꢁꢐ(
M
ꢀꢁꢐꢐ
M
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ꢀꢁꢐ(
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ꢔꢑ
ꢔꢀ
"
6,ꢅꢍꢉꢋꢋꢈ<ꢃ!#ꢌ
=ꢁꢖꢐꢈ)ꢕ*
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ<ꢃ!#ꢌ
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.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ
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ꢖꢁꢜꢐ
ꢑꢁꢛꢐ
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ꢖꢁꢖꢐ
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ꢐꢁ=ꢐ
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ꢜꢁꢀꢐ
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.ꢇꢇ#ꢎꢍꢃꢆ#
.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ
4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ
4ꢅꢉ!ꢈ<ꢃ!#ꢌ
4ꢀ
ꢀ
ꢀꢁꢐꢐꢈꢚ".
ꢐꢝ
ꢐꢁꢐꢛ
ꢐꢁꢀꢛ
M
M
M
;ꢝ
ꢊ
8
ꢐꢁꢑꢐ
ꢐꢁꢜꢐ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐ;=)
© 2009 Microchip Technology Inc.
DS11177F-page 29
MCP606/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS11177F-page 30
© 2009 Microchip Technology Inc.
MCP606/7/8/9
.-ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆ ꢐꢄꢈꢆ!ꢑꢁꢂꢋꢑꢃꢆꢕꢇꢖꢆMꢆꢙ##ꢆꢎꢋꢈꢆ$ꢔꢅ%ꢆꢗꢇ !ꢇꢚ
ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
N
NOTE 1
E1
3
1
2
D
E
A2
A
L
c
A1
b1
b
e
eB
3ꢆꢃ#
ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
ꢙ5*9"ꢕ
56ꢏ
ꢀꢖ
ꢁꢀꢐꢐꢈ)ꢕ*
M
ꢏꢙ5
ꢏꢔ7
5$ꢄ8ꢅꢍꢈꢇ%ꢈ1ꢃꢆ
1ꢃ#ꢊꢌ
5
ꢅ
ꢔ
ꢗꢇꢎꢈ#ꢇꢈꢕꢅꢉ#ꢃꢆꢓꢈ1ꢋꢉꢆꢅ
M
ꢁꢑꢀꢐ
ꢁꢀꢛ(
M
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈꢗꢌꢃꢊ/ꢆꢅ
)ꢉ ꢅꢈ#ꢇꢈꢕꢅꢉ#ꢃꢆꢓꢈ1ꢋꢉꢆꢅ
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6,ꢅꢍꢉꢋꢋꢈ4ꢅꢆꢓ#ꢌ
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4ꢅꢉ!ꢈꢗꢌꢃꢊ/ꢆꢅ
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ꢔꢀ
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ꢂ
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8
ꢅ)
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ꢁꢒꢜ(
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ꢁꢐꢐ;
ꢁꢐꢖ(
ꢁꢐꢀꢖ
M
ꢁꢀꢜꢐ
M
ꢁꢜꢀꢐ
ꢁꢑ(ꢐ
ꢁꢒ(ꢐ
ꢁꢀꢜꢐ
ꢁꢐꢀꢐ
ꢁꢐ=ꢐ
ꢁꢐꢀ;
M
ꢁꢜꢑ(
ꢁꢑ;ꢐ
ꢁꢒꢒ(
ꢁꢀ(ꢐ
ꢁꢐꢀ(
ꢁꢐꢒꢐ
ꢁꢐꢑꢑ
ꢁꢖꢜꢐ
4ꢇ-ꢅꢍꢈ4ꢅꢉ!ꢈ<ꢃ!#ꢌ
6,ꢅꢍꢉꢋꢋꢈꢚꢇ-ꢈꢕꢎꢉꢊꢃꢆꢓꢈꢈꢟ
ꢛꢔꢊꢃꢉꢜ
ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ
ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢁꢐꢀꢐ@ꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ꢈ)ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐꢐ()
© 2009 Microchip Technology Inc.
DS11177F-page 31
MCP606/7/8/9
.-ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢂꢖꢆMꢆꢛꢄꢓꢓꢔ&'ꢆꢙ()#ꢆꢎꢎꢆ$ꢔꢅ%ꢆꢗꢍꢏ!*ꢚ
ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
N
E
E1
NOTE 1
1
2
3
e
h
b
α
h
c
φ
A2
A
L
A1
β
L1
3ꢆꢃ#
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M
M
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;ꢝ
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ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢟꢈꢕꢃꢓꢆꢃ%ꢃꢊꢉꢆ#ꢈ*ꢌꢉꢍꢉꢊ#ꢅꢍꢃ #ꢃꢊꢁ
ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢖꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐ=()
DS11177F-page 32
© 2009 Microchip Technology Inc.
MCP606/7/8/9
ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
© 2009 Microchip Technology Inc.
DS11177F-page 33
MCP606/7/8/9
.-ꢁꢂꢃꢄꢅꢆꢇꢈꢄꢉꢊꢋꢌꢆꢒ+ꢋꢑꢆꢍ+ꢓꢋꢑ,ꢆꢍꢎꢄꢈꢈꢆꢏꢐꢊꢈꢋꢑꢃꢆꢕꢍꢒꢖꢆMꢆ-(-ꢆꢎꢎꢆ$ꢔꢅ%ꢆꢗꢒꢍꢍꢏꢇꢚ
ꢛꢔꢊꢃꢜ .ꢇꢍꢈ#ꢌꢅꢈꢄꢇ #ꢈꢊ$ꢍꢍꢅꢆ#ꢈꢎꢉꢊ/ꢉꢓꢅꢈ!ꢍꢉ-ꢃꢆꢓ 0ꢈꢎꢋꢅꢉ ꢅꢈ ꢅꢅꢈ#ꢌꢅꢈꢏꢃꢊꢍꢇꢊꢌꢃꢎꢈ1ꢉꢊ/ꢉꢓꢃꢆꢓꢈꢕꢎꢅꢊꢃ%ꢃꢊꢉ#ꢃꢇꢆꢈꢋꢇꢊꢉ#ꢅ!ꢈꢉ#ꢈ
ꢌ##ꢎ+22---ꢁꢄꢃꢊꢍꢇꢊꢌꢃꢎꢁꢊꢇꢄ2ꢎꢉꢊ/ꢉꢓꢃꢆꢓ
D
N
E
E1
NOTE 1
1
2
e
b
c
φ
A2
A
A1
L
L1
3ꢆꢃ#
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ꢂꢃꢄꢅꢆ ꢃꢇꢆꢈ4ꢃꢄꢃ#
ꢏꢙ5
56ꢏ
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5
ꢅ
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ꢐꢁ=(ꢈ)ꢕ*
6,ꢅꢍꢉꢋꢋꢈ9ꢅꢃꢓꢌ#
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6,ꢅꢍꢉꢋꢋꢈ<ꢃ!#ꢌ
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ<ꢃ!#ꢌ
ꢏꢇꢋ!ꢅ!ꢈ1ꢉꢊ/ꢉꢓꢅꢈ4ꢅꢆꢓ#ꢌ
.ꢇꢇ#ꢈ4ꢅꢆꢓ#ꢌ
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.ꢇꢇ#ꢈꢔꢆꢓꢋꢅ
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8
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ꢀꢁ 1ꢃꢆꢈꢀꢈ,ꢃ $ꢉꢋꢈꢃꢆ!ꢅ&ꢈ%ꢅꢉ#$ꢍꢅꢈꢄꢉꢘꢈ,ꢉꢍꢘ0ꢈ8$#ꢈꢄ$ #ꢈ8ꢅꢈꢋꢇꢊꢉ#ꢅ!ꢈ-ꢃ#ꢌꢃꢆꢈ#ꢌꢅꢈꢌꢉ#ꢊꢌꢅ!ꢈꢉꢍꢅꢉꢁ
ꢑꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆ ꢈꢂꢈꢉꢆ!ꢈ"ꢀꢈ!ꢇꢈꢆꢇ#ꢈꢃꢆꢊꢋ$!ꢅꢈꢄꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢁꢈꢏꢇꢋ!ꢈ%ꢋꢉ ꢌꢈꢇꢍꢈꢎꢍꢇ#ꢍ$ ꢃꢇꢆ ꢈ ꢌꢉꢋꢋꢈꢆꢇ#ꢈꢅ&ꢊꢅꢅ!ꢈꢐꢁꢀ(ꢈꢄꢄꢈꢎꢅꢍꢈ ꢃ!ꢅꢁ
ꢜꢁ ꢂꢃꢄꢅꢆ ꢃꢇꢆꢃꢆꢓꢈꢉꢆ!ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢃꢆꢓꢈꢎꢅꢍꢈꢔꢕꢏ"ꢈ'ꢀꢖꢁ(ꢏꢁ
)ꢕ*+ )ꢉ ꢃꢊꢈꢂꢃꢄꢅꢆ ꢃꢇꢆꢁꢈꢗꢌꢅꢇꢍꢅ#ꢃꢊꢉꢋꢋꢘꢈꢅ&ꢉꢊ#ꢈ,ꢉꢋ$ꢅꢈ ꢌꢇ-ꢆꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ ꢁ
ꢚ".+ ꢚꢅ%ꢅꢍꢅꢆꢊꢅꢈꢂꢃꢄꢅꢆ ꢃꢇꢆ0ꢈ$ $ꢉꢋꢋꢘꢈ-ꢃ#ꢌꢇ$#ꢈ#ꢇꢋꢅꢍꢉꢆꢊꢅ0ꢈ%ꢇꢍꢈꢃꢆ%ꢇꢍꢄꢉ#ꢃꢇꢆꢈꢎ$ꢍꢎꢇ ꢅ ꢈꢇꢆꢋꢘꢁ
ꢏꢃꢊꢍꢇꢊꢌꢃꢎ ꢗꢅꢊꢌꢆꢇꢋꢇꢓꢘ ꢂꢍꢉ-ꢃꢆꢓ *ꢐꢖꢞꢐ;ꢒ)
DS11177F-page 34
© 2009 Microchip Technology Inc.
MCP606/7/8/9
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2009 Microchip Technology Inc.
DS11177F-page 35
MCP606/7/8/9
NOTES:
DS11177F-page 36
© 2009 Microchip Technology Inc.
MCP606/7/8/9
APPENDIX A: REVISION HISTORY
Revision F (September 2009)
The following is the list of modifications:
1. Corrected RL text in Figure 2-22 in Section 2.0
“Typical Performance Curves”.
2. Corrected
devices’
pins
in
Table 3-1
(Section 3.0 “Pin Descriptions”).
3. Updated Section 6.0 “Packaging Informa-
tion”. Updated package outline drawings.
Revision E (March 2008)
The following is the list of modifications:
1. Increased maximum operating VDD
2. Added test circuits.
.
3. Updated performance curves.
4. Added Figure 2-31.
5. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, ad Section 4.1.3 “Normal Opera-
tion”.
6. Updated Section 5.0 “Design Aids”
7. Updated Section 6.0 “Packaging Informa-
tion”. Updated package outline drawings.
Revision D (February 2005)
The following is the list of modifications:
1. Added Section 3.0 “Pin Descriptions”.
2. Updated Section 4.0 “Applications Information”.
3. Added Section 4.3 “Capacitive Loads”
4. Updated Section 5.0 “Design Aids” to include
FilterLab® and to point to the latest SPICE
macro model.
5. Corrected and updated Section 6.0 “Packaging
Information”.
6. Added Appendix A: “Revision History”.
Revision C (January 2001)
• Undocumented changes
Revision B (May 2000)
• Undocumented changes
Revision A (January 2000)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS11177F-page 37
MCP606/7/8/9
NOTES:
DS11177F-page 38
© 2009 Microchip Technology Inc.
MCP606/7/8/9
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Examples:
a)
b)
c)
MCP606-I/P:
Industrial Temperature,
8LD PDIP package.
Temperature Package
Range
MCP606-I/SN: Industrial Temperature,
8LD SOIC package.
MCP606T-I/SN: Tape and Reel,
Industrial Temperature,
Device
MCP606
MCP606T = Single Op Amp
Tape and Reel (SOIC, TSSOP)
Dual Op Amp
MCP607T = Dual Op Amp
Tape and Reel (SOIC, TSSOP)
Single Op Amp with CS
= Single Op Amp
8LD SOIC package.
Industrial Temperature,
8LD TSSOP package.
d)
e)
MCP606-I/ST:
MCP607
=
MCP606T-I/OT: Tape and Reel,
Industrial Temperature,
MCP608
=
MCP608T = Single Op Amp with CS
Tape and Reel (SOIC, TSSOP)
5LD SOT-23 package.
MCP609
MCP609T = Quad Op Amp
Tape and Reel (SOIC, TSSOP)
= Quad Op Amp
a)
b)
MCP607-I/P:
Industrial Temperature,
8LD PDIP package.
MCP607T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC package.
Temperature Range
Package
I
=
-40°C to +85°C
a)
b)
MCP608-I/SN: Industrial Temperature,
8LD SOIC package.
MCP608T-I/SN: Tape and Reel,
Industrial Temperature,
OT
P
SN
SL
ST
=
=
=
=
=
Plastic SOT-23, 5-lead
Plastic DIP (300 mil Body), 8-lead, 14-lead
Plastic SOIC (3.90 mm body), 8-lead
Plastic SOIC (3.90 mm body), 14-lead
Plastic TSSOP, 8-lead, 14-lead
8LD SOIC package.
a)
b)
MCP609-I/P:
Industrial Temperature,
14LD PDIP package.
MCP609T-I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC package.
© 2009 Microchip Technology Inc.
DS11177F-page 39
MCP606/7/8/9
NOTES:
DS11177F-page 40
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
DS11177F-page 41
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Boston
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Korea - Seoul
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Cleveland
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Independence, OH
Tel: 216-447-0464
Fax: 216-447-0643
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Detroit
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Farmington Hills, MI
Tel: 248-538-2250
Fax: 248-538-2260
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Kokomo
Kokomo, IN
Tel: 765-864-8360
Fax: 765-864-8387
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Santa Clara
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Santa Clara, CA
Tel: 408-961-6444
Fax: 408-961-6445
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
03/26/09
DS11177F-page 42
© 2009 Microchip Technology Inc.
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