MCP6231U [MICROCHIP]
The Microchip Technology Inc. MCP6231/1R/1U/2/4 operational amplifiers (op amps) family has a 300 ;
| 型号： | MCP6231U |
| 厂家： | 
MICROCHIP |
| 描述： | The Microchip Technology Inc. MCP6231/1R/1U/2/4 operational amplifiers (op amps) family has a 300 放大器 运算放大器 放大器电路 |
| 文件： | 总20页 (文件大小：337K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MCP6231/2
20 µA, 300 kHz Rail-to-Rail Op Amp
Features
Description
• Gain Bandwidth Product: 300 kHz (typ.)
• Supply Current: IQ = 20 µA (typ.)
The Microchip Technology Inc. MCP6231/2 opera-
tional amplifiers (op amps) provide wide bandwidth for
the quiescent current. The MCP6231/2 family has a
300 kHz Gain Bandwidth Product (GBWP) and 65°
(typ.) phase margin. This family operates from a single
supply voltage as low as 1.8V, while drawing 20 µA
(typ.) quiescent current. In addition, the MCP6231/2
family supports rail-to-rail input and output swing, with
a common mode input voltage range of VDD + 300 mV
to VSS – 300 mV. These op amps are designed in one
of Microchip’s advanced CMOS processes.
• Supply Voltage: 1.8V to 5.5V
• Rail-to-Rail Input/Output
• Extended Temperature Range: -40°C to +125°C
• Available in 5-Pin SC-70 and SOT-23 packages
Applications
• Automotive
• Portable Equipment
• Transimpedance amplifiers
• Analog Filters
Package Types
MCP6231
MCP6231R
• Notebooks and PDAs
• Battery-Powered Systems
SOT-23-5
SOT-23-5
VDD
VOUT
VDD
VSS
VOUT
VSS
1
2
3
5
4
1
5
4
Available Tools
2
3
–
–
VIN
+
VIN
–
VIN
+
VIN–
SPICE Macro Models (at www.microchip.com)
FilterLab® Software (at www.microchip.com)
MCP6231U
SC-70-5, SOT-23-5
MCP6231
PDIP, SOIC, MSOP
Typical Application
VDD
R
VIN
VSS
VIN
+
1
2
3
4
8
7
6
5
NC
NC
1
2
3
5
G2
+
V
VDD
VIN
–
+
–
+
IN2
–
R
G1
VIN
VOUT
NC
–
4
VOUT
V
VSS
IN1
R
F
V
MCP6232
PDIP, SOIC, MSOP
DD
–
R
R
X
Y
V
OUT
MCP6231
+
V
V
V
8
7
6
5
OUTA
1
2
DD
_
A
V
R
-
+
INA
Z
OUTB
B
_
V
+ 3
4
+
-
V
V
INA
INB
V
+
SS
INB
Summing Amplifier Circuit
2004 Microchip Technology Inc.
DS21881B-page 1
MCP6231/2
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to maximum rating conditions for extended periods
may affect device reliability.
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
V
- V .........................................................................7.0V
SS
DD
All Inputs and Outputs ................... V – 0.3V to V + 0.3V
SS
DD
PIN FUNCTION TABLE
Difference Input Voltage ...................................... |V – V
|
DD
SS
Output Short Circuit Current ..................................continuous
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Name
VIN+, VINA+, VINB
VIN–, VINA–, VINB
VDD
Function
Non-inverting Input
Inverting Input
+
–
Positive Power Supply
Negative Power Supply
Maximum Junction Temperature (T )..........................+150°C
J
VSS
ESD Protection On All Pins (HBM;MM) ............... ≥ 4 kV; 400V
VOUT, VOUTA, VOUTB Output
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, T = +25°C, V = +1.8V to +5.5V, V = GND, V
= V /2, R = 100 kΩ
DD L
A
DD
SS
CM
to V /2 and VOUT ≈ V /2.
DD
DD
Parameters
Sym
Min
Typ
Max
Units
Conditions
Input Offset
Input Offset Voltage
Extended Temperature
V
V
–5.0
–7.0
—
—
—
+5.0
+7.0
—
mV
mV
V
= V
OS
CM SS
T = –40°C to +125°C (Note)
OS
A
Input Offset Drift with Temperature
∆V /∆T
±3.0
µV/°C T = –40°C to +125°C,
A
OS
A
V
= V
CM
SS
Power Supply Rejection
Input Bias Current and Impedance
Input Bias Current:
PSRR
—
83
—
dB
V
= V
CM
SS
I
I
I
—
—
—
—
—
—
±1.0
20
—
—
—
—
—
—
pA
pA
B
B
B
At Temperature
T = +85°C
A
At Temperature
1100
±1.0
pA
T = +125°C
A
Input Offset Current
I
pA
OS
13
Common Mode Input Impedance
Differential Input Impedance
Common Mode
Z
10 ||6
Ω||pF
Ω||pF
CM
13
Z
10 ||3
DIFF
Common Mode Input Range
Common Mode Rejection Ratio
Open-Loop Gain
V
V
– 0.3
—
V
+ 0.3
DD
V
CMR
SS
CMRR
61
75
—
dB
V
= –0.3V to 5.3V, V = 5V
CM DD
DC Open-Loop Gain (large signal)
A
90
110
—
dB
V
V
= 0.3V to V – 0.3V,
OL
OUT
DD
= V
CM
SS
Output
Maximum Output Voltage Swing
Output Short-Circuit Current
V
, V
V
+ 35
—
±6
V
– 35
mV
mA
mA
R =10 kΩ, 0.5V Output Overdrive
L
OL
OH
SS
DD
I
I
—
—
—
—
V
V
= 1.8V
= 5.5V
SC
SC
DD
DD
±23
Power Supply
Supply Voltage
V
1.8
10
—
5.5
30
V
DD
Quiescent Current per Amplifier
I
20
µA
I
= 0, V
= V – 0.5V
Q
O
CM DD
Note:
The SC-70 package is only tested at +25°C.
DS21881B-page 2
2004 Microchip Technology Inc.
MCP6231/2
AC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +1.8 to 5.5V, VSS = GND, VCM = VDD/2,
VOUT ≈ VDD/2, RL = 100 kΩ to VDD/2 and CL = 60 pF.
Parameters
Sym
Min
Typ
Max
Units
Conditions
AC Response
Gain Bandwidth Product
Phase Margin
GBWP
PM
—
—
—
300
65
—
—
—
kHz
°
G = +1
Slew Rate
SR
0.10
V/µs
Noise
Input Noise Voltage
Input Noise Voltage Density
Input Noise Current Density
Eni
eni
ini
—
—
—
6.0
52
—
—
—
µVp-p f = 0.1 Hz to 10 Hz
nV/√Hz f = 1 kHz
0.6
fA/√Hz f = 1 kHz
TEMPERATURE SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, VDD = +1.8V to +5.5V and VSS = GND.
Parameters
Temperature Ranges
Sym
Min
Typ
Max
Units
Conditions
Extended Temperature Range
Operating Temperature Range
Storage Temperature Range
Thermal Package Resistances
Thermal Resistance, 5L-SC70
Thermal Resistance, 5L-SOT-23
Thermal Resistance, 8L-PDIP
Thermal Resistance, 8L-SOIC
Thermal Resistance, 8L-MSOP
TA
TA
TA
–40
–40
–65
—
—
—
+125
+125
+150
°C
°C
°C
Note
—
—
—
—
—
—
—
—
—
—
θJA
θJA
θJA
θJA
θJA
331
256
85
°C/W
°C/W
°C/W
°C/W
°C/W
163
206
Note:
The internal Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
2004 Microchip Technology Inc.
DS21881B-page 3
MCP6231/2
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
20%
90
630 Samples
VDD = 5.0V
18%
VCM = VSS
16%
85
PSRR (VCM = VSS
)
14%
12%
10%
8%
80
75
70
6%
CMRR (VCM = -0.3 V to +5.3 V)
4%
2%
0%
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
Input Offset Voltage (mV)
FIGURE 2-1:
Input Offset Voltage.
FIGURE 2-4:
CMRR, PSRR vs. Ambient
Temperature.
100
90
80
70
60
50
40
30
120
100
80
0
RL = 100.0 kΩ
VDD = 5.0V
VDD = 5.0V
PSRR-
PSRR+
-30
Gain
V
CM = VDD/2
-60
CMRR
60
-90
Phase
40
20
0
-120
-150
-180
-210
20 1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
-20
10
100
1k
10k
100k
0.1
1
10 100 1k 10k 100k 1M 10M
Frequency (Hz)
Frequency (Hz)
FIGURE 2-2:
PSRR, CMRR vs.
FIGURE 2-5:
Open-Loop Gain, Phase vs.
Frequency.
Frequency.
22%
20%
18%
16%
14%
12%
10%
8%
30%
25%
20%
15%
10%
5%
630 Samples
VCM = VSS
TA = +85°C
632 Samples
V
CM = VSS
TA = +125°C
6%
4%
2%
0%
0%
Input Bias Current (pA)
Input Bias Current (nA)
FIGURE 2-3:
Input Bias Current at +85°C.
FIGURE 2-6:
Input Bias Current at +125°C.
DS21881B-page 4
2004 Microchip Technology Inc.
MCP6231/2
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
1,000
100
10
20%
18%
16%
14%
12%
10%
8%
628 Samples
CM = VSS
TA = -40°C to +125°C
V
6%
4%
2%
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
0%
0.1
1
10
100
1k
10k 100k
Frequency (Hz)
Input Offset Voltage Drift (µV/°C)
FIGURE 2-7:
Input Noise Voltage Density
FIGURE 2-10:
Input Offset Voltage Drift.
vs. Frequency.
100
50
550
450
350
250
VCM = VSS
TA = +125°C
TA = +85°C
0
TA = +25°C
A = -40°C
-50
-100
-150
-200
T
VDD = 5.5 V
VDD = 1.8 V
VDD = 1.8 V
-250
-300
150
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-11:
Input Offset Voltage vs.
FIGURE 2-8:
Input Offset Voltage vs.
Output Voltage.
Common Mode Input Voltage at VDD = 1.8V.
30
25
20
15
10
5
300
+ISC
TA = +125°C
TA = +85°C
200
T
T
A = +25°C
A = -40°C
100
0
TA = +125°C
T
T
A = +85°C
A = +25°C
0
-5
TA = -40°C
-10
-15
-20
-25
-30
-100
-200
-300
VDD = 5.5 V
-ISC
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
Common Mode Input Voltage (V)
FIGURE 2-12:
Output Short-Circuit Current
FIGURE 2-9:
Input Offset Voltage vs.
vs. Ambient Temperature.
Common Mode Input Voltage at VDD = 5.5V.
2004 Microchip Technology Inc.
DS21881B-page 5
MCP6231/2
Note: Unless otherwise indicated, TA = +25°C, VDD = +1.8V to +5.5V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,
RL = 100 kΩ to VDD/2 and CL = 60 pF.
120.00
0.30
G = +1 V/V
RL = 10 kΩ
Falling Edge, VDD = 5.5 V
100.00
0.25
0.20
0.15
0.10
0.05
Falling Edge, VDD = 1.8 V
80.00
60.00
40.00
20.00
0.00
Rising Edge, VDD = 5.5 V
Rising Edge, VDD = 1.8 V
-20.00
-9.E+00
-40.00
1.E+00
1.E+01
2.E+01
3.E+01
-50
-25
0
25
50
75
100 125
Time (1 µs/div)
Ambient Temperature (°C)
FIGURE 2-13:
Slew Rate vs. Ambient
FIGURE 2-16:
Small Signal Non-Inverting
Temperature.
Pulse Response.
5.0
1,000
100
10
G = +1 V/V
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
VDD - VOH
VOL - VSS
1
0.0001
0.001
0.01
0.1
10
0.1µ
1µ
10µ
100µ
11m
10m
-2.E+01
0.E+00
2.E+01
4.E+01
6.E+01
8.E+01
1.E+02
1.E+02
1.E+02
Time (20 µs/div)
Output Current Magnitude (A)
FIGURE 2-14:
Output Voltage Headroom
FIGURE 2-17:
Large Signal Non-Inverting
vs. Output Current Magnitude.
Pulse Response.
30
10
VCM = VDD - 0.5
25
20
15
10
5
VDD = 5.5 V
VDD = 1.8 V
1
TA = +125°C
T
A = +85°C
TA = +25°C
A = -40°C
T
0
0.1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Power Supply Voltage (V)
100k
100000
1M
1000000
1k
10k
10000
1000
Frequency (Hz)
FIGURE 2-15:
Output Voltage Swing vs.
FIGURE 2-18:
Quiescent Current vs.
Frequency.
Power Supply Voltage.
DS21881B-page 6
2004 Microchip Technology Inc.
MCP6231/2
3.0
APPLICATION INFORMATION
–
The MCP6231/2 family of op amps is manufactured
using Microchip’s state-of-the-art CMOS process and
is specifically designed for low-cost, low-power and
general-purpose applications. The low supply voltage,
low quiescent current and wide bandwidth makes the
MCP6231/2 ideal for battery-powered applications.
VOUT
RIN
MCP623X
+
VIN
(Maximum expected VIN) – VDD
------------------------------------------------------------------------------
2 mA
RIN
≥
3.1
Rail-to-Rail Input
VSS – (Minimum expected VIN
)
The MCP6231/2 op amps are designed to prevent
phase reversal when the input pins exceed the supply
voltages. Figure 3-1 shows the input voltage exceeding
the supply voltage without any phase reversal.
---------------------------------------------------------------------------
RIN
≥
2 mA
FIGURE 3-2:
Input Current-Limiting
Resistor (RIN).
6
VIN
VDD = 5.0V
G = +2 V/V
3.2
Rail-to-Rail Output
5
4
VOUT
The output voltage range of the MCP6231/2 op amps
is VDD – 35 mV (min.) and VSS + 35 mV (max.) when
RL = 10 kΩ is connected to VDD/2 and VDD = 5.5V.
Refer to Figure 2-14 for more information.
3
2
1
3.3
Capacitive Loads
0
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produces gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, but all gains show the
same general behavior.
-1 0.E+00
1.E+00
2.E+00
3.E+00
4.E+00
5.E+00
6.E+00
7.E+00
8.E+00
9.E+00
1.E+01
Time (1 ms/div)
FIGURE 3-1:
Phase Reversal.
The MCP6231/2 Show No
The input stage of the MCP6231/2 op amps use two
differential input stages in parallel. One operates at low
common mode input voltage (VCM) and the other at
high VCM. With this topology, the device operates with
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 3-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. It does not,
however, improve the bandwidth.
VCM up to 300 mV above VDD and 300 mV below VSS
.
The input offset voltage is measured at
VCM = VSS – 300 mV and VDD + 300 mV to ensure
proper operation.
Input voltages that exceed the input voltage range
(VSS – 0.3V to VDD + 0.3V at 25°C) can cause
excessive current to flow into or out of the input pins.
Current beyond ±2 mA can cause reliability problems.
Applications that exceed this rating must be externally
limited with a resistor, as shown in Figure 3-2.
–
RISO
VOUT
MCP623X
+
VIN
CL
FIGURE 3-3:
Output resistor, RISO
stabilizes large capacitive loads.
Figure 3-4 gives recommended RISO values for
different capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit’s noise gain. For non-inverting gains, GN and the
gain are equal. For inverting gains, GN is 1 + |Gain|
(e.g., –1 V/V gives GN = +2 V/V).
2004 Microchip Technology Inc.
DS21881B-page 7
MCP6231/2
The easiest way to reduce surface leakage is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 3-5.
1.E+04
10k
1.E+03
1k
VIN–
VIN+
GN = 1 V/V
VSS
GN = 2 V/V
GN ≥ 4 V/V
100
1.E+02
1.E+01
1.E+02
1.E+03
1.E+04
10p
100p
1n
10n
Normalized Load Capacitance; CL/GN (F)
FIGURE 3-4:
Recommended RISO Values
for Capactive Loads.
Guard Ring
Example Guard Ring Layout
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Evaluation on the bench and
simulations with the MCP6231/2 SPICE macro model
are very helpful. Modify RISO’s value until the response
is reasonable.
FIGURE 3-5:
for Inverting Gain.
1. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pin (VIN+) to the
input with a wire that does not touch the
PCB surface.
3.4
Supply Bypass
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
With this op amp, the power supply pin (VDD for
single-supply) should have a local bypass capacitor
(i.e., 0.01 µF to 0.1 µF) within 2 mm for good high-
frequency performance. It also needs a bulk capacitor
(i.e., 1 µF or larger) within 100 mm to provide large,
slow currents. This bulk capacitor can be shared with
other parts.
2. Inverting and transimpedance gain amplifiers
(convert current to voltage, such as photo
detectors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
3.5
PCB Surface Leakage
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA, if current-to-flow. This is greater than the
MCP6231/2 family’s bias current at 25°C (1 pA, typ).
DS21881B-page 8
2004 Microchip Technology Inc.
MCP6231/2
4.2
Compensating for the Parasitic
Capacitance
4.0
4.1
APPLICATION CIRCUITS
Matching the Impedance at the
Inputs
In analog circuit design, the PCB parasitic capacitance
can compromise the circuit behavior; Figure 4-2 shows
a typical scenario. If the input of an amplifier sees
To minimize the effect of input bias current in an
amplifier circuit (this is important for very high source-
impedance applications, such as pH meters and
transimpedance amplifiers), the impedance at both
inverting and non-inverting inputs needs to be
matched. This is done by choosing the circuit resistor
values so that the total resistance at each input is the
same. Figure 4-1 shows a summing amplifier circuit.
parasitic capacitance of several picofarad (CPARA
,
which includes the common mode capacitance of 6 pF,
typical), and large RF and RG, the frequency response
of the circuit will include a zero. This parasitic zero
introduces gain peaking and can cause circuit
instability.
R
G2
V
+
AC
V
V
IN2
IN1
V
R
MCP623X
–
OUT
G1
R
F
R
R
G
F
V
DD
–
V
DC
R
X
Y
V
OUT
MCP623X
+
C
R
PARA
R
C
Z
F
RG
------
RF
CF = CPARA
•
FIGURE 4-2:
Capacitance at the Input.
Effect of Parasitic
FIGURE 4-1:
Summing Amplifier Circuit.
To match the inputs, set all voltage sources to ground
and calculate the total resistance at the input nodes. In
this summing amplifier circuit, the resistance at the
inverting input is calculated by setting VIN1, VIN2 and
VOUT to ground. In this case, RG1, RG2 and RF are in
parallel. The total resistance at the inverting input is:
One solution is to use smaller resistor values to push
the zero to a higher frequency. Another solution is to
compensate by introducing a pole at the point at which
the zero occurs. This can be done by adding CF in
parallel with the feedback resistor (RF). CF needs to be
selected so that the ratio CPARA:CF is equal to the ratio
of RF:RG.
1
---------------------------------------------
RVIN- =
1
1
1
--------- --------- ------
+
+
RG1 RG2 RF
Where:
RVIN– = total resistance at the inverting input
At the non-inverting input, VDD is the only voltage
source. When VDD is set to ground, both Rx and Ry are
in parallel. The total resistance at the non-inverting
input is:
1
------------------------
RVIN
=
+ RZ
+
1
1
------ -----
+
RX RY
Where:
+
RVIN = total resistance at the inverting
input
To minimize output offset voltage and increase circuit
accuracy, the resistor values need to meet the
conditions:
-
RVIN = RVIN
+
2004 Microchip Technology Inc.
DS21881B-page 9
MCP6231/2
5.0
DESIGN TOOLS
Microchip provides the basic design tools needed for
the MCP6231/2 family of op amps.
5.1
SPICE Macro Model
The latest SPICE macro model for the MCP6231/2 op
amps is available on our web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation at room temperature. See the model
file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
®
5.2
FilterLab Software
The FilterLab software is an innovative tool that simpli-
fies analog active-filter (using op amps) design.
Available free of charge from our web site at
www.microchip.com, the FilterLab software active-filter
design tool provides full schematic diagrams of the filter
circuit with component values. It also outputs the filter
circuit in SPICE format, which can be used with the
macro model to simulate actual filter performance.
DS21881B-page 10
2004 Microchip Technology Inc.
MCP6231/2
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
5-Lead SC-70 (MCP6231U Only)
Example:
XNN
YWW
ASN
418
Example:
5
5-Lead SOT-23
5
4
3
4
3
Device
MCP6231
Code
BCNN
BDNN
BENN
AA07
XXNN
MCP6231R
MCP6231U
1
2
1
2
Note:
Applies to 5-Lead SOT-23.
Example:
8-Lead MSOP
XXXXXX
YWWNNN
6232E
418256
8-Lead PDIP (300 mil)
Example:
MCP6232
XXXXXXXX
XXXXXNNN
E/P256
0418
YYWW
8-Lead SOIC (150 mil)
Example:
XXXXXXXX
XXXXYYWW
MCP6232
E/SN0418
NNN
256
Legend: XX...X Customer specific information*
YY
WW
NNN
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line thus limiting the number of available characters
for customer specific information.
*
Standard marking consists of Microchip part number, year code, week code, traceability code (facility
code, mask rev#, and assembly code). For marking beyond this, certain price adders apply. Please
check with your Microchip Sales Office.
2004 Microchip Technology Inc.
DS21881B-page 11
MCP6231/2
5-Lead Small Outline Transistor Package (SC-70)
E
E1
D
p
B
n
1
Q1
A2
A
c
A1
L
Units
INCHES
NOM
5
MILLIMETERS*
Dimension Limits
MIN
MAX
MIN
NOM
5
MAX
n
p
Number of Pins
Pitch
.026 (BSC)
0.65 (BSC)
Overall Height
A
.031
.043
0.80
1.10
1.00
0.10
2.40
1.35
2.20
0.30
0.40
0.18
0.30
Molded Package Thickness
Standoff
A2
A1
E
.031
.000
.071
.045
.071
.004
.004
.004
.006
.039
.004
.094
.053
.087
.012
.016
.007
.012
0.80
0.00
1.80
1.15
1.80
0.10
0.10
0.10
0.15
Overall Width
Molded Package Width
Overall Length
E1
D
Foot Length
L
Q1
c
Top of Molded Pkg to Lead Shoulder
Lead Thickness
Lead Width
B
*Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
JEITA (EIAJ) Standard: SC-70
Drawing No. C04-061
DS21881B-page 12
2004 Microchip Technology Inc.
MCP6231/2
5-Lead Plastic Small Outline Transistor (OT) (SOT23)
E
E1
p
B
p1
D
n
1
α
c
A
A2
φ
A1
L
β
Units
Dimension Limits
INCHES*
NOM
5
MILLIMETERS
MIN
MAX
MIN
NOM
5
MAX
n
p
Number of Pins
Pitch
.038
0.95
p1
Outside lead pitch (basic)
Overall Height
.075
.046
.043
.003
.110
.064
.116
.018
5
1.90
1.18
1.10
0.08
2.80
1.63
2.95
0.45
5
A
A2
A1
E
.035
.035
.000
.102
.059
.110
.014
0
.057
0.90
1.45
Molded Package Thickness
Standoff
.051
.006
.118
.069
.122
.022
10
0.90
0.00
2.60
1.50
2.80
0.35
0
1.30
0.15
3.00
1.75
3.10
0.55
10
Overall Width
Molded Package Width
Overall Length
Foot Length
E1
D
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.004
.014
0
.006
.017
5
.008
.020
10
0.09
0.35
0
0.15
0.43
5
0.20
0.50
10
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
0
5
10
0
5
10
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .005" (0.127mm) per side.
EIAJ Equivalent: SC-74A
Drawing No. C04-091
2004 Microchip Technology Inc.
DS21881B-page 13
MCP6231/2
8-Lead Plastic Micro Small Outline Package (MS) (MSOP)
E
E1
p
D
2
B
n
1
α
A2
A
c
φ
A1
(F)
L
β
Units
Dimension Limits
INCHES
NOM
8
MILLIMETERS*
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
.026 BSC
0.65 BSC
Overall Height
A
A2
A1
E
-
-
.043
-
-
1.10
Molded Package Thickness
Standoff
.030
.000
.033
.037
.006
0.75
0.85
0.95
0.15
-
0.00
-
Overall Width
.193 TYP.
4.90 BSC
Molded Package Width
Overall Length
Foot Length
E1
D
.118 BSC
3.00 BSC
.118 BSC
3.00 BSC
L
.016
.024
.031
0.40
0.60
0.80
Footprint (Reference)
Foot Angle
F
.037 REF
0.95 REF
φ
c
0°
.003
.009
5°
-
.006
.012
-
8°
.009
.016
15°
0°
0.08
0.22
5°
-
-
-
-
-
8°
0.23
0.40
15°
Lead Thickness
Lead Width
B
α
β
Mold Draft Angle Top
Mold Draft Angle Bottom
*Controlling Parameter
Notes:
5°
-
15°
5°
15°
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not
exceed .010" (0.254mm) per side.
JEDEC Equivalent: MO-187
Drawing No. C04-111
DS21881B-page 14
2004 Microchip Technology Inc.
MCP6231/2
8-Lead Plastic Dual In-line (P) – 300 mil (PDIP)
E1
D
2
n
1
α
E
A2
A
L
c
A1
β
B1
B
p
eB
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
MAX
n
p
Number of Pins
Pitch
8
8
.100
.155
.130
2.54
3.94
3.30
Top to Seating Plane
A
.140
.170
3.56
4.32
Molded Package Thickness
Base to Seating Plane
Shoulder to Shoulder Width
Molded Package Width
Overall Length
A2
A1
E
.115
.015
.300
.240
.360
.125
.008
.045
.014
.310
5
.145
2.92
0.38
7.62
6.10
9.14
3.18
0.20
1.14
0.36
7.87
5
3.68
.313
.250
.373
.130
.012
.058
.018
.370
10
.325
.260
.385
.135
.015
.070
.022
.430
15
7.94
6.35
9.46
3.30
0.29
1.46
0.46
9.40
10
8.26
6.60
9.78
3.43
0.38
1.78
0.56
10.92
15
E1
D
Tip to Seating Plane
Lead Thickness
L
c
Upper Lead Width
B1
B
Lower Lead Width
Overall Row Spacing
Mold Draft Angle Top
Mold Draft Angle Bottom
§
eB
α
β
5
10
15
5
10
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-001
Drawing No. C04-018
2004 Microchip Technology Inc.
DS21881B-page 15
MCP6231/2
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC)
E
E1
p
D
2
B
n
1
h
α
45°
c
A2
A
φ
β
L
A1
Units
INCHES*
NOM
MILLIMETERS
Dimension Limits
MIN
MAX
MIN
NOM
8
MAX
n
p
Number of Pins
Pitch
8
.050
.061
.056
.007
.237
.154
.193
.015
.025
4
1.27
Overall Height
A
.053
.069
1.35
1.32
1.55
1.42
0.18
6.02
3.91
4.90
0.38
0.62
4
1.75
Molded Package Thickness
Standoff
A2
A1
E
.052
.004
.228
.146
.189
.010
.019
0
.061
.010
.244
.157
.197
.020
.030
8
1.55
0.25
6.20
3.99
5.00
0.51
0.76
8
§
0.10
5.79
3.71
4.80
0.25
0.48
0
Overall Width
Molded Package Width
Overall Length
E1
D
Chamfer Distance
Foot Length
h
L
φ
Foot Angle
c
Lead Thickness
Lead Width
.008
.013
0
.009
.017
12
.010
.020
15
0.20
0.33
0
0.23
0.42
12
0.25
0.51
15
B
α
Mold Draft Angle Top
Mold Draft Angle Bottom
β
0
12
15
0
12
15
* Controlling Parameter
§ Significant Characteristic
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
DS21881B-page 16
2004 Microchip Technology Inc.
MCP6231/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Examples:
a) MCP6231-E/SN:
PART NO.
Device
X
-X
/XX
Extended Temp.,
8LD SOIC pkg.
Tape and Reel
and/or
Alternate Pinout
Temperature Package
Range
b) MCP6231-E/MS: Extended Temp.,
8LD MSOP pkg.
c) MCP6231-E/P:
Extended Temp.,
8LD PDIP pkg.
Device:
MCP6231:
MCP6231T:
MCP6231RT:
MCP6231UT: Single Op Amp (Tape and Reel)
(SC-70, SOT-23)
MCP6232:
Single Op Amp (MSOP, PDIP, SOIC)
Single Op Amp (Tape and Reel) (SOT-23)
Single Op Amp (Tape and Reel) (SOT-23)
d) MCP6231RT-E/OT: Tape and Reel,
Extended Temp.,
5LD SOT-23 pkg
Dual Op Amp (MSOP, PDIP, SOIC)
Dual Op Amp (Tape and Reel)
e) MCP6231UT-E/OT: Tape and Reel,
Extended Temp.,
MCP6232T:
5LD SOT-23 pkg.
MCP6231UT-E/LT: Tape and Reel,
Extended Temp.,
Temperature Range:
Package:
E
=
-40°C to +125°C
f)
LT
MS
P
=
=
=
=
Plastic Package (SC-70), 5-lead (MCP6231U only)
Plastic Micro Small Outline (MSOP), 8-lead
Plastic DIP (300 mil Body), 8-lead
Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6231, MCP6231R, MCP6231U)
5LD SC-70 pkg.
g) MCP6231T-E/OT: Tape and Reel,
Extended Temp.,
OT
5LD SOT-23 pkg.
SN
=
Plastic SOIC, (150 mil Body), 8-lead
a) MCP6232-E/SN:
Extended Temp.,
8LD SOIC pkg.
b) MCP6232-E/MS: Extended Temp.,
8LD MSOP pkg.
c) MCP6232-E/P:
Extended Temp.,
8LD PDIP pkg.
d) MCP6232T-E/SN: Tape and Reel,
Extended Temp.,
SOIC pkg.
Sales and Support
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.
Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
2004 Microchip Technology Inc.
DS21881B-page 17
MCP6231/2
NOTES:
DS21881B-page 18
2004 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is intended through suggestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microchip Technology Incorporated with respect
to the accuracy or use of such information, or infringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro,
PICSTART, PRO MATE, PowerSmart, rfPIC, and
SmartShunt are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPASM,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2004 Microchip Technology Inc.
DS21881B-page 19
WORLDWIDE SALES AND SERVICE
China - Chengdu
Taiwan
AMERICAS
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Kaohsiung Branch
Kaohsiung 806, Taiwan
Tel: 886-7-536-4816
Fax: 886-7-536-4817
Ming Xing Financial Tower
Chengdu 610016, China
Tel: 86-28-86766200
Fax: 86-28-86766599
Taiwan
Fax: 480-792-7277
Technical Support: 480-792-7627
Web Address: www.microchip.com
China - Fuzhou
World Trade Plaza
Fuzhou 350001, China
Tel: 86-591-7503506
Fax: 86-591-7503521
Taiwan Branch
Taipei City, 104, Taiwan
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Atlanta
Alpharetta, GA 30022
Tel: 770-640-0034
Fax: 770-640-0307
Taiwan
Taiwan Branch
Hsinchu City 300, Taiwan
Tel: 886-3-572-9526
Fax: 886-3-572-6459
China - Hong Kong SAR
Metroplaza
Kwai Fong, N.T., Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
Boston
Westford, MA 01886
Tel: 978-692-3848
Fax: 978-692-3821
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Far East International Plaza
Shanghai, 200051
Tel: 86-21-6275-5700
Fax: 86-21-6275-5060
EUROPE
Austria
Austria
Tel: 43-7242-2244-399
Fax: 43-7242-2244-393
Chicago
Itasca, IL 60143
Tel: 630-285-0071
Fax: 630-285-0075
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Tel: 86-755-82901380
Fax: 86-755-8295-1393
Dallas
Denmark
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Fax: 972-818-2924
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Fax: 248-538-2260
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Italy
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Tel: 949-462-9523
India
Milan, Italy
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Tel: 39-0331-742611
Fax: 39-0331-466781
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Tel: 91-80-22290061 Fax: 91-80-22290062
Fax: 949-462-9608
Netherlands
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Tel: 31-416-690399
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Tel: 650-215-1444
India
International Trade Tower
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Tel: +91-11-5160-8632
Fax: +91-11-5160-8632
Fax: 31-416-690340
Fax: 650-961-0286
United Kingdom
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Berkshire, England RG41 5TU
Tel: 44-118-921-5869
Fax: 44-118-921-5820
Toronto
Mississauga, Ontario L4V 1X5, Canada
Tel: 905-673-0699
Japan
Yokohama, Kanagawa, 222-0033, Japan
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Fax: 905-673-6509
ASIA/PACIFIC
Australia
Microchip Technology Australia Pty Ltd
Sydney, Australia
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
Korea
Samsung-Dong, Kangnam-Ku
Seoul, Korea 135-882
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or 82-2-558-5934
Singapore
China - Beijing
Singapore, 188980
Tel: 65-6334-8870
Fax: 65-6334-8850
Wan Tai Bei Hai Bldg.
Beijing, 100027, China
Tel: 86-10-85282100
Fax: 86-10-85282104
08/16/04
DS21881B-page 20
2004 Microchip Technology Inc.
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