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MCP6282T-E/CH [MICROCHIP]

450 μA, 5 MHz Rail-to-Rail Op Amp; 450 μA ， 5 MHz的轨至轨运算放大器
MCP6282T-E/CH
型号： MCP6282T-E/CH
厂家： MICROCHIP    MICROCHIP
描述：

450 μA, 5 MHz Rail-to-Rail Op Amp
450 μA ， 5 MHz的轨至轨运算放大器

运算放大器
文件： 总36页 (文件大小：628K)
中文：  中文翻译
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MCP6281/1R/2/3/4/5  
450 µA, 5 MHz Rail-to-Rail Op Amp  
Description  
Features  
• Gain Bandwidth Product: 5 MHz (typical)  
• Supply Current: IQ = 450 µA (typical)  
• Supply Voltage: 2.2V to 6.0V  
The Microchip Technology Inc. MCP6281/1R/2/3/4/5  
family of operational amplifiers (op amps) provide wide  
bandwidth for the current. This family has a 5 MHz Gain  
Bandwidth Product (GBWP) and a 65° phase margin.  
This family also operates from a single supply voltage  
as low as 2.2V, while drawing 450 µA (typical) quiescent  
current. Additionally, the MCP6281/1R/2/3/4/5 supports  
rail-to-rail input and output swing, with a common mode  
• Rail-to-Rail Input/Output  
• Extended Temperature Range: -40°C to +125°C  
• Available in Single, Dual, and Quad Packages  
• Single with CS (MCP6283)  
input voltage range of V + 300 mV to V – 300 mV.  
This family of operational amplifiers is designed with  
Microchip’s advanced CMOS process.  
DD  
SS  
• Dual with CS (MCP6285)  
Applications  
The MCP6285 has a Chip Select (CS) input for dual op  
amps in an 8-pin package. This device is manufactured  
by cascading the two op amps (the output of op amp A  
connected to the non-inverting input of op amp B). The  
CS input puts the device in Low-power mode.  
• Automotive  
• Portable Equipment  
• Photodiode Amplifier  
• Analog Filters  
• Notebooks and PDAs  
• Battery-Powered Systems  
The MCP6281/1R/2/3/4/5 family operates over the  
Extended Temperature Range of -40°C to +125°C. It  
also has a power supply range of 2.2V to 6.0V.  
Design Aids  
• SPICE Macro Models  
• FilterLab® Software  
• Mindi™ Circuit Designer & Simulator  
• MAPS (Microchip Advanced Part Selector)  
• Analog Demonstration and Evaluation Boards  
• Application Notes  
Package Types  
MCP6281  
MCP6281  
MCP6281R  
MCP6282  
PDIP, SOIC, MSOP  
PDIP, SOIC, MSOP  
SOT-23-5  
SOT-23-5  
VOUTA  
1
2
3
4
8
7
6
5
NC  
VDD  
8
7
6
5
NC  
1
VDD  
VSS  
VOUT  
VSS  
VOUT  
VDD  
1
2
3
5
4
1
5
4
_
_
VIN  
VIN  
VSS  
VDD  
VOUT  
-
VINA  
2
-
VOUTB  
+
2
3
+
-
+
-
+
_
VINA+ 3  
+
-
VINB  
VIN  
+
VIN  
–
VIN  
+
VIN–  
VSS  
4
NC  
VINB  
+
MCP6283  
PDIP, SOIC, MSOP  
MCP6283  
MCP6284  
PDIP, SOIC, TSSOP  
MCP6285  
PDIP, SOIC, MSOP  
SOT-23-6  
NC  
1
2
3
4
VOUTA  
8 CS  
V
14  
1
OUTD  
_
VOUTA/VINB  
+
VDD  
8
7
6
5
1
2
3
4
VDD  
CS  
VOUT  
VSS  
1
2
3
6
5
4
_
_
VIN  
VIN  
VSS  
VDD  
7
-
VINA  
2
+
13 VIND  
-
- +  
_
VOUTB  
VINA  
VINA  
VSS  
-
+
+
-
+
VOUT  
NC  
6
5
12  
VINA+ 3  
VIND  
+
_
_
VINB  
VIN  
+
+
-
VIN  
+
11  
VDD  
4
VSS  
CS  
10  
5
6
7
VINC  
+
_
VINB  
VINB  
+
_
-
-
+ +  
9
VINC  
VOUTB  
8 VOUTC  
© 2008 Microchip Technology Inc.  
DS21811E-page 1  
MCP6281/1R/2/3/4/5  
† Notice: Stresses above those listed under “Absolute  
Maximum Ratings” may cause permanent damage to the  
device. This is a stress rating only and functional operation of  
the device at those or any other conditions above those  
indicated in the operational listings of this specification is not  
implied. Exposure to maximum rating conditions for extended  
periods may affect device reliability.  
1.0  
ELECTRICAL  
CHARACTERISTICS  
Absolute Maximum Ratings †  
VDD – VSS ........................................................................7.0V  
Current at Input Pins ....................................................±2 mA  
Analog Inputs (VIN+, VIN–) †† ........ VSS – 1.0V to VDD + 1.0V  
All Other Inputs and Outputs ......... VSS – 0.3V to VDD + 0.3V  
†† See Section 4.1.2 “Input Voltage and Current Limits”.  
Difference Input Voltage ...................................... |VDD – VSS  
|
Output Short Circuit Current .................................Continuous  
Current at Output and Supply Pins ............................±30 mA  
Storage Temperature....................................–65°C to +150°C  
Maximum Junction Temperature (TJ)..........................+150°C  
ESD Protection On All Pins (HBM; MM) .............. ≥ 4 kV; 400V  
DC ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25 C, VDD = +2.2V to +5.5V, VSS = GND, VOUT ≈ VDD/2,  
V
CM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS is tied low. (refer to Figure 1-2 and Figure 1-3).  
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Input Offset  
Input Offset Voltage  
VOS  
VOS  
-3.0  
-5.0  
—
—
+3.0  
+5.0  
mV VCM = VSS (Note 1)  
Input Offset Voltage  
mV TA= -40°C to +125°C,  
(Extended Temperature)  
V
CM = VSS (Note 1)  
µV/°C TA= -40°C to +125°C,  
CM = VSS (Note 1)  
Input Offset Temperature Drift  
ΔVOS/ΔTA  
—
±1.7  
90  
—
—
V
Power Supply Rejection Ratio  
PSRR  
70  
dB  
VCM = VSS (Note 1)  
Input Bias, Input Offset Current and Impedance  
Input Bias Current  
IB  
IB  
—
—
—
—
—
—
±1.0  
50  
—
200  
5
pA  
pA  
nA  
pA  
Note 2  
At Temperature  
TA= +85°C (Note 2)  
TA= +125°C (Note 2)  
Note 3  
At Temperature  
IB  
2
Input Offset Current  
IOS  
ZCM  
ZDIFF  
±1.0  
1013||6  
1013||3  
—
—
—
Common Mode Input Impedance  
Differential Input Impedance  
Common Mode (Note 4)  
Common Mode Input Range  
Common Mode Rejection Ratio  
Common Mode Rejection Ratio  
Open-Loop Gain  
Ω||pF Note 3  
Ω||pF Note 3  
VCMR  
CMRR  
CMRR  
VSS − 0.3  
—
85  
80  
VDD + 0.3  
V
70  
65  
—
—
dB  
dB  
VCM = -0.3V to 2.5V, VDD = 5V  
VCM = -0.3V to 5.3V, VDD = 5V  
DC Open-Loop Gain (Large Signal)  
AOL  
90  
110  
—
dB  
VOUT = 0.2V to VDD – 0.2V,  
V
CM = VSS (Note 1)  
Output  
Maximum Output Voltage Swing  
Output Short Circuit Current  
Power Supply  
VOL, VOH VSS + 15  
—
VDD – 15  
—
mV 0.5V input overdrive  
mA  
ISC  
—
±25  
Supply Voltage  
VDD  
IQ  
2.2  
—
6.0  
V
(Note 5)  
Quiescent Current per Amplifier  
300  
450  
570  
µA  
IO = 0  
Note 1: The MCP6285’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.  
2: The current at the MCP6285’s VINB– pin is specified by IB only.  
3: This specification does not apply to the MCP6285’s VOUTA/VINB+ pin.  
4: The MCP6285’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV.  
The MCP6285’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL  
.
5: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,  
the other minimum and maximum specifications are measured at 2.4V and/or 5.5V.  
DS21811E-page 2  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
AC ELECTRICAL SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VOUT ≈ VDD/2,  
V
CM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. (refer to Figure 1-2 and Figure 1-3).  
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
AC Response  
Gain Bandwidth Product  
Phase Margin at Unity-Gain  
Slew Rate  
GBWP  
PM  
—
—
—
5.0  
65  
—
—
—
MHz  
°
G = +1 V/V  
SR  
2.5  
V/µs  
Noise  
Input Noise Voltage  
Input Noise Voltage Density  
Input Noise Current Density  
Eni  
eni  
ini  
—
—
—
5.2  
16  
3
—
—
—
µVP-P  
f = 0.1 Hz to 10 Hz  
nV/√Hz f = 1 kHz  
fA/√Hz f = 1 kHz  
MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VOUT ≈ VDD/2,  
CM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. (refer to Figure 1-2 and Figure 1-3).  
V
Parameters  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
CS Low Specifications  
CS Logic Threshold, Low  
VIL  
VSS  
—
—
0.2 VDD  
—
V
CS Input Current, Low  
ICSL  
0.01  
µA  
CS = VSS  
CS High Specifications  
CS Logic Threshold, High  
VIH  
ICSH  
ISS  
0.8 VDD  
—
VDD  
2
V
CS Input Current, High  
—
—
—
0.7  
µA  
µA  
µA  
CS = VDD  
CS = VDD  
CS = VDD  
GND Current per Amplifier  
-0.7  
0.01  
—
—
Amplifier Output Leakage  
—
Dynamic Specifications (Note 1)  
CS Low to Valid Amplifier  
Output, Turn-on Time  
tON  
—
4
10  
µs  
CS Low ≤ 0.2 VDD, G = +1 V/V,  
V
IN = VDD/2, VOUT = 0.9 VDD/2,  
V
DD = 5.0V  
CS High to Amplifier Output High-Z  
Hysteresis  
tOFF  
—
—
0.01  
0.6  
—
—
µs  
V
CS High ≥ 0.8 VDD, G = +1 V/V,  
IN = VDD/2, VOUT = 0.1 VDD/2  
V
VHYST  
VDD = 5V  
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested  
at the output of op amp B (VOUTB).  
CS  
VIL  
tON  
VIH  
tOFF  
Hi-Z  
Hi-Z  
VOUT  
-0.7 µA  
(typical)  
-0.7 µA  
(typical)  
-450 µA  
(typical)  
ISS  
0.7 µA  
(typical)  
0.7 µA  
(typical)  
10 nA  
(typical)  
ICS  
FIGURE 1-1:  
Timing Diagram for the Chip  
Select (CS) pin on the MCP6283 and MCP6285.  
© 2008 Microchip Technology Inc.  
DS21811E-page 3  
MCP6281/1R/2/3/4/5  
TEMPERATURE SPECIFICATIONS  
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND.  
Parameters  
Temperature Ranges  
Sym  
Min  
Typ  
Max  
Units  
Conditions  
Operating Temperature Range  
Storage Temperature Range  
Thermal Package Resistances  
Thermal Resistance, 5L-SOT-23  
Thermal Resistance, 6L-SOT-23  
Thermal Resistance, 8L-PDIP  
Thermal Resistance, 8L-SOIC  
Thermal Resistance, 8L-MSOP  
Thermal Resistance, 14L-PDIP  
Thermal Resistance, 14L-SOIC  
Thermal Resistance, 14L-TSSOP  
TA  
TA  
-40  
-65  
—
—
+125  
+150  
°C  
°C  
Note  
θJA  
θJA  
θJA  
θJA  
θJA  
θJA  
θJA  
θJA  
—
—
—
—
—
—
—
—
256  
230  
85  
—
—
—
—
—
—
—
—
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
163  
206  
70  
120  
100  
Note:  
The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.  
1.1  
Test Circuits  
The test circuits used for the DC and AC tests are  
shown in Figure 1-2 and Figure 1-2. The bypass  
capacitors are laid out according to the rules discussed  
in Section 4.6 “Supply Bypass”.  
VDD  
1 µF  
0.1 µF  
VIN  
VOUT  
RL  
RN  
RG  
MCP628X  
CL  
RF  
VDD/2  
VL  
FIGURE 1-2:  
AC and DC Test Circuit for  
Most Non-Inverting Gain Conditions.  
VDD  
1 µF  
0.1 µF  
VDD/2  
VOUT  
RL  
RN  
RG  
MCP628X  
CL  
RF  
VIN  
VL  
FIGURE 1-3:  
AC and DC Test Circuit for  
Most Inverting Gain Conditions.  
DS21811E-page 4  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
2.0  
TYPICAL PERFORMANCE CURVES  
Note:  
The graphs and tables provided following this note are a statistical summary based on a limited number of  
samples and are provided for informational purposes only. The performance characteristics listed herein  
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified  
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.  
14%  
12%  
10%  
8%  
30%  
25%  
20%  
15%  
10%  
5%  
832 Samples  
CM = VSS  
832 Samples  
CM = VSS  
TA = -40°C to +125°C  
V
V
6%  
4%  
2%  
0%  
0%  
-10 -8  
-6  
-4  
-2  
0
2
4
6
8
10  
Input Offset Voltage (mV)  
Input Offset Voltage Drift (µV/°C)  
FIGURE 2-1:  
Input Offset Voltage.  
FIGURE 2-4:  
Input Offset Voltage Drift.  
35%  
25%  
210 Samples  
A = +125°C  
210 Samples  
TA = +85°C  
T
30%  
25%  
20%  
15%  
10%  
5%  
20%  
15%  
10%  
5%  
0%  
0%  
0
10  
20  
30  
40  
50  
60  
70  
80  
90 100  
Input Bias Current (pA)  
Input Bias Current (pA)  
FIGURE 2-2:  
Input Bias Current at  
FIGURE 2-5:  
Input Bias Current at  
T = +85 °C.  
T = +125 °C.  
A
A
300  
300  
VDD = 5.5V  
VDD = 2.2V  
250  
200  
150  
100  
50  
250  
200  
150  
100  
50  
TA = +125°C  
TA = +125°C  
0
0
TA  
TA  
TA  
=
=
=
+85°C  
+25°C  
-40°C  
TA  
TA  
TA  
=
=
=
+85°C  
+25°C  
-40°C  
-50  
-100  
-50  
-100  
-0.5  
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
Common Mode Input Voltage (V)  
Common Mode Input Voltage (V)  
FIGURE 2-3:  
Input Offset Voltage vs.  
FIGURE 2-6:  
Input Offset Voltage vs.  
Common Mode Input Voltage at V = 2.2V.  
Common Mode Input Voltage at V = 5.5V.  
DD  
DD  
© 2008 Microchip Technology Inc.  
DS21811E-page 5  
MCP6281/1R/2/3/4/5  
TYPICAL PERFORMANCE CURVES (CONTINUED)  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.  
300  
10,000  
VCM = VSS  
Representative Part  
VCM = VDD  
VDD = 5.5V  
250  
200  
150  
100  
50  
1,000  
100  
10  
Input Bias Current  
Input Offset Current  
0
VDD = 5.5V  
VDD = 2.2V  
-50  
-100  
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Output Voltage (V)  
25 35 45 55 65 75 85 95 105 115 125  
Ambient Temperature (°C)  
FIGURE 2-7:  
Input Offset Voltage vs.  
FIGURE 2-10:  
Input Bias, Input Offset  
Output Voltage.  
Currents vs. Ambient Temperature.  
120  
110  
110  
PSRR-  
100  
CMRR  
90  
80  
70  
60  
50  
40  
30  
PSRR+  
CMRR  
100  
90  
PSRR  
VCM = VSS  
80  
70  
60  
20 1.E+00  
1.E+01  
1.E+02  
1.E+03  
1.E+04  
1.E+05  
1.E+06  
-50  
-25  
0
25  
50  
75  
100  
125  
1
10  
100  
1k  
10k  
100k  
1M  
Frequency (Hz)  
Ambient Temperature (°C)  
FIGURE 2-8:  
CMRR, PSRR vs.  
FIGURE 2-11:  
CMRR, PSRR vs. Ambient  
Frequency.  
Temperature.  
55  
45  
35  
25  
15  
5
2.5  
TA = +125°C  
DD = 5.5V  
V
2.0  
1.5  
Input Bias Current  
Input Offset Current  
Input Bias Current  
Input Offset Current  
1.0  
0.5  
0.0  
-5  
TA = +85°C  
VDD = 5.5V  
-0.5  
-1.0  
-15  
-25  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Common Mode Input Voltage (V)  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Common Mode Input Voltage (V)  
FIGURE 2-9:  
Input Bias, Offset Currents  
FIGURE 2-12:  
Input Bias, Offset Currents  
vs. Common Mode Input Voltage at T = +85°C.  
vs. Common Mode Input Voltage at T = +125°C.  
A
A
DS21811E-page 6  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
TYPICAL PERFORMANCE CURVES (CONTINUED)  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.  
600  
1000  
500  
400  
100  
300  
TA = +125°C  
200  
10  
TA = +85°C  
TA = +25°C  
TA = -40°C  
VOL - VSS  
100  
0
VDD - VOH  
1
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Power Supply Voltage (V)  
0.01  
0.1  
1
10  
Output Current Magnitude (mA)  
FIGURE 2-13:  
Quiescent Current vs.  
FIGURE 2-16:  
Output Voltage Headroom  
Power Supply Voltage.  
vs. Output Current Magnitude.  
120  
100  
80  
0
6
5
90  
85  
80  
75  
70  
65  
60  
VDD = 5.5V  
-30  
Gain  
VDD = 2.2V  
-60  
Gain Bandwidth Product  
4
3
2
1
0
60  
-90  
Phase  
VDD = 5.5V  
40  
20  
0
-120  
-150  
-180  
-210  
VDD = 2.2V  
Phase Margin  
-20  
-50  
-25  
0
25  
50  
75  
100  
125  
0.1  
1
10 100 1k 10k 100k 1M 10M 100M  
Ambient Temperature (°C)  
Frequency (Hz)  
FIGURE 2-14:  
Open-Loop Gain, Phase vs.  
FIGURE 2-17:  
Gain Bandwidth Product,  
Frequency.  
Phase Margin vs. Ambient Temperature.  
10  
4.5  
Falling Edge, VDD = 2.2V  
4.0  
VDD = 5.5V  
Falling Edge, VDD = 5.5V  
3.5  
3.0  
2.5  
2.0  
VDD = 2.2V  
1
1.5  
1.0  
0.5  
0.0  
Rising Edge, VDD = 5.5V  
Rising Edge, VDD = 2.2V  
0.1  
-50  
-25  
0
25  
50  
75  
100  
125  
1k  
10k  
100k  
1M  
10M  
Ambient Temperature (°C)  
Frequency (Hz)  
FIGURE 2-15:  
Maximum Output Voltage  
FIGURE 2-18:  
Slew Rate vs. Ambient  
Swing vs. Frequency.  
Temperature.  
© 2008 Microchip Technology Inc.  
DS21811E-page 7  
MCP6281/1R/2/3/4/5  
TYPICAL PERFORMANCE CURVES (CONTINUED)  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.  
1,000  
30  
25  
20  
15  
10  
5
f = 1 kHz  
VDD = 5.0V  
100  
0
10 1.E-01  
1.E+00  
1.E+01  
1.E+02  
1.E+03  
1.E+04  
1.E+05  
1.E+06  
0.1  
1
10  
100  
1k  
10k  
100k  
1M  
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0  
Common Mode Input Voltage (V)  
Frequency (Hz)  
FIGURE 2-19:  
Input Noise Voltage Density  
FIGURE 2-22:  
Input Noise Voltage Density  
vs. Frequency.  
vs. Common Mode Input Voltage at 1 kHz.  
35  
30  
25  
20  
15  
10  
5
140  
130  
120  
110  
100  
TA = +125°C  
TA  
TA  
TA  
=
=
=
+85°C  
+25°C  
-40°C  
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Power Supply Voltage (V)  
1
10  
100  
Frequency (kHz)  
FIGURE 2-20:  
Output Short Circuit Current  
FIGURE 2-23:  
Channel-to-Channel  
vs. Power Supply Voltage.  
Separation vs. Frequency (MCP6282 and  
MCP6284 only).  
1000  
500  
450  
400  
350  
300  
250  
200  
150  
100  
50  
VDD = 5.5V  
Op-Amp shuts off here  
900  
Op-Amp turns on here  
800  
Hysteresis  
700  
CS swept  
low to high  
600  
500  
400  
300  
200  
100  
0
Hysteresis  
CS swept  
high to low  
CS swept  
low to high  
VDD = 2.2V  
Op Amp toggles On/Off here  
0
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5  
Chip Select Voltage (V)  
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2  
Chip Select Voltage (V)  
FIGURE 2-21:  
Quiescent Current vs.  
FIGURE 2-24:  
Quiescent Current vs.  
Chip Select (CS) Voltage at V = 2.2V  
Chip Select (CS) Voltage at V = 5.5V  
DD  
DD  
(MCP6283 and MCP6285 only).  
(MCP6283 and MCP6285 only).  
DS21811E-page 8  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
TYPICAL PERFORMANCE CURVES (CONTINUED)  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0 0.E+00  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
0.0 0.E+00  
G = +1V/V  
VDD = 5.0V  
G = -1V/V  
VDD = 5.0V  
2.E-06  
4.E-06  
6.E-06  
8.E-06  
1.E-05  
1.E-05  
1.E-05  
2.E-05  
2.E-05  
2.E-05  
2.E-06  
4.E-06  
6.E-06  
8.E-06  
1.E-05  
1.E-05  
1.E-05  
2.E-05  
2.E-05  
2.E-05  
Time (2 µs/div)  
Time (2 µs/div)  
FIGURE 2-28:  
Pulse Response.  
Large-Signal, Inverting  
FIGURE 2-25:  
Pulse Response.  
Large-Signal, Non-inverting  
G = +1V/V  
G = -1V/V  
Time (500 ns/div)  
Time (500 ns/div)  
FIGURE 2-29:  
Pulse Response.  
Small-Signal, Inverting  
FIGURE 2-26:  
Pulse Response.  
Small-Signal, Non-inverting  
6.0  
5.5  
5.0  
4.5  
4.0  
3.5  
3.0  
2.5  
2.0  
1.5  
1.0  
0.5  
2.5  
2.0  
1.5  
1.0  
0.5  
VDD = 5.5V  
G = +1V/V  
VDD = 2.2V  
G = +1V/V  
VIN = VSS  
CS Voltage  
VIN = VSS  
CS Voltage  
VOUT  
VOUT  
Output On  
Output High-Z  
Output On  
Output High-Z  
0.0 0.E+00  
5.E-06  
1.E-05  
2.E-05  
2.E-05  
3.E-05  
3.E-05  
4.E-05  
4.E-05  
5.E-05  
5.E-05  
0.0 0.0E+00  
5.0E-06  
1.0E-05  
1.5E-05  
2.0E-05  
2.5E-05  
3.0E-05  
3.5E-05  
4.0E-05  
4.5E-05  
5.0E-05  
Time (5 µs/div)  
Time (5 µs/div)  
FIGURE 2-30:  
Amplifier Output Response Time at V = 5.5V  
(MCP6283 and MCP6285 only).  
Chip Select (CS) to  
FIGURE 2-27:  
Amplifier Output Response Time at V = 2.2V  
(MCP6283 and MCP6285 only).  
Chip Select (CS) to  
DD  
DD  
© 2008 Microchip Technology Inc.  
DS21811E-page 9  
MCP6281/1R/2/3/4/5  
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈ VDD/2,  
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.  
1.E-02  
10m  
1.E-03  
1m  
1.E- 4  
100µ  
6
5
VDD = 5.0V  
G = +2 V/V  
1.E1-05µ  
4
VOUT  
1.E-06  
1µ  
VIN  
3
100n  
1.E- 7  
10n  
1.E- 8  
2
+125°C  
+85°C  
+25°C  
-40°C  
1n  
1.E-09  
100p  
1.E-10  
10p  
1.E-11  
1p  
1.E-12  
1
0
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0  
Input Voltage (V)  
-15  
-14  
-13  
-12  
-11  
-10  
-9  
-8  
-7  
-6  
-5  
-1  
Time (1 ms/div)  
FIGURE 2-31:  
Measured Input Current vs.  
FIGURE 2-32:  
The MCP6281/1R/2/3/4/5  
Input Voltage (below V ).  
Show No Phase Reversal.  
SS  
DS21811E-page 10  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
3.0  
PIN DESCRIPTIONS  
Descriptions of the pins are listed in Table 3-1 (single op amps) and Table 3-2 (dual and quad op amps).  
TABLE 3-1:  
PIN FUNCTION TABLE FOR SINGLE OP AMPS  
MCP6281  
MCP6281R  
MCP6283  
Symbol  
Description  
PDIP, SOIC,  
MSOP  
PDIP, SOIC,  
SOT-23-5  
SOT-23-5  
SOT-23-6  
MSOP  
6
2
1
4
1
4
6
2
1
4
VOUT Analog Output  
VIN–  
VIN+  
VDD  
VSS  
CS  
Inverting Input  
3
3
3
3
3
Non-inverting Input  
Positive Power Supply  
Negative Power Supply  
Chip Select  
7
5
2
7
6
4
2
5
4
2
—
1,5,8  
—
—
—
—
8
5
1,5  
—
NC  
No Internal Connection  
TABLE 3-2:  
PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS  
MCP6282  
MCP6284  
MCP6285  
Symbol  
Description  
PDIP, SOIC, MSOP  
PDIP, SOIC, MSOP  
PDIP, SOIC, TSSOP  
1
2
1
2
—
2
VOUTA Analog Output (op amp A)  
VINA–  
+
Inverting Input (op amp A)  
Non-inverting Input (op amp A)  
Positive Power Supply  
3
3
3
VINA  
8
4
8
VDD  
5
5
—
6
VINB  
+
Non-inverting Input (op amp B)  
Inverting Input (op amp B)  
6
6
VINB  
–
7
7
7
VOUTB Analog Output (op amp B)  
VOUTC Analog Output (op amp C)  
—
—
—
4
8
—
—
—
4
9
VINC  
–
+
Inverting Input (op amp C)  
Non-inverting Input (op amp C)  
Negative Power Supply  
10  
11  
12  
13  
14  
—
VINC  
VSS  
—
—
—
—
—
—
—
1
VIND  
+
Non-inverting Input (op amp D)  
Inverting Input (op amp D)  
VIND  
–
VOUTD Analog Output (op amp D)  
VOUTA  
/
Analog Output (op amp A)/Non-  
inverting Input (op amp B)  
VINB  
+
—
—
5
CS  
Chip Select  
3.1  
Analog Outputs  
3.4  
Chip Select Digital Input (CS)  
The output pins are low-impedance voltage sources.  
This is a CMOS, Schmitt-triggered input that places the  
part into a low-power mode of operation.  
3.2  
Analog Inputs  
3.5  
Power Supply Pins  
The non-inverting and inverting inputs are high-  
impedance CMOS inputs with low bias currents.  
The positive power supply (VDD) is 2.2V to 6.0V higher  
than the negative power supply (VSS). For normal  
operation, the other pins are between VSS and VDD  
.
3.3  
MCP6285’s VOUTA/VINB+ Pin  
Typically, these parts are used in a single (positive)  
supply configuration. In this case, VSS is connected to  
ground and VDD is connected to the supply. VDD will  
need bypass capacitors.  
For the MCP6285 only, the output of op amp A is  
connected directly to the non-inverting input of  
op amp B; this is the VOUTA/VINB+ pin. This connection  
makes it possible to provide a Chip Select pin for duals  
in 8-pin packages.  
© 2008 Microchip Technology Inc.  
DS21811E-page 11  
MCP6281/1R/2/3/4/5  
V
DD, and dump any currents onto VDD. When  
4.0  
APPLICATION INFORMATION  
implemented as shown, resistors R1 and R2 also limit  
the current through D1 and D2.  
The MCP6281/1R/2/3/4/5 family of op amps is manu-  
factured using Microchip's state-of-the-art CMOS  
process. This family is specifically designed for low-  
cost, low-power and general purpose applications.  
The low supply voltage, low quiescent current and  
wide bandwidth makes the MCP6281/1R/2/3/4/5 ideal  
for battery-powered applications.  
VDD  
D1 D2  
V1  
R1  
4.1  
Rail-to-Rail Inputs  
MCP628X  
V2  
4.1.1  
PHASE REVERSAL  
R2  
The MCP6281/1R/2/3/4/5 op amp is designed to  
prevent phase reversal when the input pins exceed the  
supply voltages. Figure 2-32 shows the input voltage  
exceeding the supply voltage without any phase  
reversal.  
R3  
VSS – (minimum expected V1)  
R1 >  
2 mA  
VSS – (minimum expected V2)  
4.1.2  
INPUT VOLTAGE AND CURRENT  
LIMITS  
R2 >  
2 mA  
FIGURE 4-2:  
Inputs.  
Protecting the Analog  
The ESD protection on the inputs can be depicted as  
shown in Figure 4-1. This structure was chosen to  
protect the input transistors, and to minimize input bias  
current (IB). The input ESD diodes clamp the inputs  
when they try to go more than one diode drop below  
VSS. They also clamp any voltages that go too far  
above VDD; their breakdown voltage is high enough to  
allow normal operation, and low enough to bypass  
quick ESD events within the specified limits.  
It is also possible to connect the diodes to the left of  
resistors R1 and R2. In this case, current through the  
diodes D1 and D2 needs to be limited by some other  
mechanism. The resistors then serve as in-rush current  
limiters; the DC current into the input pins (VIN+ and  
VIN–) should be very small.  
A significant amount of current can flow out of the  
inputs when the common mode voltage (VCM) is below  
ground (VSS); see Figure 2-31. Applications that are  
high impedance may need to limit the usable voltage  
range.  
Bond  
VDD  
Pad  
4.1.3  
NORMAL OPERATION  
Bond  
Pad  
Bond  
Pad  
Input  
Stage  
VIN+  
VIN–  
The input stage of the MCP6281/1R/2/3/4/5 op amps  
use two differential CMOS input stages in parallel. One  
operates at low common mode input voltage (VCM),  
while the other operates at high VCM. WIth this  
topology, the device operates with VCM up to 0.3V  
Bond  
Pad  
VSS  
above VDD and 0.3V below VSS  
.
There is a transition in input behavior as VCM is  
changed. It occurs when VCM is near VDD – 1.2V (see  
Figure 2-3 and Figure 2-6). For the best distortion  
performance with non-inverting gains, avoid these  
regions of operation.  
FIGURE 4-1:  
Structures.  
Simplified Analog Input ESD  
In order to prevent damage and/or improper operation  
of these op amps, the circuit they are in must limit the  
currents and voltages at the VIN+ and VIN– pins (see  
Absolute Maximum Ratings † at the beginning of  
Section 1.0 “Electrical Characteristics”). Figure 4-2  
shows the recommended approach to protecting these  
inputs. The internal ESD diodes prevent the input pins  
(VIN+ and VIN–) from going too far below ground, and  
the resistors R1 and R2 limit the possible current drawn  
out of the input pins. Diodes D1 and D2 prevent the  
input pins (VIN+ and VIN–) from going too far above  
DS21811E-page 12  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
After selecting RISO for your circuit, double-check the  
resulting frequency response peaking and step  
response overshoot. Modify RISO's value until the  
response is reasonable. Bench evaluation and simula-  
tions with the MCP6281/1R/2/3/4/5 SPICE macro  
model are helpful.  
4.2  
Rail-to-Rail Output  
The output voltage range of the MCP6281/1R/2/3/4/5  
op amp is VDD – 15 mV (min.) and VSS + 15 mV (max.)  
when RL = 10 kΩ is connected to VDD/2 and  
VDD = 5.5V. Refer to Figure 2-16 for more information.  
4.3  
Capacitive Loads  
4.4  
MCP628X Chip Select (CS)  
Driving large capacitive loads can cause stability  
problems for voltage feedback op amps. As the load  
capacitance increases, the feedback loop’s phase  
margin decreases and the closed-loop bandwidth is  
reduced. This produces gain peaking in the frequency  
response, with overshoot and ringing in the step  
response. A unity-gain buffer (G = +1) is the most  
sensitive to capacitive loads, though all gains show the  
same general behavior.  
The MCP6283 and MCP6285 are single and dual op  
amps with Chip Select (CS), respectively. When CS is  
pulled high, the supply current drops to 0.7 µA (typical)  
and flows through the CS pin to VSS. When this hap-  
pens, the amplifier output is put into a high-impedance  
state. By pulling CS low, the amplifier is enabled. The  
CS pin has an internal 5 MΩ (typical) pull-down resistor  
connected to VSS, so it will go low if the CS pin is left  
floating. Figure 1-1 shows the output voltage and  
supply current response to a CS pulse.  
When driving large capacitive loads with these op  
amps (e.g., > 100 pF when G = +1), a small series  
resistor at the output (RISO in Figure 4-3) improves the  
feedback loop’s phase margin (stability) by making the  
output load resistive at higher frequencies. The  
bandwidth will generally be lower than the bandwidth  
with no capacitive load.  
4.5  
Cascaded Dual Op Amps  
(MCP6285)  
The MCP6285 is a dual op amp with Chip Select (CS).  
The Chip Select input is available on what would be the  
non-inverting input of a standard dual op amp (pin 5).  
This pin is available because the output of op amp A  
connects to the non-inverting input of op amp B, as  
shown in Figure 4-5. The Chip Select input, which can  
be connected to a microcontroller I/O line, puts the  
device in Low-power mode. Refer to Section 4.4  
“MCP628X Chip Select (CS)”.  
–
RISO  
MCP628X  
+
VOUT  
VIN  
CL  
VINB  
–
V
OUTA/VINB  
1
+
FIGURE 4-3:  
Output Resistor, R  
ISO  
6
stabilizes large capacitive loads.  
2
3
7
Figure 4-4 gives recommended RISO values for differ-  
ent capacitive loads and gains. The x-axis is the  
normalized load capacitance (CL/GN), where GN is the  
circuit's noise gain. For non-inverting gains, GN and the  
Signal Gain are equal. For inverting gains, GN is  
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).  
VINA  
VINA  
–
VOUTB  
B
A
+
MCP6285  
5
CS  
1,000  
FIGURE 4-5:  
Cascaded Gain Amplifier.  
The output of op amp A is loaded by the input imped-  
ance of op amp B, which is typically 1013Ω 6 pF, as  
||  
specified in the DC specification table (Refer to  
Section 4.3 “Capacitive Loads” for further details  
regarding capacitive loads).  
100  
GN = 1 V/V  
GN = 2 V/V  
The common mode input range of these op amps is  
specified in the data sheet as VSS – 300 mV and  
VDD + 300 mV. However, since the output of op amp A  
is limited to VOL and VOH (20 mV from the rails with a  
10 kΩ load), the non-inverting input range of op amp B  
is limited to the common mode input range of  
VSS + 20 mV and VDD – 20 mV.  
G
N t 4 V/V  
10  
10  
100  
1,000  
10,000  
Normalized Load Capacitance; CL / GN (pF)  
FIGURE 4-4:  
for Capacitive Loads.  
Recommended R  
Values  
ISO  
© 2008 Microchip Technology Inc.  
DS21811E-page 13  
MCP6281/1R/2/3/4/5  
4.6  
Supply Bypass  
VIN–  
VIN+  
VSS  
With this family of operational amplifiers, the power  
supply pin (VDD for single-supply) should have a local  
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm  
for good, high-frequency performance. It also needs a  
bulk capacitor (i.e., 1 µF or larger) within 100 mm to  
provide large, slow currents. This bulk capacitor can be  
shared with nearby analog parts.  
Guard Ring  
Example Guard Ring Layout  
4.7  
Unused Op Amps  
An unused op amp in a quad package (MCP6284)  
should be configured as shown in Figure 4-6. These  
circuits prevent the output from toggling and causing  
crosstalk. Circuits A sets the op amp at its minimum  
noise gain. The resistor divider produces any desired  
reference voltage within the output voltage range of the  
op amp; the op amp buffers that reference voltage.  
Circuit B uses the minimum number of components  
and operates as a comparator, but it may draw more  
current.  
FIGURE 4-7:  
for Inverting Gain.  
1. For Inverting Gain and Transimpedance  
Amplifiers (convert current to voltage, such as  
photo detectors):  
a. Connect the guard ring to the non-inverting  
input pin (VIN+). This biases the guard ring  
to the same reference voltage as the op  
amp (e.g., VDD/2 or ground).  
b. Connect the inverting pin (VIN–) to the input  
with a wire that does not touch the PCB  
surface.  
¼ MCP6284 (A)  
VDD  
¼ MCP6284 (B)  
VDD  
2. Non-inverting Gain and Unity-Gain Buffer:  
a. Connect the non-inverting pin (VIN+) to the  
input with a wire that does not touch the  
PCB surface.  
VDD  
R1  
R2  
VREF  
b. Connect the guard ring to the inverting input  
pin (VIN–). This biases the guard ring to the  
common mode input voltage.  
R2  
------------------  
⋅
VREF = VDD  
R1 + R2  
FIGURE 4-6:  
Unused Op Amps.  
4.8  
PCB Surface Leakage  
In applications where low input bias current is critical,  
Printed Circuit Board (PCB) surface-leakage effects  
need to be considered. Surface leakage is caused by  
humidity, dust or other contamination on the board.  
Under low humidity conditions, a typical resistance  
between nearby traces is 1012Ω. A 5V difference would  
cause 5 pA of current to flow, which is greater than the  
MCP6281/1R/2/3/4/5 family’s bias current at +25°C  
(1 pA, typical).  
The easiest way to reduce surface leakage is to use a  
guard ring around sensitive pins (or traces). The guard  
ring is biased at the same voltage as the sensitive pin.  
An example of this type of layout is shown in  
Figure 4-7.  
DS21811E-page 14  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
4.9.3  
CASCADED OP AMP  
APPLICATIONS  
4.9  
Application Circuits  
4.9.1  
SALLEN-KEY HIGH-PASS FILTER  
The MCP6285 provides the flexibility of Low-power  
mode for dual op amps in an 8-pin package. The  
MCP6285 eliminates the added cost and space in  
battery-powered applications by using two single op  
amps with Chip Select lines or a 10-pin device with one  
Chip Select line for both op amps. Since the two op  
amps are internally cascaded, this device cannot be  
used in circuits that require active or passive elements  
between the two op amps. However, there are several  
applications where this op amp configuration with  
Chip Select line becomes suitable. The circuits below  
show possible applications for this device.  
The MCP6281/1R/2/3/4/5 op amps can be used in  
active-filter applications. Figure 4-8 shows a second-  
order Sallen-Key high-pass filter with a gain of 1. The  
output bias voltage is set by the VDD/2 reference, which  
can be changed to any voltage within the output voltage  
range.  
R1  
VIN  
+
4.9.3.1  
Load Isolation  
C1  
C2  
R2  
VOUT  
MCP6281  
With the cascaded op amp configuration, op amp B can  
be used to isolate the load from op amp A. In applica-  
tions where op amp A is driving capacitive or low resis-  
tance loads in the feedback loop (such as an integrator  
circuit or filter circuit), the op amp may not have  
sufficient source current to drive the load. In this case,  
op amp B can be used as a buffer.  
–
VDD/2  
FIGURE 4-8:  
Sallen-Key High-Pass Filter.  
This filter, and others, can be designed using  
Microchip’s Design Aids; see Section 5.2 “FilterLab®  
Software” and Section 5.3 “Mindi™ Circuit  
Designer & Simulator”.  
VOUTB  
Load  
B
4.9.2  
INVERTING MILLER INTEGRATOR  
A
Analog integrators are used in filters, control loops and  
measurement circuits. Figure 4-9 shows the most  
common implementation, the inverting Miller integrator.  
The non-inverting input is at VDD/2 so that the op amp  
properly biases up. The switch (SW) is used to zero the  
output in some applications. Other applications use a  
feedback loop to keep the output within its linear range  
of operation.  
MCP6285  
CS  
FIGURE 4-10:  
Isolating the Load with a  
Buffer.  
4.9.3.2  
Cascaded Gain  
Figure 4-11 shows a cascaded gain circuit configura-  
tion with Chip Select. Op amps A and B are configured  
in a non-inverting amplifier configuration. In this  
configuration, it is important to note that the input offset  
voltage of op amp A is amplified by the gain of  
op amp A and B, as shown below:  
SW  
R
C
VOUT  
VIN  
+
MCP6281  
VOUT = VINGAGB + VOSAGAGB + VOSBGB  
VDD/2  
–
Where:  
VOUT  
VIN  
1
sRC  
=
GA  
GB  
=
=
=
=
op amp A gain  
op amp B gain  
FIGURE 4-9:  
Miller Integrator.  
VOSA  
VOSB  
op amp A input offset voltage  
op amp B input offset voltage  
Therefore, it is recommended to set most of the gain  
with op amp A and use op amp B with relatively small  
gain (e.g., a unity-gain buffer).  
© 2008 Microchip Technology Inc.  
DS21811E-page 15  
MCP6281/1R/2/3/4/5  
R2  
C2  
RF  
R4  
R3  
R2  
R1  
VOUT  
B
R1  
A
VIN  
VOUT  
B
MCP6285  
A
C1  
VIN  
MCP6285  
CS  
||  
R1C1 = (R2 RF)C2  
CS  
FIGURE 4-13:  
Integrator with Chip Select.  
Buffered Non-inverting  
FIGURE 4-11:  
Configuration.  
Cascaded Gain Circuit  
4.9.3.5 Inverting Integrator with Active  
4.9.3.3  
Difference Amplifier  
Compensation and Chip Select  
Figure 4-12 shows op amp A configured as a difference  
amplifier with Chip Select. In this configuration, it is  
recommended to use well-matched resistors (e.g.,  
0.1%) to increase the Common Mode Rejection Ratio  
(CMRR). Op amp B can be used to provide additional  
gain and isolate the load from the difference amplifier.  
Figure 4-14 uses an active compensator (op amp B) to  
compensate for the non-ideal op amp characteristics  
introduced at higher frequencies. This circuit uses  
op amp B as a unity-gain buffer to isolate the integration  
capacitor C1 from op amp A and drives the capacitor  
with low-impedance source. Since both op amps are  
matched very well, they provide a higher quality  
integrator.  
R4  
R3  
B
R2  
R2  
R1  
A
VIN2  
R1  
C1  
VIN  
VOUT  
B
VIN1  
MCP6285  
R1  
VOUT  
A
CS  
MCP6285  
FIGURE 4-12:  
Difference Amplifier Circuit.  
CS  
Integrator Circuit with Active  
4.9.3.4 Buffered Non-inverting Integrator  
Figure 4-13 shows a lossy non-inverting integrator that  
is buffered and has a Chip Select input. Op amp A is  
configured as a non-inverting integrator. In this config-  
uration, matching the impedance at each input is  
recommended. RF is used to provide a feedback loop  
at frequencies << 1/(2πR1C1) and makes this a lossy  
integrator (it has a finite gain at DC). Op amp B is used  
to isolate the load from the integrator.  
FIGURE 4-14:  
Compensation.  
4.9.3.6  
Second-Order MFB Low-Pass Filter  
with an Extra Pole-Zero Pair  
Figure 4-15 is a second-order multiple feedback low-  
pass filter with Chip Select. Use the FilterLab® software  
from Microchip to determine the R and C values for the  
op amp A’s second-order filter. Op amp B can be used  
to add a pole-zero pair using C3, R6, and R7.  
DS21811E-page 16  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
4.9.3.8  
Capacitorless Second-Order  
Low-Pass filter with Chip Select  
R6  
C3  
R1  
The low-pass filter shown in Figure 4-17 does not  
require external capacitors and uses only three exter-  
nal resistors; the op amp's GBWP sets the corner  
frequency. R1 and R2 are used to set the circuit gain  
and R3 is used to set the Q. To avoid gain peaking in  
the frequency response, Q needs to be low (lower  
values need to be selected for R3). Note that the ampli-  
fier bandwidth varies greatly over temperature and  
process. However, this configuration provides a low-  
cost solution for applications with high bandwidth  
requirements.  
C1  
A
R7  
B
R3  
C2  
R2  
VIN  
VOUT  
R5  
R4  
MCP6285  
CS  
FIGURE 4-15:  
Second-Order Multiple  
Feedback Low-Pass Filter with an Extra  
Pole-Zero Pair.  
R2  
R1  
VIN  
4.9.3.7  
Second-Order Sallen-Key Low-Pass  
Filter with an Extra Pole-Zero Pair  
R3  
Figure 4-16 is a second-order Sallen-Key low-pass  
filter with Chip Select. Use the FilterLab® software from  
Microchip to determine the R and C values for the op  
amp A’s second-order filter. Op amp B can be used to  
add a pole-zero pair using C3, R5 and R6.  
A
VOUT  
B
VREF  
MCP6285  
CS  
C3  
R2  
R1  
A
R5  
FIGURE 4-17:  
Capacitorless Second-Order  
Low-Pass Filter with Chip Select.  
R6  
VOUT  
B
R4  
R3  
VIN  
MCP6285  
C1  
C2  
CS  
FIGURE 4-16:  
Second-Order Sallen-Key  
Low-Pass Filter with an Extra Pole-Zero Pair and  
Chip Select.  
© 2008 Microchip Technology Inc.  
DS21811E-page 17  
MCP6281/1R/2/3/4/5  
5.5  
Analog Demonstration and  
Evaluation Boards  
5.0  
DESIGN AIDS  
Microchip provides the basic design tools needed for  
the MCP6281/1R/2/3/4/5 family of op amps.  
Microchip offers a broad spectrum of Analog Demon-  
stration and Evaluation Boards that are designed to  
help you achieve faster time to market. For a complete  
listing of these boards and their corresponding user’s  
guides and technical information, visit the Microchip  
web site at www.microchip.com/analogtools.  
5.1  
SPICE Macro Model  
The latest SPICE macro model for the MCP6281/1R/2/  
3/4/5 op amps is available on the Microchip web site at  
www.microchip.com. This model is intended to be an  
initial design tool that works well in the op amp’s linear  
region of operation over the temperature range. See  
the model file for information on its capabilities.  
Two of our boards that are especially useful are:  
• P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP  
Evaluation Board  
• P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP  
Evaluation Board  
Bench testing is a very important part of any design and  
cannot be replaced with simulations. Also, simulation  
results using this macro model need to be validated by  
comparing them to the data sheet specifications and  
characteristic curves.  
5.6  
Application Notes  
The following Microchip Application Notes are avail-  
able on the Microchip web site at www.microchip. com/  
appnotes and are recommended as supplemental ref-  
erence resources.  
5.2  
FilterLab® Software  
Microchip’s FilterLab® software is an innovative  
software tool that simplifies analog active filter (using  
op amps) design. Available at no cost from the  
Microchip web site at www.microchip.com/filterlab, the  
FilterLab design tool provides full schematic diagrams  
of the filter circuit with component values. It also  
outputs the filter circuit in SPICE format, which can be  
used with the macro model to simulate actual filter  
performance.  
ADN003: “Select the Right Operational Amplifier for  
your Filtering Circuits”, DS21821  
AN722: “Operational Amplifier Topologies and DC  
Specifications”, DS00722  
AN723: “Operational Amplifier AC Specifications and  
Applications”, DS00723  
AN884: “Driving Capacitive Loads With Op Amps”,  
DS00884  
5.3  
Mindi™ Circuit Designer &  
Simulator  
AN990: “Analog Sensor Conditioning Circuits – An  
Overview”, DS00990  
Microchip’s Mindi™ Circuit Designer & Simulator aids  
in the design of various circuits useful for active filter,  
amplifier and power-management applications. It is a  
free online circuit designer & simulator available from  
the Microchip web site at www.microchip.com/mindi.  
This interactive circuit designer & simulator enables  
designers to quickly generate circuit diagrams, simu-  
late circuits. Circuits developed using the Mindi Circuit  
Designer & Simulator can be downloaded to a personal  
computer or workstation.  
These application notes and others are listed in the  
design guide:  
“Signal Chain Design Guide”, DS21825  
5.4  
MAPS (Microchip Advanced Part  
Selector)  
MAPS is a software tool that helps semiconductor  
professionals efficiently identify Microchip devices that  
fit a particular design requirement. Available at no cost  
from the Microchip web site at www.microchip.com/  
maps, the MAPS is an overall selection tool for  
Microchip’s product portfolio that includes Analog,  
Memory, MCUs and DSCs. Using this tool you can  
define a filter to sort features for a parametric search of  
devices and export side-by-side technical comparison  
reports. Helpful links are also provided for Data sheets,  
Purchase, and Sampling of Microchip parts.  
DS21811E-page 18  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
6.0  
6.1  
PACKAGING INFORMATION  
Package Marking Information  
Example:  
5-Lead SOT-23 (MCP6281 and MCP6281R)  
Device  
Code  
MCP6281  
CHNN  
EUNN  
XXNN  
CH25  
MCP6281R  
Note: Applies to 5-Lead SOT-23.  
Example:  
6-Lead SOT-23 (MCP6283)  
XXNN  
CL25  
8-Lead MSOP  
Example:  
XXXXXX  
YWWNNN  
6281E  
722256  
8-Lead PDIP (300 mil)  
Example:  
XXXXXXXX  
XXXXXNNN  
MCP6281  
MCP6281  
E/P 256  
0722  
e
3
E/P256  
OR  
YYWW  
0722  
Legend: XX...X Customer-specific information  
Y
YY  
Year code (last digit of calendar year)  
Year code (last 2 digits of calendar year)  
WW  
NNN  
Week code (week of January 1 is week ‘01’)  
Alphanumeric traceability code  
e
3
Pb-free JEDEC designator for Matte Tin (Sn)  
*
This package is Pb-free. The Pb-free JEDEC designator (  
can be found on the outer packaging for this package.  
)
e3  
Note: In the event the full Microchip part number cannot be marked on one line, it will  
be carried over to the next line, thus limiting the number of available  
characters for customer-specific information.  
© 2008 Microchip Technology Inc.  
DS21811E-page 19  
MCP6281/1R/2/3/4/5  
Package Marking Information (Continued)  
8-Lead SOIC (150 mil)  
Example:  
MCP6281E  
XXXXXXXX  
XXXXYYWW  
MCP6281  
E/SN0722  
e
3
SN 0722  
OR  
256  
NNN  
256  
14-Lead PDIP (300 mil) (MCP6284)  
Example:  
XXXXXXXXXXXXXX  
XXXXXXXXXXXXXX  
MCP6284-E/P  
0722256  
YYWWNNN  
MCP6284  
e
3
E/P  
OR  
0722256  
14-Lead SOIC (150 mil) (MCP6284)  
Example:  
XXXXXXXXXX  
XXXXXXXXXX  
MCP6284ESL  
0722256  
YYWWNNN  
MCP6284  
OR  
E/SL^  
e
3
0722256  
Example:  
14-Lead TSSOP (MCP6284)  
XXXXXX  
YYWW  
6284EST  
0437  
NNN  
256  
DS21811E-page 20  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
5-Lead Plastic Small Outline Transistor (OT) [SOT-23]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
b
N
E
E1  
3
2
1
e
e1  
D
A2  
c
A
φ
A1  
L
L1  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Lead Pitch  
N
e
5
0.95 BSC  
Outside Lead Pitch  
Overall Height  
e1  
A
1.90 BSC  
0.90  
0.89  
0.00  
2.20  
1.30  
2.70  
0.10  
0.35  
0°  
–
–
–
–
–
–
–
–
–
–
–
1.45  
1.30  
0.15  
3.20  
1.80  
3.10  
0.60  
0.80  
30°  
Molded Package Thickness  
Standoff  
A2  
A1  
E
Overall Width  
Molded Package Width  
Overall Length  
Foot Length  
E1  
D
L
Footprint  
L1  
φ
Foot Angle  
Lead Thickness  
Lead Width  
c
0.08  
0.20  
0.26  
0.51  
b
Notes:  
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.  
2. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
Microchip Technology Drawing C04-091B  
© 2008 Microchip Technology Inc.  
DS21811E-page 21  
MCP6281/1R/2/3/4/5  
6-Lead Plastic Small Outline Transistor (CH) [SOT-23]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
b
4
N
E
E1  
PIN 1 ID BY  
LASER MARK  
1
2
3
e
e1  
D
c
A
φ
A2  
L
A1  
L1  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
6
0.95 BSC  
Outside Lead Pitch  
Overall Height  
e1  
A
1.90 BSC  
0.90  
0.89  
0.00  
2.20  
1.30  
2.70  
0.10  
0.35  
0°  
–
–
–
–
–
–
–
–
–
–
–
1.45  
1.30  
0.15  
3.20  
1.80  
3.10  
0.60  
0.80  
30°  
Molded Package Thickness  
Standoff  
A2  
A1  
E
Overall Width  
Molded Package Width  
Overall Length  
Foot Length  
E1  
D
L
Footprint  
L1  
φ
Foot Angle  
Lead Thickness  
Lead Width  
c
0.08  
0.20  
0.26  
0.51  
b
Notes:  
1. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.127 mm per side.  
2. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
Microchip Technology Drawing C04-028B  
DS21811E-page 22  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
N
E
E1  
NOTE 1  
2
b
1
e
c
φ
A2  
A
L
L1  
A1  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
8
0.65 BSC  
Overall Height  
A
–
–
1.10  
0.95  
0.15  
Molded Package Thickness  
Standoff  
A2  
A1  
E
0.75  
0.00  
0.85  
–
4.90 BSC  
3.00 BSC  
3.00 BSC  
0.60  
Overall Width  
Molded Package Width  
Overall Length  
Foot Length  
E1  
D
L
0.40  
0.80  
Footprint  
L1  
φ
0.95 REF  
–
Foot Angle  
0°  
8°  
Lead Thickness  
Lead Width  
c
0.08  
0.22  
–
0.23  
0.40  
b
–
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.  
3. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-111B  
© 2008 Microchip Technology Inc.  
DS21811E-page 23  
MCP6281/1R/2/3/4/5  
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
N
NOTE 1  
E1  
3
1
2
D
E
A2  
A
L
A1  
c
e
eB  
b1  
b
Units  
INCHES  
Dimension Limits  
MIN  
NOM  
8
MAX  
Number of Pins  
Pitch  
N
e
.100 BSC  
–
Top to Seating Plane  
A
–
.210  
.195  
–
Molded Package Thickness  
Base to Seating Plane  
Shoulder to Shoulder Width  
Molded Package Width  
Overall Length  
A2  
A1  
E
.115  
.015  
.290  
.240  
.348  
.115  
.008  
.040  
.014  
–
.130  
–
.310  
.250  
.365  
.130  
.010  
.060  
.018  
–
.325  
.280  
.400  
.150  
.015  
.070  
.022  
.430  
E1  
D
Tip to Seating Plane  
Lead Thickness  
L
c
Upper Lead Width  
b1  
b
Lower Lead Width  
Overall Row Spacing §  
eB  
Notes:  
1. Pin 1 visual index feature may vary, but must be located with the hatched area.  
2. § Significant Characteristic.  
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.  
4. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
Microchip Technology Drawing C04-018B  
DS21811E-page 24  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
N
NOTE 1  
E1  
3
1
2
D
E
A2  
A
L
c
A1  
b1  
b
e
eB  
Units  
INCHES  
NOM  
14  
Dimension Limits  
MIN  
MAX  
Number of Pins  
Pitch  
N
e
.100 BSC  
–
Top to Seating Plane  
A
–
.210  
.195  
–
Molded Package Thickness  
Base to Seating Plane  
Shoulder to Shoulder Width  
Molded Package Width  
Overall Length  
A2  
A1  
E
.115  
.015  
.290  
.240  
.735  
.115  
.008  
.045  
.014  
–
.130  
–
.310  
.250  
.750  
.130  
.010  
.060  
.018  
–
.325  
.280  
.775  
.150  
.015  
.070  
.022  
.430  
E1  
D
Tip to Seating Plane  
Lead Thickness  
L
c
Upper Lead Width  
b1  
b
Lower Lead Width  
Overall Row Spacing §  
eB  
Notes:  
1. Pin 1 visual index feature may vary, but must be located with the hatched area.  
2. § Significant Characteristic.  
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.  
4. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
Microchip Technology Drawing C04-005B  
© 2008 Microchip Technology Inc.  
DS21811E-page 25  
MCP6281/1R/2/3/4/5  
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
e
N
E
E1  
NOTE 1  
1
2
3
α
h
b
h
c
φ
A2  
A
L
A1  
L1  
β
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
8
1.27 BSC  
Overall Height  
A
–
–
1.75  
–
Molded Package Thickness  
Standoff §  
A2  
A1  
E
1.25  
0.10  
–
–
0.25  
Overall Width  
6.00 BSC  
Molded Package Width  
Overall Length  
E1  
D
h
3.90 BSC  
4.90 BSC  
Chamfer (optional)  
Foot Length  
0.25  
0.40  
–
0.50  
1.27  
L
–
Footprint  
L1  
φ
1.04 REF  
Foot Angle  
0°  
0.17  
0.31  
5°  
–
–
–
–
–
8°  
Lead Thickness  
Lead Width  
c
0.25  
0.51  
15°  
b
Mold Draft Angle Top  
Mold Draft Angle Bottom  
α
β
5°  
15°  
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. § Significant Characteristic.  
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.  
4. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-057B  
DS21811E-page 26  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
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© 2008 Microchip Technology Inc.  
DS21811E-page 27  
MCP6281/1R/2/3/4/5  
14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
N
E
E1  
NOTE 1  
1
2
3
e
h
b
α
h
c
φ
A2  
A
L
A1  
β
L1  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
14  
1.27 BSC  
Overall Height  
A
–
–
1.75  
–
Molded Package Thickness  
Standoff §  
A2  
A1  
E
1.25  
0.10  
–
–
0.25  
Overall Width  
6.00 BSC  
Molded Package Width  
Overall Length  
E1  
D
h
3.90 BSC  
8.65 BSC  
Chamfer (optional)  
Foot Length  
0.25  
0.40  
–
0.50  
1.27  
L
–
Footprint  
L1  
φ
1.04 REF  
Foot Angle  
0°  
0.17  
0.31  
5°  
–
–
–
–
–
8°  
Lead Thickness  
Lead Width  
c
0.25  
0.51  
15°  
b
Mold Draft Angle Top  
Mold Draft Angle Bottom  
α
β
5°  
15°  
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. § Significant Characteristic.  
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.  
4. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-065B  
DS21811E-page 28  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]  
Note: For the most current package drawings, please see the Microchip Packaging Specification located at  
http://www.microchip.com/packaging  
D
N
E
E1  
NOTE 1  
1
2
e
b
c
φ
A2  
A
A1  
L
L1  
Units  
MILLIMETERS  
Dimension Limits  
MIN  
NOM  
MAX  
Number of Pins  
Pitch  
N
e
14  
0.65 BSC  
Overall Height  
Molded Package Thickness  
Standoff  
A
–
–
1.20  
1.05  
0.15  
A2  
A1  
E
0.80  
0.05  
1.00  
–
Overall Width  
Molded Package Width  
Molded Package Length  
Foot Length  
6.40 BSC  
E1  
D
4.30  
4.90  
0.45  
4.40  
4.50  
5.10  
0.75  
5.00  
L
0.60  
Footprint  
L1  
φ
1.00 REF  
Foot Angle  
0°  
–
–
–
8°  
Lead Thickness  
c
0.09  
0.20  
0.30  
Lead Width  
b
0.19  
Notes:  
1. Pin 1 visual index feature may vary, but must be located within the hatched area.  
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.  
3. Dimensioning and tolerancing per ASME Y14.5M.  
BSC: Basic Dimension. Theoretically exact value shown without tolerances.  
REF: Reference Dimension, usually without tolerance, for information purposes only.  
Microchip Technology Drawing C04-087B  
© 2008 Microchip Technology Inc.  
DS21811E-page 29  
MCP6281/1R/2/3/4/5  
NOTES:  
DS21811E-page 30  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
APPENDIX A: REVISION HISTORY  
Revision E (February 2008)  
The following is the list of modifications:  
1. Updated notes to Section 1.0 “Electrical Char-  
acteristics”.  
2. Increased absolute maximum voltage range of  
input pins. Increased maximum operating  
supply voltage (VDD).  
3. Added Section 1.1 “Test Circuits”.  
4. Added Figure 2-32.  
5. Updated Table 3-1 and Table 3-2 in Section 3.0  
“Pin Descriptions”.  
6. Added Section 4.1.1 “Phase Reversal”,  
Section 4.1.2 “Input Voltage and Current  
Limits”, and Section 4.1.3 “Normal Opera-  
tion”.  
7. Added Section 4.7 “Unused Op Amps”.  
8. Updated Section 5.0 “Design AIDS”.  
9. Updated package outline drawings in  
Section 6.0 “Packaging Information”.  
Revision D (December 2004)  
The following is the list of modifications:  
1. Added SOT-23-5 packages for the MCP6281  
and MCP6281R single op amps.  
2. Added SOT-23-6 package for the MCP6283  
single op amp.  
3. Added Section 3.0 “Pin Descriptions”.  
4. Corrected application circuits  
(Section 4.9 “Application Circuits”).  
5. Added SOT-23-5 and SOT-23-6 packages and  
corrected  
package  
marking  
information  
(Section 6.0 “Packaging Information”).  
6. Added Appendix A: Revision History.  
Revision C (June 2004)  
The following is the list of modifications:  
1. Undocumented changes.  
Revision B (October 2003)  
The following is the list of modifications:  
1. Undocumented changes.  
Revision A (June 2003)  
• Original data sheet release.  
© 2008 Microchip Technology Inc.  
DS21811E-page 31  
MCP6281/1R/2/3/4/5  
NOTES:  
DS21811E-page 32  
© 2008 Microchip Technology Inc.  
MCP6281/1R/2/3/4/5  
PRODUCT IDENTIFICATION SYSTEM  
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.  
Examples:  
PART NO.  
Device  
X
/XX  
–
a)  
b)  
c)  
d)  
MCP6281-E/SN:  
Extended Temperature,  
8LD SOIC package.  
Extended Temperature,  
8LD MSOP package.  
Extended Temperature,  
8LD PDIP package.  
Temperature  
Range  
Package  
MCP6281-E/MS:  
MCP6281-E/P:  
Device:  
MCP6281:  
MCP6281T:  
Single Op Amp  
Single Op Amp  
(Tape and Reel)  
(SOIC, MSOP, SOT-23-5)  
Single Op Amp  
MCP6281T-E/OT: Tape and Reel,  
Extended Temperature,  
5LD SOT-23 package.  
MCP6281RT-E/OT: Tape and Reel,  
e)  
MCP6281RT:  
Extended Temperature,  
5LD SOT-23 package.  
(Tape and Reel) (SOT-23-5)  
Dual Op Amp  
MCP6282:  
MCP6282T:  
Dual Op Amp  
a)  
b)  
c)  
d)  
MCP6282-E/SN:  
MCP6282-E/MS:  
MCP6282-E/P:  
Extended Temperature,  
8LD SOIC package.  
Extended Temperature,  
8LD MSOP package.  
Extended Temperature,  
8LD PDIP package.  
(Tape and Reel) (SOIC, MSOP)  
Single Op Amp with CS  
Single Op Amp with CS  
(Tape and Reel)  
(SOIC, MSOP, SOT-23-6)  
Quad Op Amp  
MCP6283:  
MCP6283T:  
MCP6284:  
MCP6284T:  
MCP6282T-E/SN: Tape and Reel,  
Extended Temperature,  
Quad Op Amp  
(Tape and Reel) (SOIC, TSSOP)  
Dual Op Amp with CS  
Dual Op Amp with CS  
(Tape and Reel) (SOIC, MSOP)  
8LD SOIC package.  
MCP6285:  
MCP6285T:  
a)  
b)  
c)  
d)  
MCP6283-E/SN:  
MCP6283-E/MS:  
MCP6283-E/P:  
Extended Temperature,  
8LD SOIC package.  
Extended Temperature,  
8LD MSOP package.  
Extended Temperature,  
8LD PDIP package.  
Temperature Range:  
Package:  
E
=
=
-40°C to +125°C  
MCP6283T-E/CH: Tape and Reel,  
Extended Temperature,  
CH  
Plastic Small Outline Transistor (SOT-23), 6-lead  
(MCP6283 only)  
6LD SOT-23 package.  
MS  
P
OT  
=
=
=
Plastic MSOP, 8-lead  
a)  
b)  
MCP6284-E/P:  
Extended Temperature,  
14LD PDIP package.  
Plastic DIP (300 mil body), 8-lead, 14-lead  
Plastic Small Outline Transistor (SOT-23), 5-lead  
(MCP6281, MCP6281R only)  
Plastic SOIC (3.90 mm body), 14-lead  
Plastic SOIC, (3.90 mm body), 8-lead  
Plastic TSSOP (4.4 mm body), 14-lead  
MCP6284T-E/SL: Tape and Reel,  
Extended Temperature,  
SL  
SN  
ST  
=
=
=
14LD SOIC package.  
Extended Temperature,  
14LD SOIC package.  
Extended Temperature,  
14LD TSSOP package.  
c)  
d)  
MCP6284-E/SL:  
MCP6284-E/ST:  
a)  
b)  
c)  
d)  
MCP6285-E/SN:  
MCP6285-E/MS:  
MCP6285-E/P:  
Extended Temperature,  
8LD SOIC package.  
Extended Temperature,  
8LD MSOP package.  
Extended Temperature,  
8LD PDIP package.  
MCP6285T-E/SN: Tape and Reel,  
Extended Temperature,  
8LD SOIC package.  
© 2008 Microchip Technology Inc.  
DS21811E-page 33  
MCP6281/1R/2/3/4/5  
NOTES:  
DS21811E-page 34  
© 2008 Microchip Technology Inc.  
Note the following details of the code protection feature on Microchip devices:  
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.  
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the  
intended manner and under normal conditions.  
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our  
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data  
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.  
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.  
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not  
mean that we are guaranteeing the product as “unbreakable.”  
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our  
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts  
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.  
Information contained in this publication regarding device  
applications and the like is provided only for your convenience  
and may be superseded by updates. It is your responsibility to  
ensure that your application meets with your specifications.  
MICROCHIP MAKES NO REPRESENTATIONS OR  
WARRANTIES OF ANY KIND WHETHER EXPRESS OR  
IMPLIED, WRITTEN OR ORAL, STATUTORY OR  
OTHERWISE, RELATED TO THE INFORMATION,  
INCLUDING BUT NOT LIMITED TO ITS CONDITION,  
QUALITY, PERFORMANCE, MERCHANTABILITY OR  
FITNESS FOR PURPOSE. Microchip disclaims all liability  
arising from this information and its use. Use of Microchip  
devices in life support and/or safety applications is entirely at  
the buyer’s risk, and the buyer agrees to defend, indemnify and  
hold harmless Microchip from any and all damages, claims,  
suits, or expenses resulting from such use. No licenses are  
conveyed, implicitly or otherwise, under any Microchip  
intellectual property rights.  
Trademarks  
The Microchip name and logo, the Microchip logo, Accuron,  
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,  
PICSTART, PRO MATE, rfPIC and SmartShunt are registered  
trademarks of Microchip Technology Incorporated in the  
U.S.A. and other countries.  
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,  
SEEVAL, SmartSensor and The Embedded Control Solutions  
Company are registered trademarks of Microchip Technology  
Incorporated in the U.S.A.  
Analog-for-the-Digital Age, Application Maestro, CodeGuard,  
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,  
ECONOMONITOR, FanSense, In-Circuit Serial  
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB  
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,  
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,  
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total  
Endurance, UNI/O, WiperLock and ZENA are trademarks of  
Microchip Technology Incorporated in the U.S.A. and other  
countries.  
SQTP is a service mark of Microchip Technology Incorporated  
in the U.S.A.  
All other trademarks mentioned herein are property of their  
respective companies.  
© 2008, Microchip Technology Incorporated, Printed in the  
U.S.A., All Rights Reserved.  
Printed on recycled paper.  
Microchip received ISO/TS-16949:2002 certification for its worldwide  
headquarters, design and wafer fabrication facilities in Chandler and  
Tempe, Arizona; Gresham, Oregon and design centers in California  
and India. The Company’s quality system processes and procedures  
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping  
devices, Serial EEPROMs, microperipherals, nonvolatile memory and  
analog products. In addition, Microchip’s quality system for the design  
and manufacture of development systems is ISO 9001:2000 certified.  
© 2008 Microchip Technology Inc.  
DS21811E-page 35  
WORLDWIDE SALES AND SERVICE  
AMERICAS  
ASIA/PACIFIC  
ASIA/PACIFIC  
EUROPE  
Corporate Office  
Asia Pacific Office  
Suites 3707-14, 37th Floor  
Tower 6, The Gateway  
Harbour City, Kowloon  
Hong Kong  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
India - Bangalore  
Tel: 91-80-4182-8400  
Fax: 91-80-4182-8422  
Austria - Wels  
Tel: 43-7242-2244-39  
Fax: 43-7242-2244-393  
2355 West Chandler Blvd.  
Chandler, AZ 85224-6199  
Tel: 480-792-7200  
Fax: 480-792-7277  
Technical Support:  
http://support.microchip.com  
Web Address:  
www.microchip.com  
Denmark - Copenhagen  
Tel: 45-4450-2828  
Fax: 45-4485-2829  
India - New Delhi  
Tel: 91-11-4160-8631  
Fax: 91-11-4160-8632  
France - Paris  
Tel: 33-1-69-53-63-20  
Fax: 33-1-69-30-90-79  
India - Pune  
Tel: 91-20-2566-1512  
Fax: 91-20-2566-1513  
Australia - Sydney  
Tel: 61-2-9868-6733  
Fax: 61-2-9868-6755  
Atlanta  
Duluth, GA  
Tel: 678-957-9614  
Fax: 678-957-1455  
Germany - Munich  
Tel: 49-89-627-144-0  
Fax: 49-89-627-144-44  
Japan - Yokohama  
Tel: 81-45-471- 6166  
Fax: 81-45-471-6122  
China - Beijing  
Tel: 86-10-8528-2100  
Fax: 86-10-8528-2104  
Italy - Milan  
Tel: 39-0331-742611  
Fax: 39-0331-466781  
Korea - Daegu  
Tel: 82-53-744-4301  
Fax: 82-53-744-4302  
Boston  
China - Chengdu  
Tel: 86-28-8665-5511  
Fax: 86-28-8665-7889  
Westborough, MA  
Tel: 774-760-0087  
Fax: 774-760-0088  
Netherlands - Drunen  
Tel: 31-416-690399  
Fax: 31-416-690340  
Korea - Seoul  
China - Hong Kong SAR  
Tel: 852-2401-1200  
Fax: 852-2401-3431  
Tel: 82-2-554-7200  
Fax: 82-2-558-5932 or  
82-2-558-5934  
Chicago  
Itasca, IL  
Tel: 630-285-0071  
Fax: 630-285-0075  
Spain - Madrid  
Tel: 34-91-708-08-90  
Fax: 34-91-708-08-91  
China - Nanjing  
Tel: 86-25-8473-2460  
Fax: 86-25-8473-2470  
Malaysia - Kuala Lumpur  
Tel: 60-3-6201-9857  
Fax: 60-3-6201-9859  
Dallas  
Addison, TX  
Tel: 972-818-7423  
Fax: 972-818-2924  
UK - Wokingham  
Tel: 44-118-921-5869  
Fax: 44-118-921-5820  
China - Qingdao  
Tel: 86-532-8502-7355  
Fax: 86-532-8502-7205  
Malaysia - Penang  
Tel: 60-4-227-8870  
Fax: 60-4-227-4068  
Detroit  
Farmington Hills, MI  
Tel: 248-538-2250  
Fax: 248-538-2260  
China - Shanghai  
Tel: 86-21-5407-5533  
Fax: 86-21-5407-5066  
Philippines - Manila  
Tel: 63-2-634-9065  
Fax: 63-2-634-9069  
Kokomo  
Kokomo, IN  
Tel: 765-864-8360  
Fax: 765-864-8387  
China - Shenyang  
Tel: 86-24-2334-2829  
Fax: 86-24-2334-2393  
Singapore  
Tel: 65-6334-8870  
Fax: 65-6334-8850  
China - Shenzhen  
Tel: 86-755-8203-2660  
Fax: 86-755-8203-1760  
Taiwan - Hsin Chu  
Tel: 886-3-572-9526  
Fax: 886-3-572-6459  
Los Angeles  
Mission Viejo, CA  
Tel: 949-462-9523  
Fax: 949-462-9608  
China - Wuhan  
Tel: 86-27-5980-5300  
Fax: 86-27-5980-5118  
Taiwan - Kaohsiung  
Tel: 886-7-536-4818  
Fax: 886-7-536-4803  
Santa Clara  
Santa Clara, CA  
Tel: 408-961-6444  
Fax: 408-961-6445  
China - Xiamen  
Tel: 86-592-2388138  
Fax: 86-592-2388130  
Taiwan - Taipei  
Tel: 886-2-2500-6610  
Fax: 886-2-2508-0102  
Toronto  
Mississauga, Ontario,  
Canada  
Tel: 905-673-0699  
Fax: 905-673-6509  
China - Xian  
Tel: 86-29-8833-7252  
Fax: 86-29-8833-7256  
Thailand - Bangkok  
Tel: 66-2-694-1351  
Fax: 66-2-694-1350  
China - Zhuhai  
Tel: 86-756-3210040  
Fax: 86-756-3210049  
01/02/08  
DS21811E-page 36  
© 2008 Microchip Technology Inc.  

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